From 070040c444cf0e16648b4c9b1c72f6623751402b Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Fri, 30 Jun 2023 11:29:39 +0800
Subject: [PATCH 01/13] feat(soc): added soc support for esp32p4, part3

---
 .../soc/esp32c6/include/soc/parl_io_struct.h  |    2 +-
 components/soc/esp32p4/adc_periph.c           |   21 +
 components/soc/esp32p4/gdma_periph.c          |   25 +
 components/soc/esp32p4/gpio_periph.c          |  105 +
 components/soc/esp32p4/i2c_periph.c           |   22 +
 components/soc/esp32p4/i2s_periph.c           |   34 +
 .../esp32p4/include/modem/modem_lpcon_reg.h   |  382 ++
 .../include/modem/modem_lpcon_struct.h        |  178 +
 .../esp32p4/include/modem/modem_syscon_reg.h  |  612 ++
 .../include/modem/modem_syscon_struct.h       |  205 +
 .../soc/esp32p4/include/modem/reg_base.h      |    9 +
 .../soc/esp32p4/include/soc/adc_channel.h     |   28 +
 .../soc/esp32p4/include/soc/apb_saradc_reg.h  |  884 +++
 .../esp32p4/include/soc/apb_saradc_struct.h   |  757 +++
 .../soc/esp32p4/include/soc/boot_mode.h       |   93 +
 components/soc/esp32p4/include/soc/clic_reg.h |  110 +
 .../soc/esp32p4/include/soc/clint_reg.h       |  163 +
 .../soc/esp32p4/include/soc/clk_tree_defs.h   |  426 ++
 .../soc/esp32p4/include/soc/clkout_channel.h  |    8 +
 .../soc/esp32p4/include/soc/dport_access.h    |  112 +
 .../soc/esp32p4/include/soc/dspi_mem_reg.h    | 2832 ++++++++
 .../soc/esp32p4/include/soc/efuse_reg.h       | 3088 +++++++++
 .../soc/esp32p4/include/soc/efuse_struct.h    | 1011 +++
 .../soc/esp32p4/include/soc/ext_mem_defs.h    |  152 +
 .../soc/esp32p4/include/soc/extmem_reg.h      |  871 +++
 .../soc/esp32p4/include/soc/extmem_struct.h   | 5747 +++++++++++++++++
 .../soc/esp32p4/include/soc/gdma_channel.h    |   17 +
 .../soc/esp32p4/include/soc/gpio_pins.h       |   19 +
 .../soc/esp32p4/include/soc/gpio_sd_reg.h     | 1455 +++++
 .../soc/esp32p4/include/soc/gpio_sd_struct.h  |  771 +++
 .../soc/esp32p4/include/soc/gpio_sig_map.h    |  489 ++
 .../esp32p4/include/soc/hardware_lock_reg.h   |   76 +
 .../include/soc/hardware_lock_struct.h        |   99 +
 components/soc/esp32p4/include/soc/hinf_reg.h |  647 ++
 .../soc/esp32p4/include/soc/hinf_struct.h     |  555 ++
 components/soc/esp32p4/include/soc/host_reg.h | 3883 +++++++++++
 .../soc/esp32p4/include/soc/host_struct.h     | 2738 ++++++++
 .../soc/esp32p4/include/soc/hp_apm_reg.h      | 1838 ++++++
 .../soc/esp32p4/include/soc/hp_apm_struct.h   | 1670 +++++
 .../soc/esp32p4/include/soc/hp_clkrst_reg.h   |  629 ++
 .../soc/esp32p4/include/soc/hwcrypto_reg.h    |  178 +
 .../soc/esp32p4/include/soc/i2c_ext_reg.h     | 1521 +++++
 .../soc/esp32p4/include/soc/i2c_ext_struct.h  | 1276 ++++
 .../esp32p4/include/soc/interrupt_core0_reg.h | 1094 ++++
 .../esp32p4/include/soc/interrupt_core1_reg.h | 1094 ++++
 .../include/soc/interrupt_matrix_reg.h        |  999 +++
 .../include/soc/interrupt_matrix_struct.h     | 1254 ++++
 .../soc/esp32p4/include/soc/interrupt_reg.h   |   12 +
 .../soc/esp32p4/include/soc/intpri_reg.h      |  574 ++
 .../soc/esp32p4/include/soc/intpri_struct.h   |  256 +
 .../soc/esp32p4/include/soc/io_mux_reg.h      |   60 +
 .../soc/esp32p4/include/soc/iomux_reg.h       | 5143 +++++++++++++++
 .../soc/esp32p4/include/soc/iomux_struct.h    | 3429 ++++++++++
 .../soc/esp32p4/include/soc/lcd_cam_reg.h     |  962 +++
 .../soc/esp32p4/include/soc/lcd_cam_struct.h  |  303 +
 .../soc/esp32p4/include/soc/lcdcam_struct.h   |    2 +-
 .../soc/esp32p4/include/soc/lp_aon_reg.h      |  418 ++
 .../soc/esp32p4/include/soc/lp_aon_struct.h   |  306 +
 .../soc/esp32p4/include/soc/lp_apm0_reg.h     |  506 ++
 .../soc/esp32p4/include/soc/lp_apm0_struct.h  |  499 ++
 .../soc/esp32p4/include/soc/lp_apm_reg.h      |  582 ++
 .../soc/esp32p4/include/soc/lp_apm_struct.h   |  583 ++
 .../soc/esp32p4/include/soc/lp_clkrst_reg.h   |  382 ++
 .../esp32p4/include/soc/lp_clkrst_struct.h    |  341 +
 .../soc/esp32p4/include/soc/lp_gpio_sig_map.h |   55 +
 .../esp32p4/include/soc/lp_i2c_ana_mst_reg.h  |  135 +
 .../include/soc/lp_i2c_ana_mst_struct.h       |  150 +
 .../soc/esp32p4/include/soc/lp_io_reg.h       | 1263 ++++
 .../soc/esp32p4/include/soc/lp_io_struct.h    |  362 ++
 .../soc/esp32p4/include/soc/lp_sys_reg.h      | 1349 ++++
 .../soc/esp32p4/include/soc/lp_sys_struct.h   | 1333 ++++
 .../soc/esp32p4/include/soc/lp_tee_reg.h      |   65 +
 .../soc/esp32p4/include/soc/lp_tee_struct.h   |   95 +
 .../soc/esp32p4/include/soc/lp_timer_reg.h    |  342 +
 .../soc/esp32p4/include/soc/lp_timer_struct.h |  363 ++
 .../soc/esp32p4/include/soc/lp_wdt_reg.h      |  517 ++
 .../soc/esp32p4/include/soc/lp_wdt_struct.h   |  180 +
 .../soc/esp32p4/include/soc/mem_monitor_reg.h |  166 +
 .../esp32p4/include/soc/mem_monitor_struct.h  |  328 +
 .../soc/esp32p4/include/soc/memprot_defs.h    |   91 +
 components/soc/esp32p4/include/soc/mmu.h      |   34 +
 .../soc/esp32p4/include/soc/otp_debug_reg.h   | 1600 +++++
 .../esp32p4/include/soc/otp_debug_struct.h    | 2137 ++++++
 components/soc/esp32p4/include/soc/pcr_reg.h  | 2065 ++++++
 .../soc/esp32p4/include/soc/periph_defs.h     |  223 +
 components/soc/esp32p4/include/soc/plic_reg.h |  631 ++
 .../soc/esp32p4/include/soc/pmu_icg_mapping.h |   68 +
 components/soc/esp32p4/include/soc/pwm_reg.h  | 4514 +++++++++++++
 .../soc/esp32p4/include/soc/pwm_struct.h      | 2166 +++++++
 components/soc/esp32p4/include/soc/reg_base.h |  229 +
 .../soc/esp32p4/include/soc/regi2c_bbpll.h    |  175 +
 .../soc/esp32p4/include/soc/regi2c_bias.h     |   22 +
 .../soc/esp32p4/include/soc/regi2c_brownout.h |   22 +
 .../soc/esp32p4/include/soc/regi2c_defs.h     |   37 +
 .../soc/esp32p4/include/soc/regi2c_dig_reg.h  |   64 +
 .../soc/esp32p4/include/soc/regi2c_lp_bias.h  |   55 +
 .../soc/esp32p4/include/soc/regi2c_saradc.h   |   79 +
 .../soc/esp32p4/include/soc/reset_reasons.h   |   55 +
 components/soc/esp32p4/include/soc/rtc.h      |  529 ++
 .../soc/esp32p4/include/soc/rtc_io_channel.h  |   32 +
 .../soc/esp32p4/include/soc/rtc_io_reg.h      |    8 +
 .../soc/esp32p4/include/soc/rtc_io_struct.h   |   19 +
 .../soc/esp32p4/include/soc/sdio_slave_pins.h |   14 +
 .../soc/esp32p4/include/soc/sdmmc_pins.h      |   34 +
 components/soc/esp32p4/include/soc/slc_reg.h  | 4301 ++++++++++++
 .../soc/esp32p4/include/soc/slc_struct.h      | 3253 ++++++++++
 components/soc/esp32p4/include/soc/soc.h      |  260 +
 .../soc/esp32p4/include/soc/soc_etm_source.h  |  532 ++
 components/soc/esp32p4/include/soc/soc_pins.h |   17 +
 .../soc/esp32p4/include/soc/spi_mem_reg.h     | 3448 ++++++++++
 .../soc/esp32p4/include/soc/spi_mem_struct.h  | 1139 ++++
 components/soc/esp32p4/include/soc/spi_pins.h |   26 +
 .../soc/esp32p4/include/soc/sys_clkrst_reg.h  | 1118 ++++
 .../soc/esp32p4/include/soc/system_reg.h      |    6 +
 .../soc/esp32p4/include/soc/systimer_reg.h    |  558 ++
 .../soc/esp32p4/include/soc/systimer_struct.h |  375 ++
 components/soc/esp32p4/include/soc/tee_reg.h  |  455 ++
 .../soc/esp32p4/include/soc/tee_struct.h      |  573 ++
 .../soc/esp32p4/include/soc/touch_reg.h       |  764 +++
 .../soc/esp32p4/include/soc/touch_struct.h    |  658 ++
 .../soc/esp32p4/include/soc/trace_reg.h       |  463 ++
 .../soc/esp32p4/include/soc/trace_struct.h    |  461 ++
 .../soc/esp32p4/include/soc/tsens_reg.h       |  220 +
 .../soc/esp32p4/include/soc/tsens_struct.h    |  232 +
 .../soc/esp32p4/include/soc/twai_struct.h     |  796 +++
 .../soc/esp32p4/include/soc/twaifd_reg.h      | 1795 +++++
 .../soc/esp32p4/include/soc/twaifd_struct.h   | 1548 +++++
 .../soc/esp32p4/include/soc/uart_channel.h    |   18 +
 .../soc/esp32p4/include/soc/uart_pins.h       |   36 +
 .../soc/esp32p4/include/soc/uart_struct.h     | 1271 ++++
 components/soc/esp32p4/include/soc/uhci_reg.h |  966 +++
 .../soc/esp32p4/include/soc/uhci_struct.h     |  843 +++
 .../soc/esp32p4/include/soc/usb_device_reg.h  | 1282 ++++
 .../esp32p4/include/soc/usb_device_struct.h   | 1044 +++
 .../esp32p4/include/soc/usb_serial_jtag_reg.h | 1282 ++++
 .../include/soc/usb_serial_jtag_struct.h      | 1044 +++
 .../soc/esp32p4/include/soc/usbwrap_reg.h     |  182 +
 .../soc/esp32p4/include/soc/usbwrap_struct.h  |  138 +
 components/soc/esp32p4/interrupts.c           |   87 +
 .../soc/esp32p4/ld/esp32p4.peripherals.ld     |   94 +
 components/soc/esp32p4/ledc_periph.c          |   17 +
 components/soc/esp32p4/mcpwm_periph.c         |   83 +
 components/soc/esp32p4/parlio_periph.c        |   66 +
 components/soc/esp32p4/pcnt_periph.c          |   67 +
 components/soc/esp32p4/rmt_periph.c           |   35 +
 components/soc/esp32p4/rtc_io_periph.c        |   41 +
 components/soc/esp32p4/sdio_slave_periph.c    |   20 +
 components/soc/esp32p4/sdm_periph.c           |   25 +
 components/soc/esp32p4/sdmmc_periph.c         |   63 +
 components/soc/esp32p4/spi_periph.c           |   53 +
 .../soc/esp32p4/temperature_sensor_periph.c   |   16 +
 components/soc/esp32p4/timer_periph.c         |   24 +
 components/soc/esp32p4/twai_periph.c          |   31 +
 components/soc/esp32p4/uart_periph.c          |   80 +
 components/soc/include/soc/rtc_cntl_periph.h  |    2 +-
 155 files changed, 108048 insertions(+), 3 deletions(-)
 create mode 100644 components/soc/esp32p4/adc_periph.c
 create mode 100644 components/soc/esp32p4/gdma_periph.c
 create mode 100644 components/soc/esp32p4/i2c_periph.c
 create mode 100644 components/soc/esp32p4/i2s_periph.c
 create mode 100644 components/soc/esp32p4/include/modem/modem_lpcon_reg.h
 create mode 100644 components/soc/esp32p4/include/modem/modem_lpcon_struct.h
 create mode 100644 components/soc/esp32p4/include/modem/modem_syscon_reg.h
 create mode 100644 components/soc/esp32p4/include/modem/modem_syscon_struct.h
 create mode 100644 components/soc/esp32p4/include/modem/reg_base.h
 create mode 100644 components/soc/esp32p4/include/soc/adc_channel.h
 create mode 100644 components/soc/esp32p4/include/soc/apb_saradc_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/apb_saradc_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/boot_mode.h
 create mode 100644 components/soc/esp32p4/include/soc/clic_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/clint_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/clk_tree_defs.h
 create mode 100644 components/soc/esp32p4/include/soc/clkout_channel.h
 create mode 100644 components/soc/esp32p4/include/soc/dport_access.h
 create mode 100644 components/soc/esp32p4/include/soc/dspi_mem_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/efuse_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/efuse_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/ext_mem_defs.h
 create mode 100644 components/soc/esp32p4/include/soc/extmem_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/extmem_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/gdma_channel.h
 create mode 100644 components/soc/esp32p4/include/soc/gpio_pins.h
 create mode 100644 components/soc/esp32p4/include/soc/gpio_sd_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/gpio_sd_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/gpio_sig_map.h
 create mode 100644 components/soc/esp32p4/include/soc/hardware_lock_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/hardware_lock_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/hinf_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/hinf_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/host_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/host_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/hp_apm_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/hp_apm_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/hp_clkrst_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/hwcrypto_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/i2c_ext_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/i2c_ext_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/interrupt_core0_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/interrupt_core1_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/interrupt_matrix_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/interrupt_matrix_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/interrupt_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/intpri_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/intpri_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/iomux_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/iomux_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lcd_cam_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lcd_cam_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_aon_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_aon_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_apm0_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_apm0_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_apm_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_apm_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_clkrst_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_clkrst_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_io_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_io_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_sys_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_sys_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_tee_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_tee_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_timer_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_timer_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_wdt_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/lp_wdt_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/mem_monitor_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/mem_monitor_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/memprot_defs.h
 create mode 100644 components/soc/esp32p4/include/soc/mmu.h
 create mode 100644 components/soc/esp32p4/include/soc/otp_debug_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/otp_debug_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/pcr_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/periph_defs.h
 create mode 100644 components/soc/esp32p4/include/soc/plic_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/pmu_icg_mapping.h
 create mode 100644 components/soc/esp32p4/include/soc/pwm_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/pwm_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/reg_base.h
 create mode 100644 components/soc/esp32p4/include/soc/regi2c_bbpll.h
 create mode 100644 components/soc/esp32p4/include/soc/regi2c_bias.h
 create mode 100644 components/soc/esp32p4/include/soc/regi2c_brownout.h
 create mode 100644 components/soc/esp32p4/include/soc/regi2c_defs.h
 create mode 100644 components/soc/esp32p4/include/soc/regi2c_dig_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/regi2c_lp_bias.h
 create mode 100644 components/soc/esp32p4/include/soc/regi2c_saradc.h
 create mode 100644 components/soc/esp32p4/include/soc/reset_reasons.h
 create mode 100644 components/soc/esp32p4/include/soc/rtc.h
 create mode 100644 components/soc/esp32p4/include/soc/rtc_io_channel.h
 create mode 100644 components/soc/esp32p4/include/soc/rtc_io_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/rtc_io_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/sdio_slave_pins.h
 create mode 100644 components/soc/esp32p4/include/soc/sdmmc_pins.h
 create mode 100644 components/soc/esp32p4/include/soc/slc_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/slc_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/soc.h
 create mode 100644 components/soc/esp32p4/include/soc/soc_etm_source.h
 create mode 100644 components/soc/esp32p4/include/soc/soc_pins.h
 create mode 100644 components/soc/esp32p4/include/soc/spi_mem_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/spi_mem_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/spi_pins.h
 create mode 100644 components/soc/esp32p4/include/soc/sys_clkrst_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/system_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/systimer_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/systimer_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/tee_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/tee_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/touch_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/touch_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/trace_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/trace_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/tsens_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/tsens_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/twai_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/twaifd_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/twaifd_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/uart_channel.h
 create mode 100644 components/soc/esp32p4/include/soc/uart_pins.h
 create mode 100644 components/soc/esp32p4/include/soc/uart_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/uhci_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/uhci_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/usb_device_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/usb_device_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/usbwrap_reg.h
 create mode 100644 components/soc/esp32p4/include/soc/usbwrap_struct.h
 create mode 100644 components/soc/esp32p4/ld/esp32p4.peripherals.ld
 create mode 100644 components/soc/esp32p4/ledc_periph.c
 create mode 100644 components/soc/esp32p4/mcpwm_periph.c
 create mode 100644 components/soc/esp32p4/parlio_periph.c
 create mode 100644 components/soc/esp32p4/pcnt_periph.c
 create mode 100644 components/soc/esp32p4/rmt_periph.c
 create mode 100644 components/soc/esp32p4/rtc_io_periph.c
 create mode 100644 components/soc/esp32p4/sdio_slave_periph.c
 create mode 100644 components/soc/esp32p4/sdm_periph.c
 create mode 100644 components/soc/esp32p4/sdmmc_periph.c
 create mode 100644 components/soc/esp32p4/spi_periph.c
 create mode 100644 components/soc/esp32p4/temperature_sensor_periph.c
 create mode 100644 components/soc/esp32p4/timer_periph.c
 create mode 100644 components/soc/esp32p4/twai_periph.c

diff --git a/components/soc/esp32c6/include/soc/parl_io_struct.h b/components/soc/esp32c6/include/soc/parl_io_struct.h
index 816a7de3ef..21b5f63495 100644
--- a/components/soc/esp32c6/include/soc/parl_io_struct.h
+++ b/components/soc/esp32c6/include/soc/parl_io_struct.h
@@ -14,7 +14,7 @@ extern "C" {
 /** Type of rx_cfg0 register
  *  Parallel RX module configuration register0.
  */
-typedef union {
+typedef volatile union {
     struct {
         /** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0;
          *  Write 0 to select eof generated manchnism by configured data byte length. Write 1
diff --git a/components/soc/esp32p4/adc_periph.c b/components/soc/esp32p4/adc_periph.c
new file mode 100644
index 0000000000..050fb96675
--- /dev/null
+++ b/components/soc/esp32p4/adc_periph.c
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/adc_periph.h"
+
+/* Store IO number corresponding to the ADC channel number. */
+const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
+    /* ADC1 */
+    {
+        ADC1_CHANNEL_0_GPIO_NUM,
+        ADC1_CHANNEL_1_GPIO_NUM,
+        ADC1_CHANNEL_2_GPIO_NUM,
+        ADC1_CHANNEL_3_GPIO_NUM,
+        ADC1_CHANNEL_4_GPIO_NUM,
+        ADC1_CHANNEL_5_GPIO_NUM,
+        ADC1_CHANNEL_6_GPIO_NUM,
+    },
+};
diff --git a/components/soc/esp32p4/gdma_periph.c b/components/soc/esp32p4/gdma_periph.c
new file mode 100644
index 0000000000..5ddc769de5
--- /dev/null
+++ b/components/soc/esp32p4/gdma_periph.c
@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gdma_periph.h"
+
+const gdma_signal_conn_t gdma_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_GDMA_MODULE,
+            .pairs = {
+                [0]  = {
+                    .rx_irq_id = ETS_DMA2D_IN_CH0_INTR_SOURCE,
+                    .tx_irq_id = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
+                },
+                [1]  = {
+                    .rx_irq_id = ETS_DMA2D_IN_CH1_INTR_SOURCE,
+                    .tx_irq_id = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
+                },
+            }
+        }
+    }
+};
diff --git a/components/soc/esp32p4/gpio_periph.c b/components/soc/esp32p4/gpio_periph.c
index e69de29bb2..c8158d5e19 100644
--- a/components/soc/esp32p4/gpio_periph.c
+++ b/components/soc/esp32p4/gpio_periph.c
@@ -0,0 +1,105 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gpio_periph.h"
+
+const uint32_t GPIO_PIN_MUX_REG[] = {
+    IO_MUX_GPIO0_REG,
+    IO_MUX_GPIO1_REG,
+    IO_MUX_GPIO2_REG,
+    IO_MUX_GPIO3_REG,
+    IO_MUX_GPIO4_REG,
+    IO_MUX_GPIO5_REG,
+    IO_MUX_GPIO6_REG,
+    IO_MUX_GPIO7_REG,
+    IO_MUX_GPIO8_REG,
+    IO_MUX_GPIO9_REG,
+    IO_MUX_GPIO10_REG,
+    IO_MUX_GPIO11_REG,
+    IO_MUX_GPIO12_REG,
+    IO_MUX_GPIO13_REG,
+    IO_MUX_GPIO14_REG,
+    IO_MUX_GPIO15_REG,
+    IO_MUX_GPIO16_REG,
+    IO_MUX_GPIO17_REG,
+    IO_MUX_GPIO18_REG,
+    IO_MUX_GPIO19_REG,
+    IO_MUX_GPIO20_REG,
+    IO_MUX_GPIO21_REG,
+    IO_MUX_GPIO22_REG,
+    IO_MUX_GPIO23_REG,
+    IO_MUX_GPIO24_REG,
+    IO_MUX_GPIO25_REG,
+    IO_MUX_GPIO26_REG,
+    IO_MUX_GPIO27_REG,
+    IO_MUX_GPIO28_REG,
+    IO_MUX_GPIO29_REG,
+    IO_MUX_GPIO30_REG,
+    IO_MUX_GPIO31_REG,
+    IO_MUX_GPIO32_REG,
+    IO_MUX_GPIO33_REG,
+    IO_MUX_GPIO34_REG,
+    IO_MUX_GPIO35_REG,
+    IO_MUX_GPIO36_REG,
+    IO_MUX_GPIO37_REG,
+    IO_MUX_GPIO38_REG,
+    IO_MUX_GPIO39_REG,
+    IO_MUX_GPIO40_REG,
+    IO_MUX_GPIO41_REG,
+    IO_MUX_GPIO42_REG,
+    IO_MUX_GPIO43_REG,
+    IO_MUX_GPIO44_REG,
+    IO_MUX_GPIO45_REG,
+    IO_MUX_GPIO46_REG,
+    IO_MUX_GPIO47_REG,
+    IO_MUX_GPIO48_REG,
+    IO_MUX_GPIO49_REG,
+    IO_MUX_GPIO50_REG,
+    IO_MUX_GPIO51_REG,
+    IO_MUX_GPIO52_REG,
+    IO_MUX_GPIO53_REG,
+    IO_MUX_GPIO54_REG,
+    IO_MUX_GPIO55_REG,
+    IO_MUX_GPIO56_REG,
+};
+
+_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
+
+const uint32_t GPIO_HOLD_MASK[] = {
+    BIT(0),          //GPIO0   // LP_AON_GPIO_HOLD0_REG
+    BIT(1),          //GPIO1
+    BIT(2),          //GPIO2
+    BIT(3),          //GPIO3
+    BIT(4),          //GPIO4
+    BIT(5),          //GPIO5
+    BIT(6),          //GPIO6
+    BIT(7),          //GPIO7
+    BIT(8),          //GPIO8
+    BIT(9),          //GPIO9
+    BIT(10),         //GPIO10
+    BIT(11),         //GPIO11
+    BIT(12),         //GPIO12
+    BIT(13),         //GPIO13
+    BIT(14),         //GPIO14
+    BIT(15),         //GPIO15
+    BIT(16),         //GPIO16
+    BIT(17),         //GPIO17
+    BIT(18),         //GPIO18
+    BIT(19),         //GPIO19
+    BIT(20),         //GPIO20
+    BIT(21),         //GPIO21
+    BIT(22),         //GPIO22
+    BIT(23),         //GPIO23
+    BIT(24),         //GPIO24
+    BIT(25),         //GPIO25
+    BIT(26),         //GPIO26
+    BIT(27),         //GPIO27
+    BIT(28),         //GPIO28
+    BIT(29),         //GPIO29
+    BIT(30),         //GPIO30
+};
+
+_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
diff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c
new file mode 100644
index 0000000000..dd08f58a60
--- /dev/null
+++ b/components/soc/esp32p4/i2c_periph.c
@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/i2c_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
+    {
+        .sda_out_sig = I2CEXT0_SDA_OUT_IDX,
+        .sda_in_sig = I2CEXT0_SDA_IN_IDX,
+        .scl_out_sig = I2CEXT0_SCL_OUT_IDX,
+        .scl_in_sig = I2CEXT0_SCL_IN_IDX,
+        .irq = ETS_I2C_EXT0_INTR_SOURCE,
+        .module = PERIPH_I2C0_MODULE,
+    },
+};
diff --git a/components/soc/esp32p4/i2s_periph.c b/components/soc/esp32p4/i2s_periph.c
new file mode 100644
index 0000000000..15a7ff4fff
--- /dev/null
+++ b/components/soc/esp32p4/i2s_periph.c
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/i2s_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
+    {
+        .mck_out_sig  = 0,
+
+        .m_tx_bck_sig = 0,
+        .m_rx_bck_sig = 0,
+        .m_tx_ws_sig  = 0,
+        .m_rx_ws_sig  = 0,
+
+        .s_tx_bck_sig = 0,
+        .s_rx_bck_sig = 0,
+        .s_tx_ws_sig  = 0,
+        .s_rx_ws_sig  = 0,
+
+        .data_out_sigs[0] = 0,
+        .data_out_sigs[1] = 0,
+        .data_in_sig  = 0,
+
+        .irq          = -1,
+        .module       = PERIPH_I2S1_MODULE,
+    }
+};
diff --git a/components/soc/esp32p4/include/modem/modem_lpcon_reg.h b/components/soc/esp32p4/include/modem/modem_lpcon_reg.h
new file mode 100644
index 0000000000..63889d3e68
--- /dev/null
+++ b/components/soc/esp32p4/include/modem/modem_lpcon_reg.h
@@ -0,0 +1,382 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "modem/reg_base.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
+/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_EN    (BIT(0))
+#define MODEM_LPCON_CLK_EN_M  (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
+#define MODEM_LPCON_CLK_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_EN_S  0
+/* MODEM_LPCON_CLK_DEBUG_ENA : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_DEBUG_ENA    (BIT(1))
+#define MODEM_LPCON_CLK_DEBUG_ENA_M  (MODEM_LPCON_CLK_DEBUG_ENA_V << MODEM_LPCON_CLK_DEBUG_ENA_S)
+#define MODEM_LPCON_CLK_DEBUG_ENA_V  0x00000001U
+#define MODEM_LPCON_CLK_DEBUG_ENA_S  1
+
+#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW    (BIT(0))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S  0
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST    (BIT(1))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S  1
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL    (BIT(2))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S  2
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K    (BIT(3))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S  3
+/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM    0x00000FFFU
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M  (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V  0x00000FFFU
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S  4
+
+#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
+/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW    (BIT(0))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S  0
+/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST    (BIT(1))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S  1
+/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL    (BIT(2))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M  (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S  2
+/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K    (BIT(3))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M  (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S  3
+/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM    0x00000FFFU
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M  (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V  0x00000FFFU
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S  4
+
+#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW    (BIT(0))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S  0
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST    (BIT(1))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S  1
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL    (BIT(2))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S  2
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K    (BIT(3))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S  3
+/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM    0x00000FFFU
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M  (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V  0x00000FFFU
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S  4
+
+#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
+/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_I2C_MST_SEL_160M    (BIT(0))
+#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M  (MODEM_LPCON_CLK_I2C_MST_SEL_160M_V << MODEM_LPCON_CLK_I2C_MST_SEL_160M_S)
+#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V  0x00000001U
+#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S  0
+
+#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
+/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_MODEM_32K_SEL    0x00000003U
+#define MODEM_LPCON_CLK_MODEM_32K_SEL_M  (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S)
+#define MODEM_LPCON_CLK_MODEM_32K_SEL_V  0x00000003U
+#define MODEM_LPCON_CLK_MODEM_32K_SEL_S  0
+
+#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
+/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_EN    (BIT(0))
+#define MODEM_LPCON_CLK_WIFIPWR_EN_M  (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S)
+#define MODEM_LPCON_CLK_WIFIPWR_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_EN_S  0
+/* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_EN    (BIT(1))
+#define MODEM_LPCON_CLK_COEX_EN_M  (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
+#define MODEM_LPCON_CLK_COEX_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_EN_S  1
+/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_I2C_MST_EN    (BIT(2))
+#define MODEM_LPCON_CLK_I2C_MST_EN_M  (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
+#define MODEM_LPCON_CLK_I2C_MST_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_I2C_MST_EN_S  2
+/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_TIMER_EN    (BIT(3))
+#define MODEM_LPCON_CLK_LP_TIMER_EN_M  (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S)
+#define MODEM_LPCON_CLK_LP_TIMER_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_EN_S  3
+
+#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
+/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_FO    (BIT(0))
+#define MODEM_LPCON_CLK_WIFIPWR_FO_M  (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S)
+#define MODEM_LPCON_CLK_WIFIPWR_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_FO_S  0
+/* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_FO    (BIT(1))
+#define MODEM_LPCON_CLK_COEX_FO_M  (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
+#define MODEM_LPCON_CLK_COEX_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_FO_S  1
+/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_I2C_MST_FO    (BIT(2))
+#define MODEM_LPCON_CLK_I2C_MST_FO_M  (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
+#define MODEM_LPCON_CLK_I2C_MST_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_I2C_MST_FO_S  2
+/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_TIMER_FO    (BIT(3))
+#define MODEM_LPCON_CLK_LP_TIMER_FO_M  (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S)
+#define MODEM_LPCON_CLK_LP_TIMER_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_FO_S  3
+/* MODEM_LPCON_CLK_BCMEM_FO : R/W; bitpos: [4]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_BCMEM_FO    (BIT(4))
+#define MODEM_LPCON_CLK_BCMEM_FO_M  (MODEM_LPCON_CLK_BCMEM_FO_V << MODEM_LPCON_CLK_BCMEM_FO_S)
+#define MODEM_LPCON_CLK_BCMEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_BCMEM_FO_S  4
+/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W; bitpos: [5]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO    (BIT(5))
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M  (MODEM_LPCON_CLK_I2C_MST_MEM_FO_V << MODEM_LPCON_CLK_I2C_MST_MEM_FO_S)
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S  5
+/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W; bitpos: [6]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO    (BIT(6))
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M  (MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V << MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S)
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S  6
+/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W; bitpos: [7]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_PBUS_MEM_FO    (BIT(7))
+#define MODEM_LPCON_CLK_PBUS_MEM_FO_M  (MODEM_LPCON_CLK_PBUS_MEM_FO_V << MODEM_LPCON_CLK_PBUS_MEM_FO_S)
+#define MODEM_LPCON_CLK_PBUS_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_PBUS_MEM_FO_S  7
+/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W; bitpos: [8]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_AGC_MEM_FO    (BIT(8))
+#define MODEM_LPCON_CLK_AGC_MEM_FO_M  (MODEM_LPCON_CLK_AGC_MEM_FO_V << MODEM_LPCON_CLK_AGC_MEM_FO_S)
+#define MODEM_LPCON_CLK_AGC_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_AGC_MEM_FO_S  8
+/* MODEM_LPCON_CLK_DC_MEM_FO : R/W; bitpos: [9]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_DC_MEM_FO    (BIT(9))
+#define MODEM_LPCON_CLK_DC_MEM_FO_M  (MODEM_LPCON_CLK_DC_MEM_FO_V << MODEM_LPCON_CLK_DC_MEM_FO_S)
+#define MODEM_LPCON_CLK_DC_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_DC_MEM_FO_S  9
+
+#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
+/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M  (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S  16
+/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_COEX_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_COEX_ST_MAP_M  (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S)
+#define MODEM_LPCON_CLK_COEX_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_COEX_ST_MAP_S  20
+/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M  (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S  24
+/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M  (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S)
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S  28
+
+#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
+/* MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_LPCON_RST_WIFIPWR    (BIT(0))
+#define MODEM_LPCON_RST_WIFIPWR_M  (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S)
+#define MODEM_LPCON_RST_WIFIPWR_V  0x00000001U
+#define MODEM_LPCON_RST_WIFIPWR_S  0
+/* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_RST_COEX    (BIT(1))
+#define MODEM_LPCON_RST_COEX_M  (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
+#define MODEM_LPCON_RST_COEX_V  0x00000001U
+#define MODEM_LPCON_RST_COEX_S  1
+/* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_LPCON_RST_I2C_MST    (BIT(2))
+#define MODEM_LPCON_RST_I2C_MST_M  (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
+#define MODEM_LPCON_RST_I2C_MST_V  0x00000001U
+#define MODEM_LPCON_RST_I2C_MST_S  2
+/* MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_LPCON_RST_LP_TIMER    (BIT(3))
+#define MODEM_LPCON_RST_LP_TIMER_M  (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S)
+#define MODEM_LPCON_RST_LP_TIMER_V  0x00000001U
+#define MODEM_LPCON_RST_LP_TIMER_S  3
+
+#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
+/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1; */
+/*description: */
+#define MODEM_LPCON_DC_MEM_FORCE_PU    (BIT(0))
+#define MODEM_LPCON_DC_MEM_FORCE_PU_M  (MODEM_LPCON_DC_MEM_FORCE_PU_V << MODEM_LPCON_DC_MEM_FORCE_PU_S)
+#define MODEM_LPCON_DC_MEM_FORCE_PU_V  0x00000001U
+#define MODEM_LPCON_DC_MEM_FORCE_PU_S  0
+/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_LPCON_DC_MEM_FORCE_PD    (BIT(1))
+#define MODEM_LPCON_DC_MEM_FORCE_PD_M  (MODEM_LPCON_DC_MEM_FORCE_PD_V << MODEM_LPCON_DC_MEM_FORCE_PD_S)
+#define MODEM_LPCON_DC_MEM_FORCE_PD_V  0x00000001U
+#define MODEM_LPCON_DC_MEM_FORCE_PD_S  1
+/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; */
+/*description: */
+#define MODEM_LPCON_AGC_MEM_FORCE_PU    (BIT(2))
+#define MODEM_LPCON_AGC_MEM_FORCE_PU_M  (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S)
+#define MODEM_LPCON_AGC_MEM_FORCE_PU_V  0x00000001U
+#define MODEM_LPCON_AGC_MEM_FORCE_PU_S  2
+/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_LPCON_AGC_MEM_FORCE_PD    (BIT(3))
+#define MODEM_LPCON_AGC_MEM_FORCE_PD_M  (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S)
+#define MODEM_LPCON_AGC_MEM_FORCE_PD_V  0x00000001U
+#define MODEM_LPCON_AGC_MEM_FORCE_PD_S  3
+/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; */
+/*description: */
+#define MODEM_LPCON_PBUS_MEM_FORCE_PU    (BIT(4))
+#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M  (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S)
+#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V  0x00000001U
+#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S  4
+/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; */
+/*description: */
+#define MODEM_LPCON_PBUS_MEM_FORCE_PD    (BIT(5))
+#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M  (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S)
+#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V  0x00000001U
+#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S  5
+/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W; bitpos: [6]; default: 0; */
+/*description: */
+#define MODEM_LPCON_BC_MEM_FORCE_PU    (BIT(6))
+#define MODEM_LPCON_BC_MEM_FORCE_PU_M  (MODEM_LPCON_BC_MEM_FORCE_PU_V << MODEM_LPCON_BC_MEM_FORCE_PU_S)
+#define MODEM_LPCON_BC_MEM_FORCE_PU_V  0x00000001U
+#define MODEM_LPCON_BC_MEM_FORCE_PU_S  6
+/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W; bitpos: [7]; default: 0; */
+/*description: */
+#define MODEM_LPCON_BC_MEM_FORCE_PD    (BIT(7))
+#define MODEM_LPCON_BC_MEM_FORCE_PD_M  (MODEM_LPCON_BC_MEM_FORCE_PD_V << MODEM_LPCON_BC_MEM_FORCE_PD_S)
+#define MODEM_LPCON_BC_MEM_FORCE_PD_V  0x00000001U
+#define MODEM_LPCON_BC_MEM_FORCE_PD_S  7
+/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0; */
+/*description: */
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU    (BIT(8))
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M  (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S)
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V  0x00000001U
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S  8
+/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0; */
+/*description: */
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD    (BIT(9))
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M  (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S)
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V  0x00000001U
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S  9
+/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU    (BIT(10))
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M  (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S)
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V  0x00000001U
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S  10
+/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0; */
+/*description: */
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD    (BIT(11))
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M  (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S)
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V  0x00000001U
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S  11
+/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0; */
+/*description: */
+#define MODEM_LPCON_MODEM_PWR_MEM_WP    0x00000007U
+#define MODEM_LPCON_MODEM_PWR_MEM_WP_M  (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S)
+#define MODEM_LPCON_MODEM_PWR_MEM_WP_V  0x00000007U
+#define MODEM_LPCON_MODEM_PWR_MEM_WP_S  12
+/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 4; */
+/*description: */
+#define MODEM_LPCON_MODEM_PWR_MEM_WA    0x00000007U
+#define MODEM_LPCON_MODEM_PWR_MEM_WA_M  (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S)
+#define MODEM_LPCON_MODEM_PWR_MEM_WA_V  0x00000007U
+#define MODEM_LPCON_MODEM_PWR_MEM_WA_S  15
+/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0; */
+/*description: */
+#define MODEM_LPCON_MODEM_PWR_MEM_RA    0x00000003U
+#define MODEM_LPCON_MODEM_PWR_MEM_RA_M  (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S)
+#define MODEM_LPCON_MODEM_PWR_MEM_RA_V  0x00000003U
+#define MODEM_LPCON_MODEM_PWR_MEM_RA_S  18
+
+#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x2c)
+/* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35676736; */
+/*description: */
+#define MODEM_LPCON_DATE    0x0FFFFFFFU
+#define MODEM_LPCON_DATE_M  (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
+#define MODEM_LPCON_DATE_V  0x0FFFFFFFU
+#define MODEM_LPCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/modem/modem_lpcon_struct.h b/components/soc/esp32p4/include/modem/modem_lpcon_struct.h
new file mode 100644
index 0000000000..f27074fcee
--- /dev/null
+++ b/components/soc/esp32p4/include/modem/modem_lpcon_struct.h
@@ -0,0 +1,178 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef union {
+    struct {
+        uint32_t clk_en:1;
+        uint32_t clk_debug_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} modem_lpcon_test_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_lp_timer_sel_osc_slow:1;
+        uint32_t clk_lp_timer_sel_osc_fast:1;
+        uint32_t clk_lp_timer_sel_xtal:1;
+        uint32_t clk_lp_timer_sel_xtal32k:1;
+        uint32_t clk_lp_timer_div_num:12;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} modem_lpcon_lp_timer_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_coex_lp_sel_osc_slow:1;
+        uint32_t clk_coex_lp_sel_osc_fast:1;
+        uint32_t clk_coex_lp_sel_xtal:1;
+        uint32_t clk_coex_lp_sel_xtal32k:1;
+        uint32_t clk_coex_lp_div_num:12;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} modem_lpcon_coex_lp_clk_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_wifipwr_lp_sel_osc_slow:1;
+        uint32_t clk_wifipwr_lp_sel_osc_fast:1;
+        uint32_t clk_wifipwr_lp_sel_xtal:1;
+        uint32_t clk_wifipwr_lp_sel_xtal32k:1;
+        uint32_t clk_wifipwr_lp_div_num:12;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} modem_lpcon_wifi_lp_clk_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_i2c_mst_sel_160m:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} modem_lpcon_i2c_mst_clk_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_modem_32k_sel:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} modem_lpcon_modem_32k_clk_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_wifipwr_en:1;
+        uint32_t clk_coex_en:1;
+        uint32_t clk_i2c_mst_en:1;
+        uint32_t clk_lp_timer_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} modem_lpcon_clk_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_wifipwr_fo:1;
+        uint32_t clk_coex_fo:1;
+        uint32_t clk_i2c_mst_fo:1;
+        uint32_t clk_lp_timer_fo:1;
+        uint32_t clk_bcmem_fo:1;
+        uint32_t clk_i2c_mst_mem_fo:1;
+        uint32_t clk_chan_freq_mem_fo:1;
+        uint32_t clk_pbus_mem_fo:1;
+        uint32_t clk_agc_mem_fo:1;
+        uint32_t clk_dc_mem_fo:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} modem_lpcon_clk_conf_force_on_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        uint32_t clk_wifipwr_st_map:4;
+        uint32_t clk_coex_st_map:4;
+        uint32_t clk_i2c_mst_st_map:4;
+        uint32_t clk_lp_apb_st_map:4;
+    };
+    uint32_t val;
+} modem_lpcon_clk_conf_power_st_reg_t;
+
+typedef union {
+    struct {
+        uint32_t rst_wifipwr:1;
+        uint32_t rst_coex:1;
+        uint32_t rst_i2c_mst:1;
+        uint32_t rst_lp_timer:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} modem_lpcon_rst_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t dc_mem_force_pu:1;
+        uint32_t dc_mem_force_pd:1;
+        uint32_t agc_mem_force_pu:1;
+        uint32_t agc_mem_force_pd:1;
+        uint32_t pbus_mem_force_pu:1;
+        uint32_t pbus_mem_force_pd:1;
+        uint32_t bc_mem_force_pu:1;
+        uint32_t bc_mem_force_pd:1;
+        uint32_t i2c_mst_mem_force_pu:1;
+        uint32_t i2c_mst_mem_force_pd:1;
+        uint32_t chan_freq_mem_force_pu:1;
+        uint32_t chan_freq_mem_force_pd:1;
+        uint32_t modem_pwr_mem_wp:3;
+        uint32_t modem_pwr_mem_wa:3;
+        uint32_t modem_pwr_mem_ra:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} modem_lpcon_mem_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} modem_lpcon_date_reg_t;
+
+
+typedef struct {
+    volatile modem_lpcon_test_conf_reg_t test_conf;
+    volatile modem_lpcon_lp_timer_conf_reg_t lp_timer_conf;
+    volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf;
+    volatile modem_lpcon_wifi_lp_clk_conf_reg_t wifi_lp_clk_conf;
+    volatile modem_lpcon_i2c_mst_clk_conf_reg_t i2c_mst_clk_conf;
+    volatile modem_lpcon_modem_32k_clk_conf_reg_t modem_32k_clk_conf;
+    volatile modem_lpcon_clk_conf_reg_t clk_conf;
+    volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on;
+    volatile modem_lpcon_clk_conf_power_st_reg_t clk_conf_power_st;
+    volatile modem_lpcon_rst_conf_reg_t rst_conf;
+    volatile modem_lpcon_mem_conf_reg_t mem_conf;
+    volatile modem_lpcon_date_reg_t date;
+} modem_lpcon_dev_t;
+
+extern modem_lpcon_dev_t MODEM_LPCON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(modem_lpcon_dev_t) == 0x30, "Invalid size of modem_lpcon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/modem/modem_syscon_reg.h b/components/soc/esp32p4/include/modem/modem_syscon_reg.h
new file mode 100644
index 0000000000..2feabbd036
--- /dev/null
+++ b/components/soc/esp32p4/include/modem/modem_syscon_reg.h
@@ -0,0 +1,612 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ *//*description: */
+#pragma once
+
+#include <stdint.h>
+#include "modem/reg_base.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
+/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_EN    (BIT(0))
+#define MODEM_SYSCON_CLK_EN_M  (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S)
+#define MODEM_SYSCON_CLK_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_EN_S  0
+
+#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
+/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 1; */
+/*description: */
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX    (BIT(21))
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M  (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S)
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V  0x00000001U
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S  21
+/* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_ETM_EN    (BIT(22))
+#define MODEM_SYSCON_CLK_ETM_EN_M  (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S)
+#define MODEM_SYSCON_CLK_ETM_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_ETM_EN_S  22
+/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_ZB_APB_EN    (BIT(23))
+#define MODEM_SYSCON_CLK_ZB_APB_EN_M  (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S)
+#define MODEM_SYSCON_CLK_ZB_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZB_APB_EN_S  23
+/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [24]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_ZB_MAC_EN    (BIT(24))
+#define MODEM_SYSCON_CLK_ZB_MAC_EN_M  (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S)
+#define MODEM_SYSCON_CLK_ZB_MAC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZB_MAC_EN_S  24
+/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN    (BIT(25))
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S  25
+/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN    (BIT(26))
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S  26
+/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN    (BIT(27))
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S  27
+/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN    (BIT(28))
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S  28
+/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN    (BIT(29))
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S  29
+/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN    (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M  (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S)
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S  30
+/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN    (BIT(31))
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M  (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S)
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S  31
+
+#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8)
+/* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_ETM_FO    (BIT(22))
+#define MODEM_SYSCON_CLK_ETM_FO_M  (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S)
+#define MODEM_SYSCON_CLK_ETM_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ETM_FO_S  22
+/* MODEM_SYSCON_CLK_ZB_APB_FO : R/W; bitpos: [23]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_ZB_APB_FO    (BIT(23))
+#define MODEM_SYSCON_CLK_ZB_APB_FO_M  (MODEM_SYSCON_CLK_ZB_APB_FO_V << MODEM_SYSCON_CLK_ZB_APB_FO_S)
+#define MODEM_SYSCON_CLK_ZB_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZB_APB_FO_S  23
+/* MODEM_SYSCON_CLK_ZB_MAC_FO : R/W; bitpos: [24]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_ZB_MAC_FO    (BIT(24))
+#define MODEM_SYSCON_CLK_ZB_MAC_FO_M  (MODEM_SYSCON_CLK_ZB_MAC_FO_V << MODEM_SYSCON_CLK_ZB_MAC_FO_S)
+#define MODEM_SYSCON_CLK_ZB_MAC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZB_MAC_FO_S  24
+/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO : R/W; bitpos: [25]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO    (BIT(25))
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S  25
+/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO : R/W; bitpos: [26]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO    (BIT(26))
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S  26
+/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO : R/W; bitpos: [27]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO    (BIT(27))
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S  27
+/* MODEM_SYSCON_CLK_MODEM_SEC_APB_FO : R/W; bitpos: [28]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO    (BIT(28))
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S  28
+/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO    (BIT(29))
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S  29
+/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO    (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M  (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S)
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S  30
+/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO    (BIT(31))
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M  (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S)
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S  31
+
+#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc)
+/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_ZB_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_ZB_ST_MAP_M  (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S)
+#define MODEM_SYSCON_CLK_ZB_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_ZB_ST_MAP_S  8
+/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_FE_ST_MAP_M  (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S)
+#define MODEM_SYSCON_CLK_FE_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_FE_ST_MAP_S  12
+/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_BT_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_BT_ST_MAP_M  (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S)
+#define MODEM_SYSCON_CLK_BT_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_BT_ST_MAP_S  16
+/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M  (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S)
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S  20
+/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M  (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S  24
+/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M  (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S  28
+
+#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
+/* MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_WIFIBB    (BIT(8))
+#define MODEM_SYSCON_RST_WIFIBB_M  (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S)
+#define MODEM_SYSCON_RST_WIFIBB_V  0x00000001U
+#define MODEM_SYSCON_RST_WIFIBB_S  8
+/* MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [10]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_WIFIMAC    (BIT(10))
+#define MODEM_SYSCON_RST_WIFIMAC_M  (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S)
+#define MODEM_SYSCON_RST_WIFIMAC_V  0x00000001U
+#define MODEM_SYSCON_RST_WIFIMAC_S  10
+/* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_FE    (BIT(14))
+#define MODEM_SYSCON_RST_FE_M  (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S)
+#define MODEM_SYSCON_RST_FE_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_S  14
+/* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_BTMAC_APB    (BIT(15))
+#define MODEM_SYSCON_RST_BTMAC_APB_M  (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S)
+#define MODEM_SYSCON_RST_BTMAC_APB_V  0x00000001U
+#define MODEM_SYSCON_RST_BTMAC_APB_S  15
+/* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_BTMAC    (BIT(16))
+#define MODEM_SYSCON_RST_BTMAC_M  (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S)
+#define MODEM_SYSCON_RST_BTMAC_V  0x00000001U
+#define MODEM_SYSCON_RST_BTMAC_S  16
+/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_BTBB_APB    (BIT(17))
+#define MODEM_SYSCON_RST_BTBB_APB_M  (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S)
+#define MODEM_SYSCON_RST_BTBB_APB_V  0x00000001U
+#define MODEM_SYSCON_RST_BTBB_APB_S  17
+/* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_BTBB    (BIT(18))
+#define MODEM_SYSCON_RST_BTBB_M  (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S)
+#define MODEM_SYSCON_RST_BTBB_V  0x00000001U
+#define MODEM_SYSCON_RST_BTBB_S  18
+/* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_ETM    (BIT(22))
+#define MODEM_SYSCON_RST_ETM_M  (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S)
+#define MODEM_SYSCON_RST_ETM_V  0x00000001U
+#define MODEM_SYSCON_RST_ETM_S  22
+/* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_ZBMAC    (BIT(24))
+#define MODEM_SYSCON_RST_ZBMAC_M  (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S)
+#define MODEM_SYSCON_RST_ZBMAC_V  0x00000001U
+#define MODEM_SYSCON_RST_ZBMAC_S  24
+/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_MODEM_ECB    (BIT(25))
+#define MODEM_SYSCON_RST_MODEM_ECB_M  (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S)
+#define MODEM_SYSCON_RST_MODEM_ECB_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_ECB_S  25
+/* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_MODEM_CCM    (BIT(26))
+#define MODEM_SYSCON_RST_MODEM_CCM_M  (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S)
+#define MODEM_SYSCON_RST_MODEM_CCM_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_CCM_S  26
+/* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_MODEM_BAH    (BIT(27))
+#define MODEM_SYSCON_RST_MODEM_BAH_M  (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S)
+#define MODEM_SYSCON_RST_MODEM_BAH_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_BAH_S  27
+/* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_MODEM_SEC    (BIT(29))
+#define MODEM_SYSCON_RST_MODEM_SEC_M  (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S)
+#define MODEM_SYSCON_RST_MODEM_SEC_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_SEC_S  29
+/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_BLE_TIMER    (BIT(30))
+#define MODEM_SYSCON_RST_BLE_TIMER_M  (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S)
+#define MODEM_SYSCON_RST_BLE_TIMER_V  0x00000001U
+#define MODEM_SYSCON_RST_BLE_TIMER_S  30
+/* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_RST_DATA_DUMP    (BIT(31))
+#define MODEM_SYSCON_RST_DATA_DUMP_M  (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S)
+#define MODEM_SYSCON_RST_DATA_DUMP_V  0x00000001U
+#define MODEM_SYSCON_RST_DATA_DUMP_S  31
+
+#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14)
+/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN    (BIT(0))
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S  0
+/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN    (BIT(1))
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S  1
+/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN    (BIT(2))
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S  2
+/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN    (BIT(3))
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S  3
+/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN    (BIT(4))
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S  4
+/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN    (BIT(5))
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S  5
+/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN    (BIT(6))
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S  6
+/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN    (BIT(7))
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S  7
+/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN    (BIT(8))
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S  8
+/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIMAC_EN    (BIT(9))
+#define MODEM_SYSCON_CLK_WIFIMAC_EN_M  (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S)
+#define MODEM_SYSCON_CLK_WIFIMAC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIMAC_EN_S  9
+/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFI_APB_EN    (BIT(10))
+#define MODEM_SYSCON_CLK_WIFI_APB_EN_M  (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S)
+#define MODEM_SYSCON_CLK_WIFI_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFI_APB_EN_S  10
+/* MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_20M_EN    (BIT(11))
+#define MODEM_SYSCON_CLK_FE_20M_EN_M  (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S)
+#define MODEM_SYSCON_CLK_FE_20M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_20M_EN_S  11
+/* MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_40M_EN    (BIT(12))
+#define MODEM_SYSCON_CLK_FE_40M_EN_M  (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S)
+#define MODEM_SYSCON_CLK_FE_40M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_40M_EN_S  12
+/* MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_80M_EN    (BIT(13))
+#define MODEM_SYSCON_CLK_FE_80M_EN_M  (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S)
+#define MODEM_SYSCON_CLK_FE_80M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_80M_EN_S  13
+/* MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_160M_EN    (BIT(14))
+#define MODEM_SYSCON_CLK_FE_160M_EN_M  (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S)
+#define MODEM_SYSCON_CLK_FE_160M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_160M_EN_S  14
+/* MODEM_SYSCON_CLK_FE_CAL_160M_EN : R/W; bitpos: [15]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_CAL_160M_EN    (BIT(15))
+#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_M  (MODEM_SYSCON_CLK_FE_CAL_160M_EN_V << MODEM_SYSCON_CLK_FE_CAL_160M_EN_S)
+#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_S  15
+/* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_APB_EN    (BIT(16))
+#define MODEM_SYSCON_CLK_FE_APB_EN_M  (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S)
+#define MODEM_SYSCON_CLK_FE_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_APB_EN_S  16
+/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_BT_APB_EN    (BIT(17))
+#define MODEM_SYSCON_CLK_BT_APB_EN_M  (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S)
+#define MODEM_SYSCON_CLK_BT_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_APB_EN_S  17
+/* MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_BT_EN    (BIT(18))
+#define MODEM_SYSCON_CLK_BT_EN_M  (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S)
+#define MODEM_SYSCON_CLK_BT_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_EN_S  18
+/* MODEM_SYSCON_CLK_WIFIBB_480M_EN : R/W; bitpos: [19]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_480M_EN    (BIT(19))
+#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_480M_EN_V << MODEM_SYSCON_CLK_WIFIBB_480M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_S  19
+/* MODEM_SYSCON_CLK_FE_480M_EN : R/W; bitpos: [20]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_480M_EN    (BIT(20))
+#define MODEM_SYSCON_CLK_FE_480M_EN_M  (MODEM_SYSCON_CLK_FE_480M_EN_V << MODEM_SYSCON_CLK_FE_480M_EN_S)
+#define MODEM_SYSCON_CLK_FE_480M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_480M_EN_S  20
+/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN : R/W; bitpos: [21]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN    (BIT(21))
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_M  (MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S)
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S  21
+/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN : R/W; bitpos: [22]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN    (BIT(22))
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_M  (MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S)
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S  22
+/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN : R/W; bitpos: [23]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN    (BIT(23))
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_M  (MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S)
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S  23
+
+#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x18)
+/* MODEM_SYSCON_CLK_WIFIBB_22M_FO : R/W; bitpos: [0]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO    (BIT(0))
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_22M_FO_V << MODEM_SYSCON_CLK_WIFIBB_22M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_S  0
+/* MODEM_SYSCON_CLK_WIFIBB_40M_FO : R/W; bitpos: [1]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO    (BIT(1))
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40M_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_S  1
+/* MODEM_SYSCON_CLK_WIFIBB_44M_FO : R/W; bitpos: [2]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO    (BIT(2))
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_44M_FO_V << MODEM_SYSCON_CLK_WIFIBB_44M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_S  2
+/* MODEM_SYSCON_CLK_WIFIBB_80M_FO : R/W; bitpos: [3]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO    (BIT(3))
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80M_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_S  3
+/* MODEM_SYSCON_CLK_WIFIBB_40X_FO : R/W; bitpos: [4]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_40X_FO    (BIT(4))
+#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40X_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_S  4
+/* MODEM_SYSCON_CLK_WIFIBB_80X_FO : R/W; bitpos: [5]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_80X_FO    (BIT(5))
+#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80X_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_S  5
+/* MODEM_SYSCON_CLK_WIFIBB_40X1_FO : R/W; bitpos: [6]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO    (BIT(6))
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S  6
+/* MODEM_SYSCON_CLK_WIFIBB_80X1_FO : R/W; bitpos: [7]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO    (BIT(7))
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S  7
+/* MODEM_SYSCON_CLK_WIFIBB_160X1_FO : R/W; bitpos: [8]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO    (BIT(8))
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S  8
+/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [9]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIMAC_FO    (BIT(9))
+#define MODEM_SYSCON_CLK_WIFIMAC_FO_M  (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S)
+#define MODEM_SYSCON_CLK_WIFIMAC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIMAC_FO_S  9
+/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [10]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFI_APB_FO    (BIT(10))
+#define MODEM_SYSCON_CLK_WIFI_APB_FO_M  (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S)
+#define MODEM_SYSCON_CLK_WIFI_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFI_APB_FO_S  10
+/* MODEM_SYSCON_CLK_FE_20M_FO : R/W; bitpos: [11]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_20M_FO    (BIT(11))
+#define MODEM_SYSCON_CLK_FE_20M_FO_M  (MODEM_SYSCON_CLK_FE_20M_FO_V << MODEM_SYSCON_CLK_FE_20M_FO_S)
+#define MODEM_SYSCON_CLK_FE_20M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_20M_FO_S  11
+/* MODEM_SYSCON_CLK_FE_40M_FO : R/W; bitpos: [12]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_40M_FO    (BIT(12))
+#define MODEM_SYSCON_CLK_FE_40M_FO_M  (MODEM_SYSCON_CLK_FE_40M_FO_V << MODEM_SYSCON_CLK_FE_40M_FO_S)
+#define MODEM_SYSCON_CLK_FE_40M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_40M_FO_S  12
+/* MODEM_SYSCON_CLK_FE_80M_FO : R/W; bitpos: [13]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_80M_FO    (BIT(13))
+#define MODEM_SYSCON_CLK_FE_80M_FO_M  (MODEM_SYSCON_CLK_FE_80M_FO_V << MODEM_SYSCON_CLK_FE_80M_FO_S)
+#define MODEM_SYSCON_CLK_FE_80M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_80M_FO_S  13
+/* MODEM_SYSCON_CLK_FE_160M_FO : R/W; bitpos: [14]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_160M_FO    (BIT(14))
+#define MODEM_SYSCON_CLK_FE_160M_FO_M  (MODEM_SYSCON_CLK_FE_160M_FO_V << MODEM_SYSCON_CLK_FE_160M_FO_S)
+#define MODEM_SYSCON_CLK_FE_160M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_160M_FO_S  14
+/* MODEM_SYSCON_CLK_FE_CAL_160M_FO : R/W; bitpos: [15]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_CAL_160M_FO    (BIT(15))
+#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_M  (MODEM_SYSCON_CLK_FE_CAL_160M_FO_V << MODEM_SYSCON_CLK_FE_CAL_160M_FO_S)
+#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_S  15
+/* MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [16]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_APB_FO    (BIT(16))
+#define MODEM_SYSCON_CLK_FE_APB_FO_M  (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S)
+#define MODEM_SYSCON_CLK_FE_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_APB_FO_S  16
+/* MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [17]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_BT_APB_FO    (BIT(17))
+#define MODEM_SYSCON_CLK_BT_APB_FO_M  (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S)
+#define MODEM_SYSCON_CLK_BT_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_APB_FO_S  17
+/* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_BT_FO    (BIT(18))
+#define MODEM_SYSCON_CLK_BT_FO_M  (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S)
+#define MODEM_SYSCON_CLK_BT_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_FO_S  18
+/* MODEM_SYSCON_CLK_WIFIBB_480M_FO : R/W; bitpos: [19]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_WIFIBB_480M_FO    (BIT(19))
+#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_480M_FO_V << MODEM_SYSCON_CLK_WIFIBB_480M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_S  19
+/* MODEM_SYSCON_CLK_FE_480M_FO : R/W; bitpos: [20]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_480M_FO    (BIT(20))
+#define MODEM_SYSCON_CLK_FE_480M_FO_M  (MODEM_SYSCON_CLK_FE_480M_FO_V << MODEM_SYSCON_CLK_FE_480M_FO_S)
+#define MODEM_SYSCON_CLK_FE_480M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_480M_FO_S  20
+/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO : R/W; bitpos: [21]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO    (BIT(21))
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_M  (MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S)
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S  21
+/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO : R/W; bitpos: [22]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO    (BIT(22))
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_M  (MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S)
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S  22
+/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO : R/W; bitpos: [23]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO    (BIT(23))
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_M  (MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S)
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S  23
+
+#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c)
+/* MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_WIFI_BB_CFG    0xFFFFFFFFU
+#define MODEM_SYSCON_WIFI_BB_CFG_M  (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S)
+#define MODEM_SYSCON_WIFI_BB_CFG_V  0xFFFFFFFFU
+#define MODEM_SYSCON_WIFI_BB_CFG_S  0
+
+#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20)
+/* MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_MODEM_MEM_WP    0x00000007U
+#define MODEM_SYSCON_MODEM_MEM_WP_M  (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S)
+#define MODEM_SYSCON_MODEM_MEM_WP_V  0x00000007U
+#define MODEM_SYSCON_MODEM_MEM_WP_S  0
+/* MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 4; */
+/*description: */
+#define MODEM_SYSCON_MODEM_MEM_WA    0x00000007U
+#define MODEM_SYSCON_MODEM_MEM_WA_M  (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S)
+#define MODEM_SYSCON_MODEM_MEM_WA_V  0x00000007U
+#define MODEM_SYSCON_MODEM_MEM_WA_S  3
+/* MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0; */
+/*description: */
+#define MODEM_SYSCON_MODEM_MEM_RA    0x00000003U
+#define MODEM_SYSCON_MODEM_MEM_RA_M  (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S)
+#define MODEM_SYSCON_MODEM_MEM_RA_V  0x00000003U
+#define MODEM_SYSCON_MODEM_MEM_RA_S  6
+
+#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24)
+/* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 35676928; */
+/*description: */
+#define MODEM_SYSCON_DATE    0x0FFFFFFFU
+#define MODEM_SYSCON_DATE_M  (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S)
+#define MODEM_SYSCON_DATE_V  0x0FFFFFFFU
+#define MODEM_SYSCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/modem/modem_syscon_struct.h b/components/soc/esp32p4/include/modem/modem_syscon_struct.h
new file mode 100644
index 0000000000..2635e741b9
--- /dev/null
+++ b/components/soc/esp32p4/include/modem/modem_syscon_struct.h
@@ -0,0 +1,205 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef union {
+    struct {
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} modem_syscon_test_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        uint32_t clk_data_dump_mux:1;
+        uint32_t clk_etm_en:1;
+        uint32_t clk_zb_apb_en:1;
+        uint32_t clk_zb_mac_en:1;
+        uint32_t clk_modem_sec_ecb_en:1;
+        uint32_t clk_modem_sec_ccm_en:1;
+        uint32_t clk_modem_sec_bah_en:1;
+        uint32_t clk_modem_sec_apb_en:1;
+        uint32_t clk_modem_sec_en:1;
+        uint32_t clk_ble_timer_en:1;
+        uint32_t clk_data_dump_en:1;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        uint32_t clk_etm_fo:1;
+        uint32_t clk_zb_apb_fo:1;
+        uint32_t clk_zb_mac_fo:1;
+        uint32_t clk_modem_sec_ecb_fo:1;
+        uint32_t clk_modem_sec_ccm_fo:1;
+        uint32_t clk_modem_sec_bah_fo:1;
+        uint32_t clk_modem_sec_apb_fo:1;
+        uint32_t clk_modem_sec_fo:1;
+        uint32_t clk_ble_timer_fo:1;
+        uint32_t clk_data_dump_fo:1;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf_force_on_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        uint32_t clk_zb_st_map:4;
+        uint32_t clk_fe_st_map:4;
+        uint32_t clk_bt_st_map:4;
+        uint32_t clk_wifi_st_map:4;
+        uint32_t clk_modem_peri_st_map:4;
+        uint32_t clk_modem_apb_st_map:4;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf_power_st_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        uint32_t rst_wifibb:1;
+        uint32_t reserved_9:1;
+        uint32_t rst_wifimac:1;
+        uint32_t reserved_11:3;
+        uint32_t rst_fe:1;
+        uint32_t rst_btmac_apb:1;
+        uint32_t rst_btmac:1;
+        uint32_t rst_btbb_apb:1;
+        uint32_t rst_btbb:1;
+        uint32_t reserved_19:3;
+        uint32_t rst_etm:1;
+        uint32_t reserved_23:1;
+        uint32_t rst_zbmac:1;
+        uint32_t rst_modem_ecb:1;
+        uint32_t rst_modem_ccm:1;
+        uint32_t rst_modem_bah:1;
+        uint32_t reserved_28:1;
+        uint32_t rst_modem_sec:1;
+        uint32_t rst_ble_timer:1;
+        uint32_t rst_data_dump:1;
+    };
+    uint32_t val;
+} modem_syscon_modem_rst_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_wifibb_22m_en:1;
+        uint32_t clk_wifibb_40m_en:1;
+        uint32_t clk_wifibb_44m_en:1;
+        uint32_t clk_wifibb_80m_en:1;
+        uint32_t clk_wifibb_40x_en:1;
+        uint32_t clk_wifibb_80x_en:1;
+        uint32_t clk_wifibb_40x1_en:1;
+        uint32_t clk_wifibb_80x1_en:1;
+        uint32_t clk_wifibb_160x1_en:1;
+        uint32_t clk_wifimac_en:1;
+        uint32_t clk_wifi_apb_en:1;
+        uint32_t clk_fe_20m_en:1;
+        uint32_t clk_fe_40m_en:1;
+        uint32_t clk_fe_80m_en:1;
+        uint32_t clk_fe_160m_en:1;
+        uint32_t clk_fe_cal_160m_en:1;
+        uint32_t clk_fe_apb_en:1;
+        uint32_t clk_bt_apb_en:1;
+        uint32_t clk_bt_en:1;
+        uint32_t clk_wifibb_480m_en:1;
+        uint32_t clk_fe_480m_en:1;
+        uint32_t clk_fe_anamode_40m_en:1;
+        uint32_t clk_fe_anamode_80m_en:1;
+        uint32_t clk_fe_anamode_160m_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t clk_wifibb_22m_fo:1;
+        uint32_t clk_wifibb_40m_fo:1;
+        uint32_t clk_wifibb_44m_fo:1;
+        uint32_t clk_wifibb_80m_fo:1;
+        uint32_t clk_wifibb_40x_fo:1;
+        uint32_t clk_wifibb_80x_fo:1;
+        uint32_t clk_wifibb_40x1_fo:1;
+        uint32_t clk_wifibb_80x1_fo:1;
+        uint32_t clk_wifibb_160x1_fo:1;
+        uint32_t clk_wifimac_fo:1;
+        uint32_t clk_wifi_apb_fo:1;
+        uint32_t clk_fe_20m_fo:1;
+        uint32_t clk_fe_40m_fo:1;
+        uint32_t clk_fe_80m_fo:1;
+        uint32_t clk_fe_160m_fo:1;
+        uint32_t clk_fe_cal_160m_fo:1;
+        uint32_t clk_fe_apb_fo:1;
+        uint32_t clk_bt_apb_fo:1;
+        uint32_t clk_bt_fo:1;
+        uint32_t clk_wifibb_480m_fo:1;
+        uint32_t clk_fe_480m_fo:1;
+        uint32_t clk_fe_anamode_40m_fo:1;
+        uint32_t clk_fe_anamode_80m_fo:1;
+        uint32_t clk_fe_anamode_160m_fo:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf1_force_on_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wifi_bb_cfg:32;
+    };
+    uint32_t val;
+} modem_syscon_wifi_bb_cfg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modem_mem_wp:3;
+        uint32_t modem_mem_wa:3;
+        uint32_t modem_mem_ra:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} modem_syscon_mem_conf_reg_t;
+
+typedef union {
+    struct {
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} modem_syscon_date_reg_t;
+
+
+typedef struct {
+    volatile modem_syscon_test_conf_reg_t test_conf;
+    volatile modem_syscon_clk_conf_reg_t clk_conf;
+    volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on;
+    volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st;
+    volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf;
+    volatile modem_syscon_clk_conf1_reg_t clk_conf1;
+    volatile modem_syscon_clk_conf1_force_on_reg_t clk_conf1_force_on;
+    volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
+    volatile modem_syscon_mem_conf_reg_t mem_conf;
+    volatile modem_syscon_date_reg_t date;
+} modem_syscon_dev_t;
+
+extern modem_syscon_dev_t MODEM_SYSCON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/modem/reg_base.h b/components/soc/esp32p4/include/modem/reg_base.h
new file mode 100644
index 0000000000..7a0254eac0
--- /dev/null
+++ b/components/soc/esp32p4/include/modem/reg_base.h
@@ -0,0 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#define DR_REG_MODEM_SYSCON_BASE  0x600A9800
+#define DR_REG_MODEM_LPCON_BASE   0x600AF000
diff --git a/components/soc/esp32p4/include/soc/adc_channel.h b/components/soc/esp32p4/include/soc/adc_channel.h
new file mode 100644
index 0000000000..dcdfb8633b
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/adc_channel.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define ADC1_GPIO0_CHANNEL      0
+#define ADC1_CHANNEL_0_GPIO_NUM 0
+
+#define ADC1_GPIO1_CHANNEL      1
+#define ADC1_CHANNEL_1_GPIO_NUM 1
+
+#define ADC1_GPIO2_CHANNEL      2
+#define ADC1_CHANNEL_2_GPIO_NUM 2
+
+#define ADC1_GPIO3_CHANNEL      3
+#define ADC1_CHANNEL_3_GPIO_NUM 3
+
+#define ADC1_GPIO4_CHANNEL      4
+#define ADC1_CHANNEL_4_GPIO_NUM 4
+
+#define ADC1_GPIO5_CHANNEL      5
+#define ADC1_CHANNEL_5_GPIO_NUM 5
+
+#define ADC1_GPIO6_CHANNEL      6
+#define ADC1_CHANNEL_6_GPIO_NUM 6
diff --git a/components/soc/esp32p4/include/soc/apb_saradc_reg.h b/components/soc/esp32p4/include/soc/apb_saradc_reg.h
new file mode 100644
index 0000000000..933120275b
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/apb_saradc_reg.h
@@ -0,0 +1,884 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** APB_SARADC_CTRL_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
+/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
+ *  select software enable saradc sample
+ */
+#define APB_SARADC_SARADC_START_FORCE    (BIT(0))
+#define APB_SARADC_SARADC_START_FORCE_M  (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
+#define APB_SARADC_SARADC_START_FORCE_V  0x00000001U
+#define APB_SARADC_SARADC_START_FORCE_S  0
+/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
+ *  software enable saradc sample
+ */
+#define APB_SARADC_SARADC_START    (BIT(1))
+#define APB_SARADC_SARADC_START_M  (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
+#define APB_SARADC_SARADC_START_V  0x00000001U
+#define APB_SARADC_SARADC_START_S  1
+/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
+ *  SAR clock gated
+ */
+#define APB_SARADC_SARADC_SAR_CLK_GATED    (BIT(6))
+#define APB_SARADC_SARADC_SAR_CLK_GATED_M  (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
+#define APB_SARADC_SARADC_SAR_CLK_GATED_V  0x00000001U
+#define APB_SARADC_SARADC_SAR_CLK_GATED_S  6
+/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
+ *  SAR clock divider
+ */
+#define APB_SARADC_SARADC_SAR_CLK_DIV    0x000000FFU
+#define APB_SARADC_SARADC_SAR_CLK_DIV_M  (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
+#define APB_SARADC_SARADC_SAR_CLK_DIV_V  0x000000FFU
+#define APB_SARADC_SARADC_SAR_CLK_DIV_S  7
+/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define APB_SARADC_SARADC_SAR_PATT_LEN    0x00000007U
+#define APB_SARADC_SARADC_SAR_PATT_LEN_M  (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
+#define APB_SARADC_SARADC_SAR_PATT_LEN_V  0x00000007U
+#define APB_SARADC_SARADC_SAR_PATT_LEN_S  15
+/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC1 CTRL
+ */
+#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR    (BIT(23))
+#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M  (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
+#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V  0x00000001U
+#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S  23
+/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
+ *  force option to xpd sar blocks
+ */
+#define APB_SARADC_SARADC_XPD_SAR_FORCE    0x00000003U
+#define APB_SARADC_SARADC_XPD_SAR_FORCE_M  (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
+#define APB_SARADC_SARADC_XPD_SAR_FORCE_V  0x00000003U
+#define APB_SARADC_SARADC_XPD_SAR_FORCE_S  27
+/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
+ *  enable saradc2 power detect driven func.
+ */
+#define APB_SARADC_SARADC2_PWDET_DRV    (BIT(29))
+#define APB_SARADC_SARADC2_PWDET_DRV_M  (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
+#define APB_SARADC_SARADC2_PWDET_DRV_V  0x00000001U
+#define APB_SARADC_SARADC2_PWDET_DRV_S  29
+/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
+ *  wait arbit signal stable after sar_done
+ */
+#define APB_SARADC_SARADC_WAIT_ARB_CYCLE    0x00000003U
+#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M  (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
+#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V  0x00000003U
+#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S  30
+
+/** APB_SARADC_CTRL2_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
+/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
+ *  enable max meas num
+ */
+#define APB_SARADC_SARADC_MEAS_NUM_LIMIT    (BIT(0))
+#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M  (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
+#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V  0x00000001U
+#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S  0
+/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
+ *  max conversion number
+ */
+#define APB_SARADC_SARADC_MAX_MEAS_NUM    0x000000FFU
+#define APB_SARADC_SARADC_MAX_MEAS_NUM_M  (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
+#define APB_SARADC_SARADC_MAX_MEAS_NUM_V  0x000000FFU
+#define APB_SARADC_SARADC_MAX_MEAS_NUM_S  1
+/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
+ *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+ */
+#define APB_SARADC_SARADC_SAR1_INV    (BIT(9))
+#define APB_SARADC_SARADC_SAR1_INV_M  (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
+#define APB_SARADC_SARADC_SAR1_INV_V  0x00000001U
+#define APB_SARADC_SARADC_SAR1_INV_S  9
+/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
+ *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+ */
+#define APB_SARADC_SARADC_SAR2_INV    (BIT(10))
+#define APB_SARADC_SARADC_SAR2_INV_M  (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
+#define APB_SARADC_SARADC_SAR2_INV_V  0x00000001U
+#define APB_SARADC_SARADC_SAR2_INV_S  10
+/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
+ *  to set saradc timer target
+ */
+#define APB_SARADC_SARADC_TIMER_TARGET    0x00000FFFU
+#define APB_SARADC_SARADC_TIMER_TARGET_M  (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
+#define APB_SARADC_SARADC_TIMER_TARGET_V  0x00000FFFU
+#define APB_SARADC_SARADC_TIMER_TARGET_S  12
+/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
+ *  to enable saradc timer trigger
+ */
+#define APB_SARADC_SARADC_TIMER_EN    (BIT(24))
+#define APB_SARADC_SARADC_TIMER_EN_M  (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
+#define APB_SARADC_SARADC_TIMER_EN_V  0x00000001U
+#define APB_SARADC_SARADC_TIMER_EN_S  24
+
+/** APB_SARADC_FILTER_CTRL1_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
+/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
+ *  Factor of saradc filter1
+ */
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR1    0x00000007U
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M  (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V  0x00000007U
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S  26
+/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
+ *  Factor of saradc filter0
+ */
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR0    0x00000007U
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M  (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V  0x00000007U
+#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S  29
+
+/** APB_SARADC_FSM_WAIT_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc)
+/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8;
+ *  saradc_xpd_wait
+ */
+#define APB_SARADC_SARADC_XPD_WAIT    0x000000FFU
+#define APB_SARADC_SARADC_XPD_WAIT_M  (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S)
+#define APB_SARADC_SARADC_XPD_WAIT_V  0x000000FFU
+#define APB_SARADC_SARADC_XPD_WAIT_S  0
+/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8;
+ *  saradc_rstb_wait
+ */
+#define APB_SARADC_SARADC_RSTB_WAIT    0x000000FFU
+#define APB_SARADC_SARADC_RSTB_WAIT_M  (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S)
+#define APB_SARADC_SARADC_RSTB_WAIT_V  0x000000FFU
+#define APB_SARADC_SARADC_RSTB_WAIT_S  8
+/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255;
+ *  saradc_standby_wait
+ */
+#define APB_SARADC_SARADC_STANDBY_WAIT    0x000000FFU
+#define APB_SARADC_SARADC_STANDBY_WAIT_M  (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S)
+#define APB_SARADC_SARADC_STANDBY_WAIT_V  0x000000FFU
+#define APB_SARADC_SARADC_STANDBY_WAIT_S  16
+
+/** APB_SARADC_SAR1_STATUS_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
+/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912;
+ *  saradc1 status about data and channel
+ */
+#define APB_SARADC_SARADC_SAR1_STATUS    0xFFFFFFFFU
+#define APB_SARADC_SARADC_SAR1_STATUS_M  (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S)
+#define APB_SARADC_SARADC_SAR1_STATUS_V  0xFFFFFFFFU
+#define APB_SARADC_SARADC_SAR1_STATUS_S  0
+
+/** APB_SARADC_SAR2_STATUS_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
+/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912;
+ *  saradc2 status about data and channel
+ */
+#define APB_SARADC_SARADC_SAR2_STATUS    0xFFFFFFFFU
+#define APB_SARADC_SARADC_SAR2_STATUS_M  (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S)
+#define APB_SARADC_SARADC_SAR2_STATUS_V  0xFFFFFFFFU
+#define APB_SARADC_SARADC_SAR2_STATUS_S  0
+
+/** APB_SARADC_SAR_PATT_TAB1_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
+/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
+ *  item 0 ~ 3 for pattern table 1 (each item one byte)
+ */
+#define APB_SARADC_SARADC_SAR_PATT_TAB1    0x00FFFFFFU
+#define APB_SARADC_SARADC_SAR_PATT_TAB1_M  (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
+#define APB_SARADC_SARADC_SAR_PATT_TAB1_V  0x00FFFFFFU
+#define APB_SARADC_SARADC_SAR_PATT_TAB1_S  0
+
+/** APB_SARADC_SAR_PATT_TAB2_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
+/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
+ *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+ */
+#define APB_SARADC_SARADC_SAR_PATT_TAB2    0x00FFFFFFU
+#define APB_SARADC_SARADC_SAR_PATT_TAB2_M  (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
+#define APB_SARADC_SARADC_SAR_PATT_TAB2_V  0x00FFFFFFU
+#define APB_SARADC_SARADC_SAR_PATT_TAB2_S  0
+
+/** APB_SARADC_ONETIME_SAMPLE_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
+/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
+ *  configure onetime atten
+ */
+#define APB_SARADC_SARADC_ONETIME_ATTEN    0x00000003U
+#define APB_SARADC_SARADC_ONETIME_ATTEN_M  (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
+#define APB_SARADC_SARADC_ONETIME_ATTEN_V  0x00000003U
+#define APB_SARADC_SARADC_ONETIME_ATTEN_S  23
+/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
+ *  configure onetime channel
+ */
+#define APB_SARADC_SARADC_ONETIME_CHANNEL    0x0000000FU
+#define APB_SARADC_SARADC_ONETIME_CHANNEL_M  (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
+#define APB_SARADC_SARADC_ONETIME_CHANNEL_V  0x0000000FU
+#define APB_SARADC_SARADC_ONETIME_CHANNEL_S  25
+/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
+ *  trigger adc onetime sample
+ */
+#define APB_SARADC_SARADC_ONETIME_START    (BIT(29))
+#define APB_SARADC_SARADC_ONETIME_START_M  (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
+#define APB_SARADC_SARADC_ONETIME_START_V  0x00000001U
+#define APB_SARADC_SARADC_ONETIME_START_S  29
+/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
+ *  enable adc2 onetime sample
+ */
+#define APB_SARADC_SARADC2_ONETIME_SAMPLE    (BIT(30))
+#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M  (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
+#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V  0x00000001U
+#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S  30
+/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
+ *  enable adc1 onetime sample
+ */
+#define APB_SARADC_SARADC1_ONETIME_SAMPLE    (BIT(31))
+#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M  (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
+#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V  0x00000001U
+#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S  31
+
+/** APB_SARADC_ARB_CTRL_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
+/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
+ *  adc2 arbiter force to enableapb controller
+ */
+#define APB_SARADC_ADC_ARB_APB_FORCE    (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_M  (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
+#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x00000001U
+#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
+/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
+ *  adc2 arbiter force to enable rtc controller
+ */
+#define APB_SARADC_ADC_ARB_RTC_FORCE    (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
+#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x00000001U
+#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
+/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
+ *  adc2 arbiter force to enable wifi controller
+ */
+#define APB_SARADC_ADC_ARB_WIFI_FORCE    (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x00000001U
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
+/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
+ *  adc2 arbiter force grant
+ */
+#define APB_SARADC_ADC_ARB_GRANT_FORCE    (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x00000001U
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
+/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
+ *  Set adc2 arbiterapb priority
+ */
+#define APB_SARADC_ADC_ARB_APB_PRIORITY    0x00000003U
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x00000003U
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
+/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
+ *  Set adc2 arbiter rtc priority
+ */
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY    0x00000003U
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x00000003U
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
+/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
+ *  Set adc2 arbiter wifi priority
+ */
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY    0x00000003U
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x00000003U
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
+/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
+ *  adc2 arbiter uses fixed priority
+ */
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY    (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x00000001U
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
+
+/** APB_SARADC_FILTER_CTRL0_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
+/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
+ *  configure filter1 to adc channel
+ */
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1    0x0000000FU
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M  (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V  0x0000000FU
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S  18
+/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
+ *  configure filter0 to adc channel
+ */
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0    0x0000000FU
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M  (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V  0x0000000FU
+#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S  22
+/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc1_filter
+ */
+#define APB_SARADC_APB_SARADC_FILTER_RESET    (BIT(31))
+#define APB_SARADC_APB_SARADC_FILTER_RESET_M  (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
+#define APB_SARADC_APB_SARADC_FILTER_RESET_V  0x00000001U
+#define APB_SARADC_APB_SARADC_FILTER_RESET_S  31
+
+/** APB_SARADC_SAR1DATA_STATUS_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
+/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
+ *  saradc1 data
+ */
+#define APB_SARADC_APB_SARADC1_DATA    0x0001FFFFU
+#define APB_SARADC_APB_SARADC1_DATA_M  (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
+#define APB_SARADC_APB_SARADC1_DATA_V  0x0001FFFFU
+#define APB_SARADC_APB_SARADC1_DATA_S  0
+
+/** APB_SARADC_SAR2DATA_STATUS_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
+/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
+ *  saradc2 data
+ */
+#define APB_SARADC_APB_SARADC2_DATA    0x0001FFFFU
+#define APB_SARADC_APB_SARADC2_DATA_M  (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
+#define APB_SARADC_APB_SARADC2_DATA_V  0x0001FFFFU
+#define APB_SARADC_APB_SARADC2_DATA_S  0
+
+/** APB_SARADC_THRES0_CTRL_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
+/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
+ *  configure thres0 to adc channel
+ */
+#define APB_SARADC_APB_SARADC_THRES0_CHANNEL    0x0000000FU
+#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M  (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
+#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V  0x0000000FU
+#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S  0
+/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc thres0 monitor thres
+ */
+#define APB_SARADC_APB_SARADC_THRES0_HIGH    0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_V  0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_S  5
+/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc thres0 monitor thres
+ */
+#define APB_SARADC_APB_SARADC_THRES0_LOW    0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES0_LOW_M  (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
+#define APB_SARADC_APB_SARADC_THRES0_LOW_V  0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES0_LOW_S  18
+
+/** APB_SARADC_THRES1_CTRL_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
+/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
+ *  configure thres1 to adc channel
+ */
+#define APB_SARADC_APB_SARADC_THRES1_CHANNEL    0x0000000FU
+#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M  (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
+#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V  0x0000000FU
+#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S  0
+/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc thres1 monitor thres
+ */
+#define APB_SARADC_APB_SARADC_THRES1_HIGH    0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_V  0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_S  5
+/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc thres1 monitor thres
+ */
+#define APB_SARADC_APB_SARADC_THRES1_LOW    0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES1_LOW_M  (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
+#define APB_SARADC_APB_SARADC_THRES1_LOW_V  0x00001FFFU
+#define APB_SARADC_APB_SARADC_THRES1_LOW_S  18
+
+/** APB_SARADC_THRES_CTRL_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
+/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
+ *  enable thres to all channel
+ */
+#define APB_SARADC_APB_SARADC_THRES_ALL_EN    (BIT(27))
+#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M  (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
+#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S  27
+/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
+ *  enable thres1
+ */
+#define APB_SARADC_APB_SARADC_THRES1_EN    (BIT(30))
+#define APB_SARADC_APB_SARADC_THRES1_EN_M  (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
+#define APB_SARADC_APB_SARADC_THRES1_EN_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_EN_S  30
+/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
+ *  enable thres0
+ */
+#define APB_SARADC_APB_SARADC_THRES0_EN    (BIT(31))
+#define APB_SARADC_APB_SARADC_THRES0_EN_M  (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
+#define APB_SARADC_APB_SARADC_THRES0_EN_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_EN_S  31
+
+/** APB_SARADC_INT_ENA_REG register
+ *  digital saradc int register
+ */
+#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
+/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  tsens low  interrupt enable
+ */
+#define APB_SARADC_APB_SARADC_TSENS_INT_ENA    (BIT(25))
+#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M  (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
+#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V  0x00000001U
+#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S  25
+/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  saradc thres1 low  interrupt enable
+ */
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S  26
+/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  saradc thres0 low interrupt enable
+ */
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S  27
+/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  saradc thres1 high interrupt enable
+ */
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S  28
+/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  saradc thres0 high interrupt enable
+ */
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S  29
+/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  saradc2 done interrupt enable
+ */
+#define APB_SARADC_APB_SARADC2_DONE_INT_ENA    (BIT(30))
+#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M  (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
+#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V  0x00000001U
+#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S  30
+/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  saradc1 done interrupt enable
+ */
+#define APB_SARADC_APB_SARADC1_DONE_INT_ENA    (BIT(31))
+#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M  (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
+#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V  0x00000001U
+#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S  31
+
+/** APB_SARADC_INT_RAW_REG register
+ *  digital saradc int register
+ */
+#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
+/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  saradc tsens  interrupt raw
+ */
+#define APB_SARADC_APB_SARADC_TSENS_INT_RAW    (BIT(25))
+#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M  (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
+#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V  0x00000001U
+#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S  25
+/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  saradc thres1 low  interrupt raw
+ */
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S  26
+/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  saradc thres0 low interrupt raw
+ */
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S  27
+/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  saradc thres1 high interrupt raw
+ */
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S  28
+/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  saradc thres0 high interrupt raw
+ */
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S  29
+/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  saradc2 done interrupt raw
+ */
+#define APB_SARADC_APB_SARADC2_DONE_INT_RAW    (BIT(30))
+#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M  (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
+#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V  0x00000001U
+#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S  30
+/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  saradc1 done interrupt raw
+ */
+#define APB_SARADC_APB_SARADC1_DONE_INT_RAW    (BIT(31))
+#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M  (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
+#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V  0x00000001U
+#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S  31
+
+/** APB_SARADC_INT_ST_REG register
+ *  digital saradc int register
+ */
+#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
+/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
+ *  saradc tsens  interrupt state
+ */
+#define APB_SARADC_APB_SARADC_TSENS_INT_ST    (BIT(25))
+#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M  (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
+#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V  0x00000001U
+#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S  25
+/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
+ *  saradc thres1 low  interrupt state
+ */
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST    (BIT(26))
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S  26
+/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
+ *  saradc thres0 low interrupt state
+ */
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST    (BIT(27))
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S  27
+/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
+ *  saradc thres1 high interrupt state
+ */
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S  28
+/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
+ *  saradc thres0 high interrupt state
+ */
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S  29
+/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
+ *  saradc2 done interrupt state
+ */
+#define APB_SARADC_APB_SARADC2_DONE_INT_ST    (BIT(30))
+#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M  (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
+#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V  0x00000001U
+#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S  30
+/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  saradc1 done interrupt state
+ */
+#define APB_SARADC_APB_SARADC1_DONE_INT_ST    (BIT(31))
+#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M  (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
+#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V  0x00000001U
+#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S  31
+
+/** APB_SARADC_INT_CLR_REG register
+ *  digital saradc int register
+ */
+#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
+/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  saradc tsens  interrupt clear
+ */
+#define APB_SARADC_APB_SARADC_TSENS_INT_CLR    (BIT(25))
+#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M  (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
+#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V  0x00000001U
+#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S  25
+/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  saradc thres1 low  interrupt clear
+ */
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S  26
+/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  saradc thres0 low interrupt clear
+ */
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S  27
+/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  saradc thres1 high interrupt clear
+ */
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S  28
+/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  saradc thres0 high interrupt clear
+ */
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V  0x00000001U
+#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S  29
+/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  saradc2 done interrupt clear
+ */
+#define APB_SARADC_APB_SARADC2_DONE_INT_CLR    (BIT(30))
+#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M  (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
+#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V  0x00000001U
+#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S  30
+/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  saradc1 done interrupt clear
+ */
+#define APB_SARADC_APB_SARADC1_DONE_INT_CLR    (BIT(31))
+#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M  (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
+#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V  0x00000001U
+#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S  31
+
+/** APB_SARADC_DMA_CONF_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
+/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
+ *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+ */
+#define APB_SARADC_APB_ADC_EOF_NUM    0x0000FFFFU
+#define APB_SARADC_APB_ADC_EOF_NUM_M  (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
+#define APB_SARADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
+#define APB_SARADC_APB_ADC_EOF_NUM_S  0
+/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
+ *  reset_apb_adc_state
+ */
+#define APB_SARADC_APB_ADC_RESET_FSM    (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_M  (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
+#define APB_SARADC_APB_ADC_RESET_FSM_V  0x00000001U
+#define APB_SARADC_APB_ADC_RESET_FSM_S  30
+/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc use spi_dma
+ */
+#define APB_SARADC_APB_ADC_TRANS    (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_M  (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
+#define APB_SARADC_APB_ADC_TRANS_V  0x00000001U
+#define APB_SARADC_APB_ADC_TRANS_S  31
+
+/** APB_SARADC_CLKM_CONF_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
+/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
+ *  Integral I2S clock divider value
+ */
+#define APB_SARADC_CLKM_DIV_NUM    0x000000FFU
+#define APB_SARADC_CLKM_DIV_NUM_M  (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
+#define APB_SARADC_CLKM_DIV_NUM_V  0x000000FFU
+#define APB_SARADC_CLKM_DIV_NUM_S  0
+/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
+ *  Fractional clock divider numerator value
+ */
+#define APB_SARADC_CLKM_DIV_B    0x0000003FU
+#define APB_SARADC_CLKM_DIV_B_M  (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
+#define APB_SARADC_CLKM_DIV_B_V  0x0000003FU
+#define APB_SARADC_CLKM_DIV_B_S  8
+/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
+ *  Fractional clock divider denominator value
+ */
+#define APB_SARADC_CLKM_DIV_A    0x0000003FU
+#define APB_SARADC_CLKM_DIV_A_M  (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
+#define APB_SARADC_CLKM_DIV_A_V  0x0000003FU
+#define APB_SARADC_CLKM_DIV_A_S  14
+/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  reg clk en
+ */
+#define APB_SARADC_CLK_EN    (BIT(20))
+#define APB_SARADC_CLK_EN_M  (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
+#define APB_SARADC_CLK_EN_V  0x00000001U
+#define APB_SARADC_CLK_EN_S  20
+/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
+ *  Set this bit to enable clk_apll
+ */
+#define APB_SARADC_CLK_SEL    0x00000003U
+#define APB_SARADC_CLK_SEL_M  (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
+#define APB_SARADC_CLK_SEL_V  0x00000003U
+#define APB_SARADC_CLK_SEL_S  21
+
+/** APB_SARADC_APB_TSENS_CTRL_REG register
+ *  digital tsens configure register
+ */
+#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
+/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
+ *  temperature sensor data out
+ */
+#define APB_SARADC_TSENS_OUT    0x000000FFU
+#define APB_SARADC_TSENS_OUT_M  (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
+#define APB_SARADC_TSENS_OUT_V  0x000000FFU
+#define APB_SARADC_TSENS_OUT_S  0
+/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
+ *  invert temperature sensor data
+ */
+#define APB_SARADC_TSENS_IN_INV    (BIT(13))
+#define APB_SARADC_TSENS_IN_INV_M  (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
+#define APB_SARADC_TSENS_IN_INV_V  0x00000001U
+#define APB_SARADC_TSENS_IN_INV_S  13
+/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
+ *  temperature sensor clock divider
+ */
+#define APB_SARADC_TSENS_CLK_DIV    0x000000FFU
+#define APB_SARADC_TSENS_CLK_DIV_M  (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
+#define APB_SARADC_TSENS_CLK_DIV_V  0x000000FFU
+#define APB_SARADC_TSENS_CLK_DIV_S  14
+/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
+ *  temperature sensor power up
+ */
+#define APB_SARADC_TSENS_PU    (BIT(22))
+#define APB_SARADC_TSENS_PU_M  (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
+#define APB_SARADC_TSENS_PU_V  0x00000001U
+#define APB_SARADC_TSENS_PU_S  22
+
+/** APB_SARADC_TSENS_CTRL2_REG register
+ *  digital tsens configure register
+ */
+#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
+/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2;
+ *  the time that power up tsens need wait
+ */
+#define APB_SARADC_TSENS_XPD_WAIT    0x00000FFFU
+#define APB_SARADC_TSENS_XPD_WAIT_M  (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S)
+#define APB_SARADC_TSENS_XPD_WAIT_V  0x00000FFFU
+#define APB_SARADC_TSENS_XPD_WAIT_S  0
+/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0;
+ *  force power up tsens
+ */
+#define APB_SARADC_TSENS_XPD_FORCE    0x00000003U
+#define APB_SARADC_TSENS_XPD_FORCE_M  (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S)
+#define APB_SARADC_TSENS_XPD_FORCE_V  0x00000003U
+#define APB_SARADC_TSENS_XPD_FORCE_S  12
+/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1;
+ *  inv tsens clk
+ */
+#define APB_SARADC_TSENS_CLK_INV    (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV_M  (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S)
+#define APB_SARADC_TSENS_CLK_INV_V  0x00000001U
+#define APB_SARADC_TSENS_CLK_INV_S  14
+/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
+ *  tsens clk select
+ */
+#define APB_SARADC_TSENS_CLK_SEL    (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL_M  (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
+#define APB_SARADC_TSENS_CLK_SEL_V  0x00000001U
+#define APB_SARADC_TSENS_CLK_SEL_S  15
+
+/** APB_SARADC_CALI_REG register
+ *  digital saradc configure register
+ */
+#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
+/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
+ *  saradc cali factor
+ */
+#define APB_SARADC_APB_SARADC_CALI_CFG    0x0001FFFFU
+#define APB_SARADC_APB_SARADC_CALI_CFG_M  (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
+#define APB_SARADC_APB_SARADC_CALI_CFG_V  0x0001FFFFU
+#define APB_SARADC_APB_SARADC_CALI_CFG_S  0
+
+/** APB_TSENS_WAKE_REG register
+ *  digital tsens configure register
+ */
+#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
+/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
+ *  reg_wakeup_th_low
+ */
+#define APB_SARADC_WAKEUP_TH_LOW    0x000000FFU
+#define APB_SARADC_WAKEUP_TH_LOW_M  (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
+#define APB_SARADC_WAKEUP_TH_LOW_V  0x000000FFU
+#define APB_SARADC_WAKEUP_TH_LOW_S  0
+/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
+ *  reg_wakeup_th_high
+ */
+#define APB_SARADC_WAKEUP_TH_HIGH    0x000000FFU
+#define APB_SARADC_WAKEUP_TH_HIGH_M  (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
+#define APB_SARADC_WAKEUP_TH_HIGH_V  0x000000FFU
+#define APB_SARADC_WAKEUP_TH_HIGH_S  8
+/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
+ *  reg_wakeup_over_upper_th
+ */
+#define APB_SARADC_WAKEUP_OVER_UPPER_TH    (BIT(16))
+#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M  (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
+#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S  16
+/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
+ *  reg_wakeup_mode
+ */
+#define APB_SARADC_WAKEUP_MODE    (BIT(17))
+#define APB_SARADC_WAKEUP_MODE_M  (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
+#define APB_SARADC_WAKEUP_MODE_V  0x00000001U
+#define APB_SARADC_WAKEUP_MODE_S  17
+/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
+ *  reg_wakeup_en
+ */
+#define APB_SARADC_WAKEUP_EN    (BIT(18))
+#define APB_SARADC_WAKEUP_EN_M  (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
+#define APB_SARADC_WAKEUP_EN_V  0x00000001U
+#define APB_SARADC_WAKEUP_EN_S  18
+
+/** APB_TSENS_SAMPLE_REG register
+ *  digital tsens configure register
+ */
+#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
+/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
+ *  HW sample rate
+ */
+#define APB_SARADC_TSENS_SAMPLE_RATE    0x0000FFFFU
+#define APB_SARADC_TSENS_SAMPLE_RATE_M  (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
+#define APB_SARADC_TSENS_SAMPLE_RATE_V  0x0000FFFFU
+#define APB_SARADC_TSENS_SAMPLE_RATE_S  0
+/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
+ *  HW sample en
+ */
+#define APB_SARADC_TSENS_SAMPLE_EN    (BIT(16))
+#define APB_SARADC_TSENS_SAMPLE_EN_M  (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
+#define APB_SARADC_TSENS_SAMPLE_EN_V  0x00000001U
+#define APB_SARADC_TSENS_SAMPLE_EN_S  16
+
+/** APB_SARADC_CTRL_DATE_REG register
+ *  version
+ */
+#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
+/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
+ *  version
+ */
+#define APB_SARADC_DATE    0xFFFFFFFFU
+#define APB_SARADC_DATE_M  (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
+#define APB_SARADC_DATE_V  0xFFFFFFFFU
+#define APB_SARADC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/apb_saradc_struct.h b/components/soc/esp32p4/include/soc/apb_saradc_struct.h
new file mode 100644
index 0000000000..b76d6cfb5b
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/apb_saradc_struct.h
@@ -0,0 +1,757 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configure Register */
+/** Type of saradc_ctrl register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
+         *  select software enable saradc sample
+         */
+        uint32_t saradc_saradc_start_force:1;
+        /** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
+         *  software enable saradc sample
+         */
+        uint32_t saradc_saradc_start:1;
+        uint32_t reserved_2:4;
+        /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
+         *  SAR clock gated
+         */
+        uint32_t saradc_saradc_sar_clk_gated:1;
+        /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
+         *  SAR clock divider
+         */
+        uint32_t saradc_saradc_sar_clk_div:8;
+        /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t saradc_saradc_sar_patt_len:3;
+        uint32_t reserved_18:5;
+        /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC1 CTRL
+         */
+        uint32_t saradc_saradc_sar_patt_p_clear:1;
+        uint32_t reserved_24:3;
+        /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
+         *  force option to xpd sar blocks
+         */
+        uint32_t saradc_saradc_xpd_sar_force:2;
+        /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
+         *  enable saradc2 power detect driven func.
+         */
+        uint32_t saradc_saradc2_pwdet_drv:1;
+        /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
+         *  wait arbit signal stable after sar_done
+         */
+        uint32_t saradc_saradc_wait_arb_cycle:2;
+    };
+    uint32_t val;
+} apb_saradc_ctrl_reg_t;
+
+/** Type of saradc_ctrl2 register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
+         *  enable max meas num
+         */
+        uint32_t saradc_saradc_meas_num_limit:1;
+        /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
+         *  max conversion number
+         */
+        uint32_t saradc_saradc_max_meas_num:8;
+        /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
+         *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+         */
+        uint32_t saradc_saradc_sar1_inv:1;
+        /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
+         *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+         */
+        uint32_t saradc_saradc_sar2_inv:1;
+        uint32_t reserved_11:1;
+        /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
+         *  to set saradc timer target
+         */
+        uint32_t saradc_saradc_timer_target:12;
+        /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
+         *  to enable saradc timer trigger
+         */
+        uint32_t saradc_saradc_timer_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} apb_saradc_ctrl2_reg_t;
+
+/** Type of saradc_filter_ctrl1 register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
+         *  Factor of saradc filter1
+         */
+        uint32_t saradc_apb_saradc_filter_factor1:3;
+        /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
+         *  Factor of saradc filter0
+         */
+        uint32_t saradc_apb_saradc_filter_factor0:3;
+    };
+    uint32_t val;
+} apb_saradc_filter_ctrl1_reg_t;
+
+/** Type of saradc_fsm_wait register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8;
+         *  saradc_xpd_wait
+         */
+        uint32_t saradc_saradc_xpd_wait:8;
+        /** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8;
+         *  saradc_rstb_wait
+         */
+        uint32_t saradc_saradc_rstb_wait:8;
+        /** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255;
+         *  saradc_standby_wait
+         */
+        uint32_t saradc_saradc_standby_wait:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} apb_saradc_fsm_wait_reg_t;
+
+/** Type of saradc_sar1_status register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912;
+         *  saradc1 status about data and channel
+         */
+        uint32_t saradc_saradc_sar1_status:32;
+    };
+    uint32_t val;
+} apb_saradc_sar1_status_reg_t;
+
+/** Type of saradc_sar2_status register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912;
+         *  saradc2 status about data and channel
+         */
+        uint32_t saradc_saradc_sar2_status:32;
+    };
+    uint32_t val;
+} apb_saradc_sar2_status_reg_t;
+
+/** Type of saradc_sar_patt_tab1 register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
+         *  item 0 ~ 3 for pattern table 1 (each item one byte)
+         */
+        uint32_t saradc_saradc_sar_patt_tab1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} apb_saradc_sar_patt_tab1_reg_t;
+
+/** Type of saradc_sar_patt_tab2 register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
+         *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+         */
+        uint32_t saradc_saradc_sar_patt_tab2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} apb_saradc_sar_patt_tab2_reg_t;
+
+/** Type of saradc_onetime_sample register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
+         *  configure onetime atten
+         */
+        uint32_t saradc_saradc_onetime_atten:2;
+        /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
+         *  configure onetime channel
+         */
+        uint32_t saradc_saradc_onetime_channel:4;
+        /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
+         *  trigger adc onetime sample
+         */
+        uint32_t saradc_saradc_onetime_start:1;
+        /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
+         *  enable adc2 onetime sample
+         */
+        uint32_t saradc_saradc2_onetime_sample:1;
+        /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
+         *  enable adc1 onetime sample
+         */
+        uint32_t saradc_saradc1_onetime_sample:1;
+    };
+    uint32_t val;
+} apb_saradc_onetime_sample_reg_t;
+
+/** Type of saradc_arb_ctrl register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
+         *  adc2 arbiter force to enableapb controller
+         */
+        uint32_t saradc_adc_arb_apb_force:1;
+        /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
+         *  adc2 arbiter force to enable rtc controller
+         */
+        uint32_t saradc_adc_arb_rtc_force:1;
+        /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
+         *  adc2 arbiter force to enable wifi controller
+         */
+        uint32_t saradc_adc_arb_wifi_force:1;
+        /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
+         *  adc2 arbiter force grant
+         */
+        uint32_t saradc_adc_arb_grant_force:1;
+        /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
+         *  Set adc2 arbiterapb priority
+         */
+        uint32_t saradc_adc_arb_apb_priority:2;
+        /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
+         *  Set adc2 arbiter rtc priority
+         */
+        uint32_t saradc_adc_arb_rtc_priority:2;
+        /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
+         *  Set adc2 arbiter wifi priority
+         */
+        uint32_t saradc_adc_arb_wifi_priority:2;
+        /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
+         *  adc2 arbiter uses fixed priority
+         */
+        uint32_t saradc_adc_arb_fix_priority:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} apb_saradc_arb_ctrl_reg_t;
+
+/** Type of saradc_filter_ctrl0 register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
+         *  configure filter1 to adc channel
+         */
+        uint32_t saradc_apb_saradc_filter_channel1:4;
+        /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
+         *  configure filter0 to adc channel
+         */
+        uint32_t saradc_apb_saradc_filter_channel0:4;
+        uint32_t reserved_26:5;
+        /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc1_filter
+         */
+        uint32_t saradc_apb_saradc_filter_reset:1;
+    };
+    uint32_t val;
+} apb_saradc_filter_ctrl0_reg_t;
+
+/** Type of saradc_sar1data_status register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
+         *  saradc1 data
+         */
+        uint32_t saradc_apb_saradc1_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} apb_saradc_sar1data_status_reg_t;
+
+/** Type of saradc_sar2data_status register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
+         *  saradc2 data
+         */
+        uint32_t saradc_apb_saradc2_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} apb_saradc_sar2data_status_reg_t;
+
+/** Type of saradc_thres0_ctrl register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
+         *  configure thres0 to adc channel
+         */
+        uint32_t saradc_apb_saradc_thres0_channel:4;
+        uint32_t reserved_4:1;
+        /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc thres0 monitor thres
+         */
+        uint32_t saradc_apb_saradc_thres0_high:13;
+        /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc thres0 monitor thres
+         */
+        uint32_t saradc_apb_saradc_thres0_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} apb_saradc_thres0_ctrl_reg_t;
+
+/** Type of saradc_thres1_ctrl register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
+         *  configure thres1 to adc channel
+         */
+        uint32_t saradc_apb_saradc_thres1_channel:4;
+        uint32_t reserved_4:1;
+        /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc thres1 monitor thres
+         */
+        uint32_t saradc_apb_saradc_thres1_high:13;
+        /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc thres1 monitor thres
+         */
+        uint32_t saradc_apb_saradc_thres1_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} apb_saradc_thres1_ctrl_reg_t;
+
+/** Type of saradc_thres_ctrl register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
+         *  enable thres to all channel
+         */
+        uint32_t saradc_apb_saradc_thres_all_en:1;
+        uint32_t reserved_28:2;
+        /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
+         *  enable thres1
+         */
+        uint32_t saradc_apb_saradc_thres1_en:1;
+        /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
+         *  enable thres0
+         */
+        uint32_t saradc_apb_saradc_thres0_en:1;
+    };
+    uint32_t val;
+} apb_saradc_thres_ctrl_reg_t;
+
+/** Type of saradc_int_ena register
+ *  digital saradc int register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
+         *  tsens low  interrupt enable
+         */
+        uint32_t saradc_apb_saradc_tsens_int_ena:1;
+        /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
+         *  saradc thres1 low  interrupt enable
+         */
+        uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
+        /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
+         *  saradc thres0 low interrupt enable
+         */
+        uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
+        /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
+         *  saradc thres1 high interrupt enable
+         */
+        uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
+        /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
+         *  saradc thres0 high interrupt enable
+         */
+        uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
+        /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
+         *  saradc2 done interrupt enable
+         */
+        uint32_t saradc_apb_saradc2_done_int_ena:1;
+        /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  saradc1 done interrupt enable
+         */
+        uint32_t saradc_apb_saradc1_done_int_ena:1;
+    };
+    uint32_t val;
+} apb_saradc_int_ena_reg_t;
+
+/** Type of saradc_int_raw register
+ *  digital saradc int register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  saradc tsens  interrupt raw
+         */
+        uint32_t saradc_apb_saradc_tsens_int_raw:1;
+        /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  saradc thres1 low  interrupt raw
+         */
+        uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
+        /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  saradc thres0 low interrupt raw
+         */
+        uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
+        /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  saradc thres1 high interrupt raw
+         */
+        uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
+        /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  saradc thres0 high interrupt raw
+         */
+        uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
+        /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  saradc2 done interrupt raw
+         */
+        uint32_t saradc_apb_saradc2_done_int_raw:1;
+        /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  saradc1 done interrupt raw
+         */
+        uint32_t saradc_apb_saradc1_done_int_raw:1;
+    };
+    uint32_t val;
+} apb_saradc_int_raw_reg_t;
+
+/** Type of saradc_int_st register
+ *  digital saradc int register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
+         *  saradc tsens  interrupt state
+         */
+        uint32_t saradc_apb_saradc_tsens_int_st:1;
+        /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
+         *  saradc thres1 low  interrupt state
+         */
+        uint32_t saradc_apb_saradc_thres1_low_int_st:1;
+        /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
+         *  saradc thres0 low interrupt state
+         */
+        uint32_t saradc_apb_saradc_thres0_low_int_st:1;
+        /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
+         *  saradc thres1 high interrupt state
+         */
+        uint32_t saradc_apb_saradc_thres1_high_int_st:1;
+        /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
+         *  saradc thres0 high interrupt state
+         */
+        uint32_t saradc_apb_saradc_thres0_high_int_st:1;
+        /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
+         *  saradc2 done interrupt state
+         */
+        uint32_t saradc_apb_saradc2_done_int_st:1;
+        /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
+         *  saradc1 done interrupt state
+         */
+        uint32_t saradc_apb_saradc1_done_int_st:1;
+    };
+    uint32_t val;
+} apb_saradc_int_st_reg_t;
+
+/** Type of saradc_int_clr register
+ *  digital saradc int register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
+         *  saradc tsens  interrupt clear
+         */
+        uint32_t saradc_apb_saradc_tsens_int_clr:1;
+        /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
+         *  saradc thres1 low  interrupt clear
+         */
+        uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
+        /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
+         *  saradc thres0 low interrupt clear
+         */
+        uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
+        /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
+         *  saradc thres1 high interrupt clear
+         */
+        uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
+        /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
+         *  saradc thres0 high interrupt clear
+         */
+        uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
+        /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
+         *  saradc2 done interrupt clear
+         */
+        uint32_t saradc_apb_saradc2_done_int_clr:1;
+        /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  saradc1 done interrupt clear
+         */
+        uint32_t saradc_apb_saradc1_done_int_clr:1;
+    };
+    uint32_t val;
+} apb_saradc_int_clr_reg_t;
+
+/** Type of saradc_dma_conf register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
+         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+         */
+        uint32_t saradc_apb_adc_eof_num:16;
+        uint32_t reserved_16:14;
+        /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
+         *  reset_apb_adc_state
+         */
+        uint32_t saradc_apb_adc_reset_fsm:1;
+        /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc use spi_dma
+         */
+        uint32_t saradc_apb_adc_trans:1;
+    };
+    uint32_t val;
+} apb_saradc_dma_conf_reg_t;
+
+/** Type of saradc_clkm_conf register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
+         *  Integral I2S clock divider value
+         */
+        uint32_t saradc_clkm_div_num:8;
+        /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t saradc_clkm_div_b:6;
+        /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t saradc_clkm_div_a:6;
+        /** saradc_clk_en : R/W; bitpos: [20]; default: 0;
+         *  reg clk en
+         */
+        uint32_t saradc_clk_en:1;
+        /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
+         *  Set this bit to enable clk_apll
+         */
+        uint32_t saradc_clk_sel:2;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} apb_saradc_clkm_conf_reg_t;
+
+/** Type of saradc_apb_tsens_ctrl register
+ *  digital tsens configure register
+ */
+typedef union {
+    struct {
+        /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
+         *  temperature sensor data out
+         */
+        uint32_t saradc_tsens_out:8;
+        uint32_t reserved_8:5;
+        /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
+         *  invert temperature sensor data
+         */
+        uint32_t saradc_tsens_in_inv:1;
+        /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
+         *  temperature sensor clock divider
+         */
+        uint32_t saradc_tsens_clk_div:8;
+        /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
+         *  temperature sensor power up
+         */
+        uint32_t saradc_tsens_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} apb_saradc_apb_tsens_ctrl_reg_t;
+
+/** Type of saradc_tsens_ctrl2 register
+ *  digital tsens configure register
+ */
+typedef union {
+    struct {
+        /** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2;
+         *  the time that power up tsens need wait
+         */
+        uint32_t saradc_tsens_xpd_wait:12;
+        /** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0;
+         *  force power up tsens
+         */
+        uint32_t saradc_tsens_xpd_force:2;
+        /** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1;
+         *  inv tsens clk
+         */
+        uint32_t saradc_tsens_clk_inv:1;
+        /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
+         *  tsens clk select
+         */
+        uint32_t saradc_tsens_clk_sel:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} apb_saradc_tsens_ctrl2_reg_t;
+
+/** Type of saradc_cali register
+ *  digital saradc configure register
+ */
+typedef union {
+    struct {
+        /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
+         *  saradc cali factor
+         */
+        uint32_t saradc_apb_saradc_cali_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} apb_saradc_cali_reg_t;
+
+/** Type of tsens_wake register
+ *  digital tsens configure register
+ */
+typedef union {
+    struct {
+        /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
+         *  reg_wakeup_th_low
+         */
+        uint32_t saradc_wakeup_th_low:8;
+        /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
+         *  reg_wakeup_th_high
+         */
+        uint32_t saradc_wakeup_th_high:8;
+        /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
+         *  reg_wakeup_over_upper_th
+         */
+        uint32_t saradc_wakeup_over_upper_th:1;
+        /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
+         *  reg_wakeup_mode
+         */
+        uint32_t saradc_wakeup_mode:1;
+        /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
+         *  reg_wakeup_en
+         */
+        uint32_t saradc_wakeup_en:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} apb_tsens_wake_reg_t;
+
+/** Type of tsens_sample register
+ *  digital tsens configure register
+ */
+typedef union {
+    struct {
+        /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
+         *  HW sample rate
+         */
+        uint32_t saradc_tsens_sample_rate:16;
+        /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
+         *  HW sample en
+         */
+        uint32_t saradc_tsens_sample_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} apb_tsens_sample_reg_t;
+
+/** Type of saradc_ctrl_date register
+ *  version
+ */
+typedef union {
+    struct {
+        /** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
+         *  version
+         */
+        uint32_t saradc_date:32;
+    };
+    uint32_t val;
+} apb_saradc_ctrl_date_reg_t;
+
+
+typedef struct apb_dev_t {
+    volatile apb_saradc_ctrl_reg_t saradc_ctrl;
+    volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
+    volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
+    volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait;
+    volatile apb_saradc_sar1_status_reg_t saradc_sar1_status;
+    volatile apb_saradc_sar2_status_reg_t saradc_sar2_status;
+    volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
+    volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
+    volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
+    volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
+    volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
+    volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
+    volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
+    volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
+    volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
+    volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
+    volatile apb_saradc_int_ena_reg_t saradc_int_ena;
+    volatile apb_saradc_int_raw_reg_t saradc_int_raw;
+    volatile apb_saradc_int_st_reg_t saradc_int_st;
+    volatile apb_saradc_int_clr_reg_t saradc_int_clr;
+    volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
+    volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
+    volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
+    volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
+    volatile apb_saradc_cali_reg_t saradc_cali;
+    volatile apb_tsens_wake_reg_t tsens_wake;
+    volatile apb_tsens_sample_reg_t tsens_sample;
+    uint32_t reserved_06c[228];
+    volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
+} apb_dev_t;
+
+extern apb_dev_t APB_SARADC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/boot_mode.h b/components/soc/esp32p4/include/soc/boot_mode.h
new file mode 100644
index 0000000000..d532dc1bc9
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/boot_mode.h
@@ -0,0 +1,93 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_BOOT_MODE_H_
+#define _SOC_BOOT_MODE_H_
+
+#include "soc.h"
+
+/*SPI Boot*/
+#define IS_1XXX(v)                              (((v)&0x08)==0x08)
+
+/*Download Boot, SPI(or SDIO_V2)/UART0*/
+#define IS_00XX(v)                              (((v)&0x0c)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
+#define IS_0000(v)                              (((v)&0x0f)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
+#define IS_0001(v)                              (((v)&0x0f)==0x01)
+
+/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
+#define IS_0010(v)                              (((v)&0x0f)==0x02)
+
+/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
+#define IS_0011(v)                              (((v)&0x0f)==0x03)
+
+/*legacy SPI Boot*/
+#define IS_0100(v)                              (((v)&0x0f)==0x04)
+
+/*ATE/ANALOG Mode*/
+#define IS_0101(v)                              (((v)&0x0f)==0x05)
+
+/*SPI(or SDIO_V1) download Mode*/
+#define IS_0110(v)                              (((v)&0x0f)==0x06)
+
+/*Diagnostic Mode+UART0 download Mode*/
+#define IS_0111(v)                              (((v)&0x0f)==0x07)
+
+
+
+#define BOOT_MODE_GET()                         (GPIO_REG_READ(GPIO_STRAP_REG))
+
+/*do not include download mode*/
+#define ETS_IS_UART_BOOT()                      IS_0111(BOOT_MODE_GET())
+
+/*all spi boot including spi/legacy*/
+#define ETS_IS_FLASH_BOOT()                     (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
+
+/*all faster spi boot including spi*/
+#define ETS_IS_FAST_FLASH_BOOT()                IS_1XXX(BOOT_MODE_GET())
+
+#if SUPPORT_SDIO_DOWNLOAD
+
+/*all sdio V2 of failing edge input, failing edge output*/
+#define ETS_IS_SDIO_FEI_FEO_V2_BOOT()           IS_0000(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, raising edge output*/
+#define ETS_IS_SDIO_FEI_REO_V2_BOOT()           IS_0001(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V2_BOOT()           IS_0010(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, raising edge output*/
+#define ETS_IS_SDIO_REI_REO_V2_BOOT()           IS_0011(BOOT_MODE_GET())
+
+/*all sdio V1 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V1_BOOT()           IS_0110(BOOT_MODE_GET())
+
+/*do not include joint download mode*/
+#define ETS_IS_SDIO_BOOT()                      IS_0110(BOOT_MODE_GET())
+#else
+
+/*do not include joint download mode*/
+#define ETS_IS_SPI_DOWNLOAD_BOOT()              IS_0110(BOOT_MODE_GET())
+
+#endif
+
+/*joint download boot*/
+#define ETS_IS_JOINT_DOWNLOAD_BOOT()                  IS_00XX(BOOT_MODE_GET())
+
+/*ATE mode*/
+#define ETS_IS_ATE_BOOT()                       IS_0101(BOOT_MODE_GET())
+
+/*used by  ETS_IS_SDIO_UART_BOOT*/
+#define SEL_NO_BOOT                             0
+#define SEL_SDIO_BOOT                           BIT0
+#define SEL_UART_BOOT                           BIT1
+#define SEL_SPI_SLAVE_BOOT                      BIT2
+
+#endif /* _SOC_BOOT_MODE_H_ */
diff --git a/components/soc/esp32p4/include/soc/clic_reg.h b/components/soc/esp32p4/include/soc/clic_reg.h
new file mode 100644
index 0000000000..3c170302af
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/clic_reg.h
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define _CLIC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NLBITS                   3
+#define CLIC_EXT_INTR_NUM_OFFSET 16
+#define DUALCORE_CLIC_CTRL_OFF   0x10000
+
+#define DR_REG_CLIC_BASE      ( 0x20800000 )
+#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
+
+#define CLIC_INT_CONFIG_REG          (DR_REG_CLIC_BASE + 0x0)
+/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
+/*description: .*/
+#define CLIC_INT_CONFIG_NMBITS    0x00000003
+#define CLIC_INT_CONFIG_NMBITS_M  ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S))
+#define CLIC_INT_CONFIG_NMBITS_V  0x3
+#define CLIC_INT_CONFIG_NMBITS_S  5
+/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: .*/
+#define CLIC_INT_CONFIG_NLBITS    0x0000000F
+#define CLIC_INT_CONFIG_NLBITS_M  ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S))
+#define CLIC_INT_CONFIG_NLBITS_V  0xF
+#define CLIC_INT_CONFIG_NLBITS_S  1
+/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: .*/
+#define CLIC_INT_CONFIG_NVBITS    (BIT(0))
+#define CLIC_INT_CONFIG_NVBITS_M  (BIT(0))
+#define CLIC_INT_CONFIG_NVBITS_V  0x1
+#define CLIC_INT_CONFIG_NVBITS_S  0
+
+#define CLIC_INT_INFO_REG          (DR_REG_CLIC_BASE + 0x4)
+/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
+/*description: .*/
+#define CLIC_INT_INFO_CTLBITS    0x0000000F
+#define CLIC_INT_INFO_CTLBITS_M  ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S))
+#define CLIC_INT_INFO_CTLBITS_V  0xF
+#define CLIC_INT_INFO_CTLBITS_S  21
+/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
+/*description: .*/
+#define CLIC_INT_INFO_VERSION    0x000000FF
+#define CLIC_INT_INFO_VERSION_M  ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S))
+#define CLIC_INT_INFO_VERSION_V  0xFF
+#define CLIC_INT_INFO_VERSION_S  13
+/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
+/*description: .*/
+#define CLIC_INT_INFO_NUM_INT    0x00001FFF
+#define CLIC_INT_INFO_NUM_INT_M  ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S))
+#define CLIC_INT_INFO_NUM_INT_V  0x1FFF
+#define CLIC_INT_INFO_NUM_INT_S  0
+
+#define CLIC_INT_THRESH_REG          (DR_REG_CLIC_BASE + 0x8)
+/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
+/*description: .*/
+#define CLIC_CPU_INT_THRESH    0x000000FF
+#define CLIC_CPU_INT_THRESH_M  ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
+#define CLIC_CPU_INT_THRESH_V  0xFF
+#define CLIC_CPU_INT_THRESH_S  24
+
+#define CLIC_INT_CTRL_REG(i)          (DR_REG_CLIC_CTRL_BASE + (i) * 4)
+/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
+/*description: .*/
+#define CLIC_INT_CTL    0x000000FF
+#define CLIC_INT_CTL_M  ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S))
+#define CLIC_INT_CTL_V  0xFF
+#define CLIC_INT_CTL_S  24
+/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
+/*description: .*/
+#define CLIC_INT_ATTR_MODE    0x00000003
+#define CLIC_INT_ATTR_MODE_M  ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S))
+#define CLIC_INT_ATTR_MODE_V  0x3
+#define CLIC_INT_ATTR_MODE_S  22
+/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: .*/
+#define CLIC_INT_ATTR_TRIG    0x00000003
+#define CLIC_INT_ATTR_TRIG_M  ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S))
+#define CLIC_INT_ATTR_TRIG_V  0x3
+#define CLIC_INT_ATTR_TRIG_S  17
+/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: .*/
+#define CLIC_INT_ATTR_SHV    (BIT(16))
+#define CLIC_INT_ATTR_SHV_M  (BIT(16))
+#define CLIC_INT_ATTR_SHV_V  0x1
+#define CLIC_INT_ATTR_SHV_S  16
+/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: .*/
+#define CLIC_INT_IE    (BIT(8))
+#define CLIC_INT_IE_M  (BIT(8))
+#define CLIC_INT_IE_V  0x1
+#define CLIC_INT_IE_S  8
+/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: .*/
+#define CLIC_INT_IP    (BIT(0))
+#define CLIC_INT_IP_M  (BIT(0))
+#define CLIC_INT_IP_V  0x1
+#define CLIC_INT_IP_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_CLIC_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/clint_reg.h b/components/soc/esp32p4/include/soc/clint_reg.h
new file mode 100644
index 0000000000..5ce015e17f
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/clint_reg.h
@@ -0,0 +1,163 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DR_REG_CLINT_M_BASE(i)    ( 0x20001800 + (i) * 0x100 )
+#define DR_REG_CLINT_U_BASE(i)    ( 0x20001C00 + (i) * 0x100 )
+
+/*CLINT MINT*/
+#define CLINT_MINT_SIP_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x0)
+/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define CLINT_CPU_MINT_SIP    0xFFFFFFFF
+#define CLINT_CPU_MINT_SIP_M  ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S))
+#define CLINT_CPU_MINT_SIP_V  0xFFFFFFFF
+#define CLINT_CPU_MINT_SIP_S  0
+
+#define CLINT_MINT_TIMECTL_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x4)
+/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: .*/
+#define CLINT_MINT_SAMPLING_MODE    0x00000003
+#define CLINT_MINT_SAMPLING_MODE_M  ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
+#define CLINT_MINT_SAMPLING_MODE_V  0x3
+#define CLINT_MINT_SAMPLING_MODE_S  4
+/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_MINT_COUNTER_OVERFLOW  (BIT(3))
+#define CLINT_MINT_COUNTER_OVERFLOW_M  (BIT(3))
+#define CLINT_MINT_COUNTER_OVERFLOW_V  0x1
+#define CLINT_MINT_COUNTER_OVERFLOW_S  3
+/* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_MINT_TIMERINT_PENDING  (BIT(2))
+#define CLINT_MINT_TIMERINT_PENDING_M  (BIT(2))
+#define CLINT_MINT_TIMERINT_PENDING_V  0x1
+#define CLINT_MINT_TIMERINT_PENDING_S  2
+/* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_MINT_TIMERINT_EN  (BIT(1))
+#define CLINT_MINT_TIMERINT_EN_M  (BIT(1))
+#define CLINT_MINT_TIMERINT_EN_V  0x1
+#define CLINT_MINT_TIMERINT_EN_S  1
+/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_MINT_COUNTER_EN  (BIT(0))
+#define CLINT_MINT_COUNTER_EN_M  (BIT(0))
+#define CLINT_MINT_COUNTER_EN_V  0x1
+#define CLINT_MINT_COUNTER_EN_S  0
+
+#define CLINT_MINT_MTIME_L_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x8)
+/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_MINT_MTIME_L    0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIME_L_M  ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
+#define CLINT_CPU_MINT_MTIME_L_V  0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIME_L_S  0
+
+#define CLINT_MINT_MTIME_H_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0xC)
+/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_MINT_MTIME_H    0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIME_H_M  ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
+#define CLINT_CPU_MINT_MTIME_H_V  0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIME_H_S  0
+
+#define CLINT_MINT_MTIMECMP_L_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x10)
+/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_MINT_MTIMECMP_L    0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIMECMP_L_M  ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
+#define CLINT_CPU_MINT_MTIMECMP_L_V  0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIMECMP_L_S  0
+
+#define CLINT_MINT_MTIMECMP_H_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x14)
+/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_MINT_MTIMECMP_H    0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIMECMP_H_M  ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
+#define CLINT_CPU_MINT_MTIMECMP_H_V  0xFFFFFFFF
+#define CLINT_CPU_MINT_MTIMECMP_H_S  0
+
+/*CLINT UINT*/
+#define CLINT_UINT_SIP_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x0)
+/* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define CLINT_CPU_UINT_SIP    0xFFFFFFFF
+#define CLINT_CPU_UINT_SIP_M  ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S))
+#define CLINT_CPU_UINT_SIP_V  0xFFFFFFFF
+#define CLINT_CPU_UINT_SIP_S  0
+
+#define CLINT_UINT_TIMECTL_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x4)
+/* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: .*/
+#define CLINT_UINT_SAMPLING_MODE    0x00000003
+#define CLINT_UINT_SAMPLING_MODE_M  ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S))
+#define CLINT_UINT_SAMPLING_MODE_V  0x3
+#define CLINT_UINT_SAMPLING_MODE_S  4
+/* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_UINT_COUNTER_OVERFLOW  (BIT(3))
+#define CLINT_UINT_COUNTER_OVERFLOW_M  (BIT(3))
+#define CLINT_UINT_COUNTER_OVERFLOW_V  0x1
+#define CLINT_UINT_COUNTER_OVERFLOW_S  3
+/* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_UINT_TIMERINT_PENDING  (BIT(2))
+#define CLINT_UINT_TIMERINT_PENDING_M  (BIT(2))
+#define CLINT_UINT_TIMERINT_PENDING_V  0x1
+#define CLINT_UINT_TIMERINT_PENDING_S  2
+/* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_UINT_TIMERINT_EN  (BIT(1))
+#define CLINT_UINT_TIMERINT_EN_M  (BIT(1))
+#define CLINT_UINT_TIMERINT_EN_V  0x1
+#define CLINT_UINT_TIMERINT_EN_S  1
+/* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define CLINT_UINT_COUNTER_EN  (BIT(0))
+#define CLINT_UINT_COUNTER_EN_M  (BIT(0))
+#define CLINT_UINT_COUNTER_EN_V  0x1
+#define CLINT_UINT_COUNTER_EN_S  0
+
+#define CLINT_UINT_UTIME_L_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x8)
+/* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_UINT_UTIME_L    0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIME_L_M  ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S))
+#define CLINT_CPU_UINT_UTIME_L_V  0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIME_L_S  0
+
+#define CLINT_UINT_UTIME_H_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0xC)
+/* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_UINT_UTIME_H    0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIME_H_M  ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S))
+#define CLINT_CPU_UINT_UTIME_H_V  0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIME_H_S  0
+
+#define CLINT_UINT_UTIMECMP_L_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x10)
+/* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_UINT_UTIMECMP_L    0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIMECMP_L_M  ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S))
+#define CLINT_CPU_UINT_UTIMECMP_L_V  0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIMECMP_L_S  0
+
+#define CLINT_UINT_UTIMECMP_H_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x14)
+/* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define CLINT_CPU_UINT_UTIMECMP_H    0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIMECMP_H_M  ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S))
+#define CLINT_CPU_UINT_UTIMECMP_H_V  0xFFFFFFFF
+#define CLINT_CPU_UINT_UTIMECMP_H_S  0
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
new file mode 100644
index 0000000000..6e421b6437
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -0,0 +1,426 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ ************************* ESP32C6 Root Clock Source ****************************
+ * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
+ *
+ *    This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
+ *
+ *    The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
+ *
+ * 2) External 40MHz Crystal Clock: XTAL
+ *
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
+ *
+ *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
+ *    can be computed in runtime through calibration.
+ *
+ * 4) Internal 32kHz RC Oscillator: RC32K
+ *
+ *    The exact frequency of this clock can be computed in runtime through calibration.
+ *
+ * 5) External 32kHz Crystal Clock (optional): XTAL32K
+ *
+ *    The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
+ *    pins.
+ *
+ *    XTAL32K_CLK can also be calibrated to get its exact frequency.
+ *
+ * 6) External Slow Clock (optional): OSC_SLOW
+ *
+ *    A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
+ *    RTC_SLOW_CLK.
+ *
+ *    OSC_SLOW_CLK can also be calibrated to get its exact frequency.
+ */
+
+/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
+#define SOC_CLK_RC_FAST_FREQ_APPROX         17500000                            /*!< Approximate RC_FAST_CLK frequency in Hz */
+#define SOC_CLK_RC_SLOW_FREQ_APPROX         136000                              /*!< Approximate RC_SLOW_CLK frequency in Hz */
+#define SOC_CLK_RC32K_FREQ_APPROX           32768                               /*!< Approximate RC32K_CLK frequency in Hz */
+#define SOC_CLK_XTAL32K_FREQ_APPROX         32768                               /*!< Approximate XTAL32K_CLK frequency in Hz */
+#define SOC_CLK_OSC_SLOW_FREQ_APPROX        32768                               /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
+
+// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
+// {loc}: EXT, INT
+// {type}: XTAL, RC
+// [attr] - optional: [frequency], FAST, SLOW
+/**
+ * @brief Root clock
+ */
+typedef enum {
+    SOC_ROOT_CLK_INT_RC_FAST,          /*!< Internal 17.5MHz RC oscillator */
+    SOC_ROOT_CLK_INT_RC_SLOW,          /*!< Internal 136kHz RC oscillator */
+    SOC_ROOT_CLK_EXT_XTAL,             /*!< External 40MHz crystal */
+    SOC_ROOT_CLK_EXT_XTAL32K,          /*!< External 32kHz crystal */
+    SOC_ROOT_CLK_INT_RC32K,            /*!< Internal 32kHz RC oscillator */
+    SOC_ROOT_CLK_EXT_OSC_SLOW,         /*!< External slow clock signal at pin0 */
+} soc_root_clk_t;
+
+/**
+ * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
+ * @note Enum values are matched with the register field values on purpose
+ */
+typedef enum {
+    SOC_CPU_CLK_SRC_XTAL = 0,              /*!< Select XTAL_CLK as CPU_CLK source */
+    SOC_CPU_CLK_SRC_PLL = 1,               /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
+    SOC_CPU_CLK_SRC_RC_FAST = 2,           /*!< Select RC_FAST_CLK as CPU_CLK source */
+    SOC_CPU_CLK_SRC_INVALID,               /*!< Invalid CPU_CLK source */
+} soc_cpu_clk_src_t;
+
+/**
+ * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
+ * @note Enum values are matched with the register field values on purpose
+ */
+typedef enum {
+    SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0,                 /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1,                 /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_RC32K = 2,                   /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3,                /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_INVALID,                     /*!< Invalid RTC_SLOW_CLK source */
+} soc_rtc_slow_clk_src_t;
+
+/**
+ * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
+ * @note Enum values are matched with the register field values on purpose
+ */
+typedef enum {
+    SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
+    SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1,      /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
+    SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+} soc_rtc_fast_clk_src_t;
+
+// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
+// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
+// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
+/**
+ * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
+ *
+ * @note enum starts from 1, to save 0 for special purpose
+ */
+typedef enum {
+    // For CPU domain
+    SOC_MOD_CLK_CPU = 1,                       /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
+    // For RTC domain
+    SOC_MOD_CLK_RTC_FAST,                      /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
+    SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
+    // For digital domain: peripherals, WIFI, BLE
+    SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
+    SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
+    SOC_MOD_CLK_PLL_F240M,                     /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
+    SOC_MOD_CLK_XTAL32K,                       /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
+    SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
+    SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
+    SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
+} soc_module_clk_t;
+
+//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of SYSTIMER clock source
+ */
+typedef enum {
+    SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< SYSTIMER source clock is XTAL */
+    SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
+    SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< SYSTIMER source clock default choice is XTAL */
+} soc_periph_systimer_clk_src_t;
+
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ *
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of GPTimer clock source
+ */
+typedef enum {
+    GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
+    GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
+} soc_periph_gptimer_clk_src_t;
+
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
+typedef enum {
+    TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,     /*!< Timer group clock source is PLL_F80M */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,             /*!< Timer group clock source is XTAL */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,      /*!< Timer group clock source default choice is PLL_F80M */
+} soc_periph_tg_clk_src_legacy_t;
+
+//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of RMT
+ */
+#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of RMT clock source
+ */
+typedef enum {
+    RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
+    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
+    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
+} soc_periph_rmt_clk_src_t;
+
+/**
+ * @brief Type of RMT clock source, reserved for the legacy RMT driver
+ */
+typedef enum {
+    RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
+    RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,         /*!< RMT source clock is XTAL */
+    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< RMT source clock default choice is PLL_F80M */
+} soc_periph_rmt_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Temperature Sensor
+ */
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of Temp Sensor clock source
+ */
+typedef enum {
+    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
+} soc_periph_temperature_sensor_clk_src_t;
+
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock is PLL_F80M */
+    UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST,                /*!< UART source clock is RC_FAST */
+    UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,                  /*!< UART source clock is XTAL */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock default choice is PLL_F80M */
+} soc_periph_uart_clk_src_legacy_t;
+
+//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of MCPWM Timer
+ */
+#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of MCPWM timer clock source
+ */
+typedef enum {
+    MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
+} soc_periph_mcpwm_timer_clk_src_t;
+
+/**
+ * @brief Array initializer for all supported clock sources of MCPWM Capture Timer
+ */
+#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of MCPWM capture clock source
+ */
+typedef enum {
+    MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
+} soc_periph_mcpwm_capture_clk_src_t;
+
+///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of I2S
+ */
+#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief I2S clock source enum
+ */
+typedef enum {
+    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
+    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
+    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
+} soc_periph_i2s_clk_src_t;
+
+/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of I2C
+ */
+#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of I2C clock source.
+ */
+typedef enum {
+    I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
+    I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,                  /*!< Select RC_FAST as the source clock */
+    I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,                     /*!< Select XTAL as the default source clock */
+} soc_periph_i2c_clk_src_t;
+
+
+/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of SPI
+ */
+#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of SPI clock source.
+ */
+typedef enum {
+    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,     /*!< Select PLL_80M as SPI source clock */
+    SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_80M as SPI source clock */
+    SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,            /*!< Select XTAL as SPI source clock */
+    SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,      /*!< Select RC_FAST as SPI source clock */
+} soc_periph_spi_clk_src_t;
+
+//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of SDM
+ */
+#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Sigma Delta Modulator clock source
+ */
+typedef enum {
+    SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
+    SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
+    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
+} soc_periph_sdm_clk_src_t;
+
+//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Glitch Filter
+ */
+#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Glitch filter clock source
+ */
+
+typedef enum {
+    GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
+} soc_periph_glitch_filter_clk_src_t;
+
+//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of TWAI
+ */
+#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief TWAI clock source
+ */
+typedef enum {
+    TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the source clock */
+    TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
+} soc_periph_twai_clk_src_t;
+
+//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of ADC digital controller
+ */
+#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief ADC digital controller clock source
+ */
+typedef enum {
+    ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+    ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,   /*!< Select PLL_F80M as the source clock */
+    ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
+    ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M as the default clock choice */
+} soc_periph_adc_digi_clk_src_t;
+
+//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of MWDT
+ */
+#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief MWDT clock source
+ */
+typedef enum {
+    MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+    MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,   /*!< Select PLL fixed 80 MHz as the source clock */
+    MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RTC fast as the source clock */
+    MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL fixed 80 MHz as the default clock choice */
+} soc_periph_mwdt_clk_src_t;
+
+//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of LEDC
+ */
+#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of LEDC clock source, reserved for the legacy LEDC driver
+ */
+typedef enum {
+    LEDC_AUTO_CLK = 0,                              /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
+    LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M clock as the source clock */
+    LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
+    LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+
+    LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
+} soc_periph_ledc_clk_src_legacy_t;
+
+//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of PARLIO
+ */
+#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
+
+/**
+ * @brief PARLIO clock source
+ */
+typedef enum {
+    PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+    PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
+    PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M,   /*!< Select PLL_F240M as the default clock choice */
+} soc_periph_parlio_clk_src_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..035248b78d
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/clkout_channel.h
@@ -0,0 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+// ESP32C6 CLKOUT signals has no corresponding iomux pins
diff --git a/components/soc/esp32p4/include/soc/dport_access.h b/components/soc/esp32p4/include/soc/dport_access.h
new file mode 100644
index 0000000000..3747073d22
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/dport_access.h
@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _DPORT_ACCESS_H_
+#define _DPORT_ACCESS_H_
+
+#include <stdint.h>
+#include "soc.h"
+#include "uart_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
+
+#define DPORT_INTERRUPT_DISABLE()
+#define DPORT_INTERRUPT_RESTORE()
+
+/**
+ * @brief Read a sequence of DPORT registers to the buffer.
+ *
+ * @param[out] buff_out  Contains the read data.
+ * @param[in]  address   Initial address for reading registers.
+ * @param[in]  num_words The number of words.
+ */
+void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
+
+// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
+#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
+#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
+
+// Write value to DPORT register (does not require protecting)
+#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE((_r), (_v))
+
+#define DPORT_REG_READ(_r)    _DPORT_REG_READ(_r)
+#define DPORT_SEQUENCE_REG_READ(_r)    _DPORT_REG_READ(_r)
+
+//get bit or get bits from register
+#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
+
+//set bit or set bits to register
+#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
+
+//clear bit or clear bits of register
+#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
+
+//set bits of register controlled by mask
+#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
+
+//get field from register, uses field _S & _V to determine mask
+#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
+
+//set field to register, used when _f is not left shifted by _f##_S
+#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
+#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
+#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
+#define _DPORT_REG_SET_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
+#define _DPORT_REG_CLR_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
+
+#define DPORT_READ_PERI_REG(addr)       _DPORT_READ_PERI_REG(addr)
+
+//write value to register
+#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
+
+//clear bits of register controlled by mask
+#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
+
+//set bits of register controlled by mask
+#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
+
+//get bits of register controlled by mask
+#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
+
+//get bits of register controlled by highest bit and lowest bit
+#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
+
+//set bits of register controlled by mask and shift
+#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
+
+//get field of register
+#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DPORT_ACCESS_H_ */
diff --git a/components/soc/esp32p4/include/soc/dspi_mem_reg.h b/components/soc/esp32p4/include/soc/dspi_mem_reg.h
new file mode 100644
index 0000000000..229004612d
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/dspi_mem_reg.h
@@ -0,0 +1,2832 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_DSPI_MEM_REG_H_
+#define _SOC_DSPI_MEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define DSPI_MEM_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x0)
+/* DSPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
+ion will be triggered when the bit is set. The bit will be cleared once the oper
+ation done.1: enable 0: disable..*/
+#define DSPI_MEM_USR    (BIT(18))
+#define DSPI_MEM_USR_M  (BIT(18))
+#define DSPI_MEM_USR_V  0x1
+#define DSPI_MEM_USR_S  18
+/* DSPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
+te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
+ate, 6:write data state, 7: done state, 8: read data end state..*/
+#define DSPI_MEM_SLV_ST    0x0000000F
+#define DSPI_MEM_SLV_ST_M  ((DSPI_MEM_SLV_ST_V)<<(DSPI_MEM_SLV_ST_S))
+#define DSPI_MEM_SLV_ST_V  0xF
+#define DSPI_MEM_SLV_ST_S  4
+/* DSPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
+, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
+nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
+#define DSPI_MEM_MST_ST    0x0000000F
+#define DSPI_MEM_MST_ST_M  ((DSPI_MEM_MST_ST_V)<<(DSPI_MEM_MST_ST_S))
+#define DSPI_MEM_MST_ST_V  0xF
+#define DSPI_MEM_MST_ST_S  0
+
+#define DSPI_MEM_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x8)
+/* DSPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
+lways 1. 0: Others..*/
+#define DSPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define DSPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define DSPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
+#define DSPI_MEM_DATA_IE_ALWAYS_ON_S  31
+/* DSPI_MEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
+s 1. 0: Others..*/
+#define DSPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define DSPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define DSPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
+#define DSPI_MEM_DQS_IE_ALWAYS_ON_S  30
+/* DSPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
+ble 0: disable..*/
+#define DSPI_MEM_FREAD_QIO    (BIT(24))
+#define DSPI_MEM_FREAD_QIO_M  (BIT(24))
+#define DSPI_MEM_FREAD_QIO_V  0x1
+#define DSPI_MEM_FREAD_QIO_S  24
+/* DSPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
+ble 0: disable..*/
+#define DSPI_MEM_FREAD_DIO    (BIT(23))
+#define DSPI_MEM_FREAD_DIO_M  (BIT(23))
+#define DSPI_MEM_FREAD_DIO_V  0x1
+#define DSPI_MEM_FREAD_DIO_S  23
+/* DSPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
+#define DSPI_MEM_WP_REG    (BIT(21))
+#define DSPI_MEM_WP_REG_M  (BIT(21))
+#define DSPI_MEM_WP_REG_V  0x1
+#define DSPI_MEM_WP_REG_S  21
+/* DSPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_FREAD_QUAD    (BIT(20))
+#define DSPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define DSPI_MEM_FREAD_QUAD_V  0x1
+#define DSPI_MEM_FREAD_QUAD_S  20
+/* DSPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
+#define DSPI_MEM_D_POL    (BIT(19))
+#define DSPI_MEM_D_POL_M  (BIT(19))
+#define DSPI_MEM_D_POL_V  0x1
+#define DSPI_MEM_D_POL_S  19
+/* DSPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
+#define DSPI_MEM_Q_POL    (BIT(18))
+#define DSPI_MEM_Q_POL_M  (BIT(18))
+#define DSPI_MEM_Q_POL_V  0x1
+#define DSPI_MEM_Q_POL_S  18
+/* DSPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_FREAD_DUAL    (BIT(14))
+#define DSPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define DSPI_MEM_FREAD_DUAL_V  0x1
+#define DSPI_MEM_FREAD_DUAL_S  14
+/* DSPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
+UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
+#define DSPI_MEM_FASTRD_MODE    (BIT(13))
+#define DSPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define DSPI_MEM_FASTRD_MODE_V  0x1
+#define DSPI_MEM_FASTRD_MODE_S  13
+/* DSPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
+#define DSPI_MEM_FCMD_OCT    (BIT(9))
+#define DSPI_MEM_FCMD_OCT_M  (BIT(9))
+#define DSPI_MEM_FCMD_OCT_V  0x1
+#define DSPI_MEM_FCMD_OCT_S  9
+/* DSPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
+#define DSPI_MEM_FCMD_QUAD    (BIT(8))
+#define DSPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define DSPI_MEM_FCMD_QUAD_V  0x1
+#define DSPI_MEM_FCMD_QUAD_S  8
+/* DSPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
+#define DSPI_MEM_FADDR_OCT    (BIT(6))
+#define DSPI_MEM_FADDR_OCT_M  (BIT(6))
+#define DSPI_MEM_FADDR_OCT_V  0x1
+#define DSPI_MEM_FADDR_OCT_S  6
+/* DSPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
+#define DSPI_MEM_FDIN_OCT    (BIT(5))
+#define DSPI_MEM_FDIN_OCT_M  (BIT(5))
+#define DSPI_MEM_FDIN_OCT_V  0x1
+#define DSPI_MEM_FDIN_OCT_S  5
+/* DSPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
+#define DSPI_MEM_FDOUT_OCT    (BIT(4))
+#define DSPI_MEM_FDOUT_OCT_M  (BIT(4))
+#define DSPI_MEM_FDOUT_OCT_V  0x1
+#define DSPI_MEM_FDOUT_OCT_S  4
+/* DSPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
+is output by the MSPI controller in the second half part of dummy phase. It is u
+sed to pre-drive flash..*/
+#define DSPI_MEM_FDUMMY_WOUT    (BIT(3))
+#define DSPI_MEM_FDUMMY_WOUT_M  (BIT(3))
+#define DSPI_MEM_FDUMMY_WOUT_V  0x1
+#define DSPI_MEM_FDUMMY_WOUT_S  3
+/* DSPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
+s output by the MSPI controller in the first half part of dummy phase. It is use
+d to mask invalid SPI_DQS in the half part of dummy phase..*/
+#define DSPI_MEM_FDUMMY_RIN    (BIT(2))
+#define DSPI_MEM_FDUMMY_RIN_M  (BIT(2))
+#define DSPI_MEM_FDUMMY_RIN_V  0x1
+#define DSPI_MEM_FDUMMY_RIN_S  2
+/* DSPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_IO[7:0] is output by the MSPI controller..*/
+#define DSPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define DSPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
+#define DSPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define DSPI_MEM_WDUMMY_ALWAYS_OUT_S  1
+/* DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_DQS is output by the MSPI controller..*/
+#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
+#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
+
+#define DSPI_MEM_CTRL1_REG          (DR_REG_DSPI_MEM_BASE + 0xC)
+/* DSPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+ send signals to AXI. Set this bit to reset these FIFO..*/
+#define DSPI_MEM_TXFIFO_RST    (BIT(31))
+#define DSPI_MEM_TXFIFO_RST_M  (BIT(31))
+#define DSPI_MEM_TXFIFO_RST_V  0x1
+#define DSPI_MEM_TXFIFO_RST_S  31
+/* DSPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+ receive signals from AXI.  Set this bit to reset these FIFO..*/
+#define DSPI_MEM_RXFIFO_RST    (BIT(30))
+#define DSPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define DSPI_MEM_RXFIFO_RST_V  0x1
+#define DSPI_MEM_RXFIFO_RST_S  30
+/* DSPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
+bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+in  tx_bus_fifo_l2..*/
+#define DSPI_MEM_FAST_WRITE_EN    (BIT(29))
+#define DSPI_MEM_FAST_WRITE_EN_M  (BIT(29))
+#define DSPI_MEM_FAST_WRITE_EN_V  0x1
+#define DSPI_MEM_FAST_WRITE_EN_S  29
+/* DSPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
+the same time..*/
+#define DSPI_MEM_DUAL_RAM_EN    (BIT(28))
+#define DSPI_MEM_DUAL_RAM_EN_M  (BIT(28))
+#define DSPI_MEM_DUAL_RAM_EN_V  0x1
+#define DSPI_MEM_DUAL_RAM_EN_S  28
+/* DSPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
+cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
+ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
+cessed at the same time..*/
+#define DSPI_MEM_RAM0_EN    (BIT(27))
+#define DSPI_MEM_RAM0_EN_M  (BIT(27))
+#define DSPI_MEM_RAM0_EN_V  0x1
+#define DSPI_MEM_RAM0_EN_S  27
+/* DSPI_MEM_AW_SPLICE_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Write Splice-transfer..*/
+#define DSPI_MEM_AW_SPLICE_EN    (BIT(26))
+#define DSPI_MEM_AW_SPLICE_EN_M  (BIT(26))
+#define DSPI_MEM_AW_SPLICE_EN_V  0x1
+#define DSPI_MEM_AW_SPLICE_EN_S  26
+/* DSPI_MEM_AR_SPLICE_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Read Splice-transfer..*/
+#define DSPI_MEM_AR_SPLICE_EN    (BIT(25))
+#define DSPI_MEM_AR_SPLICE_EN_M  (BIT(25))
+#define DSPI_MEM_AR_SPLICE_EN_V  0x1
+#define DSPI_MEM_AR_SPLICE_EN_S  25
+/* DSPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+ when there is a ECC error in AXI read data. The ECC error information is record
+ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
+#define DSPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
+#define DSPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
+#define DSPI_MEM_RRESP_ECC_ERR_EN_V  0x1
+#define DSPI_MEM_RRESP_ECC_ERR_EN_S  24
+/* DSPI_MEM_SPI_AXI_RDATA_BACK_FAST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
+eply AXI read data to AXI bus when all the read data is available..*/
+#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST    (BIT(23))
+#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_M  (BIT(23))
+#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_V  0x1
+#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_S  23
+/* DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
+#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
+#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V  0x1
+#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S  22
+/* DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
+y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
+#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
+#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V  0x1
+#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S  21
+/* DSPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is alwasy on..*/
+#define DSPI_MEM_CLK_MODE    0x00000003
+#define DSPI_MEM_CLK_MODE_M  ((DSPI_MEM_CLK_MODE_V)<<(DSPI_MEM_CLK_MODE_S))
+#define DSPI_MEM_CLK_MODE_V  0x3
+#define DSPI_MEM_CLK_MODE_S  0
+
+#define DSPI_MEM_CTRL2_REG          (DR_REG_DSPI_MEM_BASE + 0x10)
+/* DSPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
+#define DSPI_MEM_SYNC_RESET    (BIT(31))
+#define DSPI_MEM_SYNC_RESET_M  (BIT(31))
+#define DSPI_MEM_SYNC_RESET_V  0x1
+#define DSPI_MEM_SYNC_RESET_S  31
+/* DSPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
+ clock cycles..*/
+#define DSPI_MEM_CS_HOLD_DELAY    0x0000003F
+#define DSPI_MEM_CS_HOLD_DELAY_M  ((DSPI_MEM_CS_HOLD_DELAY_V)<<(DSPI_MEM_CS_HOLD_DELAY_S))
+#define DSPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define DSPI_MEM_CS_HOLD_DELAY_S  25
+/* DSPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
+fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
+whether there is an ECC region or not..*/
+#define DSPI_MEM_SPLIT_TRANS_EN    (BIT(24))
+#define DSPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
+#define DSPI_MEM_SPLIT_TRANS_EN_V  0x1
+#define DSPI_MEM_SPLIT_TRANS_EN_S  24
+/* DSPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
+n accesses flash..*/
+#define DSPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
+#define DSPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
+#define DSPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
+#define DSPI_MEM_ECC_16TO18_BYTE_EN_S  14
+/* DSPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
+hen accesses flash..*/
+#define DSPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
+#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
+/* DSPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+ mode when accessed flash..*/
+#define DSPI_MEM_ECC_CS_HOLD_TIME    0x00000007
+#define DSPI_MEM_ECC_CS_HOLD_TIME_M  ((DSPI_MEM_ECC_CS_HOLD_TIME_V)<<(DSPI_MEM_ECC_CS_HOLD_TIME_S))
+#define DSPI_MEM_ECC_CS_HOLD_TIME_V  0x7
+#define DSPI_MEM_ECC_CS_HOLD_TIME_S  10
+/* DSPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
+th SPI_MEM_CS_HOLD bit..*/
+#define DSPI_MEM_CS_HOLD_TIME    0x0000001F
+#define DSPI_MEM_CS_HOLD_TIME_M  ((DSPI_MEM_CS_HOLD_TIME_V)<<(DSPI_MEM_CS_HOLD_TIME_S))
+#define DSPI_MEM_CS_HOLD_TIME_V  0x1F
+#define DSPI_MEM_CS_HOLD_TIME_S  5
+/* DSPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
+M_CS_SETUP bit..*/
+#define DSPI_MEM_CS_SETUP_TIME    0x0000001F
+#define DSPI_MEM_CS_SETUP_TIME_M  ((DSPI_MEM_CS_SETUP_TIME_V)<<(DSPI_MEM_CS_SETUP_TIME_S))
+#define DSPI_MEM_CS_SETUP_TIME_V  0x1F
+#define DSPI_MEM_CS_SETUP_TIME_S  0
+
+#define DSPI_MEM_CLOCK_REG          (DR_REG_DSPI_MEM_BASE + 0x14)
+/* DSPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+ clock..*/
+#define DSPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
+#define DSPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define DSPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define DSPI_MEM_CLK_EQU_SYSCLK_S  31
+/* DSPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ system/(spi_mem_clkcnt_N+1).*/
+#define DSPI_MEM_CLKCNT_N    0x000000FF
+#define DSPI_MEM_CLKCNT_N_M  ((DSPI_MEM_CLKCNT_N_V)<<(DSPI_MEM_CLKCNT_N_S))
+#define DSPI_MEM_CLKCNT_N_V  0xFF
+#define DSPI_MEM_CLKCNT_N_S  16
+/* DSPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define DSPI_MEM_CLKCNT_H    0x000000FF
+#define DSPI_MEM_CLKCNT_H_M  ((DSPI_MEM_CLKCNT_H_V)<<(DSPI_MEM_CLKCNT_H_S))
+#define DSPI_MEM_CLKCNT_H_V  0xFF
+#define DSPI_MEM_CLKCNT_H_S  8
+/* DSPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
+#define DSPI_MEM_CLKCNT_L    0x000000FF
+#define DSPI_MEM_CLKCNT_L_M  ((DSPI_MEM_CLKCNT_L_V)<<(DSPI_MEM_CLKCNT_L_S))
+#define DSPI_MEM_CLKCNT_L_V  0xFF
+#define DSPI_MEM_CLKCNT_L_S  0
+
+#define DSPI_MEM_USER_REG          (DR_REG_DSPI_MEM_BASE + 0x18)
+/* DSPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation..*/
+#define DSPI_MEM_USR_DUMMY    (BIT(29))
+#define DSPI_MEM_USR_DUMMY_M  (BIT(29))
+#define DSPI_MEM_USR_DUMMY_V  0x1
+#define DSPI_MEM_USR_DUMMY_S  29
+/* DSPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable..*/
+#define DSPI_MEM_USR_DUMMY_IDLE    (BIT(26))
+#define DSPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define DSPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define DSPI_MEM_USR_DUMMY_IDLE_S  26
+/* DSPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
+#define DSPI_MEM_CK_OUT_EDGE    (BIT(9))
+#define DSPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define DSPI_MEM_CK_OUT_EDGE_V  0x1
+#define DSPI_MEM_CK_OUT_EDGE_S  9
+/* DSPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
+#define DSPI_MEM_CS_SETUP    (BIT(7))
+#define DSPI_MEM_CS_SETUP_M  (BIT(7))
+#define DSPI_MEM_CS_SETUP_V  0x1
+#define DSPI_MEM_CS_SETUP_S  7
+/* DSPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
+#define DSPI_MEM_CS_HOLD    (BIT(6))
+#define DSPI_MEM_CS_HOLD_M  (BIT(6))
+#define DSPI_MEM_CS_HOLD_V  0x1
+#define DSPI_MEM_CS_HOLD_S  6
+
+#define DSPI_MEM_USER1_REG          (DR_REG_DSPI_MEM_BASE + 0x1C)
+/* DSPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
+#define DSPI_MEM_USR_ADDR_BITLEN    0x0000003F
+#define DSPI_MEM_USR_ADDR_BITLEN_M  ((DSPI_MEM_USR_ADDR_BITLEN_V)<<(DSPI_MEM_USR_ADDR_BITLEN_S))
+#define DSPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define DSPI_MEM_USR_ADDR_BITLEN_S  26
+/* DSPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
+/*description: SPI0 USR_CMD read or write data byte length -1.*/
+#define DSPI_MEM_USR_DBYTELEN    0x00000007
+#define DSPI_MEM_USR_DBYTELEN_M  ((DSPI_MEM_USR_DBYTELEN_V)<<(DSPI_MEM_USR_DBYTELEN_S))
+#define DSPI_MEM_USR_DBYTELEN_V  0x7
+#define DSPI_MEM_USR_DBYTELEN_S  6
+/* DSPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
+cle_num-1)..*/
+#define DSPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
+#define DSPI_MEM_USR_DUMMY_CYCLELEN_M  ((DSPI_MEM_USR_DUMMY_CYCLELEN_V)<<(DSPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define DSPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define DSPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define DSPI_MEM_USER2_REG          (DR_REG_DSPI_MEM_BASE + 0x20)
+/* DSPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
+#define DSPI_MEM_USR_COMMAND_BITLEN    0x0000000F
+#define DSPI_MEM_USR_COMMAND_BITLEN_M  ((DSPI_MEM_USR_COMMAND_BITLEN_V)<<(DSPI_MEM_USR_COMMAND_BITLEN_S))
+#define DSPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define DSPI_MEM_USR_COMMAND_BITLEN_S  28
+/* DSPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command..*/
+#define DSPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
+#define DSPI_MEM_USR_COMMAND_VALUE_M  ((DSPI_MEM_USR_COMMAND_VALUE_V)<<(DSPI_MEM_USR_COMMAND_VALUE_S))
+#define DSPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define DSPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define DSPI_MEM_RD_STATUS_REG          (DR_REG_DSPI_MEM_BASE + 0x2C)
+/* DSPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
+it..*/
+#define DSPI_MEM_WB_MODE    0x000000FF
+#define DSPI_MEM_WB_MODE_M  ((DSPI_MEM_WB_MODE_V)<<(DSPI_MEM_WB_MODE_S))
+#define DSPI_MEM_WB_MODE_V  0xFF
+#define DSPI_MEM_WB_MODE_S  16
+
+#define DSPI_MEM_MISC_REG          (DR_REG_DSPI_MEM_BASE + 0x34)
+/* DSPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: SPI_CS line keep low when the bit is set..*/
+#define DSPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
+#define DSPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define DSPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define DSPI_MEM_CS_KEEP_ACTIVE_S  10
+/* DSPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
+#define DSPI_MEM_CK_IDLE_EDGE    (BIT(9))
+#define DSPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define DSPI_MEM_CK_IDLE_EDGE_V  0x1
+#define DSPI_MEM_CK_IDLE_EDGE_S  9
+/* DSPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0,  sram is connected to SUBPINs..*/
+#define DSPI_MEM_SSUB_PIN    (BIT(8))
+#define DSPI_MEM_SSUB_PIN_M  (BIT(8))
+#define DSPI_MEM_SSUB_PIN_V  0x1
+#define DSPI_MEM_SSUB_PIN_S  8
+/* DSPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0,  flash is connected to SUBPINs..*/
+#define DSPI_MEM_FSUB_PIN    (BIT(7))
+#define DSPI_MEM_FSUB_PIN_M  (BIT(7))
+#define DSPI_MEM_FSUB_PIN_V  0x1
+#define DSPI_MEM_FSUB_PIN_S  7
+
+#define DSPI_MEM_CACHE_FCTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x3C)
+/* DSPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
+_ERR will be replied to BRESP/RRESP..*/
+#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN    (BIT(31))
+#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_M  (BIT(31))
+#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_V  0x1
+#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_S  31
+/* DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: Set this bit to check AXI read/write the same address region..*/
+#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
+#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x1
+#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
+/* DSPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_qio..*/
+#define DSPI_MEM_FADDR_QUAD    (BIT(8))
+#define DSPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define DSPI_MEM_FADDR_QUAD_V  0x1
+#define DSPI_MEM_FADDR_QUAD_S  8
+/* DSPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
+e same with spi_mem_fread_qio..*/
+#define DSPI_MEM_FDOUT_QUAD    (BIT(7))
+#define DSPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define DSPI_MEM_FDOUT_QUAD_V  0x1
+#define DSPI_MEM_FDOUT_QUAD_S  7
+/* DSPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ same with spi_mem_fread_qio..*/
+#define DSPI_MEM_FDIN_QUAD    (BIT(6))
+#define DSPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define DSPI_MEM_FDIN_QUAD_V  0x1
+#define DSPI_MEM_FDIN_QUAD_S  6
+/* DSPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_dio..*/
+#define DSPI_MEM_FADDR_DUAL    (BIT(5))
+#define DSPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define DSPI_MEM_FADDR_DUAL_V  0x1
+#define DSPI_MEM_FADDR_DUAL_S  5
+/* DSPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+ same with spi_mem_fread_dio..*/
+#define DSPI_MEM_FDOUT_DUAL    (BIT(4))
+#define DSPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define DSPI_MEM_FDOUT_DUAL_V  0x1
+#define DSPI_MEM_FDOUT_DUAL_S  4
+/* DSPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+same with spi_mem_fread_dio..*/
+#define DSPI_MEM_FDIN_DUAL    (BIT(3))
+#define DSPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define DSPI_MEM_FDIN_DUAL_V  0x1
+#define DSPI_MEM_FDIN_DUAL_S  3
+/* DSPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
+#define DSPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
+#define DSPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define DSPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define DSPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* DSPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
+#define DSPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* DSPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
+#define DSPI_MEM_AXI_REQ_EN    (BIT(0))
+#define DSPI_MEM_AXI_REQ_EN_M  (BIT(0))
+#define DSPI_MEM_AXI_REQ_EN_V  0x1
+#define DSPI_MEM_AXI_REQ_EN_S  0
+
+#define DSPI_MEM_CACHE_SCTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x40)
+/* DSPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
+e. The register value shall be (bit_num-1)..*/
+#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
+#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
+#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
+#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
+/* DSPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: reserved.*/
+#define DSPI_MEM_SRAM_OCT    (BIT(21))
+#define DSPI_MEM_SRAM_OCT_M  (BIT(21))
+#define DSPI_MEM_SRAM_OCT_V  0x1
+#define DSPI_MEM_SRAM_OCT_S  21
+/* DSPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
+#define DSPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
+#define DSPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
+#define DSPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
+#define DSPI_MEM_CACHE_SRAM_USR_WCMD_S  20
+/* DSPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
+he register value shall be (bit_num-1)..*/
+#define DSPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
+#define DSPI_MEM_SRAM_ADDR_BITLEN_M  ((DSPI_MEM_SRAM_ADDR_BITLEN_V)<<(DSPI_MEM_SRAM_ADDR_BITLEN_S))
+#define DSPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
+#define DSPI_MEM_SRAM_ADDR_BITLEN_S  14
+/* DSPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
+. The register value shall be (bit_num-1)..*/
+#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
+#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
+#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
+#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
+/* DSPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
+nd..*/
+#define DSPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
+#define DSPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
+#define DSPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
+#define DSPI_MEM_CACHE_SRAM_USR_RCMD_S  5
+/* DSPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
+ operations..*/
+#define DSPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
+#define DSPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
+#define DSPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
+#define DSPI_MEM_USR_RD_SRAM_DUMMY_S  4
+/* DSPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
+e operations..*/
+#define DSPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
+#define DSPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
+#define DSPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
+#define DSPI_MEM_USR_WR_SRAM_DUMMY_S  3
+/* DSPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
+le.*/
+#define DSPI_MEM_USR_SRAM_QIO    (BIT(2))
+#define DSPI_MEM_USR_SRAM_QIO_M  (BIT(2))
+#define DSPI_MEM_USR_SRAM_QIO_V  0x1
+#define DSPI_MEM_USR_SRAM_QIO_S  2
+/* DSPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
+le.*/
+#define DSPI_MEM_USR_SRAM_DIO    (BIT(1))
+#define DSPI_MEM_USR_SRAM_DIO_M  (BIT(1))
+#define DSPI_MEM_USR_SRAM_DIO_V  0x1
+#define DSPI_MEM_USR_SRAM_DIO_S  1
+/* DSPI_MEM_CACHE_USR_SADDR_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
+able, 0:disable..*/
+#define DSPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
+#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
+#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
+#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
+
+#define DSPI_MEM_SRAM_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x44)
+/* DSPI_SMEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
+] are always 1. 0: Others..*/
+#define DSPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define DSPI_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define DSPI_SMEM_DATA_IE_ALWAYS_ON_V  0x1
+#define DSPI_SMEM_DATA_IE_ALWAYS_ON_S  31
+/* DSPI_SMEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
+e always 1. 0: Others..*/
+#define DSPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define DSPI_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define DSPI_SMEM_DQS_IE_ALWAYS_ON_V  0x1
+#define DSPI_SMEM_DQS_IE_ALWAYS_ON_S  30
+/* DSPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_SDOUT_HEX    (BIT(27))
+#define DSPI_MEM_SDOUT_HEX_M  (BIT(27))
+#define DSPI_MEM_SDOUT_HEX_V  0x1
+#define DSPI_MEM_SDOUT_HEX_S  27
+/* DSPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_SDIN_HEX    (BIT(26))
+#define DSPI_MEM_SDIN_HEX_M  (BIT(26))
+#define DSPI_MEM_SDIN_HEX_V  0x1
+#define DSPI_MEM_SDIN_HEX_S  26
+/* DSPI_SMEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_IO[7:0] is output by the MSPI controller..*/
+#define DSPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
+#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/* DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_DQS is output by the MSPI controller..*/
+#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
+#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/* DSPI_MEM_SDUMMY_WOUT : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
+the signal level of SPI bus is output by the MSPI controller..*/
+#define DSPI_MEM_SDUMMY_WOUT    (BIT(23))
+#define DSPI_MEM_SDUMMY_WOUT_M  (BIT(23))
+#define DSPI_MEM_SDUMMY_WOUT_V  0x1
+#define DSPI_MEM_SDUMMY_WOUT_S  23
+/* DSPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
+he signal level of SPI bus is output by the MSPI controller..*/
+#define DSPI_MEM_SDUMMY_RIN    (BIT(22))
+#define DSPI_MEM_SDUMMY_RIN_M  (BIT(22))
+#define DSPI_MEM_SDUMMY_RIN_V  0x1
+#define DSPI_MEM_SDUMMY_RIN_S  22
+/* DSPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_SCMD_OCT    (BIT(21))
+#define DSPI_MEM_SCMD_OCT_M  (BIT(21))
+#define DSPI_MEM_SCMD_OCT_V  0x1
+#define DSPI_MEM_SCMD_OCT_S  21
+/* DSPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_SADDR_OCT    (BIT(20))
+#define DSPI_MEM_SADDR_OCT_M  (BIT(20))
+#define DSPI_MEM_SADDR_OCT_V  0x1
+#define DSPI_MEM_SADDR_OCT_S  20
+/* DSPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_SDOUT_OCT    (BIT(19))
+#define DSPI_MEM_SDOUT_OCT_M  (BIT(19))
+#define DSPI_MEM_SDOUT_OCT_V  0x1
+#define DSPI_MEM_SDOUT_OCT_S  19
+/* DSPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
+#define DSPI_MEM_SDIN_OCT    (BIT(18))
+#define DSPI_MEM_SDIN_OCT_M  (BIT(18))
+#define DSPI_MEM_SDIN_OCT_V  0x1
+#define DSPI_MEM_SDIN_OCT_S  18
+/* DSPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define DSPI_MEM_SCMD_QUAD    (BIT(17))
+#define DSPI_MEM_SCMD_QUAD_M  (BIT(17))
+#define DSPI_MEM_SCMD_QUAD_V  0x1
+#define DSPI_MEM_SCMD_QUAD_S  17
+/* DSPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_qio..*/
+#define DSPI_MEM_SADDR_QUAD    (BIT(16))
+#define DSPI_MEM_SADDR_QUAD_M  (BIT(16))
+#define DSPI_MEM_SADDR_QUAD_V  0x1
+#define DSPI_MEM_SADDR_QUAD_S  16
+/* DSPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_qio..*/
+#define DSPI_MEM_SDOUT_QUAD    (BIT(15))
+#define DSPI_MEM_SDOUT_QUAD_M  (BIT(15))
+#define DSPI_MEM_SDOUT_QUAD_V  0x1
+#define DSPI_MEM_SDOUT_QUAD_S  15
+/* DSPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define DSPI_MEM_SDIN_QUAD    (BIT(14))
+#define DSPI_MEM_SDIN_QUAD_M  (BIT(14))
+#define DSPI_MEM_SDIN_QUAD_V  0x1
+#define DSPI_MEM_SDIN_QUAD_S  14
+/* DSPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_dio..*/
+#define DSPI_MEM_SADDR_DUAL    (BIT(12))
+#define DSPI_MEM_SADDR_DUAL_M  (BIT(12))
+#define DSPI_MEM_SADDR_DUAL_V  0x1
+#define DSPI_MEM_SADDR_DUAL_S  12
+/* DSPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_dio..*/
+#define DSPI_MEM_SDOUT_DUAL    (BIT(11))
+#define DSPI_MEM_SDOUT_DUAL_M  (BIT(11))
+#define DSPI_MEM_SDOUT_DUAL_V  0x1
+#define DSPI_MEM_SDOUT_DUAL_S  11
+/* DSPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_dio..*/
+#define DSPI_MEM_SDIN_DUAL    (BIT(10))
+#define DSPI_MEM_SDIN_DUAL_M  (BIT(10))
+#define DSPI_MEM_SDIN_DUAL_V  0x1
+#define DSPI_MEM_SDIN_DUAL_S  10
+/* DSPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
+/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
+_mode bit..*/
+#define DSPI_MEM_SWB_MODE    0x000000FF
+#define DSPI_MEM_SWB_MODE_M  ((DSPI_MEM_SWB_MODE_V)<<(DSPI_MEM_SWB_MODE_S))
+#define DSPI_MEM_SWB_MODE_V  0xFF
+#define DSPI_MEM_SWB_MODE_S  2
+/* DSPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on..*/
+#define DSPI_MEM_SCLK_MODE    0x00000003
+#define DSPI_MEM_SCLK_MODE_M  ((DSPI_MEM_SCLK_MODE_V)<<(DSPI_MEM_SCLK_MODE_S))
+#define DSPI_MEM_SCLK_MODE_V  0x3
+#define DSPI_MEM_SCLK_MODE_S  0
+
+#define DSPI_MEM_SRAM_DRD_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x48)
+/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
+ sram. The register value shall be (bit_num-1)..*/
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
+/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the read command value of command phase
+ for sram..*/
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
+#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
+
+#define DSPI_MEM_SRAM_DWR_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x4C)
+/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
+ The register value shall be (bit_num-1)..*/
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
+/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the write command value of command phas
+e for sram..*/
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
+#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
+
+#define DSPI_MEM_SRAM_CLK_REG          (DR_REG_DSPI_MEM_BASE + 0x50)
+/* DSPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
+lk is divided from system clock..*/
+#define DSPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
+#define DSPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
+#define DSPI_MEM_SCLK_EQU_SYSCLK_V  0x1
+#define DSPI_MEM_SCLK_EQU_SYSCLK_S  31
+/* DSPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
+lk frequency is system/(spi_mem_clkcnt_N+1).*/
+#define DSPI_MEM_SCLKCNT_N    0x000000FF
+#define DSPI_MEM_SCLKCNT_N_M  ((DSPI_MEM_SCLKCNT_N_V)<<(DSPI_MEM_SCLKCNT_N_S))
+#define DSPI_MEM_SCLKCNT_N_V  0xFF
+#define DSPI_MEM_SCLKCNT_N_S  16
+/* DSPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define DSPI_MEM_SCLKCNT_H    0x000000FF
+#define DSPI_MEM_SCLKCNT_H_M  ((DSPI_MEM_SCLKCNT_H_V)<<(DSPI_MEM_SCLKCNT_H_S))
+#define DSPI_MEM_SCLKCNT_H_V  0xFF
+#define DSPI_MEM_SCLKCNT_H_S  8
+/* DSPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
+#define DSPI_MEM_SCLKCNT_L    0x000000FF
+#define DSPI_MEM_SCLKCNT_L_M  ((DSPI_MEM_SCLKCNT_L_V)<<(DSPI_MEM_SCLKCNT_L_S))
+#define DSPI_MEM_SCLKCNT_L_V  0xFF
+#define DSPI_MEM_SCLKCNT_L_S  0
+
+#define DSPI_MEM_FSM_REG          (DR_REG_DSPI_MEM_BASE + 0x54)
+/* DSPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
+#define DSPI_MEM_LOCK_DELAY_TIME    0x0000001F
+#define DSPI_MEM_LOCK_DELAY_TIME_M  ((DSPI_MEM_LOCK_DELAY_TIME_V)<<(DSPI_MEM_LOCK_DELAY_TIME_S))
+#define DSPI_MEM_LOCK_DELAY_TIME_V  0x1F
+#define DSPI_MEM_LOCK_DELAY_TIME_S  7
+
+#define DSPI_MEM_INT_ENA_REG          (DR_REG_DSPI_MEM_BASE + 0xC0)
+/* DSPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA    (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_M  (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_V  0x1
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_S  31
+/* DSPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA    (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_M  (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_V  0x1
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_S  30
+/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA    (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M  (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V  0x1
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S  29
+/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA    (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M  (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V  0x1
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S  28
+/* DSPI_MEM_AXI_WADDR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA    (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_M  (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_V  0x1
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_S  9
+/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/* DSPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
+/* DSPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define DSPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_ENA_V  0x1
+#define DSPI_MEM_PMS_REJECT_INT_ENA_S  6
+/* DSPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define DSPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_ENA_V  0x1
+#define DSPI_MEM_ECC_ERR_INT_ENA_S  5
+/* DSPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define DSPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define DSPI_MEM_MST_ST_END_INT_ENA_S  4
+/* DSPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define DSPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define DSPI_MEM_SLV_ST_END_INT_ENA_S  3
+
+#define DSPI_MEM_INT_CLR_REG          (DR_REG_DSPI_MEM_BASE + 0xC4)
+/* DSPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR    (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_M  (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_V  0x1
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_S  31
+/* DSPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR    (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_M  (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_V  0x1
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_S  30
+/* DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR    (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M  (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V  0x1
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S  29
+/* DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR    (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M  (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V  0x1
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S  28
+/* DSPI_MEM_AXI_WADDR_ERR_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
+#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
+/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/* DSPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
+#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
+/* DSPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define DSPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_CLR_V  0x1
+#define DSPI_MEM_PMS_REJECT_INT_CLR_S  6
+/* DSPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define DSPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_CLR_V  0x1
+#define DSPI_MEM_ECC_ERR_INT_CLR_S  5
+/* DSPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define DSPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define DSPI_MEM_MST_ST_END_INT_CLR_S  4
+/* DSPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define DSPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define DSPI_MEM_SLV_ST_END_INT_CLR_S  3
+
+#define DSPI_MEM_INT_RAW_REG          (DR_REG_DSPI_MEM_BASE + 0xC8)
+/* DSPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO
+ is underflow..*/
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW    (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_M  (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_V  0x1
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_S  31
+/* DSPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO
+ is underflow..*/
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW    (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_M  (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_V  0x1
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_S  30
+/* DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
+O connected to SPI_DQS is overflow..*/
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW    (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M  (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V  0x1
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S  29
+/* DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
+O connected to SPI_DQS1 is overflow..*/
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW    (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M  (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V  0x1
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S  28
+/* DSPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+ address is invalid by compared to MMU configuration. 0: Others..*/
+#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
+#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
+/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
+ite flash request is received. 0: Others..*/
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/* DSPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+address is invalid by compared to MMU configuration. 0: Others..*/
+#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
+#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
+/* DSPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
+is rejected. 0: Others..*/
+#define DSPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_RAW_V  0x1
+#define DSPI_MEM_PMS_REJECT_INT_RAW_S  6
+/* DSPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
+et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
+ times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
+. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
+his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
+ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
+I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
+RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
+d, this bit will not be triggered..*/
+#define DSPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_RAW_V  0x1
+#define DSPI_MEM_ECC_ERR_INT_RAW_S  5
+/* DSPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
+is changed from non idle state to idle state. 0: Others..*/
+#define DSPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define DSPI_MEM_MST_ST_END_INT_RAW_S  4
+/* DSPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
+is changed from non idle state to idle state. It means that SPI_CS raises high.
+0: Others.*/
+#define DSPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define DSPI_MEM_SLV_ST_END_INT_RAW_S  3
+
+#define DSPI_MEM_INT_ST_REG          (DR_REG_DSPI_MEM_BASE + 0xCC)
+/* DSPI_MEM_BUS_FIFO0_UDF_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST    (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_M  (BIT(31))
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_V  0x1
+#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_S  31
+/* DSPI_MEM_BUS_FIFO1_UDF_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST    (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_M  (BIT(30))
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_V  0x1
+#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_S  30
+/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST    (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_M  (BIT(29))
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_V  0x1
+#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_S  29
+/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST    (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_M  (BIT(28))
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_V  0x1
+#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_S  28
+/* DSPI_MEM_AXI_WADDR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
+#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
+/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
+#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
+/* DSPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
+#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
+/* DSPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define DSPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
+#define DSPI_MEM_PMS_REJECT_INT_ST_V  0x1
+#define DSPI_MEM_PMS_REJECT_INT_ST_S  6
+/* DSPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define DSPI_MEM_ECC_ERR_INT_ST    (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
+#define DSPI_MEM_ECC_ERR_INT_ST_V  0x1
+#define DSPI_MEM_ECC_ERR_INT_ST_S  5
+/* DSPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define DSPI_MEM_MST_ST_END_INT_ST    (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define DSPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define DSPI_MEM_MST_ST_END_INT_ST_S  4
+/* DSPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define DSPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define DSPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define DSPI_MEM_SLV_ST_END_INT_ST_S  3
+
+#define DSPI_MEM_DDR_REG          (DR_REG_DSPI_MEM_BASE + 0xD4)
+/* DSPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
+#define DSPI_FMEM_HYPERBUS_CA    (BIT(30))
+#define DSPI_FMEM_HYPERBUS_CA_M  (BIT(30))
+#define DSPI_FMEM_HYPERBUS_CA_V  0x1
+#define DSPI_FMEM_HYPERBUS_CA_S  30
+/* DSPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
+..*/
+#define DSPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define DSPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define DSPI_FMEM_OCTA_RAM_ADDR_V  0x1
+#define DSPI_FMEM_OCTA_RAM_ADDR_S  29
+/* DSPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
+#define DSPI_FMEM_CLK_DIFF_INV    (BIT(28))
+#define DSPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
+#define DSPI_FMEM_CLK_DIFF_INV_V  0x1
+#define DSPI_FMEM_CLK_DIFF_INV_S  28
+/* DSPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define DSPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define DSPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define DSPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define DSPI_FMEM_HYPERBUS_DUMMY_2X_S  27
+/* DSPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define DSPI_FMEM_DQS_CA_IN    (BIT(26))
+#define DSPI_FMEM_DQS_CA_IN_M  (BIT(26))
+#define DSPI_FMEM_DQS_CA_IN_V  0x1
+#define DSPI_FMEM_DQS_CA_IN_S  26
+/* DSPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define DSPI_FMEM_CLK_DIFF_EN    (BIT(24))
+#define DSPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
+#define DSPI_FMEM_CLK_DIFF_EN_V  0x1
+#define DSPI_FMEM_CLK_DIFF_EN_S  24
+/* DSPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define DSPI_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define DSPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define DSPI_FMEM_DDR_DQS_LOOP_V  0x1
+#define DSPI_FMEM_DDR_DQS_LOOP_S  21
+/* DSPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define DSPI_FMEM_USR_DDR_DQS_THD    0x0000007F
+#define DSPI_FMEM_USR_DDR_DQS_THD_M  ((DSPI_FMEM_USR_DDR_DQS_THD_V)<<(DSPI_FMEM_USR_DDR_DQS_THD_S))
+#define DSPI_FMEM_USR_DDR_DQS_THD_V  0x7F
+#define DSPI_FMEM_USR_DDR_DQS_THD_S  14
+/* DSPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to flash..*/
+#define DSPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
+#define DSPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define DSPI_FMEM_RX_DDR_MSK_EN_V  0x1
+#define DSPI_FMEM_RX_DDR_MSK_EN_S  13
+/* DSPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to flash..*/
+#define DSPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
+#define DSPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define DSPI_FMEM_TX_DDR_MSK_EN_V  0x1
+#define DSPI_FMEM_TX_DDR_MSK_EN_S  12
+/* DSPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the panda device..*/
+#define DSPI_FMEM_OUTMINBYTELEN    0x0000007F
+#define DSPI_FMEM_OUTMINBYTELEN_M  ((DSPI_FMEM_OUTMINBYTELEN_V)<<(DSPI_FMEM_OUTMINBYTELEN_S))
+#define DSPI_FMEM_OUTMINBYTELEN_V  0x7F
+#define DSPI_FMEM_OUTMINBYTELEN_S  5
+/* DSPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define DSPI_FMEM_DDR_CMD_DIS    (BIT(4))
+#define DSPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
+#define DSPI_FMEM_DDR_CMD_DIS_V  0x1
+#define DSPI_FMEM_DDR_CMD_DIS_S  4
+/* DSPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define DSPI_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define DSPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define DSPI_FMEM_DDR_WDAT_SWP_V  0x1
+#define DSPI_FMEM_DDR_WDAT_SWP_S  3
+/* DSPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define DSPI_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define DSPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define DSPI_FMEM_DDR_RDAT_SWP_V  0x1
+#define DSPI_FMEM_DDR_RDAT_SWP_S  2
+/* DSPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define DSPI_FMEM_VAR_DUMMY    (BIT(1))
+#define DSPI_FMEM_VAR_DUMMY_M  (BIT(1))
+#define DSPI_FMEM_VAR_DUMMY_V  0x1
+#define DSPI_FMEM_VAR_DUMMY_S  1
+/* DSPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define DSPI_FMEM_DDR_EN    (BIT(0))
+#define DSPI_FMEM_DDR_EN_M  (BIT(0))
+#define DSPI_FMEM_DDR_EN_V  0x1
+#define DSPI_FMEM_DDR_EN_S  0
+
+#define DSPI_SMEM_DDR_REG          (DR_REG_DSPI_MEM_BASE + 0xD8)
+/* DSPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
+]}..*/
+#define DSPI_SMEM_HYPERBUS_CA    (BIT(30))
+#define DSPI_SMEM_HYPERBUS_CA_M  (BIT(30))
+#define DSPI_SMEM_HYPERBUS_CA_V  0x1
+#define DSPI_SMEM_HYPERBUS_CA_S  30
+/* DSPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
+, 1'b0}..*/
+#define DSPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define DSPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define DSPI_SMEM_OCTA_RAM_ADDR_V  0x1
+#define DSPI_SMEM_OCTA_RAM_ADDR_S  29
+/* DSPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
+#define DSPI_SMEM_CLK_DIFF_INV    (BIT(28))
+#define DSPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
+#define DSPI_SMEM_CLK_DIFF_INV_V  0x1
+#define DSPI_SMEM_CLK_DIFF_INV_S  28
+/* DSPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define DSPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define DSPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define DSPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define DSPI_SMEM_HYPERBUS_DUMMY_2X_S  27
+/* DSPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define DSPI_SMEM_DQS_CA_IN    (BIT(26))
+#define DSPI_SMEM_DQS_CA_IN_M  (BIT(26))
+#define DSPI_SMEM_DQS_CA_IN_V  0x1
+#define DSPI_SMEM_DQS_CA_IN_S  26
+/* DSPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define DSPI_SMEM_CLK_DIFF_EN    (BIT(24))
+#define DSPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
+#define DSPI_SMEM_CLK_DIFF_EN_V  0x1
+#define DSPI_SMEM_CLK_DIFF_EN_S  24
+/* DSPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define DSPI_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define DSPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define DSPI_SMEM_DDR_DQS_LOOP_V  0x1
+#define DSPI_SMEM_DDR_DQS_LOOP_S  21
+/* DSPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define DSPI_SMEM_USR_DDR_DQS_THD    0x0000007F
+#define DSPI_SMEM_USR_DDR_DQS_THD_M  ((DSPI_SMEM_USR_DDR_DQS_THD_V)<<(DSPI_SMEM_USR_DDR_DQS_THD_S))
+#define DSPI_SMEM_USR_DDR_DQS_THD_V  0x7F
+#define DSPI_SMEM_USR_DDR_DQS_THD_S  14
+/* DSPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to external RAM..*/
+#define DSPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define DSPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define DSPI_SMEM_RX_DDR_MSK_EN_V  0x1
+#define DSPI_SMEM_RX_DDR_MSK_EN_S  13
+/* DSPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to external RAM..*/
+#define DSPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define DSPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define DSPI_SMEM_TX_DDR_MSK_EN_V  0x1
+#define DSPI_SMEM_TX_DDR_MSK_EN_S  12
+/* DSPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the DDR psram..*/
+#define DSPI_SMEM_OUTMINBYTELEN    0x0000007F
+#define DSPI_SMEM_OUTMINBYTELEN_M  ((DSPI_SMEM_OUTMINBYTELEN_V)<<(DSPI_SMEM_OUTMINBYTELEN_S))
+#define DSPI_SMEM_OUTMINBYTELEN_V  0x7F
+#define DSPI_SMEM_OUTMINBYTELEN_S  5
+/* DSPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define DSPI_SMEM_DDR_CMD_DIS    (BIT(4))
+#define DSPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
+#define DSPI_SMEM_DDR_CMD_DIS_V  0x1
+#define DSPI_SMEM_DDR_CMD_DIS_S  4
+/* DSPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define DSPI_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define DSPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define DSPI_SMEM_DDR_WDAT_SWP_V  0x1
+#define DSPI_SMEM_DDR_WDAT_SWP_S  3
+/* DSPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define DSPI_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define DSPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define DSPI_SMEM_DDR_RDAT_SWP_V  0x1
+#define DSPI_SMEM_DDR_RDAT_SWP_S  2
+/* DSPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define DSPI_SMEM_VAR_DUMMY    (BIT(1))
+#define DSPI_SMEM_VAR_DUMMY_M  (BIT(1))
+#define DSPI_SMEM_VAR_DUMMY_V  0x1
+#define DSPI_SMEM_VAR_DUMMY_S  1
+/* DSPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define DSPI_SMEM_DDR_EN    (BIT(0))
+#define DSPI_SMEM_DDR_EN_M  (BIT(0))
+#define DSPI_SMEM_DDR_EN_V  0x1
+#define DSPI_SMEM_DDR_EN_S  0
+
+#define DSPI_FMEM_PMS0_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x100)
+/* DSPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define DSPI_FMEM_PMS0_ECC    (BIT(2))
+#define DSPI_FMEM_PMS0_ECC_M  (BIT(2))
+#define DSPI_FMEM_PMS0_ECC_V  0x1
+#define DSPI_FMEM_PMS0_ECC_S  2
+/* DSPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS0_WR_ATTR    (BIT(1))
+#define DSPI_FMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define DSPI_FMEM_PMS0_WR_ATTR_V  0x1
+#define DSPI_FMEM_PMS0_WR_ATTR_S  1
+/* DSPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS0_RD_ATTR    (BIT(0))
+#define DSPI_FMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define DSPI_FMEM_PMS0_RD_ATTR_V  0x1
+#define DSPI_FMEM_PMS0_RD_ATTR_S  0
+
+#define DSPI_FMEM_PMS1_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x104)
+/* DSPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define DSPI_FMEM_PMS1_ECC    (BIT(2))
+#define DSPI_FMEM_PMS1_ECC_M  (BIT(2))
+#define DSPI_FMEM_PMS1_ECC_V  0x1
+#define DSPI_FMEM_PMS1_ECC_S  2
+/* DSPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS1_WR_ATTR    (BIT(1))
+#define DSPI_FMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define DSPI_FMEM_PMS1_WR_ATTR_V  0x1
+#define DSPI_FMEM_PMS1_WR_ATTR_S  1
+/* DSPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS1_RD_ATTR    (BIT(0))
+#define DSPI_FMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define DSPI_FMEM_PMS1_RD_ATTR_V  0x1
+#define DSPI_FMEM_PMS1_RD_ATTR_S  0
+
+#define DSPI_FMEM_PMS2_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x108)
+/* DSPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define DSPI_FMEM_PMS2_ECC    (BIT(2))
+#define DSPI_FMEM_PMS2_ECC_M  (BIT(2))
+#define DSPI_FMEM_PMS2_ECC_V  0x1
+#define DSPI_FMEM_PMS2_ECC_S  2
+/* DSPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS2_WR_ATTR    (BIT(1))
+#define DSPI_FMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define DSPI_FMEM_PMS2_WR_ATTR_V  0x1
+#define DSPI_FMEM_PMS2_WR_ATTR_S  1
+/* DSPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS2_RD_ATTR    (BIT(0))
+#define DSPI_FMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define DSPI_FMEM_PMS2_RD_ATTR_V  0x1
+#define DSPI_FMEM_PMS2_RD_ATTR_S  0
+
+#define DSPI_FMEM_PMS3_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x10C)
+/* DSPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define DSPI_FMEM_PMS3_ECC    (BIT(2))
+#define DSPI_FMEM_PMS3_ECC_M  (BIT(2))
+#define DSPI_FMEM_PMS3_ECC_V  0x1
+#define DSPI_FMEM_PMS3_ECC_S  2
+/* DSPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS3_WR_ATTR    (BIT(1))
+#define DSPI_FMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define DSPI_FMEM_PMS3_WR_ATTR_V  0x1
+#define DSPI_FMEM_PMS3_WR_ATTR_S  1
+/* DSPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_FMEM_PMS3_RD_ATTR    (BIT(0))
+#define DSPI_FMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define DSPI_FMEM_PMS3_RD_ATTR_V  0x1
+#define DSPI_FMEM_PMS3_RD_ATTR_S  0
+
+#define DSPI_FMEM_PMS0_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x110)
+/* DSPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define DSPI_FMEM_PMS0_ADDR_S    0x03FFFFFF
+#define DSPI_FMEM_PMS0_ADDR_S_M  ((DSPI_FMEM_PMS0_ADDR_S_V)<<(DSPI_FMEM_PMS0_ADDR_S_S))
+#define DSPI_FMEM_PMS0_ADDR_S_V  0x3FFFFFF
+#define DSPI_FMEM_PMS0_ADDR_S_S  0
+
+#define DSPI_FMEM_PMS1_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x114)
+/* DSPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define DSPI_FMEM_PMS1_ADDR_S    0x03FFFFFF
+#define DSPI_FMEM_PMS1_ADDR_S_M  ((DSPI_FMEM_PMS1_ADDR_S_V)<<(DSPI_FMEM_PMS1_ADDR_S_S))
+#define DSPI_FMEM_PMS1_ADDR_S_V  0x3FFFFFF
+#define DSPI_FMEM_PMS1_ADDR_S_S  0
+
+#define DSPI_FMEM_PMS2_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x118)
+/* DSPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define DSPI_FMEM_PMS2_ADDR_S    0x03FFFFFF
+#define DSPI_FMEM_PMS2_ADDR_S_M  ((DSPI_FMEM_PMS2_ADDR_S_V)<<(DSPI_FMEM_PMS2_ADDR_S_S))
+#define DSPI_FMEM_PMS2_ADDR_S_V  0x3FFFFFF
+#define DSPI_FMEM_PMS2_ADDR_S_S  0
+
+#define DSPI_FMEM_PMS3_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x11C)
+/* DSPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define DSPI_FMEM_PMS3_ADDR_S    0x03FFFFFF
+#define DSPI_FMEM_PMS3_ADDR_S_M  ((DSPI_FMEM_PMS3_ADDR_S_V)<<(DSPI_FMEM_PMS3_ADDR_S_S))
+#define DSPI_FMEM_PMS3_ADDR_S_V  0x3FFFFFF
+#define DSPI_FMEM_PMS3_ADDR_S_S  0
+
+#define DSPI_FMEM_PMS0_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x120)
+/* DSPI_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define DSPI_FMEM_PMS0_SIZE    0x00003FFF
+#define DSPI_FMEM_PMS0_SIZE_M  ((DSPI_FMEM_PMS0_SIZE_V)<<(DSPI_FMEM_PMS0_SIZE_S))
+#define DSPI_FMEM_PMS0_SIZE_V  0x3FFF
+#define DSPI_FMEM_PMS0_SIZE_S  0
+
+#define DSPI_FMEM_PMS1_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x124)
+/* DSPI_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define DSPI_FMEM_PMS1_SIZE    0x00003FFF
+#define DSPI_FMEM_PMS1_SIZE_M  ((DSPI_FMEM_PMS1_SIZE_V)<<(DSPI_FMEM_PMS1_SIZE_S))
+#define DSPI_FMEM_PMS1_SIZE_V  0x3FFF
+#define DSPI_FMEM_PMS1_SIZE_S  0
+
+#define DSPI_FMEM_PMS2_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x128)
+/* DSPI_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define DSPI_FMEM_PMS2_SIZE    0x00003FFF
+#define DSPI_FMEM_PMS2_SIZE_M  ((DSPI_FMEM_PMS2_SIZE_V)<<(DSPI_FMEM_PMS2_SIZE_S))
+#define DSPI_FMEM_PMS2_SIZE_V  0x3FFF
+#define DSPI_FMEM_PMS2_SIZE_S  0
+
+#define DSPI_FMEM_PMS3_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x12C)
+/* DSPI_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define DSPI_FMEM_PMS3_SIZE    0x00003FFF
+#define DSPI_FMEM_PMS3_SIZE_M  ((DSPI_FMEM_PMS3_SIZE_V)<<(DSPI_FMEM_PMS3_SIZE_S))
+#define DSPI_FMEM_PMS3_SIZE_V  0x3FFF
+#define DSPI_FMEM_PMS3_SIZE_S  0
+
+#define DSPI_SMEM_PMS0_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x130)
+/* DSPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define DSPI_SMEM_PMS0_ECC    (BIT(2))
+#define DSPI_SMEM_PMS0_ECC_M  (BIT(2))
+#define DSPI_SMEM_PMS0_ECC_V  0x1
+#define DSPI_SMEM_PMS0_ECC_S  2
+/* DSPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define DSPI_SMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define DSPI_SMEM_PMS0_WR_ATTR_V  0x1
+#define DSPI_SMEM_PMS0_WR_ATTR_S  1
+/* DSPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define DSPI_SMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define DSPI_SMEM_PMS0_RD_ATTR_V  0x1
+#define DSPI_SMEM_PMS0_RD_ATTR_S  0
+
+#define DSPI_SMEM_PMS1_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x134)
+/* DSPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define DSPI_SMEM_PMS1_ECC    (BIT(2))
+#define DSPI_SMEM_PMS1_ECC_M  (BIT(2))
+#define DSPI_SMEM_PMS1_ECC_V  0x1
+#define DSPI_SMEM_PMS1_ECC_S  2
+/* DSPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define DSPI_SMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define DSPI_SMEM_PMS1_WR_ATTR_V  0x1
+#define DSPI_SMEM_PMS1_WR_ATTR_S  1
+/* DSPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define DSPI_SMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define DSPI_SMEM_PMS1_RD_ATTR_V  0x1
+#define DSPI_SMEM_PMS1_RD_ATTR_S  0
+
+#define DSPI_SMEM_PMS2_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x138)
+/* DSPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define DSPI_SMEM_PMS2_ECC    (BIT(2))
+#define DSPI_SMEM_PMS2_ECC_M  (BIT(2))
+#define DSPI_SMEM_PMS2_ECC_V  0x1
+#define DSPI_SMEM_PMS2_ECC_S  2
+/* DSPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define DSPI_SMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define DSPI_SMEM_PMS2_WR_ATTR_V  0x1
+#define DSPI_SMEM_PMS2_WR_ATTR_S  1
+/* DSPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define DSPI_SMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define DSPI_SMEM_PMS2_RD_ATTR_V  0x1
+#define DSPI_SMEM_PMS2_RD_ATTR_S  0
+
+#define DSPI_SMEM_PMS3_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x13C)
+/* DSPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define DSPI_SMEM_PMS3_ECC    (BIT(2))
+#define DSPI_SMEM_PMS3_ECC_M  (BIT(2))
+#define DSPI_SMEM_PMS3_ECC_V  0x1
+#define DSPI_SMEM_PMS3_ECC_S  2
+/* DSPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define DSPI_SMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define DSPI_SMEM_PMS3_WR_ATTR_V  0x1
+#define DSPI_SMEM_PMS3_WR_ATTR_S  1
+/* DSPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define DSPI_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define DSPI_SMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define DSPI_SMEM_PMS3_RD_ATTR_V  0x1
+#define DSPI_SMEM_PMS3_RD_ATTR_S  0
+
+#define DSPI_SMEM_PMS0_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x140)
+/* DSPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define DSPI_SMEM_PMS0_ADDR_S    0x03FFFFFF
+#define DSPI_SMEM_PMS0_ADDR_S_M  ((DSPI_SMEM_PMS0_ADDR_S_V)<<(DSPI_SMEM_PMS0_ADDR_S_S))
+#define DSPI_SMEM_PMS0_ADDR_S_V  0x3FFFFFF
+#define DSPI_SMEM_PMS0_ADDR_S_S  0
+
+#define DSPI_SMEM_PMS1_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x144)
+/* DSPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define DSPI_SMEM_PMS1_ADDR_S    0x03FFFFFF
+#define DSPI_SMEM_PMS1_ADDR_S_M  ((DSPI_SMEM_PMS1_ADDR_S_V)<<(DSPI_SMEM_PMS1_ADDR_S_S))
+#define DSPI_SMEM_PMS1_ADDR_S_V  0x3FFFFFF
+#define DSPI_SMEM_PMS1_ADDR_S_S  0
+
+#define DSPI_SMEM_PMS2_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x148)
+/* DSPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define DSPI_SMEM_PMS2_ADDR_S    0x03FFFFFF
+#define DSPI_SMEM_PMS2_ADDR_S_M  ((DSPI_SMEM_PMS2_ADDR_S_V)<<(DSPI_SMEM_PMS2_ADDR_S_S))
+#define DSPI_SMEM_PMS2_ADDR_S_V  0x3FFFFFF
+#define DSPI_SMEM_PMS2_ADDR_S_S  0
+
+#define DSPI_SMEM_PMS3_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x14C)
+/* DSPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define DSPI_SMEM_PMS3_ADDR_S    0x03FFFFFF
+#define DSPI_SMEM_PMS3_ADDR_S_M  ((DSPI_SMEM_PMS3_ADDR_S_V)<<(DSPI_SMEM_PMS3_ADDR_S_S))
+#define DSPI_SMEM_PMS3_ADDR_S_V  0x3FFFFFF
+#define DSPI_SMEM_PMS3_ADDR_S_S  0
+
+#define DSPI_SMEM_PMS0_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x150)
+/* DSPI_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define DSPI_SMEM_PMS0_SIZE    0x00003FFF
+#define DSPI_SMEM_PMS0_SIZE_M  ((DSPI_SMEM_PMS0_SIZE_V)<<(DSPI_SMEM_PMS0_SIZE_S))
+#define DSPI_SMEM_PMS0_SIZE_V  0x3FFF
+#define DSPI_SMEM_PMS0_SIZE_S  0
+
+#define DSPI_SMEM_PMS1_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x154)
+/* DSPI_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define DSPI_SMEM_PMS1_SIZE    0x00003FFF
+#define DSPI_SMEM_PMS1_SIZE_M  ((DSPI_SMEM_PMS1_SIZE_V)<<(DSPI_SMEM_PMS1_SIZE_S))
+#define DSPI_SMEM_PMS1_SIZE_V  0x3FFF
+#define DSPI_SMEM_PMS1_SIZE_S  0
+
+#define DSPI_SMEM_PMS2_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x158)
+/* DSPI_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define DSPI_SMEM_PMS2_SIZE    0x00003FFF
+#define DSPI_SMEM_PMS2_SIZE_M  ((DSPI_SMEM_PMS2_SIZE_V)<<(DSPI_SMEM_PMS2_SIZE_S))
+#define DSPI_SMEM_PMS2_SIZE_V  0x3FFF
+#define DSPI_SMEM_PMS2_SIZE_S  0
+
+#define DSPI_SMEM_PMS3_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x15C)
+/* DSPI_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define DSPI_SMEM_PMS3_SIZE    0x00003FFF
+#define DSPI_SMEM_PMS3_SIZE_M  ((DSPI_SMEM_PMS3_SIZE_V)<<(DSPI_SMEM_PMS3_SIZE_S))
+#define DSPI_SMEM_PMS3_SIZE_V  0x3FFF
+#define DSPI_SMEM_PMS3_SIZE_S  0
+
+#define DSPI_MEM_PMS_REJECT_REG          (DR_REG_DSPI_MEM_BASE + 0x164)
+/* DSPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
+/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+ error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define DSPI_MEM_PMS_IVD    (BIT(31))
+#define DSPI_MEM_PMS_IVD_M  (BIT(31))
+#define DSPI_MEM_PMS_IVD_V  0x1
+#define DSPI_MEM_PMS_IVD_S  31
+/* DSPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
+ is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define DSPI_MEM_PMS_MULTI_HIT    (BIT(30))
+#define DSPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
+#define DSPI_MEM_PMS_MULTI_HIT_V  0x1
+#define DSPI_MEM_PMS_MULTI_HIT_S  30
+/* DSPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define DSPI_MEM_PMS_ST    (BIT(29))
+#define DSPI_MEM_PMS_ST_M  (BIT(29))
+#define DSPI_MEM_PMS_ST_V  0x1
+#define DSPI_MEM_PMS_ST_S  29
+/* DSPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
+_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define DSPI_MEM_PMS_LD    (BIT(28))
+#define DSPI_MEM_PMS_LD_M  (BIT(28))
+#define DSPI_MEM_PMS_LD_V  0x1
+#define DSPI_MEM_PMS_LD_S  28
+/* DSPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
+#define DSPI_MEM_PM_EN    (BIT(26))
+#define DSPI_MEM_PM_EN_M  (BIT(26))
+#define DSPI_MEM_PM_EN_V  0x1
+#define DSPI_MEM_PM_EN_S  26
+/* DSPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define DSPI_MEM_REJECT_ADDR    0x03FFFFFF
+#define DSPI_MEM_REJECT_ADDR_M  ((DSPI_MEM_REJECT_ADDR_V)<<(DSPI_MEM_REJECT_ADDR_S))
+#define DSPI_MEM_REJECT_ADDR_V  0x3FFFFFF
+#define DSPI_MEM_REJECT_ADDR_S  0
+
+#define DSPI_MEM_ECC_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x168)
+/* DSPI_MEM_ECC_ERR_BITS : R/SS/WTC ;bitpos:[31:25] ;default: 7'd0 ; */
+/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
+ to byte 0 bit 0 to byte 15 bit 7).*/
+#define DSPI_MEM_ECC_ERR_BITS    0x0000007F
+#define DSPI_MEM_ECC_ERR_BITS_M  ((DSPI_MEM_ECC_ERR_BITS_V)<<(DSPI_MEM_ECC_ERR_BITS_S))
+#define DSPI_MEM_ECC_ERR_BITS_V  0x7F
+#define DSPI_MEM_ECC_ERR_BITS_S  25
+/* DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
+ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
+R record the first ECC error information..*/
+#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
+#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
+#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/* DSPI_MEM_USR_ECC_ADDR_EN : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
+#define DSPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
+#define DSPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
+#define DSPI_MEM_USR_ECC_ADDR_EN_V  0x1
+#define DSPI_MEM_USR_ECC_ADDR_EN_S  21
+/* DSPI_FMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
+is bit should be 0. Otherwise, this bit should be 1..*/
+#define DSPI_FMEM_ECC_ADDR_EN    (BIT(20))
+#define DSPI_FMEM_ECC_ADDR_EN_M  (BIT(20))
+#define DSPI_FMEM_ECC_ADDR_EN_V  0x1
+#define DSPI_FMEM_ECC_ADDR_EN_S  20
+/* DSPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+1024 bytes. 3: 2048 bytes..*/
+#define DSPI_FMEM_PAGE_SIZE    0x00000003
+#define DSPI_FMEM_PAGE_SIZE_M  ((DSPI_FMEM_PAGE_SIZE_V)<<(DSPI_FMEM_PAGE_SIZE_S))
+#define DSPI_FMEM_PAGE_SIZE_V  0x3
+#define DSPI_FMEM_PAGE_SIZE_S  18
+/* DSPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
+h..*/
+#define DSPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
+#define DSPI_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define DSPI_FMEM_ECC_ERR_INT_EN_V  0x1
+#define DSPI_FMEM_ECC_ERR_INT_EN_S  17
+/* DSPI_FMEM_ECC_ERR_INT_NUM : R/W ;bitpos:[16:11] ;default: 6'd10 ; */
+/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
+upt..*/
+#define DSPI_FMEM_ECC_ERR_INT_NUM    0x0000003F
+#define DSPI_FMEM_ECC_ERR_INT_NUM_M  ((DSPI_FMEM_ECC_ERR_INT_NUM_V)<<(DSPI_FMEM_ECC_ERR_INT_NUM_S))
+#define DSPI_FMEM_ECC_ERR_INT_NUM_V  0x3F
+#define DSPI_FMEM_ECC_ERR_INT_NUM_S  11
+
+#define DSPI_MEM_ECC_ERR_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x16C)
+/* DSPI_MEM_ECC_ERR_CNT : R/SS/WTC ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define DSPI_MEM_ECC_ERR_CNT    0x0000003F
+#define DSPI_MEM_ECC_ERR_CNT_M  ((DSPI_MEM_ECC_ERR_CNT_V)<<(DSPI_MEM_ECC_ERR_CNT_S))
+#define DSPI_MEM_ECC_ERR_CNT_V  0x3F
+#define DSPI_MEM_ECC_ERR_CNT_S  26
+/* DSPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define DSPI_MEM_ECC_ERR_ADDR    0x03FFFFFF
+#define DSPI_MEM_ECC_ERR_ADDR_M  ((DSPI_MEM_ECC_ERR_ADDR_V)<<(DSPI_MEM_ECC_ERR_ADDR_S))
+#define DSPI_MEM_ECC_ERR_ADDR_V  0x3FFFFFF
+#define DSPI_MEM_ECC_ERR_ADDR_S  0
+
+#define DSPI_MEM_AXI_ERR_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x170)
+/* DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
+and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
+#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
+#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
+#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+/* DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M  (BIT(30))
+#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V  0x1
+#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S  30
+/* DSPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY    (BIT(29))
+#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_M  (BIT(29))
+#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_V  0x1
+#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_S  29
+/* DSPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
+/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY    (BIT(28))
+#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_M  (BIT(28))
+#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_V  0x1
+#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_S  28
+/* DSPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY    (BIT(27))
+#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_M  (BIT(27))
+#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_V  0x1
+#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_S  27
+/* DSPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+ and SPI0 transfers are done. 0: Others..*/
+#define DSPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
+#define DSPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
+#define DSPI_MEM_ALL_FIFO_EMPTY_V  0x1
+#define DSPI_MEM_ALL_FIFO_EMPTY_S  26
+/* DSPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
+ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
+H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
+#define DSPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
+#define DSPI_MEM_AXI_ERR_ADDR_M  ((DSPI_MEM_AXI_ERR_ADDR_V)<<(DSPI_MEM_AXI_ERR_ADDR_S))
+#define DSPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
+#define DSPI_MEM_AXI_ERR_ADDR_S  0
+
+#define DSPI_SMEM_ECC_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x174)
+/* DSPI_SMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
+ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
+#define DSPI_SMEM_ECC_ADDR_EN    (BIT(20))
+#define DSPI_SMEM_ECC_ADDR_EN_M  (BIT(20))
+#define DSPI_SMEM_ECC_ADDR_EN_V  0x1
+#define DSPI_SMEM_ECC_ADDR_EN_S  20
+/* DSPI_SMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd2 ; */
+/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
+es. 2: 1024 bytes. 3: 2048 bytes..*/
+#define DSPI_SMEM_PAGE_SIZE    0x00000003
+#define DSPI_SMEM_PAGE_SIZE_M  ((DSPI_SMEM_PAGE_SIZE_V)<<(DSPI_SMEM_PAGE_SIZE_S))
+#define DSPI_SMEM_PAGE_SIZE_V  0x3
+#define DSPI_SMEM_PAGE_SIZE_S  18
+/* DSPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
+rnal RAM..*/
+#define DSPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define DSPI_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define DSPI_SMEM_ECC_ERR_INT_EN_V  0x1
+#define DSPI_SMEM_ECC_ERR_INT_EN_S  17
+
+#define DSPI_MEM_TIMING_CALI_REG          (DR_REG_DSPI_MEM_BASE + 0x180)
+/* DSPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
+#define DSPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
+#define DSPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
+#define DSPI_MEM_TIMING_CALI_UPDATE_V  0x1
+#define DSPI_MEM_TIMING_CALI_UPDATE_S  6
+/* DSPI_MEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
+lash..*/
+#define DSPI_MEM_DLL_TIMING_CALI    (BIT(5))
+#define DSPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
+#define DSPI_MEM_DLL_TIMING_CALI_V  0x1
+#define DSPI_MEM_DLL_TIMING_CALI_S  5
+/* DSPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
+#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* DSPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
+#define DSPI_MEM_TIMING_CALI    (BIT(1))
+#define DSPI_MEM_TIMING_CALI_M  (BIT(1))
+#define DSPI_MEM_TIMING_CALI_V  0x1
+#define DSPI_MEM_TIMING_CALI_S  1
+/* DSPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations..*/
+#define DSPI_MEM_TIMING_CLK_ENA    (BIT(0))
+#define DSPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define DSPI_MEM_TIMING_CLK_ENA_V  0x1
+#define DSPI_MEM_TIMING_CLK_ENA_S  0
+
+#define DSPI_MEM_DIN_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x184)
+/* DSPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define DSPI_MEM_DINS_MODE    0x00000007
+#define DSPI_MEM_DINS_MODE_M  ((DSPI_MEM_DINS_MODE_V)<<(DSPI_MEM_DINS_MODE_S))
+#define DSPI_MEM_DINS_MODE_V  0x7
+#define DSPI_MEM_DINS_MODE_S  24
+/* DSPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define DSPI_MEM_DIN7_MODE    0x00000007
+#define DSPI_MEM_DIN7_MODE_M  ((DSPI_MEM_DIN7_MODE_V)<<(DSPI_MEM_DIN7_MODE_S))
+#define DSPI_MEM_DIN7_MODE_V  0x7
+#define DSPI_MEM_DIN7_MODE_S  21
+/* DSPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define DSPI_MEM_DIN6_MODE    0x00000007
+#define DSPI_MEM_DIN6_MODE_M  ((DSPI_MEM_DIN6_MODE_V)<<(DSPI_MEM_DIN6_MODE_S))
+#define DSPI_MEM_DIN6_MODE_V  0x7
+#define DSPI_MEM_DIN6_MODE_S  18
+/* DSPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define DSPI_MEM_DIN5_MODE    0x00000007
+#define DSPI_MEM_DIN5_MODE_M  ((DSPI_MEM_DIN5_MODE_V)<<(DSPI_MEM_DIN5_MODE_S))
+#define DSPI_MEM_DIN5_MODE_V  0x7
+#define DSPI_MEM_DIN5_MODE_S  15
+/* DSPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define DSPI_MEM_DIN4_MODE    0x00000007
+#define DSPI_MEM_DIN4_MODE_M  ((DSPI_MEM_DIN4_MODE_V)<<(DSPI_MEM_DIN4_MODE_S))
+#define DSPI_MEM_DIN4_MODE_V  0x7
+#define DSPI_MEM_DIN4_MODE_S  12
+/* DSPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_MEM_DIN3_MODE    0x00000007
+#define DSPI_MEM_DIN3_MODE_M  ((DSPI_MEM_DIN3_MODE_V)<<(DSPI_MEM_DIN3_MODE_S))
+#define DSPI_MEM_DIN3_MODE_V  0x7
+#define DSPI_MEM_DIN3_MODE_S  9
+/* DSPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_MEM_DIN2_MODE    0x00000007
+#define DSPI_MEM_DIN2_MODE_M  ((DSPI_MEM_DIN2_MODE_V)<<(DSPI_MEM_DIN2_MODE_S))
+#define DSPI_MEM_DIN2_MODE_V  0x7
+#define DSPI_MEM_DIN2_MODE_S  6
+/* DSPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_MEM_DIN1_MODE    0x00000007
+#define DSPI_MEM_DIN1_MODE_M  ((DSPI_MEM_DIN1_MODE_V)<<(DSPI_MEM_DIN1_MODE_S))
+#define DSPI_MEM_DIN1_MODE_V  0x7
+#define DSPI_MEM_DIN1_MODE_S  3
+/* DSPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_MEM_DIN0_MODE    0x00000007
+#define DSPI_MEM_DIN0_MODE_M  ((DSPI_MEM_DIN0_MODE_V)<<(DSPI_MEM_DIN0_MODE_S))
+#define DSPI_MEM_DIN0_MODE_V  0x7
+#define DSPI_MEM_DIN0_MODE_S  0
+
+#define DSPI_MEM_DIN_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x188)
+/* DSPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DINS_NUM    0x00000003
+#define DSPI_MEM_DINS_NUM_M  ((DSPI_MEM_DINS_NUM_V)<<(DSPI_MEM_DINS_NUM_S))
+#define DSPI_MEM_DINS_NUM_V  0x3
+#define DSPI_MEM_DINS_NUM_S  16
+/* DSPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN7_NUM    0x00000003
+#define DSPI_MEM_DIN7_NUM_M  ((DSPI_MEM_DIN7_NUM_V)<<(DSPI_MEM_DIN7_NUM_S))
+#define DSPI_MEM_DIN7_NUM_V  0x3
+#define DSPI_MEM_DIN7_NUM_S  14
+/* DSPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN6_NUM    0x00000003
+#define DSPI_MEM_DIN6_NUM_M  ((DSPI_MEM_DIN6_NUM_V)<<(DSPI_MEM_DIN6_NUM_S))
+#define DSPI_MEM_DIN6_NUM_V  0x3
+#define DSPI_MEM_DIN6_NUM_S  12
+/* DSPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN5_NUM    0x00000003
+#define DSPI_MEM_DIN5_NUM_M  ((DSPI_MEM_DIN5_NUM_V)<<(DSPI_MEM_DIN5_NUM_S))
+#define DSPI_MEM_DIN5_NUM_V  0x3
+#define DSPI_MEM_DIN5_NUM_S  10
+/* DSPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN4_NUM    0x00000003
+#define DSPI_MEM_DIN4_NUM_M  ((DSPI_MEM_DIN4_NUM_V)<<(DSPI_MEM_DIN4_NUM_S))
+#define DSPI_MEM_DIN4_NUM_V  0x3
+#define DSPI_MEM_DIN4_NUM_S  8
+/* DSPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN3_NUM    0x00000003
+#define DSPI_MEM_DIN3_NUM_M  ((DSPI_MEM_DIN3_NUM_V)<<(DSPI_MEM_DIN3_NUM_S))
+#define DSPI_MEM_DIN3_NUM_V  0x3
+#define DSPI_MEM_DIN3_NUM_S  6
+/* DSPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN2_NUM    0x00000003
+#define DSPI_MEM_DIN2_NUM_M  ((DSPI_MEM_DIN2_NUM_V)<<(DSPI_MEM_DIN2_NUM_S))
+#define DSPI_MEM_DIN2_NUM_V  0x3
+#define DSPI_MEM_DIN2_NUM_S  4
+/* DSPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN1_NUM    0x00000003
+#define DSPI_MEM_DIN1_NUM_M  ((DSPI_MEM_DIN1_NUM_V)<<(DSPI_MEM_DIN1_NUM_S))
+#define DSPI_MEM_DIN1_NUM_V  0x3
+#define DSPI_MEM_DIN1_NUM_S  2
+/* DSPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_MEM_DIN0_NUM    0x00000003
+#define DSPI_MEM_DIN0_NUM_M  ((DSPI_MEM_DIN0_NUM_V)<<(DSPI_MEM_DIN0_NUM_S))
+#define DSPI_MEM_DIN0_NUM_V  0x3
+#define DSPI_MEM_DIN0_NUM_S  0
+
+#define DSPI_MEM_DOUT_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x18C)
+/* DSPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define DSPI_MEM_DOUTS_MODE    (BIT(8))
+#define DSPI_MEM_DOUTS_MODE_M  (BIT(8))
+#define DSPI_MEM_DOUTS_MODE_V  0x1
+#define DSPI_MEM_DOUTS_MODE_S  8
+/* DSPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define DSPI_MEM_DOUT7_MODE    (BIT(7))
+#define DSPI_MEM_DOUT7_MODE_M  (BIT(7))
+#define DSPI_MEM_DOUT7_MODE_V  0x1
+#define DSPI_MEM_DOUT7_MODE_S  7
+/* DSPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define DSPI_MEM_DOUT6_MODE    (BIT(6))
+#define DSPI_MEM_DOUT6_MODE_M  (BIT(6))
+#define DSPI_MEM_DOUT6_MODE_V  0x1
+#define DSPI_MEM_DOUT6_MODE_S  6
+/* DSPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define DSPI_MEM_DOUT5_MODE    (BIT(5))
+#define DSPI_MEM_DOUT5_MODE_M  (BIT(5))
+#define DSPI_MEM_DOUT5_MODE_V  0x1
+#define DSPI_MEM_DOUT5_MODE_S  5
+/* DSPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define DSPI_MEM_DOUT4_MODE    (BIT(4))
+#define DSPI_MEM_DOUT4_MODE_M  (BIT(4))
+#define DSPI_MEM_DOUT4_MODE_V  0x1
+#define DSPI_MEM_DOUT4_MODE_S  4
+/* DSPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_MEM_DOUT3_MODE    (BIT(3))
+#define DSPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define DSPI_MEM_DOUT3_MODE_V  0x1
+#define DSPI_MEM_DOUT3_MODE_S  3
+/* DSPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_MEM_DOUT2_MODE    (BIT(2))
+#define DSPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define DSPI_MEM_DOUT2_MODE_V  0x1
+#define DSPI_MEM_DOUT2_MODE_S  2
+/* DSPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_MEM_DOUT1_MODE    (BIT(1))
+#define DSPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define DSPI_MEM_DOUT1_MODE_V  0x1
+#define DSPI_MEM_DOUT1_MODE_S  1
+/* DSPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_MEM_DOUT0_MODE    (BIT(0))
+#define DSPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define DSPI_MEM_DOUT0_MODE_V  0x1
+#define DSPI_MEM_DOUT0_MODE_S  0
+
+#define DSPI_SMEM_TIMING_CALI_REG          (DR_REG_DSPI_MEM_BASE + 0x190)
+/* DSPI_SMEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
+XT_RAM..*/
+#define DSPI_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define DSPI_SMEM_DLL_TIMING_CALI_M  (BIT(5))
+#define DSPI_SMEM_DLL_TIMING_CALI_V  0x1
+#define DSPI_SMEM_DLL_TIMING_CALI_S  5
+/* DSPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
+#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
+#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* DSPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
+ations..*/
+#define DSPI_SMEM_TIMING_CALI    (BIT(1))
+#define DSPI_SMEM_TIMING_CALI_M  (BIT(1))
+#define DSPI_SMEM_TIMING_CALI_V  0x1
+#define DSPI_SMEM_TIMING_CALI_S  1
+/* DSPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
+ns..*/
+#define DSPI_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define DSPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
+#define DSPI_SMEM_TIMING_CLK_ENA_V  0x1
+#define DSPI_SMEM_TIMING_CLK_ENA_S  0
+
+#define DSPI_SMEM_DIN_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x194)
+/* DSPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DINS_MODE    0x00000007
+#define DSPI_SMEM_DINS_MODE_M  ((DSPI_SMEM_DINS_MODE_V)<<(DSPI_SMEM_DINS_MODE_S))
+#define DSPI_SMEM_DINS_MODE_V  0x7
+#define DSPI_SMEM_DINS_MODE_S  24
+/* DSPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN7_MODE    0x00000007
+#define DSPI_SMEM_DIN7_MODE_M  ((DSPI_SMEM_DIN7_MODE_V)<<(DSPI_SMEM_DIN7_MODE_S))
+#define DSPI_SMEM_DIN7_MODE_V  0x7
+#define DSPI_SMEM_DIN7_MODE_S  21
+/* DSPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN6_MODE    0x00000007
+#define DSPI_SMEM_DIN6_MODE_M  ((DSPI_SMEM_DIN6_MODE_V)<<(DSPI_SMEM_DIN6_MODE_S))
+#define DSPI_SMEM_DIN6_MODE_V  0x7
+#define DSPI_SMEM_DIN6_MODE_S  18
+/* DSPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN5_MODE    0x00000007
+#define DSPI_SMEM_DIN5_MODE_M  ((DSPI_SMEM_DIN5_MODE_V)<<(DSPI_SMEM_DIN5_MODE_S))
+#define DSPI_SMEM_DIN5_MODE_V  0x7
+#define DSPI_SMEM_DIN5_MODE_S  15
+/* DSPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN4_MODE    0x00000007
+#define DSPI_SMEM_DIN4_MODE_M  ((DSPI_SMEM_DIN4_MODE_V)<<(DSPI_SMEM_DIN4_MODE_S))
+#define DSPI_SMEM_DIN4_MODE_V  0x7
+#define DSPI_SMEM_DIN4_MODE_S  12
+/* DSPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN3_MODE    0x00000007
+#define DSPI_SMEM_DIN3_MODE_M  ((DSPI_SMEM_DIN3_MODE_V)<<(DSPI_SMEM_DIN3_MODE_S))
+#define DSPI_SMEM_DIN3_MODE_V  0x7
+#define DSPI_SMEM_DIN3_MODE_S  9
+/* DSPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN2_MODE    0x00000007
+#define DSPI_SMEM_DIN2_MODE_M  ((DSPI_SMEM_DIN2_MODE_V)<<(DSPI_SMEM_DIN2_MODE_S))
+#define DSPI_SMEM_DIN2_MODE_V  0x7
+#define DSPI_SMEM_DIN2_MODE_S  6
+/* DSPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN1_MODE    0x00000007
+#define DSPI_SMEM_DIN1_MODE_M  ((DSPI_SMEM_DIN1_MODE_V)<<(DSPI_SMEM_DIN1_MODE_S))
+#define DSPI_SMEM_DIN1_MODE_V  0x7
+#define DSPI_SMEM_DIN1_MODE_S  3
+/* DSPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN0_MODE    0x00000007
+#define DSPI_SMEM_DIN0_MODE_M  ((DSPI_SMEM_DIN0_MODE_V)<<(DSPI_SMEM_DIN0_MODE_S))
+#define DSPI_SMEM_DIN0_MODE_V  0x7
+#define DSPI_SMEM_DIN0_MODE_S  0
+
+#define DSPI_SMEM_DIN_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x198)
+/* DSPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DINS_NUM    0x00000003
+#define DSPI_SMEM_DINS_NUM_M  ((DSPI_SMEM_DINS_NUM_V)<<(DSPI_SMEM_DINS_NUM_S))
+#define DSPI_SMEM_DINS_NUM_V  0x3
+#define DSPI_SMEM_DINS_NUM_S  16
+/* DSPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN7_NUM    0x00000003
+#define DSPI_SMEM_DIN7_NUM_M  ((DSPI_SMEM_DIN7_NUM_V)<<(DSPI_SMEM_DIN7_NUM_S))
+#define DSPI_SMEM_DIN7_NUM_V  0x3
+#define DSPI_SMEM_DIN7_NUM_S  14
+/* DSPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN6_NUM    0x00000003
+#define DSPI_SMEM_DIN6_NUM_M  ((DSPI_SMEM_DIN6_NUM_V)<<(DSPI_SMEM_DIN6_NUM_S))
+#define DSPI_SMEM_DIN6_NUM_V  0x3
+#define DSPI_SMEM_DIN6_NUM_S  12
+/* DSPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN5_NUM    0x00000003
+#define DSPI_SMEM_DIN5_NUM_M  ((DSPI_SMEM_DIN5_NUM_V)<<(DSPI_SMEM_DIN5_NUM_S))
+#define DSPI_SMEM_DIN5_NUM_V  0x3
+#define DSPI_SMEM_DIN5_NUM_S  10
+/* DSPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN4_NUM    0x00000003
+#define DSPI_SMEM_DIN4_NUM_M  ((DSPI_SMEM_DIN4_NUM_V)<<(DSPI_SMEM_DIN4_NUM_S))
+#define DSPI_SMEM_DIN4_NUM_V  0x3
+#define DSPI_SMEM_DIN4_NUM_S  8
+/* DSPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN3_NUM    0x00000003
+#define DSPI_SMEM_DIN3_NUM_M  ((DSPI_SMEM_DIN3_NUM_V)<<(DSPI_SMEM_DIN3_NUM_S))
+#define DSPI_SMEM_DIN3_NUM_V  0x3
+#define DSPI_SMEM_DIN3_NUM_S  6
+/* DSPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN2_NUM    0x00000003
+#define DSPI_SMEM_DIN2_NUM_M  ((DSPI_SMEM_DIN2_NUM_V)<<(DSPI_SMEM_DIN2_NUM_S))
+#define DSPI_SMEM_DIN2_NUM_V  0x3
+#define DSPI_SMEM_DIN2_NUM_S  4
+/* DSPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN1_NUM    0x00000003
+#define DSPI_SMEM_DIN1_NUM_M  ((DSPI_SMEM_DIN1_NUM_V)<<(DSPI_SMEM_DIN1_NUM_S))
+#define DSPI_SMEM_DIN1_NUM_V  0x3
+#define DSPI_SMEM_DIN1_NUM_S  2
+/* DSPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN0_NUM    0x00000003
+#define DSPI_SMEM_DIN0_NUM_M  ((DSPI_SMEM_DIN0_NUM_V)<<(DSPI_SMEM_DIN0_NUM_S))
+#define DSPI_SMEM_DIN0_NUM_V  0x3
+#define DSPI_SMEM_DIN0_NUM_S  0
+
+#define DSPI_SMEM_DOUT_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x19C)
+/* DSPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUTS_MODE    (BIT(8))
+#define DSPI_SMEM_DOUTS_MODE_M  (BIT(8))
+#define DSPI_SMEM_DOUTS_MODE_V  0x1
+#define DSPI_SMEM_DOUTS_MODE_S  8
+/* DSPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT7_MODE    (BIT(7))
+#define DSPI_SMEM_DOUT7_MODE_M  (BIT(7))
+#define DSPI_SMEM_DOUT7_MODE_V  0x1
+#define DSPI_SMEM_DOUT7_MODE_S  7
+/* DSPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT6_MODE    (BIT(6))
+#define DSPI_SMEM_DOUT6_MODE_M  (BIT(6))
+#define DSPI_SMEM_DOUT6_MODE_V  0x1
+#define DSPI_SMEM_DOUT6_MODE_S  6
+/* DSPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT5_MODE    (BIT(5))
+#define DSPI_SMEM_DOUT5_MODE_M  (BIT(5))
+#define DSPI_SMEM_DOUT5_MODE_V  0x1
+#define DSPI_SMEM_DOUT5_MODE_S  5
+/* DSPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT4_MODE    (BIT(4))
+#define DSPI_SMEM_DOUT4_MODE_M  (BIT(4))
+#define DSPI_SMEM_DOUT4_MODE_V  0x1
+#define DSPI_SMEM_DOUT4_MODE_S  4
+/* DSPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT3_MODE    (BIT(3))
+#define DSPI_SMEM_DOUT3_MODE_M  (BIT(3))
+#define DSPI_SMEM_DOUT3_MODE_V  0x1
+#define DSPI_SMEM_DOUT3_MODE_S  3
+/* DSPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT2_MODE    (BIT(2))
+#define DSPI_SMEM_DOUT2_MODE_M  (BIT(2))
+#define DSPI_SMEM_DOUT2_MODE_V  0x1
+#define DSPI_SMEM_DOUT2_MODE_S  2
+/* DSPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT1_MODE    (BIT(1))
+#define DSPI_SMEM_DOUT1_MODE_M  (BIT(1))
+#define DSPI_SMEM_DOUT1_MODE_V  0x1
+#define DSPI_SMEM_DOUT1_MODE_S  1
+/* DSPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT0_MODE    (BIT(0))
+#define DSPI_SMEM_DOUT0_MODE_M  (BIT(0))
+#define DSPI_SMEM_DOUT0_MODE_V  0x1
+#define DSPI_SMEM_DOUT0_MODE_S  0
+
+#define DSPI_SMEM_AC_REG          (DR_REG_DSPI_MEM_BASE + 0x1A0)
+/* DSPI_SMEM_SPLIT_TRANS_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+ transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
+er whether there is an ECC region or not..*/
+#define DSPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define DSPI_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
+#define DSPI_SMEM_SPLIT_TRANS_EN_V  0x1
+#define DSPI_SMEM_SPLIT_TRANS_EN_S  31
+/* DSPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
+SPI core clock cycles..*/
+#define DSPI_SMEM_CS_HOLD_DELAY    0x0000003F
+#define DSPI_SMEM_CS_HOLD_DELAY_M  ((DSPI_SMEM_CS_HOLD_DELAY_V)<<(DSPI_SMEM_CS_HOLD_DELAY_S))
+#define DSPI_SMEM_CS_HOLD_DELAY_V  0x3F
+#define DSPI_SMEM_CS_HOLD_DELAY_S  25
+/* DSPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
+n accesses external RAM..*/
+#define DSPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define DSPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
+#define DSPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
+#define DSPI_SMEM_ECC_16TO18_BYTE_EN_S  16
+/* DSPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
+en accesses external RAM..*/
+#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
+#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/* DSPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
+ycles in ECC mode when accessed external RAM..*/
+#define DSPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
+#define DSPI_SMEM_ECC_CS_HOLD_TIME_M  ((DSPI_SMEM_ECC_CS_HOLD_TIME_V)<<(DSPI_SMEM_ECC_CS_HOLD_TIME_S))
+#define DSPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
+#define DSPI_SMEM_ECC_CS_HOLD_TIME_S  12
+/* DSPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */
+/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
+re combined with spi_mem_cs_hold bit..*/
+#define DSPI_SMEM_CS_HOLD_TIME    0x0000001F
+#define DSPI_SMEM_CS_HOLD_TIME_M  ((DSPI_SMEM_CS_HOLD_TIME_V)<<(DSPI_SMEM_CS_HOLD_TIME_S))
+#define DSPI_SMEM_CS_HOLD_TIME_V  0x1F
+#define DSPI_SMEM_CS_HOLD_TIME_S  7
+/* DSPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */
+/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
+pi_mem_cs_setup bit..*/
+#define DSPI_SMEM_CS_SETUP_TIME    0x0000001F
+#define DSPI_SMEM_CS_SETUP_TIME_M  ((DSPI_SMEM_CS_SETUP_TIME_V)<<(DSPI_SMEM_CS_SETUP_TIME_S))
+#define DSPI_SMEM_CS_SETUP_TIME_V  0x1F
+#define DSPI_SMEM_CS_SETUP_TIME_S  2
+/* DSPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
+le..*/
+#define DSPI_SMEM_CS_HOLD    (BIT(1))
+#define DSPI_SMEM_CS_HOLD_M  (BIT(1))
+#define DSPI_SMEM_CS_HOLD_V  0x1
+#define DSPI_SMEM_CS_HOLD_S  1
+/* DSPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
+isable..*/
+#define DSPI_SMEM_CS_SETUP    (BIT(0))
+#define DSPI_SMEM_CS_SETUP_M  (BIT(0))
+#define DSPI_SMEM_CS_SETUP_V  0x1
+#define DSPI_SMEM_CS_SETUP_S  0
+
+#define DSPI_SMEM_DIN_HEX_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x1A4)
+/* DSPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DINS_HEX_MODE    0x00000007
+#define DSPI_SMEM_DINS_HEX_MODE_M  ((DSPI_SMEM_DINS_HEX_MODE_V)<<(DSPI_SMEM_DINS_HEX_MODE_S))
+#define DSPI_SMEM_DINS_HEX_MODE_V  0x7
+#define DSPI_SMEM_DINS_HEX_MODE_S  24
+/* DSPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN15_MODE    0x00000007
+#define DSPI_SMEM_DIN15_MODE_M  ((DSPI_SMEM_DIN15_MODE_V)<<(DSPI_SMEM_DIN15_MODE_S))
+#define DSPI_SMEM_DIN15_MODE_V  0x7
+#define DSPI_SMEM_DIN15_MODE_S  21
+/* DSPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN14_MODE    0x00000007
+#define DSPI_SMEM_DIN14_MODE_M  ((DSPI_SMEM_DIN14_MODE_V)<<(DSPI_SMEM_DIN14_MODE_S))
+#define DSPI_SMEM_DIN14_MODE_V  0x7
+#define DSPI_SMEM_DIN14_MODE_S  18
+/* DSPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN13_MODE    0x00000007
+#define DSPI_SMEM_DIN13_MODE_M  ((DSPI_SMEM_DIN13_MODE_V)<<(DSPI_SMEM_DIN13_MODE_S))
+#define DSPI_SMEM_DIN13_MODE_V  0x7
+#define DSPI_SMEM_DIN13_MODE_S  15
+/* DSPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN12_MODE    0x00000007
+#define DSPI_SMEM_DIN12_MODE_M  ((DSPI_SMEM_DIN12_MODE_V)<<(DSPI_SMEM_DIN12_MODE_S))
+#define DSPI_SMEM_DIN12_MODE_V  0x7
+#define DSPI_SMEM_DIN12_MODE_S  12
+/* DSPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN11_MODE    0x00000007
+#define DSPI_SMEM_DIN11_MODE_M  ((DSPI_SMEM_DIN11_MODE_V)<<(DSPI_SMEM_DIN11_MODE_S))
+#define DSPI_SMEM_DIN11_MODE_V  0x7
+#define DSPI_SMEM_DIN11_MODE_S  9
+/* DSPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN10_MODE    0x00000007
+#define DSPI_SMEM_DIN10_MODE_M  ((DSPI_SMEM_DIN10_MODE_V)<<(DSPI_SMEM_DIN10_MODE_S))
+#define DSPI_SMEM_DIN10_MODE_V  0x7
+#define DSPI_SMEM_DIN10_MODE_S  6
+/* DSPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN09_MODE    0x00000007
+#define DSPI_SMEM_DIN09_MODE_M  ((DSPI_SMEM_DIN09_MODE_V)<<(DSPI_SMEM_DIN09_MODE_S))
+#define DSPI_SMEM_DIN09_MODE_V  0x7
+#define DSPI_SMEM_DIN09_MODE_S  3
+/* DSPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define DSPI_SMEM_DIN08_MODE    0x00000007
+#define DSPI_SMEM_DIN08_MODE_M  ((DSPI_SMEM_DIN08_MODE_V)<<(DSPI_SMEM_DIN08_MODE_S))
+#define DSPI_SMEM_DIN08_MODE_V  0x7
+#define DSPI_SMEM_DIN08_MODE_S  0
+
+#define DSPI_SMEM_DIN_HEX_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x1A8)
+/* DSPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DINS_HEX_NUM    0x00000003
+#define DSPI_SMEM_DINS_HEX_NUM_M  ((DSPI_SMEM_DINS_HEX_NUM_V)<<(DSPI_SMEM_DINS_HEX_NUM_S))
+#define DSPI_SMEM_DINS_HEX_NUM_V  0x3
+#define DSPI_SMEM_DINS_HEX_NUM_S  16
+/* DSPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN15_NUM    0x00000003
+#define DSPI_SMEM_DIN15_NUM_M  ((DSPI_SMEM_DIN15_NUM_V)<<(DSPI_SMEM_DIN15_NUM_S))
+#define DSPI_SMEM_DIN15_NUM_V  0x3
+#define DSPI_SMEM_DIN15_NUM_S  14
+/* DSPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN14_NUM    0x00000003
+#define DSPI_SMEM_DIN14_NUM_M  ((DSPI_SMEM_DIN14_NUM_V)<<(DSPI_SMEM_DIN14_NUM_S))
+#define DSPI_SMEM_DIN14_NUM_V  0x3
+#define DSPI_SMEM_DIN14_NUM_S  12
+/* DSPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN13_NUM    0x00000003
+#define DSPI_SMEM_DIN13_NUM_M  ((DSPI_SMEM_DIN13_NUM_V)<<(DSPI_SMEM_DIN13_NUM_S))
+#define DSPI_SMEM_DIN13_NUM_V  0x3
+#define DSPI_SMEM_DIN13_NUM_S  10
+/* DSPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN12_NUM    0x00000003
+#define DSPI_SMEM_DIN12_NUM_M  ((DSPI_SMEM_DIN12_NUM_V)<<(DSPI_SMEM_DIN12_NUM_S))
+#define DSPI_SMEM_DIN12_NUM_V  0x3
+#define DSPI_SMEM_DIN12_NUM_S  8
+/* DSPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN11_NUM    0x00000003
+#define DSPI_SMEM_DIN11_NUM_M  ((DSPI_SMEM_DIN11_NUM_V)<<(DSPI_SMEM_DIN11_NUM_S))
+#define DSPI_SMEM_DIN11_NUM_V  0x3
+#define DSPI_SMEM_DIN11_NUM_S  6
+/* DSPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN10_NUM    0x00000003
+#define DSPI_SMEM_DIN10_NUM_M  ((DSPI_SMEM_DIN10_NUM_V)<<(DSPI_SMEM_DIN10_NUM_S))
+#define DSPI_SMEM_DIN10_NUM_V  0x3
+#define DSPI_SMEM_DIN10_NUM_S  4
+/* DSPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN09_NUM    0x00000003
+#define DSPI_SMEM_DIN09_NUM_M  ((DSPI_SMEM_DIN09_NUM_V)<<(DSPI_SMEM_DIN09_NUM_S))
+#define DSPI_SMEM_DIN09_NUM_V  0x3
+#define DSPI_SMEM_DIN09_NUM_S  2
+/* DSPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define DSPI_SMEM_DIN08_NUM    0x00000003
+#define DSPI_SMEM_DIN08_NUM_M  ((DSPI_SMEM_DIN08_NUM_V)<<(DSPI_SMEM_DIN08_NUM_S))
+#define DSPI_SMEM_DIN08_NUM_V  0x3
+#define DSPI_SMEM_DIN08_NUM_S  0
+
+#define DSPI_SMEM_DOUT_HEX_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x1AC)
+/* DSPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUTS_HEX_MODE    (BIT(8))
+#define DSPI_SMEM_DOUTS_HEX_MODE_M  (BIT(8))
+#define DSPI_SMEM_DOUTS_HEX_MODE_V  0x1
+#define DSPI_SMEM_DOUTS_HEX_MODE_S  8
+/* DSPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT15_MODE    (BIT(7))
+#define DSPI_SMEM_DOUT15_MODE_M  (BIT(7))
+#define DSPI_SMEM_DOUT15_MODE_V  0x1
+#define DSPI_SMEM_DOUT15_MODE_S  7
+/* DSPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT14_MODE    (BIT(6))
+#define DSPI_SMEM_DOUT14_MODE_M  (BIT(6))
+#define DSPI_SMEM_DOUT14_MODE_V  0x1
+#define DSPI_SMEM_DOUT14_MODE_S  6
+/* DSPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT13_MODE    (BIT(5))
+#define DSPI_SMEM_DOUT13_MODE_M  (BIT(5))
+#define DSPI_SMEM_DOUT13_MODE_V  0x1
+#define DSPI_SMEM_DOUT13_MODE_S  5
+/* DSPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT12_MODE    (BIT(4))
+#define DSPI_SMEM_DOUT12_MODE_M  (BIT(4))
+#define DSPI_SMEM_DOUT12_MODE_V  0x1
+#define DSPI_SMEM_DOUT12_MODE_S  4
+/* DSPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT11_MODE    (BIT(3))
+#define DSPI_SMEM_DOUT11_MODE_M  (BIT(3))
+#define DSPI_SMEM_DOUT11_MODE_V  0x1
+#define DSPI_SMEM_DOUT11_MODE_S  3
+/* DSPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT10_MODE    (BIT(2))
+#define DSPI_SMEM_DOUT10_MODE_M  (BIT(2))
+#define DSPI_SMEM_DOUT10_MODE_V  0x1
+#define DSPI_SMEM_DOUT10_MODE_S  2
+/* DSPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT09_MODE    (BIT(1))
+#define DSPI_SMEM_DOUT09_MODE_M  (BIT(1))
+#define DSPI_SMEM_DOUT09_MODE_V  0x1
+#define DSPI_SMEM_DOUT09_MODE_S  1
+/* DSPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define DSPI_SMEM_DOUT08_MODE    (BIT(0))
+#define DSPI_SMEM_DOUT08_MODE_M  (BIT(0))
+#define DSPI_SMEM_DOUT08_MODE_V  0x1
+#define DSPI_SMEM_DOUT08_MODE_S  0
+
+#define DSPI_MEM_CLOCK_GATE_REG          (DR_REG_DSPI_MEM_BASE + 0x200)
+/* DSPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
+#define DSPI_MEM_SPI_CLK_EN    (BIT(0))
+#define DSPI_MEM_SPI_CLK_EN_M  (BIT(0))
+#define DSPI_MEM_SPI_CLK_EN_V  0x1
+#define DSPI_MEM_SPI_CLK_EN_S  0
+
+#define DSPI_MEM_XTS_PLAIN_BASE_REG          (DR_REG_DSPI_MEM_BASE + 0x300)
+/* DSPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This field is only used to generate include file in c case. This field is useles
+s. Please do not use this field..*/
+#define DSPI_MEM_SPI_XTS_PLAIN    0xFFFFFFFF
+#define DSPI_MEM_SPI_XTS_PLAIN_M  ((DSPI_MEM_SPI_XTS_PLAIN_V)<<(DSPI_MEM_SPI_XTS_PLAIN_S))
+#define DSPI_MEM_SPI_XTS_PLAIN_V  0xFFFFFFFF
+#define DSPI_MEM_SPI_XTS_PLAIN_S  0
+
+#define DSPI_MEM_XTS_LINESIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x340)
+/* DSPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the line-size parameter which will be used in manual encryption
+ calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
+ 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
+#define DSPI_MEM_SPI_XTS_LINESIZE    0x00000003
+#define DSPI_MEM_SPI_XTS_LINESIZE_M  ((DSPI_MEM_SPI_XTS_LINESIZE_V)<<(DSPI_MEM_SPI_XTS_LINESIZE_S))
+#define DSPI_MEM_SPI_XTS_LINESIZE_V  0x3
+#define DSPI_MEM_SPI_XTS_LINESIZE_S  0
+
+#define DSPI_MEM_XTS_DESTINATION_REG          (DR_REG_DSPI_MEM_BASE + 0x344)
+/* DSPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit stores the destination parameter which will be used in manual encryptio
+n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
+used..*/
+#define DSPI_MEM_SPI_XTS_DESTINATION    (BIT(0))
+#define DSPI_MEM_SPI_XTS_DESTINATION_M  (BIT(0))
+#define DSPI_MEM_SPI_XTS_DESTINATION_V  0x1
+#define DSPI_MEM_SPI_XTS_DESTINATION_S  0
+
+#define DSPI_MEM_XTS_PHYSICAL_ADDRESS_REG          (DR_REG_DSPI_MEM_BASE + 0x348)
+/* DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits stores the physical-address parameter which will be used in manual enc
+ryption calculation. This value should aligned with byte number decided by line-
+size parameter..*/
+#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFF
+#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M  ((DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S))
+#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V  0x3FFFFFF
+#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S  0
+
+#define DSPI_MEM_XTS_TRIGGER_REG          (DR_REG_DSPI_MEM_BASE + 0x34C)
+/* DSPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to trigger the process of manual encryption calculation. This actio
+n should only be asserted when manual encryption status is 0. After this action,
+ manual encryption status becomes 1. After calculation is done, manual encryptio
+n status becomes 2..*/
+#define DSPI_MEM_SPI_XTS_TRIGGER    (BIT(0))
+#define DSPI_MEM_SPI_XTS_TRIGGER_M  (BIT(0))
+#define DSPI_MEM_SPI_XTS_TRIGGER_V  0x1
+#define DSPI_MEM_SPI_XTS_TRIGGER_S  0
+
+#define DSPI_MEM_XTS_RELEASE_REG          (DR_REG_DSPI_MEM_BASE + 0x350)
+/* DSPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to release encrypted result to mspi. This action should only be ass
+erted when manual encryption status is 2. After this action, manual encryption s
+tatus will become 3..*/
+#define DSPI_MEM_SPI_XTS_RELEASE    (BIT(0))
+#define DSPI_MEM_SPI_XTS_RELEASE_M  (BIT(0))
+#define DSPI_MEM_SPI_XTS_RELEASE_V  0x1
+#define DSPI_MEM_SPI_XTS_RELEASE_S  0
+
+#define DSPI_MEM_XTS_DESTROY_REG          (DR_REG_DSPI_MEM_BASE + 0x354)
+/* DSPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
+en manual encryption status is 3. After this action, manual encryption status wi
+ll become 0..*/
+#define DSPI_MEM_SPI_XTS_DESTROY    (BIT(0))
+#define DSPI_MEM_SPI_XTS_DESTROY_M  (BIT(0))
+#define DSPI_MEM_SPI_XTS_DESTROY_V  0x1
+#define DSPI_MEM_SPI_XTS_DESTROY_S  0
+
+#define DSPI_MEM_XTS_STATE_REG          (DR_REG_DSPI_MEM_BASE + 0x358)
+/* DSPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+ calculation, 2: encryption calculation is done but the encrypted result is invi
+sible to mspi, 3: the encrypted result is visible to mspi..*/
+#define DSPI_MEM_SPI_XTS_STATE    0x00000003
+#define DSPI_MEM_SPI_XTS_STATE_M  ((DSPI_MEM_SPI_XTS_STATE_V)<<(DSPI_MEM_SPI_XTS_STATE_S))
+#define DSPI_MEM_SPI_XTS_STATE_V  0x3
+#define DSPI_MEM_SPI_XTS_STATE_S  0
+
+#define DSPI_MEM_XTS_DATE_REG          (DR_REG_DSPI_MEM_BASE + 0x35C)
+/* DSPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
+/*description: This bits stores the last modified-time of manual encryption feature..*/
+#define DSPI_MEM_SPI_XTS_DATE    0x3FFFFFFF
+#define DSPI_MEM_SPI_XTS_DATE_M  ((DSPI_MEM_SPI_XTS_DATE_V)<<(DSPI_MEM_SPI_XTS_DATE_S))
+#define DSPI_MEM_SPI_XTS_DATE_V  0x3FFFFFFF
+#define DSPI_MEM_SPI_XTS_DATE_S  0
+
+#define DSPI_MEM_MMU_ITEM_CONTENT_REG          (DR_REG_DSPI_MEM_BASE + 0x37C)
+/* DSPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: MSPI-MMU item content.*/
+#define DSPI_MEM_SPI_MMU_ITEM_CONTENT    0xFFFFFFFF
+#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_M  ((DSPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(DSPI_MEM_SPI_MMU_ITEM_CONTENT_S))
+#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFF
+#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_S  0
+
+#define DSPI_MEM_MMU_ITEM_INDEX_REG          (DR_REG_DSPI_MEM_BASE + 0x380)
+/* DSPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: MSPI-MMU item index.*/
+#define DSPI_MEM_SPI_MMU_ITEM_INDEX    0xFFFFFFFF
+#define DSPI_MEM_SPI_MMU_ITEM_INDEX_M  ((DSPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(DSPI_MEM_SPI_MMU_ITEM_INDEX_S))
+#define DSPI_MEM_SPI_MMU_ITEM_INDEX_V  0xFFFFFFFF
+#define DSPI_MEM_SPI_MMU_ITEM_INDEX_S  0
+
+#define DSPI_MEM_MMU_POWER_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x384)
+/* DSPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
+#define DSPI_MEM_RDN_RESULT    (BIT(31))
+#define DSPI_MEM_RDN_RESULT_M  (BIT(31))
+#define DSPI_MEM_RDN_RESULT_V  0x1
+#define DSPI_MEM_RDN_RESULT_S  31
+/* DSPI_MEM_RDN_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: ECO register enable bit.*/
+#define DSPI_MEM_RDN_ENA    (BIT(30))
+#define DSPI_MEM_RDN_ENA_M  (BIT(30))
+#define DSPI_MEM_RDN_ENA_V  0x1
+#define DSPI_MEM_RDN_ENA_S  30
+/* DSPI_MEM_AUX_CTRL : R/W ;bitpos:[29:16] ;default: 14'h1320 ; */
+/*description: MMU PSRAM aux control register.*/
+#define DSPI_MEM_AUX_CTRL    0x00003FFF
+#define DSPI_MEM_AUX_CTRL_M  ((DSPI_MEM_AUX_CTRL_V)<<(DSPI_MEM_AUX_CTRL_S))
+#define DSPI_MEM_AUX_CTRL_V  0x3FFF
+#define DSPI_MEM_AUX_CTRL_S  16
+/* DSPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
+ controlled by rtc..*/
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU    (BIT(2))
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_V  0x1
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_S  2
+/* DSPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to force mmu-memory powerdown.*/
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD    (BIT(1))
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_V  0x1
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_S  1
+/* DSPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable mmu-memory clock force on.*/
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON    (BIT(0))
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_V  0x1
+#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_S  0
+
+#define DSPI_MEM_DPA_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x388)
+/* DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
+T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
+#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
+#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V  0x1
+#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S  4
+/* DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
+ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
+ing key 1..*/
+#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
+#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V  0x1
+#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S  3
+/* DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
+7: The bigger the number is, the more secure the cryption is. (Note that the per
+formance of cryption will decrease together with this number increasing).*/
+#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL    0x00000007
+#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M  ((DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S))
+#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V  0x7
+#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S  0
+
+#define DSPI_MEM_REGISTERRND_ECO_HIGH_REG          (DR_REG_DSPI_MEM_BASE + 0x3F0)
+/* DSPI_MEM_REGISTERRND_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO high register.*/
+#define DSPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
+#define DSPI_MEM_REGISTERRND_ECO_HIGH_M  ((DSPI_MEM_REGISTERRND_ECO_HIGH_V)<<(DSPI_MEM_REGISTERRND_ECO_HIGH_S))
+#define DSPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
+#define DSPI_MEM_REGISTERRND_ECO_HIGH_S  0
+
+#define DSPI_MEM_REGISTERRND_ECO_LOW_REG          (DR_REG_DSPI_MEM_BASE + 0x3F4)
+/* DSPI_MEM_REGISTERRND_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO low register.*/
+#define DSPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
+#define DSPI_MEM_REGISTERRND_ECO_LOW_M  ((DSPI_MEM_REGISTERRND_ECO_LOW_V)<<(DSPI_MEM_REGISTERRND_ECO_LOW_S))
+#define DSPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
+#define DSPI_MEM_REGISTERRND_ECO_LOW_S  0
+
+#define DSPI_MEM_DATE_REG          (DR_REG_DSPI_MEM_BASE + 0x3FC)
+/* DSPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2211210 ; */
+/*description: SPI0 register version..*/
+#define DSPI_MEM_DATE    0x0FFFFFFF
+#define DSPI_MEM_DATE_M  ((DSPI_MEM_DATE_V)<<(DSPI_MEM_DATE_S))
+#define DSPI_MEM_DATE_V  0xFFFFFFF
+#define DSPI_MEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_DSPI_MEM_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/efuse_reg.h b/components/soc/esp32p4/include/soc/efuse_reg.h
new file mode 100644
index 0000000000..faed73b495
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/efuse_reg.h
@@ -0,0 +1,3088 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define EFUSE_READ_OP_CODE 0x5aa5
+#define EFUSE_WRITE_OP_CODE 0x5a5a
+#define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0)
+/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 0th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_0    0xFFFFFFFF
+#define EFUSE_PGM_DATA_0_M  ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S))
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_0_S  0
+
+#define EFUSE_PGM_DATA1_REG          (DR_REG_EFUSE_BASE + 0x4)
+/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 1st 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_1    0xFFFFFFFF
+#define EFUSE_PGM_DATA_1_M  ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S))
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_1_S  0
+
+#define EFUSE_PGM_DATA2_REG          (DR_REG_EFUSE_BASE + 0x8)
+/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 2nd 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_2    0xFFFFFFFF
+#define EFUSE_PGM_DATA_2_M  ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S))
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_2_S  0
+
+#define EFUSE_PGM_DATA3_REG          (DR_REG_EFUSE_BASE + 0xC)
+/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 3rd 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_3    0xFFFFFFFF
+#define EFUSE_PGM_DATA_3_M  ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S))
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_3_S  0
+
+#define EFUSE_PGM_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10)
+/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 4th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_4    0xFFFFFFFF
+#define EFUSE_PGM_DATA_4_M  ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S))
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_4_S  0
+
+#define EFUSE_PGM_DATA5_REG          (DR_REG_EFUSE_BASE + 0x14)
+/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 5th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_5    0xFFFFFFFF
+#define EFUSE_PGM_DATA_5_M  ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S))
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_5_S  0
+
+#define EFUSE_PGM_DATA6_REG          (DR_REG_EFUSE_BASE + 0x18)
+/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 6th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_6    0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_M  ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S))
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_S  0
+
+#define EFUSE_PGM_DATA7_REG          (DR_REG_EFUSE_BASE + 0x1C)
+/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 7th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_7    0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_M  ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S))
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_S  0
+
+#define EFUSE_PGM_CHECK_VALUE0_REG          (DR_REG_EFUSE_BASE + 0x20)
+/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 0th 32-bit RS code to be programmed..*/
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_M  ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S))
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+#define EFUSE_PGM_CHECK_VALUE1_REG          (DR_REG_EFUSE_BASE + 0x24)
+/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 1st 32-bit RS code to be programmed..*/
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_M  ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S))
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+#define EFUSE_PGM_CHECK_VALUE2_REG          (DR_REG_EFUSE_BASE + 0x28)
+/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Configures the 2nd 32-bit RS code to be programmed..*/
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_M  ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S))
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+#define EFUSE_RD_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x2C)
+/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Represents whether programming of individual eFuse memory bit is disabled or ena
+bled. 1: Disabled. 0 Enabled..*/
+#define EFUSE_WR_DIS    0xFFFFFFFF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA0_REG          (DR_REG_EFUSE_BASE + 0x30)
+/* EFUSE_KM_HUK_GEN_STATE_LOW : RO ;bitpos:[31:26] ;default: 6'h0 ; */
+/*description: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, ev
+en of 1 is valid..*/
+#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003F
+#define EFUSE_KM_HUK_GEN_STATE_LOW_M  ((EFUSE_KM_HUK_GEN_STATE_LOW_V)<<(EFUSE_KM_HUK_GEN_STATE_LOW_S))
+#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x3F
+#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
+/* EFUSE_USB_PHY_SEL : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: TBD.*/
+#define EFUSE_USB_PHY_SEL    (BIT(25))
+#define EFUSE_USB_PHY_SEL_M  (BIT(25))
+#define EFUSE_USB_PHY_SEL_V  0x1
+#define EFUSE_USB_PHY_SEL_S  25
+/* EFUSE_USB_OTG11_DREFH : RO ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80
+mV.*/
+#define EFUSE_USB_OTG11_DREFH    0x00000003
+#define EFUSE_USB_OTG11_DREFH_M  ((EFUSE_USB_OTG11_DREFH_V)<<(EFUSE_USB_OTG11_DREFH_S))
+#define EFUSE_USB_OTG11_DREFH_V  0x3
+#define EFUSE_USB_OTG11_DREFH_S  23
+/* EFUSE_USB_DEVICE_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 8
+0mV.*/
+#define EFUSE_USB_DEVICE_DREFH    0x00000003
+#define EFUSE_USB_DEVICE_DREFH_M  ((EFUSE_USB_DEVICE_DREFH_V)<<(EFUSE_USB_DEVICE_DREFH_S))
+#define EFUSE_USB_DEVICE_DREFH_V  0x3
+#define EFUSE_USB_DEVICE_DREFH_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Represents whether flash encrypt function is disabled or enabled(except in SPI b
+oot mode). 1: disabled. 0: enabled..*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0
+: enabled..*/
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_V  0x1
+#define EFUSE_DIS_PAD_JTAG_S  19
+/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: Represents whether JTAG is disabled in soft way. Odd number: disabled. Even numb
+er: enabled..*/
+#define EFUSE_SOFT_DIS_JTAG    0x00000007
+#define EFUSE_SOFT_DIS_JTAG_M  ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S))
+#define EFUSE_SOFT_DIS_JTAG_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Represents whether the selection between usb_to_jtag and pad_to_jtag through str
+apping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ is enabled or disabled. 1: enabled. 0: disabled..*/
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_V  0x1
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
+..*/
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (BIT(14))
+#define EFUSE_DIS_TWAI_V  0x1
+#define EFUSE_DIS_TWAI_S  14
+/* EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during b
+oot_mode_download..*/
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x1
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Represents whether the function that forces chip into download mode is disabled
+or enabled. 1: disabled. 0: enabled..*/
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/* EFUSE_DIS_USB_SERIAL_JTAG : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabl
+ed..*/
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x1
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Represents whether power glitch function is enabled. 1: enabled. 0: disabled..*/
+#define EFUSE_POWERGLITCH_EN    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_M  (BIT(10))
+#define EFUSE_POWERGLITCH_EN_V  0x1
+#define EFUSE_POWERGLITCH_EN_S  10
+/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+ disabled. 0: enabled..*/
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_V  0x1
+#define EFUSE_DIS_USB_JTAG_S  9
+/* EFUSE_USB_OTG11_EXCHG_PINS : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Enable usb otg11 exchange pins of D+ and D-..*/
+#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
+#define EFUSE_USB_OTG11_EXCHG_PINS_M  (BIT(8))
+#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x1
+#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
+/* EFUSE_USB_DEVICE_EXCHG_PINS : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Enable usb device exchange pins of D+ and D-..*/
+#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (BIT(7))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x1
+#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
+/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: Represents whether reading of individual eFuse block(block4~block10) is disabled
+ or enabled. 1: disabled. 0: enabled..*/
+#define EFUSE_RD_DIS    0x0000007F
+#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V  0x7F
+#define EFUSE_RD_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA1_REG          (DR_REG_EFUSE_BASE + 0x34)
+/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Represents the purpose of Key1..*/
+#define EFUSE_KEY_PURPOSE_1    0x0000000F
+#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
+#define EFUSE_KEY_PURPOSE_1_V  0xF
+#define EFUSE_KEY_PURPOSE_1_S  28
+/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: Represents the purpose of Key0..*/
+#define EFUSE_KEY_PURPOSE_0    0x0000000F
+#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
+#define EFUSE_KEY_PURPOSE_0_V  0xF
+#define EFUSE_KEY_PURPOSE_0_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Represents whether revoking third secure boot key is enabled or disabled. 1: ena
+bled. 0: disabled..*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Represents whether revoking second secure boot key is enabled or disabled. 1: en
+abled. 0: disabled..*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Represents whether revoking first secure boot key is enabled or disabled. 1: ena
+bled. 0: disabled..*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number o
+f 1: enabled. Even number of 1: disabled..*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: Represents whether RTC watchdog timeout threshold is selected at startup. 1: sel
+ected. 0: not selected..*/
+#define EFUSE_WDT_DELAY_SEL    0x00000003
+#define EFUSE_WDT_DELAY_SEL_M  ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
+#define EFUSE_WDT_DELAY_SEL_V  0x3
+#define EFUSE_WDT_DELAY_SEL_S  16
+/* EFUSE_XTS_KEY_LENGTH_256 : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to configure flash encryption use xts-128 key, else use xts-256 key
+..*/
+#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_M  (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_V  0x1
+#define EFUSE_XTS_KEY_LENGTH_256_S  14
+/* EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO ;bitpos:[13] ;default: 3'h0 ; */
+/*description: Set this bit to disable software written init key, and force use efuse_init_key..*/
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x1
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
+/* EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO ;bitpos:[12:9] ;default: 4'h0 ; */
+/*description: Set each bit to control whether corresponding key must come from key manager.. 1
+ is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds..*/
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000F
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  ((EFUSE_FORCE_USE_KEY_MANAGER_KEY_V)<<(EFUSE_FORCE_USE_KEY_MANAGER_KEY_S))
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0xF
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
+/* EFUSE_KM_DEPLOY_ONLY_ONCE : RO ;bitpos:[8:5] ;default: 4'h0 ; */
+/*description: Set each bit to control whether corresponding key can only be deployed once. 1 i
+s true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds..*/
+#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000F
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  ((EFUSE_KM_DEPLOY_ONLY_ONCE_V)<<(EFUSE_KM_DEPLOY_ONLY_ONCE_S))
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0xF
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
+/* EFUSE_KM_RND_SWITCH_CYCLE : RO ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: Set bits to control key manager random number switch cycle. 0: control by regist
+er. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles..*/
+#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003
+#define EFUSE_KM_RND_SWITCH_CYCLE_M  ((EFUSE_KM_RND_SWITCH_CYCLE_V)<<(EFUSE_KM_RND_SWITCH_CYCLE_S))
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x3
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
+/* EFUSE_KM_HUK_GEN_STATE_HIGH : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, ev
+en of 1 is valid..*/
+#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  ((EFUSE_KM_HUK_GEN_STATE_HIGH_V)<<(EFUSE_KM_HUK_GEN_STATE_HIGH_S))
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x7
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
+
+#define EFUSE_RD_REPEAT_DATA2_REG          (DR_REG_EFUSE_BASE + 0x38)
+/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Represents the flash waiting time after power-up, in unit of ms. When the value
+less than 15, the waiting time is the programmed value. Otherwise, the waiting t
+ime is 2 times the programmed value..*/
+#define EFUSE_FLASH_TPUW    0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  28
+/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to disable download via USB-OTG..*/
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
+/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable ecc for flash boot..*/
+#define EFUSE_FLASH_ECC_EN    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_M  (BIT(26))
+#define EFUSE_FLASH_ECC_EN_V  0x1
+#define EFUSE_FLASH_ECC_EN_S  26
+/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[25:24] ;default: 2'b0 ; */
+/*description: Set flash page size..*/
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
+#define EFUSE_FLASH_PAGE_SIZE_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_S  24
+/* EFUSE_FLASH_TYPE : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The type of interfaced flash. 0: four data lines, 1: eight data lines..*/
+#define EFUSE_FLASH_TYPE    (BIT(23))
+#define EFUSE_FLASH_TYPE_M  (BIT(23))
+#define EFUSE_FLASH_TYPE_V  0x1
+#define EFUSE_FLASH_TYPE_S  23
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Represents whether revoking aggressive secure boot is enabled or disabled. 1: en
+abled. 0: disabled..*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled..*/
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  20
+/* EFUSE_CRYPT_DPA_ENABLE : RO ;bitpos:[19] ;default: 1'b1 ; */
+/*description: Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled..*/
+#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_M  (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_V  0x1
+#define EFUSE_CRYPT_DPA_ENABLE_S  19
+/* EFUSE_ECDSA_ENABLE_SOFT_K : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Represents whether hardware random number k is forced used in ESDCA. 1: force us
+ed. 0: not force used..*/
+#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x1
+#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
+/* EFUSE_SEC_DPA_LEVEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: Represents the spa secure level by configuring the clock random divide mode..*/
+#define EFUSE_SEC_DPA_LEVEL    0x00000003
+#define EFUSE_SEC_DPA_LEVEL_M  ((EFUSE_SEC_DPA_LEVEL_V)<<(EFUSE_SEC_DPA_LEVEL_S))
+#define EFUSE_SEC_DPA_LEVEL_V  0x3
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: Represents the purpose of Key5..*/
+#define EFUSE_KEY_PURPOSE_5    0x0000000F
+#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
+#define EFUSE_KEY_PURPOSE_5_V  0xF
+#define EFUSE_KEY_PURPOSE_5_S  12
+/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: Represents the purpose of Key4..*/
+#define EFUSE_KEY_PURPOSE_4    0x0000000F
+#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
+#define EFUSE_KEY_PURPOSE_4_V  0xF
+#define EFUSE_KEY_PURPOSE_4_S  8
+/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: Represents the purpose of Key3..*/
+#define EFUSE_KEY_PURPOSE_3    0x0000000F
+#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
+#define EFUSE_KEY_PURPOSE_3_V  0xF
+#define EFUSE_KEY_PURPOSE_3_S  4
+/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Represents the purpose of Key2..*/
+#define EFUSE_KEY_PURPOSE_2    0x0000000F
+#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
+#define EFUSE_KEY_PURPOSE_2_V  0xF
+#define EFUSE_KEY_PURPOSE_2_S  0
+
+#define EFUSE_RD_REPEAT_DATA3_REG          (DR_REG_EFUSE_BASE + 0x3C)
+/* EFUSE_DCDC_VSET : RO ;bitpos:[31:27] ;default: 5'h0 ; */
+/*description: Set the dcdc voltage default..*/
+#define EFUSE_DCDC_VSET    0x0000001F
+#define EFUSE_DCDC_VSET_M  ((EFUSE_DCDC_VSET_V)<<(EFUSE_DCDC_VSET_S))
+#define EFUSE_DCDC_VSET_V  0x1F
+#define EFUSE_DCDC_VSET_S  27
+/* EFUSE_HYS_EN_PAD : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Represents whether the hysteresis function of corresponding PAD is enabled. 1: e
+nabled. 0:disabled..*/
+#define EFUSE_HYS_EN_PAD    (BIT(26))
+#define EFUSE_HYS_EN_PAD_M  (BIT(26))
+#define EFUSE_HYS_EN_PAD_V  0x1
+#define EFUSE_HYS_EN_PAD_S  26
+/* EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot i
+s enabled. 1: disabled. 0: enabled..*/
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x1
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
+/* EFUSE_SECURE_VERSION : RO ;bitpos:[24:9] ;default: 16'h0 ; */
+/*description: Represents the version used by ESP-IDF anti-rollback feature..*/
+#define EFUSE_SECURE_VERSION    0x0000FFFF
+#define EFUSE_SECURE_VERSION_M  ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S))
+#define EFUSE_SECURE_VERSION_V  0xFFFF
+#define EFUSE_SECURE_VERSION_S  9
+/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Represents whether ROM code is forced to send a resume command during SPI boot.
+1: forced. 0:not forced..*/
+#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_M  (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_S  8
+/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: Represents the type of UART printing. 00: force enable printing. 01: enable prin
+ting when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset a
+t high level. 11: force disable printing..*/
+#define EFUSE_UART_PRINT_CONTROL    0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Represents whether security download is enabled or disabled. 1: enabled. 0: disa
+bled..*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Represents whether the USB-Serial-JTAG download function is disabled or enabled.
+ 1: disabled. 0: enabled..*/
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/* EFUSE_LOCK_KM_KEY : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: TBD.*/
+#define EFUSE_LOCK_KM_KEY    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_M  (BIT(3))
+#define EFUSE_LOCK_KM_KEY_V  0x1
+#define EFUSE_LOCK_KM_KEY_S  3
+/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disable
+d. 0: enabled..*/
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x1
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enab
+led..*/
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_V  0x1
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
+..*/
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+
+#define EFUSE_RD_REPEAT_DATA4_REG          (DR_REG_EFUSE_BASE + 0x40)
+/* EFUSE_DIS_SWD : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to disable super-watchdog..*/
+#define EFUSE_DIS_SWD    (BIT(21))
+#define EFUSE_DIS_SWD_M  (BIT(21))
+#define EFUSE_DIS_SWD_V  0x1
+#define EFUSE_DIS_SWD_S  21
+/* EFUSE_DIS_WDT : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to disable watch dog..*/
+#define EFUSE_DIS_WDT    (BIT(20))
+#define EFUSE_DIS_WDT_M  (BIT(20))
+#define EFUSE_DIS_WDT_V  0x1
+#define EFUSE_DIS_WDT_S  20
+/* EFUSE_DCDC_VSET_EN : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Select dcdc vset use efuse_dcdc_vset..*/
+#define EFUSE_DCDC_VSET_EN    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_M  (BIT(19))
+#define EFUSE_DCDC_VSET_EN_V  0x1
+#define EFUSE_DCDC_VSET_EN_S  19
+/* EFUSE_HP_PWR_SRC_SEL : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: HP system power source select. 0:LDO. 1: DCDC..*/
+#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_M  (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_V  0x1
+#define EFUSE_HP_PWR_SRC_SEL_S  18
+/* EFUSE_USB_OTG11_DREFL : RO ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with ste
+p of 80 mV..*/
+#define EFUSE_USB_OTG11_DREFL    0x00000003
+#define EFUSE_USB_OTG11_DREFL_M  ((EFUSE_USB_OTG11_DREFL_V)<<(EFUSE_USB_OTG11_DREFL_S))
+#define EFUSE_USB_OTG11_DREFL_V  0x3
+#define EFUSE_USB_OTG11_DREFL_S  14
+/* EFUSE_USB_DEVICE_DREFL : RO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with st
+ep of 80 mV..*/
+#define EFUSE_USB_DEVICE_DREFL    0x00000003
+#define EFUSE_USB_DEVICE_DREFL_M  ((EFUSE_USB_DEVICE_DREFL_V)<<(EFUSE_USB_DEVICE_DREFL_S))
+#define EFUSE_USB_DEVICE_DREFL_V  0x3
+#define EFUSE_USB_DEVICE_DREFL_S  12
+/* EFUSE_KM_DISABLE_DEPLOY_MODE : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: TBD..*/
+#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000F
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  ((EFUSE_KM_DISABLE_DEPLOY_MODE_V)<<(EFUSE_KM_DISABLE_DEPLOY_MODE_S))
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0xF
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
+/* EFUSE_0PXA_TIEH_SEL_3 : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: TBD..*/
+#define EFUSE_0PXA_TIEH_SEL_3    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_3_M  ((EFUSE_0PXA_TIEH_SEL_3_V)<<(EFUSE_0PXA_TIEH_SEL_3_S))
+#define EFUSE_0PXA_TIEH_SEL_3_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_3_S  6
+/* EFUSE_0PXA_TIEH_SEL_2 : RO ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: TBD..*/
+#define EFUSE_0PXA_TIEH_SEL_2    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_2_M  ((EFUSE_0PXA_TIEH_SEL_2_V)<<(EFUSE_0PXA_TIEH_SEL_2_S))
+#define EFUSE_0PXA_TIEH_SEL_2_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_2_S  4
+/* EFUSE_0PXA_TIEH_SEL_1 : RO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: TBD..*/
+#define EFUSE_0PXA_TIEH_SEL_1    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_1_M  ((EFUSE_0PXA_TIEH_SEL_1_V)<<(EFUSE_0PXA_TIEH_SEL_1_S))
+#define EFUSE_0PXA_TIEH_SEL_1_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_1_S  2
+/* EFUSE_0PXA_TIEH_SEL_0 : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: TBD.*/
+#define EFUSE_0PXA_TIEH_SEL_0    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_0_M  ((EFUSE_0PXA_TIEH_SEL_0_V)<<(EFUSE_0PXA_TIEH_SEL_0_S))
+#define EFUSE_0PXA_TIEH_SEL_0_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_0_S  0
+
+#define EFUSE_RD_MAC_SYS_0_REG          (DR_REG_EFUSE_BASE + 0x44)
+/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the low 32 bits of MAC address..*/
+#define EFUSE_MAC_0    0xFFFFFFFF
+#define EFUSE_MAC_0_M  ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S))
+#define EFUSE_MAC_0_V  0xFFFFFFFF
+#define EFUSE_MAC_0_S  0
+
+#define EFUSE_RD_MAC_SYS_1_REG          (DR_REG_EFUSE_BASE + 0x48)
+/* EFUSE_MAC_EXT : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: Stores the extended bits of MAC address..*/
+#define EFUSE_MAC_EXT    0x0000FFFF
+#define EFUSE_MAC_EXT_M  ((EFUSE_MAC_EXT_V)<<(EFUSE_MAC_EXT_S))
+#define EFUSE_MAC_EXT_V  0xFFFF
+#define EFUSE_MAC_EXT_S  16
+/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Stores the high 16 bits of MAC address..*/
+#define EFUSE_MAC_1    0x0000FFFF
+#define EFUSE_MAC_1_M  ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S))
+#define EFUSE_MAC_1_V  0xFFFF
+#define EFUSE_MAC_1_S  0
+
+#define EFUSE_RD_MAC_SYS_2_REG          (DR_REG_EFUSE_BASE + 0x4C)
+/* EFUSE_MAC_RESERVED_0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */
+/*description: Reserved..*/
+#define EFUSE_MAC_RESERVED_0    0x0003FFFF
+#define EFUSE_MAC_RESERVED_0_M  ((EFUSE_MAC_RESERVED_0_V)<<(EFUSE_MAC_RESERVED_0_S))
+#define EFUSE_MAC_RESERVED_0_V  0x3FFFF
+#define EFUSE_MAC_RESERVED_0_S  14
+/* EFUSE_MAC_RESERVED_1 : RO ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: Reserved..*/
+#define EFUSE_MAC_RESERVED_1    0x00003FFF
+#define EFUSE_MAC_RESERVED_1_M  ((EFUSE_MAC_RESERVED_1_V)<<(EFUSE_MAC_RESERVED_1_S))
+#define EFUSE_MAC_RESERVED_1_V  0x3FFF
+#define EFUSE_MAC_RESERVED_1_S  0
+
+#define EFUSE_RD_MAC_SYS_3_REG          (DR_REG_EFUSE_BASE + 0x50)
+/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
+/*description: Stores the first 14 bits of the zeroth part of system data..*/
+#define EFUSE_SYS_DATA_PART0_0    0x00003FFF
+#define EFUSE_SYS_DATA_PART0_0_M  ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
+#define EFUSE_SYS_DATA_PART0_0_V  0x3FFF
+#define EFUSE_SYS_DATA_PART0_0_S  18
+/* EFUSE_MAC_RESERVED_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: Reserved..*/
+#define EFUSE_MAC_RESERVED_2    0x0003FFFF
+#define EFUSE_MAC_RESERVED_2_M  ((EFUSE_MAC_RESERVED_2_V)<<(EFUSE_MAC_RESERVED_2_S))
+#define EFUSE_MAC_RESERVED_2_V  0x3FFFF
+#define EFUSE_MAC_RESERVED_2_S  0
+
+#define EFUSE_RD_MAC_SYS_4_REG          (DR_REG_EFUSE_BASE + 0x54)
+/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of the zeroth part of system data..*/
+#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_M  ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_S  0
+
+#define EFUSE_RD_MAC_SYS_5_REG          (DR_REG_EFUSE_BASE + 0x58)
+/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of the zeroth part of system data..*/
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_M  ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S))
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x5C)
+/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_0_M  ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S))
+#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_0_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x60)
+/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_1_M  ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S))
+#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_1_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x64)
+/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_2_M  ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S))
+#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_2_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA3_REG          (DR_REG_EFUSE_BASE + 0x68)
+/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_3_M  ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S))
+#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_3_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA4_REG          (DR_REG_EFUSE_BASE + 0x6C)
+/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_4_M  ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S))
+#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_4_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA5_REG          (DR_REG_EFUSE_BASE + 0x70)
+/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_5_M  ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S))
+#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_5_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA6_REG          (DR_REG_EFUSE_BASE + 0x74)
+/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_6_M  ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S))
+#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_6_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA7_REG          (DR_REG_EFUSE_BASE + 0x78)
+/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of the first part of system data..*/
+#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_7_M  ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S))
+#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_7_S  0
+
+#define EFUSE_RD_USR_DATA0_REG          (DR_REG_EFUSE_BASE + 0x7C)
+/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA0    0xFFFFFFFF
+#define EFUSE_USR_DATA0_M  ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S))
+#define EFUSE_USR_DATA0_V  0xFFFFFFFF
+#define EFUSE_USR_DATA0_S  0
+
+#define EFUSE_RD_USR_DATA1_REG          (DR_REG_EFUSE_BASE + 0x80)
+/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA1    0xFFFFFFFF
+#define EFUSE_USR_DATA1_M  ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S))
+#define EFUSE_USR_DATA1_V  0xFFFFFFFF
+#define EFUSE_USR_DATA1_S  0
+
+#define EFUSE_RD_USR_DATA2_REG          (DR_REG_EFUSE_BASE + 0x84)
+/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA2    0xFFFFFFFF
+#define EFUSE_USR_DATA2_M  ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S))
+#define EFUSE_USR_DATA2_V  0xFFFFFFFF
+#define EFUSE_USR_DATA2_S  0
+
+#define EFUSE_RD_USR_DATA3_REG          (DR_REG_EFUSE_BASE + 0x88)
+/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA3    0xFFFFFFFF
+#define EFUSE_USR_DATA3_M  ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S))
+#define EFUSE_USR_DATA3_V  0xFFFFFFFF
+#define EFUSE_USR_DATA3_S  0
+
+#define EFUSE_RD_USR_DATA4_REG          (DR_REG_EFUSE_BASE + 0x8C)
+/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA4    0xFFFFFFFF
+#define EFUSE_USR_DATA4_M  ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S))
+#define EFUSE_USR_DATA4_V  0xFFFFFFFF
+#define EFUSE_USR_DATA4_S  0
+
+#define EFUSE_RD_USR_DATA5_REG          (DR_REG_EFUSE_BASE + 0x90)
+/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA5    0xFFFFFFFF
+#define EFUSE_USR_DATA5_M  ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S))
+#define EFUSE_USR_DATA5_V  0xFFFFFFFF
+#define EFUSE_USR_DATA5_S  0
+
+#define EFUSE_RD_USR_DATA6_REG          (DR_REG_EFUSE_BASE + 0x94)
+/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA6    0xFFFFFFFF
+#define EFUSE_USR_DATA6_M  ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S))
+#define EFUSE_USR_DATA6_V  0xFFFFFFFF
+#define EFUSE_USR_DATA6_S  0
+
+#define EFUSE_RD_USR_DATA7_REG          (DR_REG_EFUSE_BASE + 0x98)
+/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of BLOCK3 (user)..*/
+#define EFUSE_USR_DATA7    0xFFFFFFFF
+#define EFUSE_USR_DATA7_M  ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S))
+#define EFUSE_USR_DATA7_V  0xFFFFFFFF
+#define EFUSE_USR_DATA7_S  0
+
+#define EFUSE_RD_KEY0_DATA0_REG          (DR_REG_EFUSE_BASE + 0x9C)
+/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA0    0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_M  ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S))
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_S  0
+
+#define EFUSE_RD_KEY0_DATA1_REG          (DR_REG_EFUSE_BASE + 0xA0)
+/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA1    0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_M  ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S))
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_S  0
+
+#define EFUSE_RD_KEY0_DATA2_REG          (DR_REG_EFUSE_BASE + 0xA4)
+/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA2    0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_M  ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S))
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_S  0
+
+#define EFUSE_RD_KEY0_DATA3_REG          (DR_REG_EFUSE_BASE + 0xA8)
+/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA3    0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_M  ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S))
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_S  0
+
+#define EFUSE_RD_KEY0_DATA4_REG          (DR_REG_EFUSE_BASE + 0xAC)
+/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA4    0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_M  ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S))
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_S  0
+
+#define EFUSE_RD_KEY0_DATA5_REG          (DR_REG_EFUSE_BASE + 0xB0)
+/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA5    0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_M  ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S))
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_S  0
+
+#define EFUSE_RD_KEY0_DATA6_REG          (DR_REG_EFUSE_BASE + 0xB4)
+/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA6    0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_M  ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S))
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_S  0
+
+#define EFUSE_RD_KEY0_DATA7_REG          (DR_REG_EFUSE_BASE + 0xB8)
+/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY0..*/
+#define EFUSE_KEY0_DATA7    0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_M  ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S))
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_S  0
+
+#define EFUSE_RD_KEY1_DATA0_REG          (DR_REG_EFUSE_BASE + 0xBC)
+/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA0    0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_M  ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S))
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_S  0
+
+#define EFUSE_RD_KEY1_DATA1_REG          (DR_REG_EFUSE_BASE + 0xC0)
+/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA1    0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_M  ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S))
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_S  0
+
+#define EFUSE_RD_KEY1_DATA2_REG          (DR_REG_EFUSE_BASE + 0xC4)
+/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA2    0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_M  ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S))
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_S  0
+
+#define EFUSE_RD_KEY1_DATA3_REG          (DR_REG_EFUSE_BASE + 0xC8)
+/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA3    0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_M  ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S))
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_S  0
+
+#define EFUSE_RD_KEY1_DATA4_REG          (DR_REG_EFUSE_BASE + 0xCC)
+/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA4    0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_M  ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S))
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_S  0
+
+#define EFUSE_RD_KEY1_DATA5_REG          (DR_REG_EFUSE_BASE + 0xD0)
+/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA5    0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_M  ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S))
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_S  0
+
+#define EFUSE_RD_KEY1_DATA6_REG          (DR_REG_EFUSE_BASE + 0xD4)
+/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA6    0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_M  ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S))
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_S  0
+
+#define EFUSE_RD_KEY1_DATA7_REG          (DR_REG_EFUSE_BASE + 0xD8)
+/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY1..*/
+#define EFUSE_KEY1_DATA7    0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_M  ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S))
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_S  0
+
+#define EFUSE_RD_KEY2_DATA0_REG          (DR_REG_EFUSE_BASE + 0xDC)
+/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA0    0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_M  ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S))
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_S  0
+
+#define EFUSE_RD_KEY2_DATA1_REG          (DR_REG_EFUSE_BASE + 0xE0)
+/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA1    0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_M  ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S))
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_S  0
+
+#define EFUSE_RD_KEY2_DATA2_REG          (DR_REG_EFUSE_BASE + 0xE4)
+/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA2    0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_M  ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S))
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_S  0
+
+#define EFUSE_RD_KEY2_DATA3_REG          (DR_REG_EFUSE_BASE + 0xE8)
+/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA3    0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_M  ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S))
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_S  0
+
+#define EFUSE_RD_KEY2_DATA4_REG          (DR_REG_EFUSE_BASE + 0xEC)
+/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA4    0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_M  ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S))
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_S  0
+
+#define EFUSE_RD_KEY2_DATA5_REG          (DR_REG_EFUSE_BASE + 0xF0)
+/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA5    0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_M  ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S))
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_S  0
+
+#define EFUSE_RD_KEY2_DATA6_REG          (DR_REG_EFUSE_BASE + 0xF4)
+/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA6    0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_M  ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S))
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_S  0
+
+#define EFUSE_RD_KEY2_DATA7_REG          (DR_REG_EFUSE_BASE + 0xF8)
+/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY2..*/
+#define EFUSE_KEY2_DATA7    0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_M  ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S))
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_S  0
+
+#define EFUSE_RD_KEY3_DATA0_REG          (DR_REG_EFUSE_BASE + 0xFC)
+/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA0    0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_M  ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S))
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_S  0
+
+#define EFUSE_RD_KEY3_DATA1_REG          (DR_REG_EFUSE_BASE + 0x100)
+/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA1    0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_M  ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S))
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_S  0
+
+#define EFUSE_RD_KEY3_DATA2_REG          (DR_REG_EFUSE_BASE + 0x104)
+/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA2    0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_M  ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S))
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_S  0
+
+#define EFUSE_RD_KEY3_DATA3_REG          (DR_REG_EFUSE_BASE + 0x108)
+/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA3    0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_M  ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S))
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_S  0
+
+#define EFUSE_RD_KEY3_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10C)
+/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA4    0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_M  ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S))
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_S  0
+
+#define EFUSE_RD_KEY3_DATA5_REG          (DR_REG_EFUSE_BASE + 0x110)
+/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA5    0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_M  ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S))
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_S  0
+
+#define EFUSE_RD_KEY3_DATA6_REG          (DR_REG_EFUSE_BASE + 0x114)
+/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA6    0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_M  ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S))
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_S  0
+
+#define EFUSE_RD_KEY3_DATA7_REG          (DR_REG_EFUSE_BASE + 0x118)
+/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY3..*/
+#define EFUSE_KEY3_DATA7    0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_M  ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S))
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_S  0
+
+#define EFUSE_RD_KEY4_DATA0_REG          (DR_REG_EFUSE_BASE + 0x11C)
+/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA0    0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_M  ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S))
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_S  0
+
+#define EFUSE_RD_KEY4_DATA1_REG          (DR_REG_EFUSE_BASE + 0x120)
+/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA1    0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_M  ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S))
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_S  0
+
+#define EFUSE_RD_KEY4_DATA2_REG          (DR_REG_EFUSE_BASE + 0x124)
+/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA2    0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_M  ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S))
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_S  0
+
+#define EFUSE_RD_KEY4_DATA3_REG          (DR_REG_EFUSE_BASE + 0x128)
+/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA3    0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_M  ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S))
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_S  0
+
+#define EFUSE_RD_KEY4_DATA4_REG          (DR_REG_EFUSE_BASE + 0x12C)
+/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA4    0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_M  ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S))
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_S  0
+
+#define EFUSE_RD_KEY4_DATA5_REG          (DR_REG_EFUSE_BASE + 0x130)
+/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA5    0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_M  ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S))
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_S  0
+
+#define EFUSE_RD_KEY4_DATA6_REG          (DR_REG_EFUSE_BASE + 0x134)
+/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA6    0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_M  ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S))
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_S  0
+
+#define EFUSE_RD_KEY4_DATA7_REG          (DR_REG_EFUSE_BASE + 0x138)
+/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY4..*/
+#define EFUSE_KEY4_DATA7    0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_M  ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S))
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_S  0
+
+#define EFUSE_RD_KEY5_DATA0_REG          (DR_REG_EFUSE_BASE + 0x13C)
+/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA0    0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_M  ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S))
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_S  0
+
+#define EFUSE_RD_KEY5_DATA1_REG          (DR_REG_EFUSE_BASE + 0x140)
+/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA1    0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_M  ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S))
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_S  0
+
+#define EFUSE_RD_KEY5_DATA2_REG          (DR_REG_EFUSE_BASE + 0x144)
+/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA2    0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_M  ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S))
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_S  0
+
+#define EFUSE_RD_KEY5_DATA3_REG          (DR_REG_EFUSE_BASE + 0x148)
+/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA3    0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_M  ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S))
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_S  0
+
+#define EFUSE_RD_KEY5_DATA4_REG          (DR_REG_EFUSE_BASE + 0x14C)
+/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA4    0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_M  ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S))
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_S  0
+
+#define EFUSE_RD_KEY5_DATA5_REG          (DR_REG_EFUSE_BASE + 0x150)
+/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA5    0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_M  ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S))
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_S  0
+
+#define EFUSE_RD_KEY5_DATA6_REG          (DR_REG_EFUSE_BASE + 0x154)
+/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA6    0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_M  ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S))
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_S  0
+
+#define EFUSE_RD_KEY5_DATA7_REG          (DR_REG_EFUSE_BASE + 0x158)
+/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY5..*/
+#define EFUSE_KEY5_DATA7    0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_M  ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S))
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x15C)
+/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_0_M  ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S))
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x160)
+/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_1_M  ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S))
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x164)
+/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_2_M  ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S))
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x168)
+/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_3_M  ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S))
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x16C)
+/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_4_M  ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S))
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x170)
+/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_5_M  ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S))
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x174)
+/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_6_M  ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S))
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x178)
+/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_7_M  ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S))
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+#define EFUSE_RD_REPEAT_ERR0_REG          (DR_REG_EFUSE_BASE + 0x17C)
+/* EFUSE_HUK_GEN_STATE_LOW_ERR : RO ;bitpos:[31:26] ;default: 6'h0 ; */
+/*description: Indicates a programming error of HUK_GEN_STATE_LOW..*/
+#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003F
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  ((EFUSE_HUK_GEN_STATE_LOW_ERR_V)<<(EFUSE_HUK_GEN_STATE_LOW_ERR_S))
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x3F
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
+/* EFUSE_USB_PHY_SEL_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Indicates a programming error of USB_PHY_SEL..*/
+#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_M  (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_V  0x1
+#define EFUSE_USB_PHY_SEL_ERR_S  25
+/* EFUSE_USB_OTG11_DREFH_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: Indicates a programming error of USB_OTG11_DREFH..*/
+#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003
+#define EFUSE_USB_OTG11_DREFH_ERR_M  ((EFUSE_USB_OTG11_DREFH_ERR_V)<<(EFUSE_USB_OTG11_DREFH_ERR_S))
+#define EFUSE_USB_OTG11_DREFH_ERR_V  0x3
+#define EFUSE_USB_OTG11_DREFH_ERR_S  23
+/* EFUSE_USB_DEVICE_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: Indicates a programming error of USB_DEVICE_DREFH..*/
+#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003
+#define EFUSE_USB_DEVICE_DREFH_ERR_M  ((EFUSE_USB_DEVICE_DREFH_ERR_V)<<(EFUSE_USB_DEVICE_DREFH_ERR_S))
+#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x3
+#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT..*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_PAD_JTAG..*/
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x1
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: Indicates a programming error of SOFT_DIS_JTAG..*/
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S))
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Indicates a programming error of JTAG_SEL_ENABLE..*/
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x1
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_TWAI..*/
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_V  0x1
+#define EFUSE_DIS_TWAI_ERR_S  14
+/* EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS..*/
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x1
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_FORCE_DOWNLOAD..*/
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/* EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG..*/
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x1
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
+/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Indicates a programming error of POWERGLITCH_EN..*/
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (BIT(10))
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x1
+#define EFUSE_POWERGLITCH_EN_ERR_S  10
+/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_USB_JTAG..*/
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x1
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/* EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS..*/
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (BIT(8))
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x1
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
+/* EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS..*/
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (BIT(7))
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x1
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
+/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: Indicates a programming error of RD_DIS..*/
+#define EFUSE_RD_DIS_ERR    0x0000007F
+#define EFUSE_RD_DIS_ERR_M  ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S))
+#define EFUSE_RD_DIS_ERR_V  0x7F
+#define EFUSE_RD_DIS_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR1_REG          (DR_REG_EFUSE_BASE + 0x180)
+/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Indicates a programming error of KEY_PURPOSE_1..*/
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000F
+#define EFUSE_KEY_PURPOSE_1_ERR_M  ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S))
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: Indicates a programming error of KEY_PURPOSE_0..*/
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000F
+#define EFUSE_KEY_PURPOSE_0_ERR_M  ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S))
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE2..*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE1..*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE0..*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: Indicates a programming error of SPI_BOOT_CRYPT_CNT..*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: Indicates a programming error of WDT_DELAY_SEL..*/
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003
+#define EFUSE_WDT_DELAY_SEL_ERR_M  ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S))
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x3
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/* EFUSE_XTS_KEY_LENGTH_256_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Indicates a programming error of XTS_KEY_LENGTH_256..*/
+#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x1
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
+/* EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO ;bitpos:[13] ;default: 3'h0 ; */
+/*description: Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY..*/
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x1
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
+/* EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO ;bitpos:[12:9] ;default: 4'h0 ; */
+/*description: Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY..*/
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000F
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  ((EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V)<<(EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S))
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0xF
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
+/* EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO ;bitpos:[8:5] ;default: 4'h0 ; */
+/*description: Indicates a programming error of KM_DEPLOY_ONLY_ONCE..*/
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000F
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  ((EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V)<<(EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S))
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0xF
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
+/* EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: Indicates a programming error of KM_RND_SWITCH_CYCLE..*/
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  ((EFUSE_KM_RND_SWITCH_CYCLE_ERR_V)<<(EFUSE_KM_RND_SWITCH_CYCLE_ERR_S))
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x3
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
+/* EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: Indicates a programming error of HUK_GEN_STATE_HIGH..*/
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  ((EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V)<<(EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S))
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x7
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR2_REG          (DR_REG_EFUSE_BASE + 0x184)
+/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Indicates a programming error of FLASH_TPUW..*/
+#define EFUSE_FLASH_TPUW_ERR    0x0000000F
+#define EFUSE_FLASH_TPUW_ERR_M  ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S))
+#define EFUSE_FLASH_TPUW_ERR_V  0xF
+#define EFUSE_FLASH_TPUW_ERR_S  28
+/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE..*/
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
+/* EFUSE_FLASH_ECC_EN_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Indicates a programming error of FLASH_ECC_EN..*/
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (BIT(26))
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x1
+#define EFUSE_FLASH_ECC_EN_ERR_S  26
+/* EFUSE_FLASH_PAGE_SIZE_ERR : RO ;bitpos:[25:24] ;default: 2'b0 ; */
+/*description: Indicates a programming error of FLASH_PAGE_SIZE..*/
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  ((EFUSE_FLASH_PAGE_SIZE_ERR_V)<<(EFUSE_FLASH_PAGE_SIZE_ERR_S))
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
+/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Indicates a programming error of FLASH_TYPE..*/
+#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
+#define EFUSE_FLASH_TYPE_ERR_M  (BIT(23))
+#define EFUSE_FLASH_TYPE_ERR_V  0x1
+#define EFUSE_FLASH_TYPE_ERR_S  23
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE..*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Indicates a programming error of SECURE_BOOT_EN..*/
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/* EFUSE_CRYPT_DPA_ENABLE_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Indicates a programming error of CRYPT_DPA_ENABLE..*/
+#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x1
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/* EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K..*/
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x1
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
+/* EFUSE_SEC_DPA_LEVEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: Indicates a programming error of SEC_DPA_LEVEL..*/
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  ((EFUSE_SEC_DPA_LEVEL_ERR_V)<<(EFUSE_SEC_DPA_LEVEL_ERR_S))
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x3
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: Indicates a programming error of KEY_PURPOSE_5..*/
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000F
+#define EFUSE_KEY_PURPOSE_5_ERR_M  ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S))
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: Indicates a programming error of KEY_PURPOSE_4..*/
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000F
+#define EFUSE_KEY_PURPOSE_4_ERR_M  ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S))
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: Indicates a programming error of KEY_PURPOSE_3..*/
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000F
+#define EFUSE_KEY_PURPOSE_3_ERR_M  ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S))
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Indicates a programming error of KEY_PURPOSE_2..*/
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000F
+#define EFUSE_KEY_PURPOSE_2_ERR_M  ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S))
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR3_REG          (DR_REG_EFUSE_BASE + 0x188)
+/* EFUSE_DCDC_VSET_ERR : RO ;bitpos:[31:27] ;default: 5'h0 ; */
+/*description: Indicates a programming error of DCDC_VSET..*/
+#define EFUSE_DCDC_VSET_ERR    0x0000001F
+#define EFUSE_DCDC_VSET_ERR_M  ((EFUSE_DCDC_VSET_ERR_V)<<(EFUSE_DCDC_VSET_ERR_S))
+#define EFUSE_DCDC_VSET_ERR_V  0x1F
+#define EFUSE_DCDC_VSET_ERR_S  27
+/* EFUSE_HYS_EN_PAD_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Indicates a programming error of HYS_EN_PAD..*/
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
+#define EFUSE_HYS_EN_PAD_ERR_M  (BIT(26))
+#define EFUSE_HYS_EN_PAD_ERR_V  0x1
+#define EFUSE_HYS_EN_PAD_ERR_S  26
+/* EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE..*/
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
+/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[24:9] ;default: 16'h0 ; */
+/*description: Indicates a programming error of SECURE VERSION..*/
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFF
+#define EFUSE_SECURE_VERSION_ERR_M  ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S))
+#define EFUSE_SECURE_VERSION_ERR_V  0xFFFF
+#define EFUSE_SECURE_VERSION_ERR_S  9
+/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Indicates a programming error of FORCE_SEND_RESUME..*/
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
+/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: Indicates a programming error of UART_PRINT_CONTROL..*/
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S))
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Indicates a programming error of ENABLE_SECURITY_DOWNLOAD..*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE..*/
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/* EFUSE_LOCK_KM_KEY_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: TBD.*/
+#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_ERR_M  (BIT(3))
+#define EFUSE_LOCK_KM_KEY_ERR_V  0x1
+#define EFUSE_LOCK_KM_KEY_ERR_S  3
+/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR..*/
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x1
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
+/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_DIRECT_BOOT..*/
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x1
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_DOWNLOAD_MODE..*/
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR4_REG          (DR_REG_EFUSE_BASE + 0x18C)
+/* EFUSE_DIS_SWD_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_SWD..*/
+#define EFUSE_DIS_SWD_ERR    (BIT(21))
+#define EFUSE_DIS_SWD_ERR_M  (BIT(21))
+#define EFUSE_DIS_SWD_ERR_V  0x1
+#define EFUSE_DIS_SWD_ERR_S  21
+/* EFUSE_DIS_WDT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DIS_WDT..*/
+#define EFUSE_DIS_WDT_ERR    (BIT(20))
+#define EFUSE_DIS_WDT_ERR_M  (BIT(20))
+#define EFUSE_DIS_WDT_ERR_V  0x1
+#define EFUSE_DIS_WDT_ERR_S  20
+/* EFUSE_DCDC_VSET_EN_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Indicates a programming error of DCDC_VSET_EN..*/
+#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_ERR_M  (BIT(19))
+#define EFUSE_DCDC_VSET_EN_ERR_V  0x1
+#define EFUSE_DCDC_VSET_EN_ERR_S  19
+/* EFUSE_HP_PWR_SRC_SEL_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Indicates a programming error of HP_PWR_SRC_SEL..*/
+#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x1
+#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
+/* EFUSE_USB_OTG11_DREFL_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: Indicates a programming error of USB_OTG11_DREFL..*/
+#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003
+#define EFUSE_USB_OTG11_DREFL_ERR_M  ((EFUSE_USB_OTG11_DREFL_ERR_V)<<(EFUSE_USB_OTG11_DREFL_ERR_S))
+#define EFUSE_USB_OTG11_DREFL_ERR_V  0x3
+#define EFUSE_USB_OTG11_DREFL_ERR_S  14
+/* EFUSE_USB_DEVICE_DREFL_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: Indicates a programming error of USB_DEVICE_DREFL..*/
+#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003
+#define EFUSE_USB_DEVICE_DREFL_ERR_M  ((EFUSE_USB_DEVICE_DREFL_ERR_V)<<(EFUSE_USB_DEVICE_DREFL_ERR_S))
+#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x3
+#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
+/* EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: TBD..*/
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000F
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  ((EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V)<<(EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S))
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0xF
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
+/* EFUSE_0PXA_TIEH_SEL_3_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: Indicates a programming error of 0PXA_TIEH_SEL_3..*/
+#define EFUSE_0PXA_TIEH_SEL_3_ERR    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_3_ERR_M  ((EFUSE_0PXA_TIEH_SEL_3_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_3_ERR_S))
+#define EFUSE_0PXA_TIEH_SEL_3_ERR_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_3_ERR_S  6
+/* EFUSE_0PXA_TIEH_SEL_2_ERR : RO ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: Indicates a programming error of 0PXA_TIEH_SEL_2..*/
+#define EFUSE_0PXA_TIEH_SEL_2_ERR    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_2_ERR_M  ((EFUSE_0PXA_TIEH_SEL_2_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_2_ERR_S))
+#define EFUSE_0PXA_TIEH_SEL_2_ERR_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_2_ERR_S  4
+/* EFUSE_0PXA_TIEH_SEL_1_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: Indicates a programming error of 0PXA_TIEH_SEL_1..*/
+#define EFUSE_0PXA_TIEH_SEL_1_ERR    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_1_ERR_M  ((EFUSE_0PXA_TIEH_SEL_1_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_1_ERR_S))
+#define EFUSE_0PXA_TIEH_SEL_1_ERR_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_1_ERR_S  2
+/* EFUSE_0PXA_TIEH_SEL_0_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: Indicates a programming error of 0PXA_TIEH_SEL_0..*/
+#define EFUSE_0PXA_TIEH_SEL_0_ERR    0x00000003
+#define EFUSE_0PXA_TIEH_SEL_0_ERR_M  ((EFUSE_0PXA_TIEH_SEL_0_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_0_ERR_S))
+#define EFUSE_0PXA_TIEH_SEL_0_ERR_V  0x3
+#define EFUSE_0PXA_TIEH_SEL_0_ERR_S  0
+
+#define EFUSE_RD_RS_ERR0_REG          (DR_REG_EFUSE_BASE + 0x1C0)
+/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key4 is reliable 1: Means that programm
+ing key4 failed and the number of error bytes is over 6..*/
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (BIT(31))
+#define EFUSE_KEY4_FAIL_V  0x1
+#define EFUSE_KEY4_FAIL_S  31
+/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_KEY4_ERR_NUM    0x00000007
+#define EFUSE_KEY4_ERR_NUM_M  ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S))
+#define EFUSE_KEY4_ERR_NUM_V  0x7
+#define EFUSE_KEY4_ERR_NUM_S  28
+/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key3 is reliable 1: Means that programm
+ing key3 failed and the number of error bytes is over 6..*/
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (BIT(27))
+#define EFUSE_KEY3_FAIL_V  0x1
+#define EFUSE_KEY3_FAIL_S  27
+/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_KEY3_ERR_NUM    0x00000007
+#define EFUSE_KEY3_ERR_NUM_M  ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S))
+#define EFUSE_KEY3_ERR_NUM_V  0x7
+#define EFUSE_KEY3_ERR_NUM_S  24
+/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key2 is reliable 1: Means that programm
+ing key2 failed and the number of error bytes is over 6..*/
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (BIT(23))
+#define EFUSE_KEY2_FAIL_V  0x1
+#define EFUSE_KEY2_FAIL_S  23
+/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_KEY2_ERR_NUM    0x00000007
+#define EFUSE_KEY2_ERR_NUM_M  ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S))
+#define EFUSE_KEY2_ERR_NUM_V  0x7
+#define EFUSE_KEY2_ERR_NUM_S  20
+/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key1 is reliable 1: Means that programm
+ing key1 failed and the number of error bytes is over 6..*/
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (BIT(19))
+#define EFUSE_KEY1_FAIL_V  0x1
+#define EFUSE_KEY1_FAIL_S  19
+/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_KEY1_ERR_NUM    0x00000007
+#define EFUSE_KEY1_ERR_NUM_M  ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S))
+#define EFUSE_KEY1_ERR_NUM_V  0x7
+#define EFUSE_KEY1_ERR_NUM_S  16
+/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key0 is reliable 1: Means that programm
+ing key0 failed and the number of error bytes is over 6..*/
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (BIT(15))
+#define EFUSE_KEY0_FAIL_V  0x1
+#define EFUSE_KEY0_FAIL_S  15
+/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_KEY0_ERR_NUM    0x00000007
+#define EFUSE_KEY0_ERR_NUM_M  ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S))
+#define EFUSE_KEY0_ERR_NUM_V  0x7
+#define EFUSE_KEY0_ERR_NUM_S  12
+/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the user data is reliable 1: Means that programming
+ user data failed and the number of error bytes is over 6..*/
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (BIT(11))
+#define EFUSE_USR_DATA_FAIL_V  0x1
+#define EFUSE_USR_DATA_FAIL_S  11
+/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007
+#define EFUSE_USR_DATA_ERR_NUM_M  ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S))
+#define EFUSE_USR_DATA_ERR_NUM_V  0x7
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of system part1 is reliable 1: Means that
+programming user data failed and the number of error bytes is over 6..*/
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_V  0x1
+#define EFUSE_SYS_PART1_FAIL_S  7
+/* EFUSE_SYS_PART1_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_SYS_PART1_ERR_NUM    0x00000007
+#define EFUSE_SYS_PART1_ERR_NUM_M  ((EFUSE_SYS_PART1_ERR_NUM_V)<<(EFUSE_SYS_PART1_ERR_NUM_S))
+#define EFUSE_SYS_PART1_ERR_NUM_V  0x7
+#define EFUSE_SYS_PART1_ERR_NUM_S  4
+/* EFUSE_MAC_SYS_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that pr
+ogramming user data failed and the number of error bytes is over 6..*/
+#define EFUSE_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_MAC_SYS_FAIL_M  (BIT(3))
+#define EFUSE_MAC_SYS_FAIL_V  0x1
+#define EFUSE_MAC_SYS_FAIL_S  3
+/* EFUSE_MAC_SYS_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_MAC_SYS_ERR_NUM    0x00000007
+#define EFUSE_MAC_SYS_ERR_NUM_M  ((EFUSE_MAC_SYS_ERR_NUM_V)<<(EFUSE_MAC_SYS_ERR_NUM_S))
+#define EFUSE_MAC_SYS_ERR_NUM_V  0x7
+#define EFUSE_MAC_SYS_ERR_NUM_S  0
+
+#define EFUSE_RD_RS_ERR1_REG          (DR_REG_EFUSE_BASE + 0x1C4)
+/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of system part2 is reliable 1: Means that
+programming user data failed and the number of error bytes is over 6..*/
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_V  0x1
+#define EFUSE_SYS_PART2_FAIL_S  7
+/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007
+#define EFUSE_SYS_PART2_ERR_NUM_M  ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S))
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x7
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key5 is reliable 1: Means that programm
+ing key5 failed and the number of error bytes is over 6..*/
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (BIT(3))
+#define EFUSE_KEY5_FAIL_V  0x1
+#define EFUSE_KEY5_FAIL_S  3
+/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes..*/
+#define EFUSE_KEY5_ERR_NUM    0x00000007
+#define EFUSE_KEY5_ERR_NUM_M  ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S))
+#define EFUSE_KEY5_ERR_NUM_V  0x7
+#define EFUSE_KEY5_ERR_NUM_S  0
+
+#define EFUSE_CLK_REG          (DR_REG_EFUSE_BASE + 0x1C8)
+/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to force enable eFuse register configuration clock signal..*/
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (BIT(16))
+#define EFUSE_CLK_EN_V  0x1
+#define EFUSE_CLK_EN_S  16
+/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to force eFuse SRAM into working mode..*/
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (BIT(2))
+#define EFUSE_MEM_FORCE_PU_V  0x1
+#define EFUSE_MEM_FORCE_PU_S  2
+/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x1
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to force eFuse SRAM into power-saving mode..*/
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (BIT(0))
+#define EFUSE_MEM_FORCE_PD_V  0x1
+#define EFUSE_MEM_FORCE_PD_S  0
+
+#define EFUSE_CONF_REG          (DR_REG_EFUSE_BASE + 0x1CC)
+/* EFUSE_CFG_ECDSA_BLK : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: Configures which block to use for ECDSA key output..*/
+#define EFUSE_CFG_ECDSA_BLK    0x0000000F
+#define EFUSE_CFG_ECDSA_BLK_M  ((EFUSE_CFG_ECDSA_BLK_V)<<(EFUSE_CFG_ECDSA_BLK_S))
+#define EFUSE_CFG_ECDSA_BLK_V  0xF
+#define EFUSE_CFG_ECDSA_BLK_S  16
+/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: 0x5A5A:  programming operation command 0x5AA5: read operation command..*/
+#define EFUSE_OP_CODE    0x0000FFFF
+#define EFUSE_OP_CODE_M  ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
+#define EFUSE_OP_CODE_V  0xFFFF
+#define EFUSE_OP_CODE_S  0
+
+#define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x1D0)
+/* EFUSE_CUR_ECDSA_BLK : RO ;bitpos:[23:20] ;default: 4'h0 ; */
+/*description: Indicates which block is used for ECDSA key output..*/
+#define EFUSE_CUR_ECDSA_BLK    0x0000000F
+#define EFUSE_CUR_ECDSA_BLK_M  ((EFUSE_CUR_ECDSA_BLK_V)<<(EFUSE_CUR_ECDSA_BLK_S))
+#define EFUSE_CUR_ECDSA_BLK_V  0xF
+#define EFUSE_CUR_ECDSA_BLK_S  20
+/* EFUSE_BLK0_VALID_BIT_CNT : RO ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: Indicates the number of block valid bit..*/
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FF
+#define EFUSE_BLK0_VALID_BIT_CNT_M  ((EFUSE_BLK0_VALID_BIT_CNT_V)<<(EFUSE_BLK0_VALID_BIT_CNT_S))
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x3FF
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The value of OTP_VDDQ_IS_SW..*/
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x1
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of OTP_PGENB_SW..*/
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (BIT(8))
+#define EFUSE_OTP_PGENB_SW_V  0x1
+#define EFUSE_OTP_PGENB_SW_S  8
+/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The value of OTP_CSB_SW..*/
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (BIT(7))
+#define EFUSE_OTP_CSB_SW_V  0x1
+#define EFUSE_OTP_CSB_SW_S  7
+/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The value of OTP_STROBE_SW..*/
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (BIT(6))
+#define EFUSE_OTP_STROBE_SW_V  0x1
+#define EFUSE_OTP_STROBE_SW_S  6
+/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The value of OTP_VDDQ_C_SYNC2..*/
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x1
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The value of OTP_LOAD_SW..*/
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (BIT(4))
+#define EFUSE_OTP_LOAD_SW_V  0x1
+#define EFUSE_OTP_LOAD_SW_S  4
+/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Indicates the state of the eFuse state machine..*/
+#define EFUSE_STATE    0x0000000F
+#define EFUSE_STATE_M  ((EFUSE_STATE_V)<<(EFUSE_STATE_S))
+#define EFUSE_STATE_V  0xF
+#define EFUSE_STATE_S  0
+
+#define EFUSE_CMD_REG          (DR_REG_EFUSE_BASE + 0x1D4)
+/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */
+/*description: The serial number of the block to be programmed. Value 0-10 corresponds to block
+ number 0-10, respectively..*/
+#define EFUSE_BLK_NUM    0x0000000F
+#define EFUSE_BLK_NUM_M  ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S))
+#define EFUSE_BLK_NUM_V  0xF
+#define EFUSE_BLK_NUM_S  2
+/* EFUSE_PGM_CMD : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to send programming command..*/
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (BIT(1))
+#define EFUSE_PGM_CMD_V  0x1
+#define EFUSE_PGM_CMD_S  1
+/* EFUSE_READ_CMD : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to send read command..*/
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (BIT(0))
+#define EFUSE_READ_CMD_V  0x1
+#define EFUSE_READ_CMD_S  0
+
+#define EFUSE_INT_RAW_REG          (DR_REG_EFUSE_BASE + 0x1D8)
+/* EFUSE_PGM_DONE_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_V  0x1
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+/* EFUSE_READ_DONE_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_V  0x1
+#define EFUSE_READ_DONE_INT_RAW_S  0
+
+#define EFUSE_INT_ST_REG          (DR_REG_EFUSE_BASE + 0x1DC)
+/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_V  0x1
+#define EFUSE_PGM_DONE_INT_ST_S  1
+/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_V  0x1
+#define EFUSE_READ_DONE_INT_ST_S  0
+
+#define EFUSE_INT_ENA_REG          (DR_REG_EFUSE_BASE + 0x1E0)
+/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_V  0x1
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_V  0x1
+#define EFUSE_READ_DONE_INT_ENA_S  0
+
+#define EFUSE_INT_CLR_REG          (DR_REG_EFUSE_BASE + 0x1E4)
+/* EFUSE_PGM_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_V  0x1
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+/* EFUSE_READ_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_V  0x1
+#define EFUSE_READ_DONE_INT_CLR_S  0
+
+#define EFUSE_DAC_CONF_REG          (DR_REG_EFUSE_BASE + 0x1E8)
+/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Reduces the power supply of the programming voltage..*/
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (BIT(17))
+#define EFUSE_OE_CLR_V  0x1
+#define EFUSE_OE_CLR_S  17
+/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */
+/*description: Controls the rising period of the programming voltage..*/
+#define EFUSE_DAC_NUM    0x000000FF
+#define EFUSE_DAC_NUM_M  ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S))
+#define EFUSE_DAC_NUM_V  0xFF
+#define EFUSE_DAC_NUM_S  9
+/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Don't care..*/
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x1
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd23 ; */
+/*description: Controls the division factor of the rising clock of the programming voltage..*/
+#define EFUSE_DAC_CLK_DIV    0x000000FF
+#define EFUSE_DAC_CLK_DIV_M  ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
+#define EFUSE_DAC_CLK_DIV_V  0xFF
+#define EFUSE_DAC_CLK_DIV_S  0
+
+#define EFUSE_RD_TIM_CONF_REG          (DR_REG_EFUSE_BASE + 0x1EC)
+/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'hf ; */
+/*description: Configures the waiting time of reading eFuse memory..*/
+#define EFUSE_READ_INIT_NUM    0x000000FF
+#define EFUSE_READ_INIT_NUM_M  ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S))
+#define EFUSE_READ_INIT_NUM_V  0xFF
+#define EFUSE_READ_INIT_NUM_S  24
+/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
+/*description: Configures the read setup time..*/
+#define EFUSE_TSUR_A    0x000000FF
+#define EFUSE_TSUR_A_M  ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S))
+#define EFUSE_TSUR_A_V  0xFF
+#define EFUSE_TSUR_A_S  16
+/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
+/*description: Configures the read time..*/
+#define EFUSE_TRD    0x000000FF
+#define EFUSE_TRD_M  ((EFUSE_TRD_V)<<(EFUSE_TRD_S))
+#define EFUSE_TRD_V  0xFF
+#define EFUSE_TRD_S  8
+/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: Configures the read hold time..*/
+#define EFUSE_THR_A    0x000000FF
+#define EFUSE_THR_A_M  ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S))
+#define EFUSE_THR_A_V  0xFF
+#define EFUSE_THR_A_S  0
+
+#define EFUSE_WR_TIM_CONF1_REG          (DR_REG_EFUSE_BASE + 0x1F0)
+/* EFUSE_THP_A : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: Configures the programming hold time..*/
+#define EFUSE_THP_A    0x000000FF
+#define EFUSE_THP_A_M  ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S))
+#define EFUSE_THP_A_V  0xFF
+#define EFUSE_THP_A_S  24
+/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2667 ; */
+/*description: Configures the power up time for VDDQ..*/
+#define EFUSE_PWR_ON_NUM    0x0000FFFF
+#define EFUSE_PWR_ON_NUM_M  ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S))
+#define EFUSE_PWR_ON_NUM_V  0xFFFF
+#define EFUSE_PWR_ON_NUM_S  8
+/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: Configures the programming setup time..*/
+#define EFUSE_TSUP_A    0x000000FF
+#define EFUSE_TSUP_A_M  ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S))
+#define EFUSE_TSUP_A_V  0xFF
+#define EFUSE_TSUP_A_S  0
+
+#define EFUSE_WR_TIM_CONF2_REG          (DR_REG_EFUSE_BASE + 0x1F4)
+/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'ha0 ; */
+/*description: Configures the active programming time..*/
+#define EFUSE_TPGM    0x0000FFFF
+#define EFUSE_TPGM_M  ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S))
+#define EFUSE_TPGM_V  0xFFFF
+#define EFUSE_TPGM_S  16
+/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h140 ; */
+/*description: Configures the power outage time for VDDQ..*/
+#define EFUSE_PWR_OFF_NUM    0x0000FFFF
+#define EFUSE_PWR_OFF_NUM_M  ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S))
+#define EFUSE_PWR_OFF_NUM_V  0xFFFF
+#define EFUSE_PWR_OFF_NUM_S  0
+
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG          (DR_REG_EFUSE_BASE + 0x1F8)
+/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[20:13] ;default: 8'h1 ; */
+/*description: Configures the inactive programming time..*/
+#define EFUSE_TPGM_INACTIVE    0x000000FF
+#define EFUSE_TPGM_INACTIVE_M  ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S))
+#define EFUSE_TPGM_INACTIVE_V  0xFF
+#define EFUSE_TPGM_INACTIVE_S  13
+/* EFUSE_UPDATE : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to update multi-bit register signals..*/
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (BIT(12))
+#define EFUSE_UPDATE_V  0x1
+#define EFUSE_UPDATE_S  12
+/* EFUSE_BYPASS_RS_BLK_NUM : R/W ;bitpos:[11:1] ;default: 11'h0 ; */
+/*description: Configures block number of programming twice operation..*/
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FF
+#define EFUSE_BYPASS_RS_BLK_NUM_M  ((EFUSE_BYPASS_RS_BLK_NUM_V)<<(EFUSE_BYPASS_RS_BLK_NUM_S))
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x7FF
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/* EFUSE_BYPASS_RS_CORRECTION : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to bypass reed solomon correction step..*/
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x1
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+
+#define EFUSE_DATE_REG          (DR_REG_EFUSE_BASE + 0x1FC)
+/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2305050 ; */
+/*description: Stores eFuse version..*/
+#define EFUSE_DATE    0x0FFFFFFF
+#define EFUSE_DATE_M  ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
+#define EFUSE_DATE_V  0xFFFFFFF
+#define EFUSE_DATE_S  0
+
+#define EFUSE_APB2OTP_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x800)
+/* EFUSE_APB2OTP_BLOCK0_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 write disable data..*/
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  ((EFUSE_APB2OTP_BLOCK0_WR_DIS_V)<<(EFUSE_APB2OTP_BLOCK0_WR_DIS_S))
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG          (DR_REG_EFUSE_BASE + 0x804)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup1 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG          (DR_REG_EFUSE_BASE + 0x808)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup1 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG          (DR_REG_EFUSE_BASE + 0x80C)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup1 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG          (DR_REG_EFUSE_BASE + 0x810)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup1 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG          (DR_REG_EFUSE_BASE + 0x814)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup1 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG          (DR_REG_EFUSE_BASE + 0x818)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup2 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG          (DR_REG_EFUSE_BASE + 0x81C)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup2 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG          (DR_REG_EFUSE_BASE + 0x820)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup2 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG          (DR_REG_EFUSE_BASE + 0x824)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup2 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG          (DR_REG_EFUSE_BASE + 0x828)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup2 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG          (DR_REG_EFUSE_BASE + 0x82C)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup3 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG          (DR_REG_EFUSE_BASE + 0x830)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup3 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG          (DR_REG_EFUSE_BASE + 0x834)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup3 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG          (DR_REG_EFUSE_BASE + 0x838)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup3 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG          (DR_REG_EFUSE_BASE + 0x83C)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup3 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG          (DR_REG_EFUSE_BASE + 0x840)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup4 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG          (DR_REG_EFUSE_BASE + 0x844)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup4 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG          (DR_REG_EFUSE_BASE + 0x848)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup4 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG          (DR_REG_EFUSE_BASE + 0x84C)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup4 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
+
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG          (DR_REG_EFUSE_BASE + 0x850)
+/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block0 backup4 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S))
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
+
+#define EFUSE_APB2OTP_BLK1_W1_REG          (DR_REG_EFUSE_BASE + 0x854)
+/* EFUSE_APB2OTP_BLOCK1_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word1 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W1_M  ((EFUSE_APB2OTP_BLOCK1_W1_V)<<(EFUSE_APB2OTP_BLOCK1_W1_S))
+#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W1_S  0
+
+#define EFUSE_APB2OTP_BLK1_W2_REG          (DR_REG_EFUSE_BASE + 0x858)
+/* EFUSE_APB2OTP_BLOCK1_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word2 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W2_M  ((EFUSE_APB2OTP_BLOCK1_W2_V)<<(EFUSE_APB2OTP_BLOCK1_W2_S))
+#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W2_S  0
+
+#define EFUSE_APB2OTP_BLK1_W3_REG          (DR_REG_EFUSE_BASE + 0x85C)
+/* EFUSE_APB2OTP_BLOCK1_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word3 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W3_M  ((EFUSE_APB2OTP_BLOCK1_W3_V)<<(EFUSE_APB2OTP_BLOCK1_W3_S))
+#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W3_S  0
+
+#define EFUSE_APB2OTP_BLK1_W4_REG          (DR_REG_EFUSE_BASE + 0x860)
+/* EFUSE_APB2OTP_BLOCK1_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word4 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W4_M  ((EFUSE_APB2OTP_BLOCK1_W4_V)<<(EFUSE_APB2OTP_BLOCK1_W4_S))
+#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W4_S  0
+
+#define EFUSE_APB2OTP_BLK1_W5_REG          (DR_REG_EFUSE_BASE + 0x864)
+/* EFUSE_APB2OTP_BLOCK1_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word5 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W5_M  ((EFUSE_APB2OTP_BLOCK1_W5_V)<<(EFUSE_APB2OTP_BLOCK1_W5_S))
+#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W5_S  0
+
+#define EFUSE_APB2OTP_BLK1_W6_REG          (DR_REG_EFUSE_BASE + 0x868)
+/* EFUSE_APB2OTP_BLOCK1_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word6 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W6_M  ((EFUSE_APB2OTP_BLOCK1_W6_V)<<(EFUSE_APB2OTP_BLOCK1_W6_S))
+#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W6_S  0
+
+#define EFUSE_APB2OTP_BLK1_W7_REG          (DR_REG_EFUSE_BASE + 0x86C)
+/* EFUSE_APB2OTP_BLOCK1_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word7 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W7_M  ((EFUSE_APB2OTP_BLOCK1_W7_V)<<(EFUSE_APB2OTP_BLOCK1_W7_S))
+#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W7_S  0
+
+#define EFUSE_APB2OTP_BLK1_W8_REG          (DR_REG_EFUSE_BASE + 0x870)
+/* EFUSE_APB2OTP_BLOCK1_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word8 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W8_M  ((EFUSE_APB2OTP_BLOCK1_W8_V)<<(EFUSE_APB2OTP_BLOCK1_W8_S))
+#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W8_S  0
+
+#define EFUSE_APB2OTP_BLK1_W9_REG          (DR_REG_EFUSE_BASE + 0x874)
+/* EFUSE_APB2OTP_BLOCK1_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block1  word9 data..*/
+#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W9_M  ((EFUSE_APB2OTP_BLOCK1_W9_V)<<(EFUSE_APB2OTP_BLOCK1_W9_S))
+#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK1_W9_S  0
+
+#define EFUSE_APB2OTP_BLK2_W1_REG          (DR_REG_EFUSE_BASE + 0x878)
+/* EFUSE_APB2OTP_BLOCK2_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W1_M  ((EFUSE_APB2OTP_BLOCK2_W1_V)<<(EFUSE_APB2OTP_BLOCK2_W1_S))
+#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W1_S  0
+
+#define EFUSE_APB2OTP_BLK2_W2_REG          (DR_REG_EFUSE_BASE + 0x87C)
+/* EFUSE_APB2OTP_BLOCK2_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W2_M  ((EFUSE_APB2OTP_BLOCK2_W2_V)<<(EFUSE_APB2OTP_BLOCK2_W2_S))
+#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W2_S  0
+
+#define EFUSE_APB2OTP_BLK2_W3_REG          (DR_REG_EFUSE_BASE + 0x880)
+/* EFUSE_APB2OTP_BLOCK2_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W3_M  ((EFUSE_APB2OTP_BLOCK2_W3_V)<<(EFUSE_APB2OTP_BLOCK2_W3_S))
+#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W3_S  0
+
+#define EFUSE_APB2OTP_BLK2_W4_REG          (DR_REG_EFUSE_BASE + 0x884)
+/* EFUSE_APB2OTP_BLOCK2_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W4_M  ((EFUSE_APB2OTP_BLOCK2_W4_V)<<(EFUSE_APB2OTP_BLOCK2_W4_S))
+#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W4_S  0
+
+#define EFUSE_APB2OTP_BLK2_W5_REG          (DR_REG_EFUSE_BASE + 0x888)
+/* EFUSE_APB2OTP_BLOCK2_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W5_M  ((EFUSE_APB2OTP_BLOCK2_W5_V)<<(EFUSE_APB2OTP_BLOCK2_W5_S))
+#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W5_S  0
+
+#define EFUSE_APB2OTP_BLK2_W6_REG          (DR_REG_EFUSE_BASE + 0x88C)
+/* EFUSE_APB2OTP_BLOCK2_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W6_M  ((EFUSE_APB2OTP_BLOCK2_W6_V)<<(EFUSE_APB2OTP_BLOCK2_W6_S))
+#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W6_S  0
+
+#define EFUSE_APB2OTP_BLK2_W7_REG          (DR_REG_EFUSE_BASE + 0x890)
+/* EFUSE_APB2OTP_BLOCK2_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W7_M  ((EFUSE_APB2OTP_BLOCK2_W7_V)<<(EFUSE_APB2OTP_BLOCK2_W7_S))
+#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W7_S  0
+
+#define EFUSE_APB2OTP_BLK2_W8_REG          (DR_REG_EFUSE_BASE + 0x894)
+/* EFUSE_APB2OTP_BLOCK2_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W8_M  ((EFUSE_APB2OTP_BLOCK2_W8_V)<<(EFUSE_APB2OTP_BLOCK2_W8_S))
+#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W8_S  0
+
+#define EFUSE_APB2OTP_BLK2_W9_REG          (DR_REG_EFUSE_BASE + 0x898)
+/* EFUSE_APB2OTP_BLOCK2_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W9_M  ((EFUSE_APB2OTP_BLOCK2_W9_V)<<(EFUSE_APB2OTP_BLOCK2_W9_S))
+#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W9_S  0
+
+#define EFUSE_APB2OTP_BLK2_W10_REG          (DR_REG_EFUSE_BASE + 0x89C)
+/* EFUSE_APB2OTP_BLOCK2_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W10_M  ((EFUSE_APB2OTP_BLOCK2_W10_V)<<(EFUSE_APB2OTP_BLOCK2_W10_S))
+#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W10_S  0
+
+#define EFUSE_APB2OTP_BLK2_W11_REG          (DR_REG_EFUSE_BASE + 0x8A0)
+/* EFUSE_APB2OTP_BLOCK2_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block2 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W11_M  ((EFUSE_APB2OTP_BLOCK2_W11_V)<<(EFUSE_APB2OTP_BLOCK2_W11_S))
+#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK2_W11_S  0
+
+#define EFUSE_APB2OTP_BLK3_W1_REG          (DR_REG_EFUSE_BASE + 0x8A4)
+/* EFUSE_APB2OTP_BLOCK3_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W1_M  ((EFUSE_APB2OTP_BLOCK3_W1_V)<<(EFUSE_APB2OTP_BLOCK3_W1_S))
+#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W1_S  0
+
+#define EFUSE_APB2OTP_BLK3_W2_REG          (DR_REG_EFUSE_BASE + 0x8A8)
+/* EFUSE_APB2OTP_BLOCK3_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W2_M  ((EFUSE_APB2OTP_BLOCK3_W2_V)<<(EFUSE_APB2OTP_BLOCK3_W2_S))
+#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W2_S  0
+
+#define EFUSE_APB2OTP_BLK3_W3_REG          (DR_REG_EFUSE_BASE + 0x8AC)
+/* EFUSE_APB2OTP_BLOCK3_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W3_M  ((EFUSE_APB2OTP_BLOCK3_W3_V)<<(EFUSE_APB2OTP_BLOCK3_W3_S))
+#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W3_S  0
+
+#define EFUSE_APB2OTP_BLK3_W4_REG          (DR_REG_EFUSE_BASE + 0x8B0)
+/* EFUSE_APB2OTP_BLOCK3_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W4_M  ((EFUSE_APB2OTP_BLOCK3_W4_V)<<(EFUSE_APB2OTP_BLOCK3_W4_S))
+#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W4_S  0
+
+#define EFUSE_APB2OTP_BLK3_W5_REG          (DR_REG_EFUSE_BASE + 0x8B4)
+/* EFUSE_APB2OTP_BLOCK3_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W5_M  ((EFUSE_APB2OTP_BLOCK3_W5_V)<<(EFUSE_APB2OTP_BLOCK3_W5_S))
+#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W5_S  0
+
+#define EFUSE_APB2OTP_BLK3_W6_REG          (DR_REG_EFUSE_BASE + 0x8B8)
+/* EFUSE_APB2OTP_BLOCK3_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W6_M  ((EFUSE_APB2OTP_BLOCK3_W6_V)<<(EFUSE_APB2OTP_BLOCK3_W6_S))
+#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W6_S  0
+
+#define EFUSE_APB2OTP_BLK3_W7_REG          (DR_REG_EFUSE_BASE + 0x8BC)
+/* EFUSE_APB2OTP_BLOCK3_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W7_M  ((EFUSE_APB2OTP_BLOCK3_W7_V)<<(EFUSE_APB2OTP_BLOCK3_W7_S))
+#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W7_S  0
+
+#define EFUSE_APB2OTP_BLK3_W8_REG          (DR_REG_EFUSE_BASE + 0x8C0)
+/* EFUSE_APB2OTP_BLOCK3_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W8_M  ((EFUSE_APB2OTP_BLOCK3_W8_V)<<(EFUSE_APB2OTP_BLOCK3_W8_S))
+#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W8_S  0
+
+#define EFUSE_APB2OTP_BLK3_W9_REG          (DR_REG_EFUSE_BASE + 0x8C4)
+/* EFUSE_APB2OTP_BLOCK3_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W9_M  ((EFUSE_APB2OTP_BLOCK3_W9_V)<<(EFUSE_APB2OTP_BLOCK3_W9_S))
+#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W9_S  0
+
+#define EFUSE_APB2OTP_BLK3_W10_REG          (DR_REG_EFUSE_BASE + 0x8C8)
+/* EFUSE_APB2OTP_BLOCK3_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W10_M  ((EFUSE_APB2OTP_BLOCK3_W10_V)<<(EFUSE_APB2OTP_BLOCK3_W10_S))
+#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W10_S  0
+
+#define EFUSE_APB2OTP_BLK3_W11_REG          (DR_REG_EFUSE_BASE + 0x8CC)
+/* EFUSE_APB2OTP_BLOCK3_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block3 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W11_M  ((EFUSE_APB2OTP_BLOCK3_W11_V)<<(EFUSE_APB2OTP_BLOCK3_W11_S))
+#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK3_W11_S  0
+
+#define EFUSE_APB2OTP_BLK4_W1_REG          (DR_REG_EFUSE_BASE + 0x8D0)
+/* EFUSE_APB2OTP_BLOCK4_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W1_M  ((EFUSE_APB2OTP_BLOCK4_W1_V)<<(EFUSE_APB2OTP_BLOCK4_W1_S))
+#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W1_S  0
+
+#define EFUSE_APB2OTP_BLK4_W2_REG          (DR_REG_EFUSE_BASE + 0x8D4)
+/* EFUSE_APB2OTP_BLOCK4_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W2_M  ((EFUSE_APB2OTP_BLOCK4_W2_V)<<(EFUSE_APB2OTP_BLOCK4_W2_S))
+#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W2_S  0
+
+#define EFUSE_APB2OTP_BLK4_W3_REG          (DR_REG_EFUSE_BASE + 0x8D8)
+/* EFUSE_APB2OTP_BLOCK4_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W3_M  ((EFUSE_APB2OTP_BLOCK4_W3_V)<<(EFUSE_APB2OTP_BLOCK4_W3_S))
+#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W3_S  0
+
+#define EFUSE_APB2OTP_BLK4_W4_REG          (DR_REG_EFUSE_BASE + 0x8DC)
+/* EFUSE_APB2OTP_BLOCK4_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W4_M  ((EFUSE_APB2OTP_BLOCK4_W4_V)<<(EFUSE_APB2OTP_BLOCK4_W4_S))
+#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W4_S  0
+
+#define EFUSE_APB2OTP_BLK4_W5_REG          (DR_REG_EFUSE_BASE + 0x8E0)
+/* EFUSE_APB2OTP_BLOCK4_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W5_M  ((EFUSE_APB2OTP_BLOCK4_W5_V)<<(EFUSE_APB2OTP_BLOCK4_W5_S))
+#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W5_S  0
+
+#define EFUSE_APB2OTP_BLK4_W6_REG          (DR_REG_EFUSE_BASE + 0x8E4)
+/* EFUSE_APB2OTP_BLOCK4_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W6_M  ((EFUSE_APB2OTP_BLOCK4_W6_V)<<(EFUSE_APB2OTP_BLOCK4_W6_S))
+#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W6_S  0
+
+#define EFUSE_APB2OTP_BLK4_W7_REG          (DR_REG_EFUSE_BASE + 0x8E8)
+/* EFUSE_APB2OTP_BLOCK4_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W7_M  ((EFUSE_APB2OTP_BLOCK4_W7_V)<<(EFUSE_APB2OTP_BLOCK4_W7_S))
+#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W7_S  0
+
+#define EFUSE_APB2OTP_BLK4_W8_REG          (DR_REG_EFUSE_BASE + 0x8EC)
+/* EFUSE_APB2OTP_BLOCK4_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W8_M  ((EFUSE_APB2OTP_BLOCK4_W8_V)<<(EFUSE_APB2OTP_BLOCK4_W8_S))
+#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W8_S  0
+
+#define EFUSE_APB2OTP_BLK4_W9_REG          (DR_REG_EFUSE_BASE + 0x8F0)
+/* EFUSE_APB2OTP_BLOCK4_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W9_M  ((EFUSE_APB2OTP_BLOCK4_W9_V)<<(EFUSE_APB2OTP_BLOCK4_W9_S))
+#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W9_S  0
+
+#define EFUSE_APB2OTP_BLK4_W10_REG          (DR_REG_EFUSE_BASE + 0x8F4)
+/* EFUSE_APB2OTP_BLOCK4_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W10_M  ((EFUSE_APB2OTP_BLOCK4_W10_V)<<(EFUSE_APB2OTP_BLOCK4_W10_S))
+#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W10_S  0
+
+#define EFUSE_APB2OTP_BLK4_W11_REG          (DR_REG_EFUSE_BASE + 0x8F8)
+/* EFUSE_APB2OTP_BLOCK4_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block4 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W11_M  ((EFUSE_APB2OTP_BLOCK4_W11_V)<<(EFUSE_APB2OTP_BLOCK4_W11_S))
+#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK4_W11_S  0
+
+#define EFUSE_APB2OTP_BLK5_W1_REG          (DR_REG_EFUSE_BASE + 0x8FC)
+/* EFUSE_APB2OTP_BLOCK5_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W1_M  ((EFUSE_APB2OTP_BLOCK5_W1_V)<<(EFUSE_APB2OTP_BLOCK5_W1_S))
+#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W1_S  0
+
+#define EFUSE_APB2OTP_BLK5_W2_REG          (DR_REG_EFUSE_BASE + 0x900)
+/* EFUSE_APB2OTP_BLOCK5_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W2_M  ((EFUSE_APB2OTP_BLOCK5_W2_V)<<(EFUSE_APB2OTP_BLOCK5_W2_S))
+#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W2_S  0
+
+#define EFUSE_APB2OTP_BLK5_W3_REG          (DR_REG_EFUSE_BASE + 0x904)
+/* EFUSE_APB2OTP_BLOCK5_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W3_M  ((EFUSE_APB2OTP_BLOCK5_W3_V)<<(EFUSE_APB2OTP_BLOCK5_W3_S))
+#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W3_S  0
+
+#define EFUSE_APB2OTP_BLK5_W4_REG          (DR_REG_EFUSE_BASE + 0x908)
+/* EFUSE_APB2OTP_BLOCK5_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W4_M  ((EFUSE_APB2OTP_BLOCK5_W4_V)<<(EFUSE_APB2OTP_BLOCK5_W4_S))
+#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W4_S  0
+
+#define EFUSE_APB2OTP_BLK5_W5_REG          (DR_REG_EFUSE_BASE + 0x90C)
+/* EFUSE_APB2OTP_BLOCK5_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W5_M  ((EFUSE_APB2OTP_BLOCK5_W5_V)<<(EFUSE_APB2OTP_BLOCK5_W5_S))
+#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W5_S  0
+
+#define EFUSE_APB2OTP_BLK5_W6_REG          (DR_REG_EFUSE_BASE + 0x910)
+/* EFUSE_APB2OTP_BLOCK5_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W6_M  ((EFUSE_APB2OTP_BLOCK5_W6_V)<<(EFUSE_APB2OTP_BLOCK5_W6_S))
+#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W6_S  0
+
+#define EFUSE_APB2OTP_BLK5_W7_REG          (DR_REG_EFUSE_BASE + 0x914)
+/* EFUSE_APB2OTP_BLOCK5_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W7_M  ((EFUSE_APB2OTP_BLOCK5_W7_V)<<(EFUSE_APB2OTP_BLOCK5_W7_S))
+#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W7_S  0
+
+#define EFUSE_APB2OTP_BLK5_W8_REG          (DR_REG_EFUSE_BASE + 0x918)
+/* EFUSE_APB2OTP_BLOCK5_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W8_M  ((EFUSE_APB2OTP_BLOCK5_W8_V)<<(EFUSE_APB2OTP_BLOCK5_W8_S))
+#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W8_S  0
+
+#define EFUSE_APB2OTP_BLK5_W9_REG          (DR_REG_EFUSE_BASE + 0x91C)
+/* EFUSE_APB2OTP_BLOCK5_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W9_M  ((EFUSE_APB2OTP_BLOCK5_W9_V)<<(EFUSE_APB2OTP_BLOCK5_W9_S))
+#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W9_S  0
+
+#define EFUSE_APB2OTP_BLK5_W10_REG          (DR_REG_EFUSE_BASE + 0x920)
+/* EFUSE_APB2OTP_BLOCK5_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W10_M  ((EFUSE_APB2OTP_BLOCK5_W10_V)<<(EFUSE_APB2OTP_BLOCK5_W10_S))
+#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W10_S  0
+
+#define EFUSE_APB2OTP_BLK5_W11_REG          (DR_REG_EFUSE_BASE + 0x924)
+/* EFUSE_APB2OTP_BLOCK5_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block5 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W11_M  ((EFUSE_APB2OTP_BLOCK5_W11_V)<<(EFUSE_APB2OTP_BLOCK5_W11_S))
+#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK5_W11_S  0
+
+#define EFUSE_APB2OTP_BLK6_W1_REG          (DR_REG_EFUSE_BASE + 0x928)
+/* EFUSE_APB2OTP_BLOCK6_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W1_M  ((EFUSE_APB2OTP_BLOCK6_W1_V)<<(EFUSE_APB2OTP_BLOCK6_W1_S))
+#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W1_S  0
+
+#define EFUSE_APB2OTP_BLK6_W2_REG          (DR_REG_EFUSE_BASE + 0x92C)
+/* EFUSE_APB2OTP_BLOCK6_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W2_M  ((EFUSE_APB2OTP_BLOCK6_W2_V)<<(EFUSE_APB2OTP_BLOCK6_W2_S))
+#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W2_S  0
+
+#define EFUSE_APB2OTP_BLK6_W3_REG          (DR_REG_EFUSE_BASE + 0x930)
+/* EFUSE_APB2OTP_BLOCK6_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W3_M  ((EFUSE_APB2OTP_BLOCK6_W3_V)<<(EFUSE_APB2OTP_BLOCK6_W3_S))
+#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W3_S  0
+
+#define EFUSE_APB2OTP_BLK6_W4_REG          (DR_REG_EFUSE_BASE + 0x934)
+/* EFUSE_APB2OTP_BLOCK6_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W4_M  ((EFUSE_APB2OTP_BLOCK6_W4_V)<<(EFUSE_APB2OTP_BLOCK6_W4_S))
+#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W4_S  0
+
+#define EFUSE_APB2OTP_BLK6_W5_REG          (DR_REG_EFUSE_BASE + 0x938)
+/* EFUSE_APB2OTP_BLOCK6_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W5_M  ((EFUSE_APB2OTP_BLOCK6_W5_V)<<(EFUSE_APB2OTP_BLOCK6_W5_S))
+#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W5_S  0
+
+#define EFUSE_APB2OTP_BLK6_W6_REG          (DR_REG_EFUSE_BASE + 0x93C)
+/* EFUSE_APB2OTP_BLOCK6_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W6_M  ((EFUSE_APB2OTP_BLOCK6_W6_V)<<(EFUSE_APB2OTP_BLOCK6_W6_S))
+#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W6_S  0
+
+#define EFUSE_APB2OTP_BLK6_W7_REG          (DR_REG_EFUSE_BASE + 0x940)
+/* EFUSE_APB2OTP_BLOCK6_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W7_M  ((EFUSE_APB2OTP_BLOCK6_W7_V)<<(EFUSE_APB2OTP_BLOCK6_W7_S))
+#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W7_S  0
+
+#define EFUSE_APB2OTP_BLK6_W8_REG          (DR_REG_EFUSE_BASE + 0x944)
+/* EFUSE_APB2OTP_BLOCK6_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W8_M  ((EFUSE_APB2OTP_BLOCK6_W8_V)<<(EFUSE_APB2OTP_BLOCK6_W8_S))
+#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W8_S  0
+
+#define EFUSE_APB2OTP_BLK6_W9_REG          (DR_REG_EFUSE_BASE + 0x948)
+/* EFUSE_APB2OTP_BLOCK6_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W9_M  ((EFUSE_APB2OTP_BLOCK6_W9_V)<<(EFUSE_APB2OTP_BLOCK6_W9_S))
+#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W9_S  0
+
+#define EFUSE_APB2OTP_BLK6_W10_REG          (DR_REG_EFUSE_BASE + 0x94C)
+/* EFUSE_APB2OTP_BLOCK6_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W10_M  ((EFUSE_APB2OTP_BLOCK6_W10_V)<<(EFUSE_APB2OTP_BLOCK6_W10_S))
+#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W10_S  0
+
+#define EFUSE_APB2OTP_BLK6_W11_REG          (DR_REG_EFUSE_BASE + 0x950)
+/* EFUSE_APB2OTP_BLOCK6_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block6 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W11_M  ((EFUSE_APB2OTP_BLOCK6_W11_V)<<(EFUSE_APB2OTP_BLOCK6_W11_S))
+#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK6_W11_S  0
+
+#define EFUSE_APB2OTP_BLK7_W1_REG          (DR_REG_EFUSE_BASE + 0x954)
+/* EFUSE_APB2OTP_BLOCK7_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W1_M  ((EFUSE_APB2OTP_BLOCK7_W1_V)<<(EFUSE_APB2OTP_BLOCK7_W1_S))
+#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W1_S  0
+
+#define EFUSE_APB2OTP_BLK7_W2_REG          (DR_REG_EFUSE_BASE + 0x958)
+/* EFUSE_APB2OTP_BLOCK7_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W2_M  ((EFUSE_APB2OTP_BLOCK7_W2_V)<<(EFUSE_APB2OTP_BLOCK7_W2_S))
+#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W2_S  0
+
+#define EFUSE_APB2OTP_BLK7_W3_REG          (DR_REG_EFUSE_BASE + 0x95C)
+/* EFUSE_APB2OTP_BLOCK7_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W3_M  ((EFUSE_APB2OTP_BLOCK7_W3_V)<<(EFUSE_APB2OTP_BLOCK7_W3_S))
+#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W3_S  0
+
+#define EFUSE_APB2OTP_BLK7_W4_REG          (DR_REG_EFUSE_BASE + 0x960)
+/* EFUSE_APB2OTP_BLOCK7_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W4_M  ((EFUSE_APB2OTP_BLOCK7_W4_V)<<(EFUSE_APB2OTP_BLOCK7_W4_S))
+#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W4_S  0
+
+#define EFUSE_APB2OTP_BLK7_W5_REG          (DR_REG_EFUSE_BASE + 0x964)
+/* EFUSE_APB2OTP_BLOCK7_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W5_M  ((EFUSE_APB2OTP_BLOCK7_W5_V)<<(EFUSE_APB2OTP_BLOCK7_W5_S))
+#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W5_S  0
+
+#define EFUSE_APB2OTP_BLK7_W6_REG          (DR_REG_EFUSE_BASE + 0x968)
+/* EFUSE_APB2OTP_BLOCK7_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W6_M  ((EFUSE_APB2OTP_BLOCK7_W6_V)<<(EFUSE_APB2OTP_BLOCK7_W6_S))
+#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W6_S  0
+
+#define EFUSE_APB2OTP_BLK7_W7_REG          (DR_REG_EFUSE_BASE + 0x96C)
+/* EFUSE_APB2OTP_BLOCK7_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W7_M  ((EFUSE_APB2OTP_BLOCK7_W7_V)<<(EFUSE_APB2OTP_BLOCK7_W7_S))
+#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W7_S  0
+
+#define EFUSE_APB2OTP_BLK7_W8_REG          (DR_REG_EFUSE_BASE + 0x970)
+/* EFUSE_APB2OTP_BLOCK7_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W8_M  ((EFUSE_APB2OTP_BLOCK7_W8_V)<<(EFUSE_APB2OTP_BLOCK7_W8_S))
+#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W8_S  0
+
+#define EFUSE_APB2OTP_BLK7_W9_REG          (DR_REG_EFUSE_BASE + 0x974)
+/* EFUSE_APB2OTP_BLOCK7_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W9_M  ((EFUSE_APB2OTP_BLOCK7_W9_V)<<(EFUSE_APB2OTP_BLOCK7_W9_S))
+#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W9_S  0
+
+#define EFUSE_APB2OTP_BLK7_W10_REG          (DR_REG_EFUSE_BASE + 0x978)
+/* EFUSE_APB2OTP_BLOCK7_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W10_M  ((EFUSE_APB2OTP_BLOCK7_W10_V)<<(EFUSE_APB2OTP_BLOCK7_W10_S))
+#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W10_S  0
+
+#define EFUSE_APB2OTP_BLK7_W11_REG          (DR_REG_EFUSE_BASE + 0x97C)
+/* EFUSE_APB2OTP_BLOCK7_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block7 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W11_M  ((EFUSE_APB2OTP_BLOCK7_W11_V)<<(EFUSE_APB2OTP_BLOCK7_W11_S))
+#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK7_W11_S  0
+
+#define EFUSE_APB2OTP_BLK8_W1_REG          (DR_REG_EFUSE_BASE + 0x980)
+/* EFUSE_APB2OTP_BLOCK8_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W1_M  ((EFUSE_APB2OTP_BLOCK8_W1_V)<<(EFUSE_APB2OTP_BLOCK8_W1_S))
+#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W1_S  0
+
+#define EFUSE_APB2OTP_BLK8_W2_REG          (DR_REG_EFUSE_BASE + 0x984)
+/* EFUSE_APB2OTP_BLOCK8_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W2_M  ((EFUSE_APB2OTP_BLOCK8_W2_V)<<(EFUSE_APB2OTP_BLOCK8_W2_S))
+#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W2_S  0
+
+#define EFUSE_APB2OTP_BLK8_W3_REG          (DR_REG_EFUSE_BASE + 0x988)
+/* EFUSE_APB2OTP_BLOCK8_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W3_M  ((EFUSE_APB2OTP_BLOCK8_W3_V)<<(EFUSE_APB2OTP_BLOCK8_W3_S))
+#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W3_S  0
+
+#define EFUSE_APB2OTP_BLK8_W4_REG          (DR_REG_EFUSE_BASE + 0x98C)
+/* EFUSE_APB2OTP_BLOCK8_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W4_M  ((EFUSE_APB2OTP_BLOCK8_W4_V)<<(EFUSE_APB2OTP_BLOCK8_W4_S))
+#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W4_S  0
+
+#define EFUSE_APB2OTP_BLK8_W5_REG          (DR_REG_EFUSE_BASE + 0x990)
+/* EFUSE_APB2OTP_BLOCK8_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W5_M  ((EFUSE_APB2OTP_BLOCK8_W5_V)<<(EFUSE_APB2OTP_BLOCK8_W5_S))
+#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W5_S  0
+
+#define EFUSE_APB2OTP_BLK8_W6_REG          (DR_REG_EFUSE_BASE + 0x994)
+/* EFUSE_APB2OTP_BLOCK8_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W6_M  ((EFUSE_APB2OTP_BLOCK8_W6_V)<<(EFUSE_APB2OTP_BLOCK8_W6_S))
+#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W6_S  0
+
+#define EFUSE_APB2OTP_BLK8_W7_REG          (DR_REG_EFUSE_BASE + 0x998)
+/* EFUSE_APB2OTP_BLOCK8_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W7_M  ((EFUSE_APB2OTP_BLOCK8_W7_V)<<(EFUSE_APB2OTP_BLOCK8_W7_S))
+#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W7_S  0
+
+#define EFUSE_APB2OTP_BLK8_W8_REG          (DR_REG_EFUSE_BASE + 0x99C)
+/* EFUSE_APB2OTP_BLOCK8_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W8_M  ((EFUSE_APB2OTP_BLOCK8_W8_V)<<(EFUSE_APB2OTP_BLOCK8_W8_S))
+#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W8_S  0
+
+#define EFUSE_APB2OTP_BLK8_W9_REG          (DR_REG_EFUSE_BASE + 0x9A0)
+/* EFUSE_APB2OTP_BLOCK8_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W9_M  ((EFUSE_APB2OTP_BLOCK8_W9_V)<<(EFUSE_APB2OTP_BLOCK8_W9_S))
+#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W9_S  0
+
+#define EFUSE_APB2OTP_BLK8_W10_REG          (DR_REG_EFUSE_BASE + 0x9A4)
+/* EFUSE_APB2OTP_BLOCK8_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W10_M  ((EFUSE_APB2OTP_BLOCK8_W10_V)<<(EFUSE_APB2OTP_BLOCK8_W10_S))
+#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W10_S  0
+
+#define EFUSE_APB2OTP_BLK8_W11_REG          (DR_REG_EFUSE_BASE + 0x9A8)
+/* EFUSE_APB2OTP_BLOCK8_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block8 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W11_M  ((EFUSE_APB2OTP_BLOCK8_W11_V)<<(EFUSE_APB2OTP_BLOCK8_W11_S))
+#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK8_W11_S  0
+
+#define EFUSE_APB2OTP_BLK9_W1_REG          (DR_REG_EFUSE_BASE + 0x9AC)
+/* EFUSE_APB2OTP_BLOCK9_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W1_M  ((EFUSE_APB2OTP_BLOCK9_W1_V)<<(EFUSE_APB2OTP_BLOCK9_W1_S))
+#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W1_S  0
+
+#define EFUSE_APB2OTP_BLK9_W2_REG          (DR_REG_EFUSE_BASE + 0x9B0)
+/* EFUSE_APB2OTP_BLOCK9_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W2_M  ((EFUSE_APB2OTP_BLOCK9_W2_V)<<(EFUSE_APB2OTP_BLOCK9_W2_S))
+#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W2_S  0
+
+#define EFUSE_APB2OTP_BLK9_W3_REG          (DR_REG_EFUSE_BASE + 0x9B4)
+/* EFUSE_APB2OTP_BLOCK9_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W3_M  ((EFUSE_APB2OTP_BLOCK9_W3_V)<<(EFUSE_APB2OTP_BLOCK9_W3_S))
+#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W3_S  0
+
+#define EFUSE_APB2OTP_BLK9_W4_REG          (DR_REG_EFUSE_BASE + 0x9B8)
+/* EFUSE_APB2OTP_BLOCK9_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W4_M  ((EFUSE_APB2OTP_BLOCK9_W4_V)<<(EFUSE_APB2OTP_BLOCK9_W4_S))
+#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W4_S  0
+
+#define EFUSE_APB2OTP_BLK9_W5_REG          (DR_REG_EFUSE_BASE + 0x9BC)
+/* EFUSE_APB2OTP_BLOCK9_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W5_M  ((EFUSE_APB2OTP_BLOCK9_W5_V)<<(EFUSE_APB2OTP_BLOCK9_W5_S))
+#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W5_S  0
+
+#define EFUSE_APB2OTP_BLK9_W6_REG          (DR_REG_EFUSE_BASE + 0x9C0)
+/* EFUSE_APB2OTP_BLOCK9_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W6_M  ((EFUSE_APB2OTP_BLOCK9_W6_V)<<(EFUSE_APB2OTP_BLOCK9_W6_S))
+#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W6_S  0
+
+#define EFUSE_APB2OTP_BLK9_W7_REG          (DR_REG_EFUSE_BASE + 0x9C4)
+/* EFUSE_APB2OTP_BLOCK9_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W7_M  ((EFUSE_APB2OTP_BLOCK9_W7_V)<<(EFUSE_APB2OTP_BLOCK9_W7_S))
+#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W7_S  0
+
+#define EFUSE_APB2OTP_BLK9_W8_REG          (DR_REG_EFUSE_BASE + 0x9C8)
+/* EFUSE_APB2OTP_BLOCK9_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W8_M  ((EFUSE_APB2OTP_BLOCK9_W8_V)<<(EFUSE_APB2OTP_BLOCK9_W8_S))
+#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W8_S  0
+
+#define EFUSE_APB2OTP_BLK9_W9_REG          (DR_REG_EFUSE_BASE + 0x9CC)
+/* EFUSE_APB2OTP_BLOCK9_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W9_M  ((EFUSE_APB2OTP_BLOCK9_W9_V)<<(EFUSE_APB2OTP_BLOCK9_W9_S))
+#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W9_S  0
+
+#define EFUSE_APB2OTP_BLK9_W10_REG          (DR_REG_EFUSE_BASE + 0x9D0)
+/* EFUSE_APB2OTP_BLOCK9_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W10_M  ((EFUSE_APB2OTP_BLOCK9_W10_V)<<(EFUSE_APB2OTP_BLOCK9_W10_S))
+#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W10_S  0
+
+#define EFUSE_APB2OTP_BLK9_W11_REG          (DR_REG_EFUSE_BASE + 0x9D4)
+/* EFUSE_APB2OTP_BLOCK9_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block9 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W11_M  ((EFUSE_APB2OTP_BLOCK9_W11_V)<<(EFUSE_APB2OTP_BLOCK9_W11_S))
+#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK9_W11_S  0
+
+#define EFUSE_APB2OTP_BLK10_W1_REG          (DR_REG_EFUSE_BASE + 0x9D8)
+/* EFUSE_APB2OTP_BLOCK10_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word1 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W1_M  ((EFUSE_APB2OTP_BLOCK10_W1_V)<<(EFUSE_APB2OTP_BLOCK10_W1_S))
+#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W1_S  0
+
+#define EFUSE_APB2OTP_BLK10_W2_REG          (DR_REG_EFUSE_BASE + 0x9DC)
+/* EFUSE_APB2OTP_BLOCK10_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word2 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W2_M  ((EFUSE_APB2OTP_BLOCK10_W2_V)<<(EFUSE_APB2OTP_BLOCK10_W2_S))
+#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W2_S  0
+
+#define EFUSE_APB2OTP_BLK10_W3_REG          (DR_REG_EFUSE_BASE + 0x9E0)
+/* EFUSE_APB2OTP_BLOCK10_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word3 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W3_M  ((EFUSE_APB2OTP_BLOCK10_W3_V)<<(EFUSE_APB2OTP_BLOCK10_W3_S))
+#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W3_S  0
+
+#define EFUSE_APB2OTP_BLK10_W4_REG          (DR_REG_EFUSE_BASE + 0x9E4)
+/* EFUSE_APB2OTP_BLOCK10_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word4 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W4_M  ((EFUSE_APB2OTP_BLOCK10_W4_V)<<(EFUSE_APB2OTP_BLOCK10_W4_S))
+#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W4_S  0
+
+#define EFUSE_APB2OTP_BLK10_W5_REG          (DR_REG_EFUSE_BASE + 0x9E8)
+/* EFUSE_APB2OTP_BLOCK10_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word5 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W5_M  ((EFUSE_APB2OTP_BLOCK10_W5_V)<<(EFUSE_APB2OTP_BLOCK10_W5_S))
+#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W5_S  0
+
+#define EFUSE_APB2OTP_BLK10_W6_REG          (DR_REG_EFUSE_BASE + 0x9EC)
+/* EFUSE_APB2OTP_BLOCK10_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word6 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W6_M  ((EFUSE_APB2OTP_BLOCK10_W6_V)<<(EFUSE_APB2OTP_BLOCK10_W6_S))
+#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W6_S  0
+
+#define EFUSE_APB2OTP_BLK10_W7_REG          (DR_REG_EFUSE_BASE + 0x9F0)
+/* EFUSE_APB2OTP_BLOCK10_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word7 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W7_M  ((EFUSE_APB2OTP_BLOCK10_W7_V)<<(EFUSE_APB2OTP_BLOCK10_W7_S))
+#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W7_S  0
+
+#define EFUSE_APB2OTP_BLK10_W8_REG          (DR_REG_EFUSE_BASE + 0x9F4)
+/* EFUSE_APB2OTP_BLOCK10_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word8 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W8_M  ((EFUSE_APB2OTP_BLOCK10_W8_V)<<(EFUSE_APB2OTP_BLOCK10_W8_S))
+#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W8_S  0
+
+#define EFUSE_APB2OTP_BLK10_W9_REG          (DR_REG_EFUSE_BASE + 0x9F8)
+/* EFUSE_APB2OTP_BLOCK10_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word9 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W9_M  ((EFUSE_APB2OTP_BLOCK10_W9_V)<<(EFUSE_APB2OTP_BLOCK10_W9_S))
+#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W9_S  0
+
+#define EFUSE_APB2OTP_BLK10_W10_REG          (DR_REG_EFUSE_BASE + 0x9FC)
+/* EFUSE_APB2OTP_BLOCK19_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word10 data..*/
+#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK19_W10_M  ((EFUSE_APB2OTP_BLOCK19_W10_V)<<(EFUSE_APB2OTP_BLOCK19_W10_S))
+#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK19_W10_S  0
+
+#define EFUSE_APB2OTP_BLK10_W11_REG          (DR_REG_EFUSE_BASE + 0xA00)
+/* EFUSE_APB2OTP_BLOCK10_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Otp block10 word11 data..*/
+#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W11_M  ((EFUSE_APB2OTP_BLOCK10_W11_V)<<(EFUSE_APB2OTP_BLOCK10_W11_S))
+#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFF
+#define EFUSE_APB2OTP_BLOCK10_W11_S  0
+
+#define EFUSE_APB2OTP_EN_REG          (DR_REG_EFUSE_BASE + 0xA08)
+/* EFUSE_APB2OTP_APB2OTP_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Apb2otp mode enable signal..*/
+#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
+#define EFUSE_APB2OTP_APB2OTP_EN_M  (BIT(0))
+#define EFUSE_APB2OTP_APB2OTP_EN_V  0x1
+#define EFUSE_APB2OTP_APB2OTP_EN_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/efuse_struct.h b/components/soc/esp32p4/include/soc/efuse_struct.h
new file mode 100644
index 0000000000..ffa54c2a0e
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/efuse_struct.h
@@ -0,0 +1,1011 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t pgm_data0;
+    uint32_t pgm_data1;
+    uint32_t pgm_data2;
+    uint32_t pgm_data3;
+    uint32_t pgm_data4;
+    uint32_t pgm_data5;
+    uint32_t pgm_data6;
+    uint32_t pgm_data7;
+    uint32_t pgm_check_value0;
+    uint32_t pgm_check_value1;
+    uint32_t pgm_check_value2;
+    uint32_t rd_wr_dis;
+    union {
+        struct {
+            uint32_t rd_dis                    :    7;  /*Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t usb_device_exchg_pins     :    1;  /*Enable usb device exchange pins of D+ and D-.*/
+            uint32_t usb_otg11_exchg_pins      :    1;  /*Enable usb otg11 exchange pins of D+ and D-.*/
+            uint32_t dis_usb_jtag              :    1;  /*Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t powerglitch_en            :    1;  /*Represents whether power glitch function is enabled. 1: enabled. 0: disabled.*/
+            uint32_t dis_usb_serial_jtag       :    1;  /*Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t dis_force_download        :    1;  /*Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t spi_download_mspi_dis     :    1;  /*Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download.*/
+            uint32_t dis_twai                  :    1;  /*Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t jtag_sel_enable           :    1;  /*Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled.*/
+            uint32_t soft_dis_jtag             :    3;  /*Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled.*/
+            uint32_t dis_pad_jtag              :    1;  /*Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled.*/
+            uint32_t dis_download_manual_encrypt:    1;  /*Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled.*/
+            uint32_t usb_device_drefh          :    2;  /*USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV*/
+            uint32_t usb_otg11_drefh           :    2;  /*USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV*/
+            uint32_t usb_phy_sel               :    1;  /*TBD*/
+            uint32_t huk_gen_state_low         :    6;  /*Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid.*/
+        };
+        uint32_t val;
+    } rd_repeat_data0;
+    union {
+        struct {
+            uint32_t huk_gen_state_high        :    3;  /*Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid.*/
+            uint32_t km_rnd_switch_cycle       :    2;  /*Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.*/
+            uint32_t km_deploy_only_once       :    4;  /*Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.*/
+            uint32_t force_use_key_manager_key :    4;  /*Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.*/
+            uint32_t force_disable_sw_init_key :    1;  /*Set this bit to disable software written init key, and force use efuse_init_key.*/
+            uint32_t xts_key_length_256        :    1;  /*Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.*/
+            uint32_t reserved15                    :    1;  /*Reserved.*/
+            uint32_t wdt_delay_sel             :    2;  /*Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected.*/
+            uint32_t spi_boot_crypt_cnt        :    3;  /*Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled.*/
+            uint32_t secure_boot_key_revoke0   :    1;  /*Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/
+            uint32_t secure_boot_key_revoke1   :    1;  /*Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/
+            uint32_t secure_boot_key_revoke2   :    1;  /*Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/
+            uint32_t key_purpose_0             :    4;  /*Represents the purpose of Key0.*/
+            uint32_t key_purpose_1             :    4;  /*Represents the purpose of Key1.*/
+        };
+        uint32_t val;
+    } rd_repeat_data1;
+    union {
+        struct {
+            uint32_t key_purpose_2             :    4;  /*Represents the purpose of Key2.*/
+            uint32_t key_purpose_3             :    4;  /*Represents the purpose of Key3.*/
+            uint32_t key_purpose_4             :    4;  /*Represents the purpose of Key4.*/
+            uint32_t key_purpose_5             :    4;  /*Represents the purpose of Key5.*/
+            uint32_t sec_dpa_level             :    2;  /*Represents the spa secure level by configuring the clock random divide mode.*/
+            uint32_t ecdsa_enable_soft_k       :    1;  /*Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used.*/
+            uint32_t crypt_dpa_enable          :    1;  /*Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.*/
+            uint32_t secure_boot_en            :    1;  /*Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.*/
+            uint32_t secure_boot_aggressive_revoke:    1;  /*Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled.*/
+            uint32_t reserved22                    :    1;  /*Reserved.*/
+            uint32_t flash_type                :    1;  /*The type of interfaced flash. 0: four data lines, 1: eight data lines.*/
+            uint32_t flash_page_size           :    2;  /*Set flash page size.*/
+            uint32_t flash_ecc_en              :    1;  /*Set this bit to enable ecc for flash boot.*/
+            uint32_t dis_usb_otg_download_mode :    1;  /*Set this bit to disable download via USB-OTG.*/
+            uint32_t flash_tpuw                :    4;  /*Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value.*/
+        };
+        uint32_t val;
+    } rd_repeat_data2;
+    union {
+        struct {
+            uint32_t dis_download_mode         :    1;  /*Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t dis_direct_boot           :    1;  /*Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t dis_usb_serial_jtag_rom_print:    1;  /*Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t lock_km_key               :    1;  /*TBD*/
+            uint32_t dis_usb_serial_jtag_download_mode:    1;  /*Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled.*/
+            uint32_t enable_security_download  :    1;  /*Represents whether security download is enabled or disabled. 1: enabled. 0: disabled.*/
+            uint32_t uart_print_control        :    2;  /*Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. */
+            uint32_t force_send_resume         :    1;  /*Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced.*/
+            uint32_t secure_version            :    16;  /*Represents the version used by ESP-IDF anti-rollback feature.*/
+            uint32_t secure_boot_disable_fast_wake:    1;  /*Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled.*/
+            uint32_t hys_en_pad                :    1;  /*Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled.*/
+            uint32_t dcdc_vset                 :    5;  /*Set the dcdc voltage default.*/
+        };
+        uint32_t val;
+    } rd_repeat_data3;
+    union {
+        struct {
+            uint32_t _0pxa_tieh_sel_0           :    2;  /*TBD*/
+            uint32_t _0pxa_tieh_sel_1           :    2;  /*TBD.*/
+            uint32_t _0pxa_tieh_sel_2           :    2;  /*TBD.*/
+            uint32_t _0pxa_tieh_sel_3           :    2;  /*TBD.*/
+            uint32_t km_disable_deploy_mode    :    4;  /*TBD*/
+            uint32_t usb_device_drefl          :    2;  /*Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV.*/
+            uint32_t usb_otg11_drefl           :    2;  /*Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV.*/
+            uint32_t reserved16                    :    2;  /*Reserved.*/
+            uint32_t hp_pwr_src_sel            :    1;  /*HP system power source select. 0:LDO. 1: DCDC.*/
+            uint32_t dcdc_vset_en              :    1;  /*Select dcdc vset use efuse_dcdc_vset.*/
+            uint32_t dis_wdt                   :    1;  /*Set this bit to disable watch dog.*/
+            uint32_t dis_swd                   :    1;  /*Set this bit to disable super-watchdog.*/
+            uint32_t reserved22                    :    2;  /*Reserved.*/
+            uint32_t reserved24                    :    8;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_repeat_data4;
+    uint32_t rd_mac_sys_0;
+    union {
+        struct {
+            uint32_t mac_1                     :    16;  /*Stores the high 16 bits of MAC address.*/
+            uint32_t mac_ext                   :    16;  /*Stores the extended bits of MAC address.*/
+        };
+        uint32_t val;
+    } rd_mac_sys_1;
+    union {
+        struct {
+            uint32_t mac_reserved_1            :    14;  /*Reserved.*/
+            uint32_t mac_reserved_0            :    18;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_mac_sys_2;
+    union {
+        struct {
+            uint32_t mac_reserved_2            :    18;  /*Reserved.*/
+            uint32_t sys_data_part0_0          :    14;  /*Stores the first 14 bits of the zeroth part of system data.*/
+        };
+        uint32_t val;
+    } rd_mac_sys_3;
+    uint32_t rd_mac_sys_4;
+    uint32_t rd_mac_sys_5;
+    uint32_t rd_sys_part1_data0;
+    uint32_t rd_sys_part1_data1;
+    uint32_t rd_sys_part1_data2;
+    uint32_t rd_sys_part1_data3;
+    uint32_t rd_sys_part1_data4;
+    uint32_t rd_sys_part1_data5;
+    uint32_t rd_sys_part1_data6;
+    uint32_t rd_sys_part1_data7;
+    uint32_t rd_usr_data0;
+    uint32_t rd_usr_data1;
+    uint32_t rd_usr_data2;
+    uint32_t rd_usr_data3;
+    uint32_t rd_usr_data4;
+    uint32_t rd_usr_data5;
+    uint32_t rd_usr_data6;
+    uint32_t rd_usr_data7;
+    uint32_t rd_key0_data0;
+    uint32_t rd_key0_data1;
+    uint32_t rd_key0_data2;
+    uint32_t rd_key0_data3;
+    uint32_t rd_key0_data4;
+    uint32_t rd_key0_data5;
+    uint32_t rd_key0_data6;
+    uint32_t rd_key0_data7;
+    uint32_t rd_key1_data0;
+    uint32_t rd_key1_data1;
+    uint32_t rd_key1_data2;
+    uint32_t rd_key1_data3;
+    uint32_t rd_key1_data4;
+    uint32_t rd_key1_data5;
+    uint32_t rd_key1_data6;
+    uint32_t rd_key1_data7;
+    uint32_t rd_key2_data0;
+    uint32_t rd_key2_data1;
+    uint32_t rd_key2_data2;
+    uint32_t rd_key2_data3;
+    uint32_t rd_key2_data4;
+    uint32_t rd_key2_data5;
+    uint32_t rd_key2_data6;
+    uint32_t rd_key2_data7;
+    uint32_t rd_key3_data0;
+    uint32_t rd_key3_data1;
+    uint32_t rd_key3_data2;
+    uint32_t rd_key3_data3;
+    uint32_t rd_key3_data4;
+    uint32_t rd_key3_data5;
+    uint32_t rd_key3_data6;
+    uint32_t rd_key3_data7;
+    uint32_t rd_key4_data0;
+    uint32_t rd_key4_data1;
+    uint32_t rd_key4_data2;
+    uint32_t rd_key4_data3;
+    uint32_t rd_key4_data4;
+    uint32_t rd_key4_data5;
+    uint32_t rd_key4_data6;
+    uint32_t rd_key4_data7;
+    uint32_t rd_key5_data0;
+    uint32_t rd_key5_data1;
+    uint32_t rd_key5_data2;
+    uint32_t rd_key5_data3;
+    uint32_t rd_key5_data4;
+    uint32_t rd_key5_data5;
+    uint32_t rd_key5_data6;
+    uint32_t rd_key5_data7;
+    uint32_t rd_sys_part2_data0;
+    uint32_t rd_sys_part2_data1;
+    uint32_t rd_sys_part2_data2;
+    uint32_t rd_sys_part2_data3;
+    uint32_t rd_sys_part2_data4;
+    uint32_t rd_sys_part2_data5;
+    uint32_t rd_sys_part2_data6;
+    uint32_t rd_sys_part2_data7;
+    union {
+        struct {
+            uint32_t rd_dis_err                :    7;  /*Indicates a programming error of RD_DIS.*/
+            uint32_t usb_device_exchg_pins_err :    1;  /*Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.*/
+            uint32_t usb_otg11_exchg_pins_err  :    1;  /*Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.*/
+            uint32_t dis_usb_jtag_err          :    1;  /*Indicates a programming error of DIS_USB_JTAG.*/
+            uint32_t powerglitch_en_err        :    1;  /*Indicates a programming error of POWERGLITCH_EN.*/
+            uint32_t dis_usb_serial_jtag_err   :    1;  /*Indicates a programming error of DIS_USB_SERIAL_JTAG.*/
+            uint32_t dis_force_download_err    :    1;  /*Indicates a programming error of DIS_FORCE_DOWNLOAD.*/
+            uint32_t spi_download_mspi_dis_err :    1;  /*Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.*/
+            uint32_t dis_twai_err              :    1;  /*Indicates a programming error of DIS_TWAI.*/
+            uint32_t jtag_sel_enable_err       :    1;  /*Indicates a programming error of JTAG_SEL_ENABLE.*/
+            uint32_t soft_dis_jtag_err         :    3;  /*Indicates a programming error of SOFT_DIS_JTAG.*/
+            uint32_t dis_pad_jtag_err          :    1;  /*Indicates a programming error of DIS_PAD_JTAG.*/
+            uint32_t dis_download_manual_encrypt_err:    1;  /*Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/
+            uint32_t usb_device_drefh_err      :    2;  /*Indicates a programming error of USB_DEVICE_DREFH.*/
+            uint32_t usb_otg11_drefh_err       :    2;  /*Indicates a programming error of USB_OTG11_DREFH.*/
+            uint32_t usb_phy_sel_err           :    1;  /*Indicates a programming error of USB_PHY_SEL.*/
+            uint32_t huk_gen_state_low_err     :    6;  /*Indicates a programming error of HUK_GEN_STATE_LOW.*/
+        };
+        uint32_t val;
+    } rd_repeat_err0;
+    union {
+        struct {
+            uint32_t huk_gen_state_high_err    :    3;  /*Indicates a programming error of HUK_GEN_STATE_HIGH.*/
+            uint32_t km_rnd_switch_cycle_err   :    2;  /*Indicates a programming error of KM_RND_SWITCH_CYCLE.*/
+            uint32_t km_deploy_only_once_err   :    4;  /*Indicates a programming error of KM_DEPLOY_ONLY_ONCE.*/
+            uint32_t force_use_key_manager_key_err:    4;  /*Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.*/
+            uint32_t force_disable_sw_init_key_err:    1;  /*Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.*/
+            uint32_t xts_key_length_256_err    :    1;  /*Indicates a programming error of XTS_KEY_LENGTH_256.*/
+            uint32_t reserved15                    :    1;  /*Reserved.*/
+            uint32_t wdt_delay_sel_err         :    2;  /*Indicates a programming error of WDT_DELAY_SEL.*/
+            uint32_t spi_boot_crypt_cnt_err    :    3;  /*Indicates a programming error of SPI_BOOT_CRYPT_CNT.*/
+            uint32_t secure_boot_key_revoke0_err:    1;  /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.*/
+            uint32_t secure_boot_key_revoke1_err:    1;  /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.*/
+            uint32_t secure_boot_key_revoke2_err:    1;  /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.*/
+            uint32_t key_purpose_0_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_0.*/
+            uint32_t key_purpose_1_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_1.*/
+        };
+        uint32_t val;
+    } rd_repeat_err1;
+    union {
+        struct {
+            uint32_t key_purpose_2_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_2.*/
+            uint32_t key_purpose_3_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_3.*/
+            uint32_t key_purpose_4_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_4.*/
+            uint32_t key_purpose_5_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_5.*/
+            uint32_t sec_dpa_level_err         :    2;  /*Indicates a programming error of SEC_DPA_LEVEL.*/
+            uint32_t ecdsa_enable_soft_k_err   :    1;  /*Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.*/
+            uint32_t crypt_dpa_enable_err      :    1;  /*Indicates a programming error of CRYPT_DPA_ENABLE.*/
+            uint32_t secure_boot_en_err        :    1;  /*Indicates a programming error of SECURE_BOOT_EN.*/
+            uint32_t secure_boot_aggressive_revoke_err:    1;  /*Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.*/
+            uint32_t reserved22                    :    1;  /*Reserved.*/
+            uint32_t flash_type_err            :    1;  /*Indicates a programming error of FLASH_TYPE.*/
+            uint32_t flash_page_size_err       :    2;  /*Indicates a programming error of FLASH_PAGE_SIZE.*/
+            uint32_t flash_ecc_en_err          :    1;  /*Indicates a programming error of FLASH_ECC_EN.*/
+            uint32_t dis_usb_otg_download_mode_err:    1;  /*Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.*/
+            uint32_t flash_tpuw_err            :    4;  /*Indicates a programming error of FLASH_TPUW.*/
+        };
+        uint32_t val;
+    } rd_repeat_err2;
+    union {
+        struct {
+            uint32_t dis_download_mode_err     :    1;  /*Indicates a programming error of DIS_DOWNLOAD_MODE.*/
+            uint32_t dis_direct_boot_err       :    1;  /*Indicates a programming error of DIS_DIRECT_BOOT.*/
+            uint32_t dis_usb_serial_jtag_rom_print_err:    1;  /*Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.*/
+            uint32_t lock_km_key_err           :    1;  /*TBD*/
+            uint32_t dis_usb_serial_jtag_download_mode_err:    1;  /*Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/
+            uint32_t enable_security_download_err:    1;  /*Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.*/
+            uint32_t uart_print_control_err    :    2;  /*Indicates a programming error of UART_PRINT_CONTROL.*/
+            uint32_t force_send_resume_err     :    1;  /*Indicates a programming error of FORCE_SEND_RESUME.*/
+            uint32_t secure_version_err        :    16;  /*Indicates a programming error of SECURE VERSION.*/
+            uint32_t secure_boot_disable_fast_wake_err:    1;  /*Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.*/
+            uint32_t hys_en_pad_err            :    1;  /*Indicates a programming error of HYS_EN_PAD.*/
+            uint32_t dcdc_vset_err             :    5;  /*Indicates a programming error of DCDC_VSET.*/
+        };
+        uint32_t val;
+    } rd_repeat_err3;
+    union {
+        struct {
+            uint32_t _0pxa_tieh_sel_0_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_0.*/
+            uint32_t _0pxa_tieh_sel_1_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_1.*/
+            uint32_t _0pxa_tieh_sel_2_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_2.*/
+            uint32_t _0pxa_tieh_sel_3_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_3.*/
+            uint32_t km_disable_deploy_mode_err:    4;  /*TBD.*/
+            uint32_t usb_device_drefl_err      :    2;  /*Indicates a programming error of USB_DEVICE_DREFL.*/
+            uint32_t usb_otg11_drefl_err       :    2;  /*Indicates a programming error of USB_OTG11_DREFL.*/
+            uint32_t reserved16                    :    2;  /*Reserved.*/
+            uint32_t hp_pwr_src_sel_err        :    1;  /*Indicates a programming error of HP_PWR_SRC_SEL.*/
+            uint32_t dcdc_vset_en_err          :    1;  /*Indicates a programming error of DCDC_VSET_EN.*/
+            uint32_t dis_wdt_err               :    1;  /*Indicates a programming error of DIS_WDT.*/
+            uint32_t dis_swd_err               :    1;  /*Indicates a programming error of DIS_SWD.*/
+            uint32_t reserved22                    :    2;  /*Reserved.*/
+            uint32_t reserved24                    :    8;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_repeat_err4;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    union {
+        struct {
+            uint32_t mac_sys_err_num           :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t mac_sys_fail              :    1;  /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t sys_part1_err_num         :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t sys_part1_fail            :    1;  /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t usr_data_err_num          :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t usr_data_fail             :    1;  /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t key0_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t key0_fail                 :    1;  /*0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.*/
+            uint32_t key1_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t key1_fail                 :    1;  /*0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.*/
+            uint32_t key2_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t key2_fail                 :    1;  /*0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.*/
+            uint32_t key3_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t key3_fail                 :    1;  /*0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.*/
+            uint32_t key4_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t key4_fail                 :    1;  /*0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.*/
+        };
+        uint32_t val;
+    } rd_rs_err0;
+    union {
+        struct {
+            uint32_t key5_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t key5_fail                 :    1;  /*0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6.*/
+            uint32_t sys_part2_err_num         :    3;  /*The value of this signal means the number of error bytes.*/
+            uint32_t sys_part2_fail            :    1;  /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t reserved8                     :    24;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_rs_err1;
+    union {
+        struct {
+            uint32_t efuse_mem_force_pd        :    1;  /*Set this bit to force eFuse SRAM into power-saving mode.*/
+            uint32_t efuse_mem_clk_force_on    :    1;  /*Set this bit and force to activate clock signal of eFuse SRAM.*/
+            uint32_t efuse_mem_force_pu        :    1;  /*Set this bit to force eFuse SRAM into working mode.*/
+            uint32_t reserved3                     :    13;  /*Reserved.*/
+            uint32_t clk_en                    :    1;  /*Set this bit to force enable eFuse register configuration clock signal.*/
+            uint32_t reserved17                    :    15;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clk;
+    union {
+        struct {
+            uint32_t op_code                   :    16;  /*0x5A5A:  programming operation command 0x5AA5: read operation command.*/
+            uint32_t cfg_ecdsa_blk             :    4;  /*Configures which block to use for ECDSA key output.*/
+            uint32_t reserved20                    :    12;  /*Reserved.*/
+        };
+        uint32_t val;
+    } conf;
+    union {
+        struct {
+            uint32_t state                     :    4;  /*Indicates the state of the eFuse state machine.*/
+            uint32_t otp_load_sw               :    1;  /*The value of OTP_LOAD_SW.*/
+            uint32_t otp_vddq_c_sync2          :    1;  /*The value of OTP_VDDQ_C_SYNC2.*/
+            uint32_t otp_strobe_sw             :    1;  /*The value of OTP_STROBE_SW.*/
+            uint32_t otp_csb_sw                :    1;  /*The value of OTP_CSB_SW.*/
+            uint32_t otp_pgenb_sw              :    1;  /*The value of OTP_PGENB_SW.*/
+            uint32_t otp_vddq_is_sw            :    1;  /*The value of OTP_VDDQ_IS_SW.*/
+            uint32_t blk0_valid_bit_cnt        :    10;  /*Indicates the number of block valid bit.*/
+            uint32_t cur_ecdsa_blk             :    4;  /*Indicates which block is used for ECDSA key output.*/
+            uint32_t reserved24                    :    8;  /*Reserved.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t read_cmd                  :    1;  /*Set this bit to send read command.*/
+            uint32_t pgm_cmd                   :    1;  /*Set this bit to send programming command.*/
+            uint32_t blk_num                   :    4;  /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.*/
+            uint32_t reserved6                     :    26;  /*Reserved.*/
+        };
+        uint32_t val;
+    } cmd;
+    union {
+        struct {
+            uint32_t read_done_int_raw         :    1;  /*The raw bit signal for read_done interrupt.*/
+            uint32_t pgm_done_int_raw          :    1;  /*The raw bit signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t read_done_int_st          :    1;  /*The status signal for read_done interrupt.*/
+            uint32_t pgm_done_int_st           :    1;  /*The status signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t read_done_int_ena         :    1;  /*The enable signal for read_done interrupt.*/
+            uint32_t pgm_done_int_ena          :    1;  /*The enable signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t read_done_int_clr         :    1;  /*The clear signal for read_done interrupt.*/
+            uint32_t pgm_done_int_clr          :    1;  /*The clear signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t dac_clk_div               :    8;  /*Controls the division factor of the rising clock of the programming voltage.*/
+            uint32_t dac_clk_pad_sel           :    1;  /*Don't care.*/
+            uint32_t dac_num                   :    8;  /*Controls the rising period of the programming voltage.*/
+            uint32_t oe_clr                    :    1;  /*Reduces the power supply of the programming voltage.*/
+            uint32_t reserved18                    :    14;  /*Reserved.*/
+        };
+        uint32_t val;
+    } dac_conf;
+    union {
+        struct {
+            uint32_t thr_a                     :    8;  /*Configures the read hold time.*/
+            uint32_t trd                       :    8;  /*Configures the read time.*/
+            uint32_t tsur_a                    :    8;  /*Configures the read setup time.*/
+            uint32_t read_init_num             :    8;  /*Configures the waiting time of reading eFuse memory.*/
+        };
+        uint32_t val;
+    } rd_tim_conf;
+    union {
+        struct {
+            uint32_t tsup_a                    :    8;  /*Configures the programming setup time.*/
+            uint32_t pwr_on_num                :    16;  /*Configures the power up time for VDDQ.*/
+            uint32_t thp_a                     :    8;  /*Configures the programming hold time.*/
+        };
+        uint32_t val;
+    } wr_tim_conf1;
+    union {
+        struct {
+            uint32_t pwr_off_num               :    16;  /*Configures the power outage time for VDDQ.*/
+            uint32_t tpgm                      :    16;  /*Configures the active programming time.*/
+        };
+        uint32_t val;
+    } wr_tim_conf2;
+    union {
+        struct {
+            uint32_t bypass_rs_correction      :    1;  /*Set this bit to bypass reed solomon correction step.*/
+            uint32_t bypass_rs_blk_num         :    11;  /*Configures block number of programming twice operation.*/
+            uint32_t update                    :    1;  /*Set this bit to update multi-bit register signals.*/
+            uint32_t tpgm_inactive             :    8;  /*Configures the inactive programming time.*/
+            uint32_t reserved21                    :    11;  /*Reserved.*/
+        };
+        uint32_t val;
+    } wr_tim_conf0_rs_bypass;
+    union {
+        struct {
+            uint32_t date                      :    28;  /*Stores eFuse version.*/
+            uint32_t reserved28                    :    4;  /*Reserved.*/
+        };
+        uint32_t val;
+    } date;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t apb2otp_wr_dis;
+    uint32_t apb2otp_blk0_backup1_w1;
+    uint32_t apb2otp_blk0_backup1_w2;
+    uint32_t apb2otp_blk0_backup1_w3;
+    uint32_t apb2otp_blk0_backup1_w4;
+    uint32_t apb2otp_blk0_backup1_w5;
+    uint32_t apb2otp_blk0_backup2_w1;
+    uint32_t apb2otp_blk0_backup2_w2;
+    uint32_t apb2otp_blk0_backup2_w3;
+    uint32_t apb2otp_blk0_backup2_w4;
+    uint32_t apb2otp_blk0_backup2_w5;
+    uint32_t apb2otp_blk0_backup3_w1;
+    uint32_t apb2otp_blk0_backup3_w2;
+    uint32_t apb2otp_blk0_backup3_w3;
+    uint32_t apb2otp_blk0_backup3_w4;
+    uint32_t apb2otp_blk0_backup3_w5;
+    uint32_t apb2otp_blk0_backup4_w1;
+    uint32_t apb2otp_blk0_backup4_w2;
+    uint32_t apb2otp_blk0_backup4_w3;
+    uint32_t apb2otp_blk0_backup4_w4;
+    uint32_t apb2otp_blk0_backup4_w5;
+    uint32_t apb2otp_blk1_w1;
+    uint32_t apb2otp_blk1_w2;
+    uint32_t apb2otp_blk1_w3;
+    uint32_t apb2otp_blk1_w4;
+    uint32_t apb2otp_blk1_w5;
+    uint32_t apb2otp_blk1_w6;
+    uint32_t apb2otp_blk1_w7;
+    uint32_t apb2otp_blk1_w8;
+    uint32_t apb2otp_blk1_w9;
+    uint32_t apb2otp_blk2_w1;
+    uint32_t apb2otp_blk2_w2;
+    uint32_t apb2otp_blk2_w3;
+    uint32_t apb2otp_blk2_w4;
+    uint32_t apb2otp_blk2_w5;
+    uint32_t apb2otp_blk2_w6;
+    uint32_t apb2otp_blk2_w7;
+    uint32_t apb2otp_blk2_w8;
+    uint32_t apb2otp_blk2_w9;
+    uint32_t apb2otp_blk2_w10;
+    uint32_t apb2otp_blk2_w11;
+    uint32_t apb2otp_blk3_w1;
+    uint32_t apb2otp_blk3_w2;
+    uint32_t apb2otp_blk3_w3;
+    uint32_t apb2otp_blk3_w4;
+    uint32_t apb2otp_blk3_w5;
+    uint32_t apb2otp_blk3_w6;
+    uint32_t apb2otp_blk3_w7;
+    uint32_t apb2otp_blk3_w8;
+    uint32_t apb2otp_blk3_w9;
+    uint32_t apb2otp_blk3_w10;
+    uint32_t apb2otp_blk3_w11;
+    uint32_t apb2otp_blk4_w1;
+    uint32_t apb2otp_blk4_w2;
+    uint32_t apb2otp_blk4_w3;
+    uint32_t apb2otp_blk4_w4;
+    uint32_t apb2otp_blk4_w5;
+    uint32_t apb2otp_blk4_w6;
+    uint32_t apb2otp_blk4_w7;
+    uint32_t apb2otp_blk4_w8;
+    uint32_t apb2otp_blk4_w9;
+    uint32_t apb2otp_blk4_w10;
+    uint32_t apb2otp_blk4_w11;
+    uint32_t apb2otp_blk5_w1;
+    uint32_t apb2otp_blk5_w2;
+    uint32_t apb2otp_blk5_w3;
+    uint32_t apb2otp_blk5_w4;
+    uint32_t apb2otp_blk5_w5;
+    uint32_t apb2otp_blk5_w6;
+    uint32_t apb2otp_blk5_w7;
+    uint32_t apb2otp_blk5_w8;
+    uint32_t apb2otp_blk5_w9;
+    uint32_t apb2otp_blk5_w10;
+    uint32_t apb2otp_blk5_w11;
+    uint32_t apb2otp_blk6_w1;
+    uint32_t apb2otp_blk6_w2;
+    uint32_t apb2otp_blk6_w3;
+    uint32_t apb2otp_blk6_w4;
+    uint32_t apb2otp_blk6_w5;
+    uint32_t apb2otp_blk6_w6;
+    uint32_t apb2otp_blk6_w7;
+    uint32_t apb2otp_blk6_w8;
+    uint32_t apb2otp_blk6_w9;
+    uint32_t apb2otp_blk6_w10;
+    uint32_t apb2otp_blk6_w11;
+    uint32_t apb2otp_blk7_w1;
+    uint32_t apb2otp_blk7_w2;
+    uint32_t apb2otp_blk7_w3;
+    uint32_t apb2otp_blk7_w4;
+    uint32_t apb2otp_blk7_w5;
+    uint32_t apb2otp_blk7_w6;
+    uint32_t apb2otp_blk7_w7;
+    uint32_t apb2otp_blk7_w8;
+    uint32_t apb2otp_blk7_w9;
+    uint32_t apb2otp_blk7_w10;
+    uint32_t apb2otp_blk7_w11;
+    uint32_t apb2otp_blk8_w1;
+    uint32_t apb2otp_blk8_w2;
+    uint32_t apb2otp_blk8_w3;
+    uint32_t apb2otp_blk8_w4;
+    uint32_t apb2otp_blk8_w5;
+    uint32_t apb2otp_blk8_w6;
+    uint32_t apb2otp_blk8_w7;
+    uint32_t apb2otp_blk8_w8;
+    uint32_t apb2otp_blk8_w9;
+    uint32_t apb2otp_blk8_w10;
+    uint32_t apb2otp_blk8_w11;
+    uint32_t apb2otp_blk9_w1;
+    uint32_t apb2otp_blk9_w2;
+    uint32_t apb2otp_blk9_w3;
+    uint32_t apb2otp_blk9_w4;
+    uint32_t apb2otp_blk9_w5;
+    uint32_t apb2otp_blk9_w6;
+    uint32_t apb2otp_blk9_w7;
+    uint32_t apb2otp_blk9_w8;
+    uint32_t apb2otp_blk9_w9;
+    uint32_t apb2otp_blk9_w10;
+    uint32_t apb2otp_blk9_w11;
+    uint32_t apb2otp_blk10_w1;
+    uint32_t apb2otp_blk10_w2;
+    uint32_t apb2otp_blk10_w3;
+    uint32_t apb2otp_blk10_w4;
+    uint32_t apb2otp_blk10_w5;
+    uint32_t apb2otp_blk10_w6;
+    uint32_t apb2otp_blk10_w7;
+    uint32_t apb2otp_blk10_w8;
+    uint32_t apb2otp_blk10_w9;
+    uint32_t apb2otp_blk10_w10;
+    uint32_t apb2otp_blk10_w11;
+    uint32_t reserved_a04;
+    union {
+        struct {
+            uint32_t apb2otp_enable            :    1;  /*Apb2otp mode enable signal.*/
+            uint32_t reserved1                     :    31;  /*Reserved.*/
+        };
+        uint32_t val;
+    } apb2otp_en;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/ext_mem_defs.h b/components/soc/esp32p4/include/soc/ext_mem_defs.h
new file mode 100644
index 0000000000..6e8f3373ab
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/ext_mem_defs.h
@@ -0,0 +1,152 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "esp_bit_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !SOC_MMU_PAGE_SIZE
+/**
+ * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
+ * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
+ */
+#define SOC_MMU_PAGE_SIZE 0x10000
+#endif
+
+
+#define IRAM0_CACHE_ADDRESS_LOW                  0x40000000
+#define IRAM0_CACHE_ADDRESS_HIGH                 0x50000000
+
+#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
+#define DRAM0_CACHE_ADDRESS_HIGH                 IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
+#define DRAM0_CACHE_OPERATION_HIGH               0x44000000
+
+#define SINGLE_BANK_CACHE_ADDRESS_LOW                0x40000000
+#define SINGLE_BANK_CACHE_ADDRESS_HIGH               0x44000000
+#define DUAL_BANK_CACHE_ADDRESS_LOW                  0x48000000
+#define DUAL_BANK_CACHE_ADDRESS_HIGH                 0x4C000000
+
+#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+
+#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
+#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+
+#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+
+//TODO, remove these cache function dependencies
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 (0x400 * 4)
+#define DCACHE_MMU_SIZE                 (0x400 * 4)
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 (0x400 * 4)
+
+#define MMU_MSPI_ACCESS_FLASH           0
+#define MMU_MSPI_ACCESS_SPIRAM          BIT(10)
+#define MMU_MSPI_VALID                  BIT(12)
+#define MMU_MSPI_INVALID                0
+#define MMU_MSPI_SENSITIVE              BIT(13)
+
+#define MMU_PSRAM_ACCESS_SPIRAM         BIT(10)
+#define MMU_PSRAM_VALID                 BIT(11)
+#define MMU_PSRAM_SENSITIVE             BIT(12)
+
+#define MMU_ACCESS_FLASH                MMU_MSPI_ACCESS_FLASH
+#define MMU_ACCESS_SPIRAM               MMU_MSPI_ACCESS_SPIRAM
+#define MMU_VALID                       MMU_MSPI_VALID
+#define MMU_SENSITIVE                   MMU_MSPI_SENSITIVE
+#define DMMU_SENSITIVE                  MMU_PSRAM_SENSITIVE
+
+#define MMU_INVALID_MASK                MMU_MSPI_VALID
+#define MMU_INVALID                     MMU_MSPI_INVALID
+
+#define DMMU_INVALID_MASK               MMU_PSRAM_VALID
+#define DMMU_INVALID                    0
+
+#define CACHE_MAX_SYNC_NUM 0x400000
+#define CACHE_MAX_LOCK_NUM 0x8000
+
+/**
+ * MMU entry valid bit mask for mapping value. For an entry:
+ * valid bit + value bits
+ * valid bit is BIT(9), so value bits are 0x1ff
+ */
+#define MMU_VALID_VAL_MASK 0x3ff
+/**
+ * Max MMU available paddr page num.
+ * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * 256 * 64KB, means MMU can support 16MB paddr at most
+ */
+#define MMU_MAX_PADDR_PAGE_NUM    1024
+//MMU entry num
+#define MMU_ENTRY_NUM   1024
+
+/**
+ * This is the mask used for mapping. e.g.:
+ * 0x4200_0000 & MMU_VADDR_MASK
+ */
+#define MMU_VADDR_MASK                  ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
+
+#define SOC_MMU_FLASH_VADDR_BASE                   0x40000000
+#define SOC_MMU_PSRAM_VADDR_BASE                   0x48000000
+
+#define SOC_MMU_FLASH_VADDR_START                  0x40000000
+#define SOC_MMU_FLASH_VADDR_END                    0x44000000
+#define SOC_MMU_PSRAM_VADDR_START                  0x48000000
+#define SOC_MMU_PSRAM_VADDR_END                    0x4C000000
+
+/*------------------------------------------------------------------------------
+ * MMU Linear Address
+ *----------------------------------------------------------------------------*/
+/**
+ * - 64KB MMU page size: the last 0xFFFF, which is the offset
+ * - 1024 MMU entries, needs 0x3F to hold it.
+ *
+ * Therefore, 0x3F,FFFF
+ */
+#define SOC_MMU_MEM_PHYSICAL_LINEAR_CAP            (SOC_MMU_FLASH_VADDR_BASE ^ SOC_MMU_PSRAM_VADDR_BASE)
+#define SOC_MMU_LINEAR_FLASH_ADDR_MASK             (0xBFFFFFF)
+#define SOC_MMU_LINEAR_PARSM_ADDR_MASK             (0xBFFFFFF | SOC_MMU_MEM_PHYSICAL_LINEAR_CAP)
+
+/**
+ * - If high linear address isn't 0, this means MMU can recognize these addresses
+ * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
+ *   Under this condition, we use the max linear space.
+ */
+#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW      (SOC_MMU_FLASH_VADDR_START & SOC_MMU_LINEAR_FLASH_ADDR_MASK)
+#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_FLASH_ADDR_MASK + 1)
+#define SOC_MMU_FLASH_LINEAR_ADDRESS_SIZE     (SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH - SOC_MMU_FLASH_LINEAR_ADDRESS_LOW)
+
+#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW      (SOC_MMU_PSRAM_VADDR_START & SOC_MMU_LINEAR_PARSM_ADDR_MASK)
+#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_PARSM_ADDR_MASK + 1)
+#define SOC_MMU_PSRAM_LINEAR_ADDRESS_SIZE     (SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH - SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW)
+
+/**
+ * I/D share the MMU linear address range
+ */
+_Static_assert((SOC_MMU_FLASH_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP) == (SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP), \
+                "IRAM0 and DRAM0 raw linear address should be same");
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/extmem_reg.h b/components/soc/esp32p4/include/soc/extmem_reg.h
new file mode 100644
index 0000000000..a9cb693586
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/extmem_reg.h
@@ -0,0 +1,871 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define EXTMEM_L1_CACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x4)
+/* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
+#define EXTMEM_L1_CACHE_SHUT_DBUS    (BIT(1))
+#define EXTMEM_L1_CACHE_SHUT_DBUS_M  (BIT(1))
+#define EXTMEM_L1_CACHE_SHUT_DBUS_V  0x1
+#define EXTMEM_L1_CACHE_SHUT_DBUS_S  1
+/* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
+#define EXTMEM_L1_CACHE_SHUT_IBUS    (BIT(0))
+#define EXTMEM_L1_CACHE_SHUT_IBUS_M  (BIT(0))
+#define EXTMEM_L1_CACHE_SHUT_IBUS_V  0x1
+#define EXTMEM_L1_CACHE_SHUT_IBUS_S  0
+
+#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x20)
+/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
+#define EXTMEM_L1_CACHE_WRAP    (BIT(4))
+#define EXTMEM_L1_CACHE_WRAP_M  (BIT(4))
+#define EXTMEM_L1_CACHE_WRAP_V  0x1
+#define EXTMEM_L1_CACHE_WRAP_S  4
+
+#define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x24)
+/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
+/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M  (BIT(18))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S  18
+/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power
+down.*/
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M  (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S  17
+/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating,
+0: open clock gating..*/
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M  (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S  16
+
+#define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x28)
+/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
+/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u
+p.*/
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M  (BIT(18))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S  18
+/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+ down.*/
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M  (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S  17
+/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to close clock gating of  L1-Cache data memory. 1: close gating,
+ 0: open clock gating..*/
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M  (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S  16
+
+#define EXTMEM_L1_CACHE_FREEZE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x2C)
+/* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
+/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or
+not. 0: not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_FREEZE_DONE    (BIT(18))
+#define EXTMEM_L1_CACHE_FREEZE_DONE_M  (BIT(18))
+#define EXTMEM_L1_CACHE_FREEZE_DONE_V  0x1
+#define EXTMEM_L1_CACHE_FREEZE_DONE_S  18
+/* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+ will not stuck. 1: a miss-access will stuck..*/
+#define EXTMEM_L1_CACHE_FREEZE_MODE    (BIT(17))
+#define EXTMEM_L1_CACHE_FREEZE_MODE_M  (BIT(17))
+#define EXTMEM_L1_CACHE_FREEZE_MODE_V  0x1
+#define EXTMEM_L1_CACHE_FREEZE_MODE_S  17
+/* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof
+tware..*/
+#define EXTMEM_L1_CACHE_FREEZE_EN    (BIT(16))
+#define EXTMEM_L1_CACHE_FREEZE_EN_M  (BIT(16))
+#define EXTMEM_L1_CACHE_FREEZE_EN_V  0x1
+#define EXTMEM_L1_CACHE_FREEZE_EN_S  16
+
+#define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x30)
+/* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable,
+1: enable..*/
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M  (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S  17
+/* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1
+: enable..*/
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M  (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S  16
+
+#define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x34)
+/* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1
+: enable..*/
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M  (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S  17
+/* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+ enable..*/
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M  (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S  16
+
+#define EXTMEM_L1_CACHE_PRELOCK_CONF_REG          (DR_REG_EXTMEM_BASE + 0x78)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M  (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V  0x1
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S  1
+/* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M  (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V  0x1
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S  0
+
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x7C)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the first section
+of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0
+_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x80)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the second section
+ of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT
+1_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x84)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
+/*description: Those bits are used to configure the size of the second section of prelock on L1
+-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x3FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
+/* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
+/*description: Those bits are used to configure the size of the first section of prelock on L1-
+Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x3FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x88)
+/* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_LOCK_DONE    (BIT(2))
+#define EXTMEM_L1_CACHE_LOCK_DONE_M  (BIT(2))
+#define EXTMEM_L1_CACHE_LOCK_DONE_V  0x1
+#define EXTMEM_L1_CACHE_LOCK_DONE_S  2
+/* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
+ unlock operation done.*/
+#define EXTMEM_L1_CACHE_UNLOCK_ENA    (BIT(1))
+#define EXTMEM_L1_CACHE_UNLOCK_ENA_M  (BIT(1))
+#define EXTMEM_L1_CACHE_UNLOCK_ENA_V  0x1
+#define EXTMEM_L1_CACHE_UNLOCK_ENA_S  1
+/* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
+ock operation done.*/
+#define EXTMEM_L1_CACHE_LOCK_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_LOCK_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_LOCK_ENA_V  0x1
+#define EXTMEM_L1_CACHE_LOCK_ENA_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_MAP_REG          (DR_REG_EXTMEM_BASE + 0x8C)
+/* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: Those bits are used to indicate which caches in the two-level cache structure wi
+ll apply this lock/unlock operation. [4]: L1-Cache.*/
+#define EXTMEM_L1_CACHE_LOCK_MAP    0x0000003F
+#define EXTMEM_L1_CACHE_LOCK_MAP_M  ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S))
+#define EXTMEM_L1_CACHE_LOCK_MAP_V  0x3F
+#define EXTMEM_L1_CACHE_LOCK_MAP_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x90)
+/* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the lock/unlock op
+eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_LOCK_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_LOCK_ADDR_M  ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S))
+#define EXTMEM_L1_CACHE_LOCK_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_LOCK_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x94)
+/* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
+ould be used together with CACHE_LOCK_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_LOCK_SIZE    0x0000FFFF
+#define EXTMEM_L1_CACHE_LOCK_SIZE_M  ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S))
+#define EXTMEM_L1_CACHE_LOCK_SIZE_V  0xFFFF
+#define EXTMEM_L1_CACHE_LOCK_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x98)
+/* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
+, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE    (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_DONE_M  (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_DONE_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_S  4
+/* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
+hardware after writeback-invalidate operation done. Note that this bit and the o
+ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
+, that is, those bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V  0x1
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
+ter writeback operation done. Note that this bit and the other sync-bits (invali
+date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+those bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA    (BIT(2))
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA_M  (BIT(2))
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA_V  0x1
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA_S  2
+/* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable clean operation. It will be cleared by hardware after
+clean operation done. Note that this bit and the other sync-bits (invalidate_ena
+, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
+e bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_CLEAN_ENA    (BIT(1))
+#define EXTMEM_L1_CACHE_CLEAN_ENA_M  (BIT(1))
+#define EXTMEM_L1_CACHE_CLEAN_ENA_V  0x1
+#define EXTMEM_L1_CACHE_CLEAN_ENA_S  1
+/* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
+fter invalidate operation done. Note that this bit and the other sync-bits (clea
+n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+ those bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA_V  0x1
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_MAP_REG          (DR_REG_EXTMEM_BASE + 0x9C)
+/* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
+/*description: Those bits are used to indicate which caches in the two-level cache structure wi
+ll apply the sync operation.  [4]: L1-Cache.*/
+#define EXTMEM_L1_CACHE_SYNC_MAP    0x0000003F
+#define EXTMEM_L1_CACHE_SYNC_MAP_M  ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S))
+#define EXTMEM_L1_CACHE_SYNC_MAP_V  0x3F
+#define EXTMEM_L1_CACHE_SYNC_MAP_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xA0)
+/* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the sync operation
+, which should be used together with CACHE_SYNC_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_SYNC_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_SYNC_ADDR_M  ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S))
+#define EXTMEM_L1_CACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_SYNC_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xA4)
+/* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Those bits are used to configure the size of the sync operation, which should be
+ used together with CACHE_SYNC_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_SYNC_SIZE    0x00FFFFFF
+#define EXTMEM_L1_CACHE_SYNC_SIZE_M  ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S))
+#define EXTMEM_L1_CACHE_SYNC_SIZE_V  0xFFFFFF
+#define EXTMEM_L1_CACHE_SYNC_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xD8)
+/* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
+/*description: The bit is used to set  the gid of l1 cache preload..*/
+#define EXTMEM_L1_CACHE_PRELOAD_RGID    0x0000000F
+#define EXTMEM_L1_CACHE_PRELOAD_RGID_M  ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S))
+#define EXTMEM_L1_CACHE_PRELOAD_RGID_V  0xF
+#define EXTMEM_L1_CACHE_PRELOAD_RGID_S  3
+/* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
+: descending..*/
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER    (BIT(2))
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER_M  (BIT(2))
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER_V  0x1
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER_S  2
+/* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
+ finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_PRELOAD_DONE    (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOAD_DONE_M  (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOAD_DONE_V  0x1
+#define EXTMEM_L1_CACHE_PRELOAD_DONE_S  1
+/* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h
+ardware automatically after preload operation is done..*/
+#define EXTMEM_L1_CACHE_PRELOAD_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOAD_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOAD_ENA_V  0x1
+#define EXTMEM_L1_CACHE_PRELOAD_ENA_S  0
+
+#define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xDC)
+/* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of preload on L1-Cach
+e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR_M  ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S))
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR_S  0
+
+#define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xE0)
+/* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: Those bits are used to configure the size of the first section of prelock on L1-
+Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE    0x00003FFF
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE_M  ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S))
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE_V  0x3FFF
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x134)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0
+/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x3
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+ ascending. 1: descending..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M  (BIT(2))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S  2
+/* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o
+r not. 0: not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M  (BIT(1))
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S  1
+/* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable and disable autoload operation on L1-Cache.  1: enable
+, 0: disable..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x138)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the first section
+for autoload operation on L1-Cache. Note that it should be used together with L1
+_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x13C)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
+/*description: Those bits are used to configure the size of the first section for autoload oper
+ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
+CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x140)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the second section
+ for autoload operation on L1-Cache. Note that it should be used together with L
+1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x144)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
+/*description: Those bits are used to configure the size of the second section for autoload ope
+ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
+SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x158)
+/* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
+1-DCache due to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_ENA    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ENA_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ENA_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_ENA_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
+1-DCache due to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_ENA    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ENA_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ENA_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_ENA_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x15C)
+/* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
+ue to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_CLR    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_CLR_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_CLR_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_CLR_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
+ue to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_CLR    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_CLR_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_CLR_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_CLR_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x160)
+/* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
+e due to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_RAW    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_RAW_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_RAW_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_RAW_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
+e due to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_RAW    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_RAW_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_RAW_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_RAW_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x164)
+/* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
+n L1-DCache due to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_ST    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ST_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ST_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_ST_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
+n L1-DCache due to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_ST    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ST_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ST_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_ST_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x168)
+/* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
+to cpu accesses L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x16C)
+/* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
+o cpu accesses L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x170)
+/* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x174)
+/* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
+ue to cpu accesses L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_ST    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_ST_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x178)
+/* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
+#define EXTMEM_L1_DBUS_CNT_CLR    (BIT(21))
+#define EXTMEM_L1_DBUS_CNT_CLR_M  (BIT(21))
+#define EXTMEM_L1_DBUS_CNT_CLR_V  0x1
+#define EXTMEM_L1_DBUS_CNT_CLR_S  21
+/* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
+#define EXTMEM_L1_IBUS_CNT_CLR    (BIT(20))
+#define EXTMEM_L1_IBUS_CNT_CLR_M  (BIT(20))
+#define EXTMEM_L1_IBUS_CNT_CLR_V  0x1
+#define EXTMEM_L1_IBUS_CNT_CLR_S  20
+/* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
+#define EXTMEM_L1_DBUS_CNT_ENA    (BIT(5))
+#define EXTMEM_L1_DBUS_CNT_ENA_M  (BIT(5))
+#define EXTMEM_L1_DBUS_CNT_ENA_V  0x1
+#define EXTMEM_L1_DBUS_CNT_ENA_S  5
+/* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
+#define EXTMEM_L1_IBUS_CNT_ENA    (BIT(4))
+#define EXTMEM_L1_IBUS_CNT_ENA_M  (BIT(4))
+#define EXTMEM_L1_IBUS_CNT_ENA_V  0x1
+#define EXTMEM_L1_IBUS_CNT_ENA_S  4
+
+#define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1BC)
+/* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of hits when bus0 accesses L1-Cache..*/
+#define EXTMEM_L1_IBUS_HIT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_HIT_CNT_M  ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S))
+#define EXTMEM_L1_IBUS_HIT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_HIT_CNT_S  0
+
+#define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C0)
+/* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of missing when bus0 accesses L1-Cache..*/
+#define EXTMEM_L1_IBUS_MISS_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_MISS_CNT_M  ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S))
+#define EXTMEM_L1_IBUS_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_MISS_CNT_S  0
+
+#define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C4)
+/* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/
+#define EXTMEM_L1_IBUS_CONFLICT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_CONFLICT_CNT_M  ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S))
+#define EXTMEM_L1_IBUS_CONFLICT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_CONFLICT_CNT_S  0
+
+#define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C8)
+/* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
+bus0 accessing L1-Cache..*/
+#define EXTMEM_L1_IBUS_NXTLVL_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_NXTLVL_CNT_M  ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S))
+#define EXTMEM_L1_IBUS_NXTLVL_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_NXTLVL_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1CC)
+/* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of hits when bus1 accesses L1-Cache..*/
+#define EXTMEM_L1_DBUS_HIT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_HIT_CNT_M  ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S))
+#define EXTMEM_L1_DBUS_HIT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_HIT_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D0)
+/* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of missing when bus1 accesses L1-Cache..*/
+#define EXTMEM_L1_DBUS_MISS_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_MISS_CNT_M  ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S))
+#define EXTMEM_L1_DBUS_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_MISS_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D4)
+/* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/
+#define EXTMEM_L1_DBUS_CONFLICT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_CONFLICT_CNT_M  ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S))
+#define EXTMEM_L1_DBUS_CONFLICT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_CONFLICT_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D8)
+/* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
+bus1 accessing L1-Cache..*/
+#define EXTMEM_L1_DBUS_NXTLVL_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_NXTLVL_CNT_M  ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S))
+#define EXTMEM_L1_DBUS_NXTLVL_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_NXTLVL_CNT_S  0
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x21C)
+/* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: The register records the attribution of fail-access when cache accesses L1-Cache
+..*/
+#define EXTMEM_L1_CACHE_FAIL_ATTR    0x0000FFFF
+#define EXTMEM_L1_CACHE_FAIL_ATTR_M  ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S))
+#define EXTMEM_L1_CACHE_FAIL_ATTR_V  0xFFFF
+#define EXTMEM_L1_CACHE_FAIL_ATTR_S  16
+/* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/
+#define EXTMEM_L1_CACHE_FAIL_ID    0x0000FFFF
+#define EXTMEM_L1_CACHE_FAIL_ID_M  ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S))
+#define EXTMEM_L1_CACHE_FAIL_ID_V  0xFFFF
+#define EXTMEM_L1_CACHE_FAIL_ID_S  0
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x220)
+/* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the address of fail-access when cache accesses L1-Cache..*/
+#define EXTMEM_L1_CACHE_FAIL_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_FAIL_ADDR_M  ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S))
+#define EXTMEM_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_FAIL_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x224)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op
+eration is done, interrupt occurs..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x228)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat
+ion is done..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x22C)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
+curs..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er
+ror occurs..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+ done..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x230)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
+r..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
+peration is done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre
+load-operation is done..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG          (DR_REG_EXTMEM_BASE + 0x234)
+/* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: The values 0-2 are available which means sync map, command conflict and size are
+ error in Cache System..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE    0x00000003
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M  ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S))
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V  0x3
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S  12
+/* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE    0x00000003
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE_M  ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S))
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE_V  0x3
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE_S  8
+
+#define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x238)
+/* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
+y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
+#define EXTMEM_L1_CACHE_SYNC_RST    (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_RST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_RST_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_RST_S  4
+
+#define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x23C)
+/* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+only be used to initialize preload-logic when some fatal error of preload-logic
+occurs..*/
+#define EXTMEM_L1_CACHE_PLD_RST    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_RST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_RST_V  0x1
+#define EXTMEM_L1_CACHE_PLD_RST_S  4
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x240)
+/* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au
+toload will not work in L1-Cache. This bit should not be active when autoload wo
+rks in L1-Cache..*/
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR_V  0x1
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR_S  4
+
+#define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_EXTMEM_BASE + 0x244)
+/* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
+llocate request is responsed but not completed..*/
+#define EXTMEM_L1_CACHE_UNALLOC_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_UNALLOC_CLR_V  0x1
+#define EXTMEM_L1_CACHE_UNALLOC_CLR_S  4
+
+#define EXTMEM_L1_CACHE_OBJECT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x248)
+/* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi
+th the others fields inside this register..*/
+#define EXTMEM_L1_CACHE_MEM_OBJECT    (BIT(10))
+#define EXTMEM_L1_CACHE_MEM_OBJECT_M  (BIT(10))
+#define EXTMEM_L1_CACHE_MEM_OBJECT_V  0x1
+#define EXTMEM_L1_CACHE_MEM_OBJECT_S  10
+/* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
+h the others fields inside this register..*/
+#define EXTMEM_L1_CACHE_TAG_OBJECT    (BIT(4))
+#define EXTMEM_L1_CACHE_TAG_OBJECT_M  (BIT(4))
+#define EXTMEM_L1_CACHE_TAG_OBJECT_V  0x1
+#define EXTMEM_L1_CACHE_TAG_OBJECT_S  4
+
+#define EXTMEM_L1_CACHE_WAY_OBJECT_REG          (DR_REG_EXTMEM_BASE + 0x24C)
+/* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
+: way1, 2: way2, 3: way3, ?, 7: way7..*/
+#define EXTMEM_L1_CACHE_WAY_OBJECT    0x00000007
+#define EXTMEM_L1_CACHE_WAY_OBJECT_M  ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S))
+#define EXTMEM_L1_CACHE_WAY_OBJECT_V  0x7
+#define EXTMEM_L1_CACHE_WAY_OBJECT_S  0
+
+#define EXTMEM_L1_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x250)
+/* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
+/*description: Those bits stores the virtual address which will decide where inside the specifi
+ed tag memory object will be accessed..*/
+#define EXTMEM_L1_CACHE_VADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_VADDR_M  ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S))
+#define EXTMEM_L1_CACHE_VADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_VADDR_S  0
+
+#define EXTMEM_L1_CACHE_DEBUG_BUS_REG          (DR_REG_EXTMEM_BASE + 0x254)
+/* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
+/*description: This is a constant place where we can write data to or read data from the tag/da
+ta memory on the specified cache..*/
+#define EXTMEM_L1_CACHE_DEBUG_BUS    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_DEBUG_BUS_M  ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S))
+#define EXTMEM_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_DEBUG_BUS_S  0
+
+#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
+/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */
+/*description: version control register. Note that this default value stored is the latest date
+ when the hardware logic was updated..*/
+#define EXTMEM_DATE    0x0FFFFFFF
+#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
+#define EXTMEM_DATE_V  0xFFFFFFF
+#define EXTMEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/extmem_struct.h b/components/soc/esp32p4/include/soc/extmem_struct.h
new file mode 100644
index 0000000000..dbd90f719a
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/extmem_struct.h
@@ -0,0 +1,5747 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_undef_op:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_icache_ctrl_reg_t;
+
+/** Type of l1_cache_ctrl register
+ *  L1 data Cache(L1-Cache) control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus0:1;
+        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus1:1;
+        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus2:1;
+        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus3:1;
+        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_undef_op:4;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l1_cache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         */
+        uint32_t l2_cache_shut_dma:1;
+        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_cache_undef_op:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} extmem_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
+         *  L1-Cache.  1: disable, 1: enable.
+         */
+        uint32_t l1_cache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} extmem_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2048k:1;
+        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_cache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1k:1;
+        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2k:1;
+        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4k:1;
+        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_8k:1;
+        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_16k:1;
+        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1;
+         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_32k:1;
+        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_64k:1;
+        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_128k:1;
+        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_256k:1;
+        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_512k:1;
+        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1024k:1;
+        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2048k:1;
+        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l1_cache_cachesize_conf_reg_t;
+
+/** Type of l1_cache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_8:1;
+        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_16:1;
+        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_32:1;
+        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_64:1;
+        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_128:1;
+        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_cache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2048k:1;
+        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to enable L1-DCache wrap around mode.
+         */
+        uint32_t l1_cache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Cache Tag Memory Power Control registers */
+/** Type of l1_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_tag_mem_force_on:1;
+        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_tag_mem_force_pd:1;
+        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_tag_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_tag_mem_force_on:1;
+        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_tag_mem_force_pd:1;
+        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_tag_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_on:1;
+        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pd:1;
+        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_on:1;
+        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pd:1;
+        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_tag_mem_force_on:1;
+        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l1_cache_tag_mem_force_pd:1;
+        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_tag_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_tag_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_tag_mem_force_on:1;
+        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l2_cache_tag_mem_force_pd:1;
+        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_tag_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_tag_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Power Control registers */
+/** Type of l1_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_data_mem_force_on:1;
+        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_data_mem_force_pd:1;
+        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_data_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_data_mem_force_on:1;
+        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_data_mem_force_pd:1;
+        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_data_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_on:1;
+        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pd:1;
+        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_on:1;
+        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pd:1;
+        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_data_mem_force_on:1;
+        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_cache_data_mem_force_pd:1;
+        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_data_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_data_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_data_mem_force_on:1;
+        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l2_cache_data_mem_force_pd:1;
+        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_data_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_data_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_cache_freeze_en:1;
+        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_cache_freeze_mode:1;
+        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_rd_en:1;
+        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} extmem_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} extmem_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_rd_en:1;
+        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} extmem_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} extmem_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 prelock.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 prelock.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_cache_prelock_conf register
+ *  L1 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct0_en:1;
+        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct1_en:1;
+        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 cache prelock.
+         */
+        uint32_t l1_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_cache_prelock_conf_reg_t;
+
+/** Type of l1_cache_prelock_sct0_addr register
+ *  L1 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1  Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l2 cache prelock.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of cache_lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+         *  operation done
+         */
+        uint32_t cache_lock_ena:1;
+        /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable unlock operation. It will be cleared by hardware after
+         *  unlock operation done
+         */
+        uint32_t cache_unlock_ena:1;
+        /** cache_lock_done : RO; bitpos: [2]; default: 1;
+         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+         *  not finished. 1: finished.
+         */
+        uint32_t cache_lock_done:1;
+        /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of cache lock/unlock.
+         */
+        uint32_t cache_lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_cache_lock_ctrl_reg_t;
+
+/** Type of cache_lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply this lock/unlock operation. [4]: L1-Cache
+         */
+        uint32_t cache_lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_cache_lock_map_reg_t;
+
+/** Type of cache_lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the lock/unlock
+         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t cache_lock_addr:32;
+    };
+    uint32_t val;
+} extmem_cache_lock_addr_reg_t;
+
+/** Type of cache_lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the lock/unlock operation, which
+         *  should be used together with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t cache_lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of cache_sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  The bit is used to enable invalidate operation. It will be cleared by hardware
+         *  after invalidate operation done. Note that this bit and the other sync-bits
+         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_invalidate_ena:1;
+        /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable clean operation. It will be cleared by hardware after
+         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+         *  bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_clean_ena:1;
+        /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  The bit is used to enable writeback operation. It will be cleared by hardware after
+         *  writeback operation done. Note that this bit and the other sync-bits
+         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_writeback_ena:1;
+        /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+         *  hardware after writeback-invalidate operation done. Note that this bit and the
+         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_writeback_invalidate_ena:1;
+        /** cache_sync_done : RO; bitpos: [4]; default: 0;
+         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+         */
+        uint32_t cache_sync_done:1;
+        /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0;
+         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+         *  writeback, writeback_invalidate)
+         */
+        uint32_t cache_sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} extmem_cache_sync_ctrl_reg_t;
+
+/** Type of cache_sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_map : R/W; bitpos: [5:0]; default: 63;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply the sync operation.  [4]: L1-Cache
+         */
+        uint32_t cache_sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_cache_sync_map_reg_t;
+
+/** Type of cache_sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the sync operation,
+         *  which should be used together with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t cache_sync_addr:32;
+    };
+    uint32_t val;
+} extmem_cache_sync_addr_reg_t;
+
+/** Type of cache_sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_size : R/W; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the sync operation, which should be
+         *  used together with CACHE_SYNC_ADDR_REG
+         */
+        uint32_t cache_sync_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} extmem_cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 preload.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 preload.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_cache_preload_ctrl register
+ *  L1 Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_cache_preload_ena:1;
+        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_cache_preload_done:1;
+        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_cache_preload_order:1;
+        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 cache preload.
+         */
+        uint32_t l1_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_cache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  L1 Cache  preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
+         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_cache_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_cache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l2 cache preload.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 autoload.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 autoload.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_ctrl register
+ *  L1 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_cache_autoload_ena:1;
+        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_autoload_done:1;
+        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_cache_autoload_order:1;
+        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct0_ena:1;
+        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct1_ena:1;
+        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct2_ena:1;
+        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct3_ena:1;
+        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l1 cache autoload.
+         */
+        uint32_t l1_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_ctrl_reg_t;
+
+/** Type of l1_cache_autoload_sct0_addr register
+ *  L1 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct0_size register
+ *  L1 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct0_size_reg_t;
+
+/** Type of l1_cache_autoload_sct1_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct1_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_sct2_addr register
+ *  L1 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct2_size register
+ *  L1 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct2_size_reg_t;
+
+/** Type of l1_cache_autoload_sct3_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct3_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l2 cache autoload.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_ena:1;
+        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_clr:1;
+        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_raw:1;
+        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_st:1;
+        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of l1_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_cache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation done.
+         */
+        uint32_t cache_sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l1_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l1_cache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t cache_sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l1_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l1_cache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t cache_sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t cache_sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l1_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l1_cache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t cache_sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+         *  l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_ena:1;
+        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
+         *  The bit is used to clear ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
+         *  The bit is used to clear ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  The bit is used to clear dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_clr:1;
+        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  The bit is used to clear dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus0_acs_hit_cnt register
+ *  L1-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus0_acs_miss_cnt register
+ *  L1-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus0_acs_conflict_cnt register
+ *  L1-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus0_acs_nxtlvl_cnt register
+ *  L1-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus0 accessing L1-Cache.
+         */
+        uint32_t l1_bus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus1_acs_hit_cnt register
+ *  L1-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus1_acs_miss_cnt register
+ *  L1-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus1_acs_conflict_cnt register
+ *  L1-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus1_acs_nxtlvl_cnt register
+ *  L1-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus1 accessing L1-Cache.
+         */
+        uint32_t l1_bus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_cache_acs_fail_id_attr register
+ *  L1-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_id:16;
+        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of l1_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-Cache.
+         */
+        uint32_t l1_cache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t cache_sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_cache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+         *  works in L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+         *  works in L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
+         *  autoload will not work in L1-Cache. This bit should not be active when autoload
+         *  works in L1-Cache.
+         */
+        uint32_t l1_cache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
+         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+         *  autoload will not work in L2-Cache. This bit should not be active when autoload
+         *  works in L2-Cache.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responsed but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responsed but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 cache where the
+         *  unallocate request is responsed but not completed.
+         */
+        uint32_t l1_cache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responsed but not completed.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
+         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
+         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
+         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
+         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} extmem_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} extmem_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l1_cache_vaddr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_vaddr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
+         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
+         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} extmem_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l2_cache_vaddr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_vaddr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_debug_bus_reg_t;
+
+
+/** Group: Split L1 and L2 registers */
+/** Type of level_split0 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
+         *  Reserved
+         */
+        uint32_t level_split0:32;
+    };
+    uint32_t val;
+} extmem_level_split0_reg_t;
+
+/** Type of level_split1 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
+         *  Reserved
+         */
+        uint32_t level_split1:32;
+    };
+    uint32_t val;
+} extmem_level_split1_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L1 Cache access Attribute propagation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
+         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
+         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} extmem_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} extmem_clock_gate_reg_t;
+
+
+/** Group: Redundancy  register (Prepare for ECO) */
+/** Type of redundancy_sig0 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig0:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig0_reg_t;
+
+/** Type of redundancy_sig1 register
+ *  Cache redundancy signal 1 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig1:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig1_reg_t;
+
+/** Type of redundancy_sig2 register
+ *  Cache redundancy signal 2 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig2:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig2_reg_t;
+
+/** Type of redundancy_sig3 register
+ *  Cache redundancy signal 3 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig3:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig3_reg_t;
+
+/** Type of redundancy_sig4 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} extmem_redundancy_sig4_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35659904;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_date_reg_t;
+
+
+typedef struct extmem_dev_s {
+    volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl;
+    volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
+    volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
+    volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
+    volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
+    volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
+    volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
+    volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl;
+    volatile extmem_cache_lock_map_reg_t cache_lock_map;
+    volatile extmem_cache_lock_addr_reg_t cache_lock_addr;
+    volatile extmem_cache_lock_size_reg_t cache_lock_size;
+    volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl;
+    volatile extmem_cache_sync_map_reg_t cache_sync_map;
+    volatile extmem_cache_sync_addr_reg_t cache_sync_addr;
+    volatile extmem_cache_sync_size_reg_t cache_sync_size;
+    volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
+    volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
+    volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
+    volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
+    volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
+    volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
+    volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
+    volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
+    volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
+    volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
+    volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
+    volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
+    volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
+    volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
+    volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
+    volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
+    volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
+    volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
+    volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
+    volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
+    volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
+    volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
+    volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
+    volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
+    volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
+    volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
+    volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
+    volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr;
+    volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    volatile extmem_level_split0_reg_t level_split0;
+    volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
+    volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
+    volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
+    volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr;
+    volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    volatile extmem_level_split1_reg_t level_split1;
+    volatile extmem_clock_gate_reg_t clock_gate;
+    volatile extmem_redundancy_sig0_reg_t redundancy_sig0;
+    volatile extmem_redundancy_sig1_reg_t redundancy_sig1;
+    volatile extmem_redundancy_sig2_reg_t redundancy_sig2;
+    volatile extmem_redundancy_sig3_reg_t redundancy_sig3;
+    volatile extmem_redundancy_sig4_reg_t redundancy_sig4;
+    uint32_t reserved_3c4[14];
+    volatile extmem_date_reg_t date;
+} extmem_dev_t;
+
+extern extmem_dev_t EXTMEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/gdma_channel.h b/components/soc/esp32p4/include/soc/gdma_channel.h
new file mode 100644
index 0000000000..785d920785
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/gdma_channel.h
@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
+#define SOC_GDMA_TRIG_PERIPH_M2M0    (-1)
+#define SOC_GDMA_TRIG_PERIPH_SPI2    (0)
+#define SOC_GDMA_TRIG_PERIPH_UHCI0   (2)
+#define SOC_GDMA_TRIG_PERIPH_I2S0    (3)
+#define SOC_GDMA_TRIG_PERIPH_AES0    (6)
+#define SOC_GDMA_TRIG_PERIPH_SHA0    (7)
+#define SOC_GDMA_TRIG_PERIPH_ADC0    (8)
+#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
diff --git a/components/soc/esp32p4/include/soc/gpio_pins.h b/components/soc/esp32p4/include/soc/gpio_pins.h
new file mode 100644
index 0000000000..7731c871b0
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/gpio_pins.h
@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/gpio_sd_reg.h b/components/soc/esp32p4/include/soc/gpio_sd_reg.h
new file mode 100644
index 0000000000..3173778fda
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/gpio_sd_reg.h
@@ -0,0 +1,1455 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIOSD_SIGMADELTA0_REG register
+ *  Duty Cycle Configure Register of SDM0
+ */
+#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA1_REG register
+ *  Duty Cycle Configure Register of SDM1
+ */
+#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA2_REG register
+ *  Duty Cycle Configure Register of SDM2
+ */
+#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA3_REG register
+ *  Duty Cycle Configure Register of SDM3
+ */
+#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA4_REG register
+ *  Duty Cycle Configure Register of SDM4
+ */
+#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA5_REG register
+ *  Duty Cycle Configure Register of SDM5
+ */
+#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA6_REG register
+ *  Duty Cycle Configure Register of SDM6
+ */
+#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA7_REG register
+ *  Duty Cycle Configure Register of SDM7
+ */
+#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIOSD_SD0_IN    0x000000FFU
+#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIOSD_SD0_IN_V  0x000000FFU
+#define GPIOSD_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIOSD_SD0_PRESCALE    0x000000FFU
+#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
+#define GPIOSD_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA_MISC_REG register
+ *  MISC Register
+ */
+#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24)
+/** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Clock enable bit of sigma delta modulation.
+ */
+#define GPIOSD_FUNCTION_CLK_EN    (BIT(30))
+#define GPIOSD_FUNCTION_CLK_EN_M  (GPIOSD_FUNCTION_CLK_EN_V << GPIOSD_FUNCTION_CLK_EN_S)
+#define GPIOSD_FUNCTION_CLK_EN_V  0x00000001U
+#define GPIOSD_FUNCTION_CLK_EN_S  30
+/** GPIOSD_SPI_SWAP : R/W; bitpos: [31]; default: 0;
+ *  Reserved.
+ */
+#define GPIOSD_SPI_SWAP    (BIT(31))
+#define GPIOSD_SPI_SWAP_M  (GPIOSD_SPI_SWAP_V << GPIOSD_SPI_SWAP_S)
+#define GPIOSD_SPI_SWAP_V  0x00000001U
+#define GPIOSD_SPI_SWAP_S  31
+
+/** GPIOSD_GLITCH_FILTER_CH0_REG register
+ *  Glitch Filter Configure Register of Channel0
+ */
+#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH1_REG register
+ *  Glitch Filter Configure Register of Channel1
+ */
+#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH2_REG register
+ *  Glitch Filter Configure Register of Channel2
+ */
+#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH3_REG register
+ *  Glitch Filter Configure Register of Channel3
+ */
+#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH4_REG register
+ *  Glitch Filter Configure Register of Channel4
+ */
+#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH5_REG register
+ *  Glitch Filter Configure Register of Channel5
+ */
+#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH6_REG register
+ *  Glitch Filter Configure Register of Channel6
+ */
+#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH7_REG register
+ *  Glitch Filter Configure Register of Channel7
+ */
+#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIOSD_FILTER_CH0_EN    (BIT(0))
+#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
+#define GPIOSD_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_ETM_EVENT_CH0_CFG_REG register
+ *  Etm Config register of Channel0
+ */
+#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH1_CFG_REG register
+ *  Etm Config register of Channel1
+ */
+#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH2_CFG_REG register
+ *  Etm Config register of Channel2
+ */
+#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH3_CFG_REG register
+ *  Etm Config register of Channel3
+ */
+#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH4_CFG_REG register
+ *  Etm Config register of Channel4
+ */
+#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH5_CFG_REG register
+ *  Etm Config register of Channel5
+ */
+#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH6_CFG_REG register
+ *  Etm Config register of Channel6
+ */
+#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH7_CFG_REG register
+ *  Etm Config register of Channel7
+ */
+#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIOSD_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_TASK_P0_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0)
+/** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO0_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO0_EN_M  (GPIOSD_ETM_TASK_GPIO0_EN_V << GPIOSD_ETM_TASK_GPIO0_EN_S)
+#define GPIOSD_ETM_TASK_GPIO0_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO0_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO0_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO0_SEL_M  (GPIOSD_ETM_TASK_GPIO0_SEL_V << GPIOSD_ETM_TASK_GPIO0_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO0_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO0_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO1_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO1_EN_M  (GPIOSD_ETM_TASK_GPIO1_EN_V << GPIOSD_ETM_TASK_GPIO1_EN_S)
+#define GPIOSD_ETM_TASK_GPIO1_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO1_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO1_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO1_SEL_M  (GPIOSD_ETM_TASK_GPIO1_SEL_V << GPIOSD_ETM_TASK_GPIO1_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO1_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO1_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO2_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO2_EN_M  (GPIOSD_ETM_TASK_GPIO2_EN_V << GPIOSD_ETM_TASK_GPIO2_EN_S)
+#define GPIOSD_ETM_TASK_GPIO2_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO2_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO2_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO2_SEL_M  (GPIOSD_ETM_TASK_GPIO2_SEL_V << GPIOSD_ETM_TASK_GPIO2_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO2_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO2_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO3_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO3_EN_M  (GPIOSD_ETM_TASK_GPIO3_EN_V << GPIOSD_ETM_TASK_GPIO3_EN_S)
+#define GPIOSD_ETM_TASK_GPIO3_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO3_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO3_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO3_SEL_M  (GPIOSD_ETM_TASK_GPIO3_SEL_V << GPIOSD_ETM_TASK_GPIO3_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO3_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO3_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P1_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4)
+/** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO4_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO4_EN_M  (GPIOSD_ETM_TASK_GPIO4_EN_V << GPIOSD_ETM_TASK_GPIO4_EN_S)
+#define GPIOSD_ETM_TASK_GPIO4_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO4_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO4_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO4_SEL_M  (GPIOSD_ETM_TASK_GPIO4_SEL_V << GPIOSD_ETM_TASK_GPIO4_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO4_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO4_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO5_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO5_EN_M  (GPIOSD_ETM_TASK_GPIO5_EN_V << GPIOSD_ETM_TASK_GPIO5_EN_S)
+#define GPIOSD_ETM_TASK_GPIO5_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO5_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO5_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO5_SEL_M  (GPIOSD_ETM_TASK_GPIO5_SEL_V << GPIOSD_ETM_TASK_GPIO5_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO5_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO5_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO6_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO6_EN_M  (GPIOSD_ETM_TASK_GPIO6_EN_V << GPIOSD_ETM_TASK_GPIO6_EN_S)
+#define GPIOSD_ETM_TASK_GPIO6_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO6_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO6_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO6_SEL_M  (GPIOSD_ETM_TASK_GPIO6_SEL_V << GPIOSD_ETM_TASK_GPIO6_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO6_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO6_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO7_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO7_EN_M  (GPIOSD_ETM_TASK_GPIO7_EN_V << GPIOSD_ETM_TASK_GPIO7_EN_S)
+#define GPIOSD_ETM_TASK_GPIO7_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO7_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO7_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO7_SEL_M  (GPIOSD_ETM_TASK_GPIO7_SEL_V << GPIOSD_ETM_TASK_GPIO7_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO7_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO7_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P2_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8)
+/** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO8_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO8_EN_M  (GPIOSD_ETM_TASK_GPIO8_EN_V << GPIOSD_ETM_TASK_GPIO8_EN_S)
+#define GPIOSD_ETM_TASK_GPIO8_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO8_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO8_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO8_SEL_M  (GPIOSD_ETM_TASK_GPIO8_SEL_V << GPIOSD_ETM_TASK_GPIO8_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO8_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO8_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO9_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO9_EN_M  (GPIOSD_ETM_TASK_GPIO9_EN_V << GPIOSD_ETM_TASK_GPIO9_EN_S)
+#define GPIOSD_ETM_TASK_GPIO9_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO9_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO9_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO9_SEL_M  (GPIOSD_ETM_TASK_GPIO9_SEL_V << GPIOSD_ETM_TASK_GPIO9_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO9_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO9_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO10_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO10_EN_M  (GPIOSD_ETM_TASK_GPIO10_EN_V << GPIOSD_ETM_TASK_GPIO10_EN_S)
+#define GPIOSD_ETM_TASK_GPIO10_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO10_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO10_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO10_SEL_M  (GPIOSD_ETM_TASK_GPIO10_SEL_V << GPIOSD_ETM_TASK_GPIO10_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO10_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO10_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO11_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO11_EN_M  (GPIOSD_ETM_TASK_GPIO11_EN_V << GPIOSD_ETM_TASK_GPIO11_EN_S)
+#define GPIOSD_ETM_TASK_GPIO11_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO11_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO11_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO11_SEL_M  (GPIOSD_ETM_TASK_GPIO11_SEL_V << GPIOSD_ETM_TASK_GPIO11_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO11_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO11_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P3_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac)
+/** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO12_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO12_EN_M  (GPIOSD_ETM_TASK_GPIO12_EN_V << GPIOSD_ETM_TASK_GPIO12_EN_S)
+#define GPIOSD_ETM_TASK_GPIO12_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO12_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO12_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO12_SEL_M  (GPIOSD_ETM_TASK_GPIO12_SEL_V << GPIOSD_ETM_TASK_GPIO12_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO12_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO12_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO13_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO13_EN_M  (GPIOSD_ETM_TASK_GPIO13_EN_V << GPIOSD_ETM_TASK_GPIO13_EN_S)
+#define GPIOSD_ETM_TASK_GPIO13_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO13_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO13_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO13_SEL_M  (GPIOSD_ETM_TASK_GPIO13_SEL_V << GPIOSD_ETM_TASK_GPIO13_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO13_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO13_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO14_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO14_EN_M  (GPIOSD_ETM_TASK_GPIO14_EN_V << GPIOSD_ETM_TASK_GPIO14_EN_S)
+#define GPIOSD_ETM_TASK_GPIO14_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO14_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO14_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO14_SEL_M  (GPIOSD_ETM_TASK_GPIO14_SEL_V << GPIOSD_ETM_TASK_GPIO14_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO14_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO14_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO15_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO15_EN_M  (GPIOSD_ETM_TASK_GPIO15_EN_V << GPIOSD_ETM_TASK_GPIO15_EN_S)
+#define GPIOSD_ETM_TASK_GPIO15_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO15_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO15_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO15_SEL_M  (GPIOSD_ETM_TASK_GPIO15_SEL_V << GPIOSD_ETM_TASK_GPIO15_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO15_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO15_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P4_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0)
+/** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO16_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO16_EN_M  (GPIOSD_ETM_TASK_GPIO16_EN_V << GPIOSD_ETM_TASK_GPIO16_EN_S)
+#define GPIOSD_ETM_TASK_GPIO16_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO16_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO16_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO16_SEL_M  (GPIOSD_ETM_TASK_GPIO16_SEL_V << GPIOSD_ETM_TASK_GPIO16_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO16_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO16_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO17_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO17_EN_M  (GPIOSD_ETM_TASK_GPIO17_EN_V << GPIOSD_ETM_TASK_GPIO17_EN_S)
+#define GPIOSD_ETM_TASK_GPIO17_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO17_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO17_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO17_SEL_M  (GPIOSD_ETM_TASK_GPIO17_SEL_V << GPIOSD_ETM_TASK_GPIO17_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO17_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO17_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO18_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO18_EN_M  (GPIOSD_ETM_TASK_GPIO18_EN_V << GPIOSD_ETM_TASK_GPIO18_EN_S)
+#define GPIOSD_ETM_TASK_GPIO18_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO18_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO18_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO18_SEL_M  (GPIOSD_ETM_TASK_GPIO18_SEL_V << GPIOSD_ETM_TASK_GPIO18_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO18_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO18_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO19_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO19_EN_M  (GPIOSD_ETM_TASK_GPIO19_EN_V << GPIOSD_ETM_TASK_GPIO19_EN_S)
+#define GPIOSD_ETM_TASK_GPIO19_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO19_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO19_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO19_SEL_M  (GPIOSD_ETM_TASK_GPIO19_SEL_V << GPIOSD_ETM_TASK_GPIO19_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO19_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO19_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P5_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4)
+/** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO20_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO20_EN_M  (GPIOSD_ETM_TASK_GPIO20_EN_V << GPIOSD_ETM_TASK_GPIO20_EN_S)
+#define GPIOSD_ETM_TASK_GPIO20_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO20_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO20_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO20_SEL_M  (GPIOSD_ETM_TASK_GPIO20_SEL_V << GPIOSD_ETM_TASK_GPIO20_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO20_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO20_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO21_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO21_EN_M  (GPIOSD_ETM_TASK_GPIO21_EN_V << GPIOSD_ETM_TASK_GPIO21_EN_S)
+#define GPIOSD_ETM_TASK_GPIO21_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO21_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO21_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO21_SEL_M  (GPIOSD_ETM_TASK_GPIO21_SEL_V << GPIOSD_ETM_TASK_GPIO21_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO21_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO21_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO22_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO22_EN_M  (GPIOSD_ETM_TASK_GPIO22_EN_V << GPIOSD_ETM_TASK_GPIO22_EN_S)
+#define GPIOSD_ETM_TASK_GPIO22_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO22_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO22_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO22_SEL_M  (GPIOSD_ETM_TASK_GPIO22_SEL_V << GPIOSD_ETM_TASK_GPIO22_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO22_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO22_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO23_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO23_EN_M  (GPIOSD_ETM_TASK_GPIO23_EN_V << GPIOSD_ETM_TASK_GPIO23_EN_S)
+#define GPIOSD_ETM_TASK_GPIO23_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO23_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO23_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO23_SEL_M  (GPIOSD_ETM_TASK_GPIO23_SEL_V << GPIOSD_ETM_TASK_GPIO23_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO23_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO23_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P6_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8)
+/** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO24_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO24_EN_M  (GPIOSD_ETM_TASK_GPIO24_EN_V << GPIOSD_ETM_TASK_GPIO24_EN_S)
+#define GPIOSD_ETM_TASK_GPIO24_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO24_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO24_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO24_SEL_M  (GPIOSD_ETM_TASK_GPIO24_SEL_V << GPIOSD_ETM_TASK_GPIO24_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO24_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO24_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO25_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO25_EN_M  (GPIOSD_ETM_TASK_GPIO25_EN_V << GPIOSD_ETM_TASK_GPIO25_EN_S)
+#define GPIOSD_ETM_TASK_GPIO25_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO25_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO25_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO25_SEL_M  (GPIOSD_ETM_TASK_GPIO25_SEL_V << GPIOSD_ETM_TASK_GPIO25_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO25_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO25_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO26_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO26_EN_M  (GPIOSD_ETM_TASK_GPIO26_EN_V << GPIOSD_ETM_TASK_GPIO26_EN_S)
+#define GPIOSD_ETM_TASK_GPIO26_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO26_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO26_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO26_SEL_M  (GPIOSD_ETM_TASK_GPIO26_SEL_V << GPIOSD_ETM_TASK_GPIO26_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO26_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO26_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO27_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO27_EN_M  (GPIOSD_ETM_TASK_GPIO27_EN_V << GPIOSD_ETM_TASK_GPIO27_EN_S)
+#define GPIOSD_ETM_TASK_GPIO27_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO27_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO27_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO27_SEL_M  (GPIOSD_ETM_TASK_GPIO27_SEL_V << GPIOSD_ETM_TASK_GPIO27_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO27_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO27_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P7_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc)
+/** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO28_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO28_EN_M  (GPIOSD_ETM_TASK_GPIO28_EN_V << GPIOSD_ETM_TASK_GPIO28_EN_S)
+#define GPIOSD_ETM_TASK_GPIO28_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO28_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO28_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO28_SEL_M  (GPIOSD_ETM_TASK_GPIO28_SEL_V << GPIOSD_ETM_TASK_GPIO28_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO28_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO28_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO29_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO29_EN_M  (GPIOSD_ETM_TASK_GPIO29_EN_V << GPIOSD_ETM_TASK_GPIO29_EN_S)
+#define GPIOSD_ETM_TASK_GPIO29_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO29_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO29_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO29_SEL_M  (GPIOSD_ETM_TASK_GPIO29_SEL_V << GPIOSD_ETM_TASK_GPIO29_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO29_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO29_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO30_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO30_EN_M  (GPIOSD_ETM_TASK_GPIO30_EN_V << GPIOSD_ETM_TASK_GPIO30_EN_S)
+#define GPIOSD_ETM_TASK_GPIO30_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO30_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO30_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO30_SEL_M  (GPIOSD_ETM_TASK_GPIO30_SEL_V << GPIOSD_ETM_TASK_GPIO30_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO30_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO30_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO31_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO31_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO31_EN_M  (GPIOSD_ETM_TASK_GPIO31_EN_V << GPIOSD_ETM_TASK_GPIO31_EN_S)
+#define GPIOSD_ETM_TASK_GPIO31_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO31_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO31_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO31_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO31_SEL_M  (GPIOSD_ETM_TASK_GPIO31_SEL_V << GPIOSD_ETM_TASK_GPIO31_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO31_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO31_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P8_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0)
+/** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO32_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO32_EN_M  (GPIOSD_ETM_TASK_GPIO32_EN_V << GPIOSD_ETM_TASK_GPIO32_EN_S)
+#define GPIOSD_ETM_TASK_GPIO32_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO32_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO32_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO32_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO32_SEL_M  (GPIOSD_ETM_TASK_GPIO32_SEL_V << GPIOSD_ETM_TASK_GPIO32_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO32_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO32_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO33_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO33_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO33_EN_M  (GPIOSD_ETM_TASK_GPIO33_EN_V << GPIOSD_ETM_TASK_GPIO33_EN_S)
+#define GPIOSD_ETM_TASK_GPIO33_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO33_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO33_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO33_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO33_SEL_M  (GPIOSD_ETM_TASK_GPIO33_SEL_V << GPIOSD_ETM_TASK_GPIO33_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO33_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO33_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO34_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO34_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO34_EN_M  (GPIOSD_ETM_TASK_GPIO34_EN_V << GPIOSD_ETM_TASK_GPIO34_EN_S)
+#define GPIOSD_ETM_TASK_GPIO34_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO34_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO34_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO34_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO34_SEL_M  (GPIOSD_ETM_TASK_GPIO34_SEL_V << GPIOSD_ETM_TASK_GPIO34_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO34_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO34_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO35_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO35_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO35_EN_M  (GPIOSD_ETM_TASK_GPIO35_EN_V << GPIOSD_ETM_TASK_GPIO35_EN_S)
+#define GPIOSD_ETM_TASK_GPIO35_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO35_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO35_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO35_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO35_SEL_M  (GPIOSD_ETM_TASK_GPIO35_SEL_V << GPIOSD_ETM_TASK_GPIO35_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO35_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO35_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P9_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4)
+/** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO36_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO36_EN_M  (GPIOSD_ETM_TASK_GPIO36_EN_V << GPIOSD_ETM_TASK_GPIO36_EN_S)
+#define GPIOSD_ETM_TASK_GPIO36_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO36_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO36_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO36_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO36_SEL_M  (GPIOSD_ETM_TASK_GPIO36_SEL_V << GPIOSD_ETM_TASK_GPIO36_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO36_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO36_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO37_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO37_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO37_EN_M  (GPIOSD_ETM_TASK_GPIO37_EN_V << GPIOSD_ETM_TASK_GPIO37_EN_S)
+#define GPIOSD_ETM_TASK_GPIO37_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO37_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO37_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO37_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO37_SEL_M  (GPIOSD_ETM_TASK_GPIO37_SEL_V << GPIOSD_ETM_TASK_GPIO37_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO37_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO37_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO38_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO38_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO38_EN_M  (GPIOSD_ETM_TASK_GPIO38_EN_V << GPIOSD_ETM_TASK_GPIO38_EN_S)
+#define GPIOSD_ETM_TASK_GPIO38_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO38_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO38_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO38_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO38_SEL_M  (GPIOSD_ETM_TASK_GPIO38_SEL_V << GPIOSD_ETM_TASK_GPIO38_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO38_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO38_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO39_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO39_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO39_EN_M  (GPIOSD_ETM_TASK_GPIO39_EN_V << GPIOSD_ETM_TASK_GPIO39_EN_S)
+#define GPIOSD_ETM_TASK_GPIO39_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO39_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO39_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO39_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO39_SEL_M  (GPIOSD_ETM_TASK_GPIO39_SEL_V << GPIOSD_ETM_TASK_GPIO39_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO39_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO39_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P10_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8)
+/** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO40_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO40_EN_M  (GPIOSD_ETM_TASK_GPIO40_EN_V << GPIOSD_ETM_TASK_GPIO40_EN_S)
+#define GPIOSD_ETM_TASK_GPIO40_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO40_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO40_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO40_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO40_SEL_M  (GPIOSD_ETM_TASK_GPIO40_SEL_V << GPIOSD_ETM_TASK_GPIO40_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO40_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO40_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO41_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO41_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO41_EN_M  (GPIOSD_ETM_TASK_GPIO41_EN_V << GPIOSD_ETM_TASK_GPIO41_EN_S)
+#define GPIOSD_ETM_TASK_GPIO41_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO41_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO41_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO41_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO41_SEL_M  (GPIOSD_ETM_TASK_GPIO41_SEL_V << GPIOSD_ETM_TASK_GPIO41_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO41_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO41_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO42_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO42_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO42_EN_M  (GPIOSD_ETM_TASK_GPIO42_EN_V << GPIOSD_ETM_TASK_GPIO42_EN_S)
+#define GPIOSD_ETM_TASK_GPIO42_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO42_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO42_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO42_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO42_SEL_M  (GPIOSD_ETM_TASK_GPIO42_SEL_V << GPIOSD_ETM_TASK_GPIO42_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO42_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO42_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO43_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO43_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO43_EN_M  (GPIOSD_ETM_TASK_GPIO43_EN_V << GPIOSD_ETM_TASK_GPIO43_EN_S)
+#define GPIOSD_ETM_TASK_GPIO43_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO43_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO43_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO43_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO43_SEL_M  (GPIOSD_ETM_TASK_GPIO43_SEL_V << GPIOSD_ETM_TASK_GPIO43_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO43_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO43_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P11_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc)
+/** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO44_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO44_EN_M  (GPIOSD_ETM_TASK_GPIO44_EN_V << GPIOSD_ETM_TASK_GPIO44_EN_S)
+#define GPIOSD_ETM_TASK_GPIO44_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO44_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO44_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO44_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO44_SEL_M  (GPIOSD_ETM_TASK_GPIO44_SEL_V << GPIOSD_ETM_TASK_GPIO44_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO44_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO44_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO45_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO45_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO45_EN_M  (GPIOSD_ETM_TASK_GPIO45_EN_V << GPIOSD_ETM_TASK_GPIO45_EN_S)
+#define GPIOSD_ETM_TASK_GPIO45_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO45_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO45_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO45_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO45_SEL_M  (GPIOSD_ETM_TASK_GPIO45_SEL_V << GPIOSD_ETM_TASK_GPIO45_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO45_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO45_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO46_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO46_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO46_EN_M  (GPIOSD_ETM_TASK_GPIO46_EN_V << GPIOSD_ETM_TASK_GPIO46_EN_S)
+#define GPIOSD_ETM_TASK_GPIO46_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO46_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO46_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO46_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO46_SEL_M  (GPIOSD_ETM_TASK_GPIO46_SEL_V << GPIOSD_ETM_TASK_GPIO46_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO46_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO46_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO47_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO47_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO47_EN_M  (GPIOSD_ETM_TASK_GPIO47_EN_V << GPIOSD_ETM_TASK_GPIO47_EN_S)
+#define GPIOSD_ETM_TASK_GPIO47_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO47_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO47_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO47_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO47_SEL_M  (GPIOSD_ETM_TASK_GPIO47_SEL_V << GPIOSD_ETM_TASK_GPIO47_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO47_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO47_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P12_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0)
+/** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO48_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO48_EN_M  (GPIOSD_ETM_TASK_GPIO48_EN_V << GPIOSD_ETM_TASK_GPIO48_EN_S)
+#define GPIOSD_ETM_TASK_GPIO48_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO48_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO48_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO48_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO48_SEL_M  (GPIOSD_ETM_TASK_GPIO48_SEL_V << GPIOSD_ETM_TASK_GPIO48_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO48_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO48_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO49_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO49_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO49_EN_M  (GPIOSD_ETM_TASK_GPIO49_EN_V << GPIOSD_ETM_TASK_GPIO49_EN_S)
+#define GPIOSD_ETM_TASK_GPIO49_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO49_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO49_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO49_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO49_SEL_M  (GPIOSD_ETM_TASK_GPIO49_SEL_V << GPIOSD_ETM_TASK_GPIO49_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO49_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO49_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO50_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO50_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO50_EN_M  (GPIOSD_ETM_TASK_GPIO50_EN_V << GPIOSD_ETM_TASK_GPIO50_EN_S)
+#define GPIOSD_ETM_TASK_GPIO50_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO50_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO50_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO50_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO50_SEL_M  (GPIOSD_ETM_TASK_GPIO50_SEL_V << GPIOSD_ETM_TASK_GPIO50_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO50_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO50_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO51_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO51_EN    (BIT(24))
+#define GPIOSD_ETM_TASK_GPIO51_EN_M  (GPIOSD_ETM_TASK_GPIO51_EN_V << GPIOSD_ETM_TASK_GPIO51_EN_S)
+#define GPIOSD_ETM_TASK_GPIO51_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO51_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO51_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO51_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO51_SEL_M  (GPIOSD_ETM_TASK_GPIO51_SEL_V << GPIOSD_ETM_TASK_GPIO51_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO51_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO51_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P13_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4)
+/** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO52_EN    (BIT(0))
+#define GPIOSD_ETM_TASK_GPIO52_EN_M  (GPIOSD_ETM_TASK_GPIO52_EN_V << GPIOSD_ETM_TASK_GPIO52_EN_S)
+#define GPIOSD_ETM_TASK_GPIO52_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO52_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO52_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO52_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO52_SEL_M  (GPIOSD_ETM_TASK_GPIO52_SEL_V << GPIOSD_ETM_TASK_GPIO52_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO52_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO52_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO53_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO53_EN    (BIT(8))
+#define GPIOSD_ETM_TASK_GPIO53_EN_M  (GPIOSD_ETM_TASK_GPIO53_EN_V << GPIOSD_ETM_TASK_GPIO53_EN_S)
+#define GPIOSD_ETM_TASK_GPIO53_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO53_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO53_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO53_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO53_SEL_M  (GPIOSD_ETM_TASK_GPIO53_SEL_V << GPIOSD_ETM_TASK_GPIO53_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO53_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO53_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO54_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIOSD_ETM_TASK_GPIO54_EN    (BIT(16))
+#define GPIOSD_ETM_TASK_GPIO54_EN_M  (GPIOSD_ETM_TASK_GPIO54_EN_V << GPIOSD_ETM_TASK_GPIO54_EN_S)
+#define GPIOSD_ETM_TASK_GPIO54_EN_V  0x00000001U
+#define GPIOSD_ETM_TASK_GPIO54_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO54_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIOSD_ETM_TASK_GPIO54_SEL    0x00000007U
+#define GPIOSD_ETM_TASK_GPIO54_SEL_M  (GPIOSD_ETM_TASK_GPIO54_SEL_V << GPIOSD_ETM_TASK_GPIO54_SEL_S)
+#define GPIOSD_ETM_TASK_GPIO54_SEL_V  0x00000007U
+#define GPIOSD_ETM_TASK_GPIO54_SEL_S  17
+
+/** GPIOSD_VERSION_REG register
+ *  Version Control Register
+ */
+#define GPIOSD_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc)
+/** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952;
+ *  Version control register.
+ */
+#define GPIOSD_GPIO_SD_DATE    0x0FFFFFFFU
+#define GPIOSD_GPIO_SD_DATE_M  (GPIOSD_GPIO_SD_DATE_V << GPIOSD_GPIO_SD_DATE_S)
+#define GPIOSD_GPIO_SD_DATE_V  0x0FFFFFFFU
+#define GPIOSD_GPIO_SD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/gpio_sd_struct.h b/components/soc/esp32p4/include/soc/gpio_sd_struct.h
new file mode 100644
index 0000000000..54e9030a97
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/gpio_sd_struct.h
@@ -0,0 +1,771 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SDM Configure Registers */
+/** Type of sigmadeltan register
+ *  Duty Cycle Configure Register of SDMn
+ */
+typedef union {
+    struct {
+        /** sd0_in : R/W; bitpos: [7:0]; default: 0;
+         *  This field is used to configure the duty cycle of sigma delta modulation output.
+         */
+        uint32_t sd0_in:8;
+        /** sd0_prescale : R/W; bitpos: [15:8]; default: 255;
+         *  This field is used to set a divider value to divide APB clock.
+         */
+        uint32_t sd0_prescale:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpiosd_sigmadeltan_reg_t;
+
+/** Type of sigmadelta_misc register
+ *  MISC Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** function_clk_en : R/W; bitpos: [30]; default: 0;
+         *  Clock enable bit of sigma delta modulation.
+         */
+        uint32_t function_clk_en:1;
+        /** spi_swap : R/W; bitpos: [31]; default: 0;
+         *  Reserved.
+         */
+        uint32_t spi_swap:1;
+    };
+    uint32_t val;
+} gpiosd_sigmadelta_misc_reg_t;
+
+
+/** Group: Glitch filter Configure Registers */
+/** Type of glitch_filter_chn register
+ *  Glitch Filter Configure Register of Channeln
+ */
+typedef union {
+    struct {
+        /** filter_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Glitch Filter channel enable bit.
+         */
+        uint32_t filter_ch0_en:1;
+        /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
+         *  Glitch Filter input io number.
+         */
+        uint32_t filter_ch0_input_io_num:6;
+        /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
+         *  Glitch Filter window threshold.
+         */
+        uint32_t filter_ch0_window_thres:6;
+        /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
+         *  Glitch Filter window width.
+         */
+        uint32_t filter_ch0_window_width:6;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} gpiosd_glitch_filter_chn_reg_t;
+
+
+/** Group: Etm Configure Registers */
+/** Type of etm_event_chn_cfg register
+ *  Etm Config register of Channeln
+ */
+typedef union {
+    struct {
+        /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
+         *  Etm event channel select gpio.
+         */
+        uint32_t etm_ch0_event_sel:6;
+        uint32_t reserved_6:1;
+        /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
+         *  Etm event send enable bit.
+         */
+        uint32_t etm_ch0_event_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpiosd_etm_event_chn_cfg_reg_t;
+
+/** Type of etm_task_p0_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio0_en:1;
+        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio0_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio1_en:1;
+        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio1_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio2_en:1;
+        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio2_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio3_en:1;
+        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio3_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p0_cfg_reg_t;
+
+/** Type of etm_task_p1_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio4_en:1;
+        /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio4_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio5_en:1;
+        /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio5_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio6_en:1;
+        /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio6_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio7_en:1;
+        /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio7_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p1_cfg_reg_t;
+
+/** Type of etm_task_p2_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio8_en:1;
+        /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio8_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio9_en:1;
+        /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio9_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio10_en:1;
+        /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio10_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio11_en:1;
+        /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio11_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p2_cfg_reg_t;
+
+/** Type of etm_task_p3_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio12_en:1;
+        /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio12_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio13_en:1;
+        /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio13_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio14_en:1;
+        /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio14_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio15_en:1;
+        /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio15_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p3_cfg_reg_t;
+
+/** Type of etm_task_p4_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio16_en:1;
+        /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio16_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio17_en:1;
+        /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio17_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio18_en:1;
+        /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio18_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio19_en:1;
+        /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio19_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p4_cfg_reg_t;
+
+/** Type of etm_task_p5_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio20_en:1;
+        /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio20_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio21_en:1;
+        /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio21_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio22_en:1;
+        /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio22_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio23_en:1;
+        /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio23_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p5_cfg_reg_t;
+
+/** Type of etm_task_p6_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio24_en:1;
+        /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio24_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio25_en:1;
+        /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio25_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio26_en:1;
+        /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio26_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio27_en:1;
+        /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio27_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p6_cfg_reg_t;
+
+/** Type of etm_task_p7_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio28_en:1;
+        /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio28_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio29_en:1;
+        /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio29_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio30_en:1;
+        /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio30_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio31_en:1;
+        /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio31_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p7_cfg_reg_t;
+
+/** Type of etm_task_p8_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio32_en:1;
+        /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio32_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio33_en:1;
+        /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio33_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio34_en:1;
+        /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio34_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio35_en:1;
+        /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio35_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p8_cfg_reg_t;
+
+/** Type of etm_task_p9_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio36_en:1;
+        /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio36_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio37_en:1;
+        /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio37_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio38_en:1;
+        /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio38_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio39_en:1;
+        /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio39_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p9_cfg_reg_t;
+
+/** Type of etm_task_p10_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio40_en:1;
+        /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio40_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio41_en:1;
+        /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio41_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio42_en:1;
+        /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio42_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio43_en:1;
+        /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio43_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p10_cfg_reg_t;
+
+/** Type of etm_task_p11_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio44_en:1;
+        /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio44_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio45_en:1;
+        /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio45_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio46_en:1;
+        /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio46_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio47_en:1;
+        /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio47_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p11_cfg_reg_t;
+
+/** Type of etm_task_p12_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio48_en:1;
+        /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio48_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio49_en:1;
+        /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio49_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio50_en:1;
+        /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio50_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio51_en:1;
+        /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio51_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p12_cfg_reg_t;
+
+/** Type of etm_task_p13_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio52_en:1;
+        /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio52_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio53_en:1;
+        /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio53_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio54_en:1;
+        /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio54_sel:3;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p13_cfg_reg_t;
+
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version Control Register
+ */
+typedef union {
+    struct {
+        /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
+         *  Version control register.
+         */
+        uint32_t gpio_sd_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_version_reg_t;
+
+
+typedef struct {
+    volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
+    uint32_t reserved_020;
+    volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
+    uint32_t reserved_028[2];
+    volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
+    uint32_t reserved_050[4];
+    volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_080[8];
+    volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
+    volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
+    volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
+    volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
+    volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
+    volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
+    volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
+    volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
+    volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
+    volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
+    volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
+    volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
+    volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
+    volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
+    uint32_t reserved_0d8[9];
+    volatile gpiosd_version_reg_t version;
+} gpiosd_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h
new file mode 100644
index 0000000000..92d76b0086
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h
@@ -0,0 +1,489 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_GPIO_SIG_MAP_H_
+#define _SOC_GPIO_SIG_MAP_H_
+
+#define SD_CARD_CCLK_2_PAD_OUT_IDX                         0
+#define SD_CARD_CCMD_2_PAD_IN_IDX                          1
+#define SD_CARD_CCMD_2_PAD_OUT_IDX                         1
+#define SD_CARD_CDATA0_2_PAD_IN_IDX                        2
+#define SD_CARD_CDATA0_2_PAD_OUT_IDX                       2
+#define SD_CARD_CDATA1_2_PAD_IN_IDX                        3
+#define SD_CARD_CDATA1_2_PAD_OUT_IDX                       3
+#define SD_CARD_CDATA2_2_PAD_IN_IDX                        4
+#define SD_CARD_CDATA2_2_PAD_OUT_IDX                       4
+#define SD_CARD_CDATA3_2_PAD_IN_IDX                        5
+#define SD_CARD_CDATA3_2_PAD_OUT_IDX                       5
+#define SD_CARD_CDATA4_2_PAD_IN_IDX                        6
+#define SD_CARD_CDATA4_2_PAD_OUT_IDX                       6
+#define SD_CARD_CDATA5_2_PAD_IN_IDX                        7
+#define SD_CARD_CDATA5_2_PAD_OUT_IDX                       7
+#define SD_CARD_CDATA6_2_PAD_IN_IDX                        8
+#define SD_CARD_CDATA6_2_PAD_OUT_IDX                       8
+#define SD_CARD_CDATA7_2_PAD_IN_IDX                        9
+#define SD_CARD_CDATA7_2_PAD_OUT_IDX                       9
+#define UART0_RXD_PAD_IN_IDX                               10
+#define UART0_TXD_PAD_OUT_IDX                              10
+#define UART0_CTS_PAD_IN_IDX                               11
+#define UART0_RTS_PAD_OUT_IDX                              11
+#define UART0_DSR_PAD_IN_IDX                               12
+#define UART0_DTR_PAD_OUT_IDX                              12
+#define UART1_RXD_PAD_IN_IDX                               13
+#define UART1_TXD_PAD_OUT_IDX                              13
+#define UART1_CTS_PAD_IN_IDX                               14
+#define UART1_RTS_PAD_OUT_IDX                              14
+#define UART1_DSR_PAD_IN_IDX                               15
+#define UART1_DTR_PAD_OUT_IDX                              15
+#define UART2_RXD_PAD_IN_IDX                               16
+#define UART2_TXD_PAD_OUT_IDX                              16
+#define UART2_CTS_PAD_IN_IDX                               17
+#define UART2_RTS_PAD_OUT_IDX                              17
+#define UART2_DSR_PAD_IN_IDX                               18
+#define UART2_DTR_PAD_OUT_IDX                              18
+#define UART3_RXD_PAD_IN_IDX                               19
+#define UART3_TXD_PAD_OUT_IDX                              19
+#define UART3_CTS_PAD_IN_IDX                               20
+#define UART3_RTS_PAD_OUT_IDX                              20
+#define UART3_DSR_PAD_IN_IDX                               21
+#define UART3_DTR_PAD_OUT_IDX                              21
+#define UART4_RXD_PAD_IN_IDX                               22
+#define UART4_TXD_PAD_OUT_IDX                              22
+#define UART4_CTS_PAD_IN_IDX                               23
+#define UART4_RTS_PAD_OUT_IDX                              23
+#define UART4_DSR_PAD_IN_IDX                               24
+#define UART4_DTR_PAD_OUT_IDX                              24
+#define I2S0_O_BCK_PAD_IN_IDX                              25
+#define I2S0_O_BCK_PAD_OUT_IDX                             25
+#define I2S0_MCLK_PAD_IN_IDX                               26
+#define I2S0_MCLK_PAD_OUT_IDX                              26
+#define I2S0_O_WS_PAD_IN_IDX                               27
+#define I2S0_O_WS_PAD_OUT_IDX                              27
+#define I2S0_I_SD_PAD_IN_IDX                               28
+#define I2S0_O_SD_PAD_OUT_IDX                              28
+#define I2S0_I_BCK_PAD_IN_IDX                              29
+#define I2S0_I_BCK_PAD_OUT_IDX                             29
+#define I2S0_I_WS_PAD_IN_IDX                               30
+#define I2S0_I_WS_PAD_OUT_IDX                              30
+#define I2S1_O_BCK_PAD_IN_IDX                              31
+#define I2S1_O_BCK_PAD_OUT_IDX                             31
+#define I2S1_MCLK_PAD_IN_IDX                               32
+#define I2S1_MCLK_PAD_OUT_IDX                              32
+#define I2S1_O_WS_PAD_IN_IDX                               33
+#define I2S1_O_WS_PAD_OUT_IDX                              33
+#define I2S1_I_SD_PAD_IN_IDX                               34
+#define I2S1_O_SD_PAD_OUT_IDX                              34
+#define I2S1_I_BCK_PAD_IN_IDX                              35
+#define I2S1_I_BCK_PAD_OUT_IDX                             35
+#define I2S1_I_WS_PAD_IN_IDX                               36
+#define I2S1_I_WS_PAD_OUT_IDX                              36
+#define I2S2_O_BCK_PAD_IN_IDX                              37
+#define I2S2_O_BCK_PAD_OUT_IDX                             37
+#define I2S2_MCLK_PAD_IN_IDX                               38
+#define I2S2_MCLK_PAD_OUT_IDX                              38
+#define I2S2_O_WS_PAD_IN_IDX                               39
+#define I2S2_O_WS_PAD_OUT_IDX                              39
+#define I2S2_I_SD_PAD_IN_IDX                               40
+#define I2S2_O_SD_PAD_OUT_IDX                              40
+#define I2S2_I_BCK_PAD_IN_IDX                              41
+#define I2S2_I_BCK_PAD_OUT_IDX                             41
+#define I2S2_I_WS_PAD_IN_IDX                               42
+#define I2S2_I_WS_PAD_OUT_IDX                              42
+#define I2S0_I_SD1_PAD_IN_IDX                              43
+#define I2S0_O_SD1_PAD_OUT_IDX                             43
+#define I2S0_I_SD2_PAD_IN_IDX                              44
+#define SPI2_DQS_PAD_OUT_IDX                               44
+#define I2S0_I_SD3_PAD_IN_IDX                              45
+#define SPI3_CS2_PAD_OUT_IDX                               45
+#define SPI3_CS1_PAD_OUT_IDX                               46
+#define SPI3_CK_PAD_IN_IDX                                 47
+#define SPI3_CK_PAD_OUT_IDX                                47
+#define SPI3_Q_PAD_IN_IDX                                  48
+#define SPI3_QO_PAD_OUT_IDX                                48
+#define SPI3_D_PAD_IN_IDX                                  49
+#define SPI3_D_PAD_OUT_IDX                                 49
+#define SPI3_HOLD_PAD_IN_IDX                               50
+#define SPI3_HOLD_PAD_OUT_IDX                              50
+#define SPI3_WP_PAD_IN_IDX                                 51
+#define SPI3_WP_PAD_OUT_IDX                                51
+#define SPI3_CS_PAD_IN_IDX                                 52
+#define SPI3_CS_PAD_OUT_IDX                                52
+#define SPI2_CK_PAD_IN_IDX                                 53
+#define SPI2_CK_PAD_OUT_IDX                                53
+#define SPI2_Q_PAD_IN_IDX                                  54
+#define SPI2_Q_PAD_OUT_IDX                                 54
+#define SPI2_D_PAD_IN_IDX                                  55
+#define SPI2_D_PAD_OUT_IDX                                 55
+#define SPI2_HOLD_PAD_IN_IDX                               56
+#define SPI2_HOLD_PAD_OUT_IDX                              56
+#define SPI2_WP_PAD_IN_IDX                                 57
+#define SPI2_WP_PAD_OUT_IDX                                57
+#define SPI2_IO4_PAD_IN_IDX                                58
+#define SPI2_IO4_PAD_OUT_IDX                               58
+#define SPI2_IO5_PAD_IN_IDX                                59
+#define SPI2_IO5_PAD_OUT_IDX                               59
+#define SPI2_IO6_PAD_IN_IDX                                60
+#define SPI2_IO6_PAD_OUT_IDX                               60
+#define SPI2_IO7_PAD_IN_IDX                                61
+#define SPI2_IO7_PAD_OUT_IDX                               61
+#define SPI2_CS_PAD_IN_IDX                                 62
+#define SPI2_CS_PAD_OUT_IDX                                62
+#define PCNT_RST_PAD_IN0_IDX                               63
+#define SPI2_CS1_PAD_OUT_IDX                               63
+#define PCNT_RST_PAD_IN1_IDX                               64
+#define SPI2_CS2_PAD_OUT_IDX                               64
+#define PCNT_RST_PAD_IN2_IDX                               65
+#define SPI2_CS3_PAD_OUT_IDX                               65
+#define PCNT_RST_PAD_IN3_IDX                               66
+#define SPI2_CS4_PAD_OUT_IDX                               66
+#define SPI2_CS5_PAD_OUT_IDX                               67
+#define I2C0_SCL_PAD_IN_IDX                                68
+#define I2C0_SCL_PAD_OUT_IDX                               68
+#define I2C0_SDA_PAD_IN_IDX                                69
+#define I2C0_SDA_PAD_OUT_IDX                               69
+#define I2C1_SCL_PAD_IN_IDX                                70
+#define I2C1_SCL_PAD_OUT_IDX                               70
+#define I2C1_SDA_PAD_IN_IDX                                71
+#define I2C1_SDA_PAD_OUT_IDX                               71
+#define GPIO_SD0_OUT_IDX                                   72
+#define GPIO_SD1_OUT_IDX                                   73
+#define UART0_SLP_CLK_PAD_IN_IDX                           74
+#define GPIO_SD2_OUT_IDX                                   74
+#define UART1_SLP_CLK_PAD_IN_IDX                           75
+#define GPIO_SD3_OUT_IDX                                   75
+#define UART2_SLP_CLK_PAD_IN_IDX                           76
+#define GPIO_SD4_OUT_IDX                                   76
+#define UART3_SLP_CLK_PAD_IN_IDX                           77
+#define GPIO_SD5_OUT_IDX                                   77
+#define UART4_SLP_CLK_PAD_IN_IDX                           78
+#define GPIO_SD6_OUT_IDX                                   78
+#define GPIO_SD7_OUT_IDX                                   79
+#define CAN0_RX_PAD_IN_IDX                                 80
+#define CAN0_TX_PAD_OUT_IDX                                80
+#define CAN0_BUS_OFF_ON_PAD_OUT_IDX                        81
+#define CAN0_CLKOUT_PAD_OUT_IDX                            82
+#define CAN1_RX_PAD_IN_IDX                                 83
+#define CAN1_TX_PAD_OUT_IDX                                83
+#define CAN1_BUS_OFF_ON_PAD_OUT_IDX                        84
+#define CAN1_CLKOUT_PAD_OUT_IDX                            85
+#define CAN2_RX_PAD_IN_IDX                                 86
+#define CAN2_TX_PAD_OUT_IDX                                86
+#define CAN2_BUS_OFF_ON_PAD_OUT_IDX                        87
+#define CAN2_CLKOUT_PAD_OUT_IDX                            88
+#define PWM0_SYNC0_PAD_IN_IDX                              89
+#define PWM0_CH0_A_PAD_OUT_IDX                             89
+#define PWM0_SYNC1_PAD_IN_IDX                              90
+#define PWM0_CH0_B_PAD_OUT_IDX                             90
+#define PWM0_SYNC2_PAD_IN_IDX                              91
+#define PWM0_CH1_A_PAD_OUT_IDX                             91
+#define PWM0_F0_PAD_IN_IDX                                 92
+#define PWM0_CH1_B_PAD_OUT_IDX                             92
+#define PWM0_F1_PAD_IN_IDX                                 93
+#define PWM0_CH2_A_PAD_OUT_IDX                             93
+#define PWM0_F2_PAD_IN_IDX                                 94
+#define PWM0_CH2_B_PAD_OUT_IDX                             94
+#define PWM0_CAP0_PAD_IN_IDX                               95
+#define PWM1_CH0_A_PAD_OUT_IDX                             95
+#define PWM0_CAP1_PAD_IN_IDX                               96
+#define PWM1_CH0_B_PAD_OUT_IDX                             96
+#define PWM0_CAP2_PAD_IN_IDX                               97
+#define PWM1_CH1_A_PAD_OUT_IDX                             97
+#define PWM1_SYNC0_PAD_IN_IDX                              98
+#define PWM1_CH1_B_PAD_OUT_IDX                             98
+#define PWM1_SYNC1_PAD_IN_IDX                              99
+#define PWM1_CH2_A_PAD_OUT_IDX                             99
+#define PWM1_SYNC2_PAD_IN_IDX                              100
+#define PWM1_CH2_B_PAD_OUT_IDX                             100
+#define PWM1_F0_PAD_IN_IDX                                 101
+#define ADP_CHRG_PAD_OUT_IDX                               101
+#define PWM1_F1_PAD_IN_IDX                                 102
+#define ADP_DISCHRG_PAD_OUT_IDX                            102
+#define PWM1_F2_PAD_IN_IDX                                 103
+#define ADP_PRB_EN_PAD_OUT_IDX                             103
+#define PWM1_CAP0_PAD_IN_IDX                               104
+#define ADP_SNS_EN_PAD_OUT_IDX                             104
+#define PWM1_CAP1_PAD_IN_IDX                               105
+#define TWAI0_STANDBY_PAD_OUT_IDX                          105
+#define PWM1_CAP2_PAD_IN_IDX                               106
+#define TWAI1_STANDBY_PAD_OUT_IDX                          106
+#define GMII_MDI_PAD_IN_IDX                                107
+#define TWAI2_STANDBY_PAD_OUT_IDX                          107
+#define GMAC_PHY_COL_PAD_IN_IDX                            108
+#define GMII_MDC_PAD_OUT_IDX                               108
+#define GMAC_PHY_CRS_PAD_IN_IDX                            109
+#define GMII_MDO_PAD_OUT_IDX                               109
+#define USB_OTG11_IDDIG_PAD_IN_IDX                         110
+#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX                    110
+#define USB_OTG11_AVALID_PAD_IN_IDX                        111
+#define USB_OTG11_IDPULLUP_PAD_OUT_IDX                     111
+#define USB_SRP_BVALID_PAD_IN_IDX                          112
+#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX                   112
+#define USB_OTG11_VBUSVALID_PAD_IN_IDX                     113
+#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX                   113
+#define USB_SRP_SESSEND_PAD_IN_IDX                         114
+#define USB_OTG11_DRVVBUS_PAD_OUT_IDX                      114
+#define USB_SRP_CHRGVBUS_PAD_OUT_IDX                       115
+#define OTG_DRVVBUS_PAD_OUT_IDX                            116
+#define ULPI_CLK_PAD_IN_IDX                                117
+#define RNG_CHAIN_CLK_PAD_OUT_IDX                          117
+#define USB_HSPHY_REFCLK_IN_IDX                            118
+#define HP_PROBE_TOP_OUT0_IDX                              118
+#define HP_PROBE_TOP_OUT1_IDX                              119
+#define HP_PROBE_TOP_OUT2_IDX                              120
+#define HP_PROBE_TOP_OUT3_IDX                              121
+#define HP_PROBE_TOP_OUT4_IDX                              122
+#define HP_PROBE_TOP_OUT5_IDX                              123
+#define HP_PROBE_TOP_OUT6_IDX                              124
+#define HP_PROBE_TOP_OUT7_IDX                              125
+#define SD_CARD_DETECT_N_1_PAD_IN_IDX                      126
+#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX                       126
+#define SD_CARD_DETECT_N_2_PAD_IN_IDX                      127
+#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX                       127
+#define SD_CARD_INT_N_1_PAD_IN_IDX                         128
+#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX                       128
+#define SD_CARD_INT_N_2_PAD_IN_IDX                         129
+#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX                       129
+#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX                     130
+#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX                       130
+#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX                     131
+#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX                       131
+#define SD_DATA_STROBE_1_PAD_IN_IDX                        132
+#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX                       132
+#define SD_DATA_STROBE_2_PAD_IN_IDX                        133
+#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX                       133
+#define I3C_MST_SCL_PAD_IN_IDX                             134
+#define I3C_MST_SCL_PAD_OUT_IDX                            134
+#define I3C_MST_SDA_PAD_IN_IDX                             135
+#define I3C_MST_SDA_PAD_OUT_IDX                            135
+#define I3C_SLV_SCL_PAD_IN_IDX                             136
+#define I3C_SLV_SCL_PAD_OUT_IDX                            136
+#define I3C_SLV_SDA_PAD_IN_IDX                             137
+#define I3C_SLV_SDA_PAD_OUT_IDX                            137
+#define ADP_PRB_PAD_IN_IDX                                 138
+#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX                  138
+#define ADP_SNS_PAD_IN_IDX                                 139
+#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX                  139
+#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX                     140
+#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX                    140
+#define PCNT_SIG_CH0_PAD_IN0_IDX                           141
+#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX                    141
+#define PCNT_SIG_CH0_PAD_IN1_IDX                           142
+#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX                    142
+#define PCNT_SIG_CH0_PAD_IN2_IDX                           143
+#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX                   143
+#define PCNT_SIG_CH0_PAD_IN3_IDX                           144
+#define LCD_CS_PAD_OUT_IDX                                 144
+#define PCNT_SIG_CH1_PAD_IN0_IDX                           145
+#define LCD_DC_PAD_OUT_IDX                                 145
+#define PCNT_SIG_CH1_PAD_IN1_IDX                           146
+#define SD_RST_N_1_PAD_OUT_IDX                             146
+#define PCNT_SIG_CH1_PAD_IN2_IDX                           147
+#define SD_RST_N_2_PAD_OUT_IDX                             147
+#define PCNT_SIG_CH1_PAD_IN3_IDX                           148
+#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX                 148
+#define PCNT_CTRL_CH0_PAD_IN0_IDX                          149
+#define LCD_PCLK_PAD_OUT_IDX                               149
+#define PCNT_CTRL_CH0_PAD_IN1_IDX                          150
+#define CAM_CLK_PAD_OUT_IDX                                150
+#define PCNT_CTRL_CH0_PAD_IN2_IDX                          151
+#define LCD_H_ENABLE_PAD_OUT_IDX                           151
+#define PCNT_CTRL_CH0_PAD_IN3_IDX                          152
+#define LCD_H_SYNC_PAD_OUT_IDX                             152
+#define PCNT_CTRL_CH1_PAD_IN0_IDX                          153
+#define LCD_V_SYNC_PAD_OUT_IDX                             153
+#define PCNT_CTRL_CH1_PAD_IN1_IDX                          154
+#define LCD_DATA_OUT_PAD_OUT0_IDX                          154
+#define PCNT_CTRL_CH1_PAD_IN2_IDX                          155
+#define LCD_DATA_OUT_PAD_OUT1_IDX                          155
+#define PCNT_CTRL_CH1_PAD_IN3_IDX                          156
+#define LCD_DATA_OUT_PAD_OUT2_IDX                          156
+#define LCD_DATA_OUT_PAD_OUT3_IDX                          157
+#define CAM_PCLK_PAD_IN_IDX                                158
+#define LCD_DATA_OUT_PAD_OUT4_IDX                          158
+#define CAM_H_ENABLE_PAD_IN_IDX                            159
+#define LCD_DATA_OUT_PAD_OUT5_IDX                          159
+#define CAM_H_SYNC_PAD_IN_IDX                              160
+#define LCD_DATA_OUT_PAD_OUT6_IDX                          160
+#define CAM_V_SYNC_PAD_IN_IDX                              161
+#define LCD_DATA_OUT_PAD_OUT7_IDX                          161
+#define CAM_DATA_IN_PAD_IN0_IDX                            162
+#define LCD_DATA_OUT_PAD_OUT8_IDX                          162
+#define CAM_DATA_IN_PAD_IN1_IDX                            163
+#define LCD_DATA_OUT_PAD_OUT9_IDX                          163
+#define CAM_DATA_IN_PAD_IN2_IDX                            164
+#define LCD_DATA_OUT_PAD_OUT10_IDX                         164
+#define CAM_DATA_IN_PAD_IN3_IDX                            165
+#define LCD_DATA_OUT_PAD_OUT11_IDX                         165
+#define CAM_DATA_IN_PAD_IN4_IDX                            166
+#define LCD_DATA_OUT_PAD_OUT12_IDX                         166
+#define CAM_DATA_IN_PAD_IN5_IDX                            167
+#define LCD_DATA_OUT_PAD_OUT13_IDX                         167
+#define CAM_DATA_IN_PAD_IN6_IDX                            168
+#define LCD_DATA_OUT_PAD_OUT14_IDX                         168
+#define CAM_DATA_IN_PAD_IN7_IDX                            169
+#define LCD_DATA_OUT_PAD_OUT15_IDX                         169
+#define CAM_DATA_IN_PAD_IN8_IDX                            170
+#define LCD_DATA_OUT_PAD_OUT16_IDX                         170
+#define CAM_DATA_IN_PAD_IN9_IDX                            171
+#define LCD_DATA_OUT_PAD_OUT17_IDX                         171
+#define CAM_DATA_IN_PAD_IN10_IDX                           172
+#define LCD_DATA_OUT_PAD_OUT18_IDX                         172
+#define CAM_DATA_IN_PAD_IN11_IDX                           173
+#define LCD_DATA_OUT_PAD_OUT19_IDX                         173
+#define CAM_DATA_IN_PAD_IN12_IDX                           174
+#define LCD_DATA_OUT_PAD_OUT20_IDX                         174
+#define CAM_DATA_IN_PAD_IN13_IDX                           175
+#define LCD_DATA_OUT_PAD_OUT21_IDX                         175
+#define CAM_DATA_IN_PAD_IN14_IDX                           176
+#define LCD_DATA_OUT_PAD_OUT22_IDX                         176
+#define CAM_DATA_IN_PAD_IN15_IDX                           177
+#define LCD_DATA_OUT_PAD_OUT23_IDX                         177
+#define GMAC_PHY_RXDV_PAD_IN_IDX                           178
+#define GMAC_PHY_TXEN_PAD_OUT_IDX                          178
+#define GMAC_PHY_RXD0_PAD_IN_IDX                           179
+#define GMAC_PHY_TXD0_PAD_OUT_IDX                          179
+#define GMAC_PHY_RXD1_PAD_IN_IDX                           180
+#define GMAC_PHY_TXD1_PAD_OUT_IDX                          180
+#define GMAC_PHY_RXD2_PAD_IN_IDX                           181
+#define GMAC_PHY_TXD2_PAD_OUT_IDX                          181
+#define GMAC_PHY_RXD3_PAD_IN_IDX                           182
+#define GMAC_PHY_TXD3_PAD_OUT_IDX                          182
+#define GMAC_PHY_RXER_PAD_IN_IDX                           183
+#define GMAC_PHY_TXER_PAD_OUT_IDX                          183
+#define GMAC_RX_CLK_PAD_IN_IDX                             184
+#define DBG_CH0_CLK_IDX                                    184
+#define GMAC_TX_CLK_PAD_IN_IDX                             185
+#define DBG_CH1_CLK_IDX                                    185
+#define PARLIO_RX_CLK_PAD_IN_IDX                           186
+#define PARLIO_RX_CLK_PAD_OUT_IDX                          186
+#define PARLIO_TX_CLK_PAD_IN_IDX                           187
+#define PARLIO_TX_CLK_PAD_OUT_IDX                          187
+#define PARLIO_RX_DATA0_PAD_IN_IDX                         188
+#define PARLIO_TX_DATA0_PAD_OUT_IDX                        188
+#define PARLIO_RX_DATA1_PAD_IN_IDX                         189
+#define PARLIO_TX_DATA1_PAD_OUT_IDX                        189
+#define PARLIO_RX_DATA2_PAD_IN_IDX                         190
+#define PARLIO_TX_DATA2_PAD_OUT_IDX                        190
+#define PARLIO_RX_DATA3_PAD_IN_IDX                         191
+#define PARLIO_TX_DATA3_PAD_OUT_IDX                        191
+#define PARLIO_RX_DATA4_PAD_IN_IDX                         192
+#define PARLIO_TX_DATA4_PAD_OUT_IDX                        192
+#define PARLIO_RX_DATA5_PAD_IN_IDX                         193
+#define PARLIO_TX_DATA5_PAD_OUT_IDX                        193
+#define PARLIO_RX_DATA6_PAD_IN_IDX                         194
+#define PARLIO_TX_DATA6_PAD_OUT_IDX                        194
+#define PARLIO_RX_DATA7_PAD_IN_IDX                         195
+#define PARLIO_TX_DATA7_PAD_OUT_IDX                        195
+#define PARLIO_RX_DATA8_PAD_IN_IDX                         196
+#define PARLIO_TX_DATA8_PAD_OUT_IDX                        196
+#define PARLIO_RX_DATA9_PAD_IN_IDX                         197
+#define PARLIO_TX_DATA9_PAD_OUT_IDX                        197
+#define PARLIO_RX_DATA10_PAD_IN_IDX                        198
+#define PARLIO_TX_DATA10_PAD_OUT_IDX                       198
+#define PARLIO_RX_DATA11_PAD_IN_IDX                        199
+#define PARLIO_TX_DATA11_PAD_OUT_IDX                       199
+#define PARLIO_RX_DATA12_PAD_IN_IDX                        200
+#define PARLIO_TX_DATA12_PAD_OUT_IDX                       200
+#define PARLIO_RX_DATA13_PAD_IN_IDX                        201
+#define PARLIO_TX_DATA13_PAD_OUT_IDX                       201
+#define PARLIO_RX_DATA14_PAD_IN_IDX                        202
+#define PARLIO_TX_DATA14_PAD_OUT_IDX                       202
+#define PARLIO_RX_DATA15_PAD_IN_IDX                        203
+#define PARLIO_TX_DATA15_PAD_OUT_IDX                       203
+#define HP_PROBE_TOP_OUT8_IDX                              204
+#define HP_PROBE_TOP_OUT9_IDX                              205
+#define HP_PROBE_TOP_OUT10_IDX                             206
+#define HP_PROBE_TOP_OUT11_IDX                             207
+#define HP_PROBE_TOP_OUT12_IDX                             208
+#define HP_PROBE_TOP_OUT13_IDX                             209
+#define HP_PROBE_TOP_OUT14_IDX                             210
+#define HP_PROBE_TOP_OUT15_IDX                             211
+#define CONSTANT0_PAD_OUT_IDX                              212
+#define CONSTANT1_PAD_OUT_IDX                              213
+#define CORE_GPIO_IN_PAD_IN0_IDX                           214
+#define CORE_GPIO_OUT_PAD_OUT0_IDX                         214
+#define CORE_GPIO_IN_PAD_IN1_IDX                           215
+#define CORE_GPIO_OUT_PAD_OUT1_IDX                         215
+#define CORE_GPIO_IN_PAD_IN2_IDX                           216
+#define CORE_GPIO_OUT_PAD_OUT2_IDX                         216
+#define CORE_GPIO_IN_PAD_IN3_IDX                           217
+#define CORE_GPIO_OUT_PAD_OUT3_IDX                         217
+#define CORE_GPIO_IN_PAD_IN4_IDX                           218
+#define CORE_GPIO_OUT_PAD_OUT4_IDX                         218
+#define CORE_GPIO_IN_PAD_IN5_IDX                           219
+#define CORE_GPIO_OUT_PAD_OUT5_IDX                         219
+#define CORE_GPIO_IN_PAD_IN6_IDX                           220
+#define CORE_GPIO_OUT_PAD_OUT6_IDX                         220
+#define CORE_GPIO_IN_PAD_IN7_IDX                           221
+#define CORE_GPIO_OUT_PAD_OUT7_IDX                         221
+#define CORE_GPIO_IN_PAD_IN8_IDX                           222
+#define CORE_GPIO_OUT_PAD_OUT8_IDX                         222
+#define CORE_GPIO_IN_PAD_IN9_IDX                           223
+#define CORE_GPIO_OUT_PAD_OUT9_IDX                         223
+#define CORE_GPIO_IN_PAD_IN10_IDX                          224
+#define CORE_GPIO_OUT_PAD_OUT10_IDX                        224
+#define CORE_GPIO_IN_PAD_IN11_IDX                          225
+#define CORE_GPIO_OUT_PAD_OUT11_IDX                        225
+#define CORE_GPIO_IN_PAD_IN12_IDX                          226
+#define CORE_GPIO_OUT_PAD_OUT12_IDX                        226
+#define CORE_GPIO_IN_PAD_IN13_IDX                          227
+#define CORE_GPIO_OUT_PAD_OUT13_IDX                        227
+#define CORE_GPIO_IN_PAD_IN14_IDX                          228
+#define CORE_GPIO_OUT_PAD_OUT14_IDX                        228
+#define CORE_GPIO_IN_PAD_IN15_IDX                          229
+#define CORE_GPIO_OUT_PAD_OUT15_IDX                        229
+#define CORE_GPIO_IN_PAD_IN16_IDX                          230
+#define CORE_GPIO_OUT_PAD_OUT16_IDX                        230
+#define CORE_GPIO_IN_PAD_IN17_IDX                          231
+#define CORE_GPIO_OUT_PAD_OUT17_IDX                        231
+#define CORE_GPIO_IN_PAD_IN18_IDX                          232
+#define CORE_GPIO_OUT_PAD_OUT18_IDX                        232
+#define CORE_GPIO_IN_PAD_IN19_IDX                          233
+#define CORE_GPIO_OUT_PAD_OUT19_IDX                        233
+#define CORE_GPIO_IN_PAD_IN20_IDX                          234
+#define CORE_GPIO_OUT_PAD_OUT20_IDX                        234
+#define CORE_GPIO_IN_PAD_IN21_IDX                          235
+#define CORE_GPIO_OUT_PAD_OUT21_IDX                        235
+#define CORE_GPIO_IN_PAD_IN22_IDX                          236
+#define CORE_GPIO_OUT_PAD_OUT22_IDX                        236
+#define CORE_GPIO_IN_PAD_IN23_IDX                          237
+#define CORE_GPIO_OUT_PAD_OUT23_IDX                        237
+#define CORE_GPIO_IN_PAD_IN24_IDX                          238
+#define CORE_GPIO_OUT_PAD_OUT24_IDX                        238
+#define CORE_GPIO_IN_PAD_IN25_IDX                          239
+#define CORE_GPIO_OUT_PAD_OUT25_IDX                        239
+#define CORE_GPIO_IN_PAD_IN26_IDX                          240
+#define CORE_GPIO_OUT_PAD_OUT26_IDX                        240
+#define CORE_GPIO_IN_PAD_IN27_IDX                          241
+#define CORE_GPIO_OUT_PAD_OUT27_IDX                        241
+#define CORE_GPIO_IN_PAD_IN28_IDX                          242
+#define CORE_GPIO_OUT_PAD_OUT28_IDX                        242
+#define CORE_GPIO_IN_PAD_IN29_IDX                          243
+#define CORE_GPIO_OUT_PAD_OUT29_IDX                        243
+#define CORE_GPIO_IN_PAD_IN30_IDX                          244
+#define CORE_GPIO_OUT_PAD_OUT30_IDX                        244
+#define CORE_GPIO_IN_PAD_IN31_IDX                          245
+#define CORE_GPIO_OUT_PAD_OUT31_IDX                        245
+#define RMT_SIG_PAD_IN0_IDX                                246
+#define RMT_SIG_PAD_OUT0_IDX                               246
+#define RMT_SIG_PAD_IN1_IDX                                247
+#define RMT_SIG_PAD_OUT1_IDX                               247
+#define RMT_SIG_PAD_IN2_IDX                                248
+#define RMT_SIG_PAD_OUT2_IDX                               248
+#define RMT_SIG_PAD_IN3_IDX                                249
+#define RMT_SIG_PAD_OUT3_IDX                               249
+#define SIG_IN_FUNC250_IDX                                 250
+#define SIG_IN_FUNC250_IDX                                 250
+#define SIG_IN_FUNC251_IDX                                 251
+#define SIG_IN_FUNC251_IDX                                 251
+#define SIG_IN_FUNC252_IDX                                 252
+#define SIG_IN_FUNC252_IDX                                 252
+#define SIG_IN_FUNC253_IDX                                 253
+#define SIG_IN_FUNC253_IDX                                 253
+#define SIG_IN_FUNC254_IDX                                 254
+#define SIG_IN_FUNC254_IDX                                 254
+#define SIG_IN_FUNC255_IDX                                 255
+#define SIG_IN_FUNC255_IDX                                 255
+#endif  /* _SOC_GPIO_SIG_MAP_H_ */
diff --git a/components/soc/esp32p4/include/soc/hardware_lock_reg.h b/components/soc/esp32p4/include/soc/hardware_lock_reg.h
new file mode 100644
index 0000000000..87faa416d5
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hardware_lock_reg.h
@@ -0,0 +1,76 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ATOMIC_ADDR_LOCK_REG register
+ *  hardware lock regsiter
+ */
+#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
+/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
+ *  read to acquire hardware lock, write to release hardware lock
+ */
+#define ATOMIC_LOCK    0x00000003U
+#define ATOMIC_LOCK_M  (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
+#define ATOMIC_LOCK_V  0x00000003U
+#define ATOMIC_LOCK_S  0
+
+/** ATOMIC_LR_ADDR_REG register
+ *  gloable lr address regsiter
+ */
+#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
+/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  backup gloable address
+ */
+#define ATOMIC_GLOABLE_LR_ADDR    0xFFFFFFFFU
+#define ATOMIC_GLOABLE_LR_ADDR_M  (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
+#define ATOMIC_GLOABLE_LR_ADDR_V  0xFFFFFFFFU
+#define ATOMIC_GLOABLE_LR_ADDR_S  0
+
+/** ATOMIC_LR_VALUE_REG register
+ *  gloable lr value regsiter
+ */
+#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
+/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  backup gloable value
+ */
+#define ATOMIC_GLOABLE_LR_VALUE    0xFFFFFFFFU
+#define ATOMIC_GLOABLE_LR_VALUE_M  (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
+#define ATOMIC_GLOABLE_LR_VALUE_V  0xFFFFFFFFU
+#define ATOMIC_GLOABLE_LR_VALUE_S  0
+
+/** ATOMIC_LOCK_STATUS_REG register
+ *  lock status regsiter
+ */
+#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
+/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  read hareware lock status for debug
+ */
+#define ATOMIC_LOCK_STATUS    0x00000003U
+#define ATOMIC_LOCK_STATUS_M  (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
+#define ATOMIC_LOCK_STATUS_V  0x00000003U
+#define ATOMIC_LOCK_STATUS_S  0
+
+/** ATOMIC_COUNTER_REG register
+ *  wait counter register
+ */
+#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
+/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
+ *  delay counter
+ */
+#define ATOMIC_WAIT_COUNTER    0x0000FFFFU
+#define ATOMIC_WAIT_COUNTER_M  (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
+#define ATOMIC_WAIT_COUNTER_V  0x0000FFFFU
+#define ATOMIC_WAIT_COUNTER_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/hardware_lock_struct.h b/components/soc/esp32p4/include/soc/hardware_lock_struct.h
new file mode 100644
index 0000000000..4f5f43663c
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hardware_lock_struct.h
@@ -0,0 +1,99 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration registers */
+/** Type of addr_lock register
+ *  hardware lock regsiter
+ */
+typedef union {
+    struct {
+        /** lock : R/W; bitpos: [1:0]; default: 0;
+         *  read to acquire hardware lock, write to release hardware lock
+         */
+        uint32_t lock:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} atomic_addr_lock_reg_t;
+
+/** Type of lr_addr register
+ *  gloable lr address regsiter
+ */
+typedef union {
+    struct {
+        /** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0;
+         *  backup gloable address
+         */
+        uint32_t gloable_lr_addr:32;
+    };
+    uint32_t val;
+} atomic_lr_addr_reg_t;
+
+/** Type of lr_value register
+ *  gloable lr value regsiter
+ */
+typedef union {
+    struct {
+        /** gloable_lr_value : R/W; bitpos: [31:0]; default: 0;
+         *  backup gloable value
+         */
+        uint32_t gloable_lr_value:32;
+    };
+    uint32_t val;
+} atomic_lr_value_reg_t;
+
+/** Type of lock_status register
+ *  lock status regsiter
+ */
+typedef union {
+    struct {
+        /** lock_status : RO; bitpos: [1:0]; default: 0;
+         *  read hareware lock status for debug
+         */
+        uint32_t lock_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} atomic_lock_status_reg_t;
+
+/** Type of counter register
+ *  wait counter register
+ */
+typedef union {
+    struct {
+        /** wait_counter : R/W; bitpos: [15:0]; default: 0;
+         *  delay counter
+         */
+        uint32_t wait_counter:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} atomic_counter_reg_t;
+
+
+typedef struct atomic_dev_t {
+    volatile atomic_addr_lock_reg_t addr_lock;
+    volatile atomic_lr_addr_reg_t lr_addr;
+    volatile atomic_lr_value_reg_t lr_value;
+    volatile atomic_lock_status_reg_t lock_status;
+    volatile atomic_counter_reg_t counter;
+} atomic_dev_t;
+
+extern atomic_dev_t ATOMIC_LOCKER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/hinf_reg.h b/components/soc/esp32p4/include/soc/hinf_reg.h
new file mode 100644
index 0000000000..a5184fc97a
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hinf_reg.h
@@ -0,0 +1,647 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HINF_CFG_DATA0_REG register
+ *  Configure sdio cis content
+ */
+#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
+/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
+ *  configure device id of function1 in cis
+ */
+#define HINF_DEVICE_ID_FN1    0x0000FFFFU
+#define HINF_DEVICE_ID_FN1_M  (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
+#define HINF_DEVICE_ID_FN1_V  0x0000FFFFU
+#define HINF_DEVICE_ID_FN1_S  0
+/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
+ *  configure user id of function1 in cis
+ */
+#define HINF_USER_ID_FN1    0x0000FFFFU
+#define HINF_USER_ID_FN1_M  (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
+#define HINF_USER_ID_FN1_V  0x0000FFFFU
+#define HINF_USER_ID_FN1_S  16
+
+/** HINF_CFG_DATA1_REG register
+ *  SDIO configuration register
+ */
+#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
+/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
+ *  Sdio clock enable
+ */
+#define HINF_SDIO_ENABLE    (BIT(0))
+#define HINF_SDIO_ENABLE_M  (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
+#define HINF_SDIO_ENABLE_V  0x00000001U
+#define HINF_SDIO_ENABLE_S  0
+/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
+ *  sdio function1 io ready signal in cis
+ */
+#define HINF_SDIO_IOREADY1    (BIT(1))
+#define HINF_SDIO_IOREADY1_M  (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
+#define HINF_SDIO_IOREADY1_V  0x00000001U
+#define HINF_SDIO_IOREADY1_S  1
+/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
+ *  Highspeed enable in cccr
+ */
+#define HINF_HIGHSPEED_ENABLE    (BIT(2))
+#define HINF_HIGHSPEED_ENABLE_M  (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
+#define HINF_HIGHSPEED_ENABLE_V  0x00000001U
+#define HINF_HIGHSPEED_ENABLE_S  2
+/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
+ *  highspeed mode status in cccr
+ */
+#define HINF_HIGHSPEED_MODE    (BIT(3))
+#define HINF_HIGHSPEED_MODE_M  (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
+#define HINF_HIGHSPEED_MODE_V  0x00000001U
+#define HINF_HIGHSPEED_MODE_S  3
+/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
+ *  sdio card detect enable
+ */
+#define HINF_SDIO_CD_ENABLE    (BIT(4))
+#define HINF_SDIO_CD_ENABLE_M  (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
+#define HINF_SDIO_CD_ENABLE_V  0x00000001U
+#define HINF_SDIO_CD_ENABLE_S  4
+/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
+ *  sdio function1 io ready signal in cis
+ */
+#define HINF_SDIO_IOREADY2    (BIT(5))
+#define HINF_SDIO_IOREADY2_M  (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
+#define HINF_SDIO_IOREADY2_V  0x00000001U
+#define HINF_SDIO_IOREADY2_S  5
+/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
+ *  mask sdio interrupt in cccr, high active
+ */
+#define HINF_SDIO_INT_MASK    (BIT(6))
+#define HINF_SDIO_INT_MASK_M  (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
+#define HINF_SDIO_INT_MASK_V  0x00000001U
+#define HINF_SDIO_INT_MASK_S  6
+/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
+ *  ioe2 status in cccr
+ */
+#define HINF_IOENABLE2    (BIT(7))
+#define HINF_IOENABLE2_M  (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
+#define HINF_IOENABLE2_V  0x00000001U
+#define HINF_IOENABLE2_S  7
+/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
+ *  card disable status in cccr
+ */
+#define HINF_CD_DISABLE    (BIT(8))
+#define HINF_CD_DISABLE_M  (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
+#define HINF_CD_DISABLE_V  0x00000001U
+#define HINF_CD_DISABLE_S  8
+/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
+ *  function1 eps status in fbr
+ */
+#define HINF_FUNC1_EPS    (BIT(9))
+#define HINF_FUNC1_EPS_M  (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
+#define HINF_FUNC1_EPS_V  0x00000001U
+#define HINF_FUNC1_EPS_S  9
+/** HINF_EMP : RO; bitpos: [10]; default: 0;
+ *  empc status in cccr
+ */
+#define HINF_EMP    (BIT(10))
+#define HINF_EMP_M  (HINF_EMP_V << HINF_EMP_S)
+#define HINF_EMP_V  0x00000001U
+#define HINF_EMP_S  10
+/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
+ *  ioe1 status in cccr
+ */
+#define HINF_IOENABLE1    (BIT(11))
+#define HINF_IOENABLE1_M  (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
+#define HINF_IOENABLE1_V  0x00000001U
+#define HINF_IOENABLE1_S  11
+/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
+ *  sdio version in cccr
+ */
+#define HINF_SDIO_VER    0x00000FFFU
+#define HINF_SDIO_VER_M  (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
+#define HINF_SDIO_VER_V  0x00000FFFU
+#define HINF_SDIO_VER_S  12
+/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
+ *  function2 eps status in fbr
+ */
+#define HINF_FUNC2_EPS    (BIT(24))
+#define HINF_FUNC2_EPS_M  (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
+#define HINF_FUNC2_EPS_V  0x00000001U
+#define HINF_FUNC2_EPS_S  24
+/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
+ *  [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
+ *  in delayed cycles control,0:no delay, 1:delay 1 cycle.
+ *  [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
+ *  mode.
+ *  [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
+ *  [12]=0,posedge when highspeed mode enable.
+ *  [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
+ *  [28]: sdio data pad pull up enable
+ */
+#define HINF_SDIO20_CONF    0x0000007FU
+#define HINF_SDIO20_CONF_M  (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
+#define HINF_SDIO20_CONF_V  0x0000007FU
+#define HINF_SDIO20_CONF_S  25
+
+/** HINF_CFG_TIMING_REG register
+ *  Timing configuration registers
+ */
+#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
+/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
+ *  configure Ncrc parameter in sdr50/104 mode, no more than 6.
+ */
+#define HINF_NCRC    0x00000007U
+#define HINF_NCRC_M  (HINF_NCRC_V << HINF_NCRC_S)
+#define HINF_NCRC_V  0x00000007U
+#define HINF_NCRC_S  0
+/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
+ *  configure cycles to lower cmd after voltage is changed to 1.8V.
+ */
+#define HINF_PST_END_CMD_LOW_VALUE    0x0000007FU
+#define HINF_PST_END_CMD_LOW_VALUE_M  (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
+#define HINF_PST_END_CMD_LOW_VALUE_V  0x0000007FU
+#define HINF_PST_END_CMD_LOW_VALUE_S  3
+/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
+ *  configure cycles to lower data after voltage is changed to 1.8V.
+ */
+#define HINF_PST_END_DATA_LOW_VALUE    0x0000003FU
+#define HINF_PST_END_DATA_LOW_VALUE_M  (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
+#define HINF_PST_END_DATA_LOW_VALUE_V  0x0000003FU
+#define HINF_PST_END_DATA_LOW_VALUE_S  10
+/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
+ *  Configure the number of cycles of module clk to judge sdclk has stopped
+ */
+#define HINF_SDCLK_STOP_THRES    0x000007FFU
+#define HINF_SDCLK_STOP_THRES_M  (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
+#define HINF_SDCLK_STOP_THRES_V  0x000007FFU
+#define HINF_SDCLK_STOP_THRES_S  16
+/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
+ *  module clk divider to sample sdclk
+ */
+#define HINF_SAMPLE_CLK_DIVIDER    0x0000000FU
+#define HINF_SAMPLE_CLK_DIVIDER_M  (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
+#define HINF_SAMPLE_CLK_DIVIDER_V  0x0000000FU
+#define HINF_SAMPLE_CLK_DIVIDER_S  28
+
+/** HINF_CFG_UPDATE_REG register
+ *  update sdio configurations
+ */
+#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
+/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
+ *  update the timing configurations
+ */
+#define HINF_CONF_UPDATE    (BIT(0))
+#define HINF_CONF_UPDATE_M  (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
+#define HINF_CONF_UPDATE_V  0x00000001U
+#define HINF_CONF_UPDATE_S  0
+
+/** HINF_CFG_DATA7_REG register
+ *  SDIO configuration register
+ */
+#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
+/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
+ *  configure cis addr 318 and 574
+ */
+#define HINF_PIN_STATE    0x000000FFU
+#define HINF_PIN_STATE_M  (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
+#define HINF_PIN_STATE_V  0x000000FFU
+#define HINF_PIN_STATE_S  0
+/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
+ *  configure cis addr 312, 315, 568 and 571
+ */
+#define HINF_CHIP_STATE    0x000000FFU
+#define HINF_CHIP_STATE_M  (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
+#define HINF_CHIP_STATE_V  0x000000FFU
+#define HINF_CHIP_STATE_S  8
+/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
+ *  soft reset control for sdio module
+ */
+#define HINF_SDIO_RST    (BIT(16))
+#define HINF_SDIO_RST_M  (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
+#define HINF_SDIO_RST_V  0x00000001U
+#define HINF_SDIO_RST_S  16
+/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
+ *  sdio io ready, high enable
+ */
+#define HINF_SDIO_IOREADY0    (BIT(17))
+#define HINF_SDIO_IOREADY0_M  (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
+#define HINF_SDIO_IOREADY0_V  0x00000001U
+#define HINF_SDIO_IOREADY0_S  17
+/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
+ *  sdio memory power down, high active
+ */
+#define HINF_SDIO_MEM_PD    (BIT(18))
+#define HINF_SDIO_MEM_PD_M  (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
+#define HINF_SDIO_MEM_PD_V  0x00000001U
+#define HINF_SDIO_MEM_PD_S  18
+/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
+ *  enable sdio interrupt on data1 line
+ */
+#define HINF_ESDIO_DATA1_INT_EN    (BIT(19))
+#define HINF_ESDIO_DATA1_INT_EN_M  (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
+#define HINF_ESDIO_DATA1_INT_EN_V  0x00000001U
+#define HINF_ESDIO_DATA1_INT_EN_S  19
+/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
+ *  control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
+ */
+#define HINF_SDIO_SWITCH_VOLT_SW    (BIT(20))
+#define HINF_SDIO_SWITCH_VOLT_SW_M  (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
+#define HINF_SDIO_SWITCH_VOLT_SW_V  0x00000001U
+#define HINF_SDIO_SWITCH_VOLT_SW_S  20
+/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
+ *  enable block length to be fixed to 512 bytes in ddr50 mode
+ */
+#define HINF_DDR50_BLK_LEN_FIX_EN    (BIT(21))
+#define HINF_DDR50_BLK_LEN_FIX_EN_M  (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
+#define HINF_DDR50_BLK_LEN_FIX_EN_V  0x00000001U
+#define HINF_DDR50_BLK_LEN_FIX_EN_S  21
+/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
+ *  sdio apb clock for configuration force on control:0-gating,1-force on.
+ */
+#define HINF_CLK_EN    (BIT(22))
+#define HINF_CLK_EN_M  (HINF_CLK_EN_V << HINF_CLK_EN_S)
+#define HINF_CLK_EN_V  0x00000001U
+#define HINF_CLK_EN_S  22
+/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
+ *  configure if support sdr50 mode in cccr
+ */
+#define HINF_SDDR50    (BIT(23))
+#define HINF_SDDR50_M  (HINF_SDDR50_V << HINF_SDDR50_S)
+#define HINF_SDDR50_V  0x00000001U
+#define HINF_SDDR50_S  23
+/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
+ *  configure if support sdr104 mode in cccr
+ */
+#define HINF_SSDR104    (BIT(24))
+#define HINF_SSDR104_M  (HINF_SSDR104_V << HINF_SSDR104_S)
+#define HINF_SSDR104_V  0x00000001U
+#define HINF_SSDR104_S  24
+/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
+ *  configure if support ddr50 mode in cccr
+ */
+#define HINF_SSDR50    (BIT(25))
+#define HINF_SSDR50_M  (HINF_SSDR50_V << HINF_SSDR50_S)
+#define HINF_SSDR50_V  0x00000001U
+#define HINF_SSDR50_S  25
+/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
+ *  configure if support driver type D in cccr
+ */
+#define HINF_SDTD    (BIT(26))
+#define HINF_SDTD_M  (HINF_SDTD_V << HINF_SDTD_S)
+#define HINF_SDTD_V  0x00000001U
+#define HINF_SDTD_S  26
+/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
+ *  configure if support driver type A in cccr
+ */
+#define HINF_SDTA    (BIT(27))
+#define HINF_SDTA_M  (HINF_SDTA_V << HINF_SDTA_S)
+#define HINF_SDTA_V  0x00000001U
+#define HINF_SDTA_S  27
+/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
+ *  configure if support driver type C in cccr
+ */
+#define HINF_SDTC    (BIT(28))
+#define HINF_SDTC_M  (HINF_SDTC_V << HINF_SDTC_S)
+#define HINF_SDTC_V  0x00000001U
+#define HINF_SDTC_S  28
+/** HINF_SAI : R/W; bitpos: [29]; default: 1;
+ *  configure if support asynchronous interrupt in cccr
+ */
+#define HINF_SAI    (BIT(29))
+#define HINF_SAI_M  (HINF_SAI_V << HINF_SAI_S)
+#define HINF_SAI_V  0x00000001U
+#define HINF_SAI_S  29
+/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0;
+ *  clear sdio_wake_up signal after the chip wakes up
+ */
+#define HINF_SDIO_WAKEUP_CLR    (BIT(30))
+#define HINF_SDIO_WAKEUP_CLR_M  (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
+#define HINF_SDIO_WAKEUP_CLR_V  0x00000001U
+#define HINF_SDIO_WAKEUP_CLR_S  30
+
+/** HINF_CIS_CONF_W0_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
+/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 39~36
+ */
+#define HINF_CIS_CONF_W0    0xFFFFFFFFU
+#define HINF_CIS_CONF_W0_M  (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
+#define HINF_CIS_CONF_W0_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W0_S  0
+
+/** HINF_CIS_CONF_W1_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
+/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 43~40
+ */
+#define HINF_CIS_CONF_W1    0xFFFFFFFFU
+#define HINF_CIS_CONF_W1_M  (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
+#define HINF_CIS_CONF_W1_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W1_S  0
+
+/** HINF_CIS_CONF_W2_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
+/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 47~44
+ */
+#define HINF_CIS_CONF_W2    0xFFFFFFFFU
+#define HINF_CIS_CONF_W2_M  (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
+#define HINF_CIS_CONF_W2_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W2_S  0
+
+/** HINF_CIS_CONF_W3_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
+/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 51~48
+ */
+#define HINF_CIS_CONF_W3    0xFFFFFFFFU
+#define HINF_CIS_CONF_W3_M  (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
+#define HINF_CIS_CONF_W3_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W3_S  0
+
+/** HINF_CIS_CONF_W4_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
+/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 55~52
+ */
+#define HINF_CIS_CONF_W4    0xFFFFFFFFU
+#define HINF_CIS_CONF_W4_M  (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
+#define HINF_CIS_CONF_W4_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W4_S  0
+
+/** HINF_CIS_CONF_W5_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
+/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 59~56
+ */
+#define HINF_CIS_CONF_W5    0xFFFFFFFFU
+#define HINF_CIS_CONF_W5_M  (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
+#define HINF_CIS_CONF_W5_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W5_S  0
+
+/** HINF_CIS_CONF_W6_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
+/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 63~60
+ */
+#define HINF_CIS_CONF_W6    0xFFFFFFFFU
+#define HINF_CIS_CONF_W6_M  (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
+#define HINF_CIS_CONF_W6_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W6_S  0
+
+/** HINF_CIS_CONF_W7_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
+/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configure cis addr 67~64
+ */
+#define HINF_CIS_CONF_W7    0xFFFFFFFFU
+#define HINF_CIS_CONF_W7_M  (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
+#define HINF_CIS_CONF_W7_V  0xFFFFFFFFU
+#define HINF_CIS_CONF_W7_S  0
+
+/** HINF_CFG_DATA16_REG register
+ *  SDIO cis configuration register
+ */
+#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
+/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
+ *  configure device id of function2 in cis
+ */
+#define HINF_DEVICE_ID_FN2    0x0000FFFFU
+#define HINF_DEVICE_ID_FN2_M  (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
+#define HINF_DEVICE_ID_FN2_V  0x0000FFFFU
+#define HINF_DEVICE_ID_FN2_S  0
+/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
+ *  configure user id of function2 in cis
+ */
+#define HINF_USER_ID_FN2    0x0000FFFFU
+#define HINF_USER_ID_FN2_M  (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
+#define HINF_USER_ID_FN2_V  0x0000FFFFU
+#define HINF_USER_ID_FN2_S  16
+
+/** HINF_CFG_UHS1_INT_MODE_REG register
+ *  configure int to start and end ahead of time in uhs1 mode
+ */
+#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
+/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+ */
+#define HINF_INTOE_END_AHEAD_MODE    0x00000003U
+#define HINF_INTOE_END_AHEAD_MODE_M  (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
+#define HINF_INTOE_END_AHEAD_MODE_V  0x00000003U
+#define HINF_INTOE_END_AHEAD_MODE_S  0
+/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+ */
+#define HINF_INT_END_AHEAD_MODE    0x00000003U
+#define HINF_INT_END_AHEAD_MODE_M  (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
+#define HINF_INT_END_AHEAD_MODE_V  0x00000003U
+#define HINF_INT_END_AHEAD_MODE_S  2
+/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+ */
+#define HINF_INTOE_ST_AHEAD_MODE    0x00000003U
+#define HINF_INTOE_ST_AHEAD_MODE_M  (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
+#define HINF_INTOE_ST_AHEAD_MODE_V  0x00000003U
+#define HINF_INTOE_ST_AHEAD_MODE_S  4
+/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+ */
+#define HINF_INT_ST_AHEAD_MODE    0x00000003U
+#define HINF_INT_ST_AHEAD_MODE_M  (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
+#define HINF_INT_ST_AHEAD_MODE_V  0x00000003U
+#define HINF_INT_ST_AHEAD_MODE_S  6
+
+/** HINF_CONF_STATUS_REG register
+ *  func0 config0 status
+ */
+#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
+/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
+ *  func0 config0 (addr: 0x20f0 ) status
+ */
+#define HINF_FUNC0_CONFIG0    0x000000FFU
+#define HINF_FUNC0_CONFIG0_M  (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
+#define HINF_FUNC0_CONFIG0_V  0x000000FFU
+#define HINF_FUNC0_CONFIG0_S  0
+/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
+ *  sdr25 status
+ */
+#define HINF_SDR25_ST    (BIT(8))
+#define HINF_SDR25_ST_M  (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
+#define HINF_SDR25_ST_V  0x00000001U
+#define HINF_SDR25_ST_S  8
+/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
+ *  sdr50 status
+ */
+#define HINF_SDR50_ST    (BIT(9))
+#define HINF_SDR50_ST_M  (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
+#define HINF_SDR50_ST_V  0x00000001U
+#define HINF_SDR50_ST_S  9
+/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
+ *  sdr104 status
+ */
+#define HINF_SDR104_ST    (BIT(10))
+#define HINF_SDR104_ST_M  (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
+#define HINF_SDR104_ST_V  0x00000001U
+#define HINF_SDR104_ST_S  10
+/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
+ *  ddr50 status
+ */
+#define HINF_DDR50_ST    (BIT(11))
+#define HINF_DDR50_ST_M  (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
+#define HINF_DDR50_ST_V  0x00000001U
+#define HINF_DDR50_ST_S  11
+/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
+ *  tune_st fsm status
+ */
+#define HINF_TUNE_ST    0x00000007U
+#define HINF_TUNE_ST_M  (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
+#define HINF_TUNE_ST_V  0x00000007U
+#define HINF_TUNE_ST_S  12
+/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
+ *  sdio switch voltage status:0-3.3V, 1-1.8V.
+ */
+#define HINF_SDIO_SWITCH_VOLT_ST    (BIT(15))
+#define HINF_SDIO_SWITCH_VOLT_ST_M  (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
+#define HINF_SDIO_SWITCH_VOLT_ST_V  0x00000001U
+#define HINF_SDIO_SWITCH_VOLT_ST_S  15
+/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
+ *  sdio switch voltage ldo ready
+ */
+#define HINF_SDIO_SWITCH_END    (BIT(16))
+#define HINF_SDIO_SWITCH_END_M  (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
+#define HINF_SDIO_SWITCH_END_V  0x00000001U
+#define HINF_SDIO_SWITCH_END_S  16
+
+/** HINF_SDIO_SLAVE_ECO_LOW_REG register
+ *  sdio_slave redundant control registers
+ */
+#define HINF_SDIO_SLAVE_ECO_LOW_REG (DR_REG_HINF_BASE + 0xa4)
+/** HINF_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_RDN_ECO_LOW    0xFFFFFFFFU
+#define HINF_RDN_ECO_LOW_M  (HINF_RDN_ECO_LOW_V << HINF_RDN_ECO_LOW_S)
+#define HINF_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HINF_RDN_ECO_LOW_S  0
+
+/** HINF_SDIO_SLAVE_ECO_HIGH_REG register
+ *  sdio_slave redundant control registers
+ */
+#define HINF_SDIO_SLAVE_ECO_HIGH_REG (DR_REG_HINF_BASE + 0xa8)
+/** HINF_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HINF_RDN_ECO_HIGH_M  (HINF_RDN_ECO_HIGH_V << HINF_RDN_ECO_HIGH_S)
+#define HINF_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HINF_RDN_ECO_HIGH_S  0
+
+/** HINF_SDIO_SLAVE_ECO_CONF_REG register
+ *  sdio_slave redundant control registers
+ */
+#define HINF_SDIO_SLAVE_ECO_CONF_REG (DR_REG_HINF_BASE + 0xac)
+/** HINF_SDIO_SLAVE_RDN_RESULT : RO; bitpos: [0]; default: 0;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_SDIO_SLAVE_RDN_RESULT    (BIT(0))
+#define HINF_SDIO_SLAVE_RDN_RESULT_M  (HINF_SDIO_SLAVE_RDN_RESULT_V << HINF_SDIO_SLAVE_RDN_RESULT_S)
+#define HINF_SDIO_SLAVE_RDN_RESULT_V  0x00000001U
+#define HINF_SDIO_SLAVE_RDN_RESULT_S  0
+/** HINF_SDIO_SLAVE_RDN_ENA : R/W; bitpos: [1]; default: 0;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_SDIO_SLAVE_RDN_ENA    (BIT(1))
+#define HINF_SDIO_SLAVE_RDN_ENA_M  (HINF_SDIO_SLAVE_RDN_ENA_V << HINF_SDIO_SLAVE_RDN_ENA_S)
+#define HINF_SDIO_SLAVE_RDN_ENA_V  0x00000001U
+#define HINF_SDIO_SLAVE_RDN_ENA_S  1
+/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT : RO; bitpos: [2]; default: 0;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT    (BIT(2))
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_M  (HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S)
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V  0x00000001U
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S  2
+/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA : R/W; bitpos: [3]; default: 0;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA    (BIT(3))
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_M  (HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S)
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V  0x00000001U
+#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S  3
+/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT : RO; bitpos: [4]; default: 0;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT    (BIT(4))
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_M  (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S)
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V  0x00000001U
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S  4
+/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA : R/W; bitpos: [5]; default: 0;
+ *  redundant registers for sdio_slave
+ */
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA    (BIT(5))
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_M  (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S)
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V  0x00000001U
+#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S  5
+
+/** HINF_SDIO_SLAVE_LDO_CONF_REG register
+ *  sdio slave ldo control register
+ */
+#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
+/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
+ *  control ldo ready signal by sdio slave itself
+ */
+#define HINF_LDO_READY_CTL_IN_EN    (BIT(0))
+#define HINF_LDO_READY_CTL_IN_EN_M  (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
+#define HINF_LDO_READY_CTL_IN_EN_V  0x00000001U
+#define HINF_LDO_READY_CTL_IN_EN_S  0
+/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
+ *  configure ldo ready counting threshold value, the actual counting target is
+ *  2^(ldo_ready_thres)-1
+ */
+#define HINF_LDO_READY_THRES    0x0000001FU
+#define HINF_LDO_READY_THRES_M  (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
+#define HINF_LDO_READY_THRES_V  0x0000001FU
+#define HINF_LDO_READY_THRES_S  1
+/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
+ *  ignore ldo ready signal
+ */
+#define HINF_LDO_READY_IGNORE_EN    (BIT(6))
+#define HINF_LDO_READY_IGNORE_EN_M  (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
+#define HINF_LDO_READY_IGNORE_EN_V  0x00000001U
+#define HINF_LDO_READY_IGNORE_EN_S  6
+
+/** HINF_SDIO_DATE_REG register
+ *  ******* Description ***********
+ */
+#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
+/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208;
+ *  sdio version date.
+ */
+#define HINF_SDIO_DATE    0xFFFFFFFFU
+#define HINF_SDIO_DATE_M  (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
+#define HINF_SDIO_DATE_V  0xFFFFFFFFU
+#define HINF_SDIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/hinf_struct.h b/components/soc/esp32p4/include/soc/hinf_struct.h
new file mode 100644
index 0000000000..858db7b848
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hinf_struct.h
@@ -0,0 +1,555 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration registers */
+/** Type of cfg_data0 register
+ *  Configure sdio cis content
+ */
+typedef union {
+    struct {
+        /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
+         *  configure device id of function1 in cis
+         */
+        uint32_t device_id_fn1:16;
+        /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
+         *  configure user id of function1 in cis
+         */
+        uint32_t user_id_fn1:16;
+    };
+    uint32_t val;
+} hinf_cfg_data0_reg_t;
+
+/** Type of cfg_data1 register
+ *  SDIO configuration register
+ */
+typedef union {
+    struct {
+        /** sdio_enable : R/W; bitpos: [0]; default: 1;
+         *  Sdio clock enable
+         */
+        uint32_t sdio_enable:1;
+        /** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
+         *  sdio function1 io ready signal in cis
+         */
+        uint32_t sdio_ioready1:1;
+        /** highspeed_enable : R/W; bitpos: [2]; default: 0;
+         *  Highspeed enable in cccr
+         */
+        uint32_t highspeed_enable:1;
+        /** highspeed_mode : RO; bitpos: [3]; default: 0;
+         *  highspeed mode status in cccr
+         */
+        uint32_t highspeed_mode:1;
+        /** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
+         *  sdio card detect enable
+         */
+        uint32_t sdio_cd_enable:1;
+        /** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
+         *  sdio function1 io ready signal in cis
+         */
+        uint32_t sdio_ioready2:1;
+        /** sdio_int_mask : R/W; bitpos: [6]; default: 0;
+         *  mask sdio interrupt in cccr, high active
+         */
+        uint32_t sdio_int_mask:1;
+        /** ioenable2 : RO; bitpos: [7]; default: 0;
+         *  ioe2 status in cccr
+         */
+        uint32_t ioenable2:1;
+        /** cd_disable : RO; bitpos: [8]; default: 0;
+         *  card disable status in cccr
+         */
+        uint32_t cd_disable:1;
+        /** func1_eps : RO; bitpos: [9]; default: 0;
+         *  function1 eps status in fbr
+         */
+        uint32_t func1_eps:1;
+        /** emp : RO; bitpos: [10]; default: 0;
+         *  empc status in cccr
+         */
+        uint32_t emp:1;
+        /** ioenable1 : RO; bitpos: [11]; default: 0;
+         *  ioe1 status in cccr
+         */
+        uint32_t ioenable1:1;
+        /** sdio_ver : R/W; bitpos: [23:12]; default: 562;
+         *  sdio version in cccr
+         */
+        uint32_t sdio_ver:12;
+        /** func2_eps : RO; bitpos: [24]; default: 0;
+         *  function2 eps status in fbr
+         */
+        uint32_t func2_eps:1;
+        /** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
+         *  [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
+         *  in delayed cycles control,0:no delay, 1:delay 1 cycle.
+         *  [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
+         *  mode.
+         *  [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
+         *  [12]=0,posedge when highspeed mode enable.
+         *  [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
+         *  [28]: sdio data pad pull up enable
+         */
+        uint32_t sdio20_conf:7;
+    };
+    uint32_t val;
+} hinf_cfg_data1_reg_t;
+
+/** Type of cfg_timing register
+ *  Timing configuration registers
+ */
+typedef union {
+    struct {
+        /** ncrc : R/W; bitpos: [2:0]; default: 2;
+         *  configure Ncrc parameter in sdr50/104 mode, no more than 6.
+         */
+        uint32_t ncrc:3;
+        /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
+         *  configure cycles to lower cmd after voltage is changed to 1.8V.
+         */
+        uint32_t pst_end_cmd_low_value:7;
+        /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
+         *  configure cycles to lower data after voltage is changed to 1.8V.
+         */
+        uint32_t pst_end_data_low_value:6;
+        /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
+         *  Configure the number of cycles of module clk to judge sdclk has stopped
+         */
+        uint32_t sdclk_stop_thres:11;
+        uint32_t reserved_27:1;
+        /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
+         *  module clk divider to sample sdclk
+         */
+        uint32_t sample_clk_divider:4;
+    };
+    uint32_t val;
+} hinf_cfg_timing_reg_t;
+
+/** Type of cfg_update register
+ *  update sdio configurations
+ */
+typedef union {
+    struct {
+        /** conf_update : WT; bitpos: [0]; default: 0;
+         *  update the timing configurations
+         */
+        uint32_t conf_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hinf_cfg_update_reg_t;
+
+/** Type of cfg_data7 register
+ *  SDIO configuration register
+ */
+typedef union {
+    struct {
+        /** pin_state : R/W; bitpos: [7:0]; default: 0;
+         *  configure cis addr 318 and 574
+         */
+        uint32_t pin_state:8;
+        /** chip_state : R/W; bitpos: [15:8]; default: 0;
+         *  configure cis addr 312, 315, 568 and 571
+         */
+        uint32_t chip_state:8;
+        /** sdio_rst : R/W; bitpos: [16]; default: 0;
+         *  soft reset control for sdio module
+         */
+        uint32_t sdio_rst:1;
+        /** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
+         *  sdio io ready, high enable
+         */
+        uint32_t sdio_ioready0:1;
+        /** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
+         *  sdio memory power down, high active
+         */
+        uint32_t sdio_mem_pd:1;
+        /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
+         *  enable sdio interrupt on data1 line
+         */
+        uint32_t esdio_data1_int_en:1;
+        /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
+         *  control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
+         */
+        uint32_t sdio_switch_volt_sw:1;
+        /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
+         *  enable block length to be fixed to 512 bytes in ddr50 mode
+         */
+        uint32_t ddr50_blk_len_fix_en:1;
+        /** clk_en : R/W; bitpos: [22]; default: 0;
+         *  sdio apb clock for configuration force on control:0-gating,1-force on.
+         */
+        uint32_t clk_en:1;
+        /** sddr50 : R/W; bitpos: [23]; default: 1;
+         *  configure if support sdr50 mode in cccr
+         */
+        uint32_t sddr50:1;
+        /** ssdr104 : R/W; bitpos: [24]; default: 1;
+         *  configure if support sdr104 mode in cccr
+         */
+        uint32_t ssdr104:1;
+        /** ssdr50 : R/W; bitpos: [25]; default: 1;
+         *  configure if support ddr50 mode in cccr
+         */
+        uint32_t ssdr50:1;
+        /** sdtd : R/W; bitpos: [26]; default: 0;
+         *  configure if support driver type D in cccr
+         */
+        uint32_t sdtd:1;
+        /** sdta : R/W; bitpos: [27]; default: 0;
+         *  configure if support driver type A in cccr
+         */
+        uint32_t sdta:1;
+        /** sdtc : R/W; bitpos: [28]; default: 0;
+         *  configure if support driver type C in cccr
+         */
+        uint32_t sdtc:1;
+        /** sai : R/W; bitpos: [29]; default: 1;
+         *  configure if support asynchronous interrupt in cccr
+         */
+        uint32_t sai:1;
+        /** sdio_wakeup_clr : WT; bitpos: [30]; default: 0;
+         *  clear sdio_wake_up signal after the chip wakes up
+         */
+        uint32_t sdio_wakeup_clr:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hinf_cfg_data7_reg_t;
+
+/** Type of cis_conf_w0 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 39~36
+         */
+        uint32_t cis_conf_w0:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w0_reg_t;
+
+/** Type of cis_conf_w1 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 43~40
+         */
+        uint32_t cis_conf_w1:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w1_reg_t;
+
+/** Type of cis_conf_w2 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 47~44
+         */
+        uint32_t cis_conf_w2:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w2_reg_t;
+
+/** Type of cis_conf_w3 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 51~48
+         */
+        uint32_t cis_conf_w3:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w3_reg_t;
+
+/** Type of cis_conf_w4 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 55~52
+         */
+        uint32_t cis_conf_w4:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w4_reg_t;
+
+/** Type of cis_conf_w5 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 59~56
+         */
+        uint32_t cis_conf_w5:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w5_reg_t;
+
+/** Type of cis_conf_w6 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 63~60
+         */
+        uint32_t cis_conf_w6:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w6_reg_t;
+
+/** Type of cis_conf_w7 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configure cis addr 67~64
+         */
+        uint32_t cis_conf_w7:32;
+    };
+    uint32_t val;
+} hinf_cis_conf_w7_reg_t;
+
+/** Type of cfg_data16 register
+ *  SDIO cis configuration register
+ */
+typedef union {
+    struct {
+        /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
+         *  configure device id of function2 in cis
+         */
+        uint32_t device_id_fn2:16;
+        /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
+         *  configure user id of function2 in cis
+         */
+        uint32_t user_id_fn2:16;
+    };
+    uint32_t val;
+} hinf_cfg_data16_reg_t;
+
+/** Type of cfg_uhs1_int_mode register
+ *  configure int to start and end ahead of time in uhs1 mode
+ */
+typedef union {
+    struct {
+        /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
+         *  intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+         */
+        uint32_t intoe_end_ahead_mode:2;
+        /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
+         *  int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+         */
+        uint32_t int_end_ahead_mode:2;
+        /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
+         *  intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+         */
+        uint32_t intoe_st_ahead_mode:2;
+        /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
+         *  int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
+         */
+        uint32_t int_st_ahead_mode:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hinf_cfg_uhs1_int_mode_reg_t;
+
+/** Type of sdio_slave_eco_low register
+ *  sdio_slave redundant control registers
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} hinf_sdio_slave_eco_low_reg_t;
+
+/** Type of sdio_slave_eco_high register
+ *  sdio_slave redundant control registers
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} hinf_sdio_slave_eco_high_reg_t;
+
+/** Type of sdio_slave_eco_conf register
+ *  sdio_slave redundant control registers
+ */
+typedef union {
+    struct {
+        /** sdio_slave_rdn_result : RO; bitpos: [0]; default: 0;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t sdio_slave_rdn_result:1;
+        /** sdio_slave_rdn_ena : R/W; bitpos: [1]; default: 0;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t sdio_slave_rdn_ena:1;
+        /** sdio_slave_sdio_clk_rdn_result : RO; bitpos: [2]; default: 0;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t sdio_slave_sdio_clk_rdn_result:1;
+        /** sdio_slave_sdio_clk_rdn_ena : R/W; bitpos: [3]; default: 0;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t sdio_slave_sdio_clk_rdn_ena:1;
+        /** sdio_slave_sdclk_pad_rdn_result : RO; bitpos: [4]; default: 0;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t sdio_slave_sdclk_pad_rdn_result:1;
+        /** sdio_slave_sdclk_pad_rdn_ena : R/W; bitpos: [5]; default: 0;
+         *  redundant registers for sdio_slave
+         */
+        uint32_t sdio_slave_sdclk_pad_rdn_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hinf_sdio_slave_eco_conf_reg_t;
+
+/** Type of sdio_slave_ldo_conf register
+ *  sdio slave ldo control register
+ */
+typedef union {
+    struct {
+        /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
+         *  control ldo ready signal by sdio slave itself
+         */
+        uint32_t ldo_ready_ctl_in_en:1;
+        /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
+         *  configure ldo ready counting threshold value, the actual counting target is
+         *  2^(ldo_ready_thres)-1
+         */
+        uint32_t ldo_ready_thres:5;
+        /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
+         *  ignore ldo ready signal
+         */
+        uint32_t ldo_ready_ignore_en:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hinf_sdio_slave_ldo_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of conf_status register
+ *  func0 config0 status
+ */
+typedef union {
+    struct {
+        /** func0_config0 : RO; bitpos: [7:0]; default: 0;
+         *  func0 config0 (addr: 0x20f0 ) status
+         */
+        uint32_t func0_config0:8;
+        /** sdr25_st : RO; bitpos: [8]; default: 0;
+         *  sdr25 status
+         */
+        uint32_t sdr25_st:1;
+        /** sdr50_st : RO; bitpos: [9]; default: 0;
+         *  sdr50 status
+         */
+        uint32_t sdr50_st:1;
+        /** sdr104_st : RO; bitpos: [10]; default: 0;
+         *  sdr104 status
+         */
+        uint32_t sdr104_st:1;
+        /** ddr50_st : RO; bitpos: [11]; default: 0;
+         *  ddr50 status
+         */
+        uint32_t ddr50_st:1;
+        /** tune_st : RO; bitpos: [14:12]; default: 0;
+         *  tune_st fsm status
+         */
+        uint32_t tune_st:3;
+        /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
+         *  sdio switch voltage status:0-3.3V, 1-1.8V.
+         */
+        uint32_t sdio_switch_volt_st:1;
+        /** sdio_switch_end : RO; bitpos: [16]; default: 0;
+         *  sdio switch voltage ldo ready
+         */
+        uint32_t sdio_switch_end:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hinf_conf_status_reg_t;
+
+
+/** Group: Version register */
+/** Type of sdio_date register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** sdio_date : R/W; bitpos: [31:0]; default: 35664208;
+         *  sdio version date.
+         */
+        uint32_t sdio_date:32;
+    };
+    uint32_t val;
+} hinf_sdio_date_reg_t;
+
+
+typedef struct hinf_dev_t {
+    volatile hinf_cfg_data0_reg_t cfg_data0;
+    volatile hinf_cfg_data1_reg_t cfg_data1;
+    volatile hinf_cfg_timing_reg_t cfg_timing;
+    volatile hinf_cfg_update_reg_t cfg_update;
+    uint32_t reserved_010[3];
+    volatile hinf_cfg_data7_reg_t cfg_data7;
+    volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
+    volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
+    volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
+    volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
+    volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
+    volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
+    volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
+    volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
+    volatile hinf_cfg_data16_reg_t cfg_data16;
+    volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
+    uint32_t reserved_048[3];
+    volatile hinf_conf_status_reg_t conf_status;
+    uint32_t reserved_058[19];
+    volatile hinf_sdio_slave_eco_low_reg_t sdio_slave_eco_low;
+    volatile hinf_sdio_slave_eco_high_reg_t sdio_slave_eco_high;
+    volatile hinf_sdio_slave_eco_conf_reg_t sdio_slave_eco_conf;
+    volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
+    uint32_t reserved_0b4[18];
+    volatile hinf_sdio_date_reg_t sdio_date;
+} hinf_dev_t;
+
+extern hinf_dev_t HINF;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/host_reg.h b/components/soc/esp32p4/include/soc/host_reg.h
new file mode 100644
index 0000000000..c508e5ab36
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/host_reg.h
@@ -0,0 +1,3883 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SLCHOST_FUNC2_0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10)
+/** SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_FUNC2_INT    (BIT(24))
+#define SLCHOST_SLC_FUNC2_INT_M  (SLCHOST_SLC_FUNC2_INT_V << SLCHOST_SLC_FUNC2_INT_S)
+#define SLCHOST_SLC_FUNC2_INT_V  0x00000001U
+#define SLCHOST_SLC_FUNC2_INT_S  24
+
+/** SLCHOST_FUNC2_1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14)
+/** SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_FUNC2_INT_EN    (BIT(0))
+#define SLCHOST_SLC_FUNC2_INT_EN_M  (SLCHOST_SLC_FUNC2_INT_EN_V << SLCHOST_SLC_FUNC2_INT_EN_S)
+#define SLCHOST_SLC_FUNC2_INT_EN_V  0x00000001U
+#define SLCHOST_SLC_FUNC2_INT_EN_S  0
+
+/** SLCHOST_FUNC2_2_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
+/** SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_FUNC1_MDSTAT    (BIT(0))
+#define SLCHOST_SLC_FUNC1_MDSTAT_M  (SLCHOST_SLC_FUNC1_MDSTAT_V << SLCHOST_SLC_FUNC1_MDSTAT_S)
+#define SLCHOST_SLC_FUNC1_MDSTAT_V  0x00000001U
+#define SLCHOST_SLC_FUNC1_MDSTAT_S  0
+
+/** SLCHOST_GPIO_STATUS0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
+/** SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_INT0    0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_INT0_M  (SLCHOST_GPIO_SDIO_INT0_V << SLCHOST_GPIO_SDIO_INT0_S)
+#define SLCHOST_GPIO_SDIO_INT0_V  0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_INT0_S  0
+
+/** SLCHOST_GPIO_STATUS1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
+/** SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_INT1    0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_INT1_M  (SLCHOST_GPIO_SDIO_INT1_V << SLCHOST_GPIO_SDIO_INT1_S)
+#define SLCHOST_GPIO_SDIO_INT1_V  0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_INT1_S  0
+
+/** SLCHOST_GPIO_IN0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3c)
+/** SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_IN0    0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_IN0_M  (SLCHOST_GPIO_SDIO_IN0_V << SLCHOST_GPIO_SDIO_IN0_S)
+#define SLCHOST_GPIO_SDIO_IN0_V  0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_IN0_S  0
+
+/** SLCHOST_GPIO_IN1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
+/** SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_IN1    0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_IN1_M  (SLCHOST_GPIO_SDIO_IN1_V << SLCHOST_GPIO_SDIO_IN1_S)
+#define SLCHOST_GPIO_SDIO_IN1_V  0xFFFFFFFFU
+#define SLCHOST_GPIO_SDIO_IN1_S  0
+
+/** SLCHOST_SLC0HOST_TOKEN_RDATA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
+/** SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0    0x00000FFFU
+#define SLCHOST_SLC0_TOKEN0_M  (SLCHOST_SLC0_TOKEN0_V << SLCHOST_SLC0_TOKEN0_S)
+#define SLCHOST_SLC0_TOKEN0_V  0x00000FFFU
+#define SLCHOST_SLC0_TOKEN0_S  0
+/** SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_PF_VALID    (BIT(12))
+#define SLCHOST_SLC0_RX_PF_VALID_M  (SLCHOST_SLC0_RX_PF_VALID_V << SLCHOST_SLC0_RX_PF_VALID_S)
+#define SLCHOST_SLC0_RX_PF_VALID_V  0x00000001U
+#define SLCHOST_SLC0_RX_PF_VALID_S  12
+/** SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1    0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M  (SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V  0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S  16
+/** SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_PF_EOF    0x0000000FU
+#define SLCHOST_SLC0_RX_PF_EOF_M  (SLCHOST_SLC0_RX_PF_EOF_V << SLCHOST_SLC0_RX_PF_EOF_S)
+#define SLCHOST_SLC0_RX_PF_EOF_V  0x0000000FU
+#define SLCHOST_SLC0_RX_PF_EOF_S  28
+
+/** SLCHOST_SLC0_HOST_PF_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
+/** SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_PF_DATA    0xFFFFFFFFU
+#define SLCHOST_SLC0_PF_DATA_M  (SLCHOST_SLC0_PF_DATA_V << SLCHOST_SLC0_PF_DATA_S)
+#define SLCHOST_SLC0_PF_DATA_V  0xFFFFFFFFU
+#define SLCHOST_SLC0_PF_DATA_S  0
+
+/** SLCHOST_SLC1_HOST_PF_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4c)
+/** SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_PF_DATA    0xFFFFFFFFU
+#define SLCHOST_SLC1_PF_DATA_M  (SLCHOST_SLC1_PF_DATA_V << SLCHOST_SLC1_PF_DATA_S)
+#define SLCHOST_SLC1_PF_DATA_V  0xFFFFFFFFU
+#define SLCHOST_SLC1_PF_DATA_S  0
+
+/** SLCHOST_SLC0HOST_INT_RAW_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
+/** SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW    (BIT(0))
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S  0
+/** SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW    (BIT(1))
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S  1
+/** SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW    (BIT(2))
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S  2
+/** SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW    (BIT(3))
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S  3
+/** SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW    (BIT(4))
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S  4
+/** SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW    (BIT(5))
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S  5
+/** SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW    (BIT(6))
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S  6
+/** SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW    (BIT(7))
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S)
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S  7
+/** SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(8))
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S)
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S  8
+/** SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(9))
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S)
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S  9
+/** SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW    (BIT(10))
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S)
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S  10
+/** SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW    (BIT(11))
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S)
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S  11
+/** SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW    (BIT(12))
+#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M  (SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S)
+#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S  12
+/** SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW    (BIT(13))
+#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M  (SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S)
+#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S  13
+/** SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_START_INT_RAW    (BIT(14))
+#define SLCHOST_SLC0HOST_RX_START_INT_RAW_M  (SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SLCHOST_SLC0HOST_RX_START_INT_RAW_S)
+#define SLCHOST_SLC0HOST_RX_START_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_START_INT_RAW_S  14
+/** SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TX_START_INT_RAW    (BIT(15))
+#define SLCHOST_SLC0HOST_TX_START_INT_RAW_M  (SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SLCHOST_SLC0HOST_TX_START_INT_RAW_S)
+#define SLCHOST_SLC0HOST_TX_START_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0HOST_TX_START_INT_RAW_S  15
+/** SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_UDF_INT_RAW    (BIT(16))
+#define SLCHOST_SLC0_RX_UDF_INT_RAW_M  (SLCHOST_SLC0_RX_UDF_INT_RAW_V << SLCHOST_SLC0_RX_UDF_INT_RAW_S)
+#define SLCHOST_SLC0_RX_UDF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_RX_UDF_INT_RAW_S  16
+/** SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TX_OVF_INT_RAW    (BIT(17))
+#define SLCHOST_SLC0_TX_OVF_INT_RAW_M  (SLCHOST_SLC0_TX_OVF_INT_RAW_V << SLCHOST_SLC0_TX_OVF_INT_RAW_S)
+#define SLCHOST_SLC0_TX_OVF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_TX_OVF_INT_RAW_S  17
+/** SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW    (BIT(18))
+#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M  (SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S)
+#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S  18
+/** SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT0_INT_RAW    (BIT(19))
+#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SLCHOST_SLC0_EXT_BIT0_INT_RAW_S)
+#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_S  19
+/** SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT1_INT_RAW    (BIT(20))
+#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SLCHOST_SLC0_EXT_BIT1_INT_RAW_S)
+#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_S  20
+/** SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT2_INT_RAW    (BIT(21))
+#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SLCHOST_SLC0_EXT_BIT2_INT_RAW_S)
+#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_S  21
+/** SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT3_INT_RAW    (BIT(22))
+#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SLCHOST_SLC0_EXT_BIT3_INT_RAW_S)
+#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_S  22
+/** SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW    (BIT(23))
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S)
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S  23
+/** SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW    (BIT(24))
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S)
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S  24
+/** SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_INT_RAW    (BIT(25))
+#define SLCHOST_GPIO_SDIO_INT_RAW_M  (SLCHOST_GPIO_SDIO_INT_RAW_V << SLCHOST_GPIO_SDIO_INT_RAW_S)
+#define SLCHOST_GPIO_SDIO_INT_RAW_V  0x00000001U
+#define SLCHOST_GPIO_SDIO_INT_RAW_S  25
+
+/** SLCHOST_SLC1HOST_INT_RAW_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54)
+/** SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW    (BIT(0))
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S  0
+/** SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW    (BIT(1))
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S  1
+/** SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW    (BIT(2))
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S  2
+/** SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW    (BIT(3))
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S  3
+/** SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW    (BIT(4))
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S  4
+/** SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW    (BIT(5))
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S  5
+/** SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW    (BIT(6))
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S  6
+/** SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW    (BIT(7))
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S)
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S  7
+/** SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW    (BIT(8))
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S)
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S  8
+/** SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW    (BIT(9))
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S)
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S  9
+/** SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW    (BIT(10))
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S)
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S  10
+/** SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW    (BIT(11))
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S)
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S  11
+/** SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW    (BIT(12))
+#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M  (SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S)
+#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S  12
+/** SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW    (BIT(13))
+#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M  (SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S)
+#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S  13
+/** SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_START_INT_RAW    (BIT(14))
+#define SLCHOST_SLC1HOST_RX_START_INT_RAW_M  (SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SLCHOST_SLC1HOST_RX_START_INT_RAW_S)
+#define SLCHOST_SLC1HOST_RX_START_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_START_INT_RAW_S  14
+/** SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TX_START_INT_RAW    (BIT(15))
+#define SLCHOST_SLC1HOST_TX_START_INT_RAW_M  (SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SLCHOST_SLC1HOST_TX_START_INT_RAW_S)
+#define SLCHOST_SLC1HOST_TX_START_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1HOST_TX_START_INT_RAW_S  15
+/** SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_UDF_INT_RAW    (BIT(16))
+#define SLCHOST_SLC1_RX_UDF_INT_RAW_M  (SLCHOST_SLC1_RX_UDF_INT_RAW_V << SLCHOST_SLC1_RX_UDF_INT_RAW_S)
+#define SLCHOST_SLC1_RX_UDF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_RX_UDF_INT_RAW_S  16
+/** SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TX_OVF_INT_RAW    (BIT(17))
+#define SLCHOST_SLC1_TX_OVF_INT_RAW_M  (SLCHOST_SLC1_TX_OVF_INT_RAW_V << SLCHOST_SLC1_TX_OVF_INT_RAW_S)
+#define SLCHOST_SLC1_TX_OVF_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_TX_OVF_INT_RAW_S  17
+/** SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW    (BIT(18))
+#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M  (SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S)
+#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S  18
+/** SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT0_INT_RAW    (BIT(19))
+#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SLCHOST_SLC1_EXT_BIT0_INT_RAW_S)
+#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_S  19
+/** SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT1_INT_RAW    (BIT(20))
+#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SLCHOST_SLC1_EXT_BIT1_INT_RAW_S)
+#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_S  20
+/** SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT2_INT_RAW    (BIT(21))
+#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SLCHOST_SLC1_EXT_BIT2_INT_RAW_S)
+#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_S  21
+/** SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT3_INT_RAW    (BIT(22))
+#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SLCHOST_SLC1_EXT_BIT3_INT_RAW_S)
+#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_S  22
+/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW    (BIT(23))
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S)
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S  23
+/** SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW    (BIT(24))
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S)
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S  24
+/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW    (BIT(25))
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S)
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V  0x00000001U
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S  25
+
+/** SLCHOST_SLC0HOST_INT_ST_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
+/** SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST    (BIT(0))
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S  0
+/** SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST    (BIT(1))
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S  1
+/** SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST    (BIT(2))
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S  2
+/** SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST    (BIT(3))
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S  3
+/** SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST    (BIT(4))
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S  4
+/** SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST    (BIT(5))
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S  5
+/** SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST    (BIT(6))
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S  6
+/** SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST    (BIT(7))
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S)
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S  7
+/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST    (BIT(8))
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S)
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S  8
+/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST    (BIT(9))
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S)
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S  9
+/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST    (BIT(10))
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S)
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S  10
+/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST    (BIT(11))
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S)
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S  11
+/** SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ST    (BIT(12))
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SLCHOST_SLC0HOST_RX_SOF_INT_ST_S)
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_S  12
+/** SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ST    (BIT(13))
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SLCHOST_SLC0HOST_RX_EOF_INT_ST_S)
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_S  13
+/** SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_START_INT_ST    (BIT(14))
+#define SLCHOST_SLC0HOST_RX_START_INT_ST_M  (SLCHOST_SLC0HOST_RX_START_INT_ST_V << SLCHOST_SLC0HOST_RX_START_INT_ST_S)
+#define SLCHOST_SLC0HOST_RX_START_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_START_INT_ST_S  14
+/** SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TX_START_INT_ST    (BIT(15))
+#define SLCHOST_SLC0HOST_TX_START_INT_ST_M  (SLCHOST_SLC0HOST_TX_START_INT_ST_V << SLCHOST_SLC0HOST_TX_START_INT_ST_S)
+#define SLCHOST_SLC0HOST_TX_START_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0HOST_TX_START_INT_ST_S  15
+/** SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_UDF_INT_ST    (BIT(16))
+#define SLCHOST_SLC0_RX_UDF_INT_ST_M  (SLCHOST_SLC0_RX_UDF_INT_ST_V << SLCHOST_SLC0_RX_UDF_INT_ST_S)
+#define SLCHOST_SLC0_RX_UDF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_RX_UDF_INT_ST_S  16
+/** SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TX_OVF_INT_ST    (BIT(17))
+#define SLCHOST_SLC0_TX_OVF_INT_ST_M  (SLCHOST_SLC0_TX_OVF_INT_ST_V << SLCHOST_SLC0_TX_OVF_INT_ST_S)
+#define SLCHOST_SLC0_TX_OVF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_TX_OVF_INT_ST_S  17
+/** SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ST    (BIT(18))
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SLCHOST_SLC0_RX_PF_VALID_INT_ST_S)
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_S  18
+/** SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT0_INT_ST    (BIT(19))
+#define SLCHOST_SLC0_EXT_BIT0_INT_ST_M  (SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SLCHOST_SLC0_EXT_BIT0_INT_ST_S)
+#define SLCHOST_SLC0_EXT_BIT0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT0_INT_ST_S  19
+/** SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT1_INT_ST    (BIT(20))
+#define SLCHOST_SLC0_EXT_BIT1_INT_ST_M  (SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SLCHOST_SLC0_EXT_BIT1_INT_ST_S)
+#define SLCHOST_SLC0_EXT_BIT1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT1_INT_ST_S  20
+/** SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT2_INT_ST    (BIT(21))
+#define SLCHOST_SLC0_EXT_BIT2_INT_ST_M  (SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SLCHOST_SLC0_EXT_BIT2_INT_ST_S)
+#define SLCHOST_SLC0_EXT_BIT2_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT2_INT_ST_S  21
+/** SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT3_INT_ST    (BIT(22))
+#define SLCHOST_SLC0_EXT_BIT3_INT_ST_M  (SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SLCHOST_SLC0_EXT_BIT3_INT_ST_S)
+#define SLCHOST_SLC0_EXT_BIT3_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT3_INT_ST_S  22
+/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST    (BIT(23))
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S)
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S  23
+/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST    (BIT(24))
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S)
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V  0x00000001U
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S  24
+/** SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_INT_ST    (BIT(25))
+#define SLCHOST_GPIO_SDIO_INT_ST_M  (SLCHOST_GPIO_SDIO_INT_ST_V << SLCHOST_GPIO_SDIO_INT_ST_S)
+#define SLCHOST_GPIO_SDIO_INT_ST_V  0x00000001U
+#define SLCHOST_GPIO_SDIO_INT_ST_S  25
+
+/** SLCHOST_SLC1HOST_INT_ST_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5c)
+/** SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST    (BIT(0))
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S  0
+/** SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST    (BIT(1))
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S  1
+/** SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST    (BIT(2))
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S  2
+/** SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST    (BIT(3))
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S  3
+/** SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST    (BIT(4))
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S  4
+/** SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST    (BIT(5))
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S  5
+/** SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST    (BIT(6))
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S  6
+/** SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST    (BIT(7))
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S)
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S  7
+/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST    (BIT(8))
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S)
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S  8
+/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST    (BIT(9))
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S)
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S  9
+/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST    (BIT(10))
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S)
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S  10
+/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST    (BIT(11))
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S)
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S  11
+/** SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ST    (BIT(12))
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SLCHOST_SLC1HOST_RX_SOF_INT_ST_S)
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_S  12
+/** SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ST    (BIT(13))
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SLCHOST_SLC1HOST_RX_EOF_INT_ST_S)
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_S  13
+/** SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_START_INT_ST    (BIT(14))
+#define SLCHOST_SLC1HOST_RX_START_INT_ST_M  (SLCHOST_SLC1HOST_RX_START_INT_ST_V << SLCHOST_SLC1HOST_RX_START_INT_ST_S)
+#define SLCHOST_SLC1HOST_RX_START_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_START_INT_ST_S  14
+/** SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TX_START_INT_ST    (BIT(15))
+#define SLCHOST_SLC1HOST_TX_START_INT_ST_M  (SLCHOST_SLC1HOST_TX_START_INT_ST_V << SLCHOST_SLC1HOST_TX_START_INT_ST_S)
+#define SLCHOST_SLC1HOST_TX_START_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1HOST_TX_START_INT_ST_S  15
+/** SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_UDF_INT_ST    (BIT(16))
+#define SLCHOST_SLC1_RX_UDF_INT_ST_M  (SLCHOST_SLC1_RX_UDF_INT_ST_V << SLCHOST_SLC1_RX_UDF_INT_ST_S)
+#define SLCHOST_SLC1_RX_UDF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_RX_UDF_INT_ST_S  16
+/** SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TX_OVF_INT_ST    (BIT(17))
+#define SLCHOST_SLC1_TX_OVF_INT_ST_M  (SLCHOST_SLC1_TX_OVF_INT_ST_V << SLCHOST_SLC1_TX_OVF_INT_ST_S)
+#define SLCHOST_SLC1_TX_OVF_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_TX_OVF_INT_ST_S  17
+/** SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ST    (BIT(18))
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SLCHOST_SLC1_RX_PF_VALID_INT_ST_S)
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_S  18
+/** SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT0_INT_ST    (BIT(19))
+#define SLCHOST_SLC1_EXT_BIT0_INT_ST_M  (SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SLCHOST_SLC1_EXT_BIT0_INT_ST_S)
+#define SLCHOST_SLC1_EXT_BIT0_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT0_INT_ST_S  19
+/** SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT1_INT_ST    (BIT(20))
+#define SLCHOST_SLC1_EXT_BIT1_INT_ST_M  (SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SLCHOST_SLC1_EXT_BIT1_INT_ST_S)
+#define SLCHOST_SLC1_EXT_BIT1_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT1_INT_ST_S  20
+/** SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT2_INT_ST    (BIT(21))
+#define SLCHOST_SLC1_EXT_BIT2_INT_ST_M  (SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SLCHOST_SLC1_EXT_BIT2_INT_ST_S)
+#define SLCHOST_SLC1_EXT_BIT2_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT2_INT_ST_S  21
+/** SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT3_INT_ST    (BIT(22))
+#define SLCHOST_SLC1_EXT_BIT3_INT_ST_M  (SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SLCHOST_SLC1_EXT_BIT3_INT_ST_S)
+#define SLCHOST_SLC1_EXT_BIT3_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT3_INT_ST_S  22
+/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST    (BIT(23))
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S)
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S  23
+/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST    (BIT(24))
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S)
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S  24
+/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST    (BIT(25))
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S)
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V  0x00000001U
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S  25
+
+/** SLCHOST_PKT_LEN_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN    0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN_V  0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN_S  0
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK    0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V  0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S  20
+
+/** SLCHOST_STATE_W0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64)
+/** SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE0    0x000000FFU
+#define SLCHOST_SLCHOST_STATE0_M  (SLCHOST_SLCHOST_STATE0_V << SLCHOST_SLCHOST_STATE0_S)
+#define SLCHOST_SLCHOST_STATE0_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE0_S  0
+/** SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE1    0x000000FFU
+#define SLCHOST_SLCHOST_STATE1_M  (SLCHOST_SLCHOST_STATE1_V << SLCHOST_SLCHOST_STATE1_S)
+#define SLCHOST_SLCHOST_STATE1_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE1_S  8
+/** SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE2    0x000000FFU
+#define SLCHOST_SLCHOST_STATE2_M  (SLCHOST_SLCHOST_STATE2_V << SLCHOST_SLCHOST_STATE2_S)
+#define SLCHOST_SLCHOST_STATE2_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE2_S  16
+/** SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE3    0x000000FFU
+#define SLCHOST_SLCHOST_STATE3_M  (SLCHOST_SLCHOST_STATE3_V << SLCHOST_SLCHOST_STATE3_S)
+#define SLCHOST_SLCHOST_STATE3_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE3_S  24
+
+/** SLCHOST_STATE_W1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68)
+/** SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE4    0x000000FFU
+#define SLCHOST_SLCHOST_STATE4_M  (SLCHOST_SLCHOST_STATE4_V << SLCHOST_SLCHOST_STATE4_S)
+#define SLCHOST_SLCHOST_STATE4_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE4_S  0
+/** SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE5    0x000000FFU
+#define SLCHOST_SLCHOST_STATE5_M  (SLCHOST_SLCHOST_STATE5_V << SLCHOST_SLCHOST_STATE5_S)
+#define SLCHOST_SLCHOST_STATE5_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE5_S  8
+/** SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE6    0x000000FFU
+#define SLCHOST_SLCHOST_STATE6_M  (SLCHOST_SLCHOST_STATE6_V << SLCHOST_SLCHOST_STATE6_S)
+#define SLCHOST_SLCHOST_STATE6_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE6_S  16
+/** SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_STATE7    0x000000FFU
+#define SLCHOST_SLCHOST_STATE7_M  (SLCHOST_SLCHOST_STATE7_V << SLCHOST_SLCHOST_STATE7_S)
+#define SLCHOST_SLCHOST_STATE7_V  0x000000FFU
+#define SLCHOST_SLCHOST_STATE7_S  24
+
+/** SLCHOST_CONF_W0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6c)
+/** SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF0    0x000000FFU
+#define SLCHOST_SLCHOST_CONF0_M  (SLCHOST_SLCHOST_CONF0_V << SLCHOST_SLCHOST_CONF0_S)
+#define SLCHOST_SLCHOST_CONF0_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF0_S  0
+/** SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF1    0x000000FFU
+#define SLCHOST_SLCHOST_CONF1_M  (SLCHOST_SLCHOST_CONF1_V << SLCHOST_SLCHOST_CONF1_S)
+#define SLCHOST_SLCHOST_CONF1_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF1_S  8
+/** SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF2    0x000000FFU
+#define SLCHOST_SLCHOST_CONF2_M  (SLCHOST_SLCHOST_CONF2_V << SLCHOST_SLCHOST_CONF2_S)
+#define SLCHOST_SLCHOST_CONF2_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF2_S  16
+/** SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF3    0x000000FFU
+#define SLCHOST_SLCHOST_CONF3_M  (SLCHOST_SLCHOST_CONF3_V << SLCHOST_SLCHOST_CONF3_S)
+#define SLCHOST_SLCHOST_CONF3_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF3_S  24
+
+/** SLCHOST_CONF_W1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70)
+/** SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF4    0x000000FFU
+#define SLCHOST_SLCHOST_CONF4_M  (SLCHOST_SLCHOST_CONF4_V << SLCHOST_SLCHOST_CONF4_S)
+#define SLCHOST_SLCHOST_CONF4_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF4_S  0
+/** SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF5    0x000000FFU
+#define SLCHOST_SLCHOST_CONF5_M  (SLCHOST_SLCHOST_CONF5_V << SLCHOST_SLCHOST_CONF5_S)
+#define SLCHOST_SLCHOST_CONF5_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF5_S  8
+/** SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF6    0x000000FFU
+#define SLCHOST_SLCHOST_CONF6_M  (SLCHOST_SLCHOST_CONF6_V << SLCHOST_SLCHOST_CONF6_S)
+#define SLCHOST_SLCHOST_CONF6_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF6_S  16
+/** SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF7    0x000000FFU
+#define SLCHOST_SLCHOST_CONF7_M  (SLCHOST_SLCHOST_CONF7_V << SLCHOST_SLCHOST_CONF7_S)
+#define SLCHOST_SLCHOST_CONF7_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF7_S  24
+
+/** SLCHOST_CONF_W2_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74)
+/** SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF8    0x000000FFU
+#define SLCHOST_SLCHOST_CONF8_M  (SLCHOST_SLCHOST_CONF8_V << SLCHOST_SLCHOST_CONF8_S)
+#define SLCHOST_SLCHOST_CONF8_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF8_S  0
+/** SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF9    0x000000FFU
+#define SLCHOST_SLCHOST_CONF9_M  (SLCHOST_SLCHOST_CONF9_V << SLCHOST_SLCHOST_CONF9_S)
+#define SLCHOST_SLCHOST_CONF9_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF9_S  8
+/** SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF10    0x000000FFU
+#define SLCHOST_SLCHOST_CONF10_M  (SLCHOST_SLCHOST_CONF10_V << SLCHOST_SLCHOST_CONF10_S)
+#define SLCHOST_SLCHOST_CONF10_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF10_S  16
+/** SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF11    0x000000FFU
+#define SLCHOST_SLCHOST_CONF11_M  (SLCHOST_SLCHOST_CONF11_V << SLCHOST_SLCHOST_CONF11_S)
+#define SLCHOST_SLCHOST_CONF11_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF11_S  24
+
+/** SLCHOST_CONF_W3_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78)
+/** SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF12    0x000000FFU
+#define SLCHOST_SLCHOST_CONF12_M  (SLCHOST_SLCHOST_CONF12_V << SLCHOST_SLCHOST_CONF12_S)
+#define SLCHOST_SLCHOST_CONF12_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF12_S  0
+/** SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF13    0x000000FFU
+#define SLCHOST_SLCHOST_CONF13_M  (SLCHOST_SLCHOST_CONF13_V << SLCHOST_SLCHOST_CONF13_S)
+#define SLCHOST_SLCHOST_CONF13_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF13_S  8
+/** SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF14    0x000000FFU
+#define SLCHOST_SLCHOST_CONF14_M  (SLCHOST_SLCHOST_CONF14_V << SLCHOST_SLCHOST_CONF14_S)
+#define SLCHOST_SLCHOST_CONF14_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF14_S  16
+/** SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF15    0x000000FFU
+#define SLCHOST_SLCHOST_CONF15_M  (SLCHOST_SLCHOST_CONF15_V << SLCHOST_SLCHOST_CONF15_S)
+#define SLCHOST_SLCHOST_CONF15_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF15_S  24
+
+/** SLCHOST_CONF_W4_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7c)
+/** SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF16    0x000000FFU
+#define SLCHOST_SLCHOST_CONF16_M  (SLCHOST_SLCHOST_CONF16_V << SLCHOST_SLCHOST_CONF16_S)
+#define SLCHOST_SLCHOST_CONF16_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF16_S  0
+/** SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF17    0x000000FFU
+#define SLCHOST_SLCHOST_CONF17_M  (SLCHOST_SLCHOST_CONF17_V << SLCHOST_SLCHOST_CONF17_S)
+#define SLCHOST_SLCHOST_CONF17_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF17_S  8
+/** SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF18    0x000000FFU
+#define SLCHOST_SLCHOST_CONF18_M  (SLCHOST_SLCHOST_CONF18_V << SLCHOST_SLCHOST_CONF18_S)
+#define SLCHOST_SLCHOST_CONF18_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF18_S  16
+/** SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF19    0x000000FFU
+#define SLCHOST_SLCHOST_CONF19_M  (SLCHOST_SLCHOST_CONF19_V << SLCHOST_SLCHOST_CONF19_S)
+#define SLCHOST_SLCHOST_CONF19_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF19_S  24
+
+/** SLCHOST_CONF_W5_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80)
+/** SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF20    0x000000FFU
+#define SLCHOST_SLCHOST_CONF20_M  (SLCHOST_SLCHOST_CONF20_V << SLCHOST_SLCHOST_CONF20_S)
+#define SLCHOST_SLCHOST_CONF20_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF20_S  0
+/** SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF21    0x000000FFU
+#define SLCHOST_SLCHOST_CONF21_M  (SLCHOST_SLCHOST_CONF21_V << SLCHOST_SLCHOST_CONF21_S)
+#define SLCHOST_SLCHOST_CONF21_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF21_S  8
+/** SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF22    0x000000FFU
+#define SLCHOST_SLCHOST_CONF22_M  (SLCHOST_SLCHOST_CONF22_V << SLCHOST_SLCHOST_CONF22_S)
+#define SLCHOST_SLCHOST_CONF22_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF22_S  16
+/** SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF23    0x000000FFU
+#define SLCHOST_SLCHOST_CONF23_M  (SLCHOST_SLCHOST_CONF23_V << SLCHOST_SLCHOST_CONF23_S)
+#define SLCHOST_SLCHOST_CONF23_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF23_S  24
+
+/** SLCHOST_WIN_CMD_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84)
+/** SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_WIN_CMD    0x0000FFFFU
+#define SLCHOST_SLCHOST_WIN_CMD_M  (SLCHOST_SLCHOST_WIN_CMD_V << SLCHOST_SLCHOST_WIN_CMD_S)
+#define SLCHOST_SLCHOST_WIN_CMD_V  0x0000FFFFU
+#define SLCHOST_SLCHOST_WIN_CMD_S  0
+
+/** SLCHOST_CONF_W6_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88)
+/** SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF24    0x000000FFU
+#define SLCHOST_SLCHOST_CONF24_M  (SLCHOST_SLCHOST_CONF24_V << SLCHOST_SLCHOST_CONF24_S)
+#define SLCHOST_SLCHOST_CONF24_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF24_S  0
+/** SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF25    0x000000FFU
+#define SLCHOST_SLCHOST_CONF25_M  (SLCHOST_SLCHOST_CONF25_V << SLCHOST_SLCHOST_CONF25_S)
+#define SLCHOST_SLCHOST_CONF25_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF25_S  8
+/** SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF26    0x000000FFU
+#define SLCHOST_SLCHOST_CONF26_M  (SLCHOST_SLCHOST_CONF26_V << SLCHOST_SLCHOST_CONF26_S)
+#define SLCHOST_SLCHOST_CONF26_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF26_S  16
+/** SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF27    0x000000FFU
+#define SLCHOST_SLCHOST_CONF27_M  (SLCHOST_SLCHOST_CONF27_V << SLCHOST_SLCHOST_CONF27_S)
+#define SLCHOST_SLCHOST_CONF27_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF27_S  24
+
+/** SLCHOST_CONF_W7_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8c)
+/** SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF28    0x000000FFU
+#define SLCHOST_SLCHOST_CONF28_M  (SLCHOST_SLCHOST_CONF28_V << SLCHOST_SLCHOST_CONF28_S)
+#define SLCHOST_SLCHOST_CONF28_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF28_S  0
+/** SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF29    0x000000FFU
+#define SLCHOST_SLCHOST_CONF29_M  (SLCHOST_SLCHOST_CONF29_V << SLCHOST_SLCHOST_CONF29_S)
+#define SLCHOST_SLCHOST_CONF29_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF29_S  8
+/** SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF30    0x000000FFU
+#define SLCHOST_SLCHOST_CONF30_M  (SLCHOST_SLCHOST_CONF30_V << SLCHOST_SLCHOST_CONF30_S)
+#define SLCHOST_SLCHOST_CONF30_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF30_S  16
+/** SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF31    0x000000FFU
+#define SLCHOST_SLCHOST_CONF31_M  (SLCHOST_SLCHOST_CONF31_V << SLCHOST_SLCHOST_CONF31_S)
+#define SLCHOST_SLCHOST_CONF31_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF31_S  24
+
+/** SLCHOST_PKT_LEN0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90)
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0    0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_V  0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_S  0
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK    0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V  0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S  20
+
+/** SLCHOST_PKT_LEN1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94)
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1    0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_V  0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_S  0
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK    0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V  0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S  20
+
+/** SLCHOST_PKT_LEN2_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98)
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2    0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_V  0x000FFFFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_S  0
+/** SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK    0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S)
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V  0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S  20
+
+/** SLCHOST_CONF_W8_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9c)
+/** SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF32    0x000000FFU
+#define SLCHOST_SLCHOST_CONF32_M  (SLCHOST_SLCHOST_CONF32_V << SLCHOST_SLCHOST_CONF32_S)
+#define SLCHOST_SLCHOST_CONF32_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF32_S  0
+/** SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF33    0x000000FFU
+#define SLCHOST_SLCHOST_CONF33_M  (SLCHOST_SLCHOST_CONF33_V << SLCHOST_SLCHOST_CONF33_S)
+#define SLCHOST_SLCHOST_CONF33_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF33_S  8
+/** SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF34    0x000000FFU
+#define SLCHOST_SLCHOST_CONF34_M  (SLCHOST_SLCHOST_CONF34_V << SLCHOST_SLCHOST_CONF34_S)
+#define SLCHOST_SLCHOST_CONF34_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF34_S  16
+/** SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF35    0x000000FFU
+#define SLCHOST_SLCHOST_CONF35_M  (SLCHOST_SLCHOST_CONF35_V << SLCHOST_SLCHOST_CONF35_S)
+#define SLCHOST_SLCHOST_CONF35_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF35_S  24
+
+/** SLCHOST_CONF_W9_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xa0)
+/** SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF36    0x000000FFU
+#define SLCHOST_SLCHOST_CONF36_M  (SLCHOST_SLCHOST_CONF36_V << SLCHOST_SLCHOST_CONF36_S)
+#define SLCHOST_SLCHOST_CONF36_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF36_S  0
+/** SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF37    0x000000FFU
+#define SLCHOST_SLCHOST_CONF37_M  (SLCHOST_SLCHOST_CONF37_V << SLCHOST_SLCHOST_CONF37_S)
+#define SLCHOST_SLCHOST_CONF37_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF37_S  8
+/** SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF38    0x000000FFU
+#define SLCHOST_SLCHOST_CONF38_M  (SLCHOST_SLCHOST_CONF38_V << SLCHOST_SLCHOST_CONF38_S)
+#define SLCHOST_SLCHOST_CONF38_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF38_S  16
+/** SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF39    0x000000FFU
+#define SLCHOST_SLCHOST_CONF39_M  (SLCHOST_SLCHOST_CONF39_V << SLCHOST_SLCHOST_CONF39_S)
+#define SLCHOST_SLCHOST_CONF39_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF39_S  24
+
+/** SLCHOST_CONF_W10_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xa4)
+/** SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF40    0x000000FFU
+#define SLCHOST_SLCHOST_CONF40_M  (SLCHOST_SLCHOST_CONF40_V << SLCHOST_SLCHOST_CONF40_S)
+#define SLCHOST_SLCHOST_CONF40_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF40_S  0
+/** SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF41    0x000000FFU
+#define SLCHOST_SLCHOST_CONF41_M  (SLCHOST_SLCHOST_CONF41_V << SLCHOST_SLCHOST_CONF41_S)
+#define SLCHOST_SLCHOST_CONF41_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF41_S  8
+/** SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF42    0x000000FFU
+#define SLCHOST_SLCHOST_CONF42_M  (SLCHOST_SLCHOST_CONF42_V << SLCHOST_SLCHOST_CONF42_S)
+#define SLCHOST_SLCHOST_CONF42_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF42_S  16
+/** SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF43    0x000000FFU
+#define SLCHOST_SLCHOST_CONF43_M  (SLCHOST_SLCHOST_CONF43_V << SLCHOST_SLCHOST_CONF43_S)
+#define SLCHOST_SLCHOST_CONF43_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF43_S  24
+
+/** SLCHOST_CONF_W11_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xa8)
+/** SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF44    0x000000FFU
+#define SLCHOST_SLCHOST_CONF44_M  (SLCHOST_SLCHOST_CONF44_V << SLCHOST_SLCHOST_CONF44_S)
+#define SLCHOST_SLCHOST_CONF44_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF44_S  0
+/** SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF45    0x000000FFU
+#define SLCHOST_SLCHOST_CONF45_M  (SLCHOST_SLCHOST_CONF45_V << SLCHOST_SLCHOST_CONF45_S)
+#define SLCHOST_SLCHOST_CONF45_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF45_S  8
+/** SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF46    0x000000FFU
+#define SLCHOST_SLCHOST_CONF46_M  (SLCHOST_SLCHOST_CONF46_V << SLCHOST_SLCHOST_CONF46_S)
+#define SLCHOST_SLCHOST_CONF46_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF46_S  16
+/** SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF47    0x000000FFU
+#define SLCHOST_SLCHOST_CONF47_M  (SLCHOST_SLCHOST_CONF47_V << SLCHOST_SLCHOST_CONF47_S)
+#define SLCHOST_SLCHOST_CONF47_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF47_S  24
+
+/** SLCHOST_CONF_W12_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xac)
+/** SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF48    0x000000FFU
+#define SLCHOST_SLCHOST_CONF48_M  (SLCHOST_SLCHOST_CONF48_V << SLCHOST_SLCHOST_CONF48_S)
+#define SLCHOST_SLCHOST_CONF48_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF48_S  0
+/** SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF49    0x000000FFU
+#define SLCHOST_SLCHOST_CONF49_M  (SLCHOST_SLCHOST_CONF49_V << SLCHOST_SLCHOST_CONF49_S)
+#define SLCHOST_SLCHOST_CONF49_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF49_S  8
+/** SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF50    0x000000FFU
+#define SLCHOST_SLCHOST_CONF50_M  (SLCHOST_SLCHOST_CONF50_V << SLCHOST_SLCHOST_CONF50_S)
+#define SLCHOST_SLCHOST_CONF50_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF50_S  16
+/** SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF51    0x000000FFU
+#define SLCHOST_SLCHOST_CONF51_M  (SLCHOST_SLCHOST_CONF51_V << SLCHOST_SLCHOST_CONF51_S)
+#define SLCHOST_SLCHOST_CONF51_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF51_S  24
+
+/** SLCHOST_CONF_W13_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xb0)
+/** SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF52    0x000000FFU
+#define SLCHOST_SLCHOST_CONF52_M  (SLCHOST_SLCHOST_CONF52_V << SLCHOST_SLCHOST_CONF52_S)
+#define SLCHOST_SLCHOST_CONF52_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF52_S  0
+/** SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF53    0x000000FFU
+#define SLCHOST_SLCHOST_CONF53_M  (SLCHOST_SLCHOST_CONF53_V << SLCHOST_SLCHOST_CONF53_S)
+#define SLCHOST_SLCHOST_CONF53_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF53_S  8
+/** SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF54    0x000000FFU
+#define SLCHOST_SLCHOST_CONF54_M  (SLCHOST_SLCHOST_CONF54_V << SLCHOST_SLCHOST_CONF54_S)
+#define SLCHOST_SLCHOST_CONF54_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF54_S  16
+/** SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF55    0x000000FFU
+#define SLCHOST_SLCHOST_CONF55_M  (SLCHOST_SLCHOST_CONF55_V << SLCHOST_SLCHOST_CONF55_S)
+#define SLCHOST_SLCHOST_CONF55_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF55_S  24
+
+/** SLCHOST_CONF_W14_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xb4)
+/** SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF56    0x000000FFU
+#define SLCHOST_SLCHOST_CONF56_M  (SLCHOST_SLCHOST_CONF56_V << SLCHOST_SLCHOST_CONF56_S)
+#define SLCHOST_SLCHOST_CONF56_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF56_S  0
+/** SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF57    0x000000FFU
+#define SLCHOST_SLCHOST_CONF57_M  (SLCHOST_SLCHOST_CONF57_V << SLCHOST_SLCHOST_CONF57_S)
+#define SLCHOST_SLCHOST_CONF57_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF57_S  8
+/** SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF58    0x000000FFU
+#define SLCHOST_SLCHOST_CONF58_M  (SLCHOST_SLCHOST_CONF58_V << SLCHOST_SLCHOST_CONF58_S)
+#define SLCHOST_SLCHOST_CONF58_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF58_S  16
+/** SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF59    0x000000FFU
+#define SLCHOST_SLCHOST_CONF59_M  (SLCHOST_SLCHOST_CONF59_V << SLCHOST_SLCHOST_CONF59_S)
+#define SLCHOST_SLCHOST_CONF59_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF59_S  24
+
+/** SLCHOST_CONF_W15_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xb8)
+/** SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF60    0x000000FFU
+#define SLCHOST_SLCHOST_CONF60_M  (SLCHOST_SLCHOST_CONF60_V << SLCHOST_SLCHOST_CONF60_S)
+#define SLCHOST_SLCHOST_CONF60_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF60_S  0
+/** SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF61    0x000000FFU
+#define SLCHOST_SLCHOST_CONF61_M  (SLCHOST_SLCHOST_CONF61_V << SLCHOST_SLCHOST_CONF61_S)
+#define SLCHOST_SLCHOST_CONF61_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF61_S  8
+/** SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF62    0x000000FFU
+#define SLCHOST_SLCHOST_CONF62_M  (SLCHOST_SLCHOST_CONF62_V << SLCHOST_SLCHOST_CONF62_S)
+#define SLCHOST_SLCHOST_CONF62_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF62_S  16
+/** SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CONF63    0x000000FFU
+#define SLCHOST_SLCHOST_CONF63_M  (SLCHOST_SLCHOST_CONF63_V << SLCHOST_SLCHOST_CONF63_S)
+#define SLCHOST_SLCHOST_CONF63_V  0x000000FFU
+#define SLCHOST_SLCHOST_CONF63_S  24
+
+/** SLCHOST_CHECK_SUM0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xbc)
+/** SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CHECK_SUM0    0xFFFFFFFFU
+#define SLCHOST_SLCHOST_CHECK_SUM0_M  (SLCHOST_SLCHOST_CHECK_SUM0_V << SLCHOST_SLCHOST_CHECK_SUM0_S)
+#define SLCHOST_SLCHOST_CHECK_SUM0_V  0xFFFFFFFFU
+#define SLCHOST_SLCHOST_CHECK_SUM0_S  0
+
+/** SLCHOST_CHECK_SUM1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xc0)
+/** SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_CHECK_SUM1    0xFFFFFFFFU
+#define SLCHOST_SLCHOST_CHECK_SUM1_M  (SLCHOST_SLCHOST_CHECK_SUM1_V << SLCHOST_SLCHOST_CHECK_SUM1_S)
+#define SLCHOST_SLCHOST_CHECK_SUM1_V  0xFFFFFFFFU
+#define SLCHOST_SLCHOST_CHECK_SUM1_S  0
+
+/** SLCHOST_SLC1HOST_TOKEN_RDATA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xc4)
+/** SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0    0x00000FFFU
+#define SLCHOST_SLC1_TOKEN0_M  (SLCHOST_SLC1_TOKEN0_V << SLCHOST_SLC1_TOKEN0_S)
+#define SLCHOST_SLC1_TOKEN0_V  0x00000FFFU
+#define SLCHOST_SLC1_TOKEN0_S  0
+/** SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_PF_VALID    (BIT(12))
+#define SLCHOST_SLC1_RX_PF_VALID_M  (SLCHOST_SLC1_RX_PF_VALID_V << SLCHOST_SLC1_RX_PF_VALID_S)
+#define SLCHOST_SLC1_RX_PF_VALID_V  0x00000001U
+#define SLCHOST_SLC1_RX_PF_VALID_S  12
+/** SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1    0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M  (SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S)
+#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V  0x00000FFFU
+#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S  16
+/** SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_PF_EOF    0x0000000FU
+#define SLCHOST_SLC1_RX_PF_EOF_M  (SLCHOST_SLC1_RX_PF_EOF_V << SLCHOST_SLC1_RX_PF_EOF_S)
+#define SLCHOST_SLC1_RX_PF_EOF_V  0x0000000FU
+#define SLCHOST_SLC1_RX_PF_EOF_S  28
+
+/** SLCHOST_SLC0HOST_TOKEN_WDATA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xc8)
+/** SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN0_WD    0x00000FFFU
+#define SLCHOST_SLC0HOST_TOKEN0_WD_M  (SLCHOST_SLC0HOST_TOKEN0_WD_V << SLCHOST_SLC0HOST_TOKEN0_WD_S)
+#define SLCHOST_SLC0HOST_TOKEN0_WD_V  0x00000FFFU
+#define SLCHOST_SLC0HOST_TOKEN0_WD_S  0
+/** SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN1_WD    0x00000FFFU
+#define SLCHOST_SLC0HOST_TOKEN1_WD_M  (SLCHOST_SLC0HOST_TOKEN1_WD_V << SLCHOST_SLC0HOST_TOKEN1_WD_S)
+#define SLCHOST_SLC0HOST_TOKEN1_WD_V  0x00000FFFU
+#define SLCHOST_SLC0HOST_TOKEN1_WD_S  16
+
+/** SLCHOST_SLC1HOST_TOKEN_WDATA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xcc)
+/** SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN0_WD    0x00000FFFU
+#define SLCHOST_SLC1HOST_TOKEN0_WD_M  (SLCHOST_SLC1HOST_TOKEN0_WD_V << SLCHOST_SLC1HOST_TOKEN0_WD_S)
+#define SLCHOST_SLC1HOST_TOKEN0_WD_V  0x00000FFFU
+#define SLCHOST_SLC1HOST_TOKEN0_WD_S  0
+/** SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN1_WD    0x00000FFFU
+#define SLCHOST_SLC1HOST_TOKEN1_WD_M  (SLCHOST_SLC1HOST_TOKEN1_WD_V << SLCHOST_SLC1HOST_TOKEN1_WD_S)
+#define SLCHOST_SLC1HOST_TOKEN1_WD_V  0x00000FFFU
+#define SLCHOST_SLC1HOST_TOKEN1_WD_S  16
+
+/** SLCHOST_TOKEN_CON_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xd0)
+/** SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN0_DEC    (BIT(0))
+#define SLCHOST_SLC0HOST_TOKEN0_DEC_M  (SLCHOST_SLC0HOST_TOKEN0_DEC_V << SLCHOST_SLC0HOST_TOKEN0_DEC_S)
+#define SLCHOST_SLC0HOST_TOKEN0_DEC_V  0x00000001U
+#define SLCHOST_SLC0HOST_TOKEN0_DEC_S  0
+/** SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN1_DEC    (BIT(1))
+#define SLCHOST_SLC0HOST_TOKEN1_DEC_M  (SLCHOST_SLC0HOST_TOKEN1_DEC_V << SLCHOST_SLC0HOST_TOKEN1_DEC_S)
+#define SLCHOST_SLC0HOST_TOKEN1_DEC_V  0x00000001U
+#define SLCHOST_SLC0HOST_TOKEN1_DEC_S  1
+/** SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN0_WR    (BIT(2))
+#define SLCHOST_SLC0HOST_TOKEN0_WR_M  (SLCHOST_SLC0HOST_TOKEN0_WR_V << SLCHOST_SLC0HOST_TOKEN0_WR_S)
+#define SLCHOST_SLC0HOST_TOKEN0_WR_V  0x00000001U
+#define SLCHOST_SLC0HOST_TOKEN0_WR_S  2
+/** SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TOKEN1_WR    (BIT(3))
+#define SLCHOST_SLC0HOST_TOKEN1_WR_M  (SLCHOST_SLC0HOST_TOKEN1_WR_V << SLCHOST_SLC0HOST_TOKEN1_WR_S)
+#define SLCHOST_SLC0HOST_TOKEN1_WR_V  0x00000001U
+#define SLCHOST_SLC0HOST_TOKEN1_WR_S  3
+/** SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN0_DEC    (BIT(4))
+#define SLCHOST_SLC1HOST_TOKEN0_DEC_M  (SLCHOST_SLC1HOST_TOKEN0_DEC_V << SLCHOST_SLC1HOST_TOKEN0_DEC_S)
+#define SLCHOST_SLC1HOST_TOKEN0_DEC_V  0x00000001U
+#define SLCHOST_SLC1HOST_TOKEN0_DEC_S  4
+/** SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN1_DEC    (BIT(5))
+#define SLCHOST_SLC1HOST_TOKEN1_DEC_M  (SLCHOST_SLC1HOST_TOKEN1_DEC_V << SLCHOST_SLC1HOST_TOKEN1_DEC_S)
+#define SLCHOST_SLC1HOST_TOKEN1_DEC_V  0x00000001U
+#define SLCHOST_SLC1HOST_TOKEN1_DEC_S  5
+/** SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN0_WR    (BIT(6))
+#define SLCHOST_SLC1HOST_TOKEN0_WR_M  (SLCHOST_SLC1HOST_TOKEN0_WR_V << SLCHOST_SLC1HOST_TOKEN0_WR_S)
+#define SLCHOST_SLC1HOST_TOKEN0_WR_V  0x00000001U
+#define SLCHOST_SLC1HOST_TOKEN0_WR_S  6
+/** SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TOKEN1_WR    (BIT(7))
+#define SLCHOST_SLC1HOST_TOKEN1_WR_M  (SLCHOST_SLC1HOST_TOKEN1_WR_V << SLCHOST_SLC1HOST_TOKEN1_WR_S)
+#define SLCHOST_SLC1HOST_TOKEN1_WR_V  0x00000001U
+#define SLCHOST_SLC1HOST_TOKEN1_WR_S  7
+/** SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_LEN_WR    (BIT(8))
+#define SLCHOST_SLC0HOST_LEN_WR_M  (SLCHOST_SLC0HOST_LEN_WR_V << SLCHOST_SLC0HOST_LEN_WR_S)
+#define SLCHOST_SLC0HOST_LEN_WR_V  0x00000001U
+#define SLCHOST_SLC0HOST_LEN_WR_S  8
+
+/** SLCHOST_SLC0HOST_INT_CLR_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd4)
+/** SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR    (BIT(0))
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S  0
+/** SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR    (BIT(1))
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S  1
+/** SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR    (BIT(2))
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S  2
+/** SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR    (BIT(3))
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S  3
+/** SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR    (BIT(4))
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S  4
+/** SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR    (BIT(5))
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S  5
+/** SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR    (BIT(6))
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S  6
+/** SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR    (BIT(7))
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S)
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S  7
+/** SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(8))
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S)
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S  8
+/** SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(9))
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S)
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S  9
+/** SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR    (BIT(10))
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S)
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S  10
+/** SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR    (BIT(11))
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S)
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S  11
+/** SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR    (BIT(12))
+#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M  (SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S)
+#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S  12
+/** SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR    (BIT(13))
+#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M  (SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S)
+#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S  13
+/** SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_START_INT_CLR    (BIT(14))
+#define SLCHOST_SLC0HOST_RX_START_INT_CLR_M  (SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SLCHOST_SLC0HOST_RX_START_INT_CLR_S)
+#define SLCHOST_SLC0HOST_RX_START_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_START_INT_CLR_S  14
+/** SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TX_START_INT_CLR    (BIT(15))
+#define SLCHOST_SLC0HOST_TX_START_INT_CLR_M  (SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SLCHOST_SLC0HOST_TX_START_INT_CLR_S)
+#define SLCHOST_SLC0HOST_TX_START_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0HOST_TX_START_INT_CLR_S  15
+/** SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_UDF_INT_CLR    (BIT(16))
+#define SLCHOST_SLC0_RX_UDF_INT_CLR_M  (SLCHOST_SLC0_RX_UDF_INT_CLR_V << SLCHOST_SLC0_RX_UDF_INT_CLR_S)
+#define SLCHOST_SLC0_RX_UDF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_RX_UDF_INT_CLR_S  16
+/** SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TX_OVF_INT_CLR    (BIT(17))
+#define SLCHOST_SLC0_TX_OVF_INT_CLR_M  (SLCHOST_SLC0_TX_OVF_INT_CLR_V << SLCHOST_SLC0_TX_OVF_INT_CLR_S)
+#define SLCHOST_SLC0_TX_OVF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_TX_OVF_INT_CLR_S  17
+/** SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR    (BIT(18))
+#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M  (SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S)
+#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S  18
+/** SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT0_INT_CLR    (BIT(19))
+#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SLCHOST_SLC0_EXT_BIT0_INT_CLR_S)
+#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_S  19
+/** SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT1_INT_CLR    (BIT(20))
+#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SLCHOST_SLC0_EXT_BIT1_INT_CLR_S)
+#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_S  20
+/** SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT2_INT_CLR    (BIT(21))
+#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SLCHOST_SLC0_EXT_BIT2_INT_CLR_S)
+#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_S  21
+/** SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT3_INT_CLR    (BIT(22))
+#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SLCHOST_SLC0_EXT_BIT3_INT_CLR_S)
+#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_S  22
+/** SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR    (BIT(23))
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S)
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S  23
+/** SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR    (BIT(24))
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S)
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S  24
+/** SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_INT_CLR    (BIT(25))
+#define SLCHOST_GPIO_SDIO_INT_CLR_M  (SLCHOST_GPIO_SDIO_INT_CLR_V << SLCHOST_GPIO_SDIO_INT_CLR_S)
+#define SLCHOST_GPIO_SDIO_INT_CLR_V  0x00000001U
+#define SLCHOST_GPIO_SDIO_INT_CLR_S  25
+
+/** SLCHOST_SLC1HOST_INT_CLR_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd8)
+/** SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR    (BIT(0))
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S  0
+/** SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR    (BIT(1))
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S  1
+/** SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR    (BIT(2))
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S  2
+/** SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR    (BIT(3))
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S  3
+/** SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR    (BIT(4))
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S  4
+/** SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR    (BIT(5))
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S  5
+/** SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR    (BIT(6))
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S  6
+/** SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR    (BIT(7))
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S)
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S  7
+/** SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR    (BIT(8))
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S)
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S  8
+/** SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR    (BIT(9))
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S)
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S  9
+/** SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR    (BIT(10))
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S)
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S  10
+/** SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR    (BIT(11))
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S)
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S  11
+/** SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR    (BIT(12))
+#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M  (SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S)
+#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S  12
+/** SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR    (BIT(13))
+#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M  (SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S)
+#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S  13
+/** SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_START_INT_CLR    (BIT(14))
+#define SLCHOST_SLC1HOST_RX_START_INT_CLR_M  (SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SLCHOST_SLC1HOST_RX_START_INT_CLR_S)
+#define SLCHOST_SLC1HOST_RX_START_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_START_INT_CLR_S  14
+/** SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TX_START_INT_CLR    (BIT(15))
+#define SLCHOST_SLC1HOST_TX_START_INT_CLR_M  (SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SLCHOST_SLC1HOST_TX_START_INT_CLR_S)
+#define SLCHOST_SLC1HOST_TX_START_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1HOST_TX_START_INT_CLR_S  15
+/** SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_UDF_INT_CLR    (BIT(16))
+#define SLCHOST_SLC1_RX_UDF_INT_CLR_M  (SLCHOST_SLC1_RX_UDF_INT_CLR_V << SLCHOST_SLC1_RX_UDF_INT_CLR_S)
+#define SLCHOST_SLC1_RX_UDF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_RX_UDF_INT_CLR_S  16
+/** SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TX_OVF_INT_CLR    (BIT(17))
+#define SLCHOST_SLC1_TX_OVF_INT_CLR_M  (SLCHOST_SLC1_TX_OVF_INT_CLR_V << SLCHOST_SLC1_TX_OVF_INT_CLR_S)
+#define SLCHOST_SLC1_TX_OVF_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_TX_OVF_INT_CLR_S  17
+/** SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR    (BIT(18))
+#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M  (SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S)
+#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S  18
+/** SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT0_INT_CLR    (BIT(19))
+#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SLCHOST_SLC1_EXT_BIT0_INT_CLR_S)
+#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_S  19
+/** SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT1_INT_CLR    (BIT(20))
+#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SLCHOST_SLC1_EXT_BIT1_INT_CLR_S)
+#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_S  20
+/** SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT2_INT_CLR    (BIT(21))
+#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SLCHOST_SLC1_EXT_BIT2_INT_CLR_S)
+#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_S  21
+/** SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT3_INT_CLR    (BIT(22))
+#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SLCHOST_SLC1_EXT_BIT3_INT_CLR_S)
+#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_S  22
+/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR    (BIT(23))
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S)
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S  23
+/** SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR    (BIT(24))
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S)
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S  24
+/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR    (BIT(25))
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S)
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V  0x00000001U
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S  25
+
+/** SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xdc)
+/** SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S  0
+/** SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S  1
+/** SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S  2
+/** SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S  3
+/** SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S  4
+/** SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S  5
+/** SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S  6
+/** SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S  7
+/** SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S  8
+/** SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S  9
+/** SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S  10
+/** SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S  11
+/** SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
+#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S)
+#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S  12
+/** SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
+#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S)
+#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S  13
+/** SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA    (BIT(14))
+#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S)
+#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S  14
+/** SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA    (BIT(15))
+#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S)
+#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S  15
+/** SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA    (BIT(16))
+#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S  16
+/** SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA    (BIT(17))
+#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S  17
+/** SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
+#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S  18
+/** SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
+#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S  19
+/** SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
+#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S  20
+/** SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
+#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S  21
+/** SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
+#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S  22
+/** SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S  23
+/** SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S)
+#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S  24
+/** SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_GPIO_SDIO_INT_ENA    (BIT(25))
+#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_M  (SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SLCHOST_FN1_GPIO_SDIO_INT_ENA_S)
+#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_S  25
+
+/** SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe0)
+/** SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S  0
+/** SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S  1
+/** SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S  2
+/** SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S  3
+/** SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S  4
+/** SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S  5
+/** SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S  6
+/** SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S  7
+/** SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S  8
+/** SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S  9
+/** SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S  10
+/** SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S  11
+/** SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
+#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S)
+#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S  12
+/** SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
+#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S)
+#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S  13
+/** SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA    (BIT(14))
+#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S)
+#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S  14
+/** SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA    (BIT(15))
+#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S)
+#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S  15
+/** SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA    (BIT(16))
+#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S  16
+/** SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA    (BIT(17))
+#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S  17
+/** SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
+#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S  18
+/** SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
+#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S  19
+/** SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
+#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S  20
+/** SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
+#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S  21
+/** SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
+#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S  22
+/** SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
+/** SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S  24
+/** SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
+#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
+
+/** SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe4)
+/** SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S  0
+/** SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S  1
+/** SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S  2
+/** SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S  3
+/** SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S  4
+/** SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S  5
+/** SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S  6
+/** SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S  7
+/** SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S  8
+/** SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S  9
+/** SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S  10
+/** SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S  11
+/** SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
+#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S)
+#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S  12
+/** SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
+#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S)
+#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S  13
+/** SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA    (BIT(14))
+#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S)
+#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S  14
+/** SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA    (BIT(15))
+#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S)
+#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S  15
+/** SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA    (BIT(16))
+#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S  16
+/** SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA    (BIT(17))
+#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S  17
+/** SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
+#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S  18
+/** SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
+#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S  19
+/** SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
+#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S  20
+/** SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
+#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S  21
+/** SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
+#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S  22
+/** SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S  23
+/** SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S)
+#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S  24
+/** SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_GPIO_SDIO_INT_ENA    (BIT(25))
+#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_M  (SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SLCHOST_FN2_GPIO_SDIO_INT_ENA_S)
+#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_S  25
+
+/** SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe8)
+/** SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S  0
+/** SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S  1
+/** SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S  2
+/** SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S  3
+/** SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S  4
+/** SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S  5
+/** SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S  6
+/** SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S  7
+/** SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S  8
+/** SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S  9
+/** SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S  10
+/** SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S  11
+/** SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
+#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S)
+#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S  12
+/** SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
+#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S)
+#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S  13
+/** SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA    (BIT(14))
+#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S)
+#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S  14
+/** SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA    (BIT(15))
+#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S)
+#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S  15
+/** SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA    (BIT(16))
+#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S  16
+/** SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA    (BIT(17))
+#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S  17
+/** SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
+#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S  18
+/** SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
+#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S  19
+/** SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
+#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S  20
+/** SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
+#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S  21
+/** SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
+#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S  22
+/** SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
+/** SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S  24
+/** SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
+#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
+
+/** SLCHOST_SLC0HOST_INT_ENA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xec)
+/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S  0
+/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S  1
+/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S  2
+/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S  3
+/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S  4
+/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S  5
+/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S  6
+/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S)
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S  7
+/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S)
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S  8
+/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S)
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S  9
+/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S)
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S  10
+/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S)
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S  11
+/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S)
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S  12
+/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S)
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S  13
+/** SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA    (BIT(14))
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_SLC0HOST_RX_START_INT_ENA_S)
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA_S  14
+/** SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA    (BIT(15))
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_SLC0HOST_TX_START_INT_ENA_S)
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA_S  15
+/** SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_UDF_INT_ENA    (BIT(16))
+#define SLCHOST_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_SLC0_RX_UDF_INT_ENA_V << SLCHOST_SLC0_RX_UDF_INT_ENA_S)
+#define SLCHOST_SLC0_RX_UDF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_RX_UDF_INT_ENA_S  16
+/** SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TX_OVF_INT_ENA    (BIT(17))
+#define SLCHOST_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_SLC0_TX_OVF_INT_ENA_V << SLCHOST_SLC0_TX_OVF_INT_ENA_S)
+#define SLCHOST_SLC0_TX_OVF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_TX_OVF_INT_ENA_S  17
+/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S)
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S  18
+/** SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA_S)
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_S  19
+/** SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA_S)
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_S  20
+/** SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA_S)
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_S  21
+/** SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA_S)
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_S  22
+/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S  23
+/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S)
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S  24
+/** SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_INT_ENA    (BIT(25))
+#define SLCHOST_GPIO_SDIO_INT_ENA_M  (SLCHOST_GPIO_SDIO_INT_ENA_V << SLCHOST_GPIO_SDIO_INT_ENA_S)
+#define SLCHOST_GPIO_SDIO_INT_ENA_V  0x00000001U
+#define SLCHOST_GPIO_SDIO_INT_ENA_S  25
+
+/** SLCHOST_SLC1HOST_INT_ENA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xf0)
+/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S  0
+/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S  1
+/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S  2
+/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S  3
+/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S  4
+/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S  5
+/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S  6
+/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S)
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S  7
+/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S)
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S  8
+/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S)
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S  9
+/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S)
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S  10
+/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S)
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S  11
+/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S)
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S  12
+/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S)
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S  13
+/** SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA    (BIT(14))
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_SLC1HOST_RX_START_INT_ENA_S)
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA_S  14
+/** SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA    (BIT(15))
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_SLC1HOST_TX_START_INT_ENA_S)
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA_S  15
+/** SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_UDF_INT_ENA    (BIT(16))
+#define SLCHOST_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_SLC1_RX_UDF_INT_ENA_V << SLCHOST_SLC1_RX_UDF_INT_ENA_S)
+#define SLCHOST_SLC1_RX_UDF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_RX_UDF_INT_ENA_S  16
+/** SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TX_OVF_INT_ENA    (BIT(17))
+#define SLCHOST_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_SLC1_TX_OVF_INT_ENA_V << SLCHOST_SLC1_TX_OVF_INT_ENA_S)
+#define SLCHOST_SLC1_TX_OVF_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_TX_OVF_INT_ENA_S  17
+/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S)
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S  18
+/** SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA_S)
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_S  19
+/** SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA_S)
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_S  20
+/** SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA_S)
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_S  21
+/** SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA_S)
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_S  22
+/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
+/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S)
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S  24
+/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
+
+/** SLCHOST_SLC0HOST_RX_INFOR_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf4)
+/** SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_INFOR    0x000FFFFFU
+#define SLCHOST_SLC0HOST_RX_INFOR_M  (SLCHOST_SLC0HOST_RX_INFOR_V << SLCHOST_SLC0HOST_RX_INFOR_S)
+#define SLCHOST_SLC0HOST_RX_INFOR_V  0x000FFFFFU
+#define SLCHOST_SLC0HOST_RX_INFOR_S  0
+
+/** SLCHOST_SLC1HOST_RX_INFOR_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf8)
+/** SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_INFOR    0x000FFFFFU
+#define SLCHOST_SLC1HOST_RX_INFOR_M  (SLCHOST_SLC1HOST_RX_INFOR_V << SLCHOST_SLC1HOST_RX_INFOR_S)
+#define SLCHOST_SLC1HOST_RX_INFOR_V  0x000FFFFFU
+#define SLCHOST_SLC1HOST_RX_INFOR_S  0
+
+/** SLCHOST_SLC0HOST_LEN_WD_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xfc)
+/** SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_LEN_WD    0xFFFFFFFFU
+#define SLCHOST_SLC0HOST_LEN_WD_M  (SLCHOST_SLC0HOST_LEN_WD_V << SLCHOST_SLC0HOST_LEN_WD_S)
+#define SLCHOST_SLC0HOST_LEN_WD_V  0xFFFFFFFFU
+#define SLCHOST_SLC0HOST_LEN_WD_S  0
+
+/** SLCHOST_SLC_APBWIN_WDATA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100)
+/** SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_WDATA    0xFFFFFFFFU
+#define SLCHOST_SLC_APBWIN_WDATA_M  (SLCHOST_SLC_APBWIN_WDATA_V << SLCHOST_SLC_APBWIN_WDATA_S)
+#define SLCHOST_SLC_APBWIN_WDATA_V  0xFFFFFFFFU
+#define SLCHOST_SLC_APBWIN_WDATA_S  0
+
+/** SLCHOST_SLC_APBWIN_CONF_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104)
+/** SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_ADDR    0x0FFFFFFFU
+#define SLCHOST_SLC_APBWIN_ADDR_M  (SLCHOST_SLC_APBWIN_ADDR_V << SLCHOST_SLC_APBWIN_ADDR_S)
+#define SLCHOST_SLC_APBWIN_ADDR_V  0x0FFFFFFFU
+#define SLCHOST_SLC_APBWIN_ADDR_S  0
+/** SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_WR    (BIT(28))
+#define SLCHOST_SLC_APBWIN_WR_M  (SLCHOST_SLC_APBWIN_WR_V << SLCHOST_SLC_APBWIN_WR_S)
+#define SLCHOST_SLC_APBWIN_WR_V  0x00000001U
+#define SLCHOST_SLC_APBWIN_WR_S  28
+/** SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_START    (BIT(29))
+#define SLCHOST_SLC_APBWIN_START_M  (SLCHOST_SLC_APBWIN_START_V << SLCHOST_SLC_APBWIN_START_S)
+#define SLCHOST_SLC_APBWIN_START_V  0x00000001U
+#define SLCHOST_SLC_APBWIN_START_S  29
+
+/** SLCHOST_SLC_APBWIN_RDATA_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108)
+/** SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC_APBWIN_RDATA    0xFFFFFFFFU
+#define SLCHOST_SLC_APBWIN_RDATA_M  (SLCHOST_SLC_APBWIN_RDATA_V << SLCHOST_SLC_APBWIN_RDATA_S)
+#define SLCHOST_SLC_APBWIN_RDATA_V  0xFFFFFFFFU
+#define SLCHOST_SLC_APBWIN_RDATA_S  0
+
+/** SLCHOST_RDCLR0_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10c)
+/** SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR    0x000001FFU
+#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M  (SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S)
+#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V  0x000001FFU
+#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S  0
+/** SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR    0x000001FFU
+#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M  (SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S)
+#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V  0x000001FFU
+#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S  9
+
+/** SLCHOST_RDCLR1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110)
+/** SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR    0x000001FFU
+#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M  (SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S)
+#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V  0x000001FFU
+#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S  0
+/** SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR    0x000001FFU
+#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M  (SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S)
+#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V  0x000001FFU
+#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S  9
+
+/** SLCHOST_SLC0HOST_INT_ENA1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114)
+/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1    (BIT(0))
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S  0
+/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1    (BIT(1))
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S  1
+/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1    (BIT(2))
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S  2
+/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1    (BIT(3))
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S  3
+/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1    (BIT(4))
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S  4
+/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1    (BIT(5))
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S  5
+/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1    (BIT(6))
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S  6
+/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1    (BIT(7))
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S)
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S  7
+/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(8))
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S)
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S  8
+/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(9))
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S)
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S  9
+/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1    (BIT(10))
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S)
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S  10
+/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1    (BIT(11))
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S)
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S  11
+/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1    (BIT(12))
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S)
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S  12
+/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1    (BIT(13))
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S)
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S  13
+/** SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA1    (BIT(14))
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SLCHOST_SLC0HOST_RX_START_INT_ENA1_S)
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_S  14
+/** SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA1    (BIT(15))
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_M  (SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SLCHOST_SLC0HOST_TX_START_INT_ENA1_S)
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_S  15
+/** SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_UDF_INT_ENA1    (BIT(16))
+#define SLCHOST_SLC0_RX_UDF_INT_ENA1_M  (SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SLCHOST_SLC0_RX_UDF_INT_ENA1_S)
+#define SLCHOST_SLC0_RX_UDF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_RX_UDF_INT_ENA1_S  16
+/** SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_TX_OVF_INT_ENA1    (BIT(17))
+#define SLCHOST_SLC0_TX_OVF_INT_ENA1_M  (SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SLCHOST_SLC0_TX_OVF_INT_ENA1_S)
+#define SLCHOST_SLC0_TX_OVF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_TX_OVF_INT_ENA1_S  17
+/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1    (BIT(18))
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S)
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S  18
+/** SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1    (BIT(19))
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S)
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S  19
+/** SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1    (BIT(20))
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S)
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S  20
+/** SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1    (BIT(21))
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S)
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S  21
+/** SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1    (BIT(22))
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S)
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S  22
+/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1    (BIT(23))
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S)
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S  23
+/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1    (BIT(24))
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S)
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S  24
+/** SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_GPIO_SDIO_INT_ENA1    (BIT(25))
+#define SLCHOST_GPIO_SDIO_INT_ENA1_M  (SLCHOST_GPIO_SDIO_INT_ENA1_V << SLCHOST_GPIO_SDIO_INT_ENA1_S)
+#define SLCHOST_GPIO_SDIO_INT_ENA1_V  0x00000001U
+#define SLCHOST_GPIO_SDIO_INT_ENA1_S  25
+
+/** SLCHOST_SLC1HOST_INT_ENA1_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118)
+/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1    (BIT(0))
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S  0
+/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1    (BIT(1))
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S  1
+/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1    (BIT(2))
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S  2
+/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1    (BIT(3))
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S  3
+/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1    (BIT(4))
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S  4
+/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1    (BIT(5))
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S  5
+/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1    (BIT(6))
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S  6
+/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1    (BIT(7))
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S)
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S  7
+/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1    (BIT(8))
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S)
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S  8
+/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1    (BIT(9))
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S)
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S  9
+/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1    (BIT(10))
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S)
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S  10
+/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1    (BIT(11))
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S)
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S  11
+/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1    (BIT(12))
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S)
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S  12
+/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1    (BIT(13))
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S)
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S  13
+/** SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA1    (BIT(14))
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SLCHOST_SLC1HOST_RX_START_INT_ENA1_S)
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_S  14
+/** SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA1    (BIT(15))
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_M  (SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SLCHOST_SLC1HOST_TX_START_INT_ENA1_S)
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_S  15
+/** SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_UDF_INT_ENA1    (BIT(16))
+#define SLCHOST_SLC1_RX_UDF_INT_ENA1_M  (SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SLCHOST_SLC1_RX_UDF_INT_ENA1_S)
+#define SLCHOST_SLC1_RX_UDF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_RX_UDF_INT_ENA1_S  16
+/** SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_TX_OVF_INT_ENA1    (BIT(17))
+#define SLCHOST_SLC1_TX_OVF_INT_ENA1_M  (SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SLCHOST_SLC1_TX_OVF_INT_ENA1_S)
+#define SLCHOST_SLC1_TX_OVF_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_TX_OVF_INT_ENA1_S  17
+/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1    (BIT(18))
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S)
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S  18
+/** SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1    (BIT(19))
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S)
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S  19
+/** SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1    (BIT(20))
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S)
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S  20
+/** SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1    (BIT(21))
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S)
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S  21
+/** SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1    (BIT(22))
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S)
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S  22
+/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1    (BIT(23))
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S)
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S  23
+/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1    (BIT(24))
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S)
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S  24
+/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1    (BIT(25))
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S)
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
+#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S  25
+
+/** SLCHOST_SLCHOSTDATE_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178)
+/** SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_DATE    0xFFFFFFFFU
+#define SLCHOST_SLCHOST_DATE_M  (SLCHOST_SLCHOST_DATE_V << SLCHOST_SLCHOST_DATE_S)
+#define SLCHOST_SLCHOST_DATE_V  0xFFFFFFFFU
+#define SLCHOST_SLCHOST_DATE_S  0
+
+/** SLCHOST_SLCHOSTID_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17c)
+/** SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536;
+ *  *******Description***********
+ */
+#define SLCHOST_SLCHOST_ID    0xFFFFFFFFU
+#define SLCHOST_SLCHOST_ID_M  (SLCHOST_SLCHOST_ID_V << SLCHOST_SLCHOST_ID_S)
+#define SLCHOST_SLCHOST_ID_V  0xFFFFFFFFU
+#define SLCHOST_SLCHOST_ID_S  0
+
+/** SLCHOST_CONF_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1f0)
+/** SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FRC_SDIO11    0x0000001FU
+#define SLCHOST_FRC_SDIO11_M  (SLCHOST_FRC_SDIO11_V << SLCHOST_FRC_SDIO11_S)
+#define SLCHOST_FRC_SDIO11_V  0x0000001FU
+#define SLCHOST_FRC_SDIO11_S  0
+/** SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FRC_SDIO20    0x0000001FU
+#define SLCHOST_FRC_SDIO20_M  (SLCHOST_FRC_SDIO20_V << SLCHOST_FRC_SDIO20_S)
+#define SLCHOST_FRC_SDIO20_V  0x0000001FU
+#define SLCHOST_FRC_SDIO20_S  5
+/** SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FRC_NEG_SAMP    0x0000001FU
+#define SLCHOST_FRC_NEG_SAMP_M  (SLCHOST_FRC_NEG_SAMP_V << SLCHOST_FRC_NEG_SAMP_S)
+#define SLCHOST_FRC_NEG_SAMP_V  0x0000001FU
+#define SLCHOST_FRC_NEG_SAMP_S  10
+/** SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FRC_POS_SAMP    0x0000001FU
+#define SLCHOST_FRC_POS_SAMP_M  (SLCHOST_FRC_POS_SAMP_V << SLCHOST_FRC_POS_SAMP_S)
+#define SLCHOST_FRC_POS_SAMP_V  0x0000001FU
+#define SLCHOST_FRC_POS_SAMP_S  15
+/** SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_FRC_QUICK_IN    0x0000001FU
+#define SLCHOST_FRC_QUICK_IN_M  (SLCHOST_FRC_QUICK_IN_V << SLCHOST_FRC_QUICK_IN_S)
+#define SLCHOST_FRC_QUICK_IN_V  0x0000001FU
+#define SLCHOST_FRC_QUICK_IN_S  20
+/** SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SDIO20_INT_DELAY    (BIT(25))
+#define SLCHOST_SDIO20_INT_DELAY_M  (SLCHOST_SDIO20_INT_DELAY_V << SLCHOST_SDIO20_INT_DELAY_S)
+#define SLCHOST_SDIO20_INT_DELAY_V  0x00000001U
+#define SLCHOST_SDIO20_INT_DELAY_S  25
+/** SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SDIO_PAD_PULLUP    (BIT(26))
+#define SLCHOST_SDIO_PAD_PULLUP_M  (SLCHOST_SDIO_PAD_PULLUP_V << SLCHOST_SDIO_PAD_PULLUP_S)
+#define SLCHOST_SDIO_PAD_PULLUP_V  0x00000001U
+#define SLCHOST_SDIO_PAD_PULLUP_S  26
+/** SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_HSPEED_CON_EN    (BIT(27))
+#define SLCHOST_HSPEED_CON_EN_M  (SLCHOST_HSPEED_CON_EN_V << SLCHOST_HSPEED_CON_EN_S)
+#define SLCHOST_HSPEED_CON_EN_V  0x00000001U
+#define SLCHOST_HSPEED_CON_EN_S  27
+
+/** SLCHOST_INF_ST_REG register
+ *  *******Description***********
+ */
+#define SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1f4)
+/** SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SDIO20_MODE    0x0000001FU
+#define SLCHOST_SDIO20_MODE_M  (SLCHOST_SDIO20_MODE_V << SLCHOST_SDIO20_MODE_S)
+#define SLCHOST_SDIO20_MODE_V  0x0000001FU
+#define SLCHOST_SDIO20_MODE_S  0
+/** SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SDIO_NEG_SAMP    0x0000001FU
+#define SLCHOST_SDIO_NEG_SAMP_M  (SLCHOST_SDIO_NEG_SAMP_V << SLCHOST_SDIO_NEG_SAMP_S)
+#define SLCHOST_SDIO_NEG_SAMP_V  0x0000001FU
+#define SLCHOST_SDIO_NEG_SAMP_S  5
+/** SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0;
+ *  *******Description***********
+ */
+#define SLCHOST_SDIO_QUICK_IN    0x0000001FU
+#define SLCHOST_SDIO_QUICK_IN_M  (SLCHOST_SDIO_QUICK_IN_V << SLCHOST_SDIO_QUICK_IN_S)
+#define SLCHOST_SDIO_QUICK_IN_V  0x0000001FU
+#define SLCHOST_SDIO_QUICK_IN_S  10
+/** SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0;
+ *  dll is controlled by software
+ */
+#define SLCHOST_DLL_ON_SW    (BIT(15))
+#define SLCHOST_DLL_ON_SW_M  (SLCHOST_DLL_ON_SW_V << SLCHOST_DLL_ON_SW_S)
+#define SLCHOST_DLL_ON_SW_V  0x00000001U
+#define SLCHOST_DLL_ON_SW_S  15
+/** SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0;
+ *  Software dll on
+ */
+#define SLCHOST_DLL_ON    (BIT(16))
+#define SLCHOST_DLL_ON_M  (SLCHOST_DLL_ON_V << SLCHOST_DLL_ON_S)
+#define SLCHOST_DLL_ON_V  0x00000001U
+#define SLCHOST_DLL_ON_S  16
+/** SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0;
+ *  dll clock mode is controlled by software
+ */
+#define SLCHOST_CLK_MODE_SW    (BIT(17))
+#define SLCHOST_CLK_MODE_SW_M  (SLCHOST_CLK_MODE_SW_V << SLCHOST_CLK_MODE_SW_S)
+#define SLCHOST_CLK_MODE_SW_V  0x00000001U
+#define SLCHOST_CLK_MODE_SW_S  17
+/** SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0;
+ *  Software set clock mode
+ */
+#define SLCHOST_CLK_MODE    0x00000003U
+#define SLCHOST_CLK_MODE_M  (SLCHOST_CLK_MODE_V << SLCHOST_CLK_MODE_S)
+#define SLCHOST_CLK_MODE_V  0x00000003U
+#define SLCHOST_CLK_MODE_S  18
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/host_struct.h b/components/soc/esp32p4/include/soc/host_struct.h
new file mode 100644
index 0000000000..275e30e72f
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/host_struct.h
@@ -0,0 +1,2738 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ********Registers */
+/** Type of func2_0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** slc_func2_int : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc_func2_int:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} slchost_func2_0_reg_t;
+
+/** Type of func2_1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc_func2_int_en : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc_func2_int_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} slchost_func2_1_reg_t;
+
+/** Type of func2_2 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc_func1_mdstat : R/W; bitpos: [0]; default: 1;
+         *  *******Description***********
+         */
+        uint32_t slc_func1_mdstat:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} slchost_func2_2_reg_t;
+
+/** Type of gpio_status0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_int0:32;
+    };
+    uint32_t val;
+} slchost_gpio_status0_reg_t;
+
+/** Type of gpio_status1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_int1:32;
+    };
+    uint32_t val;
+} slchost_gpio_status1_reg_t;
+
+/** Type of gpio_in0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_in0:32;
+    };
+    uint32_t val;
+} slchost_gpio_in0_reg_t;
+
+/** Type of gpio_in1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_in1:32;
+    };
+    uint32_t val;
+} slchost_gpio_in1_reg_t;
+
+/** Type of slc0host_token_rdata register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0_token0 : RO; bitpos: [11:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0:12;
+        /** slc0_rx_pf_valid : RO; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_pf_valid:1;
+        uint32_t reserved_13:3;
+        /** hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_token1:12;
+        /** slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_pf_eof:4;
+    };
+    uint32_t val;
+} slchost_slc0host_token_rdata_reg_t;
+
+/** Type of slc0_host_pf register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0_pf_data : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_pf_data:32;
+    };
+    uint32_t val;
+} slchost_slc0_host_pf_reg_t;
+
+/** Type of slc1_host_pf register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1_pf_data : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_pf_data:32;
+    };
+    uint32_t val;
+} slchost_slc1_host_pf_reg_t;
+
+/** Type of slc0host_int_raw register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit0_int_raw:1;
+        /** slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit1_int_raw:1;
+        /** slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit2_int_raw:1;
+        /** slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit3_int_raw:1;
+        /** slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit4_int_raw:1;
+        /** slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit5_int_raw:1;
+        /** slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit6_int_raw:1;
+        /** slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit7_int_raw:1;
+        /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_1to0_int_raw:1;
+        /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_1to0_int_raw:1;
+        /** slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_0to1_int_raw:1;
+        /** slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_0to1_int_raw:1;
+        /** slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_sof_int_raw:1;
+        /** slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_eof_int_raw:1;
+        /** slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_start_int_raw:1;
+        /** slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_tx_start_int_raw:1;
+        /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_udf_int_raw:1;
+        /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tx_ovf_int_raw:1;
+        /** slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_pf_valid_int_raw:1;
+        /** slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit0_int_raw:1;
+        /** slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit1_int_raw:1;
+        /** slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit2_int_raw:1;
+        /** slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit3_int_raw:1;
+        /** slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_new_packet_int_raw:1;
+        /** slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_host_rd_retry_int_raw:1;
+        /** gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_int_raw:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc0host_int_raw_reg_t;
+
+/** Type of slc1host_int_raw register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit0_int_raw:1;
+        /** slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit1_int_raw:1;
+        /** slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit2_int_raw:1;
+        /** slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit3_int_raw:1;
+        /** slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit4_int_raw:1;
+        /** slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit5_int_raw:1;
+        /** slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit6_int_raw:1;
+        /** slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit7_int_raw:1;
+        /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_1to0_int_raw:1;
+        /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_1to0_int_raw:1;
+        /** slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_0to1_int_raw:1;
+        /** slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_0to1_int_raw:1;
+        /** slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_sof_int_raw:1;
+        /** slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_eof_int_raw:1;
+        /** slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_start_int_raw:1;
+        /** slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_tx_start_int_raw:1;
+        /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_udf_int_raw:1;
+        /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tx_ovf_int_raw:1;
+        /** slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_pf_valid_int_raw:1;
+        /** slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit0_int_raw:1;
+        /** slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit1_int_raw:1;
+        /** slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit2_int_raw:1;
+        /** slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit3_int_raw:1;
+        /** slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_wifi_rx_new_packet_int_raw:1;
+        /** slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_host_rd_retry_int_raw:1;
+        /** slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_bt_rx_new_packet_int_raw:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc1host_int_raw_reg_t;
+
+/** Type of slc0host_int_st register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit0_int_st:1;
+        /** slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit1_int_st:1;
+        /** slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit2_int_st:1;
+        /** slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit3_int_st:1;
+        /** slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit4_int_st:1;
+        /** slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit5_int_st:1;
+        /** slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit6_int_st:1;
+        /** slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit7_int_st:1;
+        /** slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_1to0_int_st:1;
+        /** slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_1to0_int_st:1;
+        /** slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_0to1_int_st:1;
+        /** slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_0to1_int_st:1;
+        /** slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_sof_int_st:1;
+        /** slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_eof_int_st:1;
+        /** slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_start_int_st:1;
+        /** slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_tx_start_int_st:1;
+        /** slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_udf_int_st:1;
+        /** slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tx_ovf_int_st:1;
+        /** slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_pf_valid_int_st:1;
+        /** slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit0_int_st:1;
+        /** slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit1_int_st:1;
+        /** slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit2_int_st:1;
+        /** slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit3_int_st:1;
+        /** slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_new_packet_int_st:1;
+        /** slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_host_rd_retry_int_st:1;
+        /** gpio_sdio_int_st : RO; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_int_st:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc0host_int_st_reg_t;
+
+/** Type of slc1host_int_st register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit0_int_st:1;
+        /** slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit1_int_st:1;
+        /** slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit2_int_st:1;
+        /** slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit3_int_st:1;
+        /** slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit4_int_st:1;
+        /** slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit5_int_st:1;
+        /** slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit6_int_st:1;
+        /** slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit7_int_st:1;
+        /** slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_1to0_int_st:1;
+        /** slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_1to0_int_st:1;
+        /** slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_0to1_int_st:1;
+        /** slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_0to1_int_st:1;
+        /** slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_sof_int_st:1;
+        /** slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_eof_int_st:1;
+        /** slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_start_int_st:1;
+        /** slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_tx_start_int_st:1;
+        /** slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_udf_int_st:1;
+        /** slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tx_ovf_int_st:1;
+        /** slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_pf_valid_int_st:1;
+        /** slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit0_int_st:1;
+        /** slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit1_int_st:1;
+        /** slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit2_int_st:1;
+        /** slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit3_int_st:1;
+        /** slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_wifi_rx_new_packet_int_st:1;
+        /** slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_host_rd_retry_int_st:1;
+        /** slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_bt_rx_new_packet_int_st:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc1host_int_st_reg_t;
+
+/** Type of pkt_len register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len:20;
+        /** hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len_check:12;
+    };
+    uint32_t val;
+} slchost_pkt_len_reg_t;
+
+/** Type of state_w0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_state0 : RO; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state0:8;
+        /** slchost_state1 : RO; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state1:8;
+        /** slchost_state2 : RO; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state2:8;
+        /** slchost_state3 : RO; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state3:8;
+    };
+    uint32_t val;
+} slchost_state_w0_reg_t;
+
+/** Type of state_w1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_state4 : RO; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state4:8;
+        /** slchost_state5 : RO; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state5:8;
+        /** slchost_state6 : RO; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state6:8;
+        /** slchost_state7 : RO; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_state7:8;
+    };
+    uint32_t val;
+} slchost_state_w1_reg_t;
+
+/** Type of conf_w0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf0 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf0:8;
+        /** slchost_conf1 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf1:8;
+        /** slchost_conf2 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf2:8;
+        /** slchost_conf3 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf3:8;
+    };
+    uint32_t val;
+} slchost_conf_w0_reg_t;
+
+/** Type of conf_w1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf4 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf4:8;
+        /** slchost_conf5 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf5:8;
+        /** slchost_conf6 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf6:8;
+        /** slchost_conf7 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf7:8;
+    };
+    uint32_t val;
+} slchost_conf_w1_reg_t;
+
+/** Type of conf_w2 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf8 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf8:8;
+        /** slchost_conf9 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf9:8;
+        /** slchost_conf10 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf10:8;
+        /** slchost_conf11 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf11:8;
+    };
+    uint32_t val;
+} slchost_conf_w2_reg_t;
+
+/** Type of conf_w3 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf12 : R/W; bitpos: [7:0]; default: 192;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf12:8;
+        /** slchost_conf13 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf13:8;
+        /** slchost_conf14 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf14:8;
+        /** slchost_conf15 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf15:8;
+    };
+    uint32_t val;
+} slchost_conf_w3_reg_t;
+
+/** Type of conf_w4 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf16 : R/W; bitpos: [7:0]; default: 255;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf16:8;
+        /** slchost_conf17 : R/W; bitpos: [15:8]; default: 1;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf17:8;
+        /** slchost_conf18 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf18:8;
+        /** slchost_conf19 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf19:8;
+    };
+    uint32_t val;
+} slchost_conf_w4_reg_t;
+
+/** Type of conf_w5 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf20 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf20:8;
+        /** slchost_conf21 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf21:8;
+        /** slchost_conf22 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf22:8;
+        /** slchost_conf23 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf23:8;
+    };
+    uint32_t val;
+} slchost_conf_w5_reg_t;
+
+/** Type of win_cmd register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_win_cmd : R/W; bitpos: [15:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_win_cmd:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} slchost_win_cmd_reg_t;
+
+/** Type of conf_w6 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf24 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf24:8;
+        /** slchost_conf25 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf25:8;
+        /** slchost_conf26 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf26:8;
+        /** slchost_conf27 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf27:8;
+    };
+    uint32_t val;
+} slchost_conf_w6_reg_t;
+
+/** Type of conf_w7 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf28 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf28:8;
+        /** slchost_conf29 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf29:8;
+        /** slchost_conf30 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf30:8;
+        /** slchost_conf31 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf31:8;
+    };
+    uint32_t val;
+} slchost_conf_w7_reg_t;
+
+/** Type of pkt_len0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len0:20;
+        /** hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len0_check:12;
+    };
+    uint32_t val;
+} slchost_pkt_len0_reg_t;
+
+/** Type of pkt_len1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len1:20;
+        /** hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len1_check:12;
+    };
+    uint32_t val;
+} slchost_pkt_len1_reg_t;
+
+/** Type of pkt_len2 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len2:20;
+        /** hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc0_len2_check:12;
+    };
+    uint32_t val;
+} slchost_pkt_len2_reg_t;
+
+/** Type of conf_w8 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf32 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf32:8;
+        /** slchost_conf33 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf33:8;
+        /** slchost_conf34 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf34:8;
+        /** slchost_conf35 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf35:8;
+    };
+    uint32_t val;
+} slchost_conf_w8_reg_t;
+
+/** Type of conf_w9 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf36 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf36:8;
+        /** slchost_conf37 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf37:8;
+        /** slchost_conf38 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf38:8;
+        /** slchost_conf39 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf39:8;
+    };
+    uint32_t val;
+} slchost_conf_w9_reg_t;
+
+/** Type of conf_w10 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf40 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf40:8;
+        /** slchost_conf41 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf41:8;
+        /** slchost_conf42 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf42:8;
+        /** slchost_conf43 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf43:8;
+    };
+    uint32_t val;
+} slchost_conf_w10_reg_t;
+
+/** Type of conf_w11 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf44 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf44:8;
+        /** slchost_conf45 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf45:8;
+        /** slchost_conf46 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf46:8;
+        /** slchost_conf47 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf47:8;
+    };
+    uint32_t val;
+} slchost_conf_w11_reg_t;
+
+/** Type of conf_w12 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf48 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf48:8;
+        /** slchost_conf49 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf49:8;
+        /** slchost_conf50 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf50:8;
+        /** slchost_conf51 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf51:8;
+    };
+    uint32_t val;
+} slchost_conf_w12_reg_t;
+
+/** Type of conf_w13 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf52 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf52:8;
+        /** slchost_conf53 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf53:8;
+        /** slchost_conf54 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf54:8;
+        /** slchost_conf55 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf55:8;
+    };
+    uint32_t val;
+} slchost_conf_w13_reg_t;
+
+/** Type of conf_w14 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf56 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf56:8;
+        /** slchost_conf57 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf57:8;
+        /** slchost_conf58 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf58:8;
+        /** slchost_conf59 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf59:8;
+    };
+    uint32_t val;
+} slchost_conf_w14_reg_t;
+
+/** Type of conf_w15 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_conf60 : R/W; bitpos: [7:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf60:8;
+        /** slchost_conf61 : R/W; bitpos: [15:8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf61:8;
+        /** slchost_conf62 : R/W; bitpos: [23:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf62:8;
+        /** slchost_conf63 : R/W; bitpos: [31:24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_conf63:8;
+    };
+    uint32_t val;
+} slchost_conf_w15_reg_t;
+
+/** Type of check_sum0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_check_sum0 : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slchost_check_sum0:32;
+    };
+    uint32_t val;
+} slchost_check_sum0_reg_t;
+
+/** Type of check_sum1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_check_sum1 : RO; bitpos: [31:0]; default: 319;
+         *  *******Description***********
+         */
+        uint32_t slchost_check_sum1:32;
+    };
+    uint32_t val;
+} slchost_check_sum1_reg_t;
+
+/** Type of slc1host_token_rdata register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1_token0 : RO; bitpos: [11:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0:12;
+        /** slc1_rx_pf_valid : RO; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_pf_valid:1;
+        uint32_t reserved_13:3;
+        /** hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hostslchost_slc1_token1:12;
+        /** slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_pf_eof:4;
+    };
+    uint32_t val;
+} slchost_slc1host_token_rdata_reg_t;
+
+/** Type of slc0host_token_wdata register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_token0_wd:12;
+        uint32_t reserved_12:4;
+        /** slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_token1_wd:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} slchost_slc0host_token_wdata_reg_t;
+
+/** Type of slc1host_token_wdata register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_token0_wd:12;
+        uint32_t reserved_12:4;
+        /** slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_token1_wd:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} slchost_slc1host_token_wdata_reg_t;
+
+/** Type of token_con register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0host_token0_dec : WT; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_token0_dec:1;
+        /** slc0host_token1_dec : WT; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_token1_dec:1;
+        /** slc0host_token0_wr : WT; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_token0_wr:1;
+        /** slc0host_token1_wr : WT; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_token1_wr:1;
+        /** slc1host_token0_dec : WT; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_token0_dec:1;
+        /** slc1host_token1_dec : WT; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_token1_dec:1;
+        /** slc1host_token0_wr : WT; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_token0_wr:1;
+        /** slc1host_token1_wr : WT; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_token1_wr:1;
+        /** slc0host_len_wr : WT; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_len_wr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} slchost_token_con_reg_t;
+
+/** Type of slc0host_int_clr register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit0_int_clr:1;
+        /** slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit1_int_clr:1;
+        /** slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit2_int_clr:1;
+        /** slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit3_int_clr:1;
+        /** slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit4_int_clr:1;
+        /** slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit5_int_clr:1;
+        /** slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit6_int_clr:1;
+        /** slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit7_int_clr:1;
+        /** slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_1to0_int_clr:1;
+        /** slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_1to0_int_clr:1;
+        /** slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_0to1_int_clr:1;
+        /** slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_0to1_int_clr:1;
+        /** slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_sof_int_clr:1;
+        /** slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_eof_int_clr:1;
+        /** slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_start_int_clr:1;
+        /** slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_tx_start_int_clr:1;
+        /** slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_udf_int_clr:1;
+        /** slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tx_ovf_int_clr:1;
+        /** slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_pf_valid_int_clr:1;
+        /** slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit0_int_clr:1;
+        /** slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit1_int_clr:1;
+        /** slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit2_int_clr:1;
+        /** slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit3_int_clr:1;
+        /** slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_new_packet_int_clr:1;
+        /** slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_host_rd_retry_int_clr:1;
+        /** gpio_sdio_int_clr : WT; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_int_clr:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc0host_int_clr_reg_t;
+
+/** Type of slc1host_int_clr register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit0_int_clr:1;
+        /** slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit1_int_clr:1;
+        /** slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit2_int_clr:1;
+        /** slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit3_int_clr:1;
+        /** slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit4_int_clr:1;
+        /** slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit5_int_clr:1;
+        /** slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit6_int_clr:1;
+        /** slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit7_int_clr:1;
+        /** slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_1to0_int_clr:1;
+        /** slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_1to0_int_clr:1;
+        /** slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_0to1_int_clr:1;
+        /** slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_0to1_int_clr:1;
+        /** slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_sof_int_clr:1;
+        /** slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_eof_int_clr:1;
+        /** slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_start_int_clr:1;
+        /** slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_tx_start_int_clr:1;
+        /** slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_udf_int_clr:1;
+        /** slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tx_ovf_int_clr:1;
+        /** slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_pf_valid_int_clr:1;
+        /** slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit0_int_clr:1;
+        /** slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit1_int_clr:1;
+        /** slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit2_int_clr:1;
+        /** slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit3_int_clr:1;
+        /** slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_wifi_rx_new_packet_int_clr:1;
+        /** slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_host_rd_retry_int_clr:1;
+        /** slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_bt_rx_new_packet_int_clr:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc1host_int_clr_reg_t;
+
+/** Type of slc0host_func1_int_ena register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit0_int_ena:1;
+        /** fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit1_int_ena:1;
+        /** fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit2_int_ena:1;
+        /** fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit3_int_ena:1;
+        /** fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit4_int_ena:1;
+        /** fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit5_int_ena:1;
+        /** fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit6_int_ena:1;
+        /** fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tohost_bit7_int_ena:1;
+        /** fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_token0_1to0_int_ena:1;
+        /** fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_token1_1to0_int_ena:1;
+        /** fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_token0_0to1_int_ena:1;
+        /** fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_token1_0to1_int_ena:1;
+        /** fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0host_rx_sof_int_ena:1;
+        /** fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0host_rx_eof_int_ena:1;
+        /** fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0host_rx_start_int_ena:1;
+        /** fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0host_tx_start_int_ena:1;
+        /** fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_rx_udf_int_ena:1;
+        /** fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_tx_ovf_int_ena:1;
+        /** fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_rx_pf_valid_int_ena:1;
+        /** fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_ext_bit0_int_ena:1;
+        /** fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_ext_bit1_int_ena:1;
+        /** fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_ext_bit2_int_ena:1;
+        /** fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_ext_bit3_int_ena:1;
+        /** fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_rx_new_packet_int_ena:1;
+        /** fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc0_host_rd_retry_int_ena:1;
+        /** fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_gpio_sdio_int_ena:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc0host_func1_int_ena_reg_t;
+
+/** Type of slc1host_func1_int_ena register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit0_int_ena:1;
+        /** fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit1_int_ena:1;
+        /** fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit2_int_ena:1;
+        /** fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit3_int_ena:1;
+        /** fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit4_int_ena:1;
+        /** fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit5_int_ena:1;
+        /** fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit6_int_ena:1;
+        /** fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tohost_bit7_int_ena:1;
+        /** fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_token0_1to0_int_ena:1;
+        /** fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_token1_1to0_int_ena:1;
+        /** fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_token0_0to1_int_ena:1;
+        /** fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_token1_0to1_int_ena:1;
+        /** fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1host_rx_sof_int_ena:1;
+        /** fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1host_rx_eof_int_ena:1;
+        /** fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1host_rx_start_int_ena:1;
+        /** fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1host_tx_start_int_ena:1;
+        /** fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_rx_udf_int_ena:1;
+        /** fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_tx_ovf_int_ena:1;
+        /** fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_rx_pf_valid_int_ena:1;
+        /** fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_ext_bit0_int_ena:1;
+        /** fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_ext_bit1_int_ena:1;
+        /** fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_ext_bit2_int_ena:1;
+        /** fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_ext_bit3_int_ena:1;
+        /** fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_wifi_rx_new_packet_int_ena:1;
+        /** fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_host_rd_retry_int_ena:1;
+        /** fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn1_slc1_bt_rx_new_packet_int_ena:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc1host_func1_int_ena_reg_t;
+
+/** Type of slc0host_func2_int_ena register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit0_int_ena:1;
+        /** fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit1_int_ena:1;
+        /** fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit2_int_ena:1;
+        /** fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit3_int_ena:1;
+        /** fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit4_int_ena:1;
+        /** fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit5_int_ena:1;
+        /** fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit6_int_ena:1;
+        /** fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tohost_bit7_int_ena:1;
+        /** fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_token0_1to0_int_ena:1;
+        /** fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_token1_1to0_int_ena:1;
+        /** fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_token0_0to1_int_ena:1;
+        /** fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_token1_0to1_int_ena:1;
+        /** fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0host_rx_sof_int_ena:1;
+        /** fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0host_rx_eof_int_ena:1;
+        /** fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0host_rx_start_int_ena:1;
+        /** fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0host_tx_start_int_ena:1;
+        /** fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_rx_udf_int_ena:1;
+        /** fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_tx_ovf_int_ena:1;
+        /** fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_rx_pf_valid_int_ena:1;
+        /** fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_ext_bit0_int_ena:1;
+        /** fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_ext_bit1_int_ena:1;
+        /** fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_ext_bit2_int_ena:1;
+        /** fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_ext_bit3_int_ena:1;
+        /** fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_rx_new_packet_int_ena:1;
+        /** fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc0_host_rd_retry_int_ena:1;
+        /** fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_gpio_sdio_int_ena:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc0host_func2_int_ena_reg_t;
+
+/** Type of slc1host_func2_int_ena register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit0_int_ena:1;
+        /** fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit1_int_ena:1;
+        /** fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit2_int_ena:1;
+        /** fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit3_int_ena:1;
+        /** fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit4_int_ena:1;
+        /** fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit5_int_ena:1;
+        /** fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit6_int_ena:1;
+        /** fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tohost_bit7_int_ena:1;
+        /** fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_token0_1to0_int_ena:1;
+        /** fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_token1_1to0_int_ena:1;
+        /** fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_token0_0to1_int_ena:1;
+        /** fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_token1_0to1_int_ena:1;
+        /** fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1host_rx_sof_int_ena:1;
+        /** fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1host_rx_eof_int_ena:1;
+        /** fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1host_rx_start_int_ena:1;
+        /** fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1host_tx_start_int_ena:1;
+        /** fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_rx_udf_int_ena:1;
+        /** fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_tx_ovf_int_ena:1;
+        /** fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_rx_pf_valid_int_ena:1;
+        /** fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_ext_bit0_int_ena:1;
+        /** fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_ext_bit1_int_ena:1;
+        /** fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_ext_bit2_int_ena:1;
+        /** fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_ext_bit3_int_ena:1;
+        /** fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_wifi_rx_new_packet_int_ena:1;
+        /** fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_host_rd_retry_int_ena:1;
+        /** fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t fn2_slc1_bt_rx_new_packet_int_ena:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc1host_func2_int_ena_reg_t;
+
+/** Type of slc0host_int_ena register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit0_int_ena:1;
+        /** slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit1_int_ena:1;
+        /** slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit2_int_ena:1;
+        /** slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit3_int_ena:1;
+        /** slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit4_int_ena:1;
+        /** slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit5_int_ena:1;
+        /** slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit6_int_ena:1;
+        /** slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit7_int_ena:1;
+        /** slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_1to0_int_ena:1;
+        /** slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_1to0_int_ena:1;
+        /** slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_0to1_int_ena:1;
+        /** slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_0to1_int_ena:1;
+        /** slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_sof_int_ena:1;
+        /** slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_eof_int_ena:1;
+        /** slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_start_int_ena:1;
+        /** slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_tx_start_int_ena:1;
+        /** slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_udf_int_ena:1;
+        /** slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tx_ovf_int_ena:1;
+        /** slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_pf_valid_int_ena:1;
+        /** slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit0_int_ena:1;
+        /** slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit1_int_ena:1;
+        /** slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit2_int_ena:1;
+        /** slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit3_int_ena:1;
+        /** slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_new_packet_int_ena:1;
+        /** slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_host_rd_retry_int_ena:1;
+        /** gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_int_ena:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc0host_int_ena_reg_t;
+
+/** Type of slc1host_int_ena register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit0_int_ena:1;
+        /** slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit1_int_ena:1;
+        /** slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit2_int_ena:1;
+        /** slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit3_int_ena:1;
+        /** slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit4_int_ena:1;
+        /** slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit5_int_ena:1;
+        /** slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit6_int_ena:1;
+        /** slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit7_int_ena:1;
+        /** slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_1to0_int_ena:1;
+        /** slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_1to0_int_ena:1;
+        /** slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_0to1_int_ena:1;
+        /** slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_0to1_int_ena:1;
+        /** slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_sof_int_ena:1;
+        /** slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_eof_int_ena:1;
+        /** slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_start_int_ena:1;
+        /** slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_tx_start_int_ena:1;
+        /** slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_udf_int_ena:1;
+        /** slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tx_ovf_int_ena:1;
+        /** slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_pf_valid_int_ena:1;
+        /** slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit0_int_ena:1;
+        /** slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit1_int_ena:1;
+        /** slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit2_int_ena:1;
+        /** slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit3_int_ena:1;
+        /** slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_wifi_rx_new_packet_int_ena:1;
+        /** slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_host_rd_retry_int_ena:1;
+        /** slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_bt_rx_new_packet_int_ena:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc1host_int_ena_reg_t;
+
+/** Type of slc0host_rx_infor register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_infor:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} slchost_slc0host_rx_infor_reg_t;
+
+/** Type of slc1host_rx_infor register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_infor:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} slchost_slc1host_rx_infor_reg_t;
+
+/** Type of slc0host_len_wd register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0host_len_wd : R/W; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_len_wd:32;
+    };
+    uint32_t val;
+} slchost_slc0host_len_wd_reg_t;
+
+/** Type of slc_apbwin_wdata register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc_apbwin_wdata:32;
+    };
+    uint32_t val;
+} slchost_slc_apbwin_wdata_reg_t;
+
+/** Type of slc_apbwin_conf register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc_apbwin_addr:28;
+        /** slc_apbwin_wr : R/W; bitpos: [28]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc_apbwin_wr:1;
+        /** slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc_apbwin_start:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} slchost_slc_apbwin_conf_reg_t;
+
+/** Type of slc_apbwin_rdata register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc_apbwin_rdata:32;
+    };
+    uint32_t val;
+} slchost_slc_apbwin_rdata_reg_t;
+
+/** Type of rdclr0 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68;
+         *  *******Description***********
+         */
+        uint32_t slchost_slc0_bit7_clraddr:9;
+        /** slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480;
+         *  *******Description***********
+         */
+        uint32_t slchost_slc0_bit6_clraddr:9;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} slchost_rdclr0_reg_t;
+
+/** Type of rdclr1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480;
+         *  *******Description***********
+         */
+        uint32_t slchost_slc1_bit7_clraddr:9;
+        /** slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480;
+         *  *******Description***********
+         */
+        uint32_t slchost_slc1_bit6_clraddr:9;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} slchost_rdclr1_reg_t;
+
+/** Type of slc0host_int_ena1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit0_int_ena1:1;
+        /** slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit1_int_ena1:1;
+        /** slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit2_int_ena1:1;
+        /** slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit3_int_ena1:1;
+        /** slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit4_int_ena1:1;
+        /** slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit5_int_ena1:1;
+        /** slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit6_int_ena1:1;
+        /** slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tohost_bit7_int_ena1:1;
+        /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_1to0_int_ena1:1;
+        /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_1to0_int_ena1:1;
+        /** slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token0_0to1_int_ena1:1;
+        /** slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_token1_0to1_int_ena1:1;
+        /** slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_sof_int_ena1:1;
+        /** slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_eof_int_ena1:1;
+        /** slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_rx_start_int_ena1:1;
+        /** slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0host_tx_start_int_ena1:1;
+        /** slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_udf_int_ena1:1;
+        /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_tx_ovf_int_ena1:1;
+        /** slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_pf_valid_int_ena1:1;
+        /** slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit0_int_ena1:1;
+        /** slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit1_int_ena1:1;
+        /** slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit2_int_ena1:1;
+        /** slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_ext_bit3_int_ena1:1;
+        /** slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_rx_new_packet_int_ena1:1;
+        /** slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc0_host_rd_retry_int_ena1:1;
+        /** gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t gpio_sdio_int_ena1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc0host_int_ena1_reg_t;
+
+/** Type of slc1host_int_ena1 register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit0_int_ena1:1;
+        /** slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit1_int_ena1:1;
+        /** slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit2_int_ena1:1;
+        /** slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit3_int_ena1:1;
+        /** slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit4_int_ena1:1;
+        /** slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit5_int_ena1:1;
+        /** slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit6_int_ena1:1;
+        /** slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tohost_bit7_int_ena1:1;
+        /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_1to0_int_ena1:1;
+        /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_1to0_int_ena1:1;
+        /** slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token0_0to1_int_ena1:1;
+        /** slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_token1_0to1_int_ena1:1;
+        /** slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_sof_int_ena1:1;
+        /** slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_eof_int_ena1:1;
+        /** slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_rx_start_int_ena1:1;
+        /** slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1host_tx_start_int_ena1:1;
+        /** slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_udf_int_ena1:1;
+        /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_tx_ovf_int_ena1:1;
+        /** slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_rx_pf_valid_int_ena1:1;
+        /** slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit0_int_ena1:1;
+        /** slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit1_int_ena1:1;
+        /** slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit2_int_ena1:1;
+        /** slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_ext_bit3_int_ena1:1;
+        /** slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_wifi_rx_new_packet_int_ena1:1;
+        /** slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_host_rd_retry_int_ena1:1;
+        /** slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t slc1_bt_rx_new_packet_int_ena1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} slchost_slc1host_int_ena1_reg_t;
+
+/** Type of slchostdate register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_date : R/W; bitpos: [31:0]; default: 554043136;
+         *  *******Description***********
+         */
+        uint32_t slchost_date:32;
+    };
+    uint32_t val;
+} slchost_slchostdate_reg_t;
+
+/** Type of slchostid register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** slchost_id : R/W; bitpos: [31:0]; default: 1536;
+         *  *******Description***********
+         */
+        uint32_t slchost_id:32;
+    };
+    uint32_t val;
+} slchost_slchostid_reg_t;
+
+/** Type of conf register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** frc_sdio11 : R/W; bitpos: [4:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t frc_sdio11:5;
+        /** frc_sdio20 : R/W; bitpos: [9:5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t frc_sdio20:5;
+        /** frc_neg_samp : R/W; bitpos: [14:10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t frc_neg_samp:5;
+        /** frc_pos_samp : R/W; bitpos: [19:15]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t frc_pos_samp:5;
+        /** frc_quick_in : R/W; bitpos: [24:20]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t frc_quick_in:5;
+        /** sdio20_int_delay : R/W; bitpos: [25]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t sdio20_int_delay:1;
+        /** sdio_pad_pullup : R/W; bitpos: [26]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t sdio_pad_pullup:1;
+        /** hspeed_con_en : R/W; bitpos: [27]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t hspeed_con_en:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} slchost_conf_reg_t;
+
+/** Type of inf_st register
+ *  *******Description***********
+ */
+typedef union {
+    struct {
+        /** sdio20_mode : RO; bitpos: [4:0]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t sdio20_mode:5;
+        /** sdio_neg_samp : RO; bitpos: [9:5]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t sdio_neg_samp:5;
+        /** sdio_quick_in : RO; bitpos: [14:10]; default: 0;
+         *  *******Description***********
+         */
+        uint32_t sdio_quick_in:5;
+        /** dll_on_sw : R/W; bitpos: [15]; default: 0;
+         *  dll is controlled by software
+         */
+        uint32_t dll_on_sw:1;
+        /** dll_on : R/W; bitpos: [16]; default: 0;
+         *  Software dll on
+         */
+        uint32_t dll_on:1;
+        /** clk_mode_sw : R/W; bitpos: [17]; default: 0;
+         *  dll clock mode is controlled by software
+         */
+        uint32_t clk_mode_sw:1;
+        /** clk_mode : R/W; bitpos: [19:18]; default: 0;
+         *  Software set clock mode
+         */
+        uint32_t clk_mode:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} slchost_inf_st_reg_t;
+
+
+typedef struct host_dev_t {
+    uint32_t reserved_000[4];
+    volatile slchost_func2_0_reg_t func2_0;
+    volatile slchost_func2_1_reg_t func2_1;
+    uint32_t reserved_018[2];
+    volatile slchost_func2_2_reg_t func2_2;
+    uint32_t reserved_024[4];
+    volatile slchost_gpio_status0_reg_t gpio_status0;
+    volatile slchost_gpio_status1_reg_t gpio_status1;
+    volatile slchost_gpio_in0_reg_t gpio_in0;
+    volatile slchost_gpio_in1_reg_t gpio_in1;
+    volatile slchost_slc0host_token_rdata_reg_t slc0host_token_rdata;
+    volatile slchost_slc0_host_pf_reg_t slc0_host_pf;
+    volatile slchost_slc1_host_pf_reg_t slc1_host_pf;
+    volatile slchost_slc0host_int_raw_reg_t slc0host_int_raw;
+    volatile slchost_slc1host_int_raw_reg_t slc1host_int_raw;
+    volatile slchost_slc0host_int_st_reg_t slc0host_int_st;
+    volatile slchost_slc1host_int_st_reg_t slc1host_int_st;
+    volatile slchost_pkt_len_reg_t pkt_len;
+    volatile slchost_state_w0_reg_t state_w0;
+    volatile slchost_state_w1_reg_t state_w1;
+    volatile slchost_conf_w0_reg_t conf_w0;
+    volatile slchost_conf_w1_reg_t conf_w1;
+    volatile slchost_conf_w2_reg_t conf_w2;
+    volatile slchost_conf_w3_reg_t conf_w3;
+    volatile slchost_conf_w4_reg_t conf_w4;
+    volatile slchost_conf_w5_reg_t conf_w5;
+    volatile slchost_win_cmd_reg_t win_cmd;
+    volatile slchost_conf_w6_reg_t conf_w6;
+    volatile slchost_conf_w7_reg_t conf_w7;
+    volatile slchost_pkt_len0_reg_t pkt_len0;
+    volatile slchost_pkt_len1_reg_t pkt_len1;
+    volatile slchost_pkt_len2_reg_t pkt_len2;
+    volatile slchost_conf_w8_reg_t conf_w8;
+    volatile slchost_conf_w9_reg_t conf_w9;
+    volatile slchost_conf_w10_reg_t conf_w10;
+    volatile slchost_conf_w11_reg_t conf_w11;
+    volatile slchost_conf_w12_reg_t conf_w12;
+    volatile slchost_conf_w13_reg_t conf_w13;
+    volatile slchost_conf_w14_reg_t conf_w14;
+    volatile slchost_conf_w15_reg_t conf_w15;
+    volatile slchost_check_sum0_reg_t check_sum0;
+    volatile slchost_check_sum1_reg_t check_sum1;
+    volatile slchost_slc1host_token_rdata_reg_t slc1host_token_rdata;
+    volatile slchost_slc0host_token_wdata_reg_t slc0host_token_wdata;
+    volatile slchost_slc1host_token_wdata_reg_t slc1host_token_wdata;
+    volatile slchost_token_con_reg_t token_con;
+    volatile slchost_slc0host_int_clr_reg_t slc0host_int_clr;
+    volatile slchost_slc1host_int_clr_reg_t slc1host_int_clr;
+    volatile slchost_slc0host_func1_int_ena_reg_t slc0host_func1_int_ena;
+    volatile slchost_slc1host_func1_int_ena_reg_t slc1host_func1_int_ena;
+    volatile slchost_slc0host_func2_int_ena_reg_t slc0host_func2_int_ena;
+    volatile slchost_slc1host_func2_int_ena_reg_t slc1host_func2_int_ena;
+    volatile slchost_slc0host_int_ena_reg_t slc0host_int_ena;
+    volatile slchost_slc1host_int_ena_reg_t slc1host_int_ena;
+    volatile slchost_slc0host_rx_infor_reg_t slc0host_rx_infor;
+    volatile slchost_slc1host_rx_infor_reg_t slc1host_rx_infor;
+    volatile slchost_slc0host_len_wd_reg_t slc0host_len_wd;
+    volatile slchost_slc_apbwin_wdata_reg_t slc_apbwin_wdata;
+    volatile slchost_slc_apbwin_conf_reg_t slc_apbwin_conf;
+    volatile slchost_slc_apbwin_rdata_reg_t slc_apbwin_rdata;
+    volatile slchost_rdclr0_reg_t rdclr0;
+    volatile slchost_rdclr1_reg_t rdclr1;
+    volatile slchost_slc0host_int_ena1_reg_t slc0host_int_ena1;
+    volatile slchost_slc1host_int_ena1_reg_t slc1host_int_ena1;
+    uint32_t reserved_11c[23];
+    volatile slchost_slchostdate_reg_t slchostdate;
+    volatile slchost_slchostid_reg_t slchostid;
+    uint32_t reserved_180[28];
+    volatile slchost_conf_reg_t conf;
+    volatile slchost_inf_st_reg_t inf_st;
+} host_dev_t;
+
+extern host_dev_t HOST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(host_dev_t) == 0x1f8, "Invalid size of host_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/hp_apm_reg.h b/components/soc/esp32p4/include/soc/hp_apm_reg.h
new file mode 100644
index 0000000000..4a9151ab69
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hp_apm_reg.h
@@ -0,0 +1,1838 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_APM_REGION_FILTER_EN_REG register
+ *  Region filter enable register
+ */
+#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0)
+/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1;
+ *  Region filter enable
+ */
+#define HP_APM_REGION_FILTER_EN    0x0000FFFFU
+#define HP_APM_REGION_FILTER_EN_M  (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S)
+#define HP_APM_REGION_FILTER_EN_V  0x0000FFFFU
+#define HP_APM_REGION_FILTER_EN_S  0
+
+/** HP_APM_REGION0_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4)
+/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region0
+ */
+#define HP_APM_REGION0_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_START_M  (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S)
+#define HP_APM_REGION0_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_START_S  0
+
+/** HP_APM_REGION0_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8)
+/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region0
+ */
+#define HP_APM_REGION0_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_END_M  (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S)
+#define HP_APM_REGION0_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_END_S  0
+
+/** HP_APM_REGION0_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc)
+/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION0_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION0_R0_PMS_X_M  (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S)
+#define HP_APM_REGION0_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION0_R0_PMS_X_S  0
+/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION0_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION0_R0_PMS_W_M  (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S)
+#define HP_APM_REGION0_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION0_R0_PMS_W_S  1
+/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION0_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION0_R0_PMS_R_M  (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S)
+#define HP_APM_REGION0_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION0_R0_PMS_R_S  2
+/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION0_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION0_R1_PMS_X_M  (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S)
+#define HP_APM_REGION0_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION0_R1_PMS_X_S  4
+/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION0_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION0_R1_PMS_W_M  (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S)
+#define HP_APM_REGION0_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION0_R1_PMS_W_S  5
+/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION0_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION0_R1_PMS_R_M  (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S)
+#define HP_APM_REGION0_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION0_R1_PMS_R_S  6
+/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION0_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION0_R2_PMS_X_M  (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S)
+#define HP_APM_REGION0_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION0_R2_PMS_X_S  8
+/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION0_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION0_R2_PMS_W_M  (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S)
+#define HP_APM_REGION0_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION0_R2_PMS_W_S  9
+/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION0_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION0_R2_PMS_R_M  (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S)
+#define HP_APM_REGION0_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION0_R2_PMS_R_S  10
+
+/** HP_APM_REGION1_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10)
+/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region1
+ */
+#define HP_APM_REGION1_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_START_M  (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S)
+#define HP_APM_REGION1_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_START_S  0
+
+/** HP_APM_REGION1_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14)
+/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region1
+ */
+#define HP_APM_REGION1_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_END_M  (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S)
+#define HP_APM_REGION1_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_END_S  0
+
+/** HP_APM_REGION1_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18)
+/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION1_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION1_R0_PMS_X_M  (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S)
+#define HP_APM_REGION1_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION1_R0_PMS_X_S  0
+/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION1_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION1_R0_PMS_W_M  (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S)
+#define HP_APM_REGION1_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION1_R0_PMS_W_S  1
+/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION1_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION1_R0_PMS_R_M  (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S)
+#define HP_APM_REGION1_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION1_R0_PMS_R_S  2
+/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION1_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION1_R1_PMS_X_M  (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S)
+#define HP_APM_REGION1_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION1_R1_PMS_X_S  4
+/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION1_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION1_R1_PMS_W_M  (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S)
+#define HP_APM_REGION1_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION1_R1_PMS_W_S  5
+/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION1_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION1_R1_PMS_R_M  (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S)
+#define HP_APM_REGION1_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION1_R1_PMS_R_S  6
+/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION1_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION1_R2_PMS_X_M  (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S)
+#define HP_APM_REGION1_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION1_R2_PMS_X_S  8
+/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION1_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION1_R2_PMS_W_M  (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S)
+#define HP_APM_REGION1_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION1_R2_PMS_W_S  9
+/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION1_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION1_R2_PMS_R_M  (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S)
+#define HP_APM_REGION1_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION1_R2_PMS_R_S  10
+
+/** HP_APM_REGION2_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c)
+/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region2
+ */
+#define HP_APM_REGION2_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_START_M  (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S)
+#define HP_APM_REGION2_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_START_S  0
+
+/** HP_APM_REGION2_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20)
+/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region2
+ */
+#define HP_APM_REGION2_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_END_M  (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S)
+#define HP_APM_REGION2_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_END_S  0
+
+/** HP_APM_REGION2_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24)
+/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION2_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION2_R0_PMS_X_M  (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S)
+#define HP_APM_REGION2_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION2_R0_PMS_X_S  0
+/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION2_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION2_R0_PMS_W_M  (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S)
+#define HP_APM_REGION2_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION2_R0_PMS_W_S  1
+/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION2_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION2_R0_PMS_R_M  (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S)
+#define HP_APM_REGION2_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION2_R0_PMS_R_S  2
+/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION2_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION2_R1_PMS_X_M  (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S)
+#define HP_APM_REGION2_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION2_R1_PMS_X_S  4
+/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION2_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION2_R1_PMS_W_M  (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S)
+#define HP_APM_REGION2_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION2_R1_PMS_W_S  5
+/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION2_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION2_R1_PMS_R_M  (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S)
+#define HP_APM_REGION2_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION2_R1_PMS_R_S  6
+/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION2_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION2_R2_PMS_X_M  (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S)
+#define HP_APM_REGION2_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION2_R2_PMS_X_S  8
+/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION2_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION2_R2_PMS_W_M  (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S)
+#define HP_APM_REGION2_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION2_R2_PMS_W_S  9
+/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION2_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION2_R2_PMS_R_M  (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S)
+#define HP_APM_REGION2_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION2_R2_PMS_R_S  10
+
+/** HP_APM_REGION3_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28)
+/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region3
+ */
+#define HP_APM_REGION3_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_START_M  (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S)
+#define HP_APM_REGION3_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_START_S  0
+
+/** HP_APM_REGION3_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c)
+/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region3
+ */
+#define HP_APM_REGION3_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_END_M  (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S)
+#define HP_APM_REGION3_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_END_S  0
+
+/** HP_APM_REGION3_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30)
+/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION3_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION3_R0_PMS_X_M  (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S)
+#define HP_APM_REGION3_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION3_R0_PMS_X_S  0
+/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION3_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION3_R0_PMS_W_M  (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S)
+#define HP_APM_REGION3_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION3_R0_PMS_W_S  1
+/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION3_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION3_R0_PMS_R_M  (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S)
+#define HP_APM_REGION3_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION3_R0_PMS_R_S  2
+/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION3_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION3_R1_PMS_X_M  (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S)
+#define HP_APM_REGION3_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION3_R1_PMS_X_S  4
+/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION3_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION3_R1_PMS_W_M  (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S)
+#define HP_APM_REGION3_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION3_R1_PMS_W_S  5
+/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION3_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION3_R1_PMS_R_M  (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S)
+#define HP_APM_REGION3_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION3_R1_PMS_R_S  6
+/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION3_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION3_R2_PMS_X_M  (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S)
+#define HP_APM_REGION3_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION3_R2_PMS_X_S  8
+/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION3_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION3_R2_PMS_W_M  (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S)
+#define HP_APM_REGION3_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION3_R2_PMS_W_S  9
+/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION3_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION3_R2_PMS_R_M  (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S)
+#define HP_APM_REGION3_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION3_R2_PMS_R_S  10
+
+/** HP_APM_REGION4_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34)
+/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region4
+ */
+#define HP_APM_REGION4_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_START_M  (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S)
+#define HP_APM_REGION4_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_START_S  0
+
+/** HP_APM_REGION4_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38)
+/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region4
+ */
+#define HP_APM_REGION4_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_END_M  (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S)
+#define HP_APM_REGION4_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_END_S  0
+
+/** HP_APM_REGION4_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c)
+/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION4_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION4_R0_PMS_X_M  (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S)
+#define HP_APM_REGION4_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION4_R0_PMS_X_S  0
+/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION4_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION4_R0_PMS_W_M  (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S)
+#define HP_APM_REGION4_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION4_R0_PMS_W_S  1
+/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION4_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION4_R0_PMS_R_M  (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S)
+#define HP_APM_REGION4_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION4_R0_PMS_R_S  2
+/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION4_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION4_R1_PMS_X_M  (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S)
+#define HP_APM_REGION4_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION4_R1_PMS_X_S  4
+/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION4_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION4_R1_PMS_W_M  (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S)
+#define HP_APM_REGION4_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION4_R1_PMS_W_S  5
+/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION4_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION4_R1_PMS_R_M  (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S)
+#define HP_APM_REGION4_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION4_R1_PMS_R_S  6
+/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION4_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION4_R2_PMS_X_M  (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S)
+#define HP_APM_REGION4_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION4_R2_PMS_X_S  8
+/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION4_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION4_R2_PMS_W_M  (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S)
+#define HP_APM_REGION4_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION4_R2_PMS_W_S  9
+/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION4_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION4_R2_PMS_R_M  (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S)
+#define HP_APM_REGION4_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION4_R2_PMS_R_S  10
+
+/** HP_APM_REGION5_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40)
+/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region5
+ */
+#define HP_APM_REGION5_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_START_M  (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S)
+#define HP_APM_REGION5_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_START_S  0
+
+/** HP_APM_REGION5_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44)
+/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region5
+ */
+#define HP_APM_REGION5_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_END_M  (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S)
+#define HP_APM_REGION5_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_END_S  0
+
+/** HP_APM_REGION5_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48)
+/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION5_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION5_R0_PMS_X_M  (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S)
+#define HP_APM_REGION5_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION5_R0_PMS_X_S  0
+/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION5_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION5_R0_PMS_W_M  (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S)
+#define HP_APM_REGION5_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION5_R0_PMS_W_S  1
+/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION5_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION5_R0_PMS_R_M  (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S)
+#define HP_APM_REGION5_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION5_R0_PMS_R_S  2
+/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION5_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION5_R1_PMS_X_M  (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S)
+#define HP_APM_REGION5_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION5_R1_PMS_X_S  4
+/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION5_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION5_R1_PMS_W_M  (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S)
+#define HP_APM_REGION5_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION5_R1_PMS_W_S  5
+/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION5_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION5_R1_PMS_R_M  (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S)
+#define HP_APM_REGION5_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION5_R1_PMS_R_S  6
+/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION5_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION5_R2_PMS_X_M  (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S)
+#define HP_APM_REGION5_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION5_R2_PMS_X_S  8
+/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION5_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION5_R2_PMS_W_M  (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S)
+#define HP_APM_REGION5_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION5_R2_PMS_W_S  9
+/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION5_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION5_R2_PMS_R_M  (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S)
+#define HP_APM_REGION5_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION5_R2_PMS_R_S  10
+
+/** HP_APM_REGION6_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c)
+/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region6
+ */
+#define HP_APM_REGION6_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_START_M  (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S)
+#define HP_APM_REGION6_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_START_S  0
+
+/** HP_APM_REGION6_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50)
+/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region6
+ */
+#define HP_APM_REGION6_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_END_M  (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S)
+#define HP_APM_REGION6_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_END_S  0
+
+/** HP_APM_REGION6_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54)
+/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION6_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION6_R0_PMS_X_M  (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S)
+#define HP_APM_REGION6_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION6_R0_PMS_X_S  0
+/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION6_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION6_R0_PMS_W_M  (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S)
+#define HP_APM_REGION6_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION6_R0_PMS_W_S  1
+/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION6_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION6_R0_PMS_R_M  (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S)
+#define HP_APM_REGION6_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION6_R0_PMS_R_S  2
+/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION6_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION6_R1_PMS_X_M  (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S)
+#define HP_APM_REGION6_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION6_R1_PMS_X_S  4
+/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION6_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION6_R1_PMS_W_M  (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S)
+#define HP_APM_REGION6_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION6_R1_PMS_W_S  5
+/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION6_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION6_R1_PMS_R_M  (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S)
+#define HP_APM_REGION6_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION6_R1_PMS_R_S  6
+/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION6_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION6_R2_PMS_X_M  (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S)
+#define HP_APM_REGION6_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION6_R2_PMS_X_S  8
+/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION6_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION6_R2_PMS_W_M  (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S)
+#define HP_APM_REGION6_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION6_R2_PMS_W_S  9
+/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION6_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION6_R2_PMS_R_M  (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S)
+#define HP_APM_REGION6_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION6_R2_PMS_R_S  10
+
+/** HP_APM_REGION7_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58)
+/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region7
+ */
+#define HP_APM_REGION7_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_START_M  (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S)
+#define HP_APM_REGION7_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_START_S  0
+
+/** HP_APM_REGION7_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c)
+/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region7
+ */
+#define HP_APM_REGION7_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_END_M  (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S)
+#define HP_APM_REGION7_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_END_S  0
+
+/** HP_APM_REGION7_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60)
+/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION7_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION7_R0_PMS_X_M  (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S)
+#define HP_APM_REGION7_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION7_R0_PMS_X_S  0
+/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION7_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION7_R0_PMS_W_M  (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S)
+#define HP_APM_REGION7_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION7_R0_PMS_W_S  1
+/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION7_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION7_R0_PMS_R_M  (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S)
+#define HP_APM_REGION7_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION7_R0_PMS_R_S  2
+/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION7_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION7_R1_PMS_X_M  (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S)
+#define HP_APM_REGION7_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION7_R1_PMS_X_S  4
+/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION7_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION7_R1_PMS_W_M  (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S)
+#define HP_APM_REGION7_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION7_R1_PMS_W_S  5
+/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION7_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION7_R1_PMS_R_M  (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S)
+#define HP_APM_REGION7_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION7_R1_PMS_R_S  6
+/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION7_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION7_R2_PMS_X_M  (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S)
+#define HP_APM_REGION7_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION7_R2_PMS_X_S  8
+/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION7_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION7_R2_PMS_W_M  (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S)
+#define HP_APM_REGION7_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION7_R2_PMS_W_S  9
+/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION7_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION7_R2_PMS_R_M  (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S)
+#define HP_APM_REGION7_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION7_R2_PMS_R_S  10
+
+/** HP_APM_REGION8_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64)
+/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region8
+ */
+#define HP_APM_REGION8_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_START_M  (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S)
+#define HP_APM_REGION8_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_START_S  0
+
+/** HP_APM_REGION8_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68)
+/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region8
+ */
+#define HP_APM_REGION8_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_END_M  (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S)
+#define HP_APM_REGION8_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_END_S  0
+
+/** HP_APM_REGION8_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c)
+/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION8_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION8_R0_PMS_X_M  (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S)
+#define HP_APM_REGION8_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION8_R0_PMS_X_S  0
+/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION8_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION8_R0_PMS_W_M  (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S)
+#define HP_APM_REGION8_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION8_R0_PMS_W_S  1
+/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION8_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION8_R0_PMS_R_M  (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S)
+#define HP_APM_REGION8_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION8_R0_PMS_R_S  2
+/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION8_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION8_R1_PMS_X_M  (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S)
+#define HP_APM_REGION8_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION8_R1_PMS_X_S  4
+/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION8_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION8_R1_PMS_W_M  (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S)
+#define HP_APM_REGION8_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION8_R1_PMS_W_S  5
+/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION8_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION8_R1_PMS_R_M  (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S)
+#define HP_APM_REGION8_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION8_R1_PMS_R_S  6
+/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION8_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION8_R2_PMS_X_M  (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S)
+#define HP_APM_REGION8_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION8_R2_PMS_X_S  8
+/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION8_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION8_R2_PMS_W_M  (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S)
+#define HP_APM_REGION8_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION8_R2_PMS_W_S  9
+/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION8_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION8_R2_PMS_R_M  (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S)
+#define HP_APM_REGION8_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION8_R2_PMS_R_S  10
+
+/** HP_APM_REGION9_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70)
+/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region9
+ */
+#define HP_APM_REGION9_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_START_M  (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S)
+#define HP_APM_REGION9_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_START_S  0
+
+/** HP_APM_REGION9_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74)
+/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region9
+ */
+#define HP_APM_REGION9_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_END_M  (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S)
+#define HP_APM_REGION9_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_END_S  0
+
+/** HP_APM_REGION9_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78)
+/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION9_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION9_R0_PMS_X_M  (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S)
+#define HP_APM_REGION9_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION9_R0_PMS_X_S  0
+/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION9_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION9_R0_PMS_W_M  (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S)
+#define HP_APM_REGION9_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION9_R0_PMS_W_S  1
+/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION9_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION9_R0_PMS_R_M  (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S)
+#define HP_APM_REGION9_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION9_R0_PMS_R_S  2
+/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION9_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION9_R1_PMS_X_M  (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S)
+#define HP_APM_REGION9_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION9_R1_PMS_X_S  4
+/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION9_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION9_R1_PMS_W_M  (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S)
+#define HP_APM_REGION9_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION9_R1_PMS_W_S  5
+/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION9_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION9_R1_PMS_R_M  (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S)
+#define HP_APM_REGION9_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION9_R1_PMS_R_S  6
+/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION9_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION9_R2_PMS_X_M  (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S)
+#define HP_APM_REGION9_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION9_R2_PMS_X_S  8
+/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION9_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION9_R2_PMS_W_M  (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S)
+#define HP_APM_REGION9_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION9_R2_PMS_W_S  9
+/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION9_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION9_R2_PMS_R_M  (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S)
+#define HP_APM_REGION9_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION9_R2_PMS_R_S  10
+
+/** HP_APM_REGION10_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c)
+/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region10
+ */
+#define HP_APM_REGION10_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_START_M  (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S)
+#define HP_APM_REGION10_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_START_S  0
+
+/** HP_APM_REGION10_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80)
+/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region10
+ */
+#define HP_APM_REGION10_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_END_M  (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S)
+#define HP_APM_REGION10_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_END_S  0
+
+/** HP_APM_REGION10_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84)
+/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION10_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION10_R0_PMS_X_M  (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S)
+#define HP_APM_REGION10_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION10_R0_PMS_X_S  0
+/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION10_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION10_R0_PMS_W_M  (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S)
+#define HP_APM_REGION10_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION10_R0_PMS_W_S  1
+/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION10_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION10_R0_PMS_R_M  (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S)
+#define HP_APM_REGION10_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION10_R0_PMS_R_S  2
+/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION10_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION10_R1_PMS_X_M  (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S)
+#define HP_APM_REGION10_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION10_R1_PMS_X_S  4
+/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION10_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION10_R1_PMS_W_M  (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S)
+#define HP_APM_REGION10_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION10_R1_PMS_W_S  5
+/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION10_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION10_R1_PMS_R_M  (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S)
+#define HP_APM_REGION10_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION10_R1_PMS_R_S  6
+/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION10_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION10_R2_PMS_X_M  (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S)
+#define HP_APM_REGION10_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION10_R2_PMS_X_S  8
+/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION10_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION10_R2_PMS_W_M  (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S)
+#define HP_APM_REGION10_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION10_R2_PMS_W_S  9
+/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION10_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION10_R2_PMS_R_M  (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S)
+#define HP_APM_REGION10_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION10_R2_PMS_R_S  10
+
+/** HP_APM_REGION11_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88)
+/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region11
+ */
+#define HP_APM_REGION11_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_START_M  (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S)
+#define HP_APM_REGION11_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_START_S  0
+
+/** HP_APM_REGION11_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c)
+/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region11
+ */
+#define HP_APM_REGION11_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_END_M  (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S)
+#define HP_APM_REGION11_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_END_S  0
+
+/** HP_APM_REGION11_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90)
+/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION11_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION11_R0_PMS_X_M  (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S)
+#define HP_APM_REGION11_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION11_R0_PMS_X_S  0
+/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION11_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION11_R0_PMS_W_M  (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S)
+#define HP_APM_REGION11_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION11_R0_PMS_W_S  1
+/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION11_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION11_R0_PMS_R_M  (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S)
+#define HP_APM_REGION11_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION11_R0_PMS_R_S  2
+/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION11_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION11_R1_PMS_X_M  (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S)
+#define HP_APM_REGION11_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION11_R1_PMS_X_S  4
+/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION11_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION11_R1_PMS_W_M  (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S)
+#define HP_APM_REGION11_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION11_R1_PMS_W_S  5
+/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION11_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION11_R1_PMS_R_M  (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S)
+#define HP_APM_REGION11_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION11_R1_PMS_R_S  6
+/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION11_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION11_R2_PMS_X_M  (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S)
+#define HP_APM_REGION11_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION11_R2_PMS_X_S  8
+/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION11_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION11_R2_PMS_W_M  (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S)
+#define HP_APM_REGION11_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION11_R2_PMS_W_S  9
+/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION11_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION11_R2_PMS_R_M  (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S)
+#define HP_APM_REGION11_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION11_R2_PMS_R_S  10
+
+/** HP_APM_REGION12_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94)
+/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region12
+ */
+#define HP_APM_REGION12_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_START_M  (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S)
+#define HP_APM_REGION12_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_START_S  0
+
+/** HP_APM_REGION12_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98)
+/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region12
+ */
+#define HP_APM_REGION12_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_END_M  (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S)
+#define HP_APM_REGION12_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_END_S  0
+
+/** HP_APM_REGION12_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c)
+/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION12_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION12_R0_PMS_X_M  (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S)
+#define HP_APM_REGION12_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION12_R0_PMS_X_S  0
+/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION12_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION12_R0_PMS_W_M  (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S)
+#define HP_APM_REGION12_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION12_R0_PMS_W_S  1
+/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION12_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION12_R0_PMS_R_M  (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S)
+#define HP_APM_REGION12_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION12_R0_PMS_R_S  2
+/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION12_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION12_R1_PMS_X_M  (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S)
+#define HP_APM_REGION12_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION12_R1_PMS_X_S  4
+/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION12_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION12_R1_PMS_W_M  (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S)
+#define HP_APM_REGION12_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION12_R1_PMS_W_S  5
+/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION12_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION12_R1_PMS_R_M  (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S)
+#define HP_APM_REGION12_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION12_R1_PMS_R_S  6
+/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION12_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION12_R2_PMS_X_M  (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S)
+#define HP_APM_REGION12_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION12_R2_PMS_X_S  8
+/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION12_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION12_R2_PMS_W_M  (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S)
+#define HP_APM_REGION12_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION12_R2_PMS_W_S  9
+/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION12_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION12_R2_PMS_R_M  (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S)
+#define HP_APM_REGION12_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION12_R2_PMS_R_S  10
+
+/** HP_APM_REGION13_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0)
+/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region13
+ */
+#define HP_APM_REGION13_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_START_M  (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S)
+#define HP_APM_REGION13_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_START_S  0
+
+/** HP_APM_REGION13_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4)
+/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region13
+ */
+#define HP_APM_REGION13_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_END_M  (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S)
+#define HP_APM_REGION13_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_END_S  0
+
+/** HP_APM_REGION13_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8)
+/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION13_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION13_R0_PMS_X_M  (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S)
+#define HP_APM_REGION13_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION13_R0_PMS_X_S  0
+/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION13_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION13_R0_PMS_W_M  (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S)
+#define HP_APM_REGION13_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION13_R0_PMS_W_S  1
+/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION13_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION13_R0_PMS_R_M  (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S)
+#define HP_APM_REGION13_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION13_R0_PMS_R_S  2
+/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION13_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION13_R1_PMS_X_M  (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S)
+#define HP_APM_REGION13_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION13_R1_PMS_X_S  4
+/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION13_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION13_R1_PMS_W_M  (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S)
+#define HP_APM_REGION13_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION13_R1_PMS_W_S  5
+/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION13_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION13_R1_PMS_R_M  (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S)
+#define HP_APM_REGION13_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION13_R1_PMS_R_S  6
+/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION13_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION13_R2_PMS_X_M  (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S)
+#define HP_APM_REGION13_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION13_R2_PMS_X_S  8
+/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION13_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION13_R2_PMS_W_M  (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S)
+#define HP_APM_REGION13_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION13_R2_PMS_W_S  9
+/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION13_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION13_R2_PMS_R_M  (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S)
+#define HP_APM_REGION13_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION13_R2_PMS_R_S  10
+
+/** HP_APM_REGION14_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac)
+/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region14
+ */
+#define HP_APM_REGION14_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_START_M  (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S)
+#define HP_APM_REGION14_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_START_S  0
+
+/** HP_APM_REGION14_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0)
+/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region14
+ */
+#define HP_APM_REGION14_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_END_M  (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S)
+#define HP_APM_REGION14_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_END_S  0
+
+/** HP_APM_REGION14_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4)
+/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION14_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION14_R0_PMS_X_M  (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S)
+#define HP_APM_REGION14_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION14_R0_PMS_X_S  0
+/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION14_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION14_R0_PMS_W_M  (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S)
+#define HP_APM_REGION14_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION14_R0_PMS_W_S  1
+/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION14_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION14_R0_PMS_R_M  (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S)
+#define HP_APM_REGION14_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION14_R0_PMS_R_S  2
+/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION14_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION14_R1_PMS_X_M  (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S)
+#define HP_APM_REGION14_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION14_R1_PMS_X_S  4
+/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION14_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION14_R1_PMS_W_M  (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S)
+#define HP_APM_REGION14_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION14_R1_PMS_W_S  5
+/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION14_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION14_R1_PMS_R_M  (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S)
+#define HP_APM_REGION14_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION14_R1_PMS_R_S  6
+/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION14_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION14_R2_PMS_X_M  (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S)
+#define HP_APM_REGION14_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION14_R2_PMS_X_S  8
+/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION14_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION14_R2_PMS_W_M  (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S)
+#define HP_APM_REGION14_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION14_R2_PMS_W_S  9
+/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION14_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION14_R2_PMS_R_M  (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S)
+#define HP_APM_REGION14_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION14_R2_PMS_R_S  10
+
+/** HP_APM_REGION15_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8)
+/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region15
+ */
+#define HP_APM_REGION15_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_START_M  (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S)
+#define HP_APM_REGION15_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_START_S  0
+
+/** HP_APM_REGION15_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc)
+/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region15
+ */
+#define HP_APM_REGION15_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_END_M  (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S)
+#define HP_APM_REGION15_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_END_S  0
+
+/** HP_APM_REGION15_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0)
+/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define HP_APM_REGION15_R0_PMS_X    (BIT(0))
+#define HP_APM_REGION15_R0_PMS_X_M  (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S)
+#define HP_APM_REGION15_R0_PMS_X_V  0x00000001U
+#define HP_APM_REGION15_R0_PMS_X_S  0
+/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define HP_APM_REGION15_R0_PMS_W    (BIT(1))
+#define HP_APM_REGION15_R0_PMS_W_M  (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S)
+#define HP_APM_REGION15_R0_PMS_W_V  0x00000001U
+#define HP_APM_REGION15_R0_PMS_W_S  1
+/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define HP_APM_REGION15_R0_PMS_R    (BIT(2))
+#define HP_APM_REGION15_R0_PMS_R_M  (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S)
+#define HP_APM_REGION15_R0_PMS_R_V  0x00000001U
+#define HP_APM_REGION15_R0_PMS_R_S  2
+/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define HP_APM_REGION15_R1_PMS_X    (BIT(4))
+#define HP_APM_REGION15_R1_PMS_X_M  (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S)
+#define HP_APM_REGION15_R1_PMS_X_V  0x00000001U
+#define HP_APM_REGION15_R1_PMS_X_S  4
+/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define HP_APM_REGION15_R1_PMS_W    (BIT(5))
+#define HP_APM_REGION15_R1_PMS_W_M  (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S)
+#define HP_APM_REGION15_R1_PMS_W_V  0x00000001U
+#define HP_APM_REGION15_R1_PMS_W_S  5
+/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define HP_APM_REGION15_R1_PMS_R    (BIT(6))
+#define HP_APM_REGION15_R1_PMS_R_M  (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S)
+#define HP_APM_REGION15_R1_PMS_R_V  0x00000001U
+#define HP_APM_REGION15_R1_PMS_R_S  6
+/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define HP_APM_REGION15_R2_PMS_X    (BIT(8))
+#define HP_APM_REGION15_R2_PMS_X_M  (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S)
+#define HP_APM_REGION15_R2_PMS_X_V  0x00000001U
+#define HP_APM_REGION15_R2_PMS_X_S  8
+/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define HP_APM_REGION15_R2_PMS_W    (BIT(9))
+#define HP_APM_REGION15_R2_PMS_W_M  (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S)
+#define HP_APM_REGION15_R2_PMS_W_V  0x00000001U
+#define HP_APM_REGION15_R2_PMS_W_S  9
+/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define HP_APM_REGION15_R2_PMS_R    (BIT(10))
+#define HP_APM_REGION15_R2_PMS_R_M  (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S)
+#define HP_APM_REGION15_R2_PMS_R_V  0x00000001U
+#define HP_APM_REGION15_R2_PMS_R_S  10
+
+/** HP_APM_FUNC_CTRL_REG register
+ *  PMS function control register
+ */
+#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4)
+/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
+ *  PMS M0 function enable
+ */
+#define HP_APM_M0_PMS_FUNC_EN    (BIT(0))
+#define HP_APM_M0_PMS_FUNC_EN_M  (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S)
+#define HP_APM_M0_PMS_FUNC_EN_V  0x00000001U
+#define HP_APM_M0_PMS_FUNC_EN_S  0
+/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
+ *  PMS M1 function enable
+ */
+#define HP_APM_M1_PMS_FUNC_EN    (BIT(1))
+#define HP_APM_M1_PMS_FUNC_EN_M  (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S)
+#define HP_APM_M1_PMS_FUNC_EN_V  0x00000001U
+#define HP_APM_M1_PMS_FUNC_EN_S  1
+/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1;
+ *  PMS M2 function enable
+ */
+#define HP_APM_M2_PMS_FUNC_EN    (BIT(2))
+#define HP_APM_M2_PMS_FUNC_EN_M  (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S)
+#define HP_APM_M2_PMS_FUNC_EN_V  0x00000001U
+#define HP_APM_M2_PMS_FUNC_EN_S  2
+/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1;
+ *  PMS M3 function enable
+ */
+#define HP_APM_M3_PMS_FUNC_EN    (BIT(3))
+#define HP_APM_M3_PMS_FUNC_EN_M  (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S)
+#define HP_APM_M3_PMS_FUNC_EN_V  0x00000001U
+#define HP_APM_M3_PMS_FUNC_EN_S  3
+
+/** HP_APM_M0_STATUS_REG register
+ *  M0 status register
+ */
+#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8)
+/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Exception status
+ */
+#define HP_APM_M0_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M0_EXCEPTION_STATUS_M  (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S)
+#define HP_APM_M0_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M0_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M0_STATUS_CLR_REG register
+ *  M0 status clear register
+ */
+#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc)
+/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear exception status
+ */
+#define HP_APM_M0_REGION_STATUS_CLR    (BIT(0))
+#define HP_APM_M0_REGION_STATUS_CLR_M  (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S)
+#define HP_APM_M0_REGION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M0_REGION_STATUS_CLR_S  0
+
+/** HP_APM_M0_EXCEPTION_INFO0_REG register
+ *  M0 exception_info0 register
+ */
+#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0)
+/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Exception region
+ */
+#define HP_APM_M0_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M0_EXCEPTION_REGION_M  (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S)
+#define HP_APM_M0_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M0_EXCEPTION_REGION_S  0
+/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Exception mode
+ */
+#define HP_APM_M0_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M0_EXCEPTION_MODE_M  (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S)
+#define HP_APM_M0_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M0_EXCEPTION_MODE_S  16
+/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Exception id information
+ */
+#define HP_APM_M0_EXCEPTION_ID    0x0000001FU
+#define HP_APM_M0_EXCEPTION_ID_M  (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S)
+#define HP_APM_M0_EXCEPTION_ID_V  0x0000001FU
+#define HP_APM_M0_EXCEPTION_ID_S  18
+
+/** HP_APM_M0_EXCEPTION_INFO1_REG register
+ *  M0 exception_info1 register
+ */
+#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4)
+/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Exception addr
+ */
+#define HP_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M0_EXCEPTION_ADDR_M  (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S)
+#define HP_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M0_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M1_STATUS_REG register
+ *  M1 status register
+ */
+#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8)
+/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Exception status
+ */
+#define HP_APM_M1_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M1_EXCEPTION_STATUS_M  (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S)
+#define HP_APM_M1_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M1_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M1_STATUS_CLR_REG register
+ *  M1 status clear register
+ */
+#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc)
+/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear exception status
+ */
+#define HP_APM_M1_REGION_STATUS_CLR    (BIT(0))
+#define HP_APM_M1_REGION_STATUS_CLR_M  (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S)
+#define HP_APM_M1_REGION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M1_REGION_STATUS_CLR_S  0
+
+/** HP_APM_M1_EXCEPTION_INFO0_REG register
+ *  M1 exception_info0 register
+ */
+#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0)
+/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Exception region
+ */
+#define HP_APM_M1_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M1_EXCEPTION_REGION_M  (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S)
+#define HP_APM_M1_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M1_EXCEPTION_REGION_S  0
+/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Exception mode
+ */
+#define HP_APM_M1_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M1_EXCEPTION_MODE_M  (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S)
+#define HP_APM_M1_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M1_EXCEPTION_MODE_S  16
+/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Exception id information
+ */
+#define HP_APM_M1_EXCEPTION_ID    0x0000001FU
+#define HP_APM_M1_EXCEPTION_ID_M  (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S)
+#define HP_APM_M1_EXCEPTION_ID_V  0x0000001FU
+#define HP_APM_M1_EXCEPTION_ID_S  18
+
+/** HP_APM_M1_EXCEPTION_INFO1_REG register
+ *  M1 exception_info1 register
+ */
+#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4)
+/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Exception addr
+ */
+#define HP_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M1_EXCEPTION_ADDR_M  (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S)
+#define HP_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M1_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M2_STATUS_REG register
+ *  M2 status register
+ */
+#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8)
+/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Exception status
+ */
+#define HP_APM_M2_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M2_EXCEPTION_STATUS_M  (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S)
+#define HP_APM_M2_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M2_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M2_STATUS_CLR_REG register
+ *  M2 status clear register
+ */
+#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec)
+/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear exception status
+ */
+#define HP_APM_M2_REGION_STATUS_CLR    (BIT(0))
+#define HP_APM_M2_REGION_STATUS_CLR_M  (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S)
+#define HP_APM_M2_REGION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M2_REGION_STATUS_CLR_S  0
+
+/** HP_APM_M2_EXCEPTION_INFO0_REG register
+ *  M2 exception_info0 register
+ */
+#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0)
+/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Exception region
+ */
+#define HP_APM_M2_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M2_EXCEPTION_REGION_M  (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S)
+#define HP_APM_M2_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M2_EXCEPTION_REGION_S  0
+/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Exception mode
+ */
+#define HP_APM_M2_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M2_EXCEPTION_MODE_M  (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S)
+#define HP_APM_M2_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M2_EXCEPTION_MODE_S  16
+/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Exception id information
+ */
+#define HP_APM_M2_EXCEPTION_ID    0x0000001FU
+#define HP_APM_M2_EXCEPTION_ID_M  (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S)
+#define HP_APM_M2_EXCEPTION_ID_V  0x0000001FU
+#define HP_APM_M2_EXCEPTION_ID_S  18
+
+/** HP_APM_M2_EXCEPTION_INFO1_REG register
+ *  M2 exception_info1 register
+ */
+#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4)
+/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Exception addr
+ */
+#define HP_APM_M2_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M2_EXCEPTION_ADDR_M  (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S)
+#define HP_APM_M2_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M2_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M3_STATUS_REG register
+ *  M3 status register
+ */
+#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8)
+/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Exception status
+ */
+#define HP_APM_M3_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M3_EXCEPTION_STATUS_M  (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S)
+#define HP_APM_M3_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M3_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M3_STATUS_CLR_REG register
+ *  M3 status clear register
+ */
+#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc)
+/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear exception status
+ */
+#define HP_APM_M3_REGION_STATUS_CLR    (BIT(0))
+#define HP_APM_M3_REGION_STATUS_CLR_M  (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S)
+#define HP_APM_M3_REGION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M3_REGION_STATUS_CLR_S  0
+
+/** HP_APM_M3_EXCEPTION_INFO0_REG register
+ *  M3 exception_info0 register
+ */
+#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100)
+/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Exception region
+ */
+#define HP_APM_M3_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M3_EXCEPTION_REGION_M  (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S)
+#define HP_APM_M3_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M3_EXCEPTION_REGION_S  0
+/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Exception mode
+ */
+#define HP_APM_M3_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M3_EXCEPTION_MODE_M  (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S)
+#define HP_APM_M3_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M3_EXCEPTION_MODE_S  16
+/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Exception id information
+ */
+#define HP_APM_M3_EXCEPTION_ID    0x0000001FU
+#define HP_APM_M3_EXCEPTION_ID_M  (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S)
+#define HP_APM_M3_EXCEPTION_ID_V  0x0000001FU
+#define HP_APM_M3_EXCEPTION_ID_S  18
+
+/** HP_APM_M3_EXCEPTION_INFO1_REG register
+ *  M3 exception_info1 register
+ */
+#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104)
+/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Exception addr
+ */
+#define HP_APM_M3_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M3_EXCEPTION_ADDR_M  (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S)
+#define HP_APM_M3_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M3_EXCEPTION_ADDR_S  0
+
+/** HP_APM_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108)
+/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  APM M0 interrupt enable
+ */
+#define HP_APM_M0_APM_INT_EN    (BIT(0))
+#define HP_APM_M0_APM_INT_EN_M  (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S)
+#define HP_APM_M0_APM_INT_EN_V  0x00000001U
+#define HP_APM_M0_APM_INT_EN_S  0
+/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  APM M1 interrupt enable
+ */
+#define HP_APM_M1_APM_INT_EN    (BIT(1))
+#define HP_APM_M1_APM_INT_EN_M  (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S)
+#define HP_APM_M1_APM_INT_EN_V  0x00000001U
+#define HP_APM_M1_APM_INT_EN_S  1
+/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0;
+ *  APM M2 interrupt enable
+ */
+#define HP_APM_M2_APM_INT_EN    (BIT(2))
+#define HP_APM_M2_APM_INT_EN_M  (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S)
+#define HP_APM_M2_APM_INT_EN_V  0x00000001U
+#define HP_APM_M2_APM_INT_EN_S  2
+/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0;
+ *  APM M3 interrupt enable
+ */
+#define HP_APM_M3_APM_INT_EN    (BIT(3))
+#define HP_APM_M3_APM_INT_EN_M  (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S)
+#define HP_APM_M3_APM_INT_EN_V  0x00000001U
+#define HP_APM_M3_APM_INT_EN_S  3
+
+/** HP_APM_CLOCK_GATE_REG register
+ *  clock gating register
+ */
+#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c)
+/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reg_clk_en
+ */
+#define HP_APM_CLK_EN    (BIT(0))
+#define HP_APM_CLK_EN_M  (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S)
+#define HP_APM_CLK_EN_V  0x00000001U
+#define HP_APM_CLK_EN_S  0
+
+/** HP_APM_DATE_REG register
+ *  Version register
+ */
+#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc)
+/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
+ *  reg_date
+ */
+#define HP_APM_DATE    0x0FFFFFFFU
+#define HP_APM_DATE_M  (HP_APM_DATE_V << HP_APM_DATE_S)
+#define HP_APM_DATE_V  0x0FFFFFFFU
+#define HP_APM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/hp_apm_struct.h b/components/soc/esp32p4/include/soc/hp_apm_struct.h
new file mode 100644
index 0000000000..faec6b3372
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hp_apm_struct.h
@@ -0,0 +1,1670 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Region filter enable register */
+/** Type of region_filter_en register
+ *  Region filter enable register
+ */
+typedef union {
+    struct {
+        /** region_filter_en : R/W; bitpos: [15:0]; default: 1;
+         *  Region filter enable
+         */
+        uint32_t region_filter_en:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} hp_apm_region_filter_en_reg_t;
+
+
+/** Group: Region address register */
+/** Type of region0_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region0
+         */
+        uint32_t region0_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region0_addr_start_reg_t;
+
+/** Type of region0_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region0
+         */
+        uint32_t region0_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region0_addr_end_reg_t;
+
+/** Type of region1_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region1
+         */
+        uint32_t region1_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region1_addr_start_reg_t;
+
+/** Type of region1_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region1
+         */
+        uint32_t region1_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region1_addr_end_reg_t;
+
+/** Type of region2_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region2
+         */
+        uint32_t region2_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region2_addr_start_reg_t;
+
+/** Type of region2_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region2
+         */
+        uint32_t region2_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region2_addr_end_reg_t;
+
+/** Type of region3_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region3
+         */
+        uint32_t region3_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region3_addr_start_reg_t;
+
+/** Type of region3_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region3
+         */
+        uint32_t region3_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region3_addr_end_reg_t;
+
+/** Type of region4_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region4_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region4
+         */
+        uint32_t region4_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region4_addr_start_reg_t;
+
+/** Type of region4_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region4
+         */
+        uint32_t region4_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region4_addr_end_reg_t;
+
+/** Type of region5_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region5_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region5
+         */
+        uint32_t region5_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region5_addr_start_reg_t;
+
+/** Type of region5_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region5
+         */
+        uint32_t region5_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region5_addr_end_reg_t;
+
+/** Type of region6_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region6_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region6
+         */
+        uint32_t region6_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region6_addr_start_reg_t;
+
+/** Type of region6_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region6
+         */
+        uint32_t region6_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region6_addr_end_reg_t;
+
+/** Type of region7_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region7_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region7
+         */
+        uint32_t region7_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region7_addr_start_reg_t;
+
+/** Type of region7_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region7
+         */
+        uint32_t region7_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region7_addr_end_reg_t;
+
+/** Type of region8_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region8_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region8
+         */
+        uint32_t region8_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region8_addr_start_reg_t;
+
+/** Type of region8_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region8
+         */
+        uint32_t region8_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region8_addr_end_reg_t;
+
+/** Type of region9_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region9_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region9
+         */
+        uint32_t region9_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region9_addr_start_reg_t;
+
+/** Type of region9_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region9
+         */
+        uint32_t region9_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region9_addr_end_reg_t;
+
+/** Type of region10_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region10_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region10
+         */
+        uint32_t region10_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region10_addr_start_reg_t;
+
+/** Type of region10_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region10
+         */
+        uint32_t region10_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region10_addr_end_reg_t;
+
+/** Type of region11_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region11_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region11
+         */
+        uint32_t region11_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region11_addr_start_reg_t;
+
+/** Type of region11_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region11
+         */
+        uint32_t region11_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region11_addr_end_reg_t;
+
+/** Type of region12_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region12_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region12
+         */
+        uint32_t region12_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region12_addr_start_reg_t;
+
+/** Type of region12_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region12
+         */
+        uint32_t region12_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region12_addr_end_reg_t;
+
+/** Type of region13_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region13_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region13
+         */
+        uint32_t region13_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region13_addr_start_reg_t;
+
+/** Type of region13_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region13
+         */
+        uint32_t region13_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region13_addr_end_reg_t;
+
+/** Type of region14_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region14_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region14
+         */
+        uint32_t region14_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region14_addr_start_reg_t;
+
+/** Type of region14_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region14
+         */
+        uint32_t region14_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region14_addr_end_reg_t;
+
+/** Type of region15_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region15_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region15
+         */
+        uint32_t region15_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_region15_addr_start_reg_t;
+
+/** Type of region15_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region15
+         */
+        uint32_t region15_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_region15_addr_end_reg_t;
+
+
+/** Group: Region access authority attribute register */
+/** Type of region0_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_x:1;
+        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_w:1;
+        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_x:1;
+        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_w:1;
+        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_x:1;
+        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_w:1;
+        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region0_pms_attr_reg_t;
+
+/** Type of region1_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_x:1;
+        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_w:1;
+        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_x:1;
+        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_w:1;
+        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_x:1;
+        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_w:1;
+        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region1_pms_attr_reg_t;
+
+/** Type of region2_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_x:1;
+        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_w:1;
+        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_x:1;
+        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_w:1;
+        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_x:1;
+        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_w:1;
+        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region2_pms_attr_reg_t;
+
+/** Type of region3_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_x:1;
+        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_w:1;
+        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_x:1;
+        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_w:1;
+        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_x:1;
+        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_w:1;
+        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region3_pms_attr_reg_t;
+
+/** Type of region4_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region4_r0_pms_x:1;
+        /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region4_r0_pms_w:1;
+        /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region4_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region4_r1_pms_x:1;
+        /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region4_r1_pms_w:1;
+        /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region4_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region4_r2_pms_x:1;
+        /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region4_r2_pms_w:1;
+        /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region4_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region4_pms_attr_reg_t;
+
+/** Type of region5_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region5_r0_pms_x:1;
+        /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region5_r0_pms_w:1;
+        /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region5_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region5_r1_pms_x:1;
+        /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region5_r1_pms_w:1;
+        /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region5_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region5_r2_pms_x:1;
+        /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region5_r2_pms_w:1;
+        /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region5_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region5_pms_attr_reg_t;
+
+/** Type of region6_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region6_r0_pms_x:1;
+        /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region6_r0_pms_w:1;
+        /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region6_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region6_r1_pms_x:1;
+        /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region6_r1_pms_w:1;
+        /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region6_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region6_r2_pms_x:1;
+        /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region6_r2_pms_w:1;
+        /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region6_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region6_pms_attr_reg_t;
+
+/** Type of region7_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region7_r0_pms_x:1;
+        /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region7_r0_pms_w:1;
+        /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region7_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region7_r1_pms_x:1;
+        /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region7_r1_pms_w:1;
+        /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region7_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region7_r2_pms_x:1;
+        /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region7_r2_pms_w:1;
+        /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region7_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region7_pms_attr_reg_t;
+
+/** Type of region8_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region8_r0_pms_x:1;
+        /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region8_r0_pms_w:1;
+        /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region8_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region8_r1_pms_x:1;
+        /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region8_r1_pms_w:1;
+        /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region8_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region8_r2_pms_x:1;
+        /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region8_r2_pms_w:1;
+        /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region8_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region8_pms_attr_reg_t;
+
+/** Type of region9_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region9_r0_pms_x:1;
+        /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region9_r0_pms_w:1;
+        /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region9_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region9_r1_pms_x:1;
+        /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region9_r1_pms_w:1;
+        /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region9_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region9_r2_pms_x:1;
+        /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region9_r2_pms_w:1;
+        /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region9_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region9_pms_attr_reg_t;
+
+/** Type of region10_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region10_r0_pms_x:1;
+        /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region10_r0_pms_w:1;
+        /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region10_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region10_r1_pms_x:1;
+        /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region10_r1_pms_w:1;
+        /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region10_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region10_r2_pms_x:1;
+        /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region10_r2_pms_w:1;
+        /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region10_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region10_pms_attr_reg_t;
+
+/** Type of region11_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region11_r0_pms_x:1;
+        /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region11_r0_pms_w:1;
+        /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region11_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region11_r1_pms_x:1;
+        /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region11_r1_pms_w:1;
+        /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region11_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region11_r2_pms_x:1;
+        /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region11_r2_pms_w:1;
+        /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region11_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region11_pms_attr_reg_t;
+
+/** Type of region12_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region12_r0_pms_x:1;
+        /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region12_r0_pms_w:1;
+        /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region12_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region12_r1_pms_x:1;
+        /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region12_r1_pms_w:1;
+        /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region12_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region12_r2_pms_x:1;
+        /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region12_r2_pms_w:1;
+        /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region12_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region12_pms_attr_reg_t;
+
+/** Type of region13_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region13_r0_pms_x:1;
+        /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region13_r0_pms_w:1;
+        /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region13_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region13_r1_pms_x:1;
+        /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region13_r1_pms_w:1;
+        /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region13_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region13_r2_pms_x:1;
+        /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region13_r2_pms_w:1;
+        /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region13_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region13_pms_attr_reg_t;
+
+/** Type of region14_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region14_r0_pms_x:1;
+        /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region14_r0_pms_w:1;
+        /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region14_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region14_r1_pms_x:1;
+        /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region14_r1_pms_w:1;
+        /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region14_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region14_r2_pms_x:1;
+        /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region14_r2_pms_w:1;
+        /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region14_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region14_pms_attr_reg_t;
+
+/** Type of region15_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region15_r0_pms_x:1;
+        /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region15_r0_pms_w:1;
+        /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region15_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region15_r1_pms_x:1;
+        /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region15_r1_pms_w:1;
+        /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region15_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region15_r2_pms_x:1;
+        /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region15_r2_pms_w:1;
+        /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region15_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_apm_region15_pms_attr_reg_t;
+
+
+/** Group: PMS function control register */
+/** Type of func_ctrl register
+ *  PMS function control register
+ */
+typedef union {
+    struct {
+        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
+         *  PMS M0 function enable
+         */
+        uint32_t m0_pms_func_en:1;
+        /** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
+         *  PMS M1 function enable
+         */
+        uint32_t m1_pms_func_en:1;
+        /** m2_pms_func_en : R/W; bitpos: [2]; default: 1;
+         *  PMS M2 function enable
+         */
+        uint32_t m2_pms_func_en:1;
+        /** m3_pms_func_en : R/W; bitpos: [3]; default: 1;
+         *  PMS M3 function enable
+         */
+        uint32_t m3_pms_func_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_apm_func_ctrl_reg_t;
+
+
+/** Group: M0 status register */
+/** Type of m0_status register
+ *  M0 status register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Exception status
+         */
+        uint32_t m0_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m0_status_reg_t;
+
+
+/** Group: M0 status clear register */
+/** Type of m0_status_clr register
+ *  M0 status clear register
+ */
+typedef union {
+    struct {
+        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
+         *  Clear exception status
+         */
+        uint32_t m0_region_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m0_status_clr_reg_t;
+
+
+/** Group: M0 exception_info0 register */
+/** Type of m0_exception_info0 register
+ *  M0 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Exception region
+         */
+        uint32_t m0_exception_region:16;
+        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Exception mode
+         */
+        uint32_t m0_exception_mode:2;
+        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Exception id information
+         */
+        uint32_t m0_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_apm_m0_exception_info0_reg_t;
+
+
+/** Group: M0 exception_info1 register */
+/** Type of m0_exception_info1 register
+ *  M0 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Exception addr
+         */
+        uint32_t m0_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m0_exception_info1_reg_t;
+
+
+/** Group: M1 status register */
+/** Type of m1_status register
+ *  M1 status register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Exception status
+         */
+        uint32_t m1_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m1_status_reg_t;
+
+
+/** Group: M1 status clear register */
+/** Type of m1_status_clr register
+ *  M1 status clear register
+ */
+typedef union {
+    struct {
+        /** m1_region_status_clr : WT; bitpos: [0]; default: 0;
+         *  Clear exception status
+         */
+        uint32_t m1_region_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m1_status_clr_reg_t;
+
+
+/** Group: M1 exception_info0 register */
+/** Type of m1_exception_info0 register
+ *  M1 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Exception region
+         */
+        uint32_t m1_exception_region:16;
+        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Exception mode
+         */
+        uint32_t m1_exception_mode:2;
+        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Exception id information
+         */
+        uint32_t m1_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_apm_m1_exception_info0_reg_t;
+
+
+/** Group: M1 exception_info1 register */
+/** Type of m1_exception_info1 register
+ *  M1 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Exception addr
+         */
+        uint32_t m1_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m1_exception_info1_reg_t;
+
+
+/** Group: M2 status register */
+/** Type of m2_status register
+ *  M2 status register
+ */
+typedef union {
+    struct {
+        /** m2_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Exception status
+         */
+        uint32_t m2_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m2_status_reg_t;
+
+
+/** Group: M2 status clear register */
+/** Type of m2_status_clr register
+ *  M2 status clear register
+ */
+typedef union {
+    struct {
+        /** m2_region_status_clr : WT; bitpos: [0]; default: 0;
+         *  Clear exception status
+         */
+        uint32_t m2_region_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m2_status_clr_reg_t;
+
+
+/** Group: M2 exception_info0 register */
+/** Type of m2_exception_info0 register
+ *  M2 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Exception region
+         */
+        uint32_t m2_exception_region:16;
+        /** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Exception mode
+         */
+        uint32_t m2_exception_mode:2;
+        /** m2_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Exception id information
+         */
+        uint32_t m2_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_apm_m2_exception_info0_reg_t;
+
+
+/** Group: M2 exception_info1 register */
+/** Type of m2_exception_info1 register
+ *  M2 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Exception addr
+         */
+        uint32_t m2_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m2_exception_info1_reg_t;
+
+
+/** Group: M3 status register */
+/** Type of m3_status register
+ *  M3 status register
+ */
+typedef union {
+    struct {
+        /** m3_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Exception status
+         */
+        uint32_t m3_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m3_status_reg_t;
+
+
+/** Group: M3 status clear register */
+/** Type of m3_status_clr register
+ *  M3 status clear register
+ */
+typedef union {
+    struct {
+        /** m3_region_status_clr : WT; bitpos: [0]; default: 0;
+         *  Clear exception status
+         */
+        uint32_t m3_region_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m3_status_clr_reg_t;
+
+
+/** Group: M3 exception_info0 register */
+/** Type of m3_exception_info0 register
+ *  M3 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Exception region
+         */
+        uint32_t m3_exception_region:16;
+        /** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Exception mode
+         */
+        uint32_t m3_exception_mode:2;
+        /** m3_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Exception id information
+         */
+        uint32_t m3_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_apm_m3_exception_info0_reg_t;
+
+
+/** Group: M3 exception_info1 register */
+/** Type of m3_exception_info1 register
+ *  M3 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Exception addr
+         */
+        uint32_t m3_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m3_exception_info1_reg_t;
+
+
+/** Group: APM interrupt enable register */
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
+         *  APM M0 interrupt enable
+         */
+        uint32_t m0_apm_int_en:1;
+        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
+         *  APM M1 interrupt enable
+         */
+        uint32_t m1_apm_int_en:1;
+        /** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
+         *  APM M2 interrupt enable
+         */
+        uint32_t m2_apm_int_en:1;
+        /** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
+         *  APM M3 interrupt enable
+         */
+        uint32_t m3_apm_int_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_apm_int_en_reg_t;
+
+
+/** Group: clock gating register */
+/** Type of clock_gate register
+ *  clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reg_clk_en
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35672640;
+         *  reg_date
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_apm_date_reg_t;
+
+
+typedef struct hp_apm_dev_t {
+    volatile hp_apm_region_filter_en_reg_t region_filter_en;
+    volatile hp_apm_region0_addr_start_reg_t region0_addr_start;
+    volatile hp_apm_region0_addr_end_reg_t region0_addr_end;
+    volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr;
+    volatile hp_apm_region1_addr_start_reg_t region1_addr_start;
+    volatile hp_apm_region1_addr_end_reg_t region1_addr_end;
+    volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr;
+    volatile hp_apm_region2_addr_start_reg_t region2_addr_start;
+    volatile hp_apm_region2_addr_end_reg_t region2_addr_end;
+    volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr;
+    volatile hp_apm_region3_addr_start_reg_t region3_addr_start;
+    volatile hp_apm_region3_addr_end_reg_t region3_addr_end;
+    volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr;
+    volatile hp_apm_region4_addr_start_reg_t region4_addr_start;
+    volatile hp_apm_region4_addr_end_reg_t region4_addr_end;
+    volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr;
+    volatile hp_apm_region5_addr_start_reg_t region5_addr_start;
+    volatile hp_apm_region5_addr_end_reg_t region5_addr_end;
+    volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr;
+    volatile hp_apm_region6_addr_start_reg_t region6_addr_start;
+    volatile hp_apm_region6_addr_end_reg_t region6_addr_end;
+    volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr;
+    volatile hp_apm_region7_addr_start_reg_t region7_addr_start;
+    volatile hp_apm_region7_addr_end_reg_t region7_addr_end;
+    volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr;
+    volatile hp_apm_region8_addr_start_reg_t region8_addr_start;
+    volatile hp_apm_region8_addr_end_reg_t region8_addr_end;
+    volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr;
+    volatile hp_apm_region9_addr_start_reg_t region9_addr_start;
+    volatile hp_apm_region9_addr_end_reg_t region9_addr_end;
+    volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr;
+    volatile hp_apm_region10_addr_start_reg_t region10_addr_start;
+    volatile hp_apm_region10_addr_end_reg_t region10_addr_end;
+    volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr;
+    volatile hp_apm_region11_addr_start_reg_t region11_addr_start;
+    volatile hp_apm_region11_addr_end_reg_t region11_addr_end;
+    volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr;
+    volatile hp_apm_region12_addr_start_reg_t region12_addr_start;
+    volatile hp_apm_region12_addr_end_reg_t region12_addr_end;
+    volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr;
+    volatile hp_apm_region13_addr_start_reg_t region13_addr_start;
+    volatile hp_apm_region13_addr_end_reg_t region13_addr_end;
+    volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr;
+    volatile hp_apm_region14_addr_start_reg_t region14_addr_start;
+    volatile hp_apm_region14_addr_end_reg_t region14_addr_end;
+    volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr;
+    volatile hp_apm_region15_addr_start_reg_t region15_addr_start;
+    volatile hp_apm_region15_addr_end_reg_t region15_addr_end;
+    volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr;
+    volatile hp_apm_func_ctrl_reg_t func_ctrl;
+    volatile hp_apm_m0_status_reg_t m0_status;
+    volatile hp_apm_m0_status_clr_reg_t m0_status_clr;
+    volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0;
+    volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1;
+    volatile hp_apm_m1_status_reg_t m1_status;
+    volatile hp_apm_m1_status_clr_reg_t m1_status_clr;
+    volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0;
+    volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1;
+    volatile hp_apm_m2_status_reg_t m2_status;
+    volatile hp_apm_m2_status_clr_reg_t m2_status_clr;
+    volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0;
+    volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1;
+    volatile hp_apm_m3_status_reg_t m3_status;
+    volatile hp_apm_m3_status_clr_reg_t m3_status_clr;
+    volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0;
+    volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1;
+    volatile hp_apm_int_en_reg_t int_en;
+    volatile hp_apm_clock_gate_reg_t clock_gate;
+    uint32_t reserved_110[443];
+    volatile hp_apm_date_reg_t date;
+} hp_apm_dev_t;
+
+extern hp_apm_dev_t HP_APM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/hp_clkrst_reg.h b/components/soc/esp32p4/include/soc/hp_clkrst_reg.h
new file mode 100644
index 0000000000..661563894f
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hp_clkrst_reg.h
@@ -0,0 +1,629 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_HP_CLKRST_REG_H_
+#define _SOC_HP_CLKRST_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define HP_CLKRST_VER_DATE_REG          (DR_REG_HP_CLKRST_BASE + 0x0)
+/* HP_CLKRST_VER_DATE : R/W ;bitpos:[31:0] ;default: 32'h20201229 ; */
+/*description: .*/
+#define HP_CLKRST_VER_DATE    0xFFFFFFFF
+#define HP_CLKRST_VER_DATE_M  ((HP_CLKRST_VER_DATE_V)<<(HP_CLKRST_VER_DATE_S))
+#define HP_CLKRST_VER_DATE_V  0xFFFFFFFF
+#define HP_CLKRST_VER_DATE_S  0
+
+#define HP_CLKRST_HP_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x4)
+/* HP_CLKRST_HP_CPU_ROOT_CLK_SEL : R/W ;bitpos:[3:2] ;default: 2'h1 ; */
+/*description: Hp cpu root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP CPU
+PLL clock; 2'h3: HP system PLL clock.*/
+#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL    0x00000003
+#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_M  ((HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S))
+#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V  0x3
+#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S  2
+/* HP_CLKRST_HP_SYS_ROOT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */
+/*description: Hp system root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP s
+ystem PLL clock; 2'h3: HP CPU PLL clock.*/
+#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL    0x00000003
+#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_M  ((HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S))
+#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V  0x3
+#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S  0
+
+#define HP_CLKRST_CPU_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x8)
+/* HP_CLKRST_CPU_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM    0x000000FF
+#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S))
+#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V  0xFF
+#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S  24
+/* HP_CLKRST_CPU_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define HP_CLKRST_CPU_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_CPU_CLK_DIV_NUM_M  ((HP_CLKRST_CPU_CLK_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_DIV_NUM_S))
+#define HP_CLKRST_CPU_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_CPU_CLK_DIV_NUM_S  8
+/* HP_CLKRST_CPU_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define HP_CLKRST_CPU_CLK_EN    (BIT(0))
+#define HP_CLKRST_CPU_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_CPU_CLK_EN_V  0x1
+#define HP_CLKRST_CPU_CLK_EN_S  0
+
+#define HP_CLKRST_SYS_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0xC)
+/* HP_CLKRST_SYS_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM    0x000000FF
+#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S))
+#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V  0xFF
+#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S  24
+/* HP_CLKRST_SYS_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: phase offset compare to clock sync signal.*/
+#define HP_CLKRST_SYS_CLK_PHASE_OFFSET    0x000000FF
+#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_M  ((HP_CLKRST_SYS_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_SYS_CLK_PHASE_OFFSET_S))
+#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_V  0xFF
+#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_S  16
+/* HP_CLKRST_SYS_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define HP_CLKRST_SYS_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_SYS_CLK_DIV_NUM_M  ((HP_CLKRST_SYS_CLK_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_DIV_NUM_S))
+#define HP_CLKRST_SYS_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_SYS_CLK_DIV_NUM_S  8
+/* HP_CLKRST_SYS_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN    (BIT(2))
+#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_V  0x1
+#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_S  2
+/* HP_CLKRST_SYS_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define HP_CLKRST_SYS_CLK_SYNC_EN    (BIT(1))
+#define HP_CLKRST_SYS_CLK_SYNC_EN_M  (BIT(1))
+#define HP_CLKRST_SYS_CLK_SYNC_EN_V  0x1
+#define HP_CLKRST_SYS_CLK_SYNC_EN_S  1
+/* HP_CLKRST_SYS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define HP_CLKRST_SYS_CLK_EN    (BIT(0))
+#define HP_CLKRST_SYS_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_SYS_CLK_EN_V  0x1
+#define HP_CLKRST_SYS_CLK_EN_S  0
+
+#define HP_CLKRST_PERI1_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x10)
+/* HP_CLKRST_PERI1_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM    0x000000FF
+#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S))
+#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V  0xFF
+#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S  24
+/* HP_CLKRST_PERI1_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: phase offset compare to clock sync signal.*/
+#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET    0x000000FF
+#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_M  ((HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S))
+#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V  0xFF
+#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S  16
+/* HP_CLKRST_PERI1_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define HP_CLKRST_PERI1_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_PERI1_CLK_DIV_NUM_M  ((HP_CLKRST_PERI1_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_DIV_NUM_S))
+#define HP_CLKRST_PERI1_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_PERI1_CLK_DIV_NUM_S  8
+/* HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN    (BIT(2))
+#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_V  0x1
+#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_S  2
+/* HP_CLKRST_PERI1_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define HP_CLKRST_PERI1_CLK_SYNC_EN    (BIT(1))
+#define HP_CLKRST_PERI1_CLK_SYNC_EN_M  (BIT(1))
+#define HP_CLKRST_PERI1_CLK_SYNC_EN_V  0x1
+#define HP_CLKRST_PERI1_CLK_SYNC_EN_S  1
+/* HP_CLKRST_PERI1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define HP_CLKRST_PERI1_CLK_EN    (BIT(0))
+#define HP_CLKRST_PERI1_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_PERI1_CLK_EN_V  0x1
+#define HP_CLKRST_PERI1_CLK_EN_S  0
+
+#define HP_CLKRST_PERI2_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x14)
+/* HP_CLKRST_PERI2_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM    0x000000FF
+#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S))
+#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V  0xFF
+#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S  24
+/* HP_CLKRST_PERI2_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: phase offset compare to clock sync signal.*/
+#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET    0x000000FF
+#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_M  ((HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S))
+#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V  0xFF
+#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S  16
+/* HP_CLKRST_PERI2_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define HP_CLKRST_PERI2_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_PERI2_CLK_DIV_NUM_M  ((HP_CLKRST_PERI2_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_DIV_NUM_S))
+#define HP_CLKRST_PERI2_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_PERI2_CLK_DIV_NUM_S  8
+/* HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN    (BIT(2))
+#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_V  0x1
+#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_S  2
+/* HP_CLKRST_PERI2_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define HP_CLKRST_PERI2_CLK_SYNC_EN    (BIT(1))
+#define HP_CLKRST_PERI2_CLK_SYNC_EN_M  (BIT(1))
+#define HP_CLKRST_PERI2_CLK_SYNC_EN_V  0x1
+#define HP_CLKRST_PERI2_CLK_SYNC_EN_S  1
+/* HP_CLKRST_PERI2_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define HP_CLKRST_PERI2_CLK_EN    (BIT(0))
+#define HP_CLKRST_PERI2_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_PERI2_CLK_EN_V  0x1
+#define HP_CLKRST_PERI2_CLK_EN_S  0
+
+#define HP_CLKRST_PSRAM_PHY_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x18)
+/* HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM    0x000000FF
+#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S))
+#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V  0xFF
+#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S  24
+/* HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: .*/
+#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_M  ((HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S))
+#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S  8
+/* HP_CLKRST_PSRAM_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */
+/*description: .*/
+#define HP_CLKRST_PSRAM_PHY_CLK_SEL    0x00000003
+#define HP_CLKRST_PSRAM_PHY_CLK_SEL_M  ((HP_CLKRST_PSRAM_PHY_CLK_SEL_V)<<(HP_CLKRST_PSRAM_PHY_CLK_SEL_S))
+#define HP_CLKRST_PSRAM_PHY_CLK_SEL_V  0x3
+#define HP_CLKRST_PSRAM_PHY_CLK_SEL_S  1
+/* HP_CLKRST_PSRAM_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define HP_CLKRST_PSRAM_PHY_CLK_EN    (BIT(0))
+#define HP_CLKRST_PSRAM_PHY_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_PSRAM_PHY_CLK_EN_V  0x1
+#define HP_CLKRST_PSRAM_PHY_CLK_EN_S  0
+
+#define HP_CLKRST_DDR_PHY_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x1C)
+/* HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM    0x000000FF
+#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S))
+#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V  0xFF
+#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S  24
+/* HP_CLKRST_DDR_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: .*/
+#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_M  ((HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S))
+#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S  8
+/* HP_CLKRST_DDR_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */
+/*description: .*/
+#define HP_CLKRST_DDR_PHY_CLK_SEL    0x00000003
+#define HP_CLKRST_DDR_PHY_CLK_SEL_M  ((HP_CLKRST_DDR_PHY_CLK_SEL_V)<<(HP_CLKRST_DDR_PHY_CLK_SEL_S))
+#define HP_CLKRST_DDR_PHY_CLK_SEL_V  0x3
+#define HP_CLKRST_DDR_PHY_CLK_SEL_S  1
+/* HP_CLKRST_DDR_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define HP_CLKRST_DDR_PHY_CLK_EN    (BIT(0))
+#define HP_CLKRST_DDR_PHY_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_DDR_PHY_CLK_EN_V  0x1
+#define HP_CLKRST_DDR_PHY_CLK_EN_S  0
+
+#define HP_CLKRST_MSPI_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x20)
+/* HP_CLKRST_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */
+/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/
+#define HP_CLKRST_MSPI_SRC_CLK_SEL    0x00000003
+#define HP_CLKRST_MSPI_SRC_CLK_SEL_M  ((HP_CLKRST_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_MSPI_SRC_CLK_SEL_S))
+#define HP_CLKRST_MSPI_SRC_CLK_SEL_V  0x3
+#define HP_CLKRST_MSPI_SRC_CLK_SEL_S  16
+/* HP_CLKRST_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */
+/*description: clock divider number.*/
+#define HP_CLKRST_MSPI_CLK_DIV_NUM    0x0000000F
+#define HP_CLKRST_MSPI_CLK_DIV_NUM_M  ((HP_CLKRST_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_MSPI_CLK_DIV_NUM_S))
+#define HP_CLKRST_MSPI_CLK_DIV_NUM_V  0xF
+#define HP_CLKRST_MSPI_CLK_DIV_NUM_S  8
+/* HP_CLKRST_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define HP_CLKRST_MSPI_CLK_EN    (BIT(0))
+#define HP_CLKRST_MSPI_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_MSPI_CLK_EN_V  0x1
+#define HP_CLKRST_MSPI_CLK_EN_S  0
+
+#define HP_CLKRST_DUAL_MSPI_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x24)
+/* HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */
+/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/
+#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL    0x00000003
+#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_M  ((HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S))
+#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V  0x3
+#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S  16
+/* HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */
+/*description: clock divider number.*/
+#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM    0x0000000F
+#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_M  ((HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S))
+#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V  0xF
+#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S  8
+/* HP_CLKRST_DUAL_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define HP_CLKRST_DUAL_MSPI_CLK_EN    (BIT(0))
+#define HP_CLKRST_DUAL_MSPI_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_DUAL_MSPI_CLK_EN_V  0x1
+#define HP_CLKRST_DUAL_MSPI_CLK_EN_S  0
+
+#define HP_CLKRST_REF_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x28)
+/* HP_CLKRST_REF_CLK2_DIV_NUM : R/W ;bitpos:[27:24] ;default: 4'h3 ; */
+/*description: 120MHz reference clock divider number, used by i3c master.*/
+#define HP_CLKRST_REF_CLK2_DIV_NUM    0x0000000F
+#define HP_CLKRST_REF_CLK2_DIV_NUM_M  ((HP_CLKRST_REF_CLK2_DIV_NUM_V)<<(HP_CLKRST_REF_CLK2_DIV_NUM_S))
+#define HP_CLKRST_REF_CLK2_DIV_NUM_V  0xF
+#define HP_CLKRST_REF_CLK2_DIV_NUM_S  24
+/* HP_CLKRST_USBPHY_CLK_DIV_NUM : R/W ;bitpos:[23:20] ;default: 4'h9 ; */
+/*description: usbphy clock divider number.*/
+#define HP_CLKRST_USBPHY_CLK_DIV_NUM    0x0000000F
+#define HP_CLKRST_USBPHY_CLK_DIV_NUM_M  ((HP_CLKRST_USBPHY_CLK_DIV_NUM_V)<<(HP_CLKRST_USBPHY_CLK_DIV_NUM_S))
+#define HP_CLKRST_USBPHY_CLK_DIV_NUM_V  0xF
+#define HP_CLKRST_USBPHY_CLK_DIV_NUM_S  20
+/* HP_CLKRST_LEDC_REF_CLK_DIV_NUM : R/W ;bitpos:[19:16] ;default: 4'h1 ; */
+/*description: ledc reference clock divider number.*/
+#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM    0x0000000F
+#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_M  ((HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S))
+#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V  0xF
+#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S  16
+/* HP_CLKRST_USB2_REF_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h27 ; */
+/*description: usb2 phy reference clock divider number.*/
+#define HP_CLKRST_USB2_REF_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_M  ((HP_CLKRST_USB2_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_USB2_REF_CLK_DIV_NUM_S))
+#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_S  8
+/* HP_CLKRST_REF_CLK_DIV_NUM : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
+/*description: reference clock divider number.*/
+#define HP_CLKRST_REF_CLK_DIV_NUM    0x0000000F
+#define HP_CLKRST_REF_CLK_DIV_NUM_M  ((HP_CLKRST_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_REF_CLK_DIV_NUM_S))
+#define HP_CLKRST_REF_CLK_DIV_NUM_V  0xF
+#define HP_CLKRST_REF_CLK_DIV_NUM_S  1
+/* HP_CLKRST_REF_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reference clock output enable.*/
+#define HP_CLKRST_REF_CLK_EN    (BIT(0))
+#define HP_CLKRST_REF_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_REF_CLK_EN_V  0x1
+#define HP_CLKRST_REF_CLK_EN_S  0
+
+#define HP_CLKRST_TM_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x2C)
+/* HP_CLKRST_TM_240M_CLK_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: 240M test mode clock enable.*/
+#define HP_CLKRST_TM_240M_CLK_EN    (BIT(7))
+#define HP_CLKRST_TM_240M_CLK_EN_M  (BIT(7))
+#define HP_CLKRST_TM_240M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_240M_CLK_EN_S  7
+/* HP_CLKRST_TM_200M_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: 200M test mode clock enable.*/
+#define HP_CLKRST_TM_200M_CLK_EN    (BIT(6))
+#define HP_CLKRST_TM_200M_CLK_EN_M  (BIT(6))
+#define HP_CLKRST_TM_200M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_200M_CLK_EN_S  6
+/* HP_CLKRST_TM_160M_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: 160M test mode clock enable.*/
+#define HP_CLKRST_TM_160M_CLK_EN    (BIT(5))
+#define HP_CLKRST_TM_160M_CLK_EN_M  (BIT(5))
+#define HP_CLKRST_TM_160M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_160M_CLK_EN_S  5
+/* HP_CLKRST_TM_120M_CLK_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: 120M test mode clock enable.*/
+#define HP_CLKRST_TM_120M_CLK_EN    (BIT(4))
+#define HP_CLKRST_TM_120M_CLK_EN_M  (BIT(4))
+#define HP_CLKRST_TM_120M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_120M_CLK_EN_S  4
+/* HP_CLKRST_TM_80M_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: 80M test mode clock enable.*/
+#define HP_CLKRST_TM_80M_CLK_EN    (BIT(3))
+#define HP_CLKRST_TM_80M_CLK_EN_M  (BIT(3))
+#define HP_CLKRST_TM_80M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_80M_CLK_EN_S  3
+/* HP_CLKRST_TM_48M_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: 48M test mode clock enable.*/
+#define HP_CLKRST_TM_48M_CLK_EN    (BIT(2))
+#define HP_CLKRST_TM_48M_CLK_EN_M  (BIT(2))
+#define HP_CLKRST_TM_48M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_48M_CLK_EN_S  2
+/* HP_CLKRST_TM_40M_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: 40M test mode clock enable.*/
+#define HP_CLKRST_TM_40M_CLK_EN    (BIT(1))
+#define HP_CLKRST_TM_40M_CLK_EN_M  (BIT(1))
+#define HP_CLKRST_TM_40M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_40M_CLK_EN_S  1
+/* HP_CLKRST_TM_20M_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 20M test mode clock enabl.*/
+#define HP_CLKRST_TM_20M_CLK_EN    (BIT(0))
+#define HP_CLKRST_TM_20M_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_TM_20M_CLK_EN_V  0x1
+#define HP_CLKRST_TM_20M_CLK_EN_S  0
+
+#define HP_CLKRST_CORE_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x30)
+/* HP_CLKRST_CORE0_GLOBAL_RSTN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: core0 software global reset.*/
+#define HP_CLKRST_CORE0_GLOBAL_RSTN    (BIT(9))
+#define HP_CLKRST_CORE0_GLOBAL_RSTN_M  (BIT(9))
+#define HP_CLKRST_CORE0_GLOBAL_RSTN_V  0x1
+#define HP_CLKRST_CORE0_GLOBAL_RSTN_S  9
+/* HP_CLKRST_CORE1_GLOBAL_RSTN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: core1 software global reset.*/
+#define HP_CLKRST_CORE1_GLOBAL_RSTN    (BIT(8))
+#define HP_CLKRST_CORE1_GLOBAL_RSTN_M  (BIT(8))
+#define HP_CLKRST_CORE1_GLOBAL_RSTN_V  0x1
+#define HP_CLKRST_CORE1_GLOBAL_RSTN_S  8
+/* HP_CLKRST_CORE0_FORCE_NORST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define HP_CLKRST_CORE0_FORCE_NORST    (BIT(7))
+#define HP_CLKRST_CORE0_FORCE_NORST_M  (BIT(7))
+#define HP_CLKRST_CORE0_FORCE_NORST_V  0x1
+#define HP_CLKRST_CORE0_FORCE_NORST_S  7
+/* HP_CLKRST_CORE1_FORCE_NORST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define HP_CLKRST_CORE1_FORCE_NORST    (BIT(6))
+#define HP_CLKRST_CORE1_FORCE_NORST_M  (BIT(6))
+#define HP_CLKRST_CORE1_FORCE_NORST_V  0x1
+#define HP_CLKRST_CORE1_FORCE_NORST_S  6
+/* HP_CLKRST_CORE2_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define HP_CLKRST_CORE2_FORCE_NORST    (BIT(5))
+#define HP_CLKRST_CORE2_FORCE_NORST_M  (BIT(5))
+#define HP_CLKRST_CORE2_FORCE_NORST_V  0x1
+#define HP_CLKRST_CORE2_FORCE_NORST_S  5
+/* HP_CLKRST_CORE3_FORCE_NORST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define HP_CLKRST_CORE3_FORCE_NORST    (BIT(4))
+#define HP_CLKRST_CORE3_FORCE_NORST_M  (BIT(4))
+#define HP_CLKRST_CORE3_FORCE_NORST_V  0x1
+#define HP_CLKRST_CORE3_FORCE_NORST_S  4
+/* HP_CLKRST_CORE0_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: hp core0 clock enable.*/
+#define HP_CLKRST_CORE0_CLK_EN    (BIT(3))
+#define HP_CLKRST_CORE0_CLK_EN_M  (BIT(3))
+#define HP_CLKRST_CORE0_CLK_EN_V  0x1
+#define HP_CLKRST_CORE0_CLK_EN_S  3
+/* HP_CLKRST_CORE1_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: hp core1 clock enable.*/
+#define HP_CLKRST_CORE1_CLK_EN    (BIT(2))
+#define HP_CLKRST_CORE1_CLK_EN_M  (BIT(2))
+#define HP_CLKRST_CORE1_CLK_EN_V  0x1
+#define HP_CLKRST_CORE1_CLK_EN_S  2
+/* HP_CLKRST_CORE2_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: hp core2 clock enable.*/
+#define HP_CLKRST_CORE2_CLK_EN    (BIT(1))
+#define HP_CLKRST_CORE2_CLK_EN_M  (BIT(1))
+#define HP_CLKRST_CORE2_CLK_EN_V  0x1
+#define HP_CLKRST_CORE2_CLK_EN_S  1
+/* HP_CLKRST_CORE3_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: hp core3 clock enable.*/
+#define HP_CLKRST_CORE3_CLK_EN    (BIT(0))
+#define HP_CLKRST_CORE3_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_CORE3_CLK_EN_V  0x1
+#define HP_CLKRST_CORE3_CLK_EN_S  0
+
+#define HP_CLKRST_CACHE_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x34)
+/* HP_CLKRST_CACHE_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: L2 cache clock divider number.*/
+#define HP_CLKRST_CACHE_CLK_DIV_NUM    0x000000FF
+#define HP_CLKRST_CACHE_CLK_DIV_NUM_M  ((HP_CLKRST_CACHE_CLK_DIV_NUM_V)<<(HP_CLKRST_CACHE_CLK_DIV_NUM_S))
+#define HP_CLKRST_CACHE_CLK_DIV_NUM_V  0xFF
+#define HP_CLKRST_CACHE_CLK_DIV_NUM_S  8
+/* HP_CLKRST_HP_CACHE_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: cache software reset: low active.*/
+#define HP_CLKRST_HP_CACHE_RSTN    (BIT(2))
+#define HP_CLKRST_HP_CACHE_RSTN_M  (BIT(2))
+#define HP_CLKRST_HP_CACHE_RSTN_V  0x1
+#define HP_CLKRST_HP_CACHE_RSTN_S  2
+/* HP_CLKRST_CACHE_APB_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: cache apb clock enable.*/
+#define HP_CLKRST_CACHE_APB_CLK_EN    (BIT(1))
+#define HP_CLKRST_CACHE_APB_CLK_EN_M  (BIT(1))
+#define HP_CLKRST_CACHE_APB_CLK_EN_V  0x1
+#define HP_CLKRST_CACHE_APB_CLK_EN_S  1
+/* HP_CLKRST_CACHE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: cache clock enable.*/
+#define HP_CLKRST_CACHE_CLK_EN    (BIT(0))
+#define HP_CLKRST_CACHE_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_CACHE_CLK_EN_V  0x1
+#define HP_CLKRST_CACHE_CLK_EN_S  0
+
+#define HP_CLKRST_CPU_PERI_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x38)
+/* HP_CLKRST_L2_MEM_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: l2 memory software reset: low active.*/
+#define HP_CLKRST_L2_MEM_RSTN    (BIT(4))
+#define HP_CLKRST_L2_MEM_RSTN_M  (BIT(4))
+#define HP_CLKRST_L2_MEM_RSTN_V  0x1
+#define HP_CLKRST_L2_MEM_RSTN_S  4
+/* HP_CLKRST_L2_MEM_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: l2 memory clock enable.*/
+#define HP_CLKRST_L2_MEM_CLK_EN    (BIT(3))
+#define HP_CLKRST_L2_MEM_CLK_EN_M  (BIT(3))
+#define HP_CLKRST_L2_MEM_CLK_EN_V  0x1
+#define HP_CLKRST_L2_MEM_CLK_EN_S  3
+/* HP_CLKRST_TCM_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: tcm software reset: low active.*/
+#define HP_CLKRST_TCM_RSTN    (BIT(2))
+#define HP_CLKRST_TCM_RSTN_M  (BIT(2))
+#define HP_CLKRST_TCM_RSTN_V  0x1
+#define HP_CLKRST_TCM_RSTN_S  2
+/* HP_CLKRST_TCM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: tcm clock enable.*/
+#define HP_CLKRST_TCM_CLK_EN    (BIT(1))
+#define HP_CLKRST_TCM_CLK_EN_M  (BIT(1))
+#define HP_CLKRST_TCM_CLK_EN_V  0x1
+#define HP_CLKRST_TCM_CLK_EN_S  1
+/* HP_CLKRST_CPU_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: cpu control logic clock enable.*/
+#define HP_CLKRST_CPU_CTRL_CLK_EN    (BIT(0))
+#define HP_CLKRST_CPU_CTRL_CLK_EN_M  (BIT(0))
+#define HP_CLKRST_CPU_CTRL_CLK_EN_V  0x1
+#define HP_CLKRST_CPU_CTRL_CLK_EN_S  0
+
+#define HP_CLKRST_SYNC_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x3C)
+/* HP_CLKRST_CLK_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: .*/
+#define HP_CLKRST_CLK_EN    (BIT(17))
+#define HP_CLKRST_CLK_EN_M  (BIT(17))
+#define HP_CLKRST_CLK_EN_V  0x1
+#define HP_CLKRST_CLK_EN_S  17
+/* HP_CLKRST_HP_ROOT_CLK_SYNC_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: clock sync signal output enable.*/
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN    (BIT(16))
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_M  (BIT(16))
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_V  0x1
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_S  16
+/* HP_CLKRST_HP_ROOT_CLK_SYNC_PERID : R/W ;bitpos:[15:0] ;default: 16'h347 ; */
+/*description: clock sync signal generation period.*/
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID    0x0000FFFF
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_M  ((HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V)<<(HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S))
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V  0xFFFF
+#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S  0
+
+#define HP_CLKRST_WFI_GATE_CLK_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x40)
+/* HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: force group3(L2 Memory) clock on after WFI.*/
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON    (BIT(18))
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_M  (BIT(18))
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_V  0x1
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_S  18
+/* HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: force group2(HP TCM) clock on after WFI.*/
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON    (BIT(17))
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_M  (BIT(17))
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_V  0x1
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_S  17
+/* HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: force group1(L1/L2 cache & trace & cpu_icm_ibus) clock on after WFI.*/
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON    (BIT(16))
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_M  (BIT(16))
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_V  0x1
+#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_S  16
+/* HP_CLKRST_CPU_WFI_DELAY_NUM : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: This register indicates delayed clock cycles before auto gating HP cache/trace c
+lock once WFI asserted.*/
+#define HP_CLKRST_CPU_WFI_DELAY_NUM    0x0000000F
+#define HP_CLKRST_CPU_WFI_DELAY_NUM_M  ((HP_CLKRST_CPU_WFI_DELAY_NUM_V)<<(HP_CLKRST_CPU_WFI_DELAY_NUM_S))
+#define HP_CLKRST_CPU_WFI_DELAY_NUM_V  0xF
+#define HP_CLKRST_CPU_WFI_DELAY_NUM_S  0
+
+#define HP_CLKRST_PVT_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x44)
+/* HP_CLKRST_PVT_APB_RSTN : R/W ;bitpos:[21] ;default: 1'h1 ; */
+/*description: pvt apb resetn.*/
+#define HP_CLKRST_PVT_APB_RSTN    (BIT(21))
+#define HP_CLKRST_PVT_APB_RSTN_M  (BIT(21))
+#define HP_CLKRST_PVT_APB_RSTN_V  0x1
+#define HP_CLKRST_PVT_APB_RSTN_S  21
+/* HP_CLKRST_PVT_PERI_GROUP2_RSTN : R/W ;bitpos:[20] ;default: 1'h1 ; */
+/*description: pvt peri group2 resetn.*/
+#define HP_CLKRST_PVT_PERI_GROUP2_RSTN    (BIT(20))
+#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_M  (BIT(20))
+#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_V  0x1
+#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_S  20
+/* HP_CLKRST_PVT_PERI_GROUP1_RSTN : R/W ;bitpos:[19] ;default: 1'h1 ; */
+/*description: pvt peri group1 resetn.*/
+#define HP_CLKRST_PVT_PERI_GROUP1_RSTN    (BIT(19))
+#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_M  (BIT(19))
+#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_V  0x1
+#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_S  19
+/* HP_CLKRST_PVT_CPU_GROUP2_RSTN : R/W ;bitpos:[18] ;default: 1'h1 ; */
+/*description: pvt cpu group2 resetn.*/
+#define HP_CLKRST_PVT_CPU_GROUP2_RSTN    (BIT(18))
+#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_M  (BIT(18))
+#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_V  0x1
+#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_S  18
+/* HP_CLKRST_PVT_CPU_GROUP1_RSTN : R/W ;bitpos:[17] ;default: 1'h1 ; */
+/*description: pvt cpu group1 resetn.*/
+#define HP_CLKRST_PVT_CPU_GROUP1_RSTN    (BIT(17))
+#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_M  (BIT(17))
+#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_V  0x1
+#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_S  17
+/* HP_CLKRST_PVT_TOP_RSTN : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: pvt top resetn.*/
+#define HP_CLKRST_PVT_TOP_RSTN    (BIT(16))
+#define HP_CLKRST_PVT_TOP_RSTN_M  (BIT(16))
+#define HP_CLKRST_PVT_TOP_RSTN_V  0x1
+#define HP_CLKRST_PVT_TOP_RSTN_S  16
+/* HP_CLKRST_PVT_APB_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: pvt apb clk en.*/
+#define HP_CLKRST_PVT_APB_CLK_EN    (BIT(13))
+#define HP_CLKRST_PVT_APB_CLK_EN_M  (BIT(13))
+#define HP_CLKRST_PVT_APB_CLK_EN_V  0x1
+#define HP_CLKRST_PVT_APB_CLK_EN_S  13
+/* HP_CLKRST_PVT_PERI_GROUP2_CLK_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: pvt peri group2 clk en.*/
+#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN    (BIT(12))
+#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_M  (BIT(12))
+#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_V  0x1
+#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_S  12
+/* HP_CLKRST_PVT_PERI_GROUP1_CLK_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: pvt peri group1 clk en.*/
+#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN    (BIT(11))
+#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_M  (BIT(11))
+#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_V  0x1
+#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_S  11
+/* HP_CLKRST_PVT_CPU_GROUP2_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: pvt cpu group2 clk en.*/
+#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN    (BIT(10))
+#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_M  (BIT(10))
+#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_V  0x1
+#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_S  10
+/* HP_CLKRST_PVT_CPU_GROUP1_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: pvt cpu group1 clk en.*/
+#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN    (BIT(9))
+#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_M  (BIT(9))
+#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_V  0x1
+#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_S  9
+/* HP_CLKRST_PVT_TOP_CLK_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: pvt top clock en.*/
+#define HP_CLKRST_PVT_TOP_CLK_EN    (BIT(8))
+#define HP_CLKRST_PVT_TOP_CLK_EN_M  (BIT(8))
+#define HP_CLKRST_PVT_TOP_CLK_EN_V  0x1
+#define HP_CLKRST_PVT_TOP_CLK_EN_S  8
+/* HP_CLKRST_PVT_CLK_DIV_NUM : R/W ;bitpos:[7:4] ;default: 4'h1 ; */
+/*description: pvt clock div number.*/
+#define HP_CLKRST_PVT_CLK_DIV_NUM    0x0000000F
+#define HP_CLKRST_PVT_CLK_DIV_NUM_M  ((HP_CLKRST_PVT_CLK_DIV_NUM_V)<<(HP_CLKRST_PVT_CLK_DIV_NUM_S))
+#define HP_CLKRST_PVT_CLK_DIV_NUM_V  0xF
+#define HP_CLKRST_PVT_CLK_DIV_NUM_S  4
+/* HP_CLKRST_PVT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */
+/*description: pvt clock sel.*/
+#define HP_CLKRST_PVT_CLK_SEL    0x00000003
+#define HP_CLKRST_PVT_CLK_SEL_M  ((HP_CLKRST_PVT_CLK_SEL_V)<<(HP_CLKRST_PVT_CLK_SEL_S))
+#define HP_CLKRST_PVT_CLK_SEL_V  0x3
+#define HP_CLKRST_PVT_CLK_SEL_S  0
+
+#define HP_CLKRST_TEST_PLL_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x48)
+/* HP_CLKRST_TEST_PLL_DIV_NUM : R/W ;bitpos:[27:16] ;default: 12'h3e7 ; */
+/*description: test pll divider number.*/
+#define HP_CLKRST_TEST_PLL_DIV_NUM    0x00000FFF
+#define HP_CLKRST_TEST_PLL_DIV_NUM_M  ((HP_CLKRST_TEST_PLL_DIV_NUM_V)<<(HP_CLKRST_TEST_PLL_DIV_NUM_S))
+#define HP_CLKRST_TEST_PLL_DIV_NUM_V  0xFFF
+#define HP_CLKRST_TEST_PLL_DIV_NUM_S  16
+/* HP_CLKRST_TEST_PLL_SEL : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: test pll source select; 3'h0: RSVD; 3'h1: system PLL; 3'h2: CPU PLL; 3'h3: MPSI
+DLL; 3'h4: SDIO PLL CK0; 3'h5: SDIO PLL CK1; 3'h6: SDIO PLL CK2; 3'h7: AUDIO APL
+L.*/
+#define HP_CLKRST_TEST_PLL_SEL    0x00000007
+#define HP_CLKRST_TEST_PLL_SEL_M  ((HP_CLKRST_TEST_PLL_SEL_V)<<(HP_CLKRST_TEST_PLL_SEL_S))
+#define HP_CLKRST_TEST_PLL_SEL_V  0x7
+#define HP_CLKRST_TEST_PLL_SEL_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_HP_CLKRST_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/hwcrypto_reg.h b/components/soc/esp32p4/include/soc/hwcrypto_reg.h
new file mode 100644
index 0000000000..af608fcd27
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/hwcrypto_reg.h
@@ -0,0 +1,178 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __HWCRYPTO_REG_H__
+#define __HWCRYPTO_REG_H__
+
+#include "soc/soc.h"
+
+/* registers for RSA acceleration via Multiple Precision Integer ops */
+#define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
+/* RB & Z use the same memory block, depending on phase of operation */
+#define RSA_MEM_RB_BLOCK_BASE         ((DR_REG_RSA_BASE)+0x200)
+#define RSA_MEM_Z_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x200)
+#define RSA_MEM_Y_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x400)
+#define RSA_MEM_X_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x600)
+
+/* Configuration registers */
+#define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
+#define RSA_LENGTH_REG                (DR_REG_RSA_BASE + 0x804)
+#define RSA_CONSTANT_TIME_REG         (DR_REG_RSA_BASE + 0x820)
+#define RSA_SEARCH_ENABLE_REG         (DR_REG_RSA_BASE + 0x824)
+#define RSA_SEARCH_POS_REG            (DR_REG_RSA_BASE + 0x828)
+
+/* Initialization registers */
+#define RSA_QUERY_CLEAN_REG           (DR_REG_RSA_BASE + 0x808)
+
+/* Calculation start registers */
+#define RSA_MODEXP_START_REG          (DR_REG_RSA_BASE + 0x80c)
+#define RSA_MOD_MULT_START_REG        (DR_REG_RSA_BASE + 0x810)
+#define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x814)
+
+/* Interrupt registers */
+#define RSA_QUERY_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x818)
+#define RSA_CLEAR_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x81C)
+#define RSA_INTERRUPT_REG             (DR_REG_RSA_BASE + 0x82C)
+#define RSA_DATE_REG                  (DR_REG_RSA_BASE + 0x82C)
+
+#define SHA_MODE_SHA1       0
+#define SHA_MODE_SHA224     1
+#define SHA_MODE_SHA256     2
+
+/* SHA acceleration registers */
+#define SHA_MODE_REG                  ((DR_REG_SHA_BASE) + 0x00)
+#define SHA_BLOCK_NUM_REG             ((DR_REG_SHA_BASE) + 0x0C)
+#define SHA_START_REG                 ((DR_REG_SHA_BASE) + 0x10)
+#define SHA_CONTINUE_REG              ((DR_REG_SHA_BASE) + 0x14)
+#define SHA_BUSY_REG                  ((DR_REG_SHA_BASE) + 0x18)
+#define SHA_DMA_START_REG             ((DR_REG_SHA_BASE) + 0x1C)
+#define SHA_DMA_CONTINUE_REG          ((DR_REG_SHA_BASE) + 0x20)
+#define SHA_CLEAR_IRQ_REG             ((DR_REG_SHA_BASE) + 0x24)
+#define SHA_INT_ENA_REG               ((DR_REG_SHA_BASE) + 0x28)
+#define SHA_DATE_REG                  ((DR_REG_SHA_BASE) + 0x2C)
+
+#define SHA_H_BASE                    ((DR_REG_SHA_BASE) + 0x40)
+#define SHA_TEXT_BASE                 ((DR_REG_SHA_BASE) + 0x80)
+
+/* AES Block operation modes */
+#define AES_BLOCK_MODE_ECB     0
+#define AES_BLOCK_MODE_CBC     1
+#define AES_BLOCK_MODE_OFB     2
+#define AES_BLOCK_MODE_CTR     3
+#define AES_BLOCK_MODE_CFB8    4
+#define AES_BLOCK_MODE_CFB128  5
+
+/* AES Block operation modes (used with DMA) */
+#define AES_BLOCK_MODE_ECB     0
+#define AES_BLOCK_MODE_CBC     1
+#define AES_BLOCK_MODE_OFB     2
+#define AES_BLOCK_MODE_CTR     3
+#define AES_BLOCK_MODE_CFB8    4
+#define AES_BLOCK_MODE_CFB128  5
+
+/* AES acceleration registers */
+#define AES_MODE_REG            ((DR_REG_AES_BASE) + 0x40)
+#define AES_ENDIAN_REG          ((DR_REG_AES_BASE) + 0x44)
+#define AES_TRIGGER_REG         ((DR_REG_AES_BASE) + 0x48)
+#define AES_STATE_REG           ((DR_REG_AES_BASE) + 0x4c)
+#define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
+#define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
+#define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
+#define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
+#define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
+#define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
+#define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
+#define AES_INT_CLEAR_REG       ((DR_REG_AES_BASE) + 0xAC)
+#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
+#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
+#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
+
+#define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
+#define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
+#define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
+#define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
+#define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
+#define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
+#define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
+
+#define AES_KEY_BASE            ((DR_REG_AES_BASE) + 0x00)
+#define AES_TEXT_IN_BASE        ((DR_REG_AES_BASE) + 0x20)
+#define AES_TEXT_OUT_BASE       ((DR_REG_AES_BASE) + 0x30)
+#define AES_IV_BASE             ((DR_REG_AES_BASE) + 0x50)
+#define AES_H_BASE              ((DR_REG_AES_BASE) + 0x60)
+#define AES_J_BASE              ((DR_REG_AES_BASE) + 0x70)
+#define AES_T_BASE              ((DR_REG_AES_BASE) + 0x80)
+
+#define AES_INT_CLR_REG         ((DR_REG_AES_BASE) + 0xAC)
+#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
+#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
+#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
+
+/* AES_STATE_REG values */
+#define AES_STATE_IDLE 0
+#define AES_STATE_BUSY 1
+#define AES_STATE_DONE 2
+
+/* HMAC Module */
+#define HMAC_SET_START_REG             ((DR_REG_HMAC_BASE) + 0x40)
+#define HMAC_SET_PARA_PURPOSE_REG      ((DR_REG_HMAC_BASE) + 0x44)
+#define HMAC_SET_PARA_KEY_REG          ((DR_REG_HMAC_BASE) + 0x48)
+#define HMAC_SET_PARA_FINISH_REG       ((DR_REG_HMAC_BASE) + 0x4c)
+#define HMAC_SET_MESSAGE_ONE_REG       ((DR_REG_HMAC_BASE) + 0x50)
+#define HMAC_SET_MESSAGE_ING_REG       ((DR_REG_HMAC_BASE) + 0x54)
+#define HMAC_SET_MESSAGE_END_REG       ((DR_REG_HMAC_BASE) + 0x58)
+#define HMAC_SET_RESULT_FINISH_REG     ((DR_REG_HMAC_BASE) + 0x5c)
+#define HMAC_SET_INVALIDATE_JTAG_REG   ((DR_REG_HMAC_BASE) + 0x60)
+#define HMAC_SET_INVALIDATE_DS_REG     ((DR_REG_HMAC_BASE) + 0x64)
+#define HMAC_QUERY_ERROR_REG           ((DR_REG_HMAC_BASE) + 0x68)
+#define HMAC_QUERY_BUSY_REG            ((DR_REG_HMAC_BASE) + 0x6c)
+
+#define HMAC_WDATA_BASE                ((DR_REG_HMAC_BASE) + 0x80)
+#define HMAC_RDATA_BASE                ((DR_REG_HMAC_BASE) + 0xC0)
+#define HMAC_SET_MESSAGE_PAD_REG       ((DR_REG_HMAC_BASE) + 0xF0)
+#define HMAC_ONE_BLOCK_REG             ((DR_REG_HMAC_BASE) + 0xF4)
+
+#define HMAC_SOFT_JTAG_CTRL_REG        ((DR_REG_HMAC_BASE) + 0xF8)
+#define HMAC_WR_JTAG_REG               ((DR_REG_HMAC_BASE) + 0xFC)
+
+#define HMAC_DATE_REG                  ((DR_REG_HMAC_BASE) + 0xF8)
+
+
+/* AES-XTS registers */
+#define AES_XTS_PLAIN_BASE        ((DR_REG_AES_XTS_BASE) + 0x00)
+#define AES_XTS_SIZE_REG          ((DR_REG_AES_XTS_BASE) + 0x40)
+#define AES_XTS_DESTINATION_REG   ((DR_REG_AES_XTS_BASE) + 0x44)
+#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
+
+#define AES_XTS_TRIGGER_REG       ((DR_REG_AES_XTS_BASE) + 0x4C)
+#define AES_XTS_RELEASE_REG       ((DR_REG_AES_XTS_BASE) + 0x50)
+#define AES_XTS_DESTROY_REG       ((DR_REG_AES_XTS_BASE) + 0x54)
+#define AES_XTS_STATE_REG         ((DR_REG_AES_XTS_BASE) + 0x58)
+#define AES_XTS_DATE_REG          ((DR_REG_AES_XTS_BASE) + 0x5C)
+
+/* Digital Signature registers and memory blocks */
+#define DS_C_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
+#define DS_C_Y_BASE               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
+#define DS_C_M_BASE               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 )
+#define DS_C_RB_BASE              ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 )
+#define DS_C_BOX_BASE             ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 )
+#define DS_IV_BASE                ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
+#define DS_X_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
+#define DS_Z_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
+
+#define DS_SET_START_REG          ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
+#define DS_SET_ME_REG             ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
+#define DS_SET_FINISH_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
+
+#define DS_QUERY_BUSY_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
+#define DS_QUERY_KEY_WRONG_REG    ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
+#define DS_QUERY_CHECK_REG        ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
+
+#define DS_QUERY_CHECK_INVALID_DIGEST  (1<<0)
+#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
+
+#define DS_DATE_REG               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
+
+#endif
diff --git a/components/soc/esp32p4/include/soc/i2c_ext_reg.h b/components/soc/esp32p4/include/soc/i2c_ext_reg.h
new file mode 100644
index 0000000000..9cdfdcede6
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/i2c_ext_reg.h
@@ -0,0 +1,1521 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_SCL_LOW_PERIOD_REG register
+ *  Configures the low level width of the SCL Clock.
+ */
+#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
+/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the low level width of the SCL Clock.
+ *  Measurement unit: i2c_sclk.
+ */
+#define I2C_SCL_LOW_PERIOD    0x000001FFU
+#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
+#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
+#define I2C_SCL_LOW_PERIOD_S  0
+
+/** I2C_CTR_REG register
+ *  Transmission setting
+ */
+#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
+/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
+ *  Configures the SDA output mode
+ *  1: Direct output,
+ *
+ *  0: Open drain output.
+ */
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
+#define I2C_SDA_FORCE_OUT_V  0x00000001U
+#define I2C_SDA_FORCE_OUT_S  0
+/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
+ *  Configures the SCL output mode
+ *  1: Direct output,
+ *
+ *  0: Open drain output.
+ */
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
+#define I2C_SCL_FORCE_OUT_V  0x00000001U
+#define I2C_SCL_FORCE_OUT_S  1
+/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
+ *  Configures the sample mode for SDA.
+ *  1: Sample SDA data on the SCL low level.
+ *
+ *  0: Sample SDA data on the SCL high level.
+ */
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
+#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
+ *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+ *  reached the threshold.
+ */
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
+#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
+ *  Configures the module as an I2C Master or Slave.
+ *  0: Slave
+ *
+ *  1: Master
+ */
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
+#define I2C_MS_MODE_V  0x00000001U
+#define I2C_MS_MODE_S  4
+/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
+ *  Configures to start sending the data in txfifo for slave.
+ *  0: No effect
+ *
+ *  1: Start
+ */
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
+#define I2C_TRANS_START_V  0x00000001U
+#define I2C_TRANS_START_S  5
+/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
+ *  Configures to control the sending order for data needing to be sent.
+ *  1: send data from the least significant bit,
+ *
+ *  0: send data from the most significant bit.
+ */
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
+#define I2C_TX_LSB_FIRST_V  0x00000001U
+#define I2C_TX_LSB_FIRST_S  6
+/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
+ *  Configures to control the storage order for received data.
+ *  1: receive data from the least significant bit
+ *
+ *  0: receive data from the most significant bit.
+ */
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
+#define I2C_RX_LSB_FIRST_V  0x00000001U
+#define I2C_RX_LSB_FIRST_S  7
+/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to gate clock signal for registers.
+ *
+ *  0: Force clock on for registers
+ *
+ *  1: Support clock only when registers are read or written to by software.
+ */
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
+#define I2C_CLK_EN_V  0x00000001U
+#define I2C_CLK_EN_S  8
+/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures to enable I2C bus arbitration detection.
+ *  0: No effect
+ *
+ *  1: Enable
+ */
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
+#define I2C_ARBITRATION_EN_V  0x00000001U
+#define I2C_ARBITRATION_EN_S  9
+/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
+ *  Configures to reset the SCL_FSM.
+ *  0: No effect
+ *
+ *  1: Reset
+ */
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
+#define I2C_FSM_RST_V  0x00000001U
+#define I2C_FSM_RST_S  10
+/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
+ *  Configures this bit for synchronization
+ *  0: No effect
+ *
+ *  1: Synchronize
+ */
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
+#define I2C_CONF_UPGATE_V  0x00000001U
+#define I2C_CONF_UPGATE_S  11
+/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures to enable slave to send data automatically
+ *  0: Disable
+ *
+ *  1: Enable
+ */
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
+#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+ *  0: Not check
+ *
+ *  1: Check
+ */
+#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
+#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
+/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures to support the 7bit general call function.
+ *  0: Not support
+ *
+ *  1: Support
+ */
+#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
+#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
+#define I2C_ADDR_BROADCASTING_EN_S  14
+
+/** I2C_SR_REG register
+ *  Describe I2C work status.
+ */
+#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
+/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
+ *  Represents the received ACK value in master mode or slave mode.
+ *  0: ACK,
+ *
+ *  1: NACK.
+ */
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
+#define I2C_RESP_REC_V  0x00000001U
+#define I2C_RESP_REC_S  0
+/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
+ *  Represents the transfer direction in slave mode,.
+ *  1: Master reads from slave,
+ *
+ *  0: Master writes to slave.
+ */
+#define I2C_SLAVE_RW    (BIT(1))
+#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
+#define I2C_SLAVE_RW_V  0x00000001U
+#define I2C_SLAVE_RW_S  1
+/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
+ *  Represents whether the I2C controller loses control of SCL line.
+ *  0: No arbitration lost
+ *
+ *  1: Arbitration lost
+ */
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
+#define I2C_ARB_LOST_V  0x00000001U
+#define I2C_ARB_LOST_S  3
+/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
+ *  Represents the I2C bus state.
+ *  1: The I2C bus is busy transferring data,
+ *
+ *  0: The I2C bus is in idle state.
+ */
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
+#define I2C_BUS_BUSY_V  0x00000001U
+#define I2C_BUS_BUSY_S  4
+/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
+ *  Represents whether the address sent by the master is equal to the address of the
+ *  slave.
+ *  Valid only when the module is configured as an I2C Slave.
+ *  0: Not equal
+ *
+ *  1: Equal
+ */
+#define I2C_SLAVE_ADDRESSED    (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
+#define I2C_SLAVE_ADDRESSED_V  0x00000001U
+#define I2C_SLAVE_ADDRESSED_S  5
+/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
+ *  Represents the number of data bytes to be sent.
+ */
+#define I2C_RXFIFO_CNT    0x0000003FU
+#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
+#define I2C_RXFIFO_CNT_V  0x0000003FU
+#define I2C_RXFIFO_CNT_S  8
+/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
+ *  Represents the cause of SCL clocking stretching in slave mode.
+ *  0: Stretching SCL low when the master starts to read data.
+ *
+ *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+ *
+ *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+ */
+#define I2C_STRETCH_CAUSE    0x00000003U
+#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
+#define I2C_STRETCH_CAUSE_V  0x00000003U
+#define I2C_STRETCH_CAUSE_S  14
+/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
+ *  Represents the number of data bytes received in RAM.
+ */
+#define I2C_TXFIFO_CNT    0x0000003FU
+#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
+#define I2C_TXFIFO_CNT_V  0x0000003FU
+#define I2C_TXFIFO_CNT_S  18
+/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  Represents the states of the I2C module state machine.
+ *  0: Idle,
+ *
+ *  1: Address shift,
+ *
+ *  2: ACK address,
+ *
+ *  3: Rx data,
+ *
+ *  4: Tx data,
+ *
+ *  5: Send ACK,
+ *
+ *  6: Wait ACK
+ */
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
+#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  Represents the states of the state machine used to produce SCL.
+ *  0: Idle,
+ *
+ *  1: Start,
+ *
+ *  2: Negative edge,
+ *
+ *  3: Low,
+ *
+ *  4: Positive edge,
+ *
+ *  5: High,
+ *
+ *  6: Stop
+ */
+#define I2C_SCL_STATE_LAST    0x00000007U
+#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
+#define I2C_SCL_STATE_LAST_V  0x00000007U
+#define I2C_SCL_STATE_LAST_S  28
+
+/** I2C_TO_REG register
+ *  Setting time out control for receiving data.
+ */
+#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
+/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the timeout threshold period for SCL stucking at high or low level. The
+ *  actual period is 2^(reg_time_out_value).
+ *  Measurement unit: i2c_sclk.
+ */
+#define I2C_TIME_OUT_VALUE    0x0000001FU
+#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
+#define I2C_TIME_OUT_VALUE_V  0x0000001FU
+#define I2C_TIME_OUT_VALUE_S  0
+/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures to enable time out control.
+ *  0: No effect
+ *
+ *  1: Enable
+ */
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
+#define I2C_TIME_OUT_EN_V  0x00000001U
+#define I2C_TIME_OUT_EN_S  5
+
+/** I2C_SLAVE_ADDR_REG register
+ *  Local slave address setting
+ */
+#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
+/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
+ *  Configure the slave address of I2C Slave.
+ */
+#define I2C_SLAVE_ADDR    0x00007FFFU
+#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
+#define I2C_SLAVE_ADDR_V  0x00007FFFU
+#define I2C_SLAVE_ADDR_S  0
+/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures to enable the slave 10-bit addressing mode in master mode.
+ *  0: No effect
+ *
+ *  1: Enable
+ */
+#define I2C_ADDR_10BIT_EN    (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
+#define I2C_ADDR_10BIT_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_EN_S  31
+
+/** I2C_FIFO_ST_REG register
+ *  FIFO status register.
+ */
+#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
+/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
+ *  Represents the offset address of the APB reading from RXFIFO
+ */
+#define I2C_RXFIFO_RADDR    0x0000001FU
+#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
+#define I2C_RXFIFO_RADDR_V  0x0000001FU
+#define I2C_RXFIFO_RADDR_S  0
+/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
+ *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+ */
+#define I2C_RXFIFO_WADDR    0x0000001FU
+#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
+#define I2C_RXFIFO_WADDR_V  0x0000001FU
+#define I2C_RXFIFO_WADDR_S  5
+/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
+ *  Represents the offset address of i2c module reading from TXFIFO.
+ */
+#define I2C_TXFIFO_RADDR    0x0000001FU
+#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
+#define I2C_TXFIFO_RADDR_V  0x0000001FU
+#define I2C_TXFIFO_RADDR_S  10
+/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
+ *  Represents the offset address of APB bus writing to TXFIFO.
+ */
+#define I2C_TXFIFO_WADDR    0x0000001FU
+#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
+#define I2C_TXFIFO_WADDR_V  0x0000001FU
+#define I2C_TXFIFO_WADDR_S  15
+/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
+ *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+ *  I2C slave mode.
+ */
+#define I2C_SLAVE_RW_POINT    0x000000FFU
+#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
+#define I2C_SLAVE_RW_POINT_V  0x000000FFU
+#define I2C_SLAVE_RW_POINT_S  22
+
+/** I2C_FIFO_CONF_REG register
+ *  FIFO configuration register.
+ */
+#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
+/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
+ *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+ *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_RXFIFO_WM_THRHD    0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
+#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_S  0
+/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
+ *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+ *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_TXFIFO_WM_THRHD    0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
+#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_S  5
+/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures to enable APB nonfifo access.
+ */
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
+#define I2C_NONFIFO_EN_V  0x00000001U
+#define I2C_NONFIFO_EN_S  10
+/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures to enable double addressing mode. When this mode is enabled, the byte
+ *  received after the I2C address byte represents the offset address in the I2C Slave
+ *  RAM.
+ *  0: Disable
+ *
+ *  1: Enable
+ */
+#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
+#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
+ *  Configures to reset RXFIFO.
+ *  0: No effect
+ *
+ *  1: Reset
+ */
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
+#define I2C_RX_FIFO_RST_V  0x00000001U
+#define I2C_RX_FIFO_RST_S  12
+/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
+ *  Configures to reset TXFIFO.
+ *  0: No effect
+ *
+ *  1: Reset
+ */
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
+#define I2C_TX_FIFO_RST_V  0x00000001U
+#define I2C_TX_FIFO_RST_S  13
+/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
+ *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+ *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+ *  0: No effect
+ *
+ *  1: Enable
+ */
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
+#define I2C_FIFO_PRT_EN_V  0x00000001U
+#define I2C_FIFO_PRT_EN_S  14
+
+/** I2C_DATA_REG register
+ *  Rx FIFO read data.
+ */
+#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
+/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
+ *  Represents the value of RXFIFO read data.
+ */
+#define I2C_FIFO_RDATA    0x000000FFU
+#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
+#define I2C_FIFO_RDATA_V  0x000000FFU
+#define I2C_FIFO_RDATA_S  0
+
+/** I2C_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
+/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
+#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
+ *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
+#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
+#define I2C_END_DETECT_INT_RAW_V  0x00000001U
+#define I2C_END_DETECT_INT_RAW_S  3
+/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
+#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
+#define I2C_TIME_OUT_INT_RAW_S  8
+/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
+#define I2C_TRANS_START_INT_RAW_V  0x00000001U
+#define I2C_TRANS_START_INT_RAW_S  9
+/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
+#define I2C_NACK_INT_RAW_V  0x00000001U
+#define I2C_NACK_INT_RAW_S  10
+/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
+#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  The raw interrupt status of I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
+#define I2C_DET_START_INT_RAW_V  0x00000001U
+#define I2C_DET_START_INT_RAW_S  15
+/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
+ *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
+#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_RAW_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M  (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S  18
+
+/** I2C_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
+/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
+#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
+#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
+#define I2C_END_DETECT_INT_CLR_V  0x00000001U
+#define I2C_END_DETECT_INT_CLR_S  3
+/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
+#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
+#define I2C_TIME_OUT_INT_CLR_S  8
+/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
+#define I2C_TRANS_START_INT_CLR_V  0x00000001U
+#define I2C_TRANS_START_INT_CLR_S  9
+/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
+#define I2C_NACK_INT_CLR_V  0x00000001U
+#define I2C_NACK_INT_CLR_S  10
+/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
+#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Write 1 to clear I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
+#define I2C_DET_START_INT_CLR_V  0x00000001U
+#define I2C_DET_START_INT_CLR_S  15
+/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
+#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_CLR_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M  (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S  18
+
+/** I2C_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
+/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
+#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
+#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
+#define I2C_END_DETECT_INT_ENA_V  0x00000001U
+#define I2C_END_DETECT_INT_ENA_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
+#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
+#define I2C_TIME_OUT_INT_ENA_S  8
+/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
+#define I2C_TRANS_START_INT_ENA_V  0x00000001U
+#define I2C_TRANS_START_INT_ENA_S  9
+/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
+#define I2C_NACK_INT_ENA_V  0x00000001U
+#define I2C_NACK_INT_ENA_S  10
+/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
+#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Write 1 to enable I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
+#define I2C_DET_START_INT_ENA_V  0x00000001U
+#define I2C_DET_START_INT_ENA_S  15
+/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
+#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ENA_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S  18
+
+/** I2C_INT_STATUS_REG register
+ *  Status of captured I2C communication events
+ */
+#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
+/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
+#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ST_S  0
+/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
+#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
+#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
+#define I2C_END_DETECT_INT_ST_V  0x00000001U
+#define I2C_END_DETECT_INT_ST_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
+#define I2C_TIME_OUT_INT_ST_V  0x00000001U
+#define I2C_TIME_OUT_INT_ST_S  8
+/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
+#define I2C_TRANS_START_INT_ST_V  0x00000001U
+#define I2C_TRANS_START_INT_ST_S  9
+/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
+#define I2C_NACK_INT_ST_V  0x00000001U
+#define I2C_NACK_INT_ST_S  10
+/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
+#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
+#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
+#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
+#define I2C_DET_START_INT_ST_V  0x00000001U
+#define I2C_DET_START_INT_ST_S  15
+/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
+#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ST_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S  18
+
+/** I2C_SDA_HOLD_REG register
+ *  Configures the hold time after a negative SCL edge.
+ */
+#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
+/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the time to hold the data after the falling edge of SCL.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_HOLD_TIME    0x000001FFU
+#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
+#define I2C_SDA_HOLD_TIME_V  0x000001FFU
+#define I2C_SDA_HOLD_TIME_S  0
+
+/** I2C_SDA_SAMPLE_REG register
+ *  Configures the sample time after a positive SCL edge.
+ */
+#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
+/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the sample time after a positive SCL edge.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_SAMPLE_TIME    0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
+#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+/** I2C_SCL_HIGH_PERIOD_REG register
+ *  Configures the high level width of SCL
+ */
+#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
+/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures for how long SCL remains high in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_HIGH_PERIOD    0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
+#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_S  0
+/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
+ *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+
+/** I2C_SCL_START_HOLD_REG register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
+/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+ *  a START condition.
+ *  Measurement unit: i2c_sclk.
+ */
+#define I2C_SCL_START_HOLD_TIME    0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
+#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+/** I2C_SCL_RSTART_SETUP_REG register
+ *  Configures the delay between the positive edge of SCL and the negative edge of SDA
+ */
+#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
+/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the positive edge of SCL and the negative edge of SDA
+ *  for a RESTART condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+/** I2C_SCL_STOP_HOLD_REG register
+ *  Configures the delay after the SCL clock edge for a stop condition
+ */
+#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
+/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the delay after the STOP condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
+#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+/** I2C_SCL_STOP_SETUP_REG register
+ *  Configures the delay between the SDA and SCL rising edge for a stop condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
+/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the rising edge of SCL and the rising edge of SDA.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
+#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+/** I2C_FILTER_CFG_REG register
+ *  SCL and SDA filter configuration register
+ */
+#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
+/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_FILTER_THRES    0x0000000FU
+#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
+#define I2C_SCL_FILTER_THRES_V  0x0000000FU
+#define I2C_SCL_FILTER_THRES_S  0
+/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_FILTER_THRES    0x0000000FU
+#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
+#define I2C_SDA_FILTER_THRES_V  0x0000000FU
+#define I2C_SDA_FILTER_THRES_S  4
+/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
+ *  Configures to enable the filter function for SCL.
+ */
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
+#define I2C_SCL_FILTER_EN_V  0x00000001U
+#define I2C_SCL_FILTER_EN_S  8
+/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures to enable the filter function for SDA.
+ */
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
+#define I2C_SDA_FILTER_EN_V  0x00000001U
+#define I2C_SDA_FILTER_EN_S  9
+
+/** I2C_COMD0_REG register
+ *  I2C command register 0
+ */
+#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
+/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 0. It consists of three parts:
+ *  op_code is the command,
+ *  0: RSTART,
+ *  1: WRITE,
+ *  2: READ,
+ *  3: STOP,
+ *  4: END.
+ *
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more information.
+ */
+#define I2C_COMMAND0    0x00003FFFU
+#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
+#define I2C_COMMAND0_V  0x00003FFFU
+#define I2C_COMMAND0_S  0
+/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 0 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
+#define I2C_COMMAND0_DONE_V  0x00000001U
+#define I2C_COMMAND0_DONE_S  31
+
+/** I2C_COMD1_REG register
+ *  I2C command register 1
+ */
+#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
+/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 1. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND1    0x00003FFFU
+#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
+#define I2C_COMMAND1_V  0x00003FFFU
+#define I2C_COMMAND1_S  0
+/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 1 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
+#define I2C_COMMAND1_DONE_V  0x00000001U
+#define I2C_COMMAND1_DONE_S  31
+
+/** I2C_COMD2_REG register
+ *  I2C command register 2
+ */
+#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
+/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 2. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND2    0x00003FFFU
+#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
+#define I2C_COMMAND2_V  0x00003FFFU
+#define I2C_COMMAND2_S  0
+/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 2 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
+#define I2C_COMMAND2_DONE_V  0x00000001U
+#define I2C_COMMAND2_DONE_S  31
+
+/** I2C_COMD3_REG register
+ *  I2C command register 3
+ */
+#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
+/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 3. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND3    0x00003FFFU
+#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
+#define I2C_COMMAND3_V  0x00003FFFU
+#define I2C_COMMAND3_S  0
+/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 3 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
+#define I2C_COMMAND3_DONE_V  0x00000001U
+#define I2C_COMMAND3_DONE_S  31
+
+/** I2C_COMD4_REG register
+ *  I2C command register 4
+ */
+#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
+/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 4. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND4    0x00003FFFU
+#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
+#define I2C_COMMAND4_V  0x00003FFFU
+#define I2C_COMMAND4_S  0
+/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 4 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
+#define I2C_COMMAND4_DONE_V  0x00000001U
+#define I2C_COMMAND4_DONE_S  31
+
+/** I2C_COMD5_REG register
+ *  I2C command register 5
+ */
+#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
+/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 5. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND5    0x00003FFFU
+#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
+#define I2C_COMMAND5_V  0x00003FFFU
+#define I2C_COMMAND5_S  0
+/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 5 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
+#define I2C_COMMAND5_DONE_V  0x00000001U
+#define I2C_COMMAND5_DONE_S  31
+
+/** I2C_COMD6_REG register
+ *  I2C command register 6
+ */
+#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
+/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 6. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND6    0x00003FFFU
+#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
+#define I2C_COMMAND6_V  0x00003FFFU
+#define I2C_COMMAND6_S  0
+/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 6 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
+#define I2C_COMMAND6_DONE_V  0x00000001U
+#define I2C_COMMAND6_DONE_S  31
+
+/** I2C_COMD7_REG register
+ *  I2C command register 7
+ */
+#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
+/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 7. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND7    0x00003FFFU
+#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
+#define I2C_COMMAND7_V  0x00003FFFU
+#define I2C_COMMAND7_S  0
+/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 7 is done in I2C Master mode.
+ *  0: Not done
+ *
+ *  1: Done
+ */
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
+#define I2C_COMMAND7_DONE_V  0x00000001U
+#define I2C_COMMAND7_DONE_S  31
+
+/** I2C_SCL_ST_TIME_OUT_REG register
+ *  SCL status time out register
+ */
+#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
+/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+ *  more than 23.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
+#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_ST_TO_I2C_S  0
+
+/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
+ *  SCL main status time out register
+ */
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
+/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
+ *  no more than 23.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
+#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_S  0
+
+/** I2C_SCL_SP_CONF_REG register
+ *  Power configuration register
+ */
+#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
+/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+ *  equals to reg_scl_rst_slv_num[4:0].
+ */
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
+#define I2C_SCL_RST_SLV_EN_V  0x00000001U
+#define I2C_SCL_RST_SLV_EN_S  0
+/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
+ *  Configure the pulses of SCL generated in I2C master mode.
+ *  Valid when reg_scl_rst_slv_en is 1.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_RST_SLV_NUM    0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
+#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_S  1
+/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures to power down the I2C output SCL line.
+ *  0: Not power down.
+ *
+ *  1: Power down.
+ *  Valid only when reg_scl_force_out is 1.
+ */
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
+#define I2C_SCL_PD_EN_V  0x00000001U
+#define I2C_SCL_PD_EN_S  6
+/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures to power down the I2C output SDA line.
+ *  0: Not power down.
+ *
+ *  1: Power down.
+ *  Valid only when reg_sda_force_out is 1.
+ */
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
+#define I2C_SDA_PD_EN_V  0x00000001U
+#define I2C_SDA_PD_EN_S  7
+
+/** I2C_SCL_STRETCH_CONF_REG register
+ *  Set SCL stretch of I2C slave
+ */
+#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
+/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
+ *  Configures the time period to release the SCL line from stretching to avoid timing
+ *  violation. Usually it should be larger than the SDA setup time.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
+#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_S  0
+/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures to enable slave SCL stretch function.
+ *  0: Disable
+ *
+ *  1: Enable
+ *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
+ *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
+ */
+#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures to clear the I2C slave SCL stretch function.
+ *  0: No effect
+ *
+ *  1: Clear
+ */
+#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures to enable the function for slave to control ACK level.
+ *  0: Disable
+ *
+ *  1: Enable
+ */
+#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
+/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
+ *  Set the ACK level when slave controlling ACK level function enables.
+ *  0: Low level
+ *
+ *  1: High level
+ */
+#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
+#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_LVL_S  13
+
+/** I2C_DATE_REG register
+ *  Version register
+ */
+#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
+/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050;
+ *  Version control register.
+ */
+#define I2C_DATE    0xFFFFFFFFU
+#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
+#define I2C_DATE_V  0xFFFFFFFFU
+#define I2C_DATE_S  0
+
+/** I2C_TXFIFO_START_ADDR_REG register
+ *  I2C TXFIFO base address register
+ */
+#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
+/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C txfifo first address.
+ */
+#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
+#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_S  0
+
+/** I2C_RXFIFO_START_ADDR_REG register
+ *  I2C RXFIFO base address register
+ */
+#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
+/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C rxfifo first address.
+ */
+#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
+#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/i2c_ext_struct.h b/components/soc/esp32p4/include/soc/i2c_ext_struct.h
new file mode 100644
index 0000000000..eb8069be9c
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/i2c_ext_struct.h
@@ -0,0 +1,1276 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL Clock.
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the low level width of the SCL Clock.
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time to hold the data after the falling edge of SCL.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the sample time after a positive SCL edge.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures for how long SCL remains high in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+         *  a START condition.
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the positive edge of SCL and the negative edge of SDA
+         *  for a RESTART condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the delay after the STOP condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and SCL rising edge for a stop condition.
+ *  Measurement unit: i2c_sclk
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the rising edge of SCL and the rising edge of SDA.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+         *  more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
+         *  no more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 0;
+         *  Configures the SDA output mode
+         *  1: Direct output,
+         *
+         *  0: Open drain output.
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 0;
+         *  Configures the SCL output mode
+         *  1: Direct output,
+         *
+         *  0: Open drain output.
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  Configures the sample mode for SDA.
+         *  1: Sample SDA data on the SCL low level.
+         *
+         *  0: Sample SDA data on the SCL high level.
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+         *  reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Configures the module as an I2C Master or Slave.
+         *  0: Slave
+         *
+         *  1: Master
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Configures to start sending the data in txfifo for slave.
+         *  0: No effect
+         *
+         *  1: Start
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  Configures to control the sending order for data needing to be sent.
+         *  1: send data from the least significant bit,
+         *
+         *  0: send data from the most significant bit.
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  Configures to control the storage order for received data.
+         *  1: receive data from the least significant bit
+         *
+         *  0: receive data from the most significant bit.
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to gate clock signal for registers.
+         *
+         *  0: Force clock on for registers
+         *
+         *  1: Support clock only when registers are read or written to by software.
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable I2C bus arbitration detection.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  Configures to reset the SCL_FSM.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  Configures this bit for synchronization
+         *  0: No effect
+         *
+         *  1: Synchronize
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable slave to send data automatically
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
+         *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+         *  0: Not check
+         *
+         *  1: Check
+         */
+        uint32_t addr_10bit_rw_check_en:1;
+        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
+         *  Configures to support the 7bit general call function.
+         *  0: Not support
+         *
+         *  1: Support
+         */
+        uint32_t addr_broadcasting_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data.
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the timeout threshold period for SCL stucking at high or low level. The
+         *  actual period is 2^(reg_time_out_value).
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  Configures to enable time out control.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of slave_addr register
+ *  Local slave address setting
+ */
+typedef union {
+    struct {
+        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
+         *  Configure the slave address of I2C Slave.
+         */
+        uint32_t slave_addr:15;
+        uint32_t reserved_15:16;
+        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  Configures to enable the slave 10-bit addressing mode in master mode.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t addr_10bit_en:1;
+    };
+    uint32_t val;
+} i2c_slave_addr_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
+         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+         *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t rxfifo_wm_thrhd:5;
+        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
+         *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+         *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:5;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
+         *  Configures to enable double addressing mode. When this mode is enabled, the byte
+         *  received after the I2C address byte represents the offset address in the I2C Slave
+         *  RAM.
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t fifo_addr_cfg_en:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Configures to reset RXFIFO.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Configures to reset TXFIFO.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  Configures to enable the filter function for SCL.
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable the filter function for SDA.
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+         *  equals to reg_scl_rst_slv_num[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode.
+         *  Valid when reg_scl_rst_slv_en is 1.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  Configures to power down the I2C output SCL line.
+         *  0: Not power down.
+         *
+         *  1: Power down.
+         *  Valid only when reg_scl_force_out is 1.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  Configures to power down the I2C output SDA line.
+         *  0: Not power down.
+         *
+         *  1: Power down.
+         *  Valid only when reg_sda_force_out is 1.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+/** Type of scl_stretch_conf register
+ *  Set SCL stretch of I2C slave
+ */
+typedef union {
+    struct {
+        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
+         *  Configures the time period to release the SCL line from stretching to avoid timing
+         *  violation. Usually it should be larger than the SDA setup time.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t stretch_protect_num:10;
+        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable slave SCL stretch function.
+         *  0: Disable
+         *
+         *  1: Enable
+         *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
+         *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
+         */
+        uint32_t slave_scl_stretch_en:1;
+        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
+         *  Configures to clear the I2C slave SCL stretch function.
+         *  0: No effect
+         *
+         *  1: Clear
+         */
+        uint32_t slave_scl_stretch_clr:1;
+        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable the function for slave to control ACK level.
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t slave_byte_ack_ctl_en:1;
+        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
+         *  Set the ACK level when slave controlling ACK level function enables.
+         *  0: Low level
+         *
+         *  1: High level
+         */
+        uint32_t slave_byte_ack_lvl:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i2c_scl_stretch_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status.
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  Represents the received ACK value in master mode or slave mode.
+         *  0: ACK,
+         *
+         *  1: NACK.
+         */
+        uint32_t resp_rec:1;
+        /** slave_rw : RO; bitpos: [1]; default: 0;
+         *  Represents the transfer direction in slave mode,.
+         *  1: Master reads from slave,
+         *
+         *  0: Master writes to slave.
+         */
+        uint32_t slave_rw:1;
+        uint32_t reserved_2:1;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  Represents whether the I2C controller loses control of SCL line.
+         *  0: No arbitration lost
+         *
+         *  1: Arbitration lost
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  Represents the I2C bus state.
+         *  1: The I2C bus is busy transferring data,
+         *
+         *  0: The I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        /** slave_addressed : RO; bitpos: [5]; default: 0;
+         *  Represents whether the address sent by the master is equal to the address of the
+         *  slave.
+         *  Valid only when the module is configured as an I2C Slave.
+         *  0: Not equal
+         *
+         *  1: Equal
+         */
+        uint32_t slave_addressed:1;
+        uint32_t reserved_6:2;
+        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
+         *  Represents the number of data bytes to be sent.
+         */
+        uint32_t rxfifo_cnt:6;
+        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
+         *  Represents the cause of SCL clocking stretching in slave mode.
+         *  0: Stretching SCL low when the master starts to read data.
+         *
+         *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+         *
+         *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+         */
+        uint32_t stretch_cause:2;
+        uint32_t reserved_16:2;
+        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
+         *  Represents the number of data bytes received in RAM.
+         */
+        uint32_t txfifo_cnt:6;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  Represents the states of the I2C module state machine.
+         *  0: Idle,
+         *
+         *  1: Address shift,
+         *
+         *  2: ACK address,
+         *
+         *  3: Rx data,
+         *
+         *  4: Tx data,
+         *
+         *  5: Send ACK,
+         *
+         *  6: Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  Represents the states of the state machine used to produce SCL.
+         *  0: Idle,
+         *
+         *  1: Start,
+         *
+         *  2: Negative edge,
+         *
+         *  3: Low,
+         *
+         *  4: Positive edge,
+         *
+         *  5: High,
+         *
+         *  6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
+         *  Represents the offset address of the APB reading from RXFIFO
+         */
+        uint32_t rxfifo_raddr:5;
+        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
+         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+         */
+        uint32_t rxfifo_waddr:5;
+        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
+         *  Represents the offset address of i2c module reading from TXFIFO.
+         */
+        uint32_t txfifo_raddr:5;
+        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
+         *  Represents the offset address of APB bus writing to TXFIFO.
+         */
+        uint32_t txfifo_waddr:5;
+        uint32_t reserved_20:2;
+        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
+         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+         *  I2C slave mode.
+         */
+        uint32_t slave_rw_point:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data.
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
+         *  Represents the value of RXFIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_raw:1;
+        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_raw:1;
+        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_raw:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_clr:1;
+        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_clr:1;
+        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_clr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_ena:1;
+        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_ena:1;
+        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_ena:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_st:1;
+        /** general_call_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_st:1;
+        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_st:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0
+ */
+typedef union {
+    struct {
+        /** command0 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 0. It consists of three parts:
+         *  op_code is the command,
+         *  0: RSTART,
+         *  1: WRITE,
+         *  2: READ,
+         *  3: STOP,
+         *  4: END.
+         *
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more information.
+         */
+        uint32_t command0:14;
+        uint32_t reserved_14:17;
+        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 0 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command0_done:1;
+    };
+    uint32_t val;
+} i2c_comd0_reg_t;
+
+/** Type of comd1 register
+ *  I2C command register 1
+ */
+typedef union {
+    struct {
+        /** command1 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 1. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command1:14;
+        uint32_t reserved_14:17;
+        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 1 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command1_done:1;
+    };
+    uint32_t val;
+} i2c_comd1_reg_t;
+
+/** Type of comd2 register
+ *  I2C command register 2
+ */
+typedef union {
+    struct {
+        /** command2 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 2. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command2:14;
+        uint32_t reserved_14:17;
+        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 2 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command2_done:1;
+    };
+    uint32_t val;
+} i2c_comd2_reg_t;
+
+/** Type of comd3 register
+ *  I2C command register 3
+ */
+typedef union {
+    struct {
+        /** command3 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 3. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command3:14;
+        uint32_t reserved_14:17;
+        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 3 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command3_done:1;
+    };
+    uint32_t val;
+} i2c_comd3_reg_t;
+
+/** Type of comd4 register
+ *  I2C command register 4
+ */
+typedef union {
+    struct {
+        /** command4 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 4. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command4:14;
+        uint32_t reserved_14:17;
+        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 4 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command4_done:1;
+    };
+    uint32_t val;
+} i2c_comd4_reg_t;
+
+/** Type of comd5 register
+ *  I2C command register 5
+ */
+typedef union {
+    struct {
+        /** command5 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 5. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command5:14;
+        uint32_t reserved_14:17;
+        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 5 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command5_done:1;
+    };
+    uint32_t val;
+} i2c_comd5_reg_t;
+
+/** Type of comd6 register
+ *  I2C command register 6
+ */
+typedef union {
+    struct {
+        /** command6 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 6. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command6:14;
+        uint32_t reserved_14:17;
+        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 6 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command6_done:1;
+    };
+    uint32_t val;
+} i2c_comd6_reg_t;
+
+/** Type of comd7 register
+ *  I2C command register 7
+ */
+typedef union {
+    struct {
+        /** command7 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 7. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command7:14;
+        uint32_t reserved_14:17;
+        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 7 is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command7_done:1;
+    };
+    uint32_t val;
+} i2c_comd7_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35656050;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+/** Group: Address register */
+/** Type of txfifo_start_addr register
+ *  I2C TXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C txfifo first address.
+         */
+        uint32_t txfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_txfifo_start_addr_reg_t;
+
+/** Type of rxfifo_start_addr register
+ *  I2C RXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C rxfifo first address.
+         */
+        uint32_t rxfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_rxfifo_start_addr_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    volatile i2c_slave_addr_reg_t slave_addr;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    uint32_t reserved_054;
+    volatile i2c_comd0_reg_t comd0;
+    volatile i2c_comd1_reg_t comd1;
+    volatile i2c_comd2_reg_t comd2;
+    volatile i2c_comd3_reg_t comd3;
+    volatile i2c_comd4_reg_t comd4;
+    volatile i2c_comd5_reg_t comd5;
+    volatile i2c_comd6_reg_t comd6;
+    volatile i2c_comd7_reg_t comd7;
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
+    uint32_t reserved_088[28];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
+    uint32_t reserved_104[31];
+    volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
+} i2c_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h
new file mode 100644
index 0000000000..98a17b234a
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h
@@ -0,0 +1,1094 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_INTERRUPT_CORE0_REG_H_
+#define _SOC_INTERRUPT_CORE0_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
+/* INTERRUPT_CORE0_LP_RTC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_M  ((INTERRUPT_CORE0_LP_RTC_INT_MAP_V)<<(INTERRUPT_CORE0_LP_RTC_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
+/* INTERRUPT_CORE0_LP_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_M  ((INTERRUPT_CORE0_LP_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_LP_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
+/* INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_M  ((INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC)
+/* INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_M  ((INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
+/* INTERRUPT_CORE0_MB_HP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_MB_HP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_M  ((INTERRUPT_CORE0_MB_HP_INT_MAP_V)<<(INTERRUPT_CORE0_MB_HP_INT_MAP_S))
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
+/* INTERRUPT_CORE0_MB_LP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_MB_LP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_M  ((INTERRUPT_CORE0_MB_LP_INT_MAP_V)<<(INTERRUPT_CORE0_MB_LP_INT_MAP_S))
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
+/* INTERRUPT_CORE0_PMU_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_M  ((INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V)<<(INTERRUPT_CORE0_PMU_REG_0_INT_MAP_S))
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C)
+/* INTERRUPT_CORE0_PMU_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_M  ((INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V)<<(INTERRUPT_CORE0_PMU_REG_1_INT_MAP_S))
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
+/* INTERRUPT_CORE0_LP_ANAPERI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_M  ((INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V)<<(INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
+/* INTERRUPT_CORE0_LP_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_M  ((INTERRUPT_CORE0_LP_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_LP_ADC_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
+/* INTERRUPT_CORE0_LP_GPIO_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_M  ((INTERRUPT_CORE0_LP_GPIO_INT_MAP_V)<<(INTERRUPT_CORE0_LP_GPIO_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x2C)
+/* INTERRUPT_CORE0_LP_I2C_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_M  ((INTERRUPT_CORE0_LP_I2C_INT_MAP_V)<<(INTERRUPT_CORE0_LP_I2C_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
+/* INTERRUPT_CORE0_LP_I2S_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_M  ((INTERRUPT_CORE0_LP_I2S_INT_MAP_V)<<(INTERRUPT_CORE0_LP_I2S_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
+/* INTERRUPT_CORE0_LP_SPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_M  ((INTERRUPT_CORE0_LP_SPI_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SPI_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
+/* INTERRUPT_CORE0_LP_TOUCH_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_M  ((INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TOUCH_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x3C)
+/* INTERRUPT_CORE0_LP_TSENS_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_M  ((INTERRUPT_CORE0_LP_TSENS_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TSENS_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
+/* INTERRUPT_CORE0_LP_UART_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_UART_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_M  ((INTERRUPT_CORE0_LP_UART_INT_MAP_V)<<(INTERRUPT_CORE0_LP_UART_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
+/* INTERRUPT_CORE0_LP_EFUSE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_LP_EFUSE_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
+/* INTERRUPT_CORE0_LP_SW_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_SW_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_M  ((INTERRUPT_CORE0_LP_SW_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SW_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x4C)
+/* INTERRUPT_CORE0_LP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SYSREG_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
+/* INTERRUPT_CORE0_LP_HUK_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_M  ((INTERRUPT_CORE0_LP_HUK_INT_MAP_V)<<(INTERRUPT_CORE0_LP_HUK_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
+/* INTERRUPT_CORE0_SYS_ICM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_M  ((INTERRUPT_CORE0_SYS_ICM_INT_MAP_V)<<(INTERRUPT_CORE0_SYS_ICM_INT_MAP_S))
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
+/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M  ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S))
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x5C)
+/* INTERRUPT_CORE0_SDIO_HOST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_M  ((INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V)<<(INTERRUPT_CORE0_SDIO_HOST_INT_MAP_S))
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_GDMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
+/* INTERRUPT_CORE0_GDMA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_GDMA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_GDMA_INT_MAP_M  ((INTERRUPT_CORE0_GDMA_INT_MAP_V)<<(INTERRUPT_CORE0_GDMA_INT_MAP_S))
+#define INTERRUPT_CORE0_GDMA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_GDMA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
+/* INTERRUPT_CORE0_SPI2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SPI2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SPI2_INT_MAP_M  ((INTERRUPT_CORE0_SPI2_INT_MAP_V)<<(INTERRUPT_CORE0_SPI2_INT_MAP_S))
+#define INTERRUPT_CORE0_SPI2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SPI2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
+/* INTERRUPT_CORE0_SPI3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SPI3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SPI3_INT_MAP_M  ((INTERRUPT_CORE0_SPI3_INT_MAP_V)<<(INTERRUPT_CORE0_SPI3_INT_MAP_S))
+#define INTERRUPT_CORE0_SPI3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SPI3_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2S0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x6C)
+/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_I2S0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_I2S0_INT_MAP_M  ((INTERRUPT_CORE0_I2S0_INT_MAP_V)<<(INTERRUPT_CORE0_I2S0_INT_MAP_S))
+#define INTERRUPT_CORE0_I2S0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_I2S0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
+/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_I2S1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_I2S1_INT_MAP_M  ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
+#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_I2S1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2S2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
+/* INTERRUPT_CORE0_I2S2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_I2S2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_I2S2_INT_MAP_M  ((INTERRUPT_CORE0_I2S2_INT_MAP_V)<<(INTERRUPT_CORE0_I2S2_INT_MAP_S))
+#define INTERRUPT_CORE0_I2S2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_I2S2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
+/* INTERRUPT_CORE0_UHCI0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_UHCI0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_M  ((INTERRUPT_CORE0_UHCI0_INT_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INT_MAP_S))
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7C)
+/* INTERRUPT_CORE0_UART0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_UART0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_UART0_INT_MAP_M  ((INTERRUPT_CORE0_UART0_INT_MAP_V)<<(INTERRUPT_CORE0_UART0_INT_MAP_S))
+#define INTERRUPT_CORE0_UART0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_UART0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
+/* INTERRUPT_CORE0_UART1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_UART1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_UART1_INT_MAP_M  ((INTERRUPT_CORE0_UART1_INT_MAP_V)<<(INTERRUPT_CORE0_UART1_INT_MAP_S))
+#define INTERRUPT_CORE0_UART1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_UART1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
+/* INTERRUPT_CORE0_UART2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_UART2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_UART2_INT_MAP_M  ((INTERRUPT_CORE0_UART2_INT_MAP_V)<<(INTERRUPT_CORE0_UART2_INT_MAP_S))
+#define INTERRUPT_CORE0_UART2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_UART2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
+/* INTERRUPT_CORE0_UART3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_UART3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_UART3_INT_MAP_M  ((INTERRUPT_CORE0_UART3_INT_MAP_V)<<(INTERRUPT_CORE0_UART3_INT_MAP_S))
+#define INTERRUPT_CORE0_UART3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_UART3_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x8C)
+/* INTERRUPT_CORE0_UART4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_UART4_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_UART4_INT_MAP_M  ((INTERRUPT_CORE0_UART4_INT_MAP_V)<<(INTERRUPT_CORE0_UART4_INT_MAP_S))
+#define INTERRUPT_CORE0_UART4_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_UART4_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
+/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M  ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE0_LCD_CAM_INT_MAP_S))
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
+/* INTERRUPT_CORE0_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_ADC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_ADC_INT_MAP_M  ((INTERRUPT_CORE0_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_ADC_INT_MAP_S))
+#define INTERRUPT_CORE0_ADC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PWM0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
+/* INTERRUPT_CORE0_PWM0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PWM0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PWM0_INT_MAP_M  ((INTERRUPT_CORE0_PWM0_INT_MAP_V)<<(INTERRUPT_CORE0_PWM0_INT_MAP_S))
+#define INTERRUPT_CORE0_PWM0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PWM0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PWM1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x9C)
+/* INTERRUPT_CORE0_PWM1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PWM1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PWM1_INT_MAP_M  ((INTERRUPT_CORE0_PWM1_INT_MAP_V)<<(INTERRUPT_CORE0_PWM1_INT_MAP_S))
+#define INTERRUPT_CORE0_PWM1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PWM1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CAN0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA0)
+/* INTERRUPT_CORE0_CAN0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CAN0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_CAN0_INT_MAP_M  ((INTERRUPT_CORE0_CAN0_INT_MAP_V)<<(INTERRUPT_CORE0_CAN0_INT_MAP_S))
+#define INTERRUPT_CORE0_CAN0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_CAN0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CAN1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA4)
+/* INTERRUPT_CORE0_CAN1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CAN1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_CAN1_INT_MAP_M  ((INTERRUPT_CORE0_CAN1_INT_MAP_V)<<(INTERRUPT_CORE0_CAN1_INT_MAP_S))
+#define INTERRUPT_CORE0_CAN1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_CAN1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CAN2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA8)
+/* INTERRUPT_CORE0_CAN2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CAN2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_CAN2_INT_MAP_M  ((INTERRUPT_CORE0_CAN2_INT_MAP_V)<<(INTERRUPT_CORE0_CAN2_INT_MAP_S))
+#define INTERRUPT_CORE0_CAN2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_CAN2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_RMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xAC)
+/* INTERRUPT_CORE0_RMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_RMT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_RMT_INT_MAP_M  ((INTERRUPT_CORE0_RMT_INT_MAP_V)<<(INTERRUPT_CORE0_RMT_INT_MAP_S))
+#define INTERRUPT_CORE0_RMT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_RMT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB0)
+/* INTERRUPT_CORE0_I2C0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_I2C0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_I2C0_INT_MAP_M  ((INTERRUPT_CORE0_I2C0_INT_MAP_V)<<(INTERRUPT_CORE0_I2C0_INT_MAP_S))
+#define INTERRUPT_CORE0_I2C0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_I2C0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB4)
+/* INTERRUPT_CORE0_I2C1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_I2C1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_I2C1_INT_MAP_M  ((INTERRUPT_CORE0_I2C1_INT_MAP_V)<<(INTERRUPT_CORE0_I2C1_INT_MAP_S))
+#define INTERRUPT_CORE0_I2C1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_I2C1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB8)
+/* INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xBC)
+/* INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_S))
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC0)
+/* INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC4)
+/* INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC8)
+/* INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_S))
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xCC)
+/* INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD0)
+/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LEDC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
+#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD4)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD8)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xDC)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE0)
+/* INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE4)
+/* INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE8)
+/* INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xEC)
+/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF0)
+/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF4)
+/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF8)
+/* INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xFC)
+/* INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/* INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
+/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_RSA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
+#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_RSA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_AES_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
+#define INTERRUPT_CORE0_AES_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_AES_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SHA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
+#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SHA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ECC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
+/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_ECC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_ECC_INT_MAP_M  ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S))
+#define INTERRUPT_CORE0_ECC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_ECC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/* INTERRUPT_CORE0_ECDSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_ECDSA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_M  ((INTERRUPT_CORE0_ECDSA_INT_MAP_V)<<(INTERRUPT_CORE0_ECDSA_INT_MAP_S))
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_KM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/* INTERRUPT_CORE0_KM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_KM_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_KM_INT_MAP_M  ((INTERRUPT_CORE0_KM_INT_MAP_V)<<(INTERRUPT_CORE0_KM_INT_MAP_S))
+#define INTERRUPT_CORE0_KM_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_KM_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/* INTERRUPT_CORE0_GPIO_INT0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_GPIO_INT0_MAP    0x0000003F
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_M  ((INTERRUPT_CORE0_GPIO_INT0_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT0_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_V  0x3F
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
+/* INTERRUPT_CORE0_GPIO_INT1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_GPIO_INT1_MAP    0x0000003F
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_M  ((INTERRUPT_CORE0_GPIO_INT1_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT1_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_V  0x3F
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/* INTERRUPT_CORE0_GPIO_INT2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_GPIO_INT2_MAP    0x0000003F
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_M  ((INTERRUPT_CORE0_GPIO_INT2_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT2_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_V  0x3F
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/* INTERRUPT_CORE0_GPIO_INT3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_GPIO_INT3_MAP    0x0000003F
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_M  ((INTERRUPT_CORE0_GPIO_INT3_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT3_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_V  0x3F
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/* INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_M  ((INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V)<<(INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_S))
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
+/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP    0x0000003F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V  0x3F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP    0x0000003F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V  0x3F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP    0x0000003F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V  0x3F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP    0x0000003F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V  0x3F
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
+/* INTERRUPT_CORE0_CACHE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CACHE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_CACHE_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_CACHE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/* INTERRUPT_CORE0_FLASH_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_M  ((INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V)<<(INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_S))
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/* INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_S))
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/* INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_S))
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
+/* INTERRUPT_CORE0_CSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CSI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_CSI_INT_MAP_M  ((INTERRUPT_CORE0_CSI_INT_MAP_V)<<(INTERRUPT_CORE0_CSI_INT_MAP_S))
+#define INTERRUPT_CORE0_CSI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_CSI_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/* INTERRUPT_CORE0_DSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_DSI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_DSI_INT_MAP_M  ((INTERRUPT_CORE0_DSI_INT_MAP_V)<<(INTERRUPT_CORE0_DSI_INT_MAP_S))
+#define INTERRUPT_CORE0_DSI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_DSI_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/* INTERRUPT_CORE0_GMII_PHY_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_M  ((INTERRUPT_CORE0_GMII_PHY_INT_MAP_V)<<(INTERRUPT_CORE0_GMII_PHY_INT_MAP_S))
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_LPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/* INTERRUPT_CORE0_LPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_LPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_LPI_INT_MAP_M  ((INTERRUPT_CORE0_LPI_INT_MAP_V)<<(INTERRUPT_CORE0_LPI_INT_MAP_S))
+#define INTERRUPT_CORE0_LPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_LPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
+/* INTERRUPT_CORE0_PMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PMT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PMT_INT_MAP_M  ((INTERRUPT_CORE0_PMT_INT_MAP_V)<<(INTERRUPT_CORE0_PMT_INT_MAP_S))
+#define INTERRUPT_CORE0_PMT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PMT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SBD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/* INTERRUPT_CORE0_SBD_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_SBD_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_SBD_INT_MAP_M  ((INTERRUPT_CORE0_SBD_INT_MAP_V)<<(INTERRUPT_CORE0_SBD_INT_MAP_S))
+#define INTERRUPT_CORE0_SBD_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_SBD_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/* INTERRUPT_CORE0_USB_OTG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_M  ((INTERRUPT_CORE0_USB_OTG_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG_INT_MAP_S))
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/* INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  ((INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S))
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_JPEG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
+/* INTERRUPT_CORE0_JPEG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_JPEG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_JPEG_INT_MAP_M  ((INTERRUPT_CORE0_JPEG_INT_MAP_V)<<(INTERRUPT_CORE0_JPEG_INT_MAP_S))
+#define INTERRUPT_CORE0_JPEG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_JPEG_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PPA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/* INTERRUPT_CORE0_PPA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PPA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PPA_INT_MAP_M  ((INTERRUPT_CORE0_PPA_INT_MAP_V)<<(INTERRUPT_CORE0_PPA_INT_MAP_S))
+#define INTERRUPT_CORE0_PPA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PPA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/* INTERRUPT_CORE0_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_TRACE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_TRACE_INT_MAP_M  ((INTERRUPT_CORE0_TRACE_INT_MAP_V)<<(INTERRUPT_CORE0_TRACE_INT_MAP_S))
+#define INTERRUPT_CORE0_TRACE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_TRACE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/* INTERRUPT_CORE0_CORE1_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_M  ((INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V)<<(INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_S))
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
+/* INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_M  ((INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V)<<(INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_S))
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ISP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/* INTERRUPT_CORE0_ISP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_ISP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_ISP_INT_MAP_M  ((INTERRUPT_CORE0_ISP_INT_MAP_V)<<(INTERRUPT_CORE0_ISP_INT_MAP_S))
+#define INTERRUPT_CORE0_ISP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_ISP_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/* INTERRUPT_CORE0_I3C_MST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I3C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I3C_MST_INT_MAP_S))
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
+/* INTERRUPT_CORE0_I3C_SLV_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_M  ((INTERRUPT_CORE0_I3C_SLV_INT_MAP_V)<<(INTERRUPT_CORE0_I3C_SLV_INT_MAP_S))
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x19C)
+/* INTERRUPT_CORE0_USB_OTG11_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_M  ((INTERRUPT_CORE0_USB_OTG11_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG11_INT_MAP_S))
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0)
+/* INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4)
+/* INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8)
+/* INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC)
+/* INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0)
+/* INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4)
+/* INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_M  ((INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V)<<(INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_S))
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B8)
+/* INTERRUPT_CORE0_HP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE0_HP_SYSREG_INT_MAP_S))
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PCNT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1BC)
+/* INTERRUPT_CORE0_PCNT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_PCNT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_PCNT_INT_MAP_M  ((INTERRUPT_CORE0_PCNT_INT_MAP_V)<<(INTERRUPT_CORE0_PCNT_INT_MAP_S))
+#define INTERRUPT_CORE0_PCNT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_PCNT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C0)
+/* INTERRUPT_CORE0_HP_PAU_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_M  ((INTERRUPT_CORE0_HP_PAU_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PAU_INT_MAP_S))
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C4)
+/* INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_M  ((INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_S))
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C8)
+/* INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_M  ((INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_S))
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1CC)
+/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1D0)
+/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1D4)
+/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1D8)
+/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1DC)
+/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1E0)
+/* INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1E4)
+/* INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1E8)
+/* INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1EC)
+/* INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1F0)
+/* INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1F4)
+/* INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1F8)
+/* INTERRUPT_CORE0_H264_REG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_H264_REG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_M  ((INTERRUPT_CORE0_H264_REG_INT_MAP_V)<<(INTERRUPT_CORE0_H264_REG_INT_MAP_S))
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1FC)
+/* INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_S))
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x200)
+/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_INTR_STATUS_0    0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
+#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x204)
+/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_INTR_STATUS_1    0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
+#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x208)
+/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_INTR_STATUS_2    0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_2_M  ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
+#define INTERRUPT_CORE0_INTR_STATUS_2_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_2_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x20C)
+/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_INTR_STATUS_3    0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_3_M  ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S))
+#define INTERRUPT_CORE0_INTR_STATUS_3_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_3_S  0
+
+#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x210)
+/* INTERRUPT_CORE0_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_REG_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE0_REG_CLK_EN_M  (BIT(0))
+#define INTERRUPT_CORE0_REG_CLK_EN_V  0x1
+#define INTERRUPT_CORE0_REG_CLK_EN_S  0
+
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x3FC)
+/* INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
+/*description: .*/
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_REG_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_REG_DATE_S))
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V  0xFFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h
new file mode 100644
index 0000000000..7ba04340b6
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h
@@ -0,0 +1,1094 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_INTERRUPT_CORE1_REG_H_
+#define _SOC_INTERRUPT_CORE1_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x0)
+/* INTERRUPT_CORE1_LP_RTC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_M  ((INTERRUPT_CORE1_LP_RTC_INT_MAP_V)<<(INTERRUPT_CORE1_LP_RTC_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x4)
+/* INTERRUPT_CORE1_LP_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_M  ((INTERRUPT_CORE1_LP_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_LP_WDT_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x8)
+/* INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_M  ((INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC)
+/* INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_M  ((INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x10)
+/* INTERRUPT_CORE1_MB_HP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_MB_HP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_M  ((INTERRUPT_CORE1_MB_HP_INT_MAP_V)<<(INTERRUPT_CORE1_MB_HP_INT_MAP_S))
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x14)
+/* INTERRUPT_CORE1_MB_LP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_MB_LP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_M  ((INTERRUPT_CORE1_MB_LP_INT_MAP_V)<<(INTERRUPT_CORE1_MB_LP_INT_MAP_S))
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x18)
+/* INTERRUPT_CORE1_PMU_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_M  ((INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V)<<(INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S))
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C)
+/* INTERRUPT_CORE1_PMU_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_M  ((INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V)<<(INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S))
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x20)
+/* INTERRUPT_CORE1_LP_ANAPERI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_M  ((INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V)<<(INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x24)
+/* INTERRUPT_CORE1_LP_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_M  ((INTERRUPT_CORE1_LP_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_LP_ADC_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x28)
+/* INTERRUPT_CORE1_LP_GPIO_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_M  ((INTERRUPT_CORE1_LP_GPIO_INT_MAP_V)<<(INTERRUPT_CORE1_LP_GPIO_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x2C)
+/* INTERRUPT_CORE1_LP_I2C_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_M  ((INTERRUPT_CORE1_LP_I2C_INT_MAP_V)<<(INTERRUPT_CORE1_LP_I2C_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x30)
+/* INTERRUPT_CORE1_LP_I2S_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_M  ((INTERRUPT_CORE1_LP_I2S_INT_MAP_V)<<(INTERRUPT_CORE1_LP_I2S_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x34)
+/* INTERRUPT_CORE1_LP_SPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_M  ((INTERRUPT_CORE1_LP_SPI_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SPI_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x38)
+/* INTERRUPT_CORE1_LP_TOUCH_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_M  ((INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x3C)
+/* INTERRUPT_CORE1_LP_TSENS_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_M  ((INTERRUPT_CORE1_LP_TSENS_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TSENS_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x40)
+/* INTERRUPT_CORE1_LP_UART_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_UART_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_M  ((INTERRUPT_CORE1_LP_UART_INT_MAP_V)<<(INTERRUPT_CORE1_LP_UART_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x44)
+/* INTERRUPT_CORE1_LP_EFUSE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_M  ((INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x48)
+/* INTERRUPT_CORE1_LP_SW_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_SW_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_M  ((INTERRUPT_CORE1_LP_SW_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SW_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x4C)
+/* INTERRUPT_CORE1_LP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x50)
+/* INTERRUPT_CORE1_LP_HUK_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_M  ((INTERRUPT_CORE1_LP_HUK_INT_MAP_V)<<(INTERRUPT_CORE1_LP_HUK_INT_MAP_S))
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x54)
+/* INTERRUPT_CORE1_SYS_ICM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_M  ((INTERRUPT_CORE1_SYS_ICM_INT_MAP_V)<<(INTERRUPT_CORE1_SYS_ICM_INT_MAP_S))
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x58)
+/* INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M  ((INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S))
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x5C)
+/* INTERRUPT_CORE1_SDIO_HOST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_M  ((INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V)<<(INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S))
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_GDMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x60)
+/* INTERRUPT_CORE1_GDMA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_GDMA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_GDMA_INT_MAP_M  ((INTERRUPT_CORE1_GDMA_INT_MAP_V)<<(INTERRUPT_CORE1_GDMA_INT_MAP_S))
+#define INTERRUPT_CORE1_GDMA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_GDMA_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SPI2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x64)
+/* INTERRUPT_CORE1_SPI2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SPI2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SPI2_INT_MAP_M  ((INTERRUPT_CORE1_SPI2_INT_MAP_V)<<(INTERRUPT_CORE1_SPI2_INT_MAP_S))
+#define INTERRUPT_CORE1_SPI2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SPI2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SPI3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x68)
+/* INTERRUPT_CORE1_SPI3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SPI3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SPI3_INT_MAP_M  ((INTERRUPT_CORE1_SPI3_INT_MAP_V)<<(INTERRUPT_CORE1_SPI3_INT_MAP_S))
+#define INTERRUPT_CORE1_SPI3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SPI3_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_I2S0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x6C)
+/* INTERRUPT_CORE1_I2S0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_I2S0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_I2S0_INT_MAP_M  ((INTERRUPT_CORE1_I2S0_INT_MAP_V)<<(INTERRUPT_CORE1_I2S0_INT_MAP_S))
+#define INTERRUPT_CORE1_I2S0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_I2S0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x70)
+/* INTERRUPT_CORE1_I2S1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_I2S1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_I2S1_INT_MAP_M  ((INTERRUPT_CORE1_I2S1_INT_MAP_V)<<(INTERRUPT_CORE1_I2S1_INT_MAP_S))
+#define INTERRUPT_CORE1_I2S1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_I2S1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_I2S2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x74)
+/* INTERRUPT_CORE1_I2S2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_I2S2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_I2S2_INT_MAP_M  ((INTERRUPT_CORE1_I2S2_INT_MAP_V)<<(INTERRUPT_CORE1_I2S2_INT_MAP_S))
+#define INTERRUPT_CORE1_I2S2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_I2S2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x78)
+/* INTERRUPT_CORE1_UHCI0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_UHCI0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_M  ((INTERRUPT_CORE1_UHCI0_INT_MAP_V)<<(INTERRUPT_CORE1_UHCI0_INT_MAP_S))
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_UART0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x7C)
+/* INTERRUPT_CORE1_UART0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_UART0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_UART0_INT_MAP_M  ((INTERRUPT_CORE1_UART0_INT_MAP_V)<<(INTERRUPT_CORE1_UART0_INT_MAP_S))
+#define INTERRUPT_CORE1_UART0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_UART0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_UART1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x80)
+/* INTERRUPT_CORE1_UART1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_UART1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_UART1_INT_MAP_M  ((INTERRUPT_CORE1_UART1_INT_MAP_V)<<(INTERRUPT_CORE1_UART1_INT_MAP_S))
+#define INTERRUPT_CORE1_UART1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_UART1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_UART2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x84)
+/* INTERRUPT_CORE1_UART2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_UART2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_UART2_INT_MAP_M  ((INTERRUPT_CORE1_UART2_INT_MAP_V)<<(INTERRUPT_CORE1_UART2_INT_MAP_S))
+#define INTERRUPT_CORE1_UART2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_UART2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_UART3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x88)
+/* INTERRUPT_CORE1_UART3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_UART3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_UART3_INT_MAP_M  ((INTERRUPT_CORE1_UART3_INT_MAP_V)<<(INTERRUPT_CORE1_UART3_INT_MAP_S))
+#define INTERRUPT_CORE1_UART3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_UART3_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_UART4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x8C)
+/* INTERRUPT_CORE1_UART4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_UART4_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_UART4_INT_MAP_M  ((INTERRUPT_CORE1_UART4_INT_MAP_V)<<(INTERRUPT_CORE1_UART4_INT_MAP_S))
+#define INTERRUPT_CORE1_UART4_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_UART4_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x90)
+/* INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M  ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE1_LCD_CAM_INT_MAP_S))
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x94)
+/* INTERRUPT_CORE1_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_ADC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_ADC_INT_MAP_M  ((INTERRUPT_CORE1_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_ADC_INT_MAP_S))
+#define INTERRUPT_CORE1_ADC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PWM0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x98)
+/* INTERRUPT_CORE1_PWM0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PWM0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PWM0_INT_MAP_M  ((INTERRUPT_CORE1_PWM0_INT_MAP_V)<<(INTERRUPT_CORE1_PWM0_INT_MAP_S))
+#define INTERRUPT_CORE1_PWM0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PWM0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PWM1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x9C)
+/* INTERRUPT_CORE1_PWM1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PWM1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PWM1_INT_MAP_M  ((INTERRUPT_CORE1_PWM1_INT_MAP_V)<<(INTERRUPT_CORE1_PWM1_INT_MAP_S))
+#define INTERRUPT_CORE1_PWM1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PWM1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_CAN0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xA0)
+/* INTERRUPT_CORE1_CAN0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CAN0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_CAN0_INT_MAP_M  ((INTERRUPT_CORE1_CAN0_INT_MAP_V)<<(INTERRUPT_CORE1_CAN0_INT_MAP_S))
+#define INTERRUPT_CORE1_CAN0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_CAN0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_CAN1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xA4)
+/* INTERRUPT_CORE1_CAN1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CAN1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_CAN1_INT_MAP_M  ((INTERRUPT_CORE1_CAN1_INT_MAP_V)<<(INTERRUPT_CORE1_CAN1_INT_MAP_S))
+#define INTERRUPT_CORE1_CAN1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_CAN1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_CAN2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xA8)
+/* INTERRUPT_CORE1_CAN2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CAN2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_CAN2_INT_MAP_M  ((INTERRUPT_CORE1_CAN2_INT_MAP_V)<<(INTERRUPT_CORE1_CAN2_INT_MAP_S))
+#define INTERRUPT_CORE1_CAN2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_CAN2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_RMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xAC)
+/* INTERRUPT_CORE1_RMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_RMT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_RMT_INT_MAP_M  ((INTERRUPT_CORE1_RMT_INT_MAP_V)<<(INTERRUPT_CORE1_RMT_INT_MAP_S))
+#define INTERRUPT_CORE1_RMT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_RMT_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_I2C0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xB0)
+/* INTERRUPT_CORE1_I2C0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_I2C0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_I2C0_INT_MAP_M  ((INTERRUPT_CORE1_I2C0_INT_MAP_V)<<(INTERRUPT_CORE1_I2C0_INT_MAP_S))
+#define INTERRUPT_CORE1_I2C0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_I2C0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_I2C1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xB4)
+/* INTERRUPT_CORE1_I2C1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_I2C1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_I2C1_INT_MAP_M  ((INTERRUPT_CORE1_I2C1_INT_MAP_V)<<(INTERRUPT_CORE1_I2C1_INT_MAP_S))
+#define INTERRUPT_CORE1_I2C1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_I2C1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xB8)
+/* INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S))
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xBC)
+/* INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S))
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC0)
+/* INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S))
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC4)
+/* INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S))
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC8)
+/* INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S))
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xCC)
+/* INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S))
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xD0)
+/* INTERRUPT_CORE1_LEDC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LEDC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LEDC_INT_MAP_M  ((INTERRUPT_CORE1_LEDC_INT_MAP_V)<<(INTERRUPT_CORE1_LEDC_INT_MAP_S))
+#define INTERRUPT_CORE1_LEDC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LEDC_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xD4)
+/* INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S))
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xD8)
+/* INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S))
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xDC)
+/* INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S))
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xE0)
+/* INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xE4)
+/* INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xE8)
+/* INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S))
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xEC)
+/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xF0)
+/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xF4)
+/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xF8)
+/* INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xFC)
+/* INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x100)
+/* INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S))
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x104)
+/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x108)
+/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x10C)
+/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x110)
+/* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_RSA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_RSA_INT_MAP_M  ((INTERRUPT_CORE1_RSA_INT_MAP_V)<<(INTERRUPT_CORE1_RSA_INT_MAP_S))
+#define INTERRUPT_CORE1_RSA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_RSA_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x114)
+/* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_AES_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_AES_INT_MAP_M  ((INTERRUPT_CORE1_AES_INT_MAP_V)<<(INTERRUPT_CORE1_AES_INT_MAP_S))
+#define INTERRUPT_CORE1_AES_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_AES_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x118)
+/* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SHA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SHA_INT_MAP_M  ((INTERRUPT_CORE1_SHA_INT_MAP_V)<<(INTERRUPT_CORE1_SHA_INT_MAP_S))
+#define INTERRUPT_CORE1_SHA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SHA_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_ECC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x11C)
+/* INTERRUPT_CORE1_ECC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_ECC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_ECC_INT_MAP_M  ((INTERRUPT_CORE1_ECC_INT_MAP_V)<<(INTERRUPT_CORE1_ECC_INT_MAP_S))
+#define INTERRUPT_CORE1_ECC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_ECC_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x120)
+/* INTERRUPT_CORE1_ECDSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_ECDSA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_M  ((INTERRUPT_CORE1_ECDSA_INT_MAP_V)<<(INTERRUPT_CORE1_ECDSA_INT_MAP_S))
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_KM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x124)
+/* INTERRUPT_CORE1_KM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_KM_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_KM_INT_MAP_M  ((INTERRUPT_CORE1_KM_INT_MAP_V)<<(INTERRUPT_CORE1_KM_INT_MAP_S))
+#define INTERRUPT_CORE1_KM_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_KM_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x128)
+/* INTERRUPT_CORE1_GPIO_INT0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_GPIO_INT0_MAP    0x0000003F
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_M  ((INTERRUPT_CORE1_GPIO_INT0_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT0_MAP_S))
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_V  0x3F
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_S  0
+
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x12C)
+/* INTERRUPT_CORE1_GPIO_INT1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_GPIO_INT1_MAP    0x0000003F
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_M  ((INTERRUPT_CORE1_GPIO_INT1_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT1_MAP_S))
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_V  0x3F
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_S  0
+
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x130)
+/* INTERRUPT_CORE1_GPIO_INT2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_GPIO_INT2_MAP    0x0000003F
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_M  ((INTERRUPT_CORE1_GPIO_INT2_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT2_MAP_S))
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_V  0x3F
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_S  0
+
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x134)
+/* INTERRUPT_CORE1_GPIO_INT3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_GPIO_INT3_MAP    0x0000003F
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_M  ((INTERRUPT_CORE1_GPIO_INT3_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT3_MAP_S))
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_V  0x3F
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_S  0
+
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x138)
+/* INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_M  ((INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V)<<(INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S))
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x13C)
+/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP    0x0000003F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S))
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V  0x3F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S  0
+
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x140)
+/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP    0x0000003F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S))
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V  0x3F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S  0
+
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x144)
+/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP    0x0000003F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S))
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V  0x3F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S  0
+
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x148)
+/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP    0x0000003F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S))
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V  0x3F
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S  0
+
+#define INTERRUPT_CORE1_CACHE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x14C)
+/* INTERRUPT_CORE1_CACHE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CACHE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_CACHE_INT_MAP_M  ((INTERRUPT_CORE1_CACHE_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_INT_MAP_S))
+#define INTERRUPT_CORE1_CACHE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_CACHE_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x150)
+/* INTERRUPT_CORE1_FLASH_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_M  ((INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V)<<(INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S))
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x154)
+/* INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S))
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x158)
+/* INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S))
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_CSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x15C)
+/* INTERRUPT_CORE1_CSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CSI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_CSI_INT_MAP_M  ((INTERRUPT_CORE1_CSI_INT_MAP_V)<<(INTERRUPT_CORE1_CSI_INT_MAP_S))
+#define INTERRUPT_CORE1_CSI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_CSI_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_DSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x160)
+/* INTERRUPT_CORE1_DSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_DSI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_DSI_INT_MAP_M  ((INTERRUPT_CORE1_DSI_INT_MAP_V)<<(INTERRUPT_CORE1_DSI_INT_MAP_S))
+#define INTERRUPT_CORE1_DSI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_DSI_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x164)
+/* INTERRUPT_CORE1_GMII_PHY_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_M  ((INTERRUPT_CORE1_GMII_PHY_INT_MAP_V)<<(INTERRUPT_CORE1_GMII_PHY_INT_MAP_S))
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_LPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x168)
+/* INTERRUPT_CORE1_LPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_LPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_LPI_INT_MAP_M  ((INTERRUPT_CORE1_LPI_INT_MAP_V)<<(INTERRUPT_CORE1_LPI_INT_MAP_S))
+#define INTERRUPT_CORE1_LPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_LPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x16C)
+/* INTERRUPT_CORE1_PMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PMT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PMT_INT_MAP_M  ((INTERRUPT_CORE1_PMT_INT_MAP_V)<<(INTERRUPT_CORE1_PMT_INT_MAP_S))
+#define INTERRUPT_CORE1_PMT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PMT_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_SBD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x170)
+/* INTERRUPT_CORE1_SBD_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_SBD_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_SBD_INT_MAP_M  ((INTERRUPT_CORE1_SBD_INT_MAP_V)<<(INTERRUPT_CORE1_SBD_INT_MAP_S))
+#define INTERRUPT_CORE1_SBD_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_SBD_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x174)
+/* INTERRUPT_CORE1_USB_OTG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_M  ((INTERRUPT_CORE1_USB_OTG_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG_INT_MAP_S))
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x178)
+/* INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  ((INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S))
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_JPEG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x17C)
+/* INTERRUPT_CORE1_JPEG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_JPEG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_JPEG_INT_MAP_M  ((INTERRUPT_CORE1_JPEG_INT_MAP_V)<<(INTERRUPT_CORE1_JPEG_INT_MAP_S))
+#define INTERRUPT_CORE1_JPEG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_JPEG_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PPA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x180)
+/* INTERRUPT_CORE1_PPA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PPA_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PPA_INT_MAP_M  ((INTERRUPT_CORE1_PPA_INT_MAP_V)<<(INTERRUPT_CORE1_PPA_INT_MAP_S))
+#define INTERRUPT_CORE1_PPA_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PPA_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x184)
+/* INTERRUPT_CORE1_CORE0_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_M  ((INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V)<<(INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S))
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x188)
+/* INTERRUPT_CORE1_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_TRACE_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_TRACE_INT_MAP_M  ((INTERRUPT_CORE1_TRACE_INT_MAP_V)<<(INTERRUPT_CORE1_TRACE_INT_MAP_S))
+#define INTERRUPT_CORE1_TRACE_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_TRACE_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x18C)
+/* INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_M  ((INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V)<<(INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S))
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_ISP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x190)
+/* INTERRUPT_CORE1_ISP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_ISP_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_ISP_INT_MAP_M  ((INTERRUPT_CORE1_ISP_INT_MAP_V)<<(INTERRUPT_CORE1_ISP_INT_MAP_S))
+#define INTERRUPT_CORE1_ISP_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_ISP_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x194)
+/* INTERRUPT_CORE1_I3C_MST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_M  ((INTERRUPT_CORE1_I3C_MST_INT_MAP_V)<<(INTERRUPT_CORE1_I3C_MST_INT_MAP_S))
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x198)
+/* INTERRUPT_CORE1_I3C_SLV_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_M  ((INTERRUPT_CORE1_I3C_SLV_INT_MAP_V)<<(INTERRUPT_CORE1_I3C_SLV_INT_MAP_S))
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x19C)
+/* INTERRUPT_CORE1_USB_OTG11_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_M  ((INTERRUPT_CORE1_USB_OTG11_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG11_INT_MAP_S))
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1A0)
+/* INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1A4)
+/* INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1A8)
+/* INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1AC)
+/* INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1B0)
+/* INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1B4)
+/* INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_M  ((INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V)<<(INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S))
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1B8)
+/* INTERRUPT_CORE1_HP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S))
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_PCNT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1BC)
+/* INTERRUPT_CORE1_PCNT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_PCNT_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_PCNT_INT_MAP_M  ((INTERRUPT_CORE1_PCNT_INT_MAP_V)<<(INTERRUPT_CORE1_PCNT_INT_MAP_S))
+#define INTERRUPT_CORE1_PCNT_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_PCNT_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C0)
+/* INTERRUPT_CORE1_HP_PAU_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_M  ((INTERRUPT_CORE1_HP_PAU_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PAU_INT_MAP_S))
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C4)
+/* INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_M  ((INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S))
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C8)
+/* INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_M  ((INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S))
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1CC)
+/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1D0)
+/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1D4)
+/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1D8)
+/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1DC)
+/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1E0)
+/* INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1E4)
+/* INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1E8)
+/* INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1EC)
+/* INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1F0)
+/* INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1F4)
+/* INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1F8)
+/* INTERRUPT_CORE1_H264_REG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_H264_REG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_M  ((INTERRUPT_CORE1_H264_REG_INT_MAP_V)<<(INTERRUPT_CORE1_H264_REG_INT_MAP_S))
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1FC)
+/* INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP    0x0000003F
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_M  ((INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V)<<(INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S))
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V  0x3F
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S  0
+
+#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x200)
+/* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_INTR_STATUS_0    0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_0_M  ((INTERRUPT_CORE1_INTR_STATUS_0_V)<<(INTERRUPT_CORE1_INTR_STATUS_0_S))
+#define INTERRUPT_CORE1_INTR_STATUS_0_V  0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_0_S  0
+
+#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x204)
+/* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_INTR_STATUS_1    0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_1_M  ((INTERRUPT_CORE1_INTR_STATUS_1_V)<<(INTERRUPT_CORE1_INTR_STATUS_1_S))
+#define INTERRUPT_CORE1_INTR_STATUS_1_V  0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_1_S  0
+
+#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x208)
+/* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_INTR_STATUS_2    0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_2_M  ((INTERRUPT_CORE1_INTR_STATUS_2_V)<<(INTERRUPT_CORE1_INTR_STATUS_2_S))
+#define INTERRUPT_CORE1_INTR_STATUS_2_V  0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_2_S  0
+
+#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x20C)
+/* INTERRUPT_CORE1_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_INTR_STATUS_3    0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_3_M  ((INTERRUPT_CORE1_INTR_STATUS_3_V)<<(INTERRUPT_CORE1_INTR_STATUS_3_S))
+#define INTERRUPT_CORE1_INTR_STATUS_3_V  0xFFFFFFFF
+#define INTERRUPT_CORE1_INTR_STATUS_3_S  0
+
+#define INTERRUPT_CORE1_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x210)
+/* INTERRUPT_CORE1_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_REG_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE1_REG_CLK_EN_M  (BIT(0))
+#define INTERRUPT_CORE1_REG_CLK_EN_V  0x1
+#define INTERRUPT_CORE1_REG_CLK_EN_S  0
+
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x3FC)
+/* INTERRUPT_CORE1_INTERRUPT_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
+/*description: .*/
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE    0x0FFFFFFF
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_M  ((INTERRUPT_CORE1_INTERRUPT_REG_DATE_V)<<(INTERRUPT_CORE1_INTERRUPT_REG_DATE_S))
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_V  0xFFFFFFF
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_CORE1_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h b/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h
new file mode 100644
index 0000000000..1c41e19b79
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h
@@ -0,0 +1,999 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
+/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M  (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
+/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M  (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S)
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S  0
+
+/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
+/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M  (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S)
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S  0
+
+/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
+/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M  (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S)
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
+/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BT_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_M  (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
+/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BT_BB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_BB_INTR_MAP_M  (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
+#define INTMTX_CORE0_BT_BB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_BB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
+/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BT_BB_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_BB_NMI_MAP_M  (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
+#define INTMTX_CORE0_BT_BB_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_BB_NMI_MAP_S  0
+
+/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
+/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_COEX_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
+/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_COEX_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_COEX_INTR_MAP_M  (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
+#define INTMTX_CORE0_COEX_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_COEX_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
+/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
+/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M  (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
+/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_I2C_MST_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_M  (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S)
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_S  0
+
+/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
+/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M  (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PMU_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
+/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PMU_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PMU_INTR_MAP_M  (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
+#define INTMTX_CORE0_PMU_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PMU_INTR_MAP_S  0
+
+/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
+/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_EFUSE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_EFUSE_INTR_MAP_M  (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
+#define INTMTX_CORE0_EFUSE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_EFUSE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
+/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
+/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_UART_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_UART_INTR_MAP_M  (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S)
+#define INTMTX_CORE0_LP_UART_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_UART_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
+/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_I2C_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_M  (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S)
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
+/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_M  (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
+/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
+/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
+/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S)
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
+/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
+/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TRACE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TRACE_INTR_MAP_M  (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
+#define INTMTX_CORE0_TRACE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TRACE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
+/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CACHE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CACHE_INTR_MAP_M  (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
+#define INTMTX_CORE0_CACHE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CACHE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
+/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
+
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
+
+/** INTMTX_CORE0_PAU_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
+/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PAU_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PAU_INTR_MAP_M  (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
+#define INTMTX_CORE0_PAU_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PAU_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
+/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
+/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
+/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
+/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
+/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
+/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
+/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_APM0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_M  (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S)
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
+/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_MSPI_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_MSPI_INTR_MAP_M  (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
+#define INTMTX_CORE0_MSPI_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_MSPI_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
+/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_I2S1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2S1_INTR_MAP_M  (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
+#define INTMTX_CORE0_I2S1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2S1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
+/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_UHCI0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UHCI0_INTR_MAP_M  (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
+#define INTMTX_CORE0_UHCI0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UHCI0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UART0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
+/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_UART0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UART0_INTR_MAP_M  (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
+#define INTMTX_CORE0_UART0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UART0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UART1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
+/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_UART1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UART1_INTR_MAP_M  (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
+#define INTMTX_CORE0_UART1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UART1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
+/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LEDC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LEDC_INTR_MAP_M  (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
+#define INTMTX_CORE0_LEDC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LEDC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
+/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CAN0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CAN0_INTR_MAP_M  (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
+#define INTMTX_CORE0_CAN0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CAN0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CAN1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
+/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CAN1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CAN1_INTR_MAP_M  (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S)
+#define INTMTX_CORE0_CAN1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CAN1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_USB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
+/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_USB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_USB_INTR_MAP_M  (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
+#define INTMTX_CORE0_USB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_USB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_RMT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
+/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_RMT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_RMT_INTR_MAP_M  (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
+#define INTMTX_CORE0_RMT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_RMT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
+/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
+/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG0_T0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_M  (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
+/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG0_T1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_M  (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
+/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M  (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
+/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG1_T0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_M  (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
+/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG1_T1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_M  (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
+/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M  (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
+/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
+/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
+/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
+/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_APB_ADC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_M  (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PWM_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
+/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PWM_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PWM_INTR_MAP_M  (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
+#define INTMTX_CORE0_PWM_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PWM_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
+/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PCNT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PCNT_INTR_MAP_M  (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
+#define INTMTX_CORE0_PCNT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PCNT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
+/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PARL_IO_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S)
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SLC0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
+/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SLC0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SLC0_INTR_MAP_M  (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S)
+#define INTMTX_CORE0_SLC0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SLC0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SLC1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
+/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SLC1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SLC1_INTR_MAP_M  (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S)
+#define INTMTX_CORE0_SLC1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SLC1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
+/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
+/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
+/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114)
+/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118)
+/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c)
+/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120)
+/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_GPSPI2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_M  (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_AES_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124)
+/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_AES_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_AES_INTR_MAP_M  (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
+#define INTMTX_CORE0_AES_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_AES_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SHA_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128)
+/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SHA_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SHA_INTR_MAP_M  (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
+#define INTMTX_CORE0_SHA_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SHA_INTR_MAP_S  0
+
+/** INTMTX_CORE0_RSA_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c)
+/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_RSA_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_RSA_INTR_MAP_M  (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
+#define INTMTX_CORE0_RSA_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_RSA_INTR_MAP_S  0
+
+/** INTMTX_CORE0_ECC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130)
+/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_ECC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ECC_INTR_MAP_M  (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
+#define INTMTX_CORE0_ECC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ECC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134)
+/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INT_STATUS_0    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_0_M  (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
+#define INTMTX_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_0_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138)
+/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INT_STATUS_1    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_1_M  (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
+#define INTMTX_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_1_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c)
+/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INT_STATUS_2    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_2_M  (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
+#define INTMTX_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_2_S  0
+
+/** INTMTX_CORE0_CLOCK_GATE_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140)
+/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define INTMTX_CORE0_REG_CLK_EN    (BIT(0))
+#define INTMTX_CORE0_REG_CLK_EN_M  (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
+#define INTMTX_CORE0_REG_CLK_EN_V  0x00000001U
+#define INTMTX_CORE0_REG_CLK_EN_S  0
+
+/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
+/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_M  (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h b/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h
new file mode 100644
index 0000000000..95dff43fc6
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h
@@ -0,0 +1,1254 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of wifi_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_mac_intr_map_reg_t;
+
+/** Type of wifi_mac_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_mac_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_mac_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_mac_nmi_map_reg_t;
+
+/** Type of wifi_pwr_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_pwr_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_pwr_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_pwr_intr_map_reg_t;
+
+/** Type of wifi_bb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_bb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_bb_intr_map_reg_t;
+
+/** Type of bt_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_bt_mac_intr_map_reg_t;
+
+/** Type of bt_bb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_bb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_bt_bb_intr_map_reg_t;
+
+/** Type of bt_bb_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_bb_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_bt_bb_nmi_map_reg_t;
+
+/** Type of lp_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_timer_intr_map_reg_t;
+
+/** Type of coex_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** coex_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t coex_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_coex_intr_map_reg_t;
+
+/** Type of ble_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ble_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ble_timer_intr_map_reg_t;
+
+/** Type of ble_sec_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ble_sec_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ble_sec_intr_map_reg_t;
+
+/** Type of i2c_mst_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2c_mst_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t i2c_mst_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_i2c_mst_intr_map_reg_t;
+
+/** Type of zb_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t zb_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_zb_mac_intr_map_reg_t;
+
+/** Type of pmu_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pmu_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pmu_intr_map_reg_t;
+
+/** Type of efuse_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t efuse_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_efuse_intr_map_reg_t;
+
+/** Type of lp_rtc_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_rtc_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_rtc_timer_intr_map_reg_t;
+
+/** Type of lp_uart_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_uart_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_uart_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_uart_intr_map_reg_t;
+
+/** Type of lp_i2c_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_i2c_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_i2c_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_i2c_intr_map_reg_t;
+
+/** Type of lp_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_wdt_intr_map_reg_t;
+
+/** Type of lp_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_peri_timeout_intr_map_reg_t;
+
+/** Type of lp_apm_m0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_apm_m0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_apm_m0_intr_map_reg_t;
+
+/** Type of lp_apm_m1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_apm_m1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_apm_m1_intr_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_0_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_0_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_1_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_1_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_2_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_2_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_3_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_3_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t;
+
+/** Type of assist_debug_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t assist_debug_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_assist_debug_intr_map_reg_t;
+
+/** Type of trace_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** trace_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t trace_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_trace_intr_map_reg_t;
+
+/** Type of cache_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cache_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cache_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cache_intr_map_reg_t;
+
+/** Type of cpu_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t;
+
+/** Type of gpio_interrupt_pro_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t gpio_interrupt_pro_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_gpio_interrupt_pro_map_reg_t;
+
+/** Type of gpio_interrupt_pro_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t gpio_interrupt_pro_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t;
+
+/** Type of pau_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pau_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pau_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pau_intr_map_reg_t;
+
+/** Type of hp_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_peri_timeout_intr_map_reg_t;
+
+/** Type of modem_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** modem_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t modem_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_modem_peri_timeout_intr_map_reg_t;
+
+/** Type of hp_apm_m0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m0_intr_map_reg_t;
+
+/** Type of hp_apm_m1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m1_intr_map_reg_t;
+
+/** Type of hp_apm_m2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m2_intr_map_reg_t;
+
+/** Type of hp_apm_m3_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m3_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m3_intr_map_reg_t;
+
+/** Type of lp_apm0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_apm0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_apm0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_apm0_intr_map_reg_t;
+
+/** Type of mspi_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t mspi_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_mspi_intr_map_reg_t;
+
+/** Type of i2s1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t i2s1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_i2s1_intr_map_reg_t;
+
+/** Type of uhci0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t uhci0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_uhci0_intr_map_reg_t;
+
+/** Type of uart0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t uart0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_uart0_intr_map_reg_t;
+
+/** Type of uart1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t uart1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_uart1_intr_map_reg_t;
+
+/** Type of ledc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ledc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ledc_intr_map_reg_t;
+
+/** Type of can0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** can0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t can0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_can0_intr_map_reg_t;
+
+/** Type of can1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** can1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t can1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_can1_intr_map_reg_t;
+
+/** Type of usb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** usb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t usb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_usb_intr_map_reg_t;
+
+/** Type of rmt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rmt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_rmt_intr_map_reg_t;
+
+/** Type of i2c_ext0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t i2c_ext0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_i2c_ext0_intr_map_reg_t;
+
+/** Type of tg0_t0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg0_t0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg0_t0_intr_map_reg_t;
+
+/** Type of tg0_t1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg0_t1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg0_t1_intr_map_reg_t;
+
+/** Type of tg0_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg0_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg0_wdt_intr_map_reg_t;
+
+/** Type of tg1_t0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg1_t0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg1_t0_intr_map_reg_t;
+
+/** Type of tg1_t1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg1_t1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg1_t1_intr_map_reg_t;
+
+/** Type of tg1_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg1_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg1_wdt_intr_map_reg_t;
+
+/** Type of systimer_target0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t systimer_target0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_systimer_target0_intr_map_reg_t;
+
+/** Type of systimer_target1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t systimer_target1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_systimer_target1_intr_map_reg_t;
+
+/** Type of systimer_target2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t systimer_target2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_systimer_target2_intr_map_reg_t;
+
+/** Type of apb_adc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t apb_adc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_apb_adc_intr_map_reg_t;
+
+/** Type of pwm_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pwm_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pwm_intr_map_reg_t;
+
+/** Type of pcnt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pcnt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pcnt_intr_map_reg_t;
+
+/** Type of parl_io_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** parl_io_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t parl_io_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_parl_io_intr_map_reg_t;
+
+/** Type of slc0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slc0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t slc0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_slc0_intr_map_reg_t;
+
+/** Type of slc1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slc1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t slc1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_slc1_intr_map_reg_t;
+
+/** Type of dma_in_ch0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_in_ch0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_in_ch0_intr_map_reg_t;
+
+/** Type of dma_in_ch1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_in_ch1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_in_ch1_intr_map_reg_t;
+
+/** Type of dma_in_ch2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_in_ch2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_in_ch2_intr_map_reg_t;
+
+/** Type of dma_out_ch0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_out_ch0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_out_ch0_intr_map_reg_t;
+
+/** Type of dma_out_ch1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_out_ch1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_out_ch1_intr_map_reg_t;
+
+/** Type of dma_out_ch2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_out_ch2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_out_ch2_intr_map_reg_t;
+
+/** Type of gpspi2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t gpspi2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_gpspi2_intr_map_reg_t;
+
+/** Type of aes_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** aes_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t aes_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_aes_intr_map_reg_t;
+
+/** Type of sha_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** sha_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t sha_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_sha_intr_map_reg_t;
+
+/** Type of rsa_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rsa_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_rsa_intr_map_reg_t;
+
+/** Type of ecc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ecc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ecc_intr_map_reg_t;
+
+/** Type of int_status_reg_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t int_status_0:32;
+    };
+    uint32_t val;
+} interrupt_matrix_int_status_reg_0_reg_t;
+
+/** Type of int_status_reg_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t int_status_1:32;
+    };
+    uint32_t val;
+} interrupt_matrix_int_status_reg_1_reg_t;
+
+/** Type of int_status_reg_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t int_status_2:32;
+    };
+    uint32_t val;
+} interrupt_matrix_int_status_reg_2_reg_t;
+
+/** Type of clock_gate register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} interrupt_matrix_clock_gate_reg_t;
+
+/** Type of interrupt_reg_date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35664144;
+         *  Need add description
+         */
+        uint32_t interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} interrupt_matrix_interrupt_reg_date_reg_t;
+
+
+typedef struct interrupt_matrix_dev_t {
+    volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map;
+    volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map;
+    volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map;
+    volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map;
+    volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map;
+    volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map;
+    volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map;
+    volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map;
+    volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map;
+    volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map;
+    volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map;
+    volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map;
+    volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map;
+    volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map;
+    volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map;
+    volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
+    volatile interrupt_matrix_lp_uart_intr_map_reg_t lp_uart_intr_map;
+    volatile interrupt_matrix_lp_i2c_intr_map_reg_t lp_i2c_intr_map;
+    volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
+    volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
+    volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
+    volatile interrupt_matrix_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
+    volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map;
+    volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map;
+    volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map;
+    volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map;
+    volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map;
+    volatile interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map;
+    volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map;
+    volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map;
+    volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map;
+    volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
+    volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
+    volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
+    volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
+    volatile interrupt_matrix_lp_apm0_intr_map_reg_t lp_apm0_intr_map;
+    volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map;
+    volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map;
+    volatile interrupt_matrix_uhci0_intr_map_reg_t uhci0_intr_map;
+    volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map;
+    volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map;
+    volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map;
+    volatile interrupt_matrix_can0_intr_map_reg_t can0_intr_map;
+    volatile interrupt_matrix_can1_intr_map_reg_t can1_intr_map;
+    volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map;
+    volatile interrupt_matrix_rmt_intr_map_reg_t rmt_intr_map;
+    volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map;
+    volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map;
+    volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map;
+    volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map;
+    volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map;
+    volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map;
+    volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map;
+    volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
+    volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
+    volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
+    volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map;
+    volatile interrupt_matrix_pwm_intr_map_reg_t pwm_intr_map;
+    volatile interrupt_matrix_pcnt_intr_map_reg_t pcnt_intr_map;
+    volatile interrupt_matrix_parl_io_intr_map_reg_t parl_io_intr_map;
+    volatile interrupt_matrix_slc0_intr_map_reg_t slc0_intr_map;
+    volatile interrupt_matrix_slc1_intr_map_reg_t slc1_intr_map;
+    volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map;
+    volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map;
+    volatile interrupt_matrix_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map;
+    volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map;
+    volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map;
+    volatile interrupt_matrix_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map;
+    volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map;
+    volatile interrupt_matrix_aes_intr_map_reg_t aes_intr_map;
+    volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map;
+    volatile interrupt_matrix_rsa_intr_map_reg_t rsa_intr_map;
+    volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map;
+    volatile interrupt_matrix_int_status_reg_0_reg_t int_status_reg_0;
+    volatile interrupt_matrix_int_status_reg_1_reg_t int_status_reg_1;
+    volatile interrupt_matrix_int_status_reg_2_reg_t int_status_reg_2;
+    volatile interrupt_matrix_clock_gate_reg_t clock_gate;
+    uint32_t reserved_144[430];
+    volatile interrupt_matrix_interrupt_reg_date_reg_t interrupt_reg_date;
+} interrupt_matrix_dev_t;
+
+extern interrupt_matrix_dev_t INTMTX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_reg.h b/components/soc/esp32p4/include/soc/interrupt_reg.h
new file mode 100644
index 0000000000..4290233051
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/interrupt_reg.h
@@ -0,0 +1,12 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/clic_reg.h"
+#include "soc/soc_caps.h"
+
+// ESP32P4 should use the CLIC controller as the interrupt controller instead of INTC (SOC_INT_CLIC_SUPPORTED = y)
+#define INTERRUPT_CORE0_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG
+#define INTERRUPT_CORE1_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG
diff --git a/components/soc/esp32p4/include/soc/intpri_reg.h b/components/soc/esp32p4/include/soc/intpri_reg.h
new file mode 100644
index 0000000000..25c3acccaa
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/intpri_reg.h
@@ -0,0 +1,574 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** INTPRI_CORE0_CPU_INT_ENABLE_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0)
+/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_INT_ENABLE    0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_ENABLE_M  (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S)
+#define INTPRI_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_ENABLE_S  0
+
+/** INTPRI_CORE0_CPU_INT_TYPE_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4)
+/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_INT_TYPE    0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_TYPE_M  (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S)
+#define INTPRI_CORE0_CPU_INT_TYPE_V  0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_TYPE_S  0
+
+/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8)
+/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_INT_EIP_STATUS    0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M  (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S)
+#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_0_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc)
+/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_0_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_0_MAP_M  (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_0_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_0_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_1_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10)
+/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_1_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_1_MAP_M  (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_1_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_1_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_2_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14)
+/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_2_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_2_MAP_M  (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_2_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_2_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_3_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18)
+/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_3_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_3_MAP_M  (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_3_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_3_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_4_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c)
+/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_4_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_4_MAP_M  (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_4_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_4_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_5_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20)
+/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_5_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_5_MAP_M  (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_5_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_5_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_6_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24)
+/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_6_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_6_MAP_M  (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_6_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_6_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_7_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28)
+/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_7_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_7_MAP_M  (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_7_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_7_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_8_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c)
+/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_8_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_8_MAP_M  (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_8_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_8_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_9_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30)
+/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_9_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_9_MAP_M  (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_9_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_9_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_10_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34)
+/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_10_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_10_MAP_M  (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_10_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_10_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_11_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38)
+/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_11_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_11_MAP_M  (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_11_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_11_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_12_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c)
+/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_12_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_12_MAP_M  (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_12_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_12_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_13_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40)
+/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_13_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_13_MAP_M  (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_13_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_13_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_14_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44)
+/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_14_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_14_MAP_M  (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_14_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_14_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_15_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48)
+/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_15_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_15_MAP_M  (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_15_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_15_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_16_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c)
+/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_16_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_16_MAP_M  (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_16_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_16_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_17_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50)
+/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_17_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_17_MAP_M  (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_17_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_17_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_18_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54)
+/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_18_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_18_MAP_M  (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_18_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_18_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_19_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58)
+/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_19_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_19_MAP_M  (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_19_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_19_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_20_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c)
+/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_20_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_20_MAP_M  (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_20_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_20_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_21_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60)
+/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_21_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_21_MAP_M  (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_21_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_21_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_22_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64)
+/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_22_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_22_MAP_M  (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_22_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_22_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_23_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68)
+/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_23_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_23_MAP_M  (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_23_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_23_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_24_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c)
+/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_24_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_24_MAP_M  (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_24_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_24_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_25_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70)
+/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_25_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_25_MAP_M  (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_25_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_25_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_26_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74)
+/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_26_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_26_MAP_M  (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_26_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_26_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_27_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78)
+/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_27_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_27_MAP_M  (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_27_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_27_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_28_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c)
+/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_28_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_28_MAP_M  (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_28_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_28_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_29_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80)
+/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_29_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_29_MAP_M  (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_29_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_29_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_30_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84)
+/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_30_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_30_MAP_M  (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_30_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_30_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_PRI_31_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88)
+/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_PRI_31_MAP    0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_31_MAP_M  (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S)
+#define INTPRI_CORE0_CPU_PRI_31_MAP_V  0x0000000FU
+#define INTPRI_CORE0_CPU_PRI_31_MAP_S  0
+
+/** INTPRI_CORE0_CPU_INT_THRESH_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c)
+/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_INT_THRESH    0x000000FFU
+#define INTPRI_CORE0_CPU_INT_THRESH_M  (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S)
+#define INTPRI_CORE0_CPU_INT_THRESH_V  0x000000FFU
+#define INTPRI_CORE0_CPU_INT_THRESH_S  0
+
+/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
+ *  register description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
+/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_0    (BIT(0))
+#define INTPRI_CPU_INTR_FROM_CPU_0_M  (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
+#define INTPRI_CPU_INTR_FROM_CPU_0_V  0x00000001U
+#define INTPRI_CPU_INTR_FROM_CPU_0_S  0
+
+/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
+ *  register description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
+/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_1    (BIT(0))
+#define INTPRI_CPU_INTR_FROM_CPU_1_M  (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
+#define INTPRI_CPU_INTR_FROM_CPU_1_V  0x00000001U
+#define INTPRI_CPU_INTR_FROM_CPU_1_S  0
+
+/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
+ *  register description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
+/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_2    (BIT(0))
+#define INTPRI_CPU_INTR_FROM_CPU_2_M  (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
+#define INTPRI_CPU_INTR_FROM_CPU_2_V  0x00000001U
+#define INTPRI_CPU_INTR_FROM_CPU_2_S  0
+
+/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
+ *  register description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
+/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CPU_INTR_FROM_CPU_3    (BIT(0))
+#define INTPRI_CPU_INTR_FROM_CPU_3_M  (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
+#define INTPRI_CPU_INTR_FROM_CPU_3_V  0x00000001U
+#define INTPRI_CPU_INTR_FROM_CPU_3_S  0
+
+/** INTPRI_DATE_REG register
+ *  register description
+ */
+#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
+/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35655824;
+ *  Need add description
+ */
+#define INTPRI_DATE    0x0FFFFFFFU
+#define INTPRI_DATE_M  (INTPRI_DATE_V << INTPRI_DATE_S)
+#define INTPRI_DATE_V  0x0FFFFFFFU
+#define INTPRI_DATE_S  0
+
+/** INTPRI_CLOCK_GATE_REG register
+ *  register description
+ */
+#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
+/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define INTPRI_CLK_EN    (BIT(0))
+#define INTPRI_CLK_EN_M  (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
+#define INTPRI_CLK_EN_V  0x00000001U
+#define INTPRI_CLK_EN_S  0
+
+/** INTPRI_CORE0_CPU_INT_CLEAR_REG register
+ *  register description
+ */
+#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8)
+/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTPRI_CORE0_CPU_INT_CLEAR    0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_CLEAR_M  (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S)
+#define INTPRI_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFFU
+#define INTPRI_CORE0_CPU_INT_CLEAR_S  0
+
+/** INTPRI_RND_ECO_REG register
+ *  redcy eco register.
+ */
+#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac)
+/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define INTPRI_REDCY_ENA    (BIT(0))
+#define INTPRI_REDCY_ENA_M  (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S)
+#define INTPRI_REDCY_ENA_V  0x00000001U
+#define INTPRI_REDCY_ENA_S  0
+/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define INTPRI_REDCY_RESULT    (BIT(1))
+#define INTPRI_REDCY_RESULT_M  (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S)
+#define INTPRI_REDCY_RESULT_V  0x00000001U
+#define INTPRI_REDCY_RESULT_S  1
+
+/** INTPRI_RND_ECO_LOW_REG register
+ *  redcy eco low register.
+ */
+#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0)
+/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define INTPRI_REDCY_LOW    0xFFFFFFFFU
+#define INTPRI_REDCY_LOW_M  (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S)
+#define INTPRI_REDCY_LOW_V  0xFFFFFFFFU
+#define INTPRI_REDCY_LOW_S  0
+
+/** INTPRI_RND_ECO_HIGH_REG register
+ *  redcy eco high register.
+ */
+#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc)
+/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
+ *  Only reserved for ECO.
+ */
+#define INTPRI_REDCY_HIGH    0xFFFFFFFFU
+#define INTPRI_REDCY_HIGH_M  (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S)
+#define INTPRI_REDCY_HIGH_V  0xFFFFFFFFU
+#define INTPRI_REDCY_HIGH_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/intpri_struct.h b/components/soc/esp32p4/include/soc/intpri_struct.h
new file mode 100644
index 0000000000..622f00818b
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/intpri_struct.h
@@ -0,0 +1,256 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of core0_cpu_int_enable register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core0_cpu_int_enable:32;
+    };
+    uint32_t val;
+} intpri_core0_cpu_int_enable_reg_t;
+
+/** Type of core0_cpu_int_type register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core0_cpu_int_type:32;
+    };
+    uint32_t val;
+} intpri_core0_cpu_int_type_reg_t;
+
+/** Type of core0_cpu_int_eip_status register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core0_cpu_int_eip_status:32;
+    };
+    uint32_t val;
+} intpri_core0_cpu_int_eip_status_reg_t;
+
+/** Type of core0_cpu_int_pri_n register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** map : R/W; bitpos: [3:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t map:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} intpri_core0_cpu_int_pri_n_reg_t;
+
+/** Type of core0_cpu_int_thresh register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core0_cpu_int_thresh:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} intpri_core0_cpu_int_thresh_reg_t;
+
+/** Type of clock_gate register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} intpri_clock_gate_reg_t;
+
+/** Type of core0_cpu_int_clear register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core0_cpu_int_clear:32;
+    };
+    uint32_t val;
+} intpri_core0_cpu_int_clear_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of cpu_intr_from_cpu_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} intpri_cpu_intr_from_cpu_0_reg_t;
+
+/** Type of cpu_intr_from_cpu_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} intpri_cpu_intr_from_cpu_1_reg_t;
+
+/** Type of cpu_intr_from_cpu_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} intpri_cpu_intr_from_cpu_2_reg_t;
+
+/** Type of cpu_intr_from_cpu_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_3:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} intpri_cpu_intr_from_cpu_3_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35655824;
+         *  Need add description
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} intpri_date_reg_t;
+
+
+/** Group: Redcy ECO Registers */
+/** Type of rnd_eco register
+ *  redcy eco register.
+ */
+typedef union {
+    struct {
+        /** redcy_ena : W/R; bitpos: [0]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_ena:1;
+        /** redcy_result : RO; bitpos: [1]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} intpri_rnd_eco_reg_t;
+
+/** Type of rnd_eco_low register
+ *  redcy eco low register.
+ */
+typedef union {
+    struct {
+        /** redcy_low : W/R; bitpos: [31:0]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_low:32;
+    };
+    uint32_t val;
+} intpri_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  redcy eco high register.
+ */
+typedef union {
+    struct {
+        /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_high:32;
+    };
+    uint32_t val;
+} intpri_rnd_eco_high_reg_t;
+
+
+typedef struct intpri_dev_t {
+    volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable;
+    volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type;
+    volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status;
+    volatile intpri_core0_cpu_int_pri_n_reg_t core0_cpu_int_pri[32];
+    volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh;
+    volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
+    volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
+    volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
+    volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
+    volatile intpri_date_reg_t date;
+    volatile intpri_clock_gate_reg_t clock_gate;
+    volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear;
+    volatile intpri_rnd_eco_reg_t rnd_eco;
+    volatile intpri_rnd_eco_low_reg_t rnd_eco_low;
+    uint32_t reserved_0b4[210];
+    volatile intpri_rnd_eco_high_reg_t rnd_eco_high;
+} intpri_dev_t;
+
+extern intpri_dev_t INTPRI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/io_mux_reg.h b/components/soc/esp32p4/include/soc/io_mux_reg.h
index 488097ee6d..475aa25bd1 100644
--- a/components/soc/esp32p4/include/soc/io_mux_reg.h
+++ b/components/soc/esp32p4/include/soc/io_mux_reg.h
@@ -64,6 +64,17 @@
 #define MCU_SEL_V 0x7
 #define MCU_SEL_S 12
 
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
 #define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
 #define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
 #define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
@@ -138,6 +149,55 @@
 #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
 #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
 
+#define SPI_CS1_GPIO_NUM 26
+#define SPI_HD_GPIO_NUM  27
+#define SPI_WP_GPIO_NUM  28
+#define SPI_CS0_GPIO_NUM 29
+#define SPI_CLK_GPIO_NUM 30
+#define SPI_Q_GPIO_NUM   31
+#define SPI_D_GPIO_NUM   32
+#define SPI_D4_GPIO_NUM  33
+#define SPI_D5_GPIO_NUM  34
+#define SPI_D6_GPIO_NUM  35
+#define SPI_D7_GPIO_NUM  36
+#define SPI_DQS_GPIO_NUM 37
+
+#define PIN_FUNC_SPI_DEBUG        4
+#define FLASH_CS_DEBUG_GPIO_NUM   49
+#define FLASH_Q_DEBUG_GPIO_NUM    50
+#define FLASH_WP_DEBUG_GPIO_NUM   51
+#define FLASH_HD_DEBUG_GPIO_NUM   52
+#define FLASH_CLK_DEBUG_GPIO_NUM  53
+#define FLASH_D_DEBUG_GPIO_NUM    54
+
+#define PSRAM_D_DEBUG_GPIO_NUM    28
+#define PSRAM_Q_DEBUG_GPIO_NUM    29
+#define PSRAM_WP_DEBUG_GPIO_NUM   30
+#define PSRAM_HOLD_DEBUG_GPIO_NUM 31
+#define PSRAM_DP4_DEBUG_GPIO_NUM  32
+#define PSRAM_DP5_DEBUG_GPIO_NUM  33
+#define PSRAM_DP6_DEBUG_GPIO_NUM  34
+#define PSRAM_DP7_DEBUG_GPIO_NUM  35
+#define PSRAM_DQS0_DEBUG_GPIO_NUM 36
+#define PSRAM_CLK_DEBUG_GPIO_NUM  22
+#define PSRAM_CS_DEBUG_GPIO_NUM   23
+#define PSRAM_DP8_DEBUG_GPIO_NUM  39
+#define PSRAM_DP9_DEBUG_GPIO_NUM  40
+#define PSRAM_DP10_DEBUG_GPIO_NUM 41
+#define PSRAM_DP11_DEBUG_GPIO_NUM 42
+#define PSRAM_DP12_DEBUG_GPIO_NUM 43
+#define PSRAM_DP13_DEBUG_GPIO_NUM 44
+#define PSRAM_DP14_DEBUG_GPIO_NUM 45
+#define PSRAM_DP15_DEBUG_GPIO_NUM 46
+#define PSRAM_DQS1_DEBUG_GPIO_NUM 47
+
+#define SD_CLK_GPIO_NUM 12
+#define SD_CMD_GPIO_NUM 11
+#define SD_DATA0_GPIO_NUM 13
+#define SD_DATA1_GPIO_NUM 14
+#define SD_DATA2_GPIO_NUM 9
+#define SD_DATA3_GPIO_NUM 10
+
 #define MAX_RTC_GPIO_NUM             15
 #define MAX_PAD_GPIO_NUM             56
 #define MAX_GPIO_NUM                 56
diff --git a/components/soc/esp32p4/include/soc/iomux_reg.h b/components/soc/esp32p4/include/soc/iomux_reg.h
new file mode 100644
index 0000000000..7e2b0b221e
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/iomux_reg.h
@@ -0,0 +1,5143 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** IO_MUX_gpio0_REG register
+ *  iomux control register for gpio0
+ */
+#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4)
+/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO0_MCU_OE_M  (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S)
+#define IO_MUX_GPIO0_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_OE_S  0
+/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO0_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO0_SLP_SEL_M  (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S)
+#define IO_MUX_GPIO0_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO0_SLP_SEL_S  1
+/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO0_MCU_WPD_M  (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S)
+#define IO_MUX_GPIO0_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_WPD_S  2
+/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO0_MCU_WPU_M  (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S)
+#define IO_MUX_GPIO0_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_WPU_S  3
+/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO0_MCU_IE_M  (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S)
+#define IO_MUX_GPIO0_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_IE_S  4
+/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO0_MCU_DRV_M  (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S)
+#define IO_MUX_GPIO0_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO0_MCU_DRV_S  5
+/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO0_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO0_FUN_WPD_M  (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S)
+#define IO_MUX_GPIO0_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO0_FUN_WPD_S  7
+/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO0_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO0_FUN_WPU_M  (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S)
+#define IO_MUX_GPIO0_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO0_FUN_WPU_S  8
+/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO0_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO0_FUN_IE_M  (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S)
+#define IO_MUX_GPIO0_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO0_FUN_IE_S  9
+/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO0_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO0_FUN_DRV_M  (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S)
+#define IO_MUX_GPIO0_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO0_FUN_DRV_S  10
+/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO0_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO0_MCU_SEL_M  (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S)
+#define IO_MUX_GPIO0_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO0_MCU_SEL_S  12
+/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO0_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO0_FILTER_EN_M  (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S)
+#define IO_MUX_GPIO0_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO0_FILTER_EN_S  15
+
+/** IO_MUX_gpio1_REG register
+ *  iomux control register for gpio1
+ */
+#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8)
+/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO1_MCU_OE_M  (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S)
+#define IO_MUX_GPIO1_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_OE_S  0
+/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO1_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO1_SLP_SEL_M  (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S)
+#define IO_MUX_GPIO1_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO1_SLP_SEL_S  1
+/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO1_MCU_WPD_M  (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S)
+#define IO_MUX_GPIO1_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_WPD_S  2
+/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO1_MCU_WPU_M  (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S)
+#define IO_MUX_GPIO1_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_WPU_S  3
+/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO1_MCU_IE_M  (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S)
+#define IO_MUX_GPIO1_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_IE_S  4
+/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO1_MCU_DRV_M  (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S)
+#define IO_MUX_GPIO1_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO1_MCU_DRV_S  5
+/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO1_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO1_FUN_WPD_M  (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S)
+#define IO_MUX_GPIO1_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO1_FUN_WPD_S  7
+/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO1_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO1_FUN_WPU_M  (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S)
+#define IO_MUX_GPIO1_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO1_FUN_WPU_S  8
+/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO1_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO1_FUN_IE_M  (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S)
+#define IO_MUX_GPIO1_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO1_FUN_IE_S  9
+/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO1_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO1_FUN_DRV_M  (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S)
+#define IO_MUX_GPIO1_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO1_FUN_DRV_S  10
+/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO1_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO1_MCU_SEL_M  (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S)
+#define IO_MUX_GPIO1_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO1_MCU_SEL_S  12
+/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO1_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO1_FILTER_EN_M  (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S)
+#define IO_MUX_GPIO1_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO1_FILTER_EN_S  15
+
+/** IO_MUX_gpio2_REG register
+ *  iomux control register for gpio2
+ */
+#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc)
+/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO2_MCU_OE_M  (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S)
+#define IO_MUX_GPIO2_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_OE_S  0
+/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO2_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO2_SLP_SEL_M  (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S)
+#define IO_MUX_GPIO2_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO2_SLP_SEL_S  1
+/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO2_MCU_WPD_M  (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S)
+#define IO_MUX_GPIO2_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_WPD_S  2
+/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO2_MCU_WPU_M  (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S)
+#define IO_MUX_GPIO2_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_WPU_S  3
+/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO2_MCU_IE_M  (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S)
+#define IO_MUX_GPIO2_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_IE_S  4
+/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO2_MCU_DRV_M  (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S)
+#define IO_MUX_GPIO2_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO2_MCU_DRV_S  5
+/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO2_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO2_FUN_WPD_M  (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S)
+#define IO_MUX_GPIO2_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO2_FUN_WPD_S  7
+/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO2_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO2_FUN_WPU_M  (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S)
+#define IO_MUX_GPIO2_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO2_FUN_WPU_S  8
+/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO2_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO2_FUN_IE_M  (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S)
+#define IO_MUX_GPIO2_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO2_FUN_IE_S  9
+/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO2_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO2_FUN_DRV_M  (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S)
+#define IO_MUX_GPIO2_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO2_FUN_DRV_S  10
+/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO2_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO2_MCU_SEL_M  (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S)
+#define IO_MUX_GPIO2_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO2_MCU_SEL_S  12
+/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO2_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO2_FILTER_EN_M  (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S)
+#define IO_MUX_GPIO2_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO2_FILTER_EN_S  15
+
+/** IO_MUX_gpio3_REG register
+ *  iomux control register for gpio3
+ */
+#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10)
+/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO3_MCU_OE_M  (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S)
+#define IO_MUX_GPIO3_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_OE_S  0
+/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO3_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO3_SLP_SEL_M  (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S)
+#define IO_MUX_GPIO3_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO3_SLP_SEL_S  1
+/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO3_MCU_WPD_M  (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S)
+#define IO_MUX_GPIO3_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_WPD_S  2
+/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO3_MCU_WPU_M  (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S)
+#define IO_MUX_GPIO3_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_WPU_S  3
+/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO3_MCU_IE_M  (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S)
+#define IO_MUX_GPIO3_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_IE_S  4
+/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO3_MCU_DRV_M  (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S)
+#define IO_MUX_GPIO3_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO3_MCU_DRV_S  5
+/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO3_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO3_FUN_WPD_M  (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S)
+#define IO_MUX_GPIO3_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO3_FUN_WPD_S  7
+/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO3_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO3_FUN_WPU_M  (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S)
+#define IO_MUX_GPIO3_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO3_FUN_WPU_S  8
+/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO3_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO3_FUN_IE_M  (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S)
+#define IO_MUX_GPIO3_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO3_FUN_IE_S  9
+/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO3_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO3_FUN_DRV_M  (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S)
+#define IO_MUX_GPIO3_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO3_FUN_DRV_S  10
+/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO3_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO3_MCU_SEL_M  (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S)
+#define IO_MUX_GPIO3_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO3_MCU_SEL_S  12
+/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO3_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO3_FILTER_EN_M  (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S)
+#define IO_MUX_GPIO3_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO3_FILTER_EN_S  15
+
+/** IO_MUX_gpio4_REG register
+ *  iomux control register for gpio4
+ */
+#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14)
+/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO4_MCU_OE_M  (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S)
+#define IO_MUX_GPIO4_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_OE_S  0
+/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO4_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO4_SLP_SEL_M  (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S)
+#define IO_MUX_GPIO4_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO4_SLP_SEL_S  1
+/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO4_MCU_WPD_M  (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S)
+#define IO_MUX_GPIO4_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_WPD_S  2
+/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO4_MCU_WPU_M  (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S)
+#define IO_MUX_GPIO4_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_WPU_S  3
+/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO4_MCU_IE_M  (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S)
+#define IO_MUX_GPIO4_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_IE_S  4
+/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO4_MCU_DRV_M  (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S)
+#define IO_MUX_GPIO4_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO4_MCU_DRV_S  5
+/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO4_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO4_FUN_WPD_M  (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S)
+#define IO_MUX_GPIO4_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO4_FUN_WPD_S  7
+/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO4_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO4_FUN_WPU_M  (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S)
+#define IO_MUX_GPIO4_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO4_FUN_WPU_S  8
+/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO4_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO4_FUN_IE_M  (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S)
+#define IO_MUX_GPIO4_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO4_FUN_IE_S  9
+/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO4_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO4_FUN_DRV_M  (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S)
+#define IO_MUX_GPIO4_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO4_FUN_DRV_S  10
+/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO4_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO4_MCU_SEL_M  (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S)
+#define IO_MUX_GPIO4_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO4_MCU_SEL_S  12
+/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO4_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO4_FILTER_EN_M  (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S)
+#define IO_MUX_GPIO4_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO4_FILTER_EN_S  15
+
+/** IO_MUX_gpio5_REG register
+ *  iomux control register for gpio5
+ */
+#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18)
+/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO5_MCU_OE_M  (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S)
+#define IO_MUX_GPIO5_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_OE_S  0
+/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO5_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO5_SLP_SEL_M  (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S)
+#define IO_MUX_GPIO5_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO5_SLP_SEL_S  1
+/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO5_MCU_WPD_M  (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S)
+#define IO_MUX_GPIO5_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_WPD_S  2
+/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO5_MCU_WPU_M  (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S)
+#define IO_MUX_GPIO5_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_WPU_S  3
+/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO5_MCU_IE_M  (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S)
+#define IO_MUX_GPIO5_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_IE_S  4
+/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO5_MCU_DRV_M  (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S)
+#define IO_MUX_GPIO5_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO5_MCU_DRV_S  5
+/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO5_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO5_FUN_WPD_M  (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S)
+#define IO_MUX_GPIO5_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO5_FUN_WPD_S  7
+/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO5_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO5_FUN_WPU_M  (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S)
+#define IO_MUX_GPIO5_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO5_FUN_WPU_S  8
+/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO5_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO5_FUN_IE_M  (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S)
+#define IO_MUX_GPIO5_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO5_FUN_IE_S  9
+/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO5_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO5_FUN_DRV_M  (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S)
+#define IO_MUX_GPIO5_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO5_FUN_DRV_S  10
+/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO5_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO5_MCU_SEL_M  (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S)
+#define IO_MUX_GPIO5_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO5_MCU_SEL_S  12
+/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO5_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO5_FILTER_EN_M  (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S)
+#define IO_MUX_GPIO5_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO5_FILTER_EN_S  15
+
+/** IO_MUX_gpio6_REG register
+ *  iomux control register for gpio6
+ */
+#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c)
+/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO6_MCU_OE_M  (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S)
+#define IO_MUX_GPIO6_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_OE_S  0
+/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO6_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO6_SLP_SEL_M  (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S)
+#define IO_MUX_GPIO6_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO6_SLP_SEL_S  1
+/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO6_MCU_WPD_M  (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S)
+#define IO_MUX_GPIO6_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_WPD_S  2
+/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO6_MCU_WPU_M  (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S)
+#define IO_MUX_GPIO6_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_WPU_S  3
+/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO6_MCU_IE_M  (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S)
+#define IO_MUX_GPIO6_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_IE_S  4
+/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO6_MCU_DRV_M  (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S)
+#define IO_MUX_GPIO6_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO6_MCU_DRV_S  5
+/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO6_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO6_FUN_WPD_M  (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S)
+#define IO_MUX_GPIO6_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO6_FUN_WPD_S  7
+/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO6_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO6_FUN_WPU_M  (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S)
+#define IO_MUX_GPIO6_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO6_FUN_WPU_S  8
+/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO6_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO6_FUN_IE_M  (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S)
+#define IO_MUX_GPIO6_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO6_FUN_IE_S  9
+/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO6_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO6_FUN_DRV_M  (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S)
+#define IO_MUX_GPIO6_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO6_FUN_DRV_S  10
+/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO6_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO6_MCU_SEL_M  (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S)
+#define IO_MUX_GPIO6_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO6_MCU_SEL_S  12
+/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO6_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO6_FILTER_EN_M  (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S)
+#define IO_MUX_GPIO6_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO6_FILTER_EN_S  15
+
+/** IO_MUX_gpio7_REG register
+ *  iomux control register for gpio7
+ */
+#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20)
+/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO7_MCU_OE_M  (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S)
+#define IO_MUX_GPIO7_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_OE_S  0
+/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO7_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO7_SLP_SEL_M  (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S)
+#define IO_MUX_GPIO7_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO7_SLP_SEL_S  1
+/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO7_MCU_WPD_M  (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S)
+#define IO_MUX_GPIO7_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_WPD_S  2
+/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO7_MCU_WPU_M  (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S)
+#define IO_MUX_GPIO7_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_WPU_S  3
+/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO7_MCU_IE_M  (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S)
+#define IO_MUX_GPIO7_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_IE_S  4
+/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO7_MCU_DRV_M  (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S)
+#define IO_MUX_GPIO7_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO7_MCU_DRV_S  5
+/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO7_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO7_FUN_WPD_M  (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S)
+#define IO_MUX_GPIO7_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO7_FUN_WPD_S  7
+/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO7_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO7_FUN_WPU_M  (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S)
+#define IO_MUX_GPIO7_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO7_FUN_WPU_S  8
+/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO7_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO7_FUN_IE_M  (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S)
+#define IO_MUX_GPIO7_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO7_FUN_IE_S  9
+/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO7_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO7_FUN_DRV_M  (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S)
+#define IO_MUX_GPIO7_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO7_FUN_DRV_S  10
+/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO7_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO7_MCU_SEL_M  (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S)
+#define IO_MUX_GPIO7_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO7_MCU_SEL_S  12
+/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO7_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO7_FILTER_EN_M  (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S)
+#define IO_MUX_GPIO7_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO7_FILTER_EN_S  15
+
+/** IO_MUX_gpio8_REG register
+ *  iomux control register for gpio8
+ */
+#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24)
+/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO8_MCU_OE_M  (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S)
+#define IO_MUX_GPIO8_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_OE_S  0
+/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO8_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO8_SLP_SEL_M  (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S)
+#define IO_MUX_GPIO8_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO8_SLP_SEL_S  1
+/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO8_MCU_WPD_M  (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S)
+#define IO_MUX_GPIO8_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_WPD_S  2
+/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO8_MCU_WPU_M  (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S)
+#define IO_MUX_GPIO8_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_WPU_S  3
+/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO8_MCU_IE_M  (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S)
+#define IO_MUX_GPIO8_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_IE_S  4
+/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO8_MCU_DRV_M  (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S)
+#define IO_MUX_GPIO8_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO8_MCU_DRV_S  5
+/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO8_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO8_FUN_WPD_M  (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S)
+#define IO_MUX_GPIO8_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO8_FUN_WPD_S  7
+/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO8_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO8_FUN_WPU_M  (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S)
+#define IO_MUX_GPIO8_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO8_FUN_WPU_S  8
+/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO8_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO8_FUN_IE_M  (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S)
+#define IO_MUX_GPIO8_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO8_FUN_IE_S  9
+/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO8_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO8_FUN_DRV_M  (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S)
+#define IO_MUX_GPIO8_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO8_FUN_DRV_S  10
+/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO8_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO8_MCU_SEL_M  (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S)
+#define IO_MUX_GPIO8_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO8_MCU_SEL_S  12
+/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO8_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO8_FILTER_EN_M  (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S)
+#define IO_MUX_GPIO8_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO8_FILTER_EN_S  15
+
+/** IO_MUX_gpio9_REG register
+ *  iomux control register for gpio9
+ */
+#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28)
+/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO9_MCU_OE_M  (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S)
+#define IO_MUX_GPIO9_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_OE_S  0
+/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO9_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO9_SLP_SEL_M  (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S)
+#define IO_MUX_GPIO9_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO9_SLP_SEL_S  1
+/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO9_MCU_WPD_M  (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S)
+#define IO_MUX_GPIO9_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_WPD_S  2
+/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO9_MCU_WPU_M  (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S)
+#define IO_MUX_GPIO9_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_WPU_S  3
+/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO9_MCU_IE_M  (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S)
+#define IO_MUX_GPIO9_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_IE_S  4
+/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO9_MCU_DRV_M  (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S)
+#define IO_MUX_GPIO9_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO9_MCU_DRV_S  5
+/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO9_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO9_FUN_WPD_M  (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S)
+#define IO_MUX_GPIO9_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO9_FUN_WPD_S  7
+/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO9_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO9_FUN_WPU_M  (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S)
+#define IO_MUX_GPIO9_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO9_FUN_WPU_S  8
+/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO9_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO9_FUN_IE_M  (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S)
+#define IO_MUX_GPIO9_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO9_FUN_IE_S  9
+/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO9_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO9_FUN_DRV_M  (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S)
+#define IO_MUX_GPIO9_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO9_FUN_DRV_S  10
+/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO9_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO9_MCU_SEL_M  (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S)
+#define IO_MUX_GPIO9_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO9_MCU_SEL_S  12
+/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO9_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO9_FILTER_EN_M  (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S)
+#define IO_MUX_GPIO9_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO9_FILTER_EN_S  15
+
+/** IO_MUX_gpio10_REG register
+ *  iomux control register for gpio10
+ */
+#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c)
+/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO10_MCU_OE_M  (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S)
+#define IO_MUX_GPIO10_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_OE_S  0
+/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO10_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO10_SLP_SEL_M  (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S)
+#define IO_MUX_GPIO10_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO10_SLP_SEL_S  1
+/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO10_MCU_WPD_M  (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S)
+#define IO_MUX_GPIO10_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_WPD_S  2
+/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO10_MCU_WPU_M  (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S)
+#define IO_MUX_GPIO10_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_WPU_S  3
+/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO10_MCU_IE_M  (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S)
+#define IO_MUX_GPIO10_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_IE_S  4
+/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO10_MCU_DRV_M  (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S)
+#define IO_MUX_GPIO10_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO10_MCU_DRV_S  5
+/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO10_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO10_FUN_WPD_M  (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S)
+#define IO_MUX_GPIO10_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO10_FUN_WPD_S  7
+/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO10_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO10_FUN_WPU_M  (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S)
+#define IO_MUX_GPIO10_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO10_FUN_WPU_S  8
+/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO10_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO10_FUN_IE_M  (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S)
+#define IO_MUX_GPIO10_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO10_FUN_IE_S  9
+/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO10_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO10_FUN_DRV_M  (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S)
+#define IO_MUX_GPIO10_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO10_FUN_DRV_S  10
+/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO10_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO10_MCU_SEL_M  (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S)
+#define IO_MUX_GPIO10_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO10_MCU_SEL_S  12
+/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO10_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO10_FILTER_EN_M  (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S)
+#define IO_MUX_GPIO10_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO10_FILTER_EN_S  15
+
+/** IO_MUX_gpio11_REG register
+ *  iomux control register for gpio11
+ */
+#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30)
+/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO11_MCU_OE_M  (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S)
+#define IO_MUX_GPIO11_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_OE_S  0
+/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO11_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO11_SLP_SEL_M  (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S)
+#define IO_MUX_GPIO11_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO11_SLP_SEL_S  1
+/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO11_MCU_WPD_M  (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S)
+#define IO_MUX_GPIO11_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_WPD_S  2
+/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO11_MCU_WPU_M  (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S)
+#define IO_MUX_GPIO11_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_WPU_S  3
+/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO11_MCU_IE_M  (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S)
+#define IO_MUX_GPIO11_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_IE_S  4
+/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO11_MCU_DRV_M  (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S)
+#define IO_MUX_GPIO11_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO11_MCU_DRV_S  5
+/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO11_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO11_FUN_WPD_M  (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S)
+#define IO_MUX_GPIO11_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO11_FUN_WPD_S  7
+/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO11_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO11_FUN_WPU_M  (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S)
+#define IO_MUX_GPIO11_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO11_FUN_WPU_S  8
+/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO11_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO11_FUN_IE_M  (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S)
+#define IO_MUX_GPIO11_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO11_FUN_IE_S  9
+/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO11_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO11_FUN_DRV_M  (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S)
+#define IO_MUX_GPIO11_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO11_FUN_DRV_S  10
+/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO11_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO11_MCU_SEL_M  (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S)
+#define IO_MUX_GPIO11_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO11_MCU_SEL_S  12
+/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO11_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO11_FILTER_EN_M  (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S)
+#define IO_MUX_GPIO11_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO11_FILTER_EN_S  15
+
+/** IO_MUX_gpio12_REG register
+ *  iomux control register for gpio12
+ */
+#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34)
+/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO12_MCU_OE_M  (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S)
+#define IO_MUX_GPIO12_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_OE_S  0
+/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO12_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO12_SLP_SEL_M  (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S)
+#define IO_MUX_GPIO12_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO12_SLP_SEL_S  1
+/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO12_MCU_WPD_M  (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S)
+#define IO_MUX_GPIO12_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_WPD_S  2
+/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO12_MCU_WPU_M  (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S)
+#define IO_MUX_GPIO12_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_WPU_S  3
+/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO12_MCU_IE_M  (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S)
+#define IO_MUX_GPIO12_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_IE_S  4
+/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO12_MCU_DRV_M  (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S)
+#define IO_MUX_GPIO12_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO12_MCU_DRV_S  5
+/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO12_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO12_FUN_WPD_M  (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S)
+#define IO_MUX_GPIO12_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO12_FUN_WPD_S  7
+/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO12_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO12_FUN_WPU_M  (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S)
+#define IO_MUX_GPIO12_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO12_FUN_WPU_S  8
+/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO12_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO12_FUN_IE_M  (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S)
+#define IO_MUX_GPIO12_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO12_FUN_IE_S  9
+/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO12_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO12_FUN_DRV_M  (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S)
+#define IO_MUX_GPIO12_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO12_FUN_DRV_S  10
+/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO12_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO12_MCU_SEL_M  (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S)
+#define IO_MUX_GPIO12_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO12_MCU_SEL_S  12
+/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO12_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO12_FILTER_EN_M  (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S)
+#define IO_MUX_GPIO12_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO12_FILTER_EN_S  15
+
+/** IO_MUX_gpio13_REG register
+ *  iomux control register for gpio13
+ */
+#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38)
+/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO13_MCU_OE_M  (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S)
+#define IO_MUX_GPIO13_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_OE_S  0
+/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO13_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO13_SLP_SEL_M  (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S)
+#define IO_MUX_GPIO13_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO13_SLP_SEL_S  1
+/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO13_MCU_WPD_M  (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S)
+#define IO_MUX_GPIO13_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_WPD_S  2
+/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO13_MCU_WPU_M  (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S)
+#define IO_MUX_GPIO13_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_WPU_S  3
+/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO13_MCU_IE_M  (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S)
+#define IO_MUX_GPIO13_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_IE_S  4
+/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO13_MCU_DRV_M  (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S)
+#define IO_MUX_GPIO13_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO13_MCU_DRV_S  5
+/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO13_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO13_FUN_WPD_M  (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S)
+#define IO_MUX_GPIO13_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO13_FUN_WPD_S  7
+/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO13_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO13_FUN_WPU_M  (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S)
+#define IO_MUX_GPIO13_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO13_FUN_WPU_S  8
+/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO13_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO13_FUN_IE_M  (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S)
+#define IO_MUX_GPIO13_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO13_FUN_IE_S  9
+/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO13_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO13_FUN_DRV_M  (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S)
+#define IO_MUX_GPIO13_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO13_FUN_DRV_S  10
+/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO13_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO13_MCU_SEL_M  (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S)
+#define IO_MUX_GPIO13_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO13_MCU_SEL_S  12
+/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO13_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO13_FILTER_EN_M  (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S)
+#define IO_MUX_GPIO13_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO13_FILTER_EN_S  15
+
+/** IO_MUX_gpio14_REG register
+ *  iomux control register for gpio14
+ */
+#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c)
+/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO14_MCU_OE_M  (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S)
+#define IO_MUX_GPIO14_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_OE_S  0
+/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO14_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO14_SLP_SEL_M  (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S)
+#define IO_MUX_GPIO14_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO14_SLP_SEL_S  1
+/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO14_MCU_WPD_M  (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S)
+#define IO_MUX_GPIO14_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_WPD_S  2
+/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO14_MCU_WPU_M  (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S)
+#define IO_MUX_GPIO14_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_WPU_S  3
+/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO14_MCU_IE_M  (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S)
+#define IO_MUX_GPIO14_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_IE_S  4
+/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO14_MCU_DRV_M  (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S)
+#define IO_MUX_GPIO14_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO14_MCU_DRV_S  5
+/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO14_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO14_FUN_WPD_M  (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S)
+#define IO_MUX_GPIO14_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO14_FUN_WPD_S  7
+/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO14_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO14_FUN_WPU_M  (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S)
+#define IO_MUX_GPIO14_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO14_FUN_WPU_S  8
+/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO14_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO14_FUN_IE_M  (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S)
+#define IO_MUX_GPIO14_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO14_FUN_IE_S  9
+/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO14_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO14_FUN_DRV_M  (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S)
+#define IO_MUX_GPIO14_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO14_FUN_DRV_S  10
+/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO14_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO14_MCU_SEL_M  (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S)
+#define IO_MUX_GPIO14_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO14_MCU_SEL_S  12
+/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO14_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO14_FILTER_EN_M  (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S)
+#define IO_MUX_GPIO14_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO14_FILTER_EN_S  15
+
+/** IO_MUX_gpio15_REG register
+ *  iomux control register for gpio15
+ */
+#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40)
+/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO15_MCU_OE_M  (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S)
+#define IO_MUX_GPIO15_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_OE_S  0
+/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO15_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO15_SLP_SEL_M  (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S)
+#define IO_MUX_GPIO15_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO15_SLP_SEL_S  1
+/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO15_MCU_WPD_M  (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S)
+#define IO_MUX_GPIO15_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_WPD_S  2
+/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO15_MCU_WPU_M  (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S)
+#define IO_MUX_GPIO15_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_WPU_S  3
+/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO15_MCU_IE_M  (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S)
+#define IO_MUX_GPIO15_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_IE_S  4
+/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO15_MCU_DRV_M  (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S)
+#define IO_MUX_GPIO15_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO15_MCU_DRV_S  5
+/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO15_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO15_FUN_WPD_M  (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S)
+#define IO_MUX_GPIO15_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO15_FUN_WPD_S  7
+/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO15_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO15_FUN_WPU_M  (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S)
+#define IO_MUX_GPIO15_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO15_FUN_WPU_S  8
+/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO15_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO15_FUN_IE_M  (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S)
+#define IO_MUX_GPIO15_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO15_FUN_IE_S  9
+/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO15_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO15_FUN_DRV_M  (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S)
+#define IO_MUX_GPIO15_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO15_FUN_DRV_S  10
+/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO15_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO15_MCU_SEL_M  (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S)
+#define IO_MUX_GPIO15_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO15_MCU_SEL_S  12
+/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO15_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO15_FILTER_EN_M  (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S)
+#define IO_MUX_GPIO15_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO15_FILTER_EN_S  15
+
+/** IO_MUX_gpio16_REG register
+ *  iomux control register for gpio16
+ */
+#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44)
+/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO16_MCU_OE_M  (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S)
+#define IO_MUX_GPIO16_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_OE_S  0
+/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO16_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO16_SLP_SEL_M  (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S)
+#define IO_MUX_GPIO16_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO16_SLP_SEL_S  1
+/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO16_MCU_WPD_M  (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S)
+#define IO_MUX_GPIO16_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_WPD_S  2
+/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO16_MCU_WPU_M  (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S)
+#define IO_MUX_GPIO16_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_WPU_S  3
+/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO16_MCU_IE_M  (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S)
+#define IO_MUX_GPIO16_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_IE_S  4
+/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO16_MCU_DRV_M  (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S)
+#define IO_MUX_GPIO16_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO16_MCU_DRV_S  5
+/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO16_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO16_FUN_WPD_M  (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S)
+#define IO_MUX_GPIO16_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO16_FUN_WPD_S  7
+/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO16_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO16_FUN_WPU_M  (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S)
+#define IO_MUX_GPIO16_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO16_FUN_WPU_S  8
+/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO16_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO16_FUN_IE_M  (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S)
+#define IO_MUX_GPIO16_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO16_FUN_IE_S  9
+/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO16_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO16_FUN_DRV_M  (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S)
+#define IO_MUX_GPIO16_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO16_FUN_DRV_S  10
+/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO16_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO16_MCU_SEL_M  (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S)
+#define IO_MUX_GPIO16_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO16_MCU_SEL_S  12
+/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO16_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO16_FILTER_EN_M  (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S)
+#define IO_MUX_GPIO16_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO16_FILTER_EN_S  15
+
+/** IO_MUX_gpio17_REG register
+ *  iomux control register for gpio17
+ */
+#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48)
+/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO17_MCU_OE_M  (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S)
+#define IO_MUX_GPIO17_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_OE_S  0
+/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO17_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO17_SLP_SEL_M  (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S)
+#define IO_MUX_GPIO17_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO17_SLP_SEL_S  1
+/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO17_MCU_WPD_M  (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S)
+#define IO_MUX_GPIO17_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_WPD_S  2
+/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO17_MCU_WPU_M  (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S)
+#define IO_MUX_GPIO17_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_WPU_S  3
+/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO17_MCU_IE_M  (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S)
+#define IO_MUX_GPIO17_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_IE_S  4
+/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO17_MCU_DRV_M  (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S)
+#define IO_MUX_GPIO17_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO17_MCU_DRV_S  5
+/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO17_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO17_FUN_WPD_M  (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S)
+#define IO_MUX_GPIO17_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO17_FUN_WPD_S  7
+/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO17_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO17_FUN_WPU_M  (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S)
+#define IO_MUX_GPIO17_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO17_FUN_WPU_S  8
+/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO17_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO17_FUN_IE_M  (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S)
+#define IO_MUX_GPIO17_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO17_FUN_IE_S  9
+/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO17_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO17_FUN_DRV_M  (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S)
+#define IO_MUX_GPIO17_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO17_FUN_DRV_S  10
+/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO17_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO17_MCU_SEL_M  (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S)
+#define IO_MUX_GPIO17_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO17_MCU_SEL_S  12
+/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO17_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO17_FILTER_EN_M  (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S)
+#define IO_MUX_GPIO17_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO17_FILTER_EN_S  15
+
+/** IO_MUX_gpio18_REG register
+ *  iomux control register for gpio18
+ */
+#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c)
+/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO18_MCU_OE_M  (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S)
+#define IO_MUX_GPIO18_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_OE_S  0
+/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO18_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO18_SLP_SEL_M  (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S)
+#define IO_MUX_GPIO18_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO18_SLP_SEL_S  1
+/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO18_MCU_WPD_M  (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S)
+#define IO_MUX_GPIO18_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_WPD_S  2
+/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO18_MCU_WPU_M  (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S)
+#define IO_MUX_GPIO18_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_WPU_S  3
+/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO18_MCU_IE_M  (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S)
+#define IO_MUX_GPIO18_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_IE_S  4
+/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO18_MCU_DRV_M  (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S)
+#define IO_MUX_GPIO18_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO18_MCU_DRV_S  5
+/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO18_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO18_FUN_WPD_M  (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S)
+#define IO_MUX_GPIO18_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO18_FUN_WPD_S  7
+/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO18_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO18_FUN_WPU_M  (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S)
+#define IO_MUX_GPIO18_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO18_FUN_WPU_S  8
+/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO18_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO18_FUN_IE_M  (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S)
+#define IO_MUX_GPIO18_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO18_FUN_IE_S  9
+/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO18_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO18_FUN_DRV_M  (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S)
+#define IO_MUX_GPIO18_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO18_FUN_DRV_S  10
+/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO18_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO18_MCU_SEL_M  (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S)
+#define IO_MUX_GPIO18_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO18_MCU_SEL_S  12
+/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO18_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO18_FILTER_EN_M  (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S)
+#define IO_MUX_GPIO18_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO18_FILTER_EN_S  15
+
+/** IO_MUX_gpio19_REG register
+ *  iomux control register for gpio19
+ */
+#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50)
+/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO19_MCU_OE_M  (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S)
+#define IO_MUX_GPIO19_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_OE_S  0
+/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO19_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO19_SLP_SEL_M  (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S)
+#define IO_MUX_GPIO19_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO19_SLP_SEL_S  1
+/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO19_MCU_WPD_M  (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S)
+#define IO_MUX_GPIO19_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_WPD_S  2
+/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO19_MCU_WPU_M  (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S)
+#define IO_MUX_GPIO19_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_WPU_S  3
+/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO19_MCU_IE_M  (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S)
+#define IO_MUX_GPIO19_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_IE_S  4
+/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO19_MCU_DRV_M  (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S)
+#define IO_MUX_GPIO19_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO19_MCU_DRV_S  5
+/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO19_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO19_FUN_WPD_M  (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S)
+#define IO_MUX_GPIO19_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO19_FUN_WPD_S  7
+/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO19_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO19_FUN_WPU_M  (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S)
+#define IO_MUX_GPIO19_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO19_FUN_WPU_S  8
+/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO19_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO19_FUN_IE_M  (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S)
+#define IO_MUX_GPIO19_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO19_FUN_IE_S  9
+/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO19_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO19_FUN_DRV_M  (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S)
+#define IO_MUX_GPIO19_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO19_FUN_DRV_S  10
+/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO19_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO19_MCU_SEL_M  (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S)
+#define IO_MUX_GPIO19_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO19_MCU_SEL_S  12
+/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO19_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO19_FILTER_EN_M  (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S)
+#define IO_MUX_GPIO19_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO19_FILTER_EN_S  15
+
+/** IO_MUX_gpio20_REG register
+ *  iomux control register for gpio20
+ */
+#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54)
+/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO20_MCU_OE_M  (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S)
+#define IO_MUX_GPIO20_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_OE_S  0
+/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO20_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO20_SLP_SEL_M  (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S)
+#define IO_MUX_GPIO20_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO20_SLP_SEL_S  1
+/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO20_MCU_WPD_M  (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S)
+#define IO_MUX_GPIO20_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_WPD_S  2
+/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO20_MCU_WPU_M  (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S)
+#define IO_MUX_GPIO20_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_WPU_S  3
+/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO20_MCU_IE_M  (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S)
+#define IO_MUX_GPIO20_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_IE_S  4
+/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO20_MCU_DRV_M  (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S)
+#define IO_MUX_GPIO20_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO20_MCU_DRV_S  5
+/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO20_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO20_FUN_WPD_M  (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S)
+#define IO_MUX_GPIO20_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO20_FUN_WPD_S  7
+/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO20_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO20_FUN_WPU_M  (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S)
+#define IO_MUX_GPIO20_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO20_FUN_WPU_S  8
+/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO20_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO20_FUN_IE_M  (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S)
+#define IO_MUX_GPIO20_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO20_FUN_IE_S  9
+/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO20_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO20_FUN_DRV_M  (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S)
+#define IO_MUX_GPIO20_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO20_FUN_DRV_S  10
+/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO20_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO20_MCU_SEL_M  (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S)
+#define IO_MUX_GPIO20_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO20_MCU_SEL_S  12
+/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO20_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO20_FILTER_EN_M  (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S)
+#define IO_MUX_GPIO20_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO20_FILTER_EN_S  15
+
+/** IO_MUX_gpio21_REG register
+ *  iomux control register for gpio21
+ */
+#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58)
+/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO21_MCU_OE_M  (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S)
+#define IO_MUX_GPIO21_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_OE_S  0
+/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO21_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO21_SLP_SEL_M  (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S)
+#define IO_MUX_GPIO21_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO21_SLP_SEL_S  1
+/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO21_MCU_WPD_M  (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S)
+#define IO_MUX_GPIO21_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_WPD_S  2
+/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO21_MCU_WPU_M  (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S)
+#define IO_MUX_GPIO21_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_WPU_S  3
+/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO21_MCU_IE_M  (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S)
+#define IO_MUX_GPIO21_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_IE_S  4
+/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO21_MCU_DRV_M  (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S)
+#define IO_MUX_GPIO21_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO21_MCU_DRV_S  5
+/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO21_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO21_FUN_WPD_M  (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S)
+#define IO_MUX_GPIO21_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO21_FUN_WPD_S  7
+/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO21_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO21_FUN_WPU_M  (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S)
+#define IO_MUX_GPIO21_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO21_FUN_WPU_S  8
+/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO21_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO21_FUN_IE_M  (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S)
+#define IO_MUX_GPIO21_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO21_FUN_IE_S  9
+/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO21_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO21_FUN_DRV_M  (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S)
+#define IO_MUX_GPIO21_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO21_FUN_DRV_S  10
+/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO21_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO21_MCU_SEL_M  (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S)
+#define IO_MUX_GPIO21_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO21_MCU_SEL_S  12
+/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO21_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO21_FILTER_EN_M  (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S)
+#define IO_MUX_GPIO21_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO21_FILTER_EN_S  15
+
+/** IO_MUX_gpio22_REG register
+ *  iomux control register for gpio22
+ */
+#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c)
+/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO22_MCU_OE_M  (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S)
+#define IO_MUX_GPIO22_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_OE_S  0
+/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO22_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO22_SLP_SEL_M  (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S)
+#define IO_MUX_GPIO22_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO22_SLP_SEL_S  1
+/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO22_MCU_WPD_M  (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S)
+#define IO_MUX_GPIO22_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_WPD_S  2
+/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO22_MCU_WPU_M  (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S)
+#define IO_MUX_GPIO22_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_WPU_S  3
+/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO22_MCU_IE_M  (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S)
+#define IO_MUX_GPIO22_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_IE_S  4
+/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO22_MCU_DRV_M  (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S)
+#define IO_MUX_GPIO22_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO22_MCU_DRV_S  5
+/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO22_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO22_FUN_WPD_M  (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S)
+#define IO_MUX_GPIO22_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO22_FUN_WPD_S  7
+/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO22_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO22_FUN_WPU_M  (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S)
+#define IO_MUX_GPIO22_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO22_FUN_WPU_S  8
+/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO22_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO22_FUN_IE_M  (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S)
+#define IO_MUX_GPIO22_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO22_FUN_IE_S  9
+/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO22_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO22_FUN_DRV_M  (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S)
+#define IO_MUX_GPIO22_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO22_FUN_DRV_S  10
+/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO22_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO22_MCU_SEL_M  (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S)
+#define IO_MUX_GPIO22_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO22_MCU_SEL_S  12
+/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO22_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO22_FILTER_EN_M  (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S)
+#define IO_MUX_GPIO22_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO22_FILTER_EN_S  15
+
+/** IO_MUX_gpio23_REG register
+ *  iomux control register for gpio23
+ */
+#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60)
+/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO23_MCU_OE_M  (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S)
+#define IO_MUX_GPIO23_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_OE_S  0
+/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO23_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO23_SLP_SEL_M  (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S)
+#define IO_MUX_GPIO23_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO23_SLP_SEL_S  1
+/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO23_MCU_WPD_M  (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S)
+#define IO_MUX_GPIO23_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_WPD_S  2
+/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO23_MCU_WPU_M  (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S)
+#define IO_MUX_GPIO23_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_WPU_S  3
+/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO23_MCU_IE_M  (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S)
+#define IO_MUX_GPIO23_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_IE_S  4
+/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO23_MCU_DRV_M  (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S)
+#define IO_MUX_GPIO23_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO23_MCU_DRV_S  5
+/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO23_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO23_FUN_WPD_M  (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S)
+#define IO_MUX_GPIO23_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO23_FUN_WPD_S  7
+/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO23_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO23_FUN_WPU_M  (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S)
+#define IO_MUX_GPIO23_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO23_FUN_WPU_S  8
+/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO23_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO23_FUN_IE_M  (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S)
+#define IO_MUX_GPIO23_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO23_FUN_IE_S  9
+/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO23_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO23_FUN_DRV_M  (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S)
+#define IO_MUX_GPIO23_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO23_FUN_DRV_S  10
+/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO23_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO23_MCU_SEL_M  (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S)
+#define IO_MUX_GPIO23_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO23_MCU_SEL_S  12
+/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO23_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO23_FILTER_EN_M  (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S)
+#define IO_MUX_GPIO23_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO23_FILTER_EN_S  15
+
+/** IO_MUX_gpio24_REG register
+ *  iomux control register for gpio24
+ */
+#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64)
+/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO24_MCU_OE_M  (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S)
+#define IO_MUX_GPIO24_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_OE_S  0
+/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO24_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO24_SLP_SEL_M  (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S)
+#define IO_MUX_GPIO24_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO24_SLP_SEL_S  1
+/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO24_MCU_WPD_M  (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S)
+#define IO_MUX_GPIO24_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_WPD_S  2
+/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO24_MCU_WPU_M  (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S)
+#define IO_MUX_GPIO24_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_WPU_S  3
+/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO24_MCU_IE_M  (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S)
+#define IO_MUX_GPIO24_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_IE_S  4
+/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO24_MCU_DRV_M  (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S)
+#define IO_MUX_GPIO24_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO24_MCU_DRV_S  5
+/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO24_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO24_FUN_WPD_M  (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S)
+#define IO_MUX_GPIO24_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO24_FUN_WPD_S  7
+/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO24_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO24_FUN_WPU_M  (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S)
+#define IO_MUX_GPIO24_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO24_FUN_WPU_S  8
+/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO24_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO24_FUN_IE_M  (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S)
+#define IO_MUX_GPIO24_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO24_FUN_IE_S  9
+/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO24_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO24_FUN_DRV_M  (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S)
+#define IO_MUX_GPIO24_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO24_FUN_DRV_S  10
+/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO24_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO24_MCU_SEL_M  (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S)
+#define IO_MUX_GPIO24_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO24_MCU_SEL_S  12
+/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO24_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO24_FILTER_EN_M  (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S)
+#define IO_MUX_GPIO24_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO24_FILTER_EN_S  15
+
+/** IO_MUX_gpio25_REG register
+ *  iomux control register for gpio25
+ */
+#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68)
+/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO25_MCU_OE_M  (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S)
+#define IO_MUX_GPIO25_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_OE_S  0
+/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO25_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO25_SLP_SEL_M  (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S)
+#define IO_MUX_GPIO25_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO25_SLP_SEL_S  1
+/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO25_MCU_WPD_M  (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S)
+#define IO_MUX_GPIO25_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_WPD_S  2
+/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO25_MCU_WPU_M  (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S)
+#define IO_MUX_GPIO25_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_WPU_S  3
+/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO25_MCU_IE_M  (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S)
+#define IO_MUX_GPIO25_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_IE_S  4
+/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO25_MCU_DRV_M  (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S)
+#define IO_MUX_GPIO25_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO25_MCU_DRV_S  5
+/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO25_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO25_FUN_WPD_M  (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S)
+#define IO_MUX_GPIO25_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO25_FUN_WPD_S  7
+/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO25_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO25_FUN_WPU_M  (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S)
+#define IO_MUX_GPIO25_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO25_FUN_WPU_S  8
+/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO25_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO25_FUN_IE_M  (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S)
+#define IO_MUX_GPIO25_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO25_FUN_IE_S  9
+/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO25_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO25_FUN_DRV_M  (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S)
+#define IO_MUX_GPIO25_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO25_FUN_DRV_S  10
+/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO25_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO25_MCU_SEL_M  (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S)
+#define IO_MUX_GPIO25_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO25_MCU_SEL_S  12
+/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO25_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO25_FILTER_EN_M  (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S)
+#define IO_MUX_GPIO25_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO25_FILTER_EN_S  15
+
+/** IO_MUX_gpio26_REG register
+ *  iomux control register for gpio26
+ */
+#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c)
+/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO26_MCU_OE_M  (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S)
+#define IO_MUX_GPIO26_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_OE_S  0
+/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO26_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO26_SLP_SEL_M  (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S)
+#define IO_MUX_GPIO26_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO26_SLP_SEL_S  1
+/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO26_MCU_WPD_M  (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S)
+#define IO_MUX_GPIO26_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_WPD_S  2
+/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO26_MCU_WPU_M  (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S)
+#define IO_MUX_GPIO26_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_WPU_S  3
+/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO26_MCU_IE_M  (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S)
+#define IO_MUX_GPIO26_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_IE_S  4
+/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO26_MCU_DRV_M  (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S)
+#define IO_MUX_GPIO26_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO26_MCU_DRV_S  5
+/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO26_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO26_FUN_WPD_M  (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S)
+#define IO_MUX_GPIO26_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO26_FUN_WPD_S  7
+/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO26_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO26_FUN_WPU_M  (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S)
+#define IO_MUX_GPIO26_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO26_FUN_WPU_S  8
+/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO26_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO26_FUN_IE_M  (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S)
+#define IO_MUX_GPIO26_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO26_FUN_IE_S  9
+/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO26_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO26_FUN_DRV_M  (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S)
+#define IO_MUX_GPIO26_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO26_FUN_DRV_S  10
+/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO26_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO26_MCU_SEL_M  (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S)
+#define IO_MUX_GPIO26_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO26_MCU_SEL_S  12
+/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO26_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO26_FILTER_EN_M  (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S)
+#define IO_MUX_GPIO26_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO26_FILTER_EN_S  15
+
+/** IO_MUX_gpio27_REG register
+ *  iomux control register for gpio27
+ */
+#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70)
+/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO27_MCU_OE_M  (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S)
+#define IO_MUX_GPIO27_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_OE_S  0
+/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO27_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO27_SLP_SEL_M  (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S)
+#define IO_MUX_GPIO27_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO27_SLP_SEL_S  1
+/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO27_MCU_WPD_M  (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S)
+#define IO_MUX_GPIO27_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_WPD_S  2
+/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO27_MCU_WPU_M  (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S)
+#define IO_MUX_GPIO27_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_WPU_S  3
+/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO27_MCU_IE_M  (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S)
+#define IO_MUX_GPIO27_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_IE_S  4
+/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO27_MCU_DRV_M  (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S)
+#define IO_MUX_GPIO27_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO27_MCU_DRV_S  5
+/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO27_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO27_FUN_WPD_M  (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S)
+#define IO_MUX_GPIO27_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO27_FUN_WPD_S  7
+/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO27_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO27_FUN_WPU_M  (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S)
+#define IO_MUX_GPIO27_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO27_FUN_WPU_S  8
+/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO27_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO27_FUN_IE_M  (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S)
+#define IO_MUX_GPIO27_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO27_FUN_IE_S  9
+/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO27_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO27_FUN_DRV_M  (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S)
+#define IO_MUX_GPIO27_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO27_FUN_DRV_S  10
+/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO27_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO27_MCU_SEL_M  (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S)
+#define IO_MUX_GPIO27_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO27_MCU_SEL_S  12
+/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO27_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO27_FILTER_EN_M  (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S)
+#define IO_MUX_GPIO27_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO27_FILTER_EN_S  15
+
+/** IO_MUX_gpio28_REG register
+ *  iomux control register for gpio28
+ */
+#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74)
+/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO28_MCU_OE_M  (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S)
+#define IO_MUX_GPIO28_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_OE_S  0
+/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO28_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO28_SLP_SEL_M  (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S)
+#define IO_MUX_GPIO28_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO28_SLP_SEL_S  1
+/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO28_MCU_WPD_M  (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S)
+#define IO_MUX_GPIO28_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_WPD_S  2
+/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO28_MCU_WPU_M  (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S)
+#define IO_MUX_GPIO28_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_WPU_S  3
+/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO28_MCU_IE_M  (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S)
+#define IO_MUX_GPIO28_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_IE_S  4
+/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO28_MCU_DRV_M  (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S)
+#define IO_MUX_GPIO28_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO28_MCU_DRV_S  5
+/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO28_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO28_FUN_WPD_M  (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S)
+#define IO_MUX_GPIO28_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO28_FUN_WPD_S  7
+/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO28_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO28_FUN_WPU_M  (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S)
+#define IO_MUX_GPIO28_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO28_FUN_WPU_S  8
+/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO28_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO28_FUN_IE_M  (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S)
+#define IO_MUX_GPIO28_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO28_FUN_IE_S  9
+/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO28_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO28_FUN_DRV_M  (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S)
+#define IO_MUX_GPIO28_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO28_FUN_DRV_S  10
+/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO28_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO28_MCU_SEL_M  (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S)
+#define IO_MUX_GPIO28_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO28_MCU_SEL_S  12
+/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO28_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO28_FILTER_EN_M  (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S)
+#define IO_MUX_GPIO28_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO28_FILTER_EN_S  15
+
+/** IO_MUX_gpio29_REG register
+ *  iomux control register for gpio29
+ */
+#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78)
+/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO29_MCU_OE_M  (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S)
+#define IO_MUX_GPIO29_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_OE_S  0
+/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO29_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO29_SLP_SEL_M  (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S)
+#define IO_MUX_GPIO29_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO29_SLP_SEL_S  1
+/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO29_MCU_WPD_M  (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S)
+#define IO_MUX_GPIO29_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_WPD_S  2
+/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO29_MCU_WPU_M  (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S)
+#define IO_MUX_GPIO29_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_WPU_S  3
+/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO29_MCU_IE_M  (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S)
+#define IO_MUX_GPIO29_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_IE_S  4
+/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO29_MCU_DRV_M  (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S)
+#define IO_MUX_GPIO29_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO29_MCU_DRV_S  5
+/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO29_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO29_FUN_WPD_M  (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S)
+#define IO_MUX_GPIO29_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO29_FUN_WPD_S  7
+/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO29_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO29_FUN_WPU_M  (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S)
+#define IO_MUX_GPIO29_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO29_FUN_WPU_S  8
+/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO29_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO29_FUN_IE_M  (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S)
+#define IO_MUX_GPIO29_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO29_FUN_IE_S  9
+/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO29_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO29_FUN_DRV_M  (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S)
+#define IO_MUX_GPIO29_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO29_FUN_DRV_S  10
+/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO29_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO29_MCU_SEL_M  (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S)
+#define IO_MUX_GPIO29_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO29_MCU_SEL_S  12
+/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO29_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO29_FILTER_EN_M  (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S)
+#define IO_MUX_GPIO29_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO29_FILTER_EN_S  15
+
+/** IO_MUX_gpio30_REG register
+ *  iomux control register for gpio30
+ */
+#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c)
+/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO30_MCU_OE_M  (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S)
+#define IO_MUX_GPIO30_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_OE_S  0
+/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO30_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO30_SLP_SEL_M  (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S)
+#define IO_MUX_GPIO30_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO30_SLP_SEL_S  1
+/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO30_MCU_WPD_M  (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S)
+#define IO_MUX_GPIO30_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_WPD_S  2
+/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO30_MCU_WPU_M  (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S)
+#define IO_MUX_GPIO30_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_WPU_S  3
+/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO30_MCU_IE_M  (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S)
+#define IO_MUX_GPIO30_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_IE_S  4
+/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO30_MCU_DRV_M  (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S)
+#define IO_MUX_GPIO30_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO30_MCU_DRV_S  5
+/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO30_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO30_FUN_WPD_M  (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S)
+#define IO_MUX_GPIO30_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO30_FUN_WPD_S  7
+/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO30_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO30_FUN_WPU_M  (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S)
+#define IO_MUX_GPIO30_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO30_FUN_WPU_S  8
+/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO30_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO30_FUN_IE_M  (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S)
+#define IO_MUX_GPIO30_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO30_FUN_IE_S  9
+/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO30_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO30_FUN_DRV_M  (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S)
+#define IO_MUX_GPIO30_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO30_FUN_DRV_S  10
+/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO30_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO30_MCU_SEL_M  (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S)
+#define IO_MUX_GPIO30_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO30_MCU_SEL_S  12
+/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO30_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO30_FILTER_EN_M  (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S)
+#define IO_MUX_GPIO30_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO30_FILTER_EN_S  15
+
+/** IO_MUX_gpio31_REG register
+ *  iomux control register for gpio31
+ */
+#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80)
+/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO31_MCU_OE_M  (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S)
+#define IO_MUX_GPIO31_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_OE_S  0
+/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO31_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO31_SLP_SEL_M  (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S)
+#define IO_MUX_GPIO31_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO31_SLP_SEL_S  1
+/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO31_MCU_WPD_M  (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S)
+#define IO_MUX_GPIO31_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_WPD_S  2
+/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO31_MCU_WPU_M  (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S)
+#define IO_MUX_GPIO31_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_WPU_S  3
+/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO31_MCU_IE_M  (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S)
+#define IO_MUX_GPIO31_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_IE_S  4
+/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO31_MCU_DRV_M  (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S)
+#define IO_MUX_GPIO31_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO31_MCU_DRV_S  5
+/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO31_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO31_FUN_WPD_M  (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S)
+#define IO_MUX_GPIO31_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO31_FUN_WPD_S  7
+/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO31_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO31_FUN_WPU_M  (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S)
+#define IO_MUX_GPIO31_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO31_FUN_WPU_S  8
+/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO31_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO31_FUN_IE_M  (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S)
+#define IO_MUX_GPIO31_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO31_FUN_IE_S  9
+/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO31_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO31_FUN_DRV_M  (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S)
+#define IO_MUX_GPIO31_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO31_FUN_DRV_S  10
+/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO31_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO31_MCU_SEL_M  (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S)
+#define IO_MUX_GPIO31_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO31_MCU_SEL_S  12
+/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO31_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO31_FILTER_EN_M  (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S)
+#define IO_MUX_GPIO31_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO31_FILTER_EN_S  15
+
+/** IO_MUX_gpio32_REG register
+ *  iomux control register for gpio32
+ */
+#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84)
+/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO32_MCU_OE_M  (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S)
+#define IO_MUX_GPIO32_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_OE_S  0
+/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO32_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO32_SLP_SEL_M  (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S)
+#define IO_MUX_GPIO32_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO32_SLP_SEL_S  1
+/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO32_MCU_WPD_M  (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S)
+#define IO_MUX_GPIO32_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_WPD_S  2
+/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO32_MCU_WPU_M  (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S)
+#define IO_MUX_GPIO32_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_WPU_S  3
+/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO32_MCU_IE_M  (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S)
+#define IO_MUX_GPIO32_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_IE_S  4
+/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO32_MCU_DRV_M  (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S)
+#define IO_MUX_GPIO32_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO32_MCU_DRV_S  5
+/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO32_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO32_FUN_WPD_M  (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S)
+#define IO_MUX_GPIO32_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO32_FUN_WPD_S  7
+/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO32_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO32_FUN_WPU_M  (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S)
+#define IO_MUX_GPIO32_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO32_FUN_WPU_S  8
+/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO32_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO32_FUN_IE_M  (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S)
+#define IO_MUX_GPIO32_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO32_FUN_IE_S  9
+/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO32_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO32_FUN_DRV_M  (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S)
+#define IO_MUX_GPIO32_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO32_FUN_DRV_S  10
+/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO32_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO32_MCU_SEL_M  (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S)
+#define IO_MUX_GPIO32_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO32_MCU_SEL_S  12
+/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO32_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO32_FILTER_EN_M  (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S)
+#define IO_MUX_GPIO32_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO32_FILTER_EN_S  15
+/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO32_RUE_I3C    (BIT(16))
+#define IO_MUX_GPIO32_RUE_I3C_M  (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S)
+#define IO_MUX_GPIO32_RUE_I3C_V  0x00000001U
+#define IO_MUX_GPIO32_RUE_I3C_S  16
+/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO32_RU_I3C    0x00000003U
+#define IO_MUX_GPIO32_RU_I3C_M  (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S)
+#define IO_MUX_GPIO32_RU_I3C_V  0x00000003U
+#define IO_MUX_GPIO32_RU_I3C_S  17
+/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO32_RUE_SEL_I3C    (BIT(19))
+#define IO_MUX_GPIO32_RUE_SEL_I3C_M  (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S)
+#define IO_MUX_GPIO32_RUE_SEL_I3C_V  0x00000001U
+#define IO_MUX_GPIO32_RUE_SEL_I3C_S  19
+
+/** IO_MUX_gpio33_REG register
+ *  iomux control register for gpio33
+ */
+#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88)
+/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO33_MCU_OE_M  (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S)
+#define IO_MUX_GPIO33_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_OE_S  0
+/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO33_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO33_SLP_SEL_M  (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S)
+#define IO_MUX_GPIO33_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO33_SLP_SEL_S  1
+/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO33_MCU_WPD_M  (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S)
+#define IO_MUX_GPIO33_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_WPD_S  2
+/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO33_MCU_WPU_M  (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S)
+#define IO_MUX_GPIO33_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_WPU_S  3
+/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO33_MCU_IE_M  (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S)
+#define IO_MUX_GPIO33_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_IE_S  4
+/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO33_MCU_DRV_M  (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S)
+#define IO_MUX_GPIO33_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO33_MCU_DRV_S  5
+/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO33_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO33_FUN_WPD_M  (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S)
+#define IO_MUX_GPIO33_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO33_FUN_WPD_S  7
+/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO33_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO33_FUN_WPU_M  (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S)
+#define IO_MUX_GPIO33_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO33_FUN_WPU_S  8
+/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO33_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO33_FUN_IE_M  (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S)
+#define IO_MUX_GPIO33_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO33_FUN_IE_S  9
+/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO33_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO33_FUN_DRV_M  (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S)
+#define IO_MUX_GPIO33_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO33_FUN_DRV_S  10
+/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO33_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO33_MCU_SEL_M  (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S)
+#define IO_MUX_GPIO33_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO33_MCU_SEL_S  12
+/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO33_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO33_FILTER_EN_M  (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S)
+#define IO_MUX_GPIO33_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO33_FILTER_EN_S  15
+/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO33_RUE_I3C    (BIT(16))
+#define IO_MUX_GPIO33_RUE_I3C_M  (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S)
+#define IO_MUX_GPIO33_RUE_I3C_V  0x00000001U
+#define IO_MUX_GPIO33_RUE_I3C_S  16
+/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO33_RU_I3C    0x00000003U
+#define IO_MUX_GPIO33_RU_I3C_M  (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S)
+#define IO_MUX_GPIO33_RU_I3C_V  0x00000003U
+#define IO_MUX_GPIO33_RU_I3C_S  17
+/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO33_RUE_SEL_I3C    (BIT(19))
+#define IO_MUX_GPIO33_RUE_SEL_I3C_M  (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S)
+#define IO_MUX_GPIO33_RUE_SEL_I3C_V  0x00000001U
+#define IO_MUX_GPIO33_RUE_SEL_I3C_S  19
+
+/** IO_MUX_gpio34_REG register
+ *  iomux control register for gpio34
+ */
+#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c)
+/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO34_MCU_OE_M  (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S)
+#define IO_MUX_GPIO34_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_OE_S  0
+/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO34_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO34_SLP_SEL_M  (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S)
+#define IO_MUX_GPIO34_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO34_SLP_SEL_S  1
+/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO34_MCU_WPD_M  (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S)
+#define IO_MUX_GPIO34_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_WPD_S  2
+/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO34_MCU_WPU_M  (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S)
+#define IO_MUX_GPIO34_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_WPU_S  3
+/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO34_MCU_IE_M  (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S)
+#define IO_MUX_GPIO34_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_IE_S  4
+/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO34_MCU_DRV_M  (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S)
+#define IO_MUX_GPIO34_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO34_MCU_DRV_S  5
+/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO34_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO34_FUN_WPD_M  (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S)
+#define IO_MUX_GPIO34_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO34_FUN_WPD_S  7
+/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO34_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO34_FUN_WPU_M  (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S)
+#define IO_MUX_GPIO34_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO34_FUN_WPU_S  8
+/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO34_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO34_FUN_IE_M  (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S)
+#define IO_MUX_GPIO34_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO34_FUN_IE_S  9
+/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO34_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO34_FUN_DRV_M  (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S)
+#define IO_MUX_GPIO34_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO34_FUN_DRV_S  10
+/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO34_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO34_MCU_SEL_M  (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S)
+#define IO_MUX_GPIO34_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO34_MCU_SEL_S  12
+/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO34_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO34_FILTER_EN_M  (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S)
+#define IO_MUX_GPIO34_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO34_FILTER_EN_S  15
+
+/** IO_MUX_gpio35_REG register
+ *  iomux control register for gpio35
+ */
+#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90)
+/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO35_MCU_OE_M  (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S)
+#define IO_MUX_GPIO35_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_OE_S  0
+/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO35_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO35_SLP_SEL_M  (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S)
+#define IO_MUX_GPIO35_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO35_SLP_SEL_S  1
+/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO35_MCU_WPD_M  (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S)
+#define IO_MUX_GPIO35_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_WPD_S  2
+/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO35_MCU_WPU_M  (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S)
+#define IO_MUX_GPIO35_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_WPU_S  3
+/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO35_MCU_IE_M  (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S)
+#define IO_MUX_GPIO35_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_IE_S  4
+/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO35_MCU_DRV_M  (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S)
+#define IO_MUX_GPIO35_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO35_MCU_DRV_S  5
+/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO35_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO35_FUN_WPD_M  (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S)
+#define IO_MUX_GPIO35_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO35_FUN_WPD_S  7
+/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO35_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO35_FUN_WPU_M  (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S)
+#define IO_MUX_GPIO35_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO35_FUN_WPU_S  8
+/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO35_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO35_FUN_IE_M  (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S)
+#define IO_MUX_GPIO35_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO35_FUN_IE_S  9
+/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO35_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO35_FUN_DRV_M  (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S)
+#define IO_MUX_GPIO35_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO35_FUN_DRV_S  10
+/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO35_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO35_MCU_SEL_M  (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S)
+#define IO_MUX_GPIO35_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO35_MCU_SEL_S  12
+/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO35_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO35_FILTER_EN_M  (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S)
+#define IO_MUX_GPIO35_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO35_FILTER_EN_S  15
+
+/** IO_MUX_gpio36_REG register
+ *  iomux control register for gpio36
+ */
+#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94)
+/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO36_MCU_OE_M  (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S)
+#define IO_MUX_GPIO36_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_OE_S  0
+/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO36_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO36_SLP_SEL_M  (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S)
+#define IO_MUX_GPIO36_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO36_SLP_SEL_S  1
+/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO36_MCU_WPD_M  (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S)
+#define IO_MUX_GPIO36_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_WPD_S  2
+/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO36_MCU_WPU_M  (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S)
+#define IO_MUX_GPIO36_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_WPU_S  3
+/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO36_MCU_IE_M  (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S)
+#define IO_MUX_GPIO36_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_IE_S  4
+/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO36_MCU_DRV_M  (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S)
+#define IO_MUX_GPIO36_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO36_MCU_DRV_S  5
+/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO36_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO36_FUN_WPD_M  (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S)
+#define IO_MUX_GPIO36_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO36_FUN_WPD_S  7
+/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO36_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO36_FUN_WPU_M  (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S)
+#define IO_MUX_GPIO36_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO36_FUN_WPU_S  8
+/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO36_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO36_FUN_IE_M  (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S)
+#define IO_MUX_GPIO36_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO36_FUN_IE_S  9
+/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO36_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO36_FUN_DRV_M  (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S)
+#define IO_MUX_GPIO36_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO36_FUN_DRV_S  10
+/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO36_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO36_MCU_SEL_M  (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S)
+#define IO_MUX_GPIO36_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO36_MCU_SEL_S  12
+/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO36_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO36_FILTER_EN_M  (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S)
+#define IO_MUX_GPIO36_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO36_FILTER_EN_S  15
+
+/** IO_MUX_gpio37_REG register
+ *  iomux control register for gpio37
+ */
+#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98)
+/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO37_MCU_OE_M  (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S)
+#define IO_MUX_GPIO37_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_OE_S  0
+/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO37_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO37_SLP_SEL_M  (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S)
+#define IO_MUX_GPIO37_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO37_SLP_SEL_S  1
+/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO37_MCU_WPD_M  (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S)
+#define IO_MUX_GPIO37_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_WPD_S  2
+/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO37_MCU_WPU_M  (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S)
+#define IO_MUX_GPIO37_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_WPU_S  3
+/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO37_MCU_IE_M  (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S)
+#define IO_MUX_GPIO37_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_IE_S  4
+/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO37_MCU_DRV_M  (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S)
+#define IO_MUX_GPIO37_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO37_MCU_DRV_S  5
+/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO37_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO37_FUN_WPD_M  (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S)
+#define IO_MUX_GPIO37_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO37_FUN_WPD_S  7
+/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO37_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO37_FUN_WPU_M  (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S)
+#define IO_MUX_GPIO37_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO37_FUN_WPU_S  8
+/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO37_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO37_FUN_IE_M  (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S)
+#define IO_MUX_GPIO37_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO37_FUN_IE_S  9
+/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO37_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO37_FUN_DRV_M  (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S)
+#define IO_MUX_GPIO37_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO37_FUN_DRV_S  10
+/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO37_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO37_MCU_SEL_M  (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S)
+#define IO_MUX_GPIO37_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO37_MCU_SEL_S  12
+/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO37_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO37_FILTER_EN_M  (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S)
+#define IO_MUX_GPIO37_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO37_FILTER_EN_S  15
+
+/** IO_MUX_gpio38_REG register
+ *  iomux control register for gpio38
+ */
+#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c)
+/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO38_MCU_OE_M  (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S)
+#define IO_MUX_GPIO38_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_OE_S  0
+/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO38_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO38_SLP_SEL_M  (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S)
+#define IO_MUX_GPIO38_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO38_SLP_SEL_S  1
+/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO38_MCU_WPD_M  (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S)
+#define IO_MUX_GPIO38_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_WPD_S  2
+/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO38_MCU_WPU_M  (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S)
+#define IO_MUX_GPIO38_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_WPU_S  3
+/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO38_MCU_IE_M  (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S)
+#define IO_MUX_GPIO38_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_IE_S  4
+/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO38_MCU_DRV_M  (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S)
+#define IO_MUX_GPIO38_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO38_MCU_DRV_S  5
+/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO38_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO38_FUN_WPD_M  (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S)
+#define IO_MUX_GPIO38_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO38_FUN_WPD_S  7
+/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO38_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO38_FUN_WPU_M  (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S)
+#define IO_MUX_GPIO38_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO38_FUN_WPU_S  8
+/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO38_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO38_FUN_IE_M  (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S)
+#define IO_MUX_GPIO38_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO38_FUN_IE_S  9
+/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO38_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO38_FUN_DRV_M  (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S)
+#define IO_MUX_GPIO38_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO38_FUN_DRV_S  10
+/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO38_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO38_MCU_SEL_M  (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S)
+#define IO_MUX_GPIO38_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO38_MCU_SEL_S  12
+/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO38_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO38_FILTER_EN_M  (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S)
+#define IO_MUX_GPIO38_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO38_FILTER_EN_S  15
+
+/** IO_MUX_gpio39_REG register
+ *  iomux control register for gpio39
+ */
+#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0)
+/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO39_MCU_OE_M  (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S)
+#define IO_MUX_GPIO39_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_OE_S  0
+/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO39_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO39_SLP_SEL_M  (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S)
+#define IO_MUX_GPIO39_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO39_SLP_SEL_S  1
+/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO39_MCU_WPD_M  (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S)
+#define IO_MUX_GPIO39_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_WPD_S  2
+/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO39_MCU_WPU_M  (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S)
+#define IO_MUX_GPIO39_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_WPU_S  3
+/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO39_MCU_IE_M  (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S)
+#define IO_MUX_GPIO39_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_IE_S  4
+/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO39_MCU_DRV_M  (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S)
+#define IO_MUX_GPIO39_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO39_MCU_DRV_S  5
+/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO39_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO39_FUN_WPD_M  (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S)
+#define IO_MUX_GPIO39_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO39_FUN_WPD_S  7
+/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO39_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO39_FUN_WPU_M  (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S)
+#define IO_MUX_GPIO39_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO39_FUN_WPU_S  8
+/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO39_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO39_FUN_IE_M  (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S)
+#define IO_MUX_GPIO39_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO39_FUN_IE_S  9
+/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO39_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO39_FUN_DRV_M  (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S)
+#define IO_MUX_GPIO39_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO39_FUN_DRV_S  10
+/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO39_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO39_MCU_SEL_M  (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S)
+#define IO_MUX_GPIO39_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO39_MCU_SEL_S  12
+/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO39_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO39_FILTER_EN_M  (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S)
+#define IO_MUX_GPIO39_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO39_FILTER_EN_S  15
+
+/** IO_MUX_gpio40_REG register
+ *  iomux control register for gpio40
+ */
+#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4)
+/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO40_MCU_OE_M  (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S)
+#define IO_MUX_GPIO40_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_OE_S  0
+/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO40_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO40_SLP_SEL_M  (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S)
+#define IO_MUX_GPIO40_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO40_SLP_SEL_S  1
+/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO40_MCU_WPD_M  (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S)
+#define IO_MUX_GPIO40_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_WPD_S  2
+/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO40_MCU_WPU_M  (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S)
+#define IO_MUX_GPIO40_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_WPU_S  3
+/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO40_MCU_IE_M  (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S)
+#define IO_MUX_GPIO40_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_IE_S  4
+/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO40_MCU_DRV_M  (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S)
+#define IO_MUX_GPIO40_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO40_MCU_DRV_S  5
+/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO40_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO40_FUN_WPD_M  (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S)
+#define IO_MUX_GPIO40_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO40_FUN_WPD_S  7
+/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO40_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO40_FUN_WPU_M  (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S)
+#define IO_MUX_GPIO40_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO40_FUN_WPU_S  8
+/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO40_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO40_FUN_IE_M  (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S)
+#define IO_MUX_GPIO40_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO40_FUN_IE_S  9
+/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO40_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO40_FUN_DRV_M  (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S)
+#define IO_MUX_GPIO40_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO40_FUN_DRV_S  10
+/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO40_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO40_MCU_SEL_M  (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S)
+#define IO_MUX_GPIO40_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO40_MCU_SEL_S  12
+/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO40_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO40_FILTER_EN_M  (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S)
+#define IO_MUX_GPIO40_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO40_FILTER_EN_S  15
+
+/** IO_MUX_gpio41_REG register
+ *  iomux control register for gpio41
+ */
+#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8)
+/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO41_MCU_OE_M  (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S)
+#define IO_MUX_GPIO41_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_OE_S  0
+/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO41_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO41_SLP_SEL_M  (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S)
+#define IO_MUX_GPIO41_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO41_SLP_SEL_S  1
+/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO41_MCU_WPD_M  (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S)
+#define IO_MUX_GPIO41_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_WPD_S  2
+/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO41_MCU_WPU_M  (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S)
+#define IO_MUX_GPIO41_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_WPU_S  3
+/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO41_MCU_IE_M  (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S)
+#define IO_MUX_GPIO41_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_IE_S  4
+/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO41_MCU_DRV_M  (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S)
+#define IO_MUX_GPIO41_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO41_MCU_DRV_S  5
+/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO41_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO41_FUN_WPD_M  (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S)
+#define IO_MUX_GPIO41_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO41_FUN_WPD_S  7
+/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO41_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO41_FUN_WPU_M  (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S)
+#define IO_MUX_GPIO41_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO41_FUN_WPU_S  8
+/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO41_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO41_FUN_IE_M  (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S)
+#define IO_MUX_GPIO41_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO41_FUN_IE_S  9
+/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO41_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO41_FUN_DRV_M  (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S)
+#define IO_MUX_GPIO41_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO41_FUN_DRV_S  10
+/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO41_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO41_MCU_SEL_M  (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S)
+#define IO_MUX_GPIO41_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO41_MCU_SEL_S  12
+/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO41_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO41_FILTER_EN_M  (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S)
+#define IO_MUX_GPIO41_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO41_FILTER_EN_S  15
+
+/** IO_MUX_gpio42_REG register
+ *  iomux control register for gpio42
+ */
+#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac)
+/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO42_MCU_OE_M  (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S)
+#define IO_MUX_GPIO42_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_OE_S  0
+/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO42_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO42_SLP_SEL_M  (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S)
+#define IO_MUX_GPIO42_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO42_SLP_SEL_S  1
+/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO42_MCU_WPD_M  (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S)
+#define IO_MUX_GPIO42_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_WPD_S  2
+/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO42_MCU_WPU_M  (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S)
+#define IO_MUX_GPIO42_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_WPU_S  3
+/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO42_MCU_IE_M  (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S)
+#define IO_MUX_GPIO42_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_IE_S  4
+/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO42_MCU_DRV_M  (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S)
+#define IO_MUX_GPIO42_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO42_MCU_DRV_S  5
+/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO42_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO42_FUN_WPD_M  (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S)
+#define IO_MUX_GPIO42_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO42_FUN_WPD_S  7
+/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO42_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO42_FUN_WPU_M  (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S)
+#define IO_MUX_GPIO42_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO42_FUN_WPU_S  8
+/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO42_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO42_FUN_IE_M  (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S)
+#define IO_MUX_GPIO42_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO42_FUN_IE_S  9
+/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO42_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO42_FUN_DRV_M  (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S)
+#define IO_MUX_GPIO42_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO42_FUN_DRV_S  10
+/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO42_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO42_MCU_SEL_M  (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S)
+#define IO_MUX_GPIO42_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO42_MCU_SEL_S  12
+/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO42_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO42_FILTER_EN_M  (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S)
+#define IO_MUX_GPIO42_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO42_FILTER_EN_S  15
+
+/** IO_MUX_gpio43_REG register
+ *  iomux control register for gpio43
+ */
+#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0)
+/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO43_MCU_OE_M  (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S)
+#define IO_MUX_GPIO43_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_OE_S  0
+/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO43_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO43_SLP_SEL_M  (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S)
+#define IO_MUX_GPIO43_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO43_SLP_SEL_S  1
+/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO43_MCU_WPD_M  (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S)
+#define IO_MUX_GPIO43_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_WPD_S  2
+/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO43_MCU_WPU_M  (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S)
+#define IO_MUX_GPIO43_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_WPU_S  3
+/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO43_MCU_IE_M  (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S)
+#define IO_MUX_GPIO43_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_IE_S  4
+/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO43_MCU_DRV_M  (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S)
+#define IO_MUX_GPIO43_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO43_MCU_DRV_S  5
+/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO43_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO43_FUN_WPD_M  (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S)
+#define IO_MUX_GPIO43_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO43_FUN_WPD_S  7
+/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO43_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO43_FUN_WPU_M  (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S)
+#define IO_MUX_GPIO43_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO43_FUN_WPU_S  8
+/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO43_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO43_FUN_IE_M  (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S)
+#define IO_MUX_GPIO43_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO43_FUN_IE_S  9
+/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO43_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO43_FUN_DRV_M  (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S)
+#define IO_MUX_GPIO43_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO43_FUN_DRV_S  10
+/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO43_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO43_MCU_SEL_M  (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S)
+#define IO_MUX_GPIO43_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO43_MCU_SEL_S  12
+/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO43_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO43_FILTER_EN_M  (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S)
+#define IO_MUX_GPIO43_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO43_FILTER_EN_S  15
+
+/** IO_MUX_gpio44_REG register
+ *  iomux control register for gpio44
+ */
+#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4)
+/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO44_MCU_OE_M  (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S)
+#define IO_MUX_GPIO44_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_OE_S  0
+/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO44_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO44_SLP_SEL_M  (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S)
+#define IO_MUX_GPIO44_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO44_SLP_SEL_S  1
+/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO44_MCU_WPD_M  (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S)
+#define IO_MUX_GPIO44_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_WPD_S  2
+/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO44_MCU_WPU_M  (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S)
+#define IO_MUX_GPIO44_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_WPU_S  3
+/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO44_MCU_IE_M  (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S)
+#define IO_MUX_GPIO44_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_IE_S  4
+/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO44_MCU_DRV_M  (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S)
+#define IO_MUX_GPIO44_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO44_MCU_DRV_S  5
+/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO44_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO44_FUN_WPD_M  (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S)
+#define IO_MUX_GPIO44_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO44_FUN_WPD_S  7
+/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO44_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO44_FUN_WPU_M  (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S)
+#define IO_MUX_GPIO44_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO44_FUN_WPU_S  8
+/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO44_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO44_FUN_IE_M  (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S)
+#define IO_MUX_GPIO44_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO44_FUN_IE_S  9
+/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO44_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO44_FUN_DRV_M  (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S)
+#define IO_MUX_GPIO44_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO44_FUN_DRV_S  10
+/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO44_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO44_MCU_SEL_M  (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S)
+#define IO_MUX_GPIO44_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO44_MCU_SEL_S  12
+/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO44_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO44_FILTER_EN_M  (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S)
+#define IO_MUX_GPIO44_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO44_FILTER_EN_S  15
+
+/** IO_MUX_gpio45_REG register
+ *  iomux control register for gpio45
+ */
+#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8)
+/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO45_MCU_OE_M  (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S)
+#define IO_MUX_GPIO45_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_OE_S  0
+/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO45_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO45_SLP_SEL_M  (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S)
+#define IO_MUX_GPIO45_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO45_SLP_SEL_S  1
+/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO45_MCU_WPD_M  (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S)
+#define IO_MUX_GPIO45_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_WPD_S  2
+/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO45_MCU_WPU_M  (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S)
+#define IO_MUX_GPIO45_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_WPU_S  3
+/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO45_MCU_IE_M  (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S)
+#define IO_MUX_GPIO45_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_IE_S  4
+/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO45_MCU_DRV_M  (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S)
+#define IO_MUX_GPIO45_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO45_MCU_DRV_S  5
+/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO45_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO45_FUN_WPD_M  (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S)
+#define IO_MUX_GPIO45_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO45_FUN_WPD_S  7
+/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO45_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO45_FUN_WPU_M  (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S)
+#define IO_MUX_GPIO45_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO45_FUN_WPU_S  8
+/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO45_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO45_FUN_IE_M  (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S)
+#define IO_MUX_GPIO45_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO45_FUN_IE_S  9
+/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO45_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO45_FUN_DRV_M  (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S)
+#define IO_MUX_GPIO45_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO45_FUN_DRV_S  10
+/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO45_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO45_MCU_SEL_M  (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S)
+#define IO_MUX_GPIO45_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO45_MCU_SEL_S  12
+/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO45_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO45_FILTER_EN_M  (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S)
+#define IO_MUX_GPIO45_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO45_FILTER_EN_S  15
+
+/** IO_MUX_gpio46_REG register
+ *  iomux control register for gpio46
+ */
+#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc)
+/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO46_MCU_OE_M  (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S)
+#define IO_MUX_GPIO46_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_OE_S  0
+/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO46_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO46_SLP_SEL_M  (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S)
+#define IO_MUX_GPIO46_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO46_SLP_SEL_S  1
+/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO46_MCU_WPD_M  (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S)
+#define IO_MUX_GPIO46_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_WPD_S  2
+/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO46_MCU_WPU_M  (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S)
+#define IO_MUX_GPIO46_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_WPU_S  3
+/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO46_MCU_IE_M  (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S)
+#define IO_MUX_GPIO46_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_IE_S  4
+/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO46_MCU_DRV_M  (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S)
+#define IO_MUX_GPIO46_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO46_MCU_DRV_S  5
+/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO46_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO46_FUN_WPD_M  (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S)
+#define IO_MUX_GPIO46_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO46_FUN_WPD_S  7
+/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO46_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO46_FUN_WPU_M  (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S)
+#define IO_MUX_GPIO46_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO46_FUN_WPU_S  8
+/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO46_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO46_FUN_IE_M  (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S)
+#define IO_MUX_GPIO46_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO46_FUN_IE_S  9
+/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO46_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO46_FUN_DRV_M  (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S)
+#define IO_MUX_GPIO46_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO46_FUN_DRV_S  10
+/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO46_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO46_MCU_SEL_M  (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S)
+#define IO_MUX_GPIO46_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO46_MCU_SEL_S  12
+/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO46_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO46_FILTER_EN_M  (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S)
+#define IO_MUX_GPIO46_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO46_FILTER_EN_S  15
+
+/** IO_MUX_gpio47_REG register
+ *  iomux control register for gpio47
+ */
+#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0)
+/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO47_MCU_OE_M  (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S)
+#define IO_MUX_GPIO47_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_OE_S  0
+/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO47_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO47_SLP_SEL_M  (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S)
+#define IO_MUX_GPIO47_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO47_SLP_SEL_S  1
+/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO47_MCU_WPD_M  (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S)
+#define IO_MUX_GPIO47_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_WPD_S  2
+/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO47_MCU_WPU_M  (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S)
+#define IO_MUX_GPIO47_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_WPU_S  3
+/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO47_MCU_IE_M  (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S)
+#define IO_MUX_GPIO47_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_IE_S  4
+/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO47_MCU_DRV_M  (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S)
+#define IO_MUX_GPIO47_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO47_MCU_DRV_S  5
+/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO47_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO47_FUN_WPD_M  (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S)
+#define IO_MUX_GPIO47_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO47_FUN_WPD_S  7
+/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO47_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO47_FUN_WPU_M  (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S)
+#define IO_MUX_GPIO47_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO47_FUN_WPU_S  8
+/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO47_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO47_FUN_IE_M  (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S)
+#define IO_MUX_GPIO47_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO47_FUN_IE_S  9
+/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO47_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO47_FUN_DRV_M  (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S)
+#define IO_MUX_GPIO47_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO47_FUN_DRV_S  10
+/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO47_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO47_MCU_SEL_M  (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S)
+#define IO_MUX_GPIO47_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO47_MCU_SEL_S  12
+/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO47_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO47_FILTER_EN_M  (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S)
+#define IO_MUX_GPIO47_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO47_FILTER_EN_S  15
+
+/** IO_MUX_gpio48_REG register
+ *  iomux control register for gpio48
+ */
+#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4)
+/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO48_MCU_OE_M  (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S)
+#define IO_MUX_GPIO48_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_OE_S  0
+/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO48_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO48_SLP_SEL_M  (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S)
+#define IO_MUX_GPIO48_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO48_SLP_SEL_S  1
+/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO48_MCU_WPD_M  (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S)
+#define IO_MUX_GPIO48_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_WPD_S  2
+/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO48_MCU_WPU_M  (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S)
+#define IO_MUX_GPIO48_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_WPU_S  3
+/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO48_MCU_IE_M  (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S)
+#define IO_MUX_GPIO48_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_IE_S  4
+/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO48_MCU_DRV_M  (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S)
+#define IO_MUX_GPIO48_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO48_MCU_DRV_S  5
+/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO48_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO48_FUN_WPD_M  (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S)
+#define IO_MUX_GPIO48_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO48_FUN_WPD_S  7
+/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO48_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO48_FUN_WPU_M  (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S)
+#define IO_MUX_GPIO48_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO48_FUN_WPU_S  8
+/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO48_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO48_FUN_IE_M  (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S)
+#define IO_MUX_GPIO48_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO48_FUN_IE_S  9
+/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO48_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO48_FUN_DRV_M  (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S)
+#define IO_MUX_GPIO48_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO48_FUN_DRV_S  10
+/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO48_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO48_MCU_SEL_M  (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S)
+#define IO_MUX_GPIO48_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO48_MCU_SEL_S  12
+/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO48_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO48_FILTER_EN_M  (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S)
+#define IO_MUX_GPIO48_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO48_FILTER_EN_S  15
+
+/** IO_MUX_gpio49_REG register
+ *  iomux control register for gpio49
+ */
+#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8)
+/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO49_MCU_OE_M  (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S)
+#define IO_MUX_GPIO49_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_OE_S  0
+/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO49_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO49_SLP_SEL_M  (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S)
+#define IO_MUX_GPIO49_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO49_SLP_SEL_S  1
+/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO49_MCU_WPD_M  (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S)
+#define IO_MUX_GPIO49_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_WPD_S  2
+/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO49_MCU_WPU_M  (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S)
+#define IO_MUX_GPIO49_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_WPU_S  3
+/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO49_MCU_IE_M  (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S)
+#define IO_MUX_GPIO49_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_IE_S  4
+/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO49_MCU_DRV_M  (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S)
+#define IO_MUX_GPIO49_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO49_MCU_DRV_S  5
+/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO49_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO49_FUN_WPD_M  (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S)
+#define IO_MUX_GPIO49_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO49_FUN_WPD_S  7
+/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO49_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO49_FUN_WPU_M  (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S)
+#define IO_MUX_GPIO49_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO49_FUN_WPU_S  8
+/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO49_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO49_FUN_IE_M  (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S)
+#define IO_MUX_GPIO49_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO49_FUN_IE_S  9
+/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO49_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO49_FUN_DRV_M  (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S)
+#define IO_MUX_GPIO49_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO49_FUN_DRV_S  10
+/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO49_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO49_MCU_SEL_M  (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S)
+#define IO_MUX_GPIO49_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO49_MCU_SEL_S  12
+/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO49_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO49_FILTER_EN_M  (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S)
+#define IO_MUX_GPIO49_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO49_FILTER_EN_S  15
+
+/** IO_MUX_gpio50_REG register
+ *  iomux control register for gpio50
+ */
+#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc)
+/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO50_MCU_OE_M  (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S)
+#define IO_MUX_GPIO50_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_OE_S  0
+/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO50_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO50_SLP_SEL_M  (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S)
+#define IO_MUX_GPIO50_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO50_SLP_SEL_S  1
+/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO50_MCU_WPD_M  (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S)
+#define IO_MUX_GPIO50_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_WPD_S  2
+/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO50_MCU_WPU_M  (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S)
+#define IO_MUX_GPIO50_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_WPU_S  3
+/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO50_MCU_IE_M  (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S)
+#define IO_MUX_GPIO50_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_IE_S  4
+/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO50_MCU_DRV_M  (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S)
+#define IO_MUX_GPIO50_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO50_MCU_DRV_S  5
+/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO50_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO50_FUN_WPD_M  (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S)
+#define IO_MUX_GPIO50_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO50_FUN_WPD_S  7
+/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO50_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO50_FUN_WPU_M  (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S)
+#define IO_MUX_GPIO50_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO50_FUN_WPU_S  8
+/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO50_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO50_FUN_IE_M  (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S)
+#define IO_MUX_GPIO50_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO50_FUN_IE_S  9
+/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO50_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO50_FUN_DRV_M  (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S)
+#define IO_MUX_GPIO50_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO50_FUN_DRV_S  10
+/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO50_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO50_MCU_SEL_M  (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S)
+#define IO_MUX_GPIO50_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO50_MCU_SEL_S  12
+/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO50_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO50_FILTER_EN_M  (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S)
+#define IO_MUX_GPIO50_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO50_FILTER_EN_S  15
+
+/** IO_MUX_gpio51_REG register
+ *  iomux control register for gpio51
+ */
+#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0)
+/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO51_MCU_OE_M  (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S)
+#define IO_MUX_GPIO51_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_OE_S  0
+/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO51_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO51_SLP_SEL_M  (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S)
+#define IO_MUX_GPIO51_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO51_SLP_SEL_S  1
+/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO51_MCU_WPD_M  (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S)
+#define IO_MUX_GPIO51_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_WPD_S  2
+/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO51_MCU_WPU_M  (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S)
+#define IO_MUX_GPIO51_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_WPU_S  3
+/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO51_MCU_IE_M  (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S)
+#define IO_MUX_GPIO51_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_IE_S  4
+/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO51_MCU_DRV_M  (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S)
+#define IO_MUX_GPIO51_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO51_MCU_DRV_S  5
+/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO51_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO51_FUN_WPD_M  (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S)
+#define IO_MUX_GPIO51_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO51_FUN_WPD_S  7
+/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO51_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO51_FUN_WPU_M  (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S)
+#define IO_MUX_GPIO51_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO51_FUN_WPU_S  8
+/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO51_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO51_FUN_IE_M  (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S)
+#define IO_MUX_GPIO51_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO51_FUN_IE_S  9
+/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO51_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO51_FUN_DRV_M  (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S)
+#define IO_MUX_GPIO51_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO51_FUN_DRV_S  10
+/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO51_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO51_MCU_SEL_M  (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S)
+#define IO_MUX_GPIO51_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO51_MCU_SEL_S  12
+/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO51_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO51_FILTER_EN_M  (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S)
+#define IO_MUX_GPIO51_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO51_FILTER_EN_S  15
+
+/** IO_MUX_gpio52_REG register
+ *  iomux control register for gpio52
+ */
+#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4)
+/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO52_MCU_OE_M  (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S)
+#define IO_MUX_GPIO52_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_OE_S  0
+/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO52_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO52_SLP_SEL_M  (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S)
+#define IO_MUX_GPIO52_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO52_SLP_SEL_S  1
+/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO52_MCU_WPD_M  (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S)
+#define IO_MUX_GPIO52_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_WPD_S  2
+/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO52_MCU_WPU_M  (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S)
+#define IO_MUX_GPIO52_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_WPU_S  3
+/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO52_MCU_IE_M  (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S)
+#define IO_MUX_GPIO52_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_IE_S  4
+/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO52_MCU_DRV_M  (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S)
+#define IO_MUX_GPIO52_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO52_MCU_DRV_S  5
+/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO52_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO52_FUN_WPD_M  (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S)
+#define IO_MUX_GPIO52_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO52_FUN_WPD_S  7
+/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO52_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO52_FUN_WPU_M  (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S)
+#define IO_MUX_GPIO52_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO52_FUN_WPU_S  8
+/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO52_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO52_FUN_IE_M  (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S)
+#define IO_MUX_GPIO52_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO52_FUN_IE_S  9
+/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO52_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO52_FUN_DRV_M  (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S)
+#define IO_MUX_GPIO52_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO52_FUN_DRV_S  10
+/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO52_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO52_MCU_SEL_M  (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S)
+#define IO_MUX_GPIO52_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO52_MCU_SEL_S  12
+/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO52_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO52_FILTER_EN_M  (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S)
+#define IO_MUX_GPIO52_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO52_FILTER_EN_S  15
+
+/** IO_MUX_gpio53_REG register
+ *  iomux control register for gpio53
+ */
+#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8)
+/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO53_MCU_OE_M  (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S)
+#define IO_MUX_GPIO53_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_OE_S  0
+/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO53_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO53_SLP_SEL_M  (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S)
+#define IO_MUX_GPIO53_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO53_SLP_SEL_S  1
+/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO53_MCU_WPD_M  (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S)
+#define IO_MUX_GPIO53_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_WPD_S  2
+/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO53_MCU_WPU_M  (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S)
+#define IO_MUX_GPIO53_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_WPU_S  3
+/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO53_MCU_IE_M  (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S)
+#define IO_MUX_GPIO53_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_IE_S  4
+/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO53_MCU_DRV_M  (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S)
+#define IO_MUX_GPIO53_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO53_MCU_DRV_S  5
+/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO53_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO53_FUN_WPD_M  (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S)
+#define IO_MUX_GPIO53_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO53_FUN_WPD_S  7
+/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO53_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO53_FUN_WPU_M  (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S)
+#define IO_MUX_GPIO53_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO53_FUN_WPU_S  8
+/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO53_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO53_FUN_IE_M  (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S)
+#define IO_MUX_GPIO53_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO53_FUN_IE_S  9
+/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO53_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO53_FUN_DRV_M  (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S)
+#define IO_MUX_GPIO53_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO53_FUN_DRV_S  10
+/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO53_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO53_MCU_SEL_M  (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S)
+#define IO_MUX_GPIO53_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO53_MCU_SEL_S  12
+/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO53_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO53_FILTER_EN_M  (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S)
+#define IO_MUX_GPIO53_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO53_FILTER_EN_S  15
+
+/** IO_MUX_gpio54_REG register
+ *  iomux control register for gpio54
+ */
+#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc)
+/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO54_MCU_OE_M  (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S)
+#define IO_MUX_GPIO54_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_OE_S  0
+/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO54_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO54_SLP_SEL_M  (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S)
+#define IO_MUX_GPIO54_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO54_SLP_SEL_S  1
+/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO54_MCU_WPD_M  (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S)
+#define IO_MUX_GPIO54_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_WPD_S  2
+/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO54_MCU_WPU_M  (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S)
+#define IO_MUX_GPIO54_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_WPU_S  3
+/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO54_MCU_IE_M  (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S)
+#define IO_MUX_GPIO54_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_IE_S  4
+/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO54_MCU_DRV_M  (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S)
+#define IO_MUX_GPIO54_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO54_MCU_DRV_S  5
+/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO54_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO54_FUN_WPD_M  (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S)
+#define IO_MUX_GPIO54_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO54_FUN_WPD_S  7
+/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO54_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO54_FUN_WPU_M  (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S)
+#define IO_MUX_GPIO54_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO54_FUN_WPU_S  8
+/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO54_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO54_FUN_IE_M  (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S)
+#define IO_MUX_GPIO54_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO54_FUN_IE_S  9
+/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO54_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO54_FUN_DRV_M  (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S)
+#define IO_MUX_GPIO54_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO54_FUN_DRV_S  10
+/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO54_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO54_MCU_SEL_M  (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S)
+#define IO_MUX_GPIO54_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO54_MCU_SEL_S  12
+/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO54_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO54_FILTER_EN_M  (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S)
+#define IO_MUX_GPIO54_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO54_FILTER_EN_S  15
+
+/** IO_MUX_gpio55_REG register
+ *  iomux control register for gpio55
+ */
+#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0)
+/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO55_MCU_OE_M  (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S)
+#define IO_MUX_GPIO55_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_OE_S  0
+/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO55_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO55_SLP_SEL_M  (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S)
+#define IO_MUX_GPIO55_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO55_SLP_SEL_S  1
+/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO55_MCU_WPD_M  (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S)
+#define IO_MUX_GPIO55_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_WPD_S  2
+/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO55_MCU_WPU_M  (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S)
+#define IO_MUX_GPIO55_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_WPU_S  3
+/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO55_MCU_IE_M  (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S)
+#define IO_MUX_GPIO55_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_IE_S  4
+/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO55_MCU_DRV_M  (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S)
+#define IO_MUX_GPIO55_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO55_MCU_DRV_S  5
+/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO55_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO55_FUN_WPD_M  (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S)
+#define IO_MUX_GPIO55_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO55_FUN_WPD_S  7
+/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO55_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO55_FUN_WPU_M  (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S)
+#define IO_MUX_GPIO55_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO55_FUN_WPU_S  8
+/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO55_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO55_FUN_IE_M  (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S)
+#define IO_MUX_GPIO55_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO55_FUN_IE_S  9
+/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO55_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO55_FUN_DRV_M  (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S)
+#define IO_MUX_GPIO55_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO55_FUN_DRV_S  10
+/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO55_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO55_MCU_SEL_M  (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S)
+#define IO_MUX_GPIO55_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO55_MCU_SEL_S  12
+/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO55_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO55_FILTER_EN_M  (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S)
+#define IO_MUX_GPIO55_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO55_FILTER_EN_S  15
+
+/** IO_MUX_gpio56_REG register
+ *  iomux control register for gpio56
+ */
+#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4)
+/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO56_MCU_OE_M  (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S)
+#define IO_MUX_GPIO56_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_OE_S  0
+/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO56_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO56_SLP_SEL_M  (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S)
+#define IO_MUX_GPIO56_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO56_SLP_SEL_S  1
+/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO56_MCU_WPD_M  (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S)
+#define IO_MUX_GPIO56_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_WPD_S  2
+/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO56_MCU_WPU_M  (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S)
+#define IO_MUX_GPIO56_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_WPU_S  3
+/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO56_MCU_IE_M  (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S)
+#define IO_MUX_GPIO56_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_IE_S  4
+/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strenth on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO56_MCU_DRV_M  (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S)
+#define IO_MUX_GPIO56_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO56_MCU_DRV_S  5
+/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO56_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO56_FUN_WPD_M  (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S)
+#define IO_MUX_GPIO56_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO56_FUN_WPD_S  7
+/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO56_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO56_FUN_WPU_M  (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S)
+#define IO_MUX_GPIO56_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO56_FUN_WPU_S  8
+/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO56_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO56_FUN_IE_M  (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S)
+#define IO_MUX_GPIO56_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO56_FUN_IE_S  9
+/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO56_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO56_FUN_DRV_M  (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S)
+#define IO_MUX_GPIO56_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO56_FUN_DRV_S  10
+/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO56_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO56_MCU_SEL_M  (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S)
+#define IO_MUX_GPIO56_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO56_MCU_SEL_S  12
+/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO56_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO56_FILTER_EN_M  (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S)
+#define IO_MUX_GPIO56_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO56_FILTER_EN_S  15
+
+/** IO_MUX_DATE_REG register
+ *  iomux version
+ */
+#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104)
+/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794;
+ *  csv date
+ */
+#define IO_MUX_DATE    0x0FFFFFFFU
+#define IO_MUX_DATE_M  (IO_MUX_DATE_V << IO_MUX_DATE_S)
+#define IO_MUX_DATE_V  0x0FFFFFFFU
+#define IO_MUX_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/iomux_struct.h b/components/soc/esp32p4/include/soc/iomux_struct.h
new file mode 100644
index 0000000000..583b6dec07
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/iomux_struct.h
@@ -0,0 +1,3429 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: IOMUX Register */
+/** Type of gpio0 register
+ *  iomux control register for gpio0
+ */
+typedef union {
+    struct {
+        /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio0_mcu_oe:1;
+        /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio0_slp_sel:1;
+        /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio0_mcu_wpd:1;
+        /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio0_mcu_wpu:1;
+        /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio0_mcu_ie:1;
+        /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio0_mcu_drv:2;
+        /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio0_fun_wpd:1;
+        /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio0_fun_wpu:1;
+        /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio0_fun_ie:1;
+        /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio0_fun_drv:2;
+        /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio0_mcu_sel:3;
+        /** gpio0_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio0_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio0_reg_t;
+
+/** Type of gpio1 register
+ *  iomux control register for gpio1
+ */
+typedef union {
+    struct {
+        /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio1_mcu_oe:1;
+        /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio1_slp_sel:1;
+        /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio1_mcu_wpd:1;
+        /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio1_mcu_wpu:1;
+        /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio1_mcu_ie:1;
+        /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio1_mcu_drv:2;
+        /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio1_fun_wpd:1;
+        /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio1_fun_wpu:1;
+        /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio1_fun_ie:1;
+        /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio1_fun_drv:2;
+        /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio1_mcu_sel:3;
+        /** gpio1_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio1_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio1_reg_t;
+
+/** Type of gpio2 register
+ *  iomux control register for gpio2
+ */
+typedef union {
+    struct {
+        /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio2_mcu_oe:1;
+        /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio2_slp_sel:1;
+        /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio2_mcu_wpd:1;
+        /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio2_mcu_wpu:1;
+        /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio2_mcu_ie:1;
+        /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio2_mcu_drv:2;
+        /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio2_fun_wpd:1;
+        /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio2_fun_wpu:1;
+        /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio2_fun_ie:1;
+        /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio2_fun_drv:2;
+        /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio2_mcu_sel:3;
+        /** gpio2_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio2_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio2_reg_t;
+
+/** Type of gpio3 register
+ *  iomux control register for gpio3
+ */
+typedef union {
+    struct {
+        /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio3_mcu_oe:1;
+        /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio3_slp_sel:1;
+        /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio3_mcu_wpd:1;
+        /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio3_mcu_wpu:1;
+        /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio3_mcu_ie:1;
+        /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio3_mcu_drv:2;
+        /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio3_fun_wpd:1;
+        /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio3_fun_wpu:1;
+        /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio3_fun_ie:1;
+        /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio3_fun_drv:2;
+        /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio3_mcu_sel:3;
+        /** gpio3_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio3_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio3_reg_t;
+
+/** Type of gpio4 register
+ *  iomux control register for gpio4
+ */
+typedef union {
+    struct {
+        /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio4_mcu_oe:1;
+        /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio4_slp_sel:1;
+        /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio4_mcu_wpd:1;
+        /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio4_mcu_wpu:1;
+        /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio4_mcu_ie:1;
+        /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio4_mcu_drv:2;
+        /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio4_fun_wpd:1;
+        /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio4_fun_wpu:1;
+        /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio4_fun_ie:1;
+        /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio4_fun_drv:2;
+        /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio4_mcu_sel:3;
+        /** gpio4_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio4_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio4_reg_t;
+
+/** Type of gpio5 register
+ *  iomux control register for gpio5
+ */
+typedef union {
+    struct {
+        /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio5_mcu_oe:1;
+        /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio5_slp_sel:1;
+        /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio5_mcu_wpd:1;
+        /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio5_mcu_wpu:1;
+        /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio5_mcu_ie:1;
+        /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio5_mcu_drv:2;
+        /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio5_fun_wpd:1;
+        /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio5_fun_wpu:1;
+        /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio5_fun_ie:1;
+        /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio5_fun_drv:2;
+        /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio5_mcu_sel:3;
+        /** gpio5_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio5_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio5_reg_t;
+
+/** Type of gpio6 register
+ *  iomux control register for gpio6
+ */
+typedef union {
+    struct {
+        /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio6_mcu_oe:1;
+        /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio6_slp_sel:1;
+        /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio6_mcu_wpd:1;
+        /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio6_mcu_wpu:1;
+        /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio6_mcu_ie:1;
+        /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio6_mcu_drv:2;
+        /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio6_fun_wpd:1;
+        /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio6_fun_wpu:1;
+        /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio6_fun_ie:1;
+        /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio6_fun_drv:2;
+        /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio6_mcu_sel:3;
+        /** gpio6_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio6_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio6_reg_t;
+
+/** Type of gpio7 register
+ *  iomux control register for gpio7
+ */
+typedef union {
+    struct {
+        /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio7_mcu_oe:1;
+        /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio7_slp_sel:1;
+        /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio7_mcu_wpd:1;
+        /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio7_mcu_wpu:1;
+        /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio7_mcu_ie:1;
+        /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio7_mcu_drv:2;
+        /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio7_fun_wpd:1;
+        /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio7_fun_wpu:1;
+        /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio7_fun_ie:1;
+        /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio7_fun_drv:2;
+        /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio7_mcu_sel:3;
+        /** gpio7_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio7_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio7_reg_t;
+
+/** Type of gpio8 register
+ *  iomux control register for gpio8
+ */
+typedef union {
+    struct {
+        /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio8_mcu_oe:1;
+        /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio8_slp_sel:1;
+        /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio8_mcu_wpd:1;
+        /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio8_mcu_wpu:1;
+        /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio8_mcu_ie:1;
+        /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio8_mcu_drv:2;
+        /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio8_fun_wpd:1;
+        /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio8_fun_wpu:1;
+        /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio8_fun_ie:1;
+        /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio8_fun_drv:2;
+        /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio8_mcu_sel:3;
+        /** gpio8_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio8_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio8_reg_t;
+
+/** Type of gpio9 register
+ *  iomux control register for gpio9
+ */
+typedef union {
+    struct {
+        /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio9_mcu_oe:1;
+        /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio9_slp_sel:1;
+        /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio9_mcu_wpd:1;
+        /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio9_mcu_wpu:1;
+        /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio9_mcu_ie:1;
+        /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio9_mcu_drv:2;
+        /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio9_fun_wpd:1;
+        /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio9_fun_wpu:1;
+        /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio9_fun_ie:1;
+        /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio9_fun_drv:2;
+        /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio9_mcu_sel:3;
+        /** gpio9_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio9_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio9_reg_t;
+
+/** Type of gpio10 register
+ *  iomux control register for gpio10
+ */
+typedef union {
+    struct {
+        /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio10_mcu_oe:1;
+        /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio10_slp_sel:1;
+        /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio10_mcu_wpd:1;
+        /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio10_mcu_wpu:1;
+        /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio10_mcu_ie:1;
+        /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio10_mcu_drv:2;
+        /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio10_fun_wpd:1;
+        /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio10_fun_wpu:1;
+        /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio10_fun_ie:1;
+        /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio10_fun_drv:2;
+        /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio10_mcu_sel:3;
+        /** gpio10_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio10_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio10_reg_t;
+
+/** Type of gpio11 register
+ *  iomux control register for gpio11
+ */
+typedef union {
+    struct {
+        /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio11_mcu_oe:1;
+        /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio11_slp_sel:1;
+        /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio11_mcu_wpd:1;
+        /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio11_mcu_wpu:1;
+        /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio11_mcu_ie:1;
+        /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio11_mcu_drv:2;
+        /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio11_fun_wpd:1;
+        /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio11_fun_wpu:1;
+        /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio11_fun_ie:1;
+        /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio11_fun_drv:2;
+        /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio11_mcu_sel:3;
+        /** gpio11_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio11_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio11_reg_t;
+
+/** Type of gpio12 register
+ *  iomux control register for gpio12
+ */
+typedef union {
+    struct {
+        /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio12_mcu_oe:1;
+        /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio12_slp_sel:1;
+        /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio12_mcu_wpd:1;
+        /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio12_mcu_wpu:1;
+        /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio12_mcu_ie:1;
+        /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio12_mcu_drv:2;
+        /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio12_fun_wpd:1;
+        /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio12_fun_wpu:1;
+        /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio12_fun_ie:1;
+        /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio12_fun_drv:2;
+        /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio12_mcu_sel:3;
+        /** gpio12_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio12_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio12_reg_t;
+
+/** Type of gpio13 register
+ *  iomux control register for gpio13
+ */
+typedef union {
+    struct {
+        /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio13_mcu_oe:1;
+        /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio13_slp_sel:1;
+        /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio13_mcu_wpd:1;
+        /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio13_mcu_wpu:1;
+        /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio13_mcu_ie:1;
+        /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio13_mcu_drv:2;
+        /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio13_fun_wpd:1;
+        /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio13_fun_wpu:1;
+        /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio13_fun_ie:1;
+        /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio13_fun_drv:2;
+        /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio13_mcu_sel:3;
+        /** gpio13_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio13_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio13_reg_t;
+
+/** Type of gpio14 register
+ *  iomux control register for gpio14
+ */
+typedef union {
+    struct {
+        /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio14_mcu_oe:1;
+        /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio14_slp_sel:1;
+        /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio14_mcu_wpd:1;
+        /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio14_mcu_wpu:1;
+        /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio14_mcu_ie:1;
+        /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio14_mcu_drv:2;
+        /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio14_fun_wpd:1;
+        /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio14_fun_wpu:1;
+        /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio14_fun_ie:1;
+        /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio14_fun_drv:2;
+        /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio14_mcu_sel:3;
+        /** gpio14_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio14_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio14_reg_t;
+
+/** Type of gpio15 register
+ *  iomux control register for gpio15
+ */
+typedef union {
+    struct {
+        /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio15_mcu_oe:1;
+        /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio15_slp_sel:1;
+        /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio15_mcu_wpd:1;
+        /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio15_mcu_wpu:1;
+        /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio15_mcu_ie:1;
+        /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio15_mcu_drv:2;
+        /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio15_fun_wpd:1;
+        /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio15_fun_wpu:1;
+        /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio15_fun_ie:1;
+        /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio15_fun_drv:2;
+        /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio15_mcu_sel:3;
+        /** gpio15_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio15_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio15_reg_t;
+
+/** Type of gpio16 register
+ *  iomux control register for gpio16
+ */
+typedef union {
+    struct {
+        /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio16_mcu_oe:1;
+        /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio16_slp_sel:1;
+        /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio16_mcu_wpd:1;
+        /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio16_mcu_wpu:1;
+        /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio16_mcu_ie:1;
+        /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio16_mcu_drv:2;
+        /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio16_fun_wpd:1;
+        /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio16_fun_wpu:1;
+        /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio16_fun_ie:1;
+        /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio16_fun_drv:2;
+        /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio16_mcu_sel:3;
+        /** gpio16_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio16_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio16_reg_t;
+
+/** Type of gpio17 register
+ *  iomux control register for gpio17
+ */
+typedef union {
+    struct {
+        /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio17_mcu_oe:1;
+        /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio17_slp_sel:1;
+        /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio17_mcu_wpd:1;
+        /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio17_mcu_wpu:1;
+        /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio17_mcu_ie:1;
+        /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio17_mcu_drv:2;
+        /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio17_fun_wpd:1;
+        /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio17_fun_wpu:1;
+        /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio17_fun_ie:1;
+        /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio17_fun_drv:2;
+        /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio17_mcu_sel:3;
+        /** gpio17_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio17_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio17_reg_t;
+
+/** Type of gpio18 register
+ *  iomux control register for gpio18
+ */
+typedef union {
+    struct {
+        /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio18_mcu_oe:1;
+        /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio18_slp_sel:1;
+        /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio18_mcu_wpd:1;
+        /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio18_mcu_wpu:1;
+        /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio18_mcu_ie:1;
+        /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio18_mcu_drv:2;
+        /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio18_fun_wpd:1;
+        /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio18_fun_wpu:1;
+        /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio18_fun_ie:1;
+        /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio18_fun_drv:2;
+        /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio18_mcu_sel:3;
+        /** gpio18_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio18_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio18_reg_t;
+
+/** Type of gpio19 register
+ *  iomux control register for gpio19
+ */
+typedef union {
+    struct {
+        /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio19_mcu_oe:1;
+        /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio19_slp_sel:1;
+        /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio19_mcu_wpd:1;
+        /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio19_mcu_wpu:1;
+        /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio19_mcu_ie:1;
+        /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio19_mcu_drv:2;
+        /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio19_fun_wpd:1;
+        /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio19_fun_wpu:1;
+        /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio19_fun_ie:1;
+        /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio19_fun_drv:2;
+        /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio19_mcu_sel:3;
+        /** gpio19_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio19_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio19_reg_t;
+
+/** Type of gpio20 register
+ *  iomux control register for gpio20
+ */
+typedef union {
+    struct {
+        /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio20_mcu_oe:1;
+        /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio20_slp_sel:1;
+        /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio20_mcu_wpd:1;
+        /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio20_mcu_wpu:1;
+        /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio20_mcu_ie:1;
+        /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio20_mcu_drv:2;
+        /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio20_fun_wpd:1;
+        /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio20_fun_wpu:1;
+        /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio20_fun_ie:1;
+        /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio20_fun_drv:2;
+        /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio20_mcu_sel:3;
+        /** gpio20_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio20_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio20_reg_t;
+
+/** Type of gpio21 register
+ *  iomux control register for gpio21
+ */
+typedef union {
+    struct {
+        /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio21_mcu_oe:1;
+        /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio21_slp_sel:1;
+        /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio21_mcu_wpd:1;
+        /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio21_mcu_wpu:1;
+        /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio21_mcu_ie:1;
+        /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio21_mcu_drv:2;
+        /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio21_fun_wpd:1;
+        /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio21_fun_wpu:1;
+        /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio21_fun_ie:1;
+        /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio21_fun_drv:2;
+        /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio21_mcu_sel:3;
+        /** gpio21_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio21_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio21_reg_t;
+
+/** Type of gpio22 register
+ *  iomux control register for gpio22
+ */
+typedef union {
+    struct {
+        /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio22_mcu_oe:1;
+        /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio22_slp_sel:1;
+        /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio22_mcu_wpd:1;
+        /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio22_mcu_wpu:1;
+        /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio22_mcu_ie:1;
+        /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio22_mcu_drv:2;
+        /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio22_fun_wpd:1;
+        /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio22_fun_wpu:1;
+        /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio22_fun_ie:1;
+        /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio22_fun_drv:2;
+        /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio22_mcu_sel:3;
+        /** gpio22_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio22_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio22_reg_t;
+
+/** Type of gpio23 register
+ *  iomux control register for gpio23
+ */
+typedef union {
+    struct {
+        /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio23_mcu_oe:1;
+        /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio23_slp_sel:1;
+        /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio23_mcu_wpd:1;
+        /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio23_mcu_wpu:1;
+        /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio23_mcu_ie:1;
+        /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio23_mcu_drv:2;
+        /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio23_fun_wpd:1;
+        /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio23_fun_wpu:1;
+        /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio23_fun_ie:1;
+        /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio23_fun_drv:2;
+        /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio23_mcu_sel:3;
+        /** gpio23_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio23_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio23_reg_t;
+
+/** Type of gpio24 register
+ *  iomux control register for gpio24
+ */
+typedef union {
+    struct {
+        /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio24_mcu_oe:1;
+        /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio24_slp_sel:1;
+        /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio24_mcu_wpd:1;
+        /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio24_mcu_wpu:1;
+        /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio24_mcu_ie:1;
+        /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio24_mcu_drv:2;
+        /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio24_fun_wpd:1;
+        /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio24_fun_wpu:1;
+        /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio24_fun_ie:1;
+        /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio24_fun_drv:2;
+        /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio24_mcu_sel:3;
+        /** gpio24_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio24_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio24_reg_t;
+
+/** Type of gpio25 register
+ *  iomux control register for gpio25
+ */
+typedef union {
+    struct {
+        /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio25_mcu_oe:1;
+        /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio25_slp_sel:1;
+        /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio25_mcu_wpd:1;
+        /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio25_mcu_wpu:1;
+        /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio25_mcu_ie:1;
+        /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio25_mcu_drv:2;
+        /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio25_fun_wpd:1;
+        /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio25_fun_wpu:1;
+        /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio25_fun_ie:1;
+        /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio25_fun_drv:2;
+        /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio25_mcu_sel:3;
+        /** gpio25_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio25_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio25_reg_t;
+
+/** Type of gpio26 register
+ *  iomux control register for gpio26
+ */
+typedef union {
+    struct {
+        /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio26_mcu_oe:1;
+        /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio26_slp_sel:1;
+        /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio26_mcu_wpd:1;
+        /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio26_mcu_wpu:1;
+        /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio26_mcu_ie:1;
+        /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio26_mcu_drv:2;
+        /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio26_fun_wpd:1;
+        /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio26_fun_wpu:1;
+        /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio26_fun_ie:1;
+        /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio26_fun_drv:2;
+        /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio26_mcu_sel:3;
+        /** gpio26_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio26_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio26_reg_t;
+
+/** Type of gpio27 register
+ *  iomux control register for gpio27
+ */
+typedef union {
+    struct {
+        /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio27_mcu_oe:1;
+        /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio27_slp_sel:1;
+        /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio27_mcu_wpd:1;
+        /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio27_mcu_wpu:1;
+        /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio27_mcu_ie:1;
+        /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio27_mcu_drv:2;
+        /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio27_fun_wpd:1;
+        /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio27_fun_wpu:1;
+        /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio27_fun_ie:1;
+        /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio27_fun_drv:2;
+        /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio27_mcu_sel:3;
+        /** gpio27_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio27_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio27_reg_t;
+
+/** Type of gpio28 register
+ *  iomux control register for gpio28
+ */
+typedef union {
+    struct {
+        /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio28_mcu_oe:1;
+        /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio28_slp_sel:1;
+        /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio28_mcu_wpd:1;
+        /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio28_mcu_wpu:1;
+        /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio28_mcu_ie:1;
+        /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio28_mcu_drv:2;
+        /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio28_fun_wpd:1;
+        /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio28_fun_wpu:1;
+        /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio28_fun_ie:1;
+        /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio28_fun_drv:2;
+        /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio28_mcu_sel:3;
+        /** gpio28_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio28_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio28_reg_t;
+
+/** Type of gpio29 register
+ *  iomux control register for gpio29
+ */
+typedef union {
+    struct {
+        /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio29_mcu_oe:1;
+        /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio29_slp_sel:1;
+        /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio29_mcu_wpd:1;
+        /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio29_mcu_wpu:1;
+        /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio29_mcu_ie:1;
+        /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio29_mcu_drv:2;
+        /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio29_fun_wpd:1;
+        /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio29_fun_wpu:1;
+        /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio29_fun_ie:1;
+        /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio29_fun_drv:2;
+        /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio29_mcu_sel:3;
+        /** gpio29_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio29_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio29_reg_t;
+
+/** Type of gpio30 register
+ *  iomux control register for gpio30
+ */
+typedef union {
+    struct {
+        /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio30_mcu_oe:1;
+        /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio30_slp_sel:1;
+        /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio30_mcu_wpd:1;
+        /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio30_mcu_wpu:1;
+        /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio30_mcu_ie:1;
+        /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio30_mcu_drv:2;
+        /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio30_fun_wpd:1;
+        /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio30_fun_wpu:1;
+        /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio30_fun_ie:1;
+        /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio30_fun_drv:2;
+        /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio30_mcu_sel:3;
+        /** gpio30_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio30_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio30_reg_t;
+
+/** Type of gpio31 register
+ *  iomux control register for gpio31
+ */
+typedef union {
+    struct {
+        /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio31_mcu_oe:1;
+        /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio31_slp_sel:1;
+        /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio31_mcu_wpd:1;
+        /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio31_mcu_wpu:1;
+        /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio31_mcu_ie:1;
+        /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio31_mcu_drv:2;
+        /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio31_fun_wpd:1;
+        /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio31_fun_wpu:1;
+        /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio31_fun_ie:1;
+        /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio31_fun_drv:2;
+        /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio31_mcu_sel:3;
+        /** gpio31_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio31_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio31_reg_t;
+
+/** Type of gpio32 register
+ *  iomux control register for gpio32
+ */
+typedef union {
+    struct {
+        /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio32_mcu_oe:1;
+        /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio32_slp_sel:1;
+        /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio32_mcu_wpd:1;
+        /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio32_mcu_wpu:1;
+        /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio32_mcu_ie:1;
+        /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio32_mcu_drv:2;
+        /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio32_fun_wpd:1;
+        /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio32_fun_wpu:1;
+        /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio32_fun_ie:1;
+        /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio32_fun_drv:2;
+        /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio32_mcu_sel:3;
+        /** gpio32_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio32_filter_en:1;
+        /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t gpio32_rue_i3c:1;
+        /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0;
+         *  NA
+         */
+        uint32_t gpio32_ru_i3c:2;
+        /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t gpio32_rue_sel_i3c:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} io_mux_gpio32_reg_t;
+
+/** Type of gpio33 register
+ *  iomux control register for gpio33
+ */
+typedef union {
+    struct {
+        /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio33_mcu_oe:1;
+        /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio33_slp_sel:1;
+        /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio33_mcu_wpd:1;
+        /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio33_mcu_wpu:1;
+        /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio33_mcu_ie:1;
+        /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio33_mcu_drv:2;
+        /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio33_fun_wpd:1;
+        /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio33_fun_wpu:1;
+        /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio33_fun_ie:1;
+        /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio33_fun_drv:2;
+        /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio33_mcu_sel:3;
+        /** gpio33_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio33_filter_en:1;
+        /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t gpio33_rue_i3c:1;
+        /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0;
+         *  NA
+         */
+        uint32_t gpio33_ru_i3c:2;
+        /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t gpio33_rue_sel_i3c:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} io_mux_gpio33_reg_t;
+
+/** Type of gpio34 register
+ *  iomux control register for gpio34
+ */
+typedef union {
+    struct {
+        /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio34_mcu_oe:1;
+        /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio34_slp_sel:1;
+        /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio34_mcu_wpd:1;
+        /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio34_mcu_wpu:1;
+        /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio34_mcu_ie:1;
+        /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio34_mcu_drv:2;
+        /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio34_fun_wpd:1;
+        /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio34_fun_wpu:1;
+        /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio34_fun_ie:1;
+        /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio34_fun_drv:2;
+        /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio34_mcu_sel:3;
+        /** gpio34_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio34_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio34_reg_t;
+
+/** Type of gpio35 register
+ *  iomux control register for gpio35
+ */
+typedef union {
+    struct {
+        /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio35_mcu_oe:1;
+        /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio35_slp_sel:1;
+        /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio35_mcu_wpd:1;
+        /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio35_mcu_wpu:1;
+        /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio35_mcu_ie:1;
+        /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio35_mcu_drv:2;
+        /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio35_fun_wpd:1;
+        /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio35_fun_wpu:1;
+        /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio35_fun_ie:1;
+        /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio35_fun_drv:2;
+        /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio35_mcu_sel:3;
+        /** gpio35_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio35_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio35_reg_t;
+
+/** Type of gpio36 register
+ *  iomux control register for gpio36
+ */
+typedef union {
+    struct {
+        /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio36_mcu_oe:1;
+        /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio36_slp_sel:1;
+        /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio36_mcu_wpd:1;
+        /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio36_mcu_wpu:1;
+        /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio36_mcu_ie:1;
+        /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio36_mcu_drv:2;
+        /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio36_fun_wpd:1;
+        /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio36_fun_wpu:1;
+        /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio36_fun_ie:1;
+        /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio36_fun_drv:2;
+        /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio36_mcu_sel:3;
+        /** gpio36_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio36_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio36_reg_t;
+
+/** Type of gpio37 register
+ *  iomux control register for gpio37
+ */
+typedef union {
+    struct {
+        /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio37_mcu_oe:1;
+        /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio37_slp_sel:1;
+        /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio37_mcu_wpd:1;
+        /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio37_mcu_wpu:1;
+        /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio37_mcu_ie:1;
+        /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio37_mcu_drv:2;
+        /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio37_fun_wpd:1;
+        /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio37_fun_wpu:1;
+        /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio37_fun_ie:1;
+        /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio37_fun_drv:2;
+        /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio37_mcu_sel:3;
+        /** gpio37_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio37_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio37_reg_t;
+
+/** Type of gpio38 register
+ *  iomux control register for gpio38
+ */
+typedef union {
+    struct {
+        /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio38_mcu_oe:1;
+        /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio38_slp_sel:1;
+        /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio38_mcu_wpd:1;
+        /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio38_mcu_wpu:1;
+        /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio38_mcu_ie:1;
+        /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio38_mcu_drv:2;
+        /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio38_fun_wpd:1;
+        /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio38_fun_wpu:1;
+        /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio38_fun_ie:1;
+        /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio38_fun_drv:2;
+        /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio38_mcu_sel:3;
+        /** gpio38_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio38_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio38_reg_t;
+
+/** Type of gpio39 register
+ *  iomux control register for gpio39
+ */
+typedef union {
+    struct {
+        /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio39_mcu_oe:1;
+        /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio39_slp_sel:1;
+        /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio39_mcu_wpd:1;
+        /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio39_mcu_wpu:1;
+        /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio39_mcu_ie:1;
+        /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio39_mcu_drv:2;
+        /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio39_fun_wpd:1;
+        /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio39_fun_wpu:1;
+        /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio39_fun_ie:1;
+        /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio39_fun_drv:2;
+        /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio39_mcu_sel:3;
+        /** gpio39_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio39_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio39_reg_t;
+
+/** Type of gpio40 register
+ *  iomux control register for gpio40
+ */
+typedef union {
+    struct {
+        /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio40_mcu_oe:1;
+        /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio40_slp_sel:1;
+        /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio40_mcu_wpd:1;
+        /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio40_mcu_wpu:1;
+        /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio40_mcu_ie:1;
+        /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio40_mcu_drv:2;
+        /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio40_fun_wpd:1;
+        /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio40_fun_wpu:1;
+        /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio40_fun_ie:1;
+        /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio40_fun_drv:2;
+        /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio40_mcu_sel:3;
+        /** gpio40_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio40_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio40_reg_t;
+
+/** Type of gpio41 register
+ *  iomux control register for gpio41
+ */
+typedef union {
+    struct {
+        /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio41_mcu_oe:1;
+        /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio41_slp_sel:1;
+        /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio41_mcu_wpd:1;
+        /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio41_mcu_wpu:1;
+        /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio41_mcu_ie:1;
+        /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio41_mcu_drv:2;
+        /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio41_fun_wpd:1;
+        /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio41_fun_wpu:1;
+        /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio41_fun_ie:1;
+        /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio41_fun_drv:2;
+        /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio41_mcu_sel:3;
+        /** gpio41_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio41_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio41_reg_t;
+
+/** Type of gpio42 register
+ *  iomux control register for gpio42
+ */
+typedef union {
+    struct {
+        /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio42_mcu_oe:1;
+        /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio42_slp_sel:1;
+        /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio42_mcu_wpd:1;
+        /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio42_mcu_wpu:1;
+        /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio42_mcu_ie:1;
+        /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio42_mcu_drv:2;
+        /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio42_fun_wpd:1;
+        /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio42_fun_wpu:1;
+        /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio42_fun_ie:1;
+        /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio42_fun_drv:2;
+        /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio42_mcu_sel:3;
+        /** gpio42_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio42_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio42_reg_t;
+
+/** Type of gpio43 register
+ *  iomux control register for gpio43
+ */
+typedef union {
+    struct {
+        /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio43_mcu_oe:1;
+        /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio43_slp_sel:1;
+        /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio43_mcu_wpd:1;
+        /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio43_mcu_wpu:1;
+        /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio43_mcu_ie:1;
+        /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio43_mcu_drv:2;
+        /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio43_fun_wpd:1;
+        /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio43_fun_wpu:1;
+        /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio43_fun_ie:1;
+        /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio43_fun_drv:2;
+        /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio43_mcu_sel:3;
+        /** gpio43_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio43_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio43_reg_t;
+
+/** Type of gpio44 register
+ *  iomux control register for gpio44
+ */
+typedef union {
+    struct {
+        /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio44_mcu_oe:1;
+        /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio44_slp_sel:1;
+        /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio44_mcu_wpd:1;
+        /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio44_mcu_wpu:1;
+        /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio44_mcu_ie:1;
+        /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio44_mcu_drv:2;
+        /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio44_fun_wpd:1;
+        /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio44_fun_wpu:1;
+        /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio44_fun_ie:1;
+        /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio44_fun_drv:2;
+        /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio44_mcu_sel:3;
+        /** gpio44_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio44_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio44_reg_t;
+
+/** Type of gpio45 register
+ *  iomux control register for gpio45
+ */
+typedef union {
+    struct {
+        /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio45_mcu_oe:1;
+        /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio45_slp_sel:1;
+        /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio45_mcu_wpd:1;
+        /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio45_mcu_wpu:1;
+        /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio45_mcu_ie:1;
+        /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio45_mcu_drv:2;
+        /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio45_fun_wpd:1;
+        /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio45_fun_wpu:1;
+        /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio45_fun_ie:1;
+        /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio45_fun_drv:2;
+        /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio45_mcu_sel:3;
+        /** gpio45_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio45_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio45_reg_t;
+
+/** Type of gpio46 register
+ *  iomux control register for gpio46
+ */
+typedef union {
+    struct {
+        /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio46_mcu_oe:1;
+        /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio46_slp_sel:1;
+        /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio46_mcu_wpd:1;
+        /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio46_mcu_wpu:1;
+        /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio46_mcu_ie:1;
+        /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio46_mcu_drv:2;
+        /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio46_fun_wpd:1;
+        /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio46_fun_wpu:1;
+        /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio46_fun_ie:1;
+        /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio46_fun_drv:2;
+        /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio46_mcu_sel:3;
+        /** gpio46_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio46_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio46_reg_t;
+
+/** Type of gpio47 register
+ *  iomux control register for gpio47
+ */
+typedef union {
+    struct {
+        /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio47_mcu_oe:1;
+        /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio47_slp_sel:1;
+        /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio47_mcu_wpd:1;
+        /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio47_mcu_wpu:1;
+        /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio47_mcu_ie:1;
+        /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio47_mcu_drv:2;
+        /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio47_fun_wpd:1;
+        /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio47_fun_wpu:1;
+        /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio47_fun_ie:1;
+        /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio47_fun_drv:2;
+        /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio47_mcu_sel:3;
+        /** gpio47_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio47_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio47_reg_t;
+
+/** Type of gpio48 register
+ *  iomux control register for gpio48
+ */
+typedef union {
+    struct {
+        /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio48_mcu_oe:1;
+        /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio48_slp_sel:1;
+        /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio48_mcu_wpd:1;
+        /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio48_mcu_wpu:1;
+        /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio48_mcu_ie:1;
+        /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio48_mcu_drv:2;
+        /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio48_fun_wpd:1;
+        /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio48_fun_wpu:1;
+        /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio48_fun_ie:1;
+        /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio48_fun_drv:2;
+        /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio48_mcu_sel:3;
+        /** gpio48_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio48_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio48_reg_t;
+
+/** Type of gpio49 register
+ *  iomux control register for gpio49
+ */
+typedef union {
+    struct {
+        /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio49_mcu_oe:1;
+        /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio49_slp_sel:1;
+        /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio49_mcu_wpd:1;
+        /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio49_mcu_wpu:1;
+        /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio49_mcu_ie:1;
+        /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio49_mcu_drv:2;
+        /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio49_fun_wpd:1;
+        /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio49_fun_wpu:1;
+        /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio49_fun_ie:1;
+        /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio49_fun_drv:2;
+        /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio49_mcu_sel:3;
+        /** gpio49_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio49_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio49_reg_t;
+
+/** Type of gpio50 register
+ *  iomux control register for gpio50
+ */
+typedef union {
+    struct {
+        /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio50_mcu_oe:1;
+        /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio50_slp_sel:1;
+        /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio50_mcu_wpd:1;
+        /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio50_mcu_wpu:1;
+        /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio50_mcu_ie:1;
+        /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio50_mcu_drv:2;
+        /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio50_fun_wpd:1;
+        /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio50_fun_wpu:1;
+        /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio50_fun_ie:1;
+        /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio50_fun_drv:2;
+        /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio50_mcu_sel:3;
+        /** gpio50_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio50_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio50_reg_t;
+
+/** Type of gpio51 register
+ *  iomux control register for gpio51
+ */
+typedef union {
+    struct {
+        /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio51_mcu_oe:1;
+        /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio51_slp_sel:1;
+        /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio51_mcu_wpd:1;
+        /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio51_mcu_wpu:1;
+        /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio51_mcu_ie:1;
+        /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio51_mcu_drv:2;
+        /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio51_fun_wpd:1;
+        /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio51_fun_wpu:1;
+        /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio51_fun_ie:1;
+        /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio51_fun_drv:2;
+        /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio51_mcu_sel:3;
+        /** gpio51_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio51_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio51_reg_t;
+
+/** Type of gpio52 register
+ *  iomux control register for gpio52
+ */
+typedef union {
+    struct {
+        /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio52_mcu_oe:1;
+        /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio52_slp_sel:1;
+        /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio52_mcu_wpd:1;
+        /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio52_mcu_wpu:1;
+        /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio52_mcu_ie:1;
+        /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio52_mcu_drv:2;
+        /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio52_fun_wpd:1;
+        /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio52_fun_wpu:1;
+        /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio52_fun_ie:1;
+        /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio52_fun_drv:2;
+        /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio52_mcu_sel:3;
+        /** gpio52_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio52_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio52_reg_t;
+
+/** Type of gpio53 register
+ *  iomux control register for gpio53
+ */
+typedef union {
+    struct {
+        /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio53_mcu_oe:1;
+        /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio53_slp_sel:1;
+        /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio53_mcu_wpd:1;
+        /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio53_mcu_wpu:1;
+        /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio53_mcu_ie:1;
+        /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio53_mcu_drv:2;
+        /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio53_fun_wpd:1;
+        /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio53_fun_wpu:1;
+        /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio53_fun_ie:1;
+        /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio53_fun_drv:2;
+        /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio53_mcu_sel:3;
+        /** gpio53_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio53_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio53_reg_t;
+
+/** Type of gpio54 register
+ *  iomux control register for gpio54
+ */
+typedef union {
+    struct {
+        /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio54_mcu_oe:1;
+        /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio54_slp_sel:1;
+        /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio54_mcu_wpd:1;
+        /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio54_mcu_wpu:1;
+        /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio54_mcu_ie:1;
+        /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio54_mcu_drv:2;
+        /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio54_fun_wpd:1;
+        /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio54_fun_wpu:1;
+        /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio54_fun_ie:1;
+        /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio54_fun_drv:2;
+        /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio54_mcu_sel:3;
+        /** gpio54_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio54_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio54_reg_t;
+
+/** Type of gpio55 register
+ *  iomux control register for gpio55
+ */
+typedef union {
+    struct {
+        /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio55_mcu_oe:1;
+        /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio55_slp_sel:1;
+        /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio55_mcu_wpd:1;
+        /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio55_mcu_wpu:1;
+        /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio55_mcu_ie:1;
+        /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio55_mcu_drv:2;
+        /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio55_fun_wpd:1;
+        /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio55_fun_wpu:1;
+        /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio55_fun_ie:1;
+        /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio55_fun_drv:2;
+        /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio55_mcu_sel:3;
+        /** gpio55_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio55_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio55_reg_t;
+
+/** Type of gpio56 register
+ *  iomux control register for gpio56
+ */
+typedef union {
+    struct {
+        /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio56_mcu_oe:1;
+        /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio56_slp_sel:1;
+        /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio56_mcu_wpd:1;
+        /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio56_mcu_wpu:1;
+        /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio56_mcu_ie:1;
+        /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strenth on sleep mode
+         */
+        uint32_t gpio56_mcu_drv:2;
+        /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio56_fun_wpd:1;
+        /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio56_fun_wpu:1;
+        /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio56_fun_ie:1;
+        /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio56_fun_drv:2;
+        /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio56_mcu_sel:3;
+        /** gpio56_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio56_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio56_reg_t;
+
+/** Type of date register
+ *  iomux version
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2101794;
+         *  csv date
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} io_mux_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile io_mux_gpio0_reg_t gpio0;
+    volatile io_mux_gpio1_reg_t gpio1;
+    volatile io_mux_gpio2_reg_t gpio2;
+    volatile io_mux_gpio3_reg_t gpio3;
+    volatile io_mux_gpio4_reg_t gpio4;
+    volatile io_mux_gpio5_reg_t gpio5;
+    volatile io_mux_gpio6_reg_t gpio6;
+    volatile io_mux_gpio7_reg_t gpio7;
+    volatile io_mux_gpio8_reg_t gpio8;
+    volatile io_mux_gpio9_reg_t gpio9;
+    volatile io_mux_gpio10_reg_t gpio10;
+    volatile io_mux_gpio11_reg_t gpio11;
+    volatile io_mux_gpio12_reg_t gpio12;
+    volatile io_mux_gpio13_reg_t gpio13;
+    volatile io_mux_gpio14_reg_t gpio14;
+    volatile io_mux_gpio15_reg_t gpio15;
+    volatile io_mux_gpio16_reg_t gpio16;
+    volatile io_mux_gpio17_reg_t gpio17;
+    volatile io_mux_gpio18_reg_t gpio18;
+    volatile io_mux_gpio19_reg_t gpio19;
+    volatile io_mux_gpio20_reg_t gpio20;
+    volatile io_mux_gpio21_reg_t gpio21;
+    volatile io_mux_gpio22_reg_t gpio22;
+    volatile io_mux_gpio23_reg_t gpio23;
+    volatile io_mux_gpio24_reg_t gpio24;
+    volatile io_mux_gpio25_reg_t gpio25;
+    volatile io_mux_gpio26_reg_t gpio26;
+    volatile io_mux_gpio27_reg_t gpio27;
+    volatile io_mux_gpio28_reg_t gpio28;
+    volatile io_mux_gpio29_reg_t gpio29;
+    volatile io_mux_gpio30_reg_t gpio30;
+    volatile io_mux_gpio31_reg_t gpio31;
+    volatile io_mux_gpio32_reg_t gpio32;
+    volatile io_mux_gpio33_reg_t gpio33;
+    volatile io_mux_gpio34_reg_t gpio34;
+    volatile io_mux_gpio35_reg_t gpio35;
+    volatile io_mux_gpio36_reg_t gpio36;
+    volatile io_mux_gpio37_reg_t gpio37;
+    volatile io_mux_gpio38_reg_t gpio38;
+    volatile io_mux_gpio39_reg_t gpio39;
+    volatile io_mux_gpio40_reg_t gpio40;
+    volatile io_mux_gpio41_reg_t gpio41;
+    volatile io_mux_gpio42_reg_t gpio42;
+    volatile io_mux_gpio43_reg_t gpio43;
+    volatile io_mux_gpio44_reg_t gpio44;
+    volatile io_mux_gpio45_reg_t gpio45;
+    volatile io_mux_gpio46_reg_t gpio46;
+    volatile io_mux_gpio47_reg_t gpio47;
+    volatile io_mux_gpio48_reg_t gpio48;
+    volatile io_mux_gpio49_reg_t gpio49;
+    volatile io_mux_gpio50_reg_t gpio50;
+    volatile io_mux_gpio51_reg_t gpio51;
+    volatile io_mux_gpio52_reg_t gpio52;
+    volatile io_mux_gpio53_reg_t gpio53;
+    volatile io_mux_gpio54_reg_t gpio54;
+    volatile io_mux_gpio55_reg_t gpio55;
+    volatile io_mux_gpio56_reg_t gpio56;
+    uint32_t reserved_0e8[7];
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lcd_cam_reg.h b/components/soc/esp32p4/include/soc/lcd_cam_reg.h
new file mode 100644
index 0000000000..715dc51396
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lcd_cam_reg.h
@@ -0,0 +1,962 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_LCD_CAM_REG_H_
+#define _SOC_LCD_CAM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define LCD_CAM_LCD_CLOCK_REG          (DR_REG_LCD_CAM_BASE + 0x0)
+/* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate.*/
+#define LCD_CAM_CLK_EN    (BIT(31))
+#define LCD_CAM_CLK_EN_M  (BIT(31))
+#define LCD_CAM_CLK_EN_V  0x1
+#define LCD_CAM_CLK_EN_S  31
+/* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
+/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
+#define LCD_CAM_LCD_CLK_SEL    0x00000003
+#define LCD_CAM_LCD_CLK_SEL_M  ((LCD_CAM_LCD_CLK_SEL_V)<<(LCD_CAM_LCD_CLK_SEL_S))
+#define LCD_CAM_LCD_CLK_SEL_V  0x3
+#define LCD_CAM_LCD_CLK_SEL_S  29
+/* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
+/*description: Fractional clock divider denominator value.*/
+#define LCD_CAM_LCD_CLKM_DIV_A    0x0000003F
+#define LCD_CAM_LCD_CLKM_DIV_A_M  ((LCD_CAM_LCD_CLKM_DIV_A_V)<<(LCD_CAM_LCD_CLKM_DIV_A_S))
+#define LCD_CAM_LCD_CLKM_DIV_A_V  0x3F
+#define LCD_CAM_LCD_CLKM_DIV_A_S  23
+/* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
+/*description: Fractional clock divider numerator value.*/
+#define LCD_CAM_LCD_CLKM_DIV_B    0x0000003F
+#define LCD_CAM_LCD_CLKM_DIV_B_M  ((LCD_CAM_LCD_CLKM_DIV_B_V)<<(LCD_CAM_LCD_CLKM_DIV_B_S))
+#define LCD_CAM_LCD_CLKM_DIV_B_V  0x3F
+#define LCD_CAM_LCD_CLKM_DIV_B_S  17
+/* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
+/*description: Integral LCD clock divider value.*/
+#define LCD_CAM_LCD_CLKM_DIV_NUM    0x000000FF
+#define LCD_CAM_LCD_CLKM_DIV_NUM_M  ((LCD_CAM_LCD_CLKM_DIV_NUM_V)<<(LCD_CAM_LCD_CLKM_DIV_NUM_S))
+#define LCD_CAM_LCD_CLKM_DIV_NUM_V  0xFF
+#define LCD_CAM_LCD_CLKM_DIV_NUM_S  9
+/* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: 1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is l
+ow in the second half data cycle..*/
+#define LCD_CAM_LCD_CK_OUT_EDGE    (BIT(8))
+#define LCD_CAM_LCD_CK_OUT_EDGE_M  (BIT(8))
+#define LCD_CAM_LCD_CK_OUT_EDGE_V  0x1
+#define LCD_CAM_LCD_CK_OUT_EDGE_S  8
+/* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle..*/
+#define LCD_CAM_LCD_CK_IDLE_EDGE    (BIT(7))
+#define LCD_CAM_LCD_CK_IDLE_EDGE_M  (BIT(7))
+#define LCD_CAM_LCD_CK_IDLE_EDGE_V  0x1
+#define LCD_CAM_LCD_CK_IDLE_EDGE_S  7
+/* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */
+/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)..*/
+#define LCD_CAM_LCD_CLK_EQU_SYSCLK    (BIT(6))
+#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M  (BIT(6))
+#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V  0x1
+#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S  6
+/* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0..*/
+#define LCD_CAM_LCD_CLKCNT_N    0x0000003F
+#define LCD_CAM_LCD_CLKCNT_N_M  ((LCD_CAM_LCD_CLKCNT_N_V)<<(LCD_CAM_LCD_CLKCNT_N_S))
+#define LCD_CAM_LCD_CLKCNT_N_V  0x3F
+#define LCD_CAM_LCD_CLKCNT_N_S  0
+
+#define LCD_CAM_CAM_CTRL_REG          (DR_REG_LCD_CAM_BASE + 0x4)
+/* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
+/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
+#define LCD_CAM_CAM_CLK_SEL    0x00000003
+#define LCD_CAM_CAM_CLK_SEL_M  ((LCD_CAM_CAM_CLK_SEL_V)<<(LCD_CAM_CAM_CLK_SEL_S))
+#define LCD_CAM_CAM_CLK_SEL_V  0x3
+#define LCD_CAM_CAM_CLK_SEL_S  29
+/* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
+/*description: Fractional clock divider denominator value.*/
+#define LCD_CAM_CAM_CLKM_DIV_A    0x0000003F
+#define LCD_CAM_CAM_CLKM_DIV_A_M  ((LCD_CAM_CAM_CLKM_DIV_A_V)<<(LCD_CAM_CAM_CLKM_DIV_A_S))
+#define LCD_CAM_CAM_CLKM_DIV_A_V  0x3F
+#define LCD_CAM_CAM_CLKM_DIV_A_S  23
+/* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
+/*description: Fractional clock divider numerator value.*/
+#define LCD_CAM_CAM_CLKM_DIV_B    0x0000003F
+#define LCD_CAM_CAM_CLKM_DIV_B_M  ((LCD_CAM_CAM_CLKM_DIV_B_V)<<(LCD_CAM_CAM_CLKM_DIV_B_S))
+#define LCD_CAM_CAM_CLKM_DIV_B_V  0x3F
+#define LCD_CAM_CAM_CLKM_DIV_B_S  17
+/* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
+/*description: Integral Camera clock divider value.*/
+#define LCD_CAM_CAM_CLKM_DIV_NUM    0x000000FF
+#define LCD_CAM_CAM_CLKM_DIV_NUM_M  ((LCD_CAM_CAM_CLKM_DIV_NUM_V)<<(LCD_CAM_CAM_CLKM_DIV_NUM_S))
+#define LCD_CAM_CAM_CLKM_DIV_NUM_V  0xFF
+#define LCD_CAM_CAM_CLKM_DIV_NUM_S  9
+/* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_
+data_cyclelen..*/
+#define LCD_CAM_CAM_VS_EOF_EN    (BIT(8))
+#define LCD_CAM_CAM_VS_EOF_EN_M  (BIT(8))
+#define LCD_CAM_CAM_VS_EOF_EN_V  0x1
+#define LCD_CAM_CAM_VS_EOF_EN_S  8
+/* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: 1: Enable to generate CAM_HS_INT. 0: Disable..*/
+#define LCD_CAM_CAM_LINE_INT_EN    (BIT(7))
+#define LCD_CAM_CAM_LINE_INT_EN_M  (BIT(7))
+#define LCD_CAM_CAM_LINE_INT_EN_V  0x1
+#define LCD_CAM_CAM_LINE_INT_EN_S  7
+/* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
+#define LCD_CAM_CAM_BIT_ORDER    (BIT(6))
+#define LCD_CAM_CAM_BIT_ORDER_M  (BIT(6))
+#define LCD_CAM_CAM_BIT_ORDER_V  0x1
+#define LCD_CAM_CAM_BIT_ORDER_S  6
+/* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byt
+e mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change..*/
+#define LCD_CAM_CAM_BYTE_ORDER    (BIT(5))
+#define LCD_CAM_CAM_BYTE_ORDER_M  (BIT(5))
+#define LCD_CAM_CAM_BYTE_ORDER_V  0x1
+#define LCD_CAM_CAM_BYTE_ORDER_S  5
+/* LCD_CAM_CAM_UPDATE_REG : R/W/SC ;bitpos:[4] ;default: 1'h0 ; */
+/*description: 1: Update Camera registers, will be cleared by hardware. 0 : Not care..*/
+#define LCD_CAM_CAM_UPDATE_REG    (BIT(4))
+#define LCD_CAM_CAM_UPDATE_REG_M  (BIT(4))
+#define LCD_CAM_CAM_UPDATE_REG_V  0x1
+#define LCD_CAM_CAM_UPDATE_REG_S  4
+/* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */
+/*description: Filter threshold value for CAM_VSYNC signal..*/
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES    0x00000007
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M  ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V)<<(LCD_CAM_CAM_VSYNC_FILTER_THRES_S))
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V  0x7
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S  1
+/* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop
+..*/
+#define LCD_CAM_CAM_STOP_EN    (BIT(0))
+#define LCD_CAM_CAM_STOP_EN_M  (BIT(0))
+#define LCD_CAM_CAM_STOP_EN_V  0x1
+#define LCD_CAM_CAM_STOP_EN_S  0
+
+#define LCD_CAM_CAM_CTRL1_REG          (DR_REG_LCD_CAM_BASE + 0x8)
+/* LCD_CAM_CAM_AFIFO_RESET : WT ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Camera AFIFO reset signal..*/
+#define LCD_CAM_CAM_AFIFO_RESET    (BIT(31))
+#define LCD_CAM_CAM_AFIFO_RESET_M  (BIT(31))
+#define LCD_CAM_CAM_AFIFO_RESET_V  0x1
+#define LCD_CAM_CAM_AFIFO_RESET_S  31
+/* LCD_CAM_CAM_RESET : WT ;bitpos:[30] ;default: 1'h0 ; */
+/*description: Camera module reset signal..*/
+#define LCD_CAM_CAM_RESET    (BIT(30))
+#define LCD_CAM_CAM_RESET_M  (BIT(30))
+#define LCD_CAM_CAM_RESET_V  0x1
+#define LCD_CAM_CAM_RESET_S  30
+/* LCD_CAM_CAM_START : R/W/SC ;bitpos:[29] ;default: 1'h0 ; */
+/*description: Camera module start signal..*/
+#define LCD_CAM_CAM_START    (BIT(29))
+#define LCD_CAM_CAM_START_M  (BIT(29))
+#define LCD_CAM_CAM_START_V  0x1
+#define LCD_CAM_CAM_START_S  29
+/* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
+/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control si
+gnals are CAM_DE and CAM_VSYNC..*/
+#define LCD_CAM_CAM_VH_DE_MODE_EN    (BIT(28))
+#define LCD_CAM_CAM_VH_DE_MODE_EN_M  (BIT(28))
+#define LCD_CAM_CAM_VH_DE_MODE_EN_V  0x1
+#define LCD_CAM_CAM_VH_DE_MODE_EN_S  28
+/* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */
+/*description: CAM_VSYNC invert enable signal, valid in high level..*/
+#define LCD_CAM_CAM_VSYNC_INV    (BIT(27))
+#define LCD_CAM_CAM_VSYNC_INV_M  (BIT(27))
+#define LCD_CAM_CAM_VSYNC_INV_V  0x1
+#define LCD_CAM_CAM_VSYNC_INV_S  27
+/* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: CAM_HSYNC invert enable signal, valid in high level..*/
+#define LCD_CAM_CAM_HSYNC_INV    (BIT(26))
+#define LCD_CAM_CAM_HSYNC_INV_M  (BIT(26))
+#define LCD_CAM_CAM_HSYNC_INV_V  0x1
+#define LCD_CAM_CAM_HSYNC_INV_S  26
+/* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: CAM_DE invert enable signal, valid in high level..*/
+#define LCD_CAM_CAM_DE_INV    (BIT(25))
+#define LCD_CAM_CAM_DE_INV_M  (BIT(25))
+#define LCD_CAM_CAM_DE_INV_V  0x1
+#define LCD_CAM_CAM_DE_INV_S  25
+/* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: 1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8
+..*/
+#define LCD_CAM_CAM_2BYTE_EN    (BIT(24))
+#define LCD_CAM_CAM_2BYTE_EN_M  (BIT(24))
+#define LCD_CAM_CAM_2BYTE_EN_V  0x1
+#define LCD_CAM_CAM_2BYTE_EN_S  24
+/* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: 1: Enable CAM_VSYNC filter function. 0: bypass..*/
+#define LCD_CAM_CAM_VSYNC_FILTER_EN    (BIT(23))
+#define LCD_CAM_CAM_VSYNC_FILTER_EN_M  (BIT(23))
+#define LCD_CAM_CAM_VSYNC_FILTER_EN_V  0x1
+#define LCD_CAM_CAM_VSYNC_FILTER_EN_S  23
+/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Invert  the input signal CAM_PCLK. 0: Not invert..*/
+#define LCD_CAM_CAM_CLK_INV    (BIT(22))
+#define LCD_CAM_CAM_CLK_INV_M  (BIT(22))
+#define LCD_CAM_CAM_CLK_INV_V  0x1
+#define LCD_CAM_CAM_CLK_INV_S  22
+/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[21:16] ;default: 6'h0 ; */
+/*description: The line number minus 1 to generate cam_hs_int..*/
+#define LCD_CAM_CAM_LINE_INT_NUM    0x0000003F
+#define LCD_CAM_CAM_LINE_INT_NUM_M  ((LCD_CAM_CAM_LINE_INT_NUM_V)<<(LCD_CAM_CAM_LINE_INT_NUM_S))
+#define LCD_CAM_CAM_LINE_INT_NUM_V  0x3F
+#define LCD_CAM_CAM_LINE_INT_NUM_S  16
+/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int..*/
+#define LCD_CAM_CAM_REC_DATA_BYTELEN    0x0000FFFF
+#define LCD_CAM_CAM_REC_DATA_BYTELEN_M  ((LCD_CAM_CAM_REC_DATA_BYTELEN_V)<<(LCD_CAM_CAM_REC_DATA_BYTELEN_S))
+#define LCD_CAM_CAM_REC_DATA_BYTELEN_V  0xFFFF
+#define LCD_CAM_CAM_REC_DATA_BYTELEN_S  0
+
+#define LCD_CAM_CAM_RGB_YUV_REG          (DR_REG_LCD_CAM_BASE + 0xC)
+/* LCD_CAM_CAM_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 0: Bypass converter. 1: Enable converter..*/
+#define LCD_CAM_CAM_CONV_ENABLE    (BIT(31))
+#define LCD_CAM_CAM_CONV_ENABLE_M  (BIT(31))
+#define LCD_CAM_CAM_CONV_ENABLE_V  0x1
+#define LCD_CAM_CAM_CONV_ENABLE_S  31
+/* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: YUV to RGB. 1: RGB to YUV..*/
+#define LCD_CAM_CAM_CONV_TRANS_MODE    (BIT(30))
+#define LCD_CAM_CAM_CONV_TRANS_MODE_M  (BIT(30))
+#define LCD_CAM_CAM_CONV_TRANS_MODE_V  0x1
+#define LCD_CAM_CAM_CONV_TRANS_MODE_S  30
+/* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 0: 16bits mode. 1: 8bits mode..*/
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M  (BIT(29))
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V  0x1
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S  29
+/* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE    (BIT(28))
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M  (BIT(28))
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V  0x1
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S  28
+/* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M  (BIT(27))
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V  0x1
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S  27
+/* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 0:BT601. 1:BT709..*/
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M  (BIT(26))
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V  0x1
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S  26
+/* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
+/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+mode of Data_in.*/
+#define LCD_CAM_CAM_CONV_YUV_MODE    0x00000003
+#define LCD_CAM_CAM_CONV_YUV_MODE_M  ((LCD_CAM_CAM_CONV_YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV_MODE_S))
+#define LCD_CAM_CAM_CONV_YUV_MODE_V  0x3
+#define LCD_CAM_CAM_CONV_YUV_MODE_S  24
+/* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
+/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+trans_mode must be set to 1..*/
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE    0x00000003
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M  ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV2YUV_MODE_S))
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V  0x3
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S  22
+/* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1:invert every two 8bits input data. 2. disabled..*/
+#define LCD_CAM_CAM_CONV_8BITS_DATA_INV    (BIT(21))
+#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M  (BIT(21))
+#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V  0x1
+#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S  21
+
+#define LCD_CAM_LCD_RGB_YUV_REG          (DR_REG_LCD_CAM_BASE + 0x10)
+/* LCD_CAM_LCD_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 0: Bypass converter. 1: Enable converter..*/
+#define LCD_CAM_LCD_CONV_ENABLE    (BIT(31))
+#define LCD_CAM_LCD_CONV_ENABLE_M  (BIT(31))
+#define LCD_CAM_LCD_CONV_ENABLE_V  0x1
+#define LCD_CAM_LCD_CONV_ENABLE_S  31
+/* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: YUV to RGB. 1: RGB to YUV..*/
+#define LCD_CAM_LCD_CONV_TRANS_MODE    (BIT(30))
+#define LCD_CAM_LCD_CONV_TRANS_MODE_M  (BIT(30))
+#define LCD_CAM_LCD_CONV_TRANS_MODE_V  0x1
+#define LCD_CAM_LCD_CONV_TRANS_MODE_S  30
+/* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 0: 16bits mode. 1: 8bits mode..*/
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M  (BIT(29))
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V  0x1
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S  29
+/* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE    (BIT(28))
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M  (BIT(28))
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V  0x1
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S  28
+/* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M  (BIT(27))
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V  0x1
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S  27
+/* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 0:BT601. 1:BT709..*/
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M  (BIT(26))
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V  0x1
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S  26
+/* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
+/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+mode of Data_in.*/
+#define LCD_CAM_LCD_CONV_YUV_MODE    0x00000003
+#define LCD_CAM_LCD_CONV_YUV_MODE_M  ((LCD_CAM_LCD_CONV_YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV_MODE_S))
+#define LCD_CAM_LCD_CONV_YUV_MODE_V  0x3
+#define LCD_CAM_LCD_CONV_YUV_MODE_S  24
+/* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
+/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+trans_mode must be set to 1..*/
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE    0x00000003
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M  ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV2YUV_MODE_S))
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V  0x3
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S  22
+/* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 0: txtorx mode off. 1: txtorx mode on..*/
+#define LCD_CAM_LCD_CONV_TXTORX    (BIT(21))
+#define LCD_CAM_LCD_CONV_TXTORX_M  (BIT(21))
+#define LCD_CAM_LCD_CONV_TXTORX_V  0x1
+#define LCD_CAM_LCD_CONV_TXTORX_S  21
+/* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: 1:invert every two 8bits input data. 2. disabled..*/
+#define LCD_CAM_LCD_CONV_8BITS_DATA_INV    (BIT(20))
+#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M  (BIT(20))
+#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V  0x1
+#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S  20
+
+#define LCD_CAM_LCD_USER_REG          (DR_REG_LCD_CAM_BASE + 0x14)
+/* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: The cycle length of command phase. 1: 2 cycles. 0: 1 cycle..*/
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN    (BIT(31))
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M  (BIT(31))
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V  0x1
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S  31
+/* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
+/*description: The dummy cycle length minus 1..*/
+#define LCD_CAM_LCD_DUMMY_CYCLELEN    0x00000003
+#define LCD_CAM_LCD_DUMMY_CYCLELEN_M  ((LCD_CAM_LCD_DUMMY_CYCLELEN_V)<<(LCD_CAM_LCD_DUMMY_CYCLELEN_S))
+#define LCD_CAM_LCD_DUMMY_CYCLELEN_V  0x3
+#define LCD_CAM_LCD_DUMMY_CYCLELEN_S  29
+/* LCD_CAM_LCD_RESET : WT ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The value of  command..*/
+#define LCD_CAM_LCD_RESET    (BIT(28))
+#define LCD_CAM_LCD_RESET_M  (BIT(28))
+#define LCD_CAM_LCD_RESET_V  0x1
+#define LCD_CAM_LCD_RESET_S  28
+/* LCD_CAM_LCD_START : R/W/SC ;bitpos:[27] ;default: 1'h0 ; */
+/*description: LCD start sending data enable signal, valid in high level..*/
+#define LCD_CAM_LCD_START    (BIT(27))
+#define LCD_CAM_LCD_START_M  (BIT(27))
+#define LCD_CAM_LCD_START_V  0x1
+#define LCD_CAM_LCD_START_S  27
+/* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable..*/
+#define LCD_CAM_LCD_CMD    (BIT(26))
+#define LCD_CAM_LCD_CMD_M  (BIT(26))
+#define LCD_CAM_LCD_CMD_V  0x1
+#define LCD_CAM_LCD_CMD_S  26
+/* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable..*/
+#define LCD_CAM_LCD_DUMMY    (BIT(25))
+#define LCD_CAM_LCD_DUMMY_M  (BIT(25))
+#define LCD_CAM_LCD_DUMMY_V  0x1
+#define LCD_CAM_LCD_DUMMY_S  25
+/* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable..*/
+#define LCD_CAM_LCD_DOUT    (BIT(24))
+#define LCD_CAM_LCD_DOUT_M  (BIT(24))
+#define LCD_CAM_LCD_DOUT_V  0x1
+#define LCD_CAM_LCD_DOUT_S  24
+/* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
+#define LCD_CAM_LCD_BYTE_ORDER    (BIT(23))
+#define LCD_CAM_LCD_BYTE_ORDER_M  (BIT(23))
+#define LCD_CAM_LCD_BYTE_ORDER_V  0x1
+#define LCD_CAM_LCD_BYTE_ORDER_S  23
+/* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one b
+yte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change..*/
+#define LCD_CAM_LCD_BIT_ORDER    (BIT(22))
+#define LCD_CAM_LCD_BIT_ORDER_M  (BIT(22))
+#define LCD_CAM_LCD_BIT_ORDER_V  0x1
+#define LCD_CAM_LCD_BIT_ORDER_S  22
+/* LCD_CAM_LCD_UPDATE_REG : R/W/SC ;bitpos:[21] ;default: 1'h0 ; */
+/*description: 1: Update LCD registers, will be cleared by hardware. 0 : Not care..*/
+#define LCD_CAM_LCD_UPDATE_REG    (BIT(21))
+#define LCD_CAM_LCD_UPDATE_REG_M  (BIT(21))
+#define LCD_CAM_LCD_UPDATE_REG_V  0x1
+#define LCD_CAM_LCD_UPDATE_REG_S  21
+/* LCD_CAM_LCD_BYTE_MODE : R/W ;bitpos:[20:19] ;default: 2'h0 ; */
+/*description: 2: 24bit mode. 1: 16bit mode. 0: 8bit mode.*/
+#define LCD_CAM_LCD_BYTE_MODE    0x00000003
+#define LCD_CAM_LCD_BYTE_MODE_M  ((LCD_CAM_LCD_BYTE_MODE_V)<<(LCD_CAM_LCD_BYTE_MODE_S))
+#define LCD_CAM_LCD_BYTE_MODE_V  0x3
+#define LCD_CAM_LCD_BYTE_MODE_S  19
+/* LCD_CAM_LCD_DOUT_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: 1: change bit order in every byte. 0: Not change..*/
+#define LCD_CAM_LCD_DOUT_BIT_ORDER    (BIT(18))
+#define LCD_CAM_LCD_DOUT_BIT_ORDER_M  (BIT(18))
+#define LCD_CAM_LCD_DOUT_BIT_ORDER_V  0x1
+#define LCD_CAM_LCD_DOUT_BIT_ORDER_S  18
+/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: 1: enable byte swizzle 0: disable.*/
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE    (BIT(17))
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M  (BIT(17))
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V  0x1
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S  17
+/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W ;bitpos:[16:14] ;default: 3'h0 ; */
+/*description: 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA.*/
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE    0x00000007
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M  ((LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V)<<(LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S))
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V  0x7
+#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S  14
+/* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */
+/*description: LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared
+ or reg_lcd_reset is set..*/
+#define LCD_CAM_LCD_ALWAYS_OUT_EN    (BIT(13))
+#define LCD_CAM_LCD_ALWAYS_OUT_EN_M  (BIT(13))
+#define LCD_CAM_LCD_ALWAYS_OUT_EN_V  0x1
+#define LCD_CAM_LCD_ALWAYS_OUT_EN_S  13
+/* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
+/*description: The output data cycles minus 1 of LCD module..*/
+#define LCD_CAM_LCD_DOUT_CYCLELEN    0x00001FFF
+#define LCD_CAM_LCD_DOUT_CYCLELEN_M  ((LCD_CAM_LCD_DOUT_CYCLELEN_V)<<(LCD_CAM_LCD_DOUT_CYCLELEN_S))
+#define LCD_CAM_LCD_DOUT_CYCLELEN_V  0x1FFF
+#define LCD_CAM_LCD_DOUT_CYCLELEN_S  0
+
+#define LCD_CAM_LCD_MISC_REG          (DR_REG_LCD_CAM_BASE + 0x18)
+/* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: The default value of LCD_CD..*/
+#define LCD_CAM_LCD_CD_IDLE_EDGE    (BIT(31))
+#define LCD_CAM_LCD_CD_IDLE_EDGE_M  (BIT(31))
+#define LCD_CAM_LCD_CD_IDLE_EDGE_V  0x1
+#define LCD_CAM_LCD_CD_IDLE_EDGE_S  31
+/* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+ reg_cd_idle_edge..*/
+#define LCD_CAM_LCD_CD_CMD_SET    (BIT(30))
+#define LCD_CAM_LCD_CD_CMD_SET_M  (BIT(30))
+#define LCD_CAM_LCD_CD_CMD_SET_V  0x1
+#define LCD_CAM_LCD_CD_CMD_SET_S  30
+/* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */
+/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD
+ = reg_cd_idle_edge..*/
+#define LCD_CAM_LCD_CD_DUMMY_SET    (BIT(29))
+#define LCD_CAM_LCD_CD_DUMMY_SET_M  (BIT(29))
+#define LCD_CAM_LCD_CD_DUMMY_SET_V  0x1
+#define LCD_CAM_LCD_CD_DUMMY_SET_S  29
+/* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD
+= reg_cd_idle_edge..*/
+#define LCD_CAM_LCD_CD_DATA_SET    (BIT(28))
+#define LCD_CAM_LCD_CD_DATA_SET_M  (BIT(28))
+#define LCD_CAM_LCD_CD_DATA_SET_V  0x1
+#define LCD_CAM_LCD_CD_DATA_SET_S  28
+/* LCD_CAM_LCD_AFIFO_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
+/*description: LCD AFIFO reset signal..*/
+#define LCD_CAM_LCD_AFIFO_RESET    (BIT(27))
+#define LCD_CAM_LCD_AFIFO_RESET_M  (BIT(27))
+#define LCD_CAM_LCD_AFIFO_RESET_V  0x1
+#define LCD_CAM_LCD_AFIFO_RESET_S  27
+/* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: Enable blank region when LCD sends data out. 0: No blank region..*/
+#define LCD_CAM_LCD_BK_EN    (BIT(26))
+#define LCD_CAM_LCD_BK_EN_M  (BIT(26))
+#define LCD_CAM_LCD_BK_EN_V  0x1
+#define LCD_CAM_LCD_BK_EN_S  26
+/* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: Send the next frame data when the current frame is sent out. 0: LCD stops whe
+n the current frame is sent out..*/
+#define LCD_CAM_LCD_NEXT_FRAME_EN    (BIT(25))
+#define LCD_CAM_LCD_NEXT_FRAME_EN_M  (BIT(25))
+#define LCD_CAM_LCD_NEXT_FRAME_EN_V  0x1
+#define LCD_CAM_LCD_NEXT_FRAME_EN_S  25
+/* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */
+/*description: The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+ time cycle length in LCD non-RGB mode..*/
+#define LCD_CAM_LCD_VBK_CYCLELEN    0x00001FFF
+#define LCD_CAM_LCD_VBK_CYCLELEN_M  ((LCD_CAM_LCD_VBK_CYCLELEN_V)<<(LCD_CAM_LCD_VBK_CYCLELEN_S))
+#define LCD_CAM_LCD_VBK_CYCLELEN_V  0x1FFF
+#define LCD_CAM_LCD_VBK_CYCLELEN_S  12
+/* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */
+/*description: The setup cycle length minus 1 in LCD non-RGB mode..*/
+#define LCD_CAM_LCD_VFK_CYCLELEN    0x0000003F
+#define LCD_CAM_LCD_VFK_CYCLELEN_M  ((LCD_CAM_LCD_VFK_CYCLELEN_V)<<(LCD_CAM_LCD_VFK_CYCLELEN_S))
+#define LCD_CAM_LCD_VFK_CYCLELEN_V  0x3F
+#define LCD_CAM_LCD_VFK_CYCLELEN_S  6
+/* LCD_CAM_LCD_WIRE_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit.*/
+#define LCD_CAM_LCD_WIRE_MODE    0x00000003
+#define LCD_CAM_LCD_WIRE_MODE_M  ((LCD_CAM_LCD_WIRE_MODE_V)<<(LCD_CAM_LCD_WIRE_MODE_S))
+#define LCD_CAM_LCD_WIRE_MODE_V  0x3
+#define LCD_CAM_LCD_WIRE_MODE_S  4
+
+#define LCD_CAM_LCD_CTRL_REG          (DR_REG_LCD_CAM_BASE + 0x1C)
+/* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: Enable LCD RGB mode. 0: Disable LCD RGB mode..*/
+#define LCD_CAM_LCD_RGB_MODE_EN    (BIT(31))
+#define LCD_CAM_LCD_RGB_MODE_EN_M  (BIT(31))
+#define LCD_CAM_LCD_RGB_MODE_EN_V  0x1
+#define LCD_CAM_LCD_RGB_MODE_EN_S  31
+/* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */
+/*description: It is the vertical total height of a frame..*/
+#define LCD_CAM_LCD_VT_HEIGHT    0x000003FF
+#define LCD_CAM_LCD_VT_HEIGHT_M  ((LCD_CAM_LCD_VT_HEIGHT_V)<<(LCD_CAM_LCD_VT_HEIGHT_S))
+#define LCD_CAM_LCD_VT_HEIGHT_V  0x3FF
+#define LCD_CAM_LCD_VT_HEIGHT_S  21
+/* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */
+/*description: It is the vertical active height of a frame..*/
+#define LCD_CAM_LCD_VA_HEIGHT    0x000003FF
+#define LCD_CAM_LCD_VA_HEIGHT_M  ((LCD_CAM_LCD_VA_HEIGHT_V)<<(LCD_CAM_LCD_VA_HEIGHT_S))
+#define LCD_CAM_LCD_VA_HEIGHT_V  0x3FF
+#define LCD_CAM_LCD_VA_HEIGHT_S  11
+/* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */
+/*description: It is the horizontal blank front porch of a frame..*/
+#define LCD_CAM_LCD_HB_FRONT    0x000007FF
+#define LCD_CAM_LCD_HB_FRONT_M  ((LCD_CAM_LCD_HB_FRONT_V)<<(LCD_CAM_LCD_HB_FRONT_S))
+#define LCD_CAM_LCD_HB_FRONT_V  0x7FF
+#define LCD_CAM_LCD_HB_FRONT_S  0
+
+#define LCD_CAM_LCD_CTRL1_REG          (DR_REG_LCD_CAM_BASE + 0x20)
+/* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */
+/*description: It is the horizontal total width of a frame..*/
+#define LCD_CAM_LCD_HT_WIDTH    0x00000FFF
+#define LCD_CAM_LCD_HT_WIDTH_M  ((LCD_CAM_LCD_HT_WIDTH_V)<<(LCD_CAM_LCD_HT_WIDTH_S))
+#define LCD_CAM_LCD_HT_WIDTH_V  0xFFF
+#define LCD_CAM_LCD_HT_WIDTH_S  20
+/* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */
+/*description: It is the horizontal active width of a frame..*/
+#define LCD_CAM_LCD_HA_WIDTH    0x00000FFF
+#define LCD_CAM_LCD_HA_WIDTH_M  ((LCD_CAM_LCD_HA_WIDTH_V)<<(LCD_CAM_LCD_HA_WIDTH_S))
+#define LCD_CAM_LCD_HA_WIDTH_V  0xFFF
+#define LCD_CAM_LCD_HA_WIDTH_S  8
+/* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
+/*description: It is the vertical blank front porch of a frame..*/
+#define LCD_CAM_LCD_VB_FRONT    0x000000FF
+#define LCD_CAM_LCD_VB_FRONT_M  ((LCD_CAM_LCD_VB_FRONT_V)<<(LCD_CAM_LCD_VB_FRONT_S))
+#define LCD_CAM_LCD_VB_FRONT_V  0xFF
+#define LCD_CAM_LCD_VB_FRONT_S  0
+
+#define LCD_CAM_LCD_CTRL2_REG          (DR_REG_LCD_CAM_BASE + 0x24)
+/* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
+/*description: It is the position of LCD_HSYNC active pulse in a line..*/
+#define LCD_CAM_LCD_HSYNC_POSITION    0x000000FF
+#define LCD_CAM_LCD_HSYNC_POSITION_M  ((LCD_CAM_LCD_HSYNC_POSITION_V)<<(LCD_CAM_LCD_HSYNC_POSITION_S))
+#define LCD_CAM_LCD_HSYNC_POSITION_V  0xFF
+#define LCD_CAM_LCD_HSYNC_POSITION_S  24
+/* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: It is the idle value of LCD_HSYNC..*/
+#define LCD_CAM_LCD_HSYNC_IDLE_POL    (BIT(23))
+#define LCD_CAM_LCD_HSYNC_IDLE_POL_M  (BIT(23))
+#define LCD_CAM_LCD_HSYNC_IDLE_POL_V  0x1
+#define LCD_CAM_LCD_HSYNC_IDLE_POL_S  23
+/* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */
+/*description: It is the position of LCD_HSYNC active pulse in a line..*/
+#define LCD_CAM_LCD_HSYNC_WIDTH    0x0000007F
+#define LCD_CAM_LCD_HSYNC_WIDTH_M  ((LCD_CAM_LCD_HSYNC_WIDTH_V)<<(LCD_CAM_LCD_HSYNC_WIDTH_S))
+#define LCD_CAM_LCD_HSYNC_WIDTH_V  0x7F
+#define LCD_CAM_LCD_HSYNC_WIDTH_S  16
+/* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSY
+NC pulse is valid only in active region lines in RGB mode..*/
+#define LCD_CAM_LCD_HS_BLANK_EN    (BIT(9))
+#define LCD_CAM_LCD_HS_BLANK_EN_M  (BIT(9))
+#define LCD_CAM_LCD_HS_BLANK_EN_V  0x1
+#define LCD_CAM_LCD_HS_BLANK_EN_S  9
+/* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: It is the idle value of LCD_DE..*/
+#define LCD_CAM_LCD_DE_IDLE_POL    (BIT(8))
+#define LCD_CAM_LCD_DE_IDLE_POL_M  (BIT(8))
+#define LCD_CAM_LCD_DE_IDLE_POL_V  0x1
+#define LCD_CAM_LCD_DE_IDLE_POL_S  8
+/* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: It is the idle value of LCD_VSYNC..*/
+#define LCD_CAM_LCD_VSYNC_IDLE_POL    (BIT(7))
+#define LCD_CAM_LCD_VSYNC_IDLE_POL_M  (BIT(7))
+#define LCD_CAM_LCD_VSYNC_IDLE_POL_V  0x1
+#define LCD_CAM_LCD_VSYNC_IDLE_POL_S  7
+/* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
+/*description: It is the position of LCD_VSYNC active pulse in a line..*/
+#define LCD_CAM_LCD_VSYNC_WIDTH    0x0000007F
+#define LCD_CAM_LCD_VSYNC_WIDTH_M  ((LCD_CAM_LCD_VSYNC_WIDTH_V)<<(LCD_CAM_LCD_VSYNC_WIDTH_S))
+#define LCD_CAM_LCD_VSYNC_WIDTH_V  0x7F
+#define LCD_CAM_LCD_VSYNC_WIDTH_S  0
+
+#define LCD_CAM_LCD_FIRST_CMD_VAL_REG          (DR_REG_LCD_CAM_BASE + 0x28)
+/* LCD_CAM_LCD_FIRST_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The LCD write command value of first cmd cycle..*/
+#define LCD_CAM_LCD_FIRST_CMD_VALUE    0xFFFFFFFF
+#define LCD_CAM_LCD_FIRST_CMD_VALUE_M  ((LCD_CAM_LCD_FIRST_CMD_VALUE_V)<<(LCD_CAM_LCD_FIRST_CMD_VALUE_S))
+#define LCD_CAM_LCD_FIRST_CMD_VALUE_V  0xFFFFFFFF
+#define LCD_CAM_LCD_FIRST_CMD_VALUE_S  0
+
+#define LCD_CAM_LCD_LATTER_CMD_VAL_REG          (DR_REG_LCD_CAM_BASE + 0x2C)
+/* LCD_CAM_LCD_LATTER_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The LCD write command value of latter cmd cycle..*/
+#define LCD_CAM_LCD_LATTER_CMD_VALUE    0xFFFFFFFF
+#define LCD_CAM_LCD_LATTER_CMD_VALUE_M  ((LCD_CAM_LCD_LATTER_CMD_VALUE_V)<<(LCD_CAM_LCD_LATTER_CMD_VALUE_S))
+#define LCD_CAM_LCD_LATTER_CMD_VALUE_V  0xFFFFFFFF
+#define LCD_CAM_LCD_LATTER_CMD_VALUE_S  0
+
+#define LCD_CAM_LCD_DLY_MODE_CFG1_REG          (DR_REG_LCD_CAM_BASE + 0x30)
+/* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
+/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay
+ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L
+CD_CLK..*/
+#define LCD_CAM_LCD_VSYNC_MODE    0x00000003
+#define LCD_CAM_LCD_VSYNC_MODE_M  ((LCD_CAM_LCD_VSYNC_MODE_V)<<(LCD_CAM_LCD_VSYNC_MODE_S))
+#define LCD_CAM_LCD_VSYNC_MODE_V  0x3
+#define LCD_CAM_LCD_VSYNC_MODE_S  22
+/* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay
+ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L
+CD_CLK..*/
+#define LCD_CAM_LCD_HSYNC_MODE    0x00000003
+#define LCD_CAM_LCD_HSYNC_MODE_M  ((LCD_CAM_LCD_HSYNC_MODE_V)<<(LCD_CAM_LCD_HSYNC_MODE_S))
+#define LCD_CAM_LCD_HSYNC_MODE_V  0x3
+#define LCD_CAM_LCD_HSYNC_MODE_S  20
+/* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
+/*description: The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed.
+ 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_
+CLK..*/
+#define LCD_CAM_LCD_DE_MODE    0x00000003
+#define LCD_CAM_LCD_DE_MODE_M  ((LCD_CAM_LCD_DE_MODE_V)<<(LCD_CAM_LCD_DE_MODE_S))
+#define LCD_CAM_LCD_DE_MODE_V  0x3
+#define LCD_CAM_LCD_DE_MODE_S  18
+/* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed.
+ 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_
+CLK..*/
+#define LCD_CAM_LCD_CD_MODE    0x00000003
+#define LCD_CAM_LCD_CD_MODE_M  ((LCD_CAM_LCD_CD_MODE_V)<<(LCD_CAM_LCD_CD_MODE_S))
+#define LCD_CAM_LCD_CD_MODE_V  0x3
+#define LCD_CAM_LCD_CD_MODE_S  16
+/* LCD_CAM_DOUT23_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT23_MODE    0x00000003
+#define LCD_CAM_DOUT23_MODE_M  ((LCD_CAM_DOUT23_MODE_V)<<(LCD_CAM_DOUT23_MODE_S))
+#define LCD_CAM_DOUT23_MODE_V  0x3
+#define LCD_CAM_DOUT23_MODE_S  14
+/* LCD_CAM_DOUT22_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT22_MODE    0x00000003
+#define LCD_CAM_DOUT22_MODE_M  ((LCD_CAM_DOUT22_MODE_V)<<(LCD_CAM_DOUT22_MODE_S))
+#define LCD_CAM_DOUT22_MODE_V  0x3
+#define LCD_CAM_DOUT22_MODE_S  12
+/* LCD_CAM_DOUT21_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT21_MODE    0x00000003
+#define LCD_CAM_DOUT21_MODE_M  ((LCD_CAM_DOUT21_MODE_V)<<(LCD_CAM_DOUT21_MODE_S))
+#define LCD_CAM_DOUT21_MODE_V  0x3
+#define LCD_CAM_DOUT21_MODE_S  10
+/* LCD_CAM_DOUT20_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT20_MODE    0x00000003
+#define LCD_CAM_DOUT20_MODE_M  ((LCD_CAM_DOUT20_MODE_V)<<(LCD_CAM_DOUT20_MODE_S))
+#define LCD_CAM_DOUT20_MODE_V  0x3
+#define LCD_CAM_DOUT20_MODE_S  8
+/* LCD_CAM_DOUT19_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT19_MODE    0x00000003
+#define LCD_CAM_DOUT19_MODE_M  ((LCD_CAM_DOUT19_MODE_V)<<(LCD_CAM_DOUT19_MODE_S))
+#define LCD_CAM_DOUT19_MODE_V  0x3
+#define LCD_CAM_DOUT19_MODE_S  6
+/* LCD_CAM_DOUT18_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT18_MODE    0x00000003
+#define LCD_CAM_DOUT18_MODE_M  ((LCD_CAM_DOUT18_MODE_V)<<(LCD_CAM_DOUT18_MODE_S))
+#define LCD_CAM_DOUT18_MODE_V  0x3
+#define LCD_CAM_DOUT18_MODE_S  4
+/* LCD_CAM_DOUT17_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT17_MODE    0x00000003
+#define LCD_CAM_DOUT17_MODE_M  ((LCD_CAM_DOUT17_MODE_V)<<(LCD_CAM_DOUT17_MODE_S))
+#define LCD_CAM_DOUT17_MODE_V  0x3
+#define LCD_CAM_DOUT17_MODE_S  2
+/* LCD_CAM_DOUT16_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT16_MODE    0x00000003
+#define LCD_CAM_DOUT16_MODE_M  ((LCD_CAM_DOUT16_MODE_V)<<(LCD_CAM_DOUT16_MODE_S))
+#define LCD_CAM_DOUT16_MODE_V  0x3
+#define LCD_CAM_DOUT16_MODE_S  0
+
+#define LCD_CAM_LCD_DLY_MODE_CFG2_REG          (DR_REG_LCD_CAM_BASE + 0x38)
+/* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT15_MODE    0x00000003
+#define LCD_CAM_DOUT15_MODE_M  ((LCD_CAM_DOUT15_MODE_V)<<(LCD_CAM_DOUT15_MODE_S))
+#define LCD_CAM_DOUT15_MODE_V  0x3
+#define LCD_CAM_DOUT15_MODE_S  30
+/* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT14_MODE    0x00000003
+#define LCD_CAM_DOUT14_MODE_M  ((LCD_CAM_DOUT14_MODE_V)<<(LCD_CAM_DOUT14_MODE_S))
+#define LCD_CAM_DOUT14_MODE_V  0x3
+#define LCD_CAM_DOUT14_MODE_S  28
+/* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT13_MODE    0x00000003
+#define LCD_CAM_DOUT13_MODE_M  ((LCD_CAM_DOUT13_MODE_V)<<(LCD_CAM_DOUT13_MODE_S))
+#define LCD_CAM_DOUT13_MODE_V  0x3
+#define LCD_CAM_DOUT13_MODE_S  26
+/* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT12_MODE    0x00000003
+#define LCD_CAM_DOUT12_MODE_M  ((LCD_CAM_DOUT12_MODE_V)<<(LCD_CAM_DOUT12_MODE_S))
+#define LCD_CAM_DOUT12_MODE_V  0x3
+#define LCD_CAM_DOUT12_MODE_S  24
+/* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT11_MODE    0x00000003
+#define LCD_CAM_DOUT11_MODE_M  ((LCD_CAM_DOUT11_MODE_V)<<(LCD_CAM_DOUT11_MODE_S))
+#define LCD_CAM_DOUT11_MODE_V  0x3
+#define LCD_CAM_DOUT11_MODE_S  22
+/* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT10_MODE    0x00000003
+#define LCD_CAM_DOUT10_MODE_M  ((LCD_CAM_DOUT10_MODE_V)<<(LCD_CAM_DOUT10_MODE_S))
+#define LCD_CAM_DOUT10_MODE_V  0x3
+#define LCD_CAM_DOUT10_MODE_S  20
+/* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT9_MODE    0x00000003
+#define LCD_CAM_DOUT9_MODE_M  ((LCD_CAM_DOUT9_MODE_V)<<(LCD_CAM_DOUT9_MODE_S))
+#define LCD_CAM_DOUT9_MODE_V  0x3
+#define LCD_CAM_DOUT9_MODE_S  18
+/* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT8_MODE    0x00000003
+#define LCD_CAM_DOUT8_MODE_M  ((LCD_CAM_DOUT8_MODE_V)<<(LCD_CAM_DOUT8_MODE_S))
+#define LCD_CAM_DOUT8_MODE_V  0x3
+#define LCD_CAM_DOUT8_MODE_S  16
+/* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT7_MODE    0x00000003
+#define LCD_CAM_DOUT7_MODE_M  ((LCD_CAM_DOUT7_MODE_V)<<(LCD_CAM_DOUT7_MODE_S))
+#define LCD_CAM_DOUT7_MODE_V  0x3
+#define LCD_CAM_DOUT7_MODE_S  14
+/* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT6_MODE    0x00000003
+#define LCD_CAM_DOUT6_MODE_M  ((LCD_CAM_DOUT6_MODE_V)<<(LCD_CAM_DOUT6_MODE_S))
+#define LCD_CAM_DOUT6_MODE_V  0x3
+#define LCD_CAM_DOUT6_MODE_S  12
+/* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT5_MODE    0x00000003
+#define LCD_CAM_DOUT5_MODE_M  ((LCD_CAM_DOUT5_MODE_V)<<(LCD_CAM_DOUT5_MODE_S))
+#define LCD_CAM_DOUT5_MODE_V  0x3
+#define LCD_CAM_DOUT5_MODE_S  10
+/* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT4_MODE    0x00000003
+#define LCD_CAM_DOUT4_MODE_M  ((LCD_CAM_DOUT4_MODE_V)<<(LCD_CAM_DOUT4_MODE_S))
+#define LCD_CAM_DOUT4_MODE_V  0x3
+#define LCD_CAM_DOUT4_MODE_S  8
+/* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT3_MODE    0x00000003
+#define LCD_CAM_DOUT3_MODE_M  ((LCD_CAM_DOUT3_MODE_V)<<(LCD_CAM_DOUT3_MODE_S))
+#define LCD_CAM_DOUT3_MODE_V  0x3
+#define LCD_CAM_DOUT3_MODE_S  6
+/* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT2_MODE    0x00000003
+#define LCD_CAM_DOUT2_MODE_M  ((LCD_CAM_DOUT2_MODE_V)<<(LCD_CAM_DOUT2_MODE_S))
+#define LCD_CAM_DOUT2_MODE_V  0x3
+#define LCD_CAM_DOUT2_MODE_S  4
+/* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT1_MODE    0x00000003
+#define LCD_CAM_DOUT1_MODE_M  ((LCD_CAM_DOUT1_MODE_V)<<(LCD_CAM_DOUT1_MODE_S))
+#define LCD_CAM_DOUT1_MODE_V  0x3
+#define LCD_CAM_DOUT1_MODE_S  2
+/* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
+ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ LCD_CLK..*/
+#define LCD_CAM_DOUT0_MODE    0x00000003
+#define LCD_CAM_DOUT0_MODE_M  ((LCD_CAM_DOUT0_MODE_V)<<(LCD_CAM_DOUT0_MODE_S))
+#define LCD_CAM_DOUT0_MODE_V  0x3
+#define LCD_CAM_DOUT0_MODE_S  0
+
+#define LCD_CAM_LC_DMA_INT_ENA_REG          (DR_REG_LCD_CAM_BASE + 0x64)
+/* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for Camera line interrupt..*/
+#define LCD_CAM_CAM_HS_INT_ENA    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_ENA_M  (BIT(3))
+#define LCD_CAM_CAM_HS_INT_ENA_V  0x1
+#define LCD_CAM_CAM_HS_INT_ENA_S  3
+/* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for Camera frame end interrupt..*/
+#define LCD_CAM_CAM_VSYNC_INT_ENA    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_ENA_M  (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_ENA_V  0x1
+#define LCD_CAM_CAM_VSYNC_INT_ENA_S  2
+/* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for lcd transfer end interrupt..*/
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M  (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V  0x1
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S  1
+/* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for LCD frame end interrupt..*/
+#define LCD_CAM_LCD_VSYNC_INT_ENA    (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_ENA_M  (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_ENA_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_ENA_S  0
+
+#define LCD_CAM_LC_DMA_INT_RAW_REG          (DR_REG_LCD_CAM_BASE + 0x68)
+/* LCD_CAM_CAM_HS_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for Camera line interrupt..*/
+#define LCD_CAM_CAM_HS_INT_RAW    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_RAW_M  (BIT(3))
+#define LCD_CAM_CAM_HS_INT_RAW_V  0x1
+#define LCD_CAM_CAM_HS_INT_RAW_S  3
+/* LCD_CAM_CAM_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for Camera frame end interrupt..*/
+#define LCD_CAM_CAM_VSYNC_INT_RAW    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_RAW_M  (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_RAW_V  0x1
+#define LCD_CAM_CAM_VSYNC_INT_RAW_S  2
+/* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for lcd transfer end interrupt..*/
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M  (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V  0x1
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S  1
+/* LCD_CAM_LCD_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for LCD frame end interrupt..*/
+#define LCD_CAM_LCD_VSYNC_INT_RAW    (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_RAW_M  (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_RAW_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_RAW_S  0
+
+#define LCD_CAM_LC_DMA_INT_ST_REG          (DR_REG_LCD_CAM_BASE + 0x6C)
+/* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for Camera transfer end interrupt..*/
+#define LCD_CAM_CAM_HS_INT_ST    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_ST_M  (BIT(3))
+#define LCD_CAM_CAM_HS_INT_ST_V  0x1
+#define LCD_CAM_CAM_HS_INT_ST_S  3
+/* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for Camera frame end interrupt..*/
+#define LCD_CAM_CAM_VSYNC_INT_ST    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_ST_M  (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_ST_V  0x1
+#define LCD_CAM_CAM_VSYNC_INT_ST_S  2
+/* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for lcd transfer end interrupt..*/
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M  (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V  0x1
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S  1
+/* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for LCD frame end interrupt..*/
+#define LCD_CAM_LCD_VSYNC_INT_ST    (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_ST_M  (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_ST_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_ST_S  0
+
+#define LCD_CAM_LC_DMA_INT_CLR_REG          (DR_REG_LCD_CAM_BASE + 0x70)
+/* LCD_CAM_CAM_HS_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for Camera line interrupt..*/
+#define LCD_CAM_CAM_HS_INT_CLR    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_CLR_M  (BIT(3))
+#define LCD_CAM_CAM_HS_INT_CLR_V  0x1
+#define LCD_CAM_CAM_HS_INT_CLR_S  3
+/* LCD_CAM_CAM_VSYNC_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for Camera frame end interrupt..*/
+#define LCD_CAM_CAM_VSYNC_INT_CLR    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_CLR_M  (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_CLR_V  0x1
+#define LCD_CAM_CAM_VSYNC_INT_CLR_S  2
+/* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for lcd transfer end interrupt..*/
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M  (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V  0x1
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S  1
+/* LCD_CAM_LCD_VSYNC_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for LCD frame end interrupt..*/
+#define LCD_CAM_LCD_VSYNC_INT_CLR    (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_CLR_M  (BIT(0))
+#define LCD_CAM_LCD_VSYNC_INT_CLR_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_CLR_S  0
+
+#define LCD_CAM_LC_REG_DATE_REG          (DR_REG_LCD_CAM_BASE + 0xFC)
+/* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2303090 ; */
+/*description: LCD_CAM version control register.*/
+#define LCD_CAM_LC_DATE    0x0FFFFFFF
+#define LCD_CAM_LC_DATE_M  ((LCD_CAM_LC_DATE_V)<<(LCD_CAM_LC_DATE_S))
+#define LCD_CAM_LC_DATE_V  0xFFFFFFF
+#define LCD_CAM_LC_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_LCD_CAM_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/lcd_cam_struct.h b/components/soc/esp32p4/include/soc/lcd_cam_struct.h
new file mode 100644
index 0000000000..ed787f0761
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lcd_cam_struct.h
@@ -0,0 +1,303 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_LCD_CAM_STRUCT_H_
+#define _SOC_LCD_CAM_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t lcd_clkcnt_n                  :    6;  /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
+            uint32_t lcd_clk_equ_sysclk            :    1;  /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
+            uint32_t lcd_ck_idle_edge              :    1;  /*1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle. */
+            uint32_t lcd_ck_out_edge               :    1;  /*1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low in the second half data cycle. */
+            uint32_t lcd_clkm_div_num              :    8;  /*Integral LCD clock divider value*/
+            uint32_t lcd_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
+            uint32_t lcd_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
+            uint32_t lcd_clk_sel                   :    2;  /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+        };
+        uint32_t val;
+    } lcd_clock;
+    union {
+        struct {
+            uint32_t cam_stop_en                   :    1;  /*Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/
+            uint32_t cam_vsync_filter_thres        :    3;  /*Filter threshold value for CAM_VSYNC signal.*/
+            uint32_t cam_update                    :    1;  /*1: Update Camera registers, will be cleared by hardware. 0 : Not care.*/
+            uint32_t cam_byte_order                :    1;  /*1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
+            uint32_t cam_bit_order                 :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
+            uint32_t cam_line_int_en               :    1;  /*1: Enable to generate CAM_HS_INT. 0: Disable.*/
+            uint32_t cam_vs_eof_en                 :    1;  /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/
+            uint32_t cam_clkm_div_num              :    8;  /*Integral Camera clock divider value*/
+            uint32_t cam_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
+            uint32_t cam_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
+            uint32_t cam_clk_sel                   :    2;  /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } cam_ctrl;
+    union {
+        struct {
+            uint32_t cam_rec_data_bytelen          :    16;  /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
+            uint32_t cam_line_int_num              :    6;  /*The line number minus 1 to generate cam_hs_int.*/
+            uint32_t cam_clk_inv                   :    1;  /*1: Invert  the input signal CAM_PCLK. 0: Not invert.*/
+            uint32_t cam_vsync_filter_en           :    1;  /*1: Enable CAM_VSYNC filter function. 0: bypass.*/
+            uint32_t cam_2byte_en                  :    1;  /*1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8. */
+            uint32_t cam_de_inv                    :    1;  /*CAM_DE invert enable signal, valid in high level.*/
+            uint32_t cam_hsync_inv                 :    1;  /*CAM_HSYNC invert enable signal, valid in high level.*/
+            uint32_t cam_vsync_inv                 :    1;  /*CAM_VSYNC invert enable signal, valid in high level.*/
+            uint32_t cam_vh_de_mode_en             :    1;  /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC.*/
+            uint32_t cam_start                     :    1;  /*Camera module start signal.*/
+            uint32_t cam_reset                     :    1;  /*Camera module reset signal.*/
+            uint32_t cam_afifo_reset               :    1;  /*Camera AFIFO reset signal.*/
+        };
+        uint32_t val;
+    } cam_ctrl1;
+    union {
+        struct {
+            uint32_t reserved0                     :    21;  /*reserved*/
+            uint32_t cam_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
+            uint32_t cam_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
+            uint32_t cam_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
+            uint32_t cam_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
+            uint32_t cam_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
+            uint32_t cam_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
+            uint32_t cam_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
+            uint32_t cam_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
+            uint32_t cam_conv_enable               :    1;  /*0: Bypass converter. 1: Enable converter.*/
+        };
+        uint32_t val;
+    } cam_rgb_yuv;
+    union {
+        struct {
+            uint32_t reserved0                     :    20;  /*reserved*/
+            uint32_t lcd_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
+            uint32_t lcd_conv_txtorx               :    1;  /*0: txtorx mode off. 1: txtorx mode on.*/
+            uint32_t lcd_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
+            uint32_t lcd_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
+            uint32_t lcd_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
+            uint32_t lcd_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
+            uint32_t lcd_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
+            uint32_t lcd_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
+            uint32_t lcd_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
+            uint32_t lcd_conv_enable               :    1;  /*0: Bypass converter. 1: Enable converter.*/
+        };
+        uint32_t val;
+    } lcd_rgb_yuv;
+    union {
+        struct {
+            uint32_t lcd_dout_cyclelen             :    13;  /*The output data cycles minus 1 of LCD module.*/
+            uint32_t lcd_always_out_en             :    1;  /*LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set.*/
+            uint32_t lcd_dout_byte_swizzle_mode    :    3;  /*0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA*/
+            uint32_t lcd_dout_byte_swizzle_enable  :    1;  /*1: enable byte swizzle 0: disable*/
+            uint32_t lcd_dout_bit_order            :    1;  /*1: change bit order in every byte. 0: Not change.*/
+            uint32_t lcd_byte_mode                 :    2;  /*2: 24bit mode. 1: 16bit mode. 0: 8bit mode*/
+            uint32_t lcd_update                    :    1;  /*1: Update LCD registers, will be cleared by hardware. 0 : Not care.*/
+            uint32_t lcd_bit_order                 :    1;  /*1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
+            uint32_t lcd_byte_order                :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
+            uint32_t lcd_dout                      :    1;  /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
+            uint32_t lcd_dummy                     :    1;  /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
+            uint32_t lcd_cmd                       :    1;  /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
+            uint32_t lcd_start                     :    1;  /*LCD start sending data enable signal, valid in high level.*/
+            uint32_t lcd_reset                     :    1;  /*The value of  command. */
+            uint32_t lcd_dummy_cyclelen            :    2;  /*The dummy cycle length minus 1.*/
+            uint32_t lcd_cmd_2_cycle_en            :    1;  /*The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */
+        };
+        uint32_t val;
+    } lcd_user;
+    union {
+        struct {
+            uint32_t reserved0                     :    4;  /*reserved*/
+            uint32_t lcd_wire_mode                 :    2;  /*The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit*/
+            uint32_t lcd_vfk_cyclelen              :    6;  /*The setup cycle length minus 1 in LCD non-RGB mode.*/
+            uint32_t lcd_vbk_cyclelen              :    13;  /*The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode.*/
+            uint32_t lcd_next_frame_en             :    1;  /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/
+            uint32_t lcd_bk_en                     :    1;  /*1: Enable blank region when LCD sends data out. 0: No blank region.*/
+            uint32_t lcd_afifo_reset               :    1;  /*LCD AFIFO reset signal.*/
+            uint32_t lcd_cd_data_set               :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD = reg_cd_idle_edge. */
+            uint32_t lcd_cd_dummy_set              :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD = reg_cd_idle_edge. */
+            uint32_t lcd_cd_cmd_set                :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD = reg_cd_idle_edge. */
+            uint32_t lcd_cd_idle_edge              :    1;  /*The default value of LCD_CD. */
+        };
+        uint32_t val;
+    } lcd_misc;
+    union {
+        struct {
+            uint32_t lcd_hb_front                  :    11;  /*It is the horizontal blank front porch of a frame. */
+            uint32_t lcd_va_height                 :    10;  /*It is the vertical active height of a frame. */
+            uint32_t lcd_vt_height                 :    10;  /*It is the vertical total height of a frame. */
+            uint32_t lcd_rgb_mode_en               :    1;  /*1: Enable LCD RGB mode. 0: Disable LCD RGB mode.*/
+        };
+        uint32_t val;
+    } lcd_ctrl;
+    union {
+        struct {
+            uint32_t lcd_vb_front                  :    8;  /*It is the vertical blank front porch of a frame. */
+            uint32_t lcd_ha_width                  :    12;  /*It is the horizontal active width of a frame. */
+            uint32_t lcd_ht_width                  :    12;  /*It is the horizontal total width of a frame. */
+        };
+        uint32_t val;
+    } lcd_ctrl1;
+    union {
+        struct {
+            uint32_t lcd_vsync_width               :    7;  /*It is the position of LCD_VSYNC active pulse in a line. */
+            uint32_t lcd_vsync_idle_pol            :    1;  /*It is the idle value of LCD_VSYNC. */
+            uint32_t lcd_de_idle_pol               :    1;  /*It is the idle value of LCD_DE. */
+            uint32_t lcd_hs_blank_en               :    1;  /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. */
+            uint32_t reserved10                    :    6;  /*reserved*/
+            uint32_t lcd_hsync_width               :    7;  /*It is the position of LCD_HSYNC active pulse in a line. */
+            uint32_t lcd_hsync_idle_pol            :    1;  /*It is the idle value of LCD_HSYNC. */
+            uint32_t lcd_hsync_position            :    8;  /*It is the position of LCD_HSYNC active pulse in a line. */
+        };
+        uint32_t val;
+    } lcd_ctrl2;
+    uint32_t lcd_first_cmd_val;
+    uint32_t lcd_latter_cmd_val;
+    union {
+        struct {
+            uint32_t dout16_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout17_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout18_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout19_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout20_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout21_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout22_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout23_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t lcd_cd_mode                   :    2;  /*The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t lcd_de_mode                   :    2;  /*The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t lcd_hsync_mode                :    2;  /*The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t lcd_vsync_mode                :    2;  /*The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } lcd_dly_mode_cfg1;
+    uint32_t reserved_34;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout1_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout2_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout3_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout4_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout5_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout6_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout7_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout8_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout9_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout10_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout11_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout12_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout13_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout14_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+            uint32_t dout15_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
+        };
+        uint32_t val;
+    } lcd_dly_mode_cfg2;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    union {
+        struct {
+            uint32_t lcd_vsync                     :    1;  /*The enable bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The enable bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The enable bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The enable bit for Camera line interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t lcd_vsync                     :    1;  /*The raw bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The raw bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The raw bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The raw bit for Camera line interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t lcd_vsync                     :    1;  /*The status bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The status bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The status bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The status bit for Camera transfer end interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    union {
+        struct {
+            uint32_t lcd_vsync                     :    1;  /*The clear bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The clear bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The clear bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The clear bit for Camera line interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*LCD_CAM version control register*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} lcd_cam_dev_t;
+extern lcd_cam_dev_t LCD_CAM;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_LCD_CAM_STRUCT_H_ */
diff --git a/components/soc/esp32p4/include/soc/lcdcam_struct.h b/components/soc/esp32p4/include/soc/lcdcam_struct.h
index 52187ae4c2..7d79afce3c 100644
--- a/components/soc/esp32p4/include/soc/lcdcam_struct.h
+++ b/components/soc/esp32p4/include/soc/lcdcam_struct.h
@@ -820,7 +820,7 @@ typedef union {
 } lcdcam_lc_reg_date_reg_t;
 
 
-typedef struct {
+typedef struct lcd_cam_dev_s {
     volatile lcdcam_lcd_clock_reg_t lcd_clock;
     volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
     volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
diff --git a/components/soc/esp32p4/include/soc/lp_aon_reg.h b/components/soc/esp32p4/include/soc/lp_aon_reg.h
new file mode 100644
index 0000000000..07d035f462
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_aon_reg.h
@@ -0,0 +1,418 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_AON_STORE0_REG register
+ *  need_des
+ */
+#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
+/** LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE0    0xFFFFFFFFU
+#define LP_AON_STORE0_M  (LP_AON_STORE0_V << LP_AON_STORE0_S)
+#define LP_AON_STORE0_V  0xFFFFFFFFU
+#define LP_AON_STORE0_S  0
+
+/** LP_AON_STORE1_REG register
+ *  need_des
+ */
+#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
+/** LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE1    0xFFFFFFFFU
+#define LP_AON_STORE1_M  (LP_AON_STORE1_V << LP_AON_STORE1_S)
+#define LP_AON_STORE1_V  0xFFFFFFFFU
+#define LP_AON_STORE1_S  0
+
+/** LP_AON_STORE2_REG register
+ *  need_des
+ */
+#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
+/** LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE2    0xFFFFFFFFU
+#define LP_AON_STORE2_M  (LP_AON_STORE2_V << LP_AON_STORE2_S)
+#define LP_AON_STORE2_V  0xFFFFFFFFU
+#define LP_AON_STORE2_S  0
+
+/** LP_AON_STORE3_REG register
+ *  need_des
+ */
+#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
+/** LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE3    0xFFFFFFFFU
+#define LP_AON_STORE3_M  (LP_AON_STORE3_V << LP_AON_STORE3_S)
+#define LP_AON_STORE3_V  0xFFFFFFFFU
+#define LP_AON_STORE3_S  0
+
+/** LP_AON_STORE4_REG register
+ *  need_des
+ */
+#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
+/** LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE4    0xFFFFFFFFU
+#define LP_AON_STORE4_M  (LP_AON_STORE4_V << LP_AON_STORE4_S)
+#define LP_AON_STORE4_V  0xFFFFFFFFU
+#define LP_AON_STORE4_S  0
+
+/** LP_AON_STORE5_REG register
+ *  need_des
+ */
+#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
+/** LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE5    0xFFFFFFFFU
+#define LP_AON_STORE5_M  (LP_AON_STORE5_V << LP_AON_STORE5_S)
+#define LP_AON_STORE5_V  0xFFFFFFFFU
+#define LP_AON_STORE5_S  0
+
+/** LP_AON_STORE6_REG register
+ *  need_des
+ */
+#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
+/** LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE6    0xFFFFFFFFU
+#define LP_AON_STORE6_M  (LP_AON_STORE6_V << LP_AON_STORE6_S)
+#define LP_AON_STORE6_V  0xFFFFFFFFU
+#define LP_AON_STORE6_S  0
+
+/** LP_AON_STORE7_REG register
+ *  need_des
+ */
+#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
+/** LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE7    0xFFFFFFFFU
+#define LP_AON_STORE7_M  (LP_AON_STORE7_V << LP_AON_STORE7_S)
+#define LP_AON_STORE7_V  0xFFFFFFFFU
+#define LP_AON_STORE7_S  0
+
+/** LP_AON_STORE8_REG register
+ *  need_des
+ */
+#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
+/** LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE8    0xFFFFFFFFU
+#define LP_AON_STORE8_M  (LP_AON_STORE8_V << LP_AON_STORE8_S)
+#define LP_AON_STORE8_V  0xFFFFFFFFU
+#define LP_AON_STORE8_S  0
+
+/** LP_AON_STORE9_REG register
+ *  need_des
+ */
+#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
+/** LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_STORE9    0xFFFFFFFFU
+#define LP_AON_STORE9_M  (LP_AON_STORE9_V << LP_AON_STORE9_S)
+#define LP_AON_STORE9_V  0xFFFFFFFFU
+#define LP_AON_STORE9_S  0
+
+/** LP_AON_GPIO_MUX_REG register
+ *  need_des
+ */
+#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
+/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_GPIO_MUX_SEL    0x000000FFU
+#define LP_AON_GPIO_MUX_SEL_M  (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
+#define LP_AON_GPIO_MUX_SEL_V  0x000000FFU
+#define LP_AON_GPIO_MUX_SEL_S  0
+
+/** LP_AON_GPIO_HOLD0_REG register
+ *  need_des
+ */
+#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
+/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_GPIO_HOLD0    0xFFFFFFFFU
+#define LP_AON_GPIO_HOLD0_M  (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
+#define LP_AON_GPIO_HOLD0_V  0xFFFFFFFFU
+#define LP_AON_GPIO_HOLD0_S  0
+
+/** LP_AON_GPIO_HOLD1_REG register
+ *  need_des
+ */
+#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
+/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_GPIO_HOLD1    0xFFFFFFFFU
+#define LP_AON_GPIO_HOLD1_M  (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
+#define LP_AON_GPIO_HOLD1_V  0xFFFFFFFFU
+#define LP_AON_GPIO_HOLD1_S  0
+
+/** LP_AON_SYS_CFG_REG register
+ *  need_des
+ */
+#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
+/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_AON_FORCE_DOWNLOAD_BOOT    (BIT(30))
+#define LP_AON_FORCE_DOWNLOAD_BOOT_M  (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
+#define LP_AON_FORCE_DOWNLOAD_BOOT_V  0x00000001U
+#define LP_AON_FORCE_DOWNLOAD_BOOT_S  30
+/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_AON_HPSYS_SW_RESET    (BIT(31))
+#define LP_AON_HPSYS_SW_RESET_M  (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
+#define LP_AON_HPSYS_SW_RESET_V  0x00000001U
+#define LP_AON_HPSYS_SW_RESET_S  31
+
+/** LP_AON_CPUCORE0_CFG_REG register
+ *  need_des
+ */
+#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
+/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_CPU_CORE0_SW_STALL    0x000000FFU
+#define LP_AON_CPU_CORE0_SW_STALL_M  (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
+#define LP_AON_CPU_CORE0_SW_STALL_V  0x000000FFU
+#define LP_AON_CPU_CORE0_SW_STALL_S  0
+/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_AON_CPU_CORE0_SW_RESET    (BIT(28))
+#define LP_AON_CPU_CORE0_SW_RESET_M  (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
+#define LP_AON_CPU_CORE0_SW_RESET_V  0x00000001U
+#define LP_AON_CPU_CORE0_SW_RESET_S  28
+/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET    (BIT(29))
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M  (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V  0x00000001U
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S  29
+/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL    (BIT(30))
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M  (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V  0x00000001U
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S  30
+/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_AON_CPU_CORE0_DRESET_MASK    (BIT(31))
+#define LP_AON_CPU_CORE0_DRESET_MASK_M  (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
+#define LP_AON_CPU_CORE0_DRESET_MASK_V  0x00000001U
+#define LP_AON_CPU_CORE0_DRESET_MASK_S  31
+
+/** LP_AON_IO_MUX_REG register
+ *  need_des
+ */
+#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
+/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_AON_IO_MUX_RESET_DISABLE    (BIT(31))
+#define LP_AON_IO_MUX_RESET_DISABLE_M  (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
+#define LP_AON_IO_MUX_RESET_DISABLE_V  0x00000001U
+#define LP_AON_IO_MUX_RESET_DISABLE_S  31
+
+/** LP_AON_EXT_WAKEUP_CNTL_REG register
+ *  need_des
+ */
+#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
+/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_EXT_WAKEUP_STATUS    0x000000FFU
+#define LP_AON_EXT_WAKEUP_STATUS_M  (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
+#define LP_AON_EXT_WAKEUP_STATUS_V  0x000000FFU
+#define LP_AON_EXT_WAKEUP_STATUS_S  0
+/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define LP_AON_EXT_WAKEUP_STATUS_CLR    (BIT(14))
+#define LP_AON_EXT_WAKEUP_STATUS_CLR_M  (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
+#define LP_AON_EXT_WAKEUP_STATUS_CLR_V  0x00000001U
+#define LP_AON_EXT_WAKEUP_STATUS_CLR_S  14
+/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
+ *  need_des
+ */
+#define LP_AON_EXT_WAKEUP_SEL    0x000000FFU
+#define LP_AON_EXT_WAKEUP_SEL_M  (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
+#define LP_AON_EXT_WAKEUP_SEL_V  0x000000FFU
+#define LP_AON_EXT_WAKEUP_SEL_S  15
+/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
+ *  need_des
+ */
+#define LP_AON_EXT_WAKEUP_LV    0x000000FFU
+#define LP_AON_EXT_WAKEUP_LV_M  (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
+#define LP_AON_EXT_WAKEUP_LV_V  0x000000FFU
+#define LP_AON_EXT_WAKEUP_LV_S  23
+/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_AON_EXT_WAKEUP_FILTER    (BIT(31))
+#define LP_AON_EXT_WAKEUP_FILTER_M  (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
+#define LP_AON_EXT_WAKEUP_FILTER_V  0x00000001U
+#define LP_AON_EXT_WAKEUP_FILTER_S  31
+
+/** LP_AON_USB_REG register
+ *  need_des
+ */
+#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
+/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_AON_USB_RESET_DISABLE    (BIT(31))
+#define LP_AON_USB_RESET_DISABLE_M  (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
+#define LP_AON_USB_RESET_DISABLE_V  0x00000001U
+#define LP_AON_USB_RESET_DISABLE_S  31
+
+/** LP_AON_LPBUS_REG register
+ *  need_des
+ */
+#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
+/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0;
+ *  This field controls fast memory WPULSE parameter.
+ */
+#define LP_AON_FAST_MEM_WPULSE    0x00000007U
+#define LP_AON_FAST_MEM_WPULSE_M  (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S)
+#define LP_AON_FAST_MEM_WPULSE_V  0x00000007U
+#define LP_AON_FAST_MEM_WPULSE_S  16
+/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4;
+ *  This field controls fast memory WA parameter.
+ */
+#define LP_AON_FAST_MEM_WA    0x00000007U
+#define LP_AON_FAST_MEM_WA_M  (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S)
+#define LP_AON_FAST_MEM_WA_V  0x00000007U
+#define LP_AON_FAST_MEM_WA_S  19
+/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0;
+ *  This field controls fast memory RA parameter.
+ */
+#define LP_AON_FAST_MEM_RA    0x00000003U
+#define LP_AON_FAST_MEM_RA_M  (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S)
+#define LP_AON_FAST_MEM_RA_V  0x00000003U
+#define LP_AON_FAST_MEM_RA_S  22
+/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
+ *  need_des
+ */
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE    (BIT(28))
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M  (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V  0x00000001U
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S  28
+/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
+ *  need_des
+ */
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS    (BIT(29))
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M  (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V  0x00000001U
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S  29
+/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE    (BIT(30))
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M  (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V  0x00000001U
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S  30
+/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define LP_AON_FAST_MEM_MUX_SEL    (BIT(31))
+#define LP_AON_FAST_MEM_MUX_SEL_M  (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
+#define LP_AON_FAST_MEM_MUX_SEL_V  0x00000001U
+#define LP_AON_FAST_MEM_MUX_SEL_S  31
+
+/** LP_AON_SDIO_ACTIVE_REG register
+ *  need_des
+ */
+#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
+/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
+ *  need_des
+ */
+#define LP_AON_SDIO_ACT_DNUM    0x000003FFU
+#define LP_AON_SDIO_ACT_DNUM_M  (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
+#define LP_AON_SDIO_ACT_DNUM_V  0x000003FFU
+#define LP_AON_SDIO_ACT_DNUM_S  22
+
+/** LP_AON_LPCORE_REG register
+ *  need_des
+ */
+#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
+/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR    (BIT(0))
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S  0
+/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG    (BIT(1))
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V  0x00000001U
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S  1
+/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_AON_LPCORE_DISABLE    (BIT(31))
+#define LP_AON_LPCORE_DISABLE_M  (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
+#define LP_AON_LPCORE_DISABLE_V  0x00000001U
+#define LP_AON_LPCORE_DISABLE_S  31
+
+/** LP_AON_SAR_CCT_REG register
+ *  need_des
+ */
+#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
+/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
+ *  need_des
+ */
+#define LP_AON_SAR2_PWDET_CCT    0x00000007U
+#define LP_AON_SAR2_PWDET_CCT_M  (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
+#define LP_AON_SAR2_PWDET_CCT_V  0x00000007U
+#define LP_AON_SAR2_PWDET_CCT_S  29
+
+/** LP_AON_DATE_REG register
+ *  need_des
+ */
+#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
+/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704;
+ *  need_des
+ */
+#define LP_AON_DATE    0x7FFFFFFFU
+#define LP_AON_DATE_M  (LP_AON_DATE_V << LP_AON_DATE_S)
+#define LP_AON_DATE_V  0x7FFFFFFFU
+#define LP_AON_DATE_S  0
+/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_AON_CLK_EN    (BIT(31))
+#define LP_AON_CLK_EN_M  (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
+#define LP_AON_CLK_EN_V  0x00000001U
+#define LP_AON_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_aon_struct.h b/components/soc/esp32p4/include/soc/lp_aon_struct.h
new file mode 100644
index 0000000000..372d3b06ea
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_aon_struct.h
@@ -0,0 +1,306 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of store register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** store : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t store:32;
+    };
+    uint32_t val;
+} lp_aon_store_reg_t;
+
+/** Type of gpio_mux register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t gpio_mux_sel:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_aon_gpio_mux_reg_t;
+
+/** Type of gpio_hold0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t gpio_hold0:32;
+    };
+    uint32_t val;
+} lp_aon_gpio_hold0_reg_t;
+
+/** Type of gpio_hold1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t gpio_hold1:32;
+    };
+    uint32_t val;
+} lp_aon_gpio_hold1_reg_t;
+
+/** Type of sys_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** force_download_boot : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t force_download_boot:1;
+        /** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hpsys_sw_reset:1;
+    };
+    uint32_t val;
+} lp_aon_sys_cfg_reg_t;
+
+/** Type of cpucore0_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_core0_sw_stall:8;
+        uint32_t reserved_8:20;
+        /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_core0_sw_reset:1;
+        /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_core0_ocd_halt_on_reset:1;
+        /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_core0_stat_vector_sel:1;
+        /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_core0_dreset_mask:1;
+    };
+    uint32_t val;
+} lp_aon_cpucore0_cfg_reg_t;
+
+/** Type of io_mux register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t io_mux_reset_disable:1;
+    };
+    uint32_t val;
+} lp_aon_io_mux_reg_t;
+
+/** Type of ext_wakeup_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_status:8;
+        uint32_t reserved_8:6;
+        /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_status_clr:1;
+        /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_sel:8;
+        /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_lv:8;
+        /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_filter:1;
+    };
+    uint32_t val;
+} lp_aon_ext_wakeup_cntl_reg_t;
+
+/** Type of usb register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** usb_reset_disable : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t usb_reset_disable:1;
+    };
+    uint32_t val;
+} lp_aon_usb_reg_t;
+
+/** Type of lpbus register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0;
+         *  This field controls fast memory WPULSE parameter.
+         */
+        uint32_t fast_mem_wpulse:3;
+        /** fast_mem_wa : R/W; bitpos: [21:19]; default: 4;
+         *  This field controls fast memory WA parameter.
+         */
+        uint32_t fast_mem_wa:3;
+        /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0;
+         *  This field controls fast memory RA parameter.
+         */
+        uint32_t fast_mem_ra:2;
+        uint32_t reserved_24:4;
+        /** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_mem_mux_fsm_idle:1;
+        /** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_mem_mux_sel_status:1;
+        /** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t fast_mem_mux_sel_update:1;
+        /** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_mem_mux_sel:1;
+    };
+    uint32_t val;
+} lp_aon_lpbus_reg_t;
+
+/** Type of sdio_active register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
+         *  need_des
+         */
+        uint32_t sdio_act_dnum:10;
+    };
+    uint32_t val;
+} lp_aon_sdio_active_reg_t;
+
+/** Type of lpcore register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_etm_wakeup_flag_clr:1;
+        /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_etm_wakeup_flag:1;
+        uint32_t reserved_2:29;
+        /** lpcore_disable : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_disable:1;
+    };
+    uint32_t val;
+} lp_aon_lpcore_reg_t;
+
+/** Type of sar_cct register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_pwdet_cct:3;
+    };
+    uint32_t val;
+} lp_aon_sar_cct_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 35672704;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_aon_date_reg_t;
+
+
+typedef struct lp_aon_dev_t {
+    volatile lp_aon_store_reg_t store[10];
+    volatile lp_aon_gpio_mux_reg_t gpio_mux;
+    volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
+    volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
+    volatile lp_aon_sys_cfg_reg_t sys_cfg;
+    volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
+    volatile lp_aon_io_mux_reg_t io_mux;
+    volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
+    volatile lp_aon_usb_reg_t usb;
+    volatile lp_aon_lpbus_reg_t lpbus;
+    volatile lp_aon_sdio_active_reg_t sdio_active;
+    volatile lp_aon_lpcore_reg_t lpcore;
+    volatile lp_aon_sar_cct_reg_t sar_cct;
+    uint32_t reserved_058[233];
+    volatile lp_aon_date_reg_t date;
+} lp_aon_dev_t;
+
+extern lp_aon_dev_t LP_AON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm0_reg.h b/components/soc/esp32p4/include/soc/lp_apm0_reg.h
new file mode 100644
index 0000000000..495cc35ba2
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_apm0_reg.h
@@ -0,0 +1,506 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_APM0_REGION_FILTER_EN_REG register
+ *  Region filter enable register
+ */
+#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
+/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
+ *  Region filter enable
+ */
+#define LP_APM0_REGION_FILTER_EN    0x0000000FU
+#define LP_APM0_REGION_FILTER_EN_M  (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
+#define LP_APM0_REGION_FILTER_EN_V  0x0000000FU
+#define LP_APM0_REGION_FILTER_EN_S  0
+
+/** LP_APM0_REGION0_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
+/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region0
+ */
+#define LP_APM0_REGION0_ADDR_START    0xFFFFFFFFU
+#define LP_APM0_REGION0_ADDR_START_M  (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
+#define LP_APM0_REGION0_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM0_REGION0_ADDR_START_S  0
+
+/** LP_APM0_REGION0_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
+/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region0
+ */
+#define LP_APM0_REGION0_ADDR_END    0xFFFFFFFFU
+#define LP_APM0_REGION0_ADDR_END_M  (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
+#define LP_APM0_REGION0_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM0_REGION0_ADDR_END_S  0
+
+/** LP_APM0_REGION0_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
+/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM0_REGION0_R0_PMS_X    (BIT(0))
+#define LP_APM0_REGION0_R0_PMS_X_M  (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S)
+#define LP_APM0_REGION0_R0_PMS_X_V  0x00000001U
+#define LP_APM0_REGION0_R0_PMS_X_S  0
+/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM0_REGION0_R0_PMS_W    (BIT(1))
+#define LP_APM0_REGION0_R0_PMS_W_M  (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S)
+#define LP_APM0_REGION0_R0_PMS_W_V  0x00000001U
+#define LP_APM0_REGION0_R0_PMS_W_S  1
+/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM0_REGION0_R0_PMS_R    (BIT(2))
+#define LP_APM0_REGION0_R0_PMS_R_M  (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S)
+#define LP_APM0_REGION0_R0_PMS_R_V  0x00000001U
+#define LP_APM0_REGION0_R0_PMS_R_S  2
+/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM0_REGION0_R1_PMS_X    (BIT(4))
+#define LP_APM0_REGION0_R1_PMS_X_M  (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S)
+#define LP_APM0_REGION0_R1_PMS_X_V  0x00000001U
+#define LP_APM0_REGION0_R1_PMS_X_S  4
+/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM0_REGION0_R1_PMS_W    (BIT(5))
+#define LP_APM0_REGION0_R1_PMS_W_M  (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S)
+#define LP_APM0_REGION0_R1_PMS_W_V  0x00000001U
+#define LP_APM0_REGION0_R1_PMS_W_S  5
+/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM0_REGION0_R1_PMS_R    (BIT(6))
+#define LP_APM0_REGION0_R1_PMS_R_M  (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S)
+#define LP_APM0_REGION0_R1_PMS_R_V  0x00000001U
+#define LP_APM0_REGION0_R1_PMS_R_S  6
+/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM0_REGION0_R2_PMS_X    (BIT(8))
+#define LP_APM0_REGION0_R2_PMS_X_M  (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S)
+#define LP_APM0_REGION0_R2_PMS_X_V  0x00000001U
+#define LP_APM0_REGION0_R2_PMS_X_S  8
+/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM0_REGION0_R2_PMS_W    (BIT(9))
+#define LP_APM0_REGION0_R2_PMS_W_M  (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S)
+#define LP_APM0_REGION0_R2_PMS_W_V  0x00000001U
+#define LP_APM0_REGION0_R2_PMS_W_S  9
+/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM0_REGION0_R2_PMS_R    (BIT(10))
+#define LP_APM0_REGION0_R2_PMS_R_M  (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S)
+#define LP_APM0_REGION0_R2_PMS_R_V  0x00000001U
+#define LP_APM0_REGION0_R2_PMS_R_S  10
+
+/** LP_APM0_REGION1_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
+/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region1
+ */
+#define LP_APM0_REGION1_ADDR_START    0xFFFFFFFFU
+#define LP_APM0_REGION1_ADDR_START_M  (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
+#define LP_APM0_REGION1_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM0_REGION1_ADDR_START_S  0
+
+/** LP_APM0_REGION1_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
+/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region1
+ */
+#define LP_APM0_REGION1_ADDR_END    0xFFFFFFFFU
+#define LP_APM0_REGION1_ADDR_END_M  (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
+#define LP_APM0_REGION1_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM0_REGION1_ADDR_END_S  0
+
+/** LP_APM0_REGION1_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
+/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM0_REGION1_R0_PMS_X    (BIT(0))
+#define LP_APM0_REGION1_R0_PMS_X_M  (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S)
+#define LP_APM0_REGION1_R0_PMS_X_V  0x00000001U
+#define LP_APM0_REGION1_R0_PMS_X_S  0
+/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM0_REGION1_R0_PMS_W    (BIT(1))
+#define LP_APM0_REGION1_R0_PMS_W_M  (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S)
+#define LP_APM0_REGION1_R0_PMS_W_V  0x00000001U
+#define LP_APM0_REGION1_R0_PMS_W_S  1
+/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM0_REGION1_R0_PMS_R    (BIT(2))
+#define LP_APM0_REGION1_R0_PMS_R_M  (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S)
+#define LP_APM0_REGION1_R0_PMS_R_V  0x00000001U
+#define LP_APM0_REGION1_R0_PMS_R_S  2
+/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM0_REGION1_R1_PMS_X    (BIT(4))
+#define LP_APM0_REGION1_R1_PMS_X_M  (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S)
+#define LP_APM0_REGION1_R1_PMS_X_V  0x00000001U
+#define LP_APM0_REGION1_R1_PMS_X_S  4
+/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM0_REGION1_R1_PMS_W    (BIT(5))
+#define LP_APM0_REGION1_R1_PMS_W_M  (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S)
+#define LP_APM0_REGION1_R1_PMS_W_V  0x00000001U
+#define LP_APM0_REGION1_R1_PMS_W_S  5
+/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM0_REGION1_R1_PMS_R    (BIT(6))
+#define LP_APM0_REGION1_R1_PMS_R_M  (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S)
+#define LP_APM0_REGION1_R1_PMS_R_V  0x00000001U
+#define LP_APM0_REGION1_R1_PMS_R_S  6
+/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM0_REGION1_R2_PMS_X    (BIT(8))
+#define LP_APM0_REGION1_R2_PMS_X_M  (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S)
+#define LP_APM0_REGION1_R2_PMS_X_V  0x00000001U
+#define LP_APM0_REGION1_R2_PMS_X_S  8
+/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM0_REGION1_R2_PMS_W    (BIT(9))
+#define LP_APM0_REGION1_R2_PMS_W_M  (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S)
+#define LP_APM0_REGION1_R2_PMS_W_V  0x00000001U
+#define LP_APM0_REGION1_R2_PMS_W_S  9
+/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM0_REGION1_R2_PMS_R    (BIT(10))
+#define LP_APM0_REGION1_R2_PMS_R_M  (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S)
+#define LP_APM0_REGION1_R2_PMS_R_V  0x00000001U
+#define LP_APM0_REGION1_R2_PMS_R_S  10
+
+/** LP_APM0_REGION2_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
+/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region2
+ */
+#define LP_APM0_REGION2_ADDR_START    0xFFFFFFFFU
+#define LP_APM0_REGION2_ADDR_START_M  (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
+#define LP_APM0_REGION2_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM0_REGION2_ADDR_START_S  0
+
+/** LP_APM0_REGION2_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
+/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region2
+ */
+#define LP_APM0_REGION2_ADDR_END    0xFFFFFFFFU
+#define LP_APM0_REGION2_ADDR_END_M  (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
+#define LP_APM0_REGION2_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM0_REGION2_ADDR_END_S  0
+
+/** LP_APM0_REGION2_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
+/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM0_REGION2_R0_PMS_X    (BIT(0))
+#define LP_APM0_REGION2_R0_PMS_X_M  (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S)
+#define LP_APM0_REGION2_R0_PMS_X_V  0x00000001U
+#define LP_APM0_REGION2_R0_PMS_X_S  0
+/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM0_REGION2_R0_PMS_W    (BIT(1))
+#define LP_APM0_REGION2_R0_PMS_W_M  (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S)
+#define LP_APM0_REGION2_R0_PMS_W_V  0x00000001U
+#define LP_APM0_REGION2_R0_PMS_W_S  1
+/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM0_REGION2_R0_PMS_R    (BIT(2))
+#define LP_APM0_REGION2_R0_PMS_R_M  (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S)
+#define LP_APM0_REGION2_R0_PMS_R_V  0x00000001U
+#define LP_APM0_REGION2_R0_PMS_R_S  2
+/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM0_REGION2_R1_PMS_X    (BIT(4))
+#define LP_APM0_REGION2_R1_PMS_X_M  (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S)
+#define LP_APM0_REGION2_R1_PMS_X_V  0x00000001U
+#define LP_APM0_REGION2_R1_PMS_X_S  4
+/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM0_REGION2_R1_PMS_W    (BIT(5))
+#define LP_APM0_REGION2_R1_PMS_W_M  (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S)
+#define LP_APM0_REGION2_R1_PMS_W_V  0x00000001U
+#define LP_APM0_REGION2_R1_PMS_W_S  5
+/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM0_REGION2_R1_PMS_R    (BIT(6))
+#define LP_APM0_REGION2_R1_PMS_R_M  (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S)
+#define LP_APM0_REGION2_R1_PMS_R_V  0x00000001U
+#define LP_APM0_REGION2_R1_PMS_R_S  6
+/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM0_REGION2_R2_PMS_X    (BIT(8))
+#define LP_APM0_REGION2_R2_PMS_X_M  (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S)
+#define LP_APM0_REGION2_R2_PMS_X_V  0x00000001U
+#define LP_APM0_REGION2_R2_PMS_X_S  8
+/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM0_REGION2_R2_PMS_W    (BIT(9))
+#define LP_APM0_REGION2_R2_PMS_W_M  (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S)
+#define LP_APM0_REGION2_R2_PMS_W_V  0x00000001U
+#define LP_APM0_REGION2_R2_PMS_W_S  9
+/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM0_REGION2_R2_PMS_R    (BIT(10))
+#define LP_APM0_REGION2_R2_PMS_R_M  (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S)
+#define LP_APM0_REGION2_R2_PMS_R_V  0x00000001U
+#define LP_APM0_REGION2_R2_PMS_R_S  10
+
+/** LP_APM0_REGION3_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
+/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region3
+ */
+#define LP_APM0_REGION3_ADDR_START    0xFFFFFFFFU
+#define LP_APM0_REGION3_ADDR_START_M  (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
+#define LP_APM0_REGION3_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM0_REGION3_ADDR_START_S  0
+
+/** LP_APM0_REGION3_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
+/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region3
+ */
+#define LP_APM0_REGION3_ADDR_END    0xFFFFFFFFU
+#define LP_APM0_REGION3_ADDR_END_M  (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
+#define LP_APM0_REGION3_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM0_REGION3_ADDR_END_S  0
+
+/** LP_APM0_REGION3_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
+/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM0_REGION3_R0_PMS_X    (BIT(0))
+#define LP_APM0_REGION3_R0_PMS_X_M  (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S)
+#define LP_APM0_REGION3_R0_PMS_X_V  0x00000001U
+#define LP_APM0_REGION3_R0_PMS_X_S  0
+/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM0_REGION3_R0_PMS_W    (BIT(1))
+#define LP_APM0_REGION3_R0_PMS_W_M  (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S)
+#define LP_APM0_REGION3_R0_PMS_W_V  0x00000001U
+#define LP_APM0_REGION3_R0_PMS_W_S  1
+/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM0_REGION3_R0_PMS_R    (BIT(2))
+#define LP_APM0_REGION3_R0_PMS_R_M  (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S)
+#define LP_APM0_REGION3_R0_PMS_R_V  0x00000001U
+#define LP_APM0_REGION3_R0_PMS_R_S  2
+/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM0_REGION3_R1_PMS_X    (BIT(4))
+#define LP_APM0_REGION3_R1_PMS_X_M  (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S)
+#define LP_APM0_REGION3_R1_PMS_X_V  0x00000001U
+#define LP_APM0_REGION3_R1_PMS_X_S  4
+/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM0_REGION3_R1_PMS_W    (BIT(5))
+#define LP_APM0_REGION3_R1_PMS_W_M  (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S)
+#define LP_APM0_REGION3_R1_PMS_W_V  0x00000001U
+#define LP_APM0_REGION3_R1_PMS_W_S  5
+/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM0_REGION3_R1_PMS_R    (BIT(6))
+#define LP_APM0_REGION3_R1_PMS_R_M  (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S)
+#define LP_APM0_REGION3_R1_PMS_R_V  0x00000001U
+#define LP_APM0_REGION3_R1_PMS_R_S  6
+/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM0_REGION3_R2_PMS_X    (BIT(8))
+#define LP_APM0_REGION3_R2_PMS_X_M  (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S)
+#define LP_APM0_REGION3_R2_PMS_X_V  0x00000001U
+#define LP_APM0_REGION3_R2_PMS_X_S  8
+/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM0_REGION3_R2_PMS_W    (BIT(9))
+#define LP_APM0_REGION3_R2_PMS_W_M  (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S)
+#define LP_APM0_REGION3_R2_PMS_W_V  0x00000001U
+#define LP_APM0_REGION3_R2_PMS_W_S  9
+/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM0_REGION3_R2_PMS_R    (BIT(10))
+#define LP_APM0_REGION3_R2_PMS_R_M  (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S)
+#define LP_APM0_REGION3_R2_PMS_R_V  0x00000001U
+#define LP_APM0_REGION3_R2_PMS_R_S  10
+
+/** LP_APM0_FUNC_CTRL_REG register
+ *  PMS function control register
+ */
+#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
+/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
+ *  PMS M0 function enable
+ */
+#define LP_APM0_M0_PMS_FUNC_EN    (BIT(0))
+#define LP_APM0_M0_PMS_FUNC_EN_M  (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S)
+#define LP_APM0_M0_PMS_FUNC_EN_V  0x00000001U
+#define LP_APM0_M0_PMS_FUNC_EN_S  0
+
+/** LP_APM0_M0_STATUS_REG register
+ *  M0 status register
+ */
+#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
+/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Exception status
+ */
+#define LP_APM0_M0_EXCEPTION_STATUS    0x00000003U
+#define LP_APM0_M0_EXCEPTION_STATUS_M  (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
+#define LP_APM0_M0_EXCEPTION_STATUS_V  0x00000003U
+#define LP_APM0_M0_EXCEPTION_STATUS_S  0
+
+/** LP_APM0_M0_STATUS_CLR_REG register
+ *  M0 status clear register
+ */
+#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
+/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear exception status
+ */
+#define LP_APM0_M0_REGION_STATUS_CLR    (BIT(0))
+#define LP_APM0_M0_REGION_STATUS_CLR_M  (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S)
+#define LP_APM0_M0_REGION_STATUS_CLR_V  0x00000001U
+#define LP_APM0_M0_REGION_STATUS_CLR_S  0
+
+/** LP_APM0_M0_EXCEPTION_INFO0_REG register
+ *  M0 exception_info0 register
+ */
+#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
+/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
+ *  Exception region
+ */
+#define LP_APM0_M0_EXCEPTION_REGION    0x0000000FU
+#define LP_APM0_M0_EXCEPTION_REGION_M  (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
+#define LP_APM0_M0_EXCEPTION_REGION_V  0x0000000FU
+#define LP_APM0_M0_EXCEPTION_REGION_S  0
+/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Exception mode
+ */
+#define LP_APM0_M0_EXCEPTION_MODE    0x00000003U
+#define LP_APM0_M0_EXCEPTION_MODE_M  (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
+#define LP_APM0_M0_EXCEPTION_MODE_V  0x00000003U
+#define LP_APM0_M0_EXCEPTION_MODE_S  16
+/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Exception id information
+ */
+#define LP_APM0_M0_EXCEPTION_ID    0x0000001FU
+#define LP_APM0_M0_EXCEPTION_ID_M  (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
+#define LP_APM0_M0_EXCEPTION_ID_V  0x0000001FU
+#define LP_APM0_M0_EXCEPTION_ID_S  18
+
+/** LP_APM0_M0_EXCEPTION_INFO1_REG register
+ *  M0 exception_info1 register
+ */
+#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
+/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Exception addr
+ */
+#define LP_APM0_M0_EXCEPTION_ADDR    0xFFFFFFFFU
+#define LP_APM0_M0_EXCEPTION_ADDR_M  (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
+#define LP_APM0_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define LP_APM0_M0_EXCEPTION_ADDR_S  0
+
+/** LP_APM0_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
+/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  APM M0 interrupt enable
+ */
+#define LP_APM0_M0_APM_INT_EN    (BIT(0))
+#define LP_APM0_M0_APM_INT_EN_M  (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
+#define LP_APM0_M0_APM_INT_EN_V  0x00000001U
+#define LP_APM0_M0_APM_INT_EN_S  0
+
+/** LP_APM0_CLOCK_GATE_REG register
+ *  clock gating register
+ */
+#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
+/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reg_clk_en
+ */
+#define LP_APM0_CLK_EN    (BIT(0))
+#define LP_APM0_CLK_EN_M  (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
+#define LP_APM0_CLK_EN_V  0x00000001U
+#define LP_APM0_CLK_EN_S  0
+
+/** LP_APM0_DATE_REG register
+ *  Version register
+ */
+#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
+/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640;
+ *  reg_date
+ */
+#define LP_APM0_DATE    0x0FFFFFFFU
+#define LP_APM0_DATE_M  (LP_APM0_DATE_V << LP_APM0_DATE_S)
+#define LP_APM0_DATE_V  0x0FFFFFFFU
+#define LP_APM0_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm0_struct.h b/components/soc/esp32p4/include/soc/lp_apm0_struct.h
new file mode 100644
index 0000000000..79939b7b37
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_apm0_struct.h
@@ -0,0 +1,499 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Region filter enable register */
+/** Type of region_filter_en register
+ *  Region filter enable register
+ */
+typedef union {
+    struct {
+        /** region_filter_en : R/W; bitpos: [3:0]; default: 1;
+         *  Region filter enable
+         */
+        uint32_t region_filter_en:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_apm0_region_filter_en_reg_t;
+
+
+/** Group: Region address register */
+/** Type of region0_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region0
+         */
+        uint32_t region0_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm0_region0_addr_start_reg_t;
+
+/** Type of region0_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region0
+         */
+        uint32_t region0_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm0_region0_addr_end_reg_t;
+
+/** Type of region1_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region1
+         */
+        uint32_t region1_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm0_region1_addr_start_reg_t;
+
+/** Type of region1_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region1
+         */
+        uint32_t region1_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm0_region1_addr_end_reg_t;
+
+/** Type of region2_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region2
+         */
+        uint32_t region2_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm0_region2_addr_start_reg_t;
+
+/** Type of region2_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region2
+         */
+        uint32_t region2_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm0_region2_addr_end_reg_t;
+
+/** Type of region3_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region3
+         */
+        uint32_t region3_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm0_region3_addr_start_reg_t;
+
+/** Type of region3_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region3
+         */
+        uint32_t region3_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm0_region3_addr_end_reg_t;
+
+
+/** Group: Region access authority attribute register */
+/** Type of region0_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_x:1;
+        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_w:1;
+        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_x:1;
+        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_w:1;
+        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_x:1;
+        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_w:1;
+        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm0_region0_pms_attr_reg_t;
+
+/** Type of region1_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_x:1;
+        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_w:1;
+        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_x:1;
+        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_w:1;
+        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_x:1;
+        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_w:1;
+        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm0_region1_pms_attr_reg_t;
+
+/** Type of region2_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_x:1;
+        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_w:1;
+        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_x:1;
+        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_w:1;
+        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_x:1;
+        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_w:1;
+        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm0_region2_pms_attr_reg_t;
+
+/** Type of region3_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_x:1;
+        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_w:1;
+        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_x:1;
+        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_w:1;
+        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_x:1;
+        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_w:1;
+        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm0_region3_pms_attr_reg_t;
+
+
+/** Group: PMS function control register */
+/** Type of func_ctrl register
+ *  PMS function control register
+ */
+typedef union {
+    struct {
+        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
+         *  PMS M0 function enable
+         */
+        uint32_t m0_pms_func_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_apm0_func_ctrl_reg_t;
+
+
+/** Group: M0 status register */
+/** Type of m0_status register
+ *  M0 status register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Exception status
+         */
+        uint32_t m0_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_apm0_m0_status_reg_t;
+
+
+/** Group: M0 status clear register */
+/** Type of m0_status_clr register
+ *  M0 status clear register
+ */
+typedef union {
+    struct {
+        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
+         *  Clear exception status
+         */
+        uint32_t m0_region_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_apm0_m0_status_clr_reg_t;
+
+
+/** Group: M0 exception_info0 register */
+/** Type of m0_exception_info0 register
+ *  M0 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_region : RO; bitpos: [3:0]; default: 0;
+         *  Exception region
+         */
+        uint32_t m0_exception_region:4;
+        uint32_t reserved_4:12;
+        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Exception mode
+         */
+        uint32_t m0_exception_mode:2;
+        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Exception id information
+         */
+        uint32_t m0_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_apm0_m0_exception_info0_reg_t;
+
+
+/** Group: M0 exception_info1 register */
+/** Type of m0_exception_info1 register
+ *  M0 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Exception addr
+         */
+        uint32_t m0_exception_addr:32;
+    };
+    uint32_t val;
+} lp_apm0_m0_exception_info1_reg_t;
+
+
+/** Group: APM interrupt enable register */
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
+         *  APM M0 interrupt enable
+         */
+        uint32_t m0_apm_int_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_apm0_int_en_reg_t;
+
+
+/** Group: clock gating register */
+/** Type of clock_gate register
+ *  clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reg_clk_en
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_apm0_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35672640;
+         *  reg_date
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_apm0_date_reg_t;
+
+
+typedef struct lp_apm0_dev_t {
+    volatile lp_apm0_region_filter_en_reg_t region_filter_en;
+    volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
+    volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
+    volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr;
+    volatile lp_apm0_region1_addr_start_reg_t region1_addr_start;
+    volatile lp_apm0_region1_addr_end_reg_t region1_addr_end;
+    volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr;
+    volatile lp_apm0_region2_addr_start_reg_t region2_addr_start;
+    volatile lp_apm0_region2_addr_end_reg_t region2_addr_end;
+    volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr;
+    volatile lp_apm0_region3_addr_start_reg_t region3_addr_start;
+    volatile lp_apm0_region3_addr_end_reg_t region3_addr_end;
+    volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr;
+    uint32_t reserved_034[36];
+    volatile lp_apm0_func_ctrl_reg_t func_ctrl;
+    volatile lp_apm0_m0_status_reg_t m0_status;
+    volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
+    volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
+    volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
+    volatile lp_apm0_int_en_reg_t int_en;
+    volatile lp_apm0_clock_gate_reg_t clock_gate;
+    uint32_t reserved_0e0[455];
+    volatile lp_apm0_date_reg_t date;
+} lp_apm0_dev_t;
+
+extern lp_apm0_dev_t LP_APM0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm_reg.h b/components/soc/esp32p4/include/soc/lp_apm_reg.h
new file mode 100644
index 0000000000..30b6038345
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_apm_reg.h
@@ -0,0 +1,582 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_APM_REGION_FILTER_EN_REG register
+ *  Region filter enable register
+ */
+#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
+/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
+ *  Region filter enable
+ */
+#define LP_APM_REGION_FILTER_EN    0x0000000FU
+#define LP_APM_REGION_FILTER_EN_M  (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
+#define LP_APM_REGION_FILTER_EN_V  0x0000000FU
+#define LP_APM_REGION_FILTER_EN_S  0
+
+/** LP_APM_REGION0_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
+/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region0
+ */
+#define LP_APM_REGION0_ADDR_START    0xFFFFFFFFU
+#define LP_APM_REGION0_ADDR_START_M  (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
+#define LP_APM_REGION0_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM_REGION0_ADDR_START_S  0
+
+/** LP_APM_REGION0_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
+/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region0
+ */
+#define LP_APM_REGION0_ADDR_END    0xFFFFFFFFU
+#define LP_APM_REGION0_ADDR_END_M  (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
+#define LP_APM_REGION0_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM_REGION0_ADDR_END_S  0
+
+/** LP_APM_REGION0_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
+/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM_REGION0_R0_PMS_X    (BIT(0))
+#define LP_APM_REGION0_R0_PMS_X_M  (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
+#define LP_APM_REGION0_R0_PMS_X_V  0x00000001U
+#define LP_APM_REGION0_R0_PMS_X_S  0
+/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM_REGION0_R0_PMS_W    (BIT(1))
+#define LP_APM_REGION0_R0_PMS_W_M  (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
+#define LP_APM_REGION0_R0_PMS_W_V  0x00000001U
+#define LP_APM_REGION0_R0_PMS_W_S  1
+/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM_REGION0_R0_PMS_R    (BIT(2))
+#define LP_APM_REGION0_R0_PMS_R_M  (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
+#define LP_APM_REGION0_R0_PMS_R_V  0x00000001U
+#define LP_APM_REGION0_R0_PMS_R_S  2
+/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM_REGION0_R1_PMS_X    (BIT(4))
+#define LP_APM_REGION0_R1_PMS_X_M  (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
+#define LP_APM_REGION0_R1_PMS_X_V  0x00000001U
+#define LP_APM_REGION0_R1_PMS_X_S  4
+/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM_REGION0_R1_PMS_W    (BIT(5))
+#define LP_APM_REGION0_R1_PMS_W_M  (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
+#define LP_APM_REGION0_R1_PMS_W_V  0x00000001U
+#define LP_APM_REGION0_R1_PMS_W_S  5
+/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM_REGION0_R1_PMS_R    (BIT(6))
+#define LP_APM_REGION0_R1_PMS_R_M  (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
+#define LP_APM_REGION0_R1_PMS_R_V  0x00000001U
+#define LP_APM_REGION0_R1_PMS_R_S  6
+/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM_REGION0_R2_PMS_X    (BIT(8))
+#define LP_APM_REGION0_R2_PMS_X_M  (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
+#define LP_APM_REGION0_R2_PMS_X_V  0x00000001U
+#define LP_APM_REGION0_R2_PMS_X_S  8
+/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM_REGION0_R2_PMS_W    (BIT(9))
+#define LP_APM_REGION0_R2_PMS_W_M  (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
+#define LP_APM_REGION0_R2_PMS_W_V  0x00000001U
+#define LP_APM_REGION0_R2_PMS_W_S  9
+/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM_REGION0_R2_PMS_R    (BIT(10))
+#define LP_APM_REGION0_R2_PMS_R_M  (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
+#define LP_APM_REGION0_R2_PMS_R_V  0x00000001U
+#define LP_APM_REGION0_R2_PMS_R_S  10
+
+/** LP_APM_REGION1_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
+/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region1
+ */
+#define LP_APM_REGION1_ADDR_START    0xFFFFFFFFU
+#define LP_APM_REGION1_ADDR_START_M  (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
+#define LP_APM_REGION1_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM_REGION1_ADDR_START_S  0
+
+/** LP_APM_REGION1_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
+/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region1
+ */
+#define LP_APM_REGION1_ADDR_END    0xFFFFFFFFU
+#define LP_APM_REGION1_ADDR_END_M  (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
+#define LP_APM_REGION1_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM_REGION1_ADDR_END_S  0
+
+/** LP_APM_REGION1_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
+/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM_REGION1_R0_PMS_X    (BIT(0))
+#define LP_APM_REGION1_R0_PMS_X_M  (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
+#define LP_APM_REGION1_R0_PMS_X_V  0x00000001U
+#define LP_APM_REGION1_R0_PMS_X_S  0
+/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM_REGION1_R0_PMS_W    (BIT(1))
+#define LP_APM_REGION1_R0_PMS_W_M  (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
+#define LP_APM_REGION1_R0_PMS_W_V  0x00000001U
+#define LP_APM_REGION1_R0_PMS_W_S  1
+/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM_REGION1_R0_PMS_R    (BIT(2))
+#define LP_APM_REGION1_R0_PMS_R_M  (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
+#define LP_APM_REGION1_R0_PMS_R_V  0x00000001U
+#define LP_APM_REGION1_R0_PMS_R_S  2
+/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM_REGION1_R1_PMS_X    (BIT(4))
+#define LP_APM_REGION1_R1_PMS_X_M  (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
+#define LP_APM_REGION1_R1_PMS_X_V  0x00000001U
+#define LP_APM_REGION1_R1_PMS_X_S  4
+/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM_REGION1_R1_PMS_W    (BIT(5))
+#define LP_APM_REGION1_R1_PMS_W_M  (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
+#define LP_APM_REGION1_R1_PMS_W_V  0x00000001U
+#define LP_APM_REGION1_R1_PMS_W_S  5
+/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM_REGION1_R1_PMS_R    (BIT(6))
+#define LP_APM_REGION1_R1_PMS_R_M  (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
+#define LP_APM_REGION1_R1_PMS_R_V  0x00000001U
+#define LP_APM_REGION1_R1_PMS_R_S  6
+/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM_REGION1_R2_PMS_X    (BIT(8))
+#define LP_APM_REGION1_R2_PMS_X_M  (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
+#define LP_APM_REGION1_R2_PMS_X_V  0x00000001U
+#define LP_APM_REGION1_R2_PMS_X_S  8
+/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM_REGION1_R2_PMS_W    (BIT(9))
+#define LP_APM_REGION1_R2_PMS_W_M  (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
+#define LP_APM_REGION1_R2_PMS_W_V  0x00000001U
+#define LP_APM_REGION1_R2_PMS_W_S  9
+/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM_REGION1_R2_PMS_R    (BIT(10))
+#define LP_APM_REGION1_R2_PMS_R_M  (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
+#define LP_APM_REGION1_R2_PMS_R_V  0x00000001U
+#define LP_APM_REGION1_R2_PMS_R_S  10
+
+/** LP_APM_REGION2_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
+/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region2
+ */
+#define LP_APM_REGION2_ADDR_START    0xFFFFFFFFU
+#define LP_APM_REGION2_ADDR_START_M  (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
+#define LP_APM_REGION2_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM_REGION2_ADDR_START_S  0
+
+/** LP_APM_REGION2_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
+/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region2
+ */
+#define LP_APM_REGION2_ADDR_END    0xFFFFFFFFU
+#define LP_APM_REGION2_ADDR_END_M  (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
+#define LP_APM_REGION2_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM_REGION2_ADDR_END_S  0
+
+/** LP_APM_REGION2_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
+/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM_REGION2_R0_PMS_X    (BIT(0))
+#define LP_APM_REGION2_R0_PMS_X_M  (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
+#define LP_APM_REGION2_R0_PMS_X_V  0x00000001U
+#define LP_APM_REGION2_R0_PMS_X_S  0
+/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM_REGION2_R0_PMS_W    (BIT(1))
+#define LP_APM_REGION2_R0_PMS_W_M  (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
+#define LP_APM_REGION2_R0_PMS_W_V  0x00000001U
+#define LP_APM_REGION2_R0_PMS_W_S  1
+/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM_REGION2_R0_PMS_R    (BIT(2))
+#define LP_APM_REGION2_R0_PMS_R_M  (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
+#define LP_APM_REGION2_R0_PMS_R_V  0x00000001U
+#define LP_APM_REGION2_R0_PMS_R_S  2
+/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM_REGION2_R1_PMS_X    (BIT(4))
+#define LP_APM_REGION2_R1_PMS_X_M  (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
+#define LP_APM_REGION2_R1_PMS_X_V  0x00000001U
+#define LP_APM_REGION2_R1_PMS_X_S  4
+/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM_REGION2_R1_PMS_W    (BIT(5))
+#define LP_APM_REGION2_R1_PMS_W_M  (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
+#define LP_APM_REGION2_R1_PMS_W_V  0x00000001U
+#define LP_APM_REGION2_R1_PMS_W_S  5
+/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM_REGION2_R1_PMS_R    (BIT(6))
+#define LP_APM_REGION2_R1_PMS_R_M  (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
+#define LP_APM_REGION2_R1_PMS_R_V  0x00000001U
+#define LP_APM_REGION2_R1_PMS_R_S  6
+/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM_REGION2_R2_PMS_X    (BIT(8))
+#define LP_APM_REGION2_R2_PMS_X_M  (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
+#define LP_APM_REGION2_R2_PMS_X_V  0x00000001U
+#define LP_APM_REGION2_R2_PMS_X_S  8
+/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM_REGION2_R2_PMS_W    (BIT(9))
+#define LP_APM_REGION2_R2_PMS_W_M  (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
+#define LP_APM_REGION2_R2_PMS_W_V  0x00000001U
+#define LP_APM_REGION2_R2_PMS_W_S  9
+/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM_REGION2_R2_PMS_R    (BIT(10))
+#define LP_APM_REGION2_R2_PMS_R_M  (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
+#define LP_APM_REGION2_R2_PMS_R_V  0x00000001U
+#define LP_APM_REGION2_R2_PMS_R_S  10
+
+/** LP_APM_REGION3_ADDR_START_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
+/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Start address of region3
+ */
+#define LP_APM_REGION3_ADDR_START    0xFFFFFFFFU
+#define LP_APM_REGION3_ADDR_START_M  (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
+#define LP_APM_REGION3_ADDR_START_V  0xFFFFFFFFU
+#define LP_APM_REGION3_ADDR_START_S  0
+
+/** LP_APM_REGION3_ADDR_END_REG register
+ *  Region address register
+ */
+#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
+/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  End address of region3
+ */
+#define LP_APM_REGION3_ADDR_END    0xFFFFFFFFU
+#define LP_APM_REGION3_ADDR_END_M  (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
+#define LP_APM_REGION3_ADDR_END_V  0xFFFFFFFFU
+#define LP_APM_REGION3_ADDR_END_S  0
+
+/** LP_APM_REGION3_PMS_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
+/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
+ *  Region execute authority in REE_MODE0
+ */
+#define LP_APM_REGION3_R0_PMS_X    (BIT(0))
+#define LP_APM_REGION3_R0_PMS_X_M  (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
+#define LP_APM_REGION3_R0_PMS_X_V  0x00000001U
+#define LP_APM_REGION3_R0_PMS_X_S  0
+/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
+ *  Region write authority in REE_MODE0
+ */
+#define LP_APM_REGION3_R0_PMS_W    (BIT(1))
+#define LP_APM_REGION3_R0_PMS_W_M  (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
+#define LP_APM_REGION3_R0_PMS_W_V  0x00000001U
+#define LP_APM_REGION3_R0_PMS_W_S  1
+/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
+ *  Region read authority in REE_MODE0
+ */
+#define LP_APM_REGION3_R0_PMS_R    (BIT(2))
+#define LP_APM_REGION3_R0_PMS_R_M  (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
+#define LP_APM_REGION3_R0_PMS_R_V  0x00000001U
+#define LP_APM_REGION3_R0_PMS_R_S  2
+/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
+ *  Region execute authority in REE_MODE1
+ */
+#define LP_APM_REGION3_R1_PMS_X    (BIT(4))
+#define LP_APM_REGION3_R1_PMS_X_M  (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
+#define LP_APM_REGION3_R1_PMS_X_V  0x00000001U
+#define LP_APM_REGION3_R1_PMS_X_S  4
+/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
+ *  Region write authority in REE_MODE1
+ */
+#define LP_APM_REGION3_R1_PMS_W    (BIT(5))
+#define LP_APM_REGION3_R1_PMS_W_M  (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
+#define LP_APM_REGION3_R1_PMS_W_V  0x00000001U
+#define LP_APM_REGION3_R1_PMS_W_S  5
+/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
+ *  Region read authority in REE_MODE1
+ */
+#define LP_APM_REGION3_R1_PMS_R    (BIT(6))
+#define LP_APM_REGION3_R1_PMS_R_M  (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
+#define LP_APM_REGION3_R1_PMS_R_V  0x00000001U
+#define LP_APM_REGION3_R1_PMS_R_S  6
+/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
+ *  Region execute authority in REE_MODE2
+ */
+#define LP_APM_REGION3_R2_PMS_X    (BIT(8))
+#define LP_APM_REGION3_R2_PMS_X_M  (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
+#define LP_APM_REGION3_R2_PMS_X_V  0x00000001U
+#define LP_APM_REGION3_R2_PMS_X_S  8
+/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
+ *  Region write authority in REE_MODE2
+ */
+#define LP_APM_REGION3_R2_PMS_W    (BIT(9))
+#define LP_APM_REGION3_R2_PMS_W_M  (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
+#define LP_APM_REGION3_R2_PMS_W_V  0x00000001U
+#define LP_APM_REGION3_R2_PMS_W_S  9
+/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
+ *  Region read authority in REE_MODE2
+ */
+#define LP_APM_REGION3_R2_PMS_R    (BIT(10))
+#define LP_APM_REGION3_R2_PMS_R_M  (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
+#define LP_APM_REGION3_R2_PMS_R_V  0x00000001U
+#define LP_APM_REGION3_R2_PMS_R_S  10
+
+/** LP_APM_FUNC_CTRL_REG register
+ *  PMS function control register
+ */
+#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
+/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
+ *  PMS M0 function enable
+ */
+#define LP_APM_M0_PMS_FUNC_EN    (BIT(0))
+#define LP_APM_M0_PMS_FUNC_EN_M  (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
+#define LP_APM_M0_PMS_FUNC_EN_V  0x00000001U
+#define LP_APM_M0_PMS_FUNC_EN_S  0
+/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
+ *  PMS M1 function enable
+ */
+#define LP_APM_M1_PMS_FUNC_EN    (BIT(1))
+#define LP_APM_M1_PMS_FUNC_EN_M  (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S)
+#define LP_APM_M1_PMS_FUNC_EN_V  0x00000001U
+#define LP_APM_M1_PMS_FUNC_EN_S  1
+
+/** LP_APM_M0_STATUS_REG register
+ *  M0 status register
+ */
+#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
+/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Exception status
+ */
+#define LP_APM_M0_EXCEPTION_STATUS    0x00000003U
+#define LP_APM_M0_EXCEPTION_STATUS_M  (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
+#define LP_APM_M0_EXCEPTION_STATUS_V  0x00000003U
+#define LP_APM_M0_EXCEPTION_STATUS_S  0
+
+/** LP_APM_M0_STATUS_CLR_REG register
+ *  M0 status clear register
+ */
+#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
+/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear exception status
+ */
+#define LP_APM_M0_REGION_STATUS_CLR    (BIT(0))
+#define LP_APM_M0_REGION_STATUS_CLR_M  (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
+#define LP_APM_M0_REGION_STATUS_CLR_V  0x00000001U
+#define LP_APM_M0_REGION_STATUS_CLR_S  0
+
+/** LP_APM_M0_EXCEPTION_INFO0_REG register
+ *  M0 exception_info0 register
+ */
+#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
+/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
+ *  Exception region
+ */
+#define LP_APM_M0_EXCEPTION_REGION    0x0000000FU
+#define LP_APM_M0_EXCEPTION_REGION_M  (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
+#define LP_APM_M0_EXCEPTION_REGION_V  0x0000000FU
+#define LP_APM_M0_EXCEPTION_REGION_S  0
+/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Exception mode
+ */
+#define LP_APM_M0_EXCEPTION_MODE    0x00000003U
+#define LP_APM_M0_EXCEPTION_MODE_M  (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
+#define LP_APM_M0_EXCEPTION_MODE_V  0x00000003U
+#define LP_APM_M0_EXCEPTION_MODE_S  16
+/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Exception id information
+ */
+#define LP_APM_M0_EXCEPTION_ID    0x0000001FU
+#define LP_APM_M0_EXCEPTION_ID_M  (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
+#define LP_APM_M0_EXCEPTION_ID_V  0x0000001FU
+#define LP_APM_M0_EXCEPTION_ID_S  18
+
+/** LP_APM_M0_EXCEPTION_INFO1_REG register
+ *  M0 exception_info1 register
+ */
+#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
+/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Exception addr
+ */
+#define LP_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
+#define LP_APM_M0_EXCEPTION_ADDR_M  (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
+#define LP_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define LP_APM_M0_EXCEPTION_ADDR_S  0
+
+/** LP_APM_M1_STATUS_REG register
+ *  M1 status register
+ */
+#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
+/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Exception status
+ */
+#define LP_APM_M1_EXCEPTION_STATUS    0x00000003U
+#define LP_APM_M1_EXCEPTION_STATUS_M  (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
+#define LP_APM_M1_EXCEPTION_STATUS_V  0x00000003U
+#define LP_APM_M1_EXCEPTION_STATUS_S  0
+
+/** LP_APM_M1_STATUS_CLR_REG register
+ *  M1 status clear register
+ */
+#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
+/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear exception status
+ */
+#define LP_APM_M1_REGION_STATUS_CLR    (BIT(0))
+#define LP_APM_M1_REGION_STATUS_CLR_M  (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S)
+#define LP_APM_M1_REGION_STATUS_CLR_V  0x00000001U
+#define LP_APM_M1_REGION_STATUS_CLR_S  0
+
+/** LP_APM_M1_EXCEPTION_INFO0_REG register
+ *  M1 exception_info0 register
+ */
+#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
+/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
+ *  Exception region
+ */
+#define LP_APM_M1_EXCEPTION_REGION    0x0000000FU
+#define LP_APM_M1_EXCEPTION_REGION_M  (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
+#define LP_APM_M1_EXCEPTION_REGION_V  0x0000000FU
+#define LP_APM_M1_EXCEPTION_REGION_S  0
+/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Exception mode
+ */
+#define LP_APM_M1_EXCEPTION_MODE    0x00000003U
+#define LP_APM_M1_EXCEPTION_MODE_M  (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
+#define LP_APM_M1_EXCEPTION_MODE_V  0x00000003U
+#define LP_APM_M1_EXCEPTION_MODE_S  16
+/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Exception id information
+ */
+#define LP_APM_M1_EXCEPTION_ID    0x0000001FU
+#define LP_APM_M1_EXCEPTION_ID_M  (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
+#define LP_APM_M1_EXCEPTION_ID_V  0x0000001FU
+#define LP_APM_M1_EXCEPTION_ID_S  18
+
+/** LP_APM_M1_EXCEPTION_INFO1_REG register
+ *  M1 exception_info1 register
+ */
+#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
+/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Exception addr
+ */
+#define LP_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
+#define LP_APM_M1_EXCEPTION_ADDR_M  (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
+#define LP_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define LP_APM_M1_EXCEPTION_ADDR_S  0
+
+/** LP_APM_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
+/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  APM M0 interrupt enable
+ */
+#define LP_APM_M0_APM_INT_EN    (BIT(0))
+#define LP_APM_M0_APM_INT_EN_M  (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
+#define LP_APM_M0_APM_INT_EN_V  0x00000001U
+#define LP_APM_M0_APM_INT_EN_S  0
+/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  APM M1 interrupt enable
+ */
+#define LP_APM_M1_APM_INT_EN    (BIT(1))
+#define LP_APM_M1_APM_INT_EN_M  (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
+#define LP_APM_M1_APM_INT_EN_V  0x00000001U
+#define LP_APM_M1_APM_INT_EN_S  1
+
+/** LP_APM_CLOCK_GATE_REG register
+ *  clock gating register
+ */
+#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
+/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reg_clk_en
+ */
+#define LP_APM_CLK_EN    (BIT(0))
+#define LP_APM_CLK_EN_M  (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
+#define LP_APM_CLK_EN_V  0x00000001U
+#define LP_APM_CLK_EN_S  0
+
+/** LP_APM_DATE_REG register
+ *  Version register
+ */
+#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
+/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
+ *  reg_date
+ */
+#define LP_APM_DATE    0x0FFFFFFFU
+#define LP_APM_DATE_M  (LP_APM_DATE_V << LP_APM_DATE_S)
+#define LP_APM_DATE_V  0x0FFFFFFFU
+#define LP_APM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm_struct.h b/components/soc/esp32p4/include/soc/lp_apm_struct.h
new file mode 100644
index 0000000000..82587d5501
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_apm_struct.h
@@ -0,0 +1,583 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Region filter enable register */
+/** Type of region_filter_en register
+ *  Region filter enable register
+ */
+typedef union {
+    struct {
+        /** region_filter_en : R/W; bitpos: [3:0]; default: 1;
+         *  Region filter enable
+         */
+        uint32_t region_filter_en:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_apm_region_filter_en_reg_t;
+
+
+/** Group: Region address register */
+/** Type of region0_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region0
+         */
+        uint32_t region0_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm_region0_addr_start_reg_t;
+
+/** Type of region0_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region0
+         */
+        uint32_t region0_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm_region0_addr_end_reg_t;
+
+/** Type of region1_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region1
+         */
+        uint32_t region1_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm_region1_addr_start_reg_t;
+
+/** Type of region1_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region1
+         */
+        uint32_t region1_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm_region1_addr_end_reg_t;
+
+/** Type of region2_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region2
+         */
+        uint32_t region2_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm_region2_addr_start_reg_t;
+
+/** Type of region2_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region2
+         */
+        uint32_t region2_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm_region2_addr_end_reg_t;
+
+/** Type of region3_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Start address of region3
+         */
+        uint32_t region3_addr_start:32;
+    };
+    uint32_t val;
+} lp_apm_region3_addr_start_reg_t;
+
+/** Type of region3_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  End address of region3
+         */
+        uint32_t region3_addr_end:32;
+    };
+    uint32_t val;
+} lp_apm_region3_addr_end_reg_t;
+
+
+/** Group: Region access authority attribute register */
+/** Type of region0_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_x:1;
+        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_w:1;
+        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region0_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_x:1;
+        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_w:1;
+        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region0_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_x:1;
+        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_w:1;
+        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region0_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm_region0_pms_attr_reg_t;
+
+/** Type of region1_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_x:1;
+        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_w:1;
+        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region1_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_x:1;
+        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_w:1;
+        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region1_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_x:1;
+        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_w:1;
+        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region1_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm_region1_pms_attr_reg_t;
+
+/** Type of region2_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_x:1;
+        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_w:1;
+        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region2_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_x:1;
+        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_w:1;
+        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region2_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_x:1;
+        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_w:1;
+        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region2_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm_region2_pms_attr_reg_t;
+
+/** Type of region3_pms_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
+         *  Region execute authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_x:1;
+        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
+         *  Region write authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_w:1;
+        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
+         *  Region read authority in REE_MODE0
+         */
+        uint32_t region3_r0_pms_r:1;
+        uint32_t reserved_3:1;
+        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
+         *  Region execute authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_x:1;
+        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
+         *  Region write authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_w:1;
+        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
+         *  Region read authority in REE_MODE1
+         */
+        uint32_t region3_r1_pms_r:1;
+        uint32_t reserved_7:1;
+        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
+         *  Region execute authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_x:1;
+        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
+         *  Region write authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_w:1;
+        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
+         *  Region read authority in REE_MODE2
+         */
+        uint32_t region3_r2_pms_r:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_apm_region3_pms_attr_reg_t;
+
+
+/** Group: PMS function control register */
+/** Type of func_ctrl register
+ *  PMS function control register
+ */
+typedef union {
+    struct {
+        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
+         *  PMS M0 function enable
+         */
+        uint32_t m0_pms_func_en:1;
+        /** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
+         *  PMS M1 function enable
+         */
+        uint32_t m1_pms_func_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_apm_func_ctrl_reg_t;
+
+
+/** Group: M0 status register */
+/** Type of m0_status register
+ *  M0 status register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Exception status
+         */
+        uint32_t m0_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_apm_m0_status_reg_t;
+
+
+/** Group: M0 status clear register */
+/** Type of m0_status_clr register
+ *  M0 status clear register
+ */
+typedef union {
+    struct {
+        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
+         *  Clear exception status
+         */
+        uint32_t m0_region_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_apm_m0_status_clr_reg_t;
+
+
+/** Group: M0 exception_info0 register */
+/** Type of m0_exception_info0 register
+ *  M0 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_region : RO; bitpos: [3:0]; default: 0;
+         *  Exception region
+         */
+        uint32_t m0_exception_region:4;
+        uint32_t reserved_4:12;
+        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Exception mode
+         */
+        uint32_t m0_exception_mode:2;
+        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Exception id information
+         */
+        uint32_t m0_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_apm_m0_exception_info0_reg_t;
+
+
+/** Group: M0 exception_info1 register */
+/** Type of m0_exception_info1 register
+ *  M0 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Exception addr
+         */
+        uint32_t m0_exception_addr:32;
+    };
+    uint32_t val;
+} lp_apm_m0_exception_info1_reg_t;
+
+
+/** Group: M1 status register */
+/** Type of m1_status register
+ *  M1 status register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Exception status
+         */
+        uint32_t m1_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_apm_m1_status_reg_t;
+
+
+/** Group: M1 status clear register */
+/** Type of m1_status_clr register
+ *  M1 status clear register
+ */
+typedef union {
+    struct {
+        /** m1_region_status_clr : WT; bitpos: [0]; default: 0;
+         *  Clear exception status
+         */
+        uint32_t m1_region_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_apm_m1_status_clr_reg_t;
+
+
+/** Group: M1 exception_info0 register */
+/** Type of m1_exception_info0 register
+ *  M1 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_region : RO; bitpos: [3:0]; default: 0;
+         *  Exception region
+         */
+        uint32_t m1_exception_region:4;
+        uint32_t reserved_4:12;
+        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Exception mode
+         */
+        uint32_t m1_exception_mode:2;
+        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Exception id information
+         */
+        uint32_t m1_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_apm_m1_exception_info0_reg_t;
+
+
+/** Group: M1 exception_info1 register */
+/** Type of m1_exception_info1 register
+ *  M1 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Exception addr
+         */
+        uint32_t m1_exception_addr:32;
+    };
+    uint32_t val;
+} lp_apm_m1_exception_info1_reg_t;
+
+
+/** Group: APM interrupt enable register */
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
+         *  APM M0 interrupt enable
+         */
+        uint32_t m0_apm_int_en:1;
+        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
+         *  APM M1 interrupt enable
+         */
+        uint32_t m1_apm_int_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_apm_int_en_reg_t;
+
+
+/** Group: clock gating register */
+/** Type of clock_gate register
+ *  clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reg_clk_en
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_apm_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35672640;
+         *  reg_date
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_apm_date_reg_t;
+
+
+typedef struct lp_apm_dev_t {
+    volatile lp_apm_region_filter_en_reg_t region_filter_en;
+    volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
+    volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
+    volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
+    volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
+    volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
+    volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
+    volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
+    volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
+    volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
+    volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
+    volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
+    volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
+    uint32_t reserved_034[36];
+    volatile lp_apm_func_ctrl_reg_t func_ctrl;
+    volatile lp_apm_m0_status_reg_t m0_status;
+    volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
+    volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
+    volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
+    volatile lp_apm_m1_status_reg_t m1_status;
+    volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
+    volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
+    volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
+    volatile lp_apm_int_en_reg_t int_en;
+    volatile lp_apm_clock_gate_reg_t clock_gate;
+    uint32_t reserved_0f0[3];
+    volatile lp_apm_date_reg_t date;
+} lp_apm_dev_t;
+
+extern lp_apm_dev_t LP_APM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h
new file mode 100644
index 0000000000..6d7ef6a48c
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h
@@ -0,0 +1,382 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_CLKRST_LP_CLK_CONF_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
+/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_SLOW_CLK_SEL    0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
+#define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_S  0
+/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_FAST_CLK_SEL    (BIT(2))
+#define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
+#define LP_CLKRST_FAST_CLK_SEL_V  0x00000001U
+#define LP_CLKRST_FAST_CLK_SEL_S  2
+/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_PERI_DIV_NUM    0x000000FFU
+#define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
+#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_LP_PERI_DIV_NUM_S  3
+
+/** LP_CLKRST_LP_CLK_PO_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
+/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_AON_SLOW_OEN    (BIT(0))
+#define LP_CLKRST_AON_SLOW_OEN_M  (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
+#define LP_CLKRST_AON_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_AON_SLOW_OEN_S  0
+/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_AON_FAST_OEN    (BIT(1))
+#define LP_CLKRST_AON_FAST_OEN_M  (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
+#define LP_CLKRST_AON_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_AON_FAST_OEN_S  1
+/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_SOSC_OEN    (BIT(2))
+#define LP_CLKRST_SOSC_OEN_M  (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
+#define LP_CLKRST_SOSC_OEN_V  0x00000001U
+#define LP_CLKRST_SOSC_OEN_S  2
+/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_OEN    (BIT(3))
+#define LP_CLKRST_FOSC_OEN_M  (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
+#define LP_CLKRST_FOSC_OEN_V  0x00000001U
+#define LP_CLKRST_FOSC_OEN_S  3
+/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_OSC32K_OEN    (BIT(4))
+#define LP_CLKRST_OSC32K_OEN_M  (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
+#define LP_CLKRST_OSC32K_OEN_V  0x00000001U
+#define LP_CLKRST_OSC32K_OEN_S  4
+/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_XTAL32K_OEN    (BIT(5))
+#define LP_CLKRST_XTAL32K_OEN_M  (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
+#define LP_CLKRST_XTAL32K_OEN_V  0x00000001U
+#define LP_CLKRST_XTAL32K_OEN_S  5
+/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_CORE_EFUSE_OEN    (BIT(6))
+#define LP_CLKRST_CORE_EFUSE_OEN_M  (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
+#define LP_CLKRST_CORE_EFUSE_OEN_V  0x00000001U
+#define LP_CLKRST_CORE_EFUSE_OEN_S  6
+/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_SLOW_OEN    (BIT(7))
+#define LP_CLKRST_SLOW_OEN_M  (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
+#define LP_CLKRST_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_SLOW_OEN_S  7
+/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_FAST_OEN    (BIT(8))
+#define LP_CLKRST_FAST_OEN_M  (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
+#define LP_CLKRST_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_FAST_OEN_S  8
+/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_RNG_OEN    (BIT(9))
+#define LP_CLKRST_RNG_OEN_M  (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
+#define LP_CLKRST_RNG_OEN_V  0x00000001U
+#define LP_CLKRST_RNG_OEN_S  9
+/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_LPBUS_OEN    (BIT(10))
+#define LP_CLKRST_LPBUS_OEN_M  (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
+#define LP_CLKRST_LPBUS_OEN_V  0x00000001U
+#define LP_CLKRST_LPBUS_OEN_S  10
+
+/** LP_CLKRST_LP_CLK_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
+/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_FAST_ORI_GATE    (BIT(31))
+#define LP_CLKRST_FAST_ORI_GATE_M  (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
+#define LP_CLKRST_FAST_ORI_GATE_V  0x00000001U
+#define LP_CLKRST_FAST_ORI_GATE_S  31
+
+/** LP_CLKRST_LP_RST_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
+/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN    (BIT(28))
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M  (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V  0x00000001U
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S  28
+/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_TIMER_RESET_EN    (BIT(29))
+#define LP_CLKRST_LP_TIMER_RESET_EN_M  (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
+#define LP_CLKRST_LP_TIMER_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_TIMER_RESET_EN_S  29
+/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_WDT_RESET_EN    (BIT(30))
+#define LP_CLKRST_WDT_RESET_EN_M  (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
+#define LP_CLKRST_WDT_RESET_EN_V  0x00000001U
+#define LP_CLKRST_WDT_RESET_EN_S  30
+/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_ANA_PERI_RESET_EN    (BIT(31))
+#define LP_CLKRST_ANA_PERI_RESET_EN_M  (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
+#define LP_CLKRST_ANA_PERI_RESET_EN_V  0x00000001U
+#define LP_CLKRST_ANA_PERI_RESET_EN_S  31
+
+/** LP_CLKRST_RESET_CAUSE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
+/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RESET_CAUSE    0x0000001FU
+#define LP_CLKRST_RESET_CAUSE_M  (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
+#define LP_CLKRST_RESET_CAUSE_V  0x0000001FU
+#define LP_CLKRST_RESET_CAUSE_S  0
+/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_CORE0_RESET_FLAG    (BIT(5))
+#define LP_CLKRST_CORE0_RESET_FLAG_M  (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
+#define LP_CLKRST_CORE0_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_FLAG_S  5
+/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR    (BIT(29))
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S  29
+/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CORE0_RESET_FLAG_SET    (BIT(30))
+#define LP_CLKRST_CORE0_RESET_FLAG_SET_M  (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
+#define LP_CLKRST_CORE0_RESET_FLAG_SET_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_FLAG_SET_S  30
+/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR    (BIT(31))
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M  (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S  31
+
+/** LP_CLKRST_CPU_RESET_REG register
+ *  need_des
+ */
+#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
+/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M  (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S  22
+/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN    (BIT(25))
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M  (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V  0x00000001U
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S  25
+/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_CPU_STALL_WAIT    0x0000001FU
+#define LP_CLKRST_CPU_STALL_WAIT_M  (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
+#define LP_CLKRST_CPU_STALL_WAIT_V  0x0000001FU
+#define LP_CLKRST_CPU_STALL_WAIT_S  26
+/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CPU_STALL_EN    (BIT(31))
+#define LP_CLKRST_CPU_STALL_EN_M  (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
+#define LP_CLKRST_CPU_STALL_EN_V  0x00000001U
+#define LP_CLKRST_CPU_STALL_EN_S  31
+
+/** LP_CLKRST_FOSC_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
+/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_DFREQ    0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_M  (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
+#define LP_CLKRST_FOSC_DFREQ_V  0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_S  22
+
+/** LP_CLKRST_RC32K_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
+/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
+ *  need_des
+ */
+#define LP_CLKRST_RC32K_DFREQ    0x000003FFU
+#define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
+#define LP_CLKRST_RC32K_DFREQ_V  0x000003FFU
+#define LP_CLKRST_RC32K_DFREQ_S  22
+
+/** LP_CLKRST_CLK_TO_HP_REG register
+ *  need_des
+ */
+#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
+/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
+#define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
+#define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_XTAL32K_S  28
+/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
+#define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
+#define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_SOSC_S  29
+/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
+#define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
+#define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_OSC32K_S  30
+/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
+#define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
+#define LP_CLKRST_ICG_HP_FOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_FOSC_S  31
+
+/** LP_CLKRST_LPMEM_FORCE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
+/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
+
+/** LP_CLKRST_LPPERI_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
+/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_I2C_CLK_SEL    (BIT(30))
+#define LP_CLKRST_LP_I2C_CLK_SEL_M  (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
+#define LP_CLKRST_LP_I2C_CLK_SEL_V  0x00000001U
+#define LP_CLKRST_LP_I2C_CLK_SEL_S  30
+/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_UART_CLK_SEL    (BIT(31))
+#define LP_CLKRST_LP_UART_CLK_SEL_M  (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
+#define LP_CLKRST_LP_UART_CLK_SEL_V  0x00000001U
+#define LP_CLKRST_LP_UART_CLK_SEL_S  31
+
+/** LP_CLKRST_XTAL32K_REG register
+ *  need_des
+ */
+#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
+/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DRES_XTAL32K    0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_M  (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
+#define LP_CLKRST_DRES_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_S  22
+/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DGM_XTAL32K    0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_M  (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
+#define LP_CLKRST_DGM_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_S  25
+/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_DBUF_XTAL32K    (BIT(28))
+#define LP_CLKRST_DBUF_XTAL32K_M  (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
+#define LP_CLKRST_DBUF_XTAL32K_V  0x00000001U
+#define LP_CLKRST_DBUF_XTAL32K_S  28
+/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DAC_XTAL32K    0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_M  (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
+#define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_S  29
+
+/** LP_CLKRST_DATE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
+/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35676304;
+ *  need_des
+ */
+#define LP_CLKRST_CLKRST_DATE    0x7FFFFFFFU
+#define LP_CLKRST_CLKRST_DATE_M  (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
+#define LP_CLKRST_CLKRST_DATE_V  0x7FFFFFFFU
+#define LP_CLKRST_CLKRST_DATE_S  0
+/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_EN    (BIT(31))
+#define LP_CLKRST_CLK_EN_M  (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
+#define LP_CLKRST_CLK_EN_V  0x00000001U
+#define LP_CLKRST_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h
new file mode 100644
index 0000000000..453817997f
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h
@@ -0,0 +1,341 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_clk_conf register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t slow_clk_sel:2;
+        /** fast_clk_sel : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_clk_sel:1;
+        /** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_peri_div_num:8;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_conf_reg_t;
+
+/** Type of lp_clk_po_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** aon_slow_oen : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t aon_slow_oen:1;
+        /** aon_fast_oen : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t aon_fast_oen:1;
+        /** sosc_oen : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t sosc_oen:1;
+        /** fosc_oen : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t fosc_oen:1;
+        /** osc32k_oen : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t osc32k_oen:1;
+        /** xtal32k_oen : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t xtal32k_oen:1;
+        /** core_efuse_oen : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t core_efuse_oen:1;
+        /** slow_oen : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t slow_oen:1;
+        /** fast_oen : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_oen:1;
+        /** rng_oen : R/W; bitpos: [9]; default: 1;
+         *  need_des
+         */
+        uint32_t rng_oen:1;
+        /** lpbus_oen : R/W; bitpos: [10]; default: 1;
+         *  need_des
+         */
+        uint32_t lpbus_oen:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_po_en_reg_t;
+
+/** Type of lp_clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** fast_ori_gate : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t fast_ori_gate:1;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_en_reg_t;
+
+/** Type of lp_rst_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t aon_efuse_core_reset_en:1;
+        /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_timer_reset_en:1;
+        /** wdt_reset_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_reset_en:1;
+        /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_peri_reset_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_lp_rst_en_reg_t;
+
+/** Type of reset_cause register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reset_cause : RO; bitpos: [4:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reset_cause:5;
+        /** core0_reset_flag : RO; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t core0_reset_flag:1;
+        uint32_t reserved_6:23;
+        /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t core0_reset_cause_clr:1;
+        /** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t core0_reset_flag_set:1;
+        /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t core0_reset_flag_clr:1;
+    };
+    uint32_t val;
+} lp_clkrst_reset_cause_reg_t;
+
+/** Type of cpu_reset register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
+         *  need_des
+         */
+        uint32_t rtc_wdt_cpu_reset_length:3;
+        /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t rtc_wdt_cpu_reset_en:1;
+        /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_stall_wait:5;
+        /** cpu_stall_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_stall_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_cpu_reset_reg_t;
+
+/** Type of fosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  need_des
+         */
+        uint32_t fosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_clkrst_fosc_cntl_reg_t;
+
+/** Type of rc32k_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  need_des
+         */
+        uint32_t rc32k_dfreq:10;
+    };
+    uint32_t val;
+} lp_clkrst_rc32k_cntl_reg_t;
+
+/** Type of clk_to_hp register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
+         *  need_des
+         */
+        uint32_t icg_hp_xtal32k:1;
+        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
+         *  need_des
+         */
+        uint32_t icg_hp_sosc:1;
+        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
+         *  need_des
+         */
+        uint32_t icg_hp_osc32k:1;
+        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t icg_hp_fosc:1;
+    };
+    uint32_t val;
+} lp_clkrst_clk_to_hp_reg_t;
+
+/** Type of lpmem_force register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lpmem_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_clkrst_lpmem_force_reg_t;
+
+/** Type of lpperi register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2c_clk_sel:1;
+        /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_clk_sel:1;
+    };
+    uint32_t val;
+} lp_clkrst_lpperi_reg_t;
+
+/** Type of xtal32k register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
+         *  need_des
+         */
+        uint32_t dres_xtal32k:3;
+        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
+         *  need_des
+         */
+        uint32_t dgm_xtal32k:3;
+        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t dbuf_xtal32k:1;
+        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
+         *  need_des
+         */
+        uint32_t dac_xtal32k:3;
+    };
+    uint32_t val;
+} lp_clkrst_xtal32k_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** clkrst_date : R/W; bitpos: [30:0]; default: 35676304;
+         *  need_des
+         */
+        uint32_t clkrst_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_date_reg_t;
+
+
+typedef struct lp_clkrst_dev_t {
+    volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
+    volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
+    volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
+    volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
+    volatile lp_clkrst_reset_cause_reg_t reset_cause;
+    volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
+    volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
+    volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
+    volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
+    volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
+    volatile lp_clkrst_lpperi_reg_t lpperi;
+    volatile lp_clkrst_xtal32k_reg_t xtal32k;
+    uint32_t reserved_030[243];
+    volatile lp_clkrst_date_reg_t date;
+} lp_clkrst_dev_t;
+
+extern lp_clkrst_dev_t LP_CLKRST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
new file mode 100644
index 0000000000..5bfb2830d2
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_LP_GPIO_SIG_MAP_H_
+#define _SOC_LP_GPIO_SIG_MAP_H_
+
+#define LP_I2C_SCL_PAD_IN_IDX                             0
+#define LP_I2C_SCL_PAD_OUT_IDX                            0
+#define LP_I2C_SDA_PAD_IN_IDX                             1
+#define LP_I2C_SDA_PAD_OUT_IDX                            1
+#define LP_UART_RXD_PAD_IN_IDX                            2
+#define LP_UART_TXD_PAD_OUT_IDX                           2
+#define LP_UART_CTSN_PAD_IN_IDX                           3
+#define LP_UART_RTSN_PAD_OUT_IDX                          3
+#define LP_UART_DSRN_PAD_IN_IDX                           4
+#define LP_UART_DTRN_PAD_OUT_IDX                          4
+#define LP_SPI_CK_PAD_IN_IDX                              5
+#define LP_SPI_CK_PAD_OUT_IDX                             5
+#define LP_SPI_CS_PAD_IN_IDX                              6
+#define LP_SPI_CS_PAD_OUT_IDX                             6
+#define LP_SPI_D_PAD_IN_IDX                               7
+#define LP_SPI_D_PAD_OUT_IDX                              7
+#define LP_SPI_Q_PAD_IN_IDX                               8
+#define LP_SPI_Q_PAD_OUT_IDX                              8
+#define LP_I2S_I_BCK_PAD_IN_IDX                           9
+#define LP_I2S_I_BCK_PAD_OUT_IDX                          9
+#define LP_I2S_I_SD_PAD_IN_IDX                            10
+#define LP_I2S_O_SD_PAD_OUT_IDX                           10
+#define LP_I2S_I_WS_PAD_IN_IDX                            11
+#define LP_I2S_I_WS_PAD_OUT_IDX                           11
+#define LP_I2S_O_BCK_PAD_IN_IDX                           12
+#define LP_I2S_O_BCK_PAD_OUT_IDX                          12
+#define LP_I2S_O_WS_PAD_IN_IDX                            13
+#define LP_I2S_O_WS_PAD_OUT_IDX                           13
+#define LP_PROBE_TOP_OUT0_IDX                             14
+#define LP_PROBE_TOP_OUT1_IDX                             15
+#define LP_PROBE_TOP_OUT2_IDX                             16
+#define LP_PROBE_TOP_OUT3_IDX                             17
+#define LP_PROBE_TOP_OUT4_IDX                             18
+#define LP_PROBE_TOP_OUT5_IDX                             19
+#define LP_PROBE_TOP_OUT6_IDX                             20
+#define LP_PROBE_TOP_OUT7_IDX                             21
+#define LP_PROBE_TOP_OUT8_IDX                             22
+#define LP_PROBE_TOP_OUT9_IDX                             23
+#define LP_PROBE_TOP_OUT10_IDX                            24
+#define LP_PROBE_TOP_OUT11_IDX                            25
+#define LP_PROBE_TOP_OUT12_IDX                            26
+#define LP_PROBE_TOP_OUT13_IDX                            27
+#define LP_PROBE_TOP_OUT14_IDX                            28
+#define LP_PROBE_TOP_OUT15_IDX                            29
+#define PROBE_CHAIN_CLK_PAD_OUT_IDX                       30
+#define GPIO_MAP_DATE_IDX                                 0x230323
+#endif  /* _SOC_LP_GPIO_SIG_MAP_H_ */
diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h
new file mode 100644
index 0000000000..ed40ee7b05
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h
@@ -0,0 +1,135 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_I2C_ANA_MST_I2C0_CTRL_REG register
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
+/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_CTRL    0x01FFFFFFU
+#define LP_I2C_ANA_MST_I2C0_CTRL_M  (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S)
+#define LP_I2C_ANA_MST_I2C0_CTRL_V  0x01FFFFFFU
+#define LP_I2C_ANA_MST_I2C0_CTRL_S  0
+/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_BUSY    (BIT(25))
+#define LP_I2C_ANA_MST_I2C0_BUSY_M  (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S)
+#define LP_I2C_ANA_MST_I2C0_BUSY_V  0x00000001U
+#define LP_I2C_ANA_MST_I2C0_BUSY_S  25
+
+/** LP_I2C_ANA_MST_I2C0_CONF_REG register
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4)
+/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_CONF    0x00FFFFFFU
+#define LP_I2C_ANA_MST_I2C0_CONF_M  (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S)
+#define LP_I2C_ANA_MST_I2C0_CONF_V  0x00FFFFFFU
+#define LP_I2C_ANA_MST_I2C0_CONF_S  0
+/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7;
+ *  reserved
+ */
+#define LP_I2C_ANA_MST_I2C0_STATUS    0x000000FFU
+#define LP_I2C_ANA_MST_I2C0_STATUS_M  (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S)
+#define LP_I2C_ANA_MST_I2C0_STATUS_V  0x000000FFU
+#define LP_I2C_ANA_MST_I2C0_STATUS_S  24
+
+/** LP_I2C_ANA_MST_I2C0_DATA_REG register
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8)
+/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_RDATA    0x000000FFU
+#define LP_I2C_ANA_MST_I2C0_RDATA_M  (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S)
+#define LP_I2C_ANA_MST_I2C0_RDATA_V  0x000000FFU
+#define LP_I2C_ANA_MST_I2C0_RDATA_S  0
+/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C0_CLK_SEL    0x00000007U
+#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M  (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S)
+#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V  0x00000007U
+#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S  8
+/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1;
+ *  need  des
+ */
+#define LP_I2C_ANA_MST_I2C_MST_SEL    (BIT(11))
+#define LP_I2C_ANA_MST_I2C_MST_SEL_M  (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S)
+#define LP_I2C_ANA_MST_I2C_MST_SEL_V  0x00000001U
+#define LP_I2C_ANA_MST_I2C_MST_SEL_S  11
+
+/** LP_I2C_ANA_MST_ANA_CONF1_REG register
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc)
+/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_ANA_CONF1    0x00FFFFFFU
+#define LP_I2C_ANA_MST_ANA_CONF1_M  (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
+#define LP_I2C_ANA_MST_ANA_CONF1_V  0x00FFFFFFU
+#define LP_I2C_ANA_MST_ANA_CONF1_S  0
+
+/** LP_I2C_ANA_MST_NOUSE_REG register
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10)
+/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C_MST_NOUSE    0xFFFFFFFFU
+#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M  (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S)
+#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V  0xFFFFFFFFU
+#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S  0
+
+/** LP_I2C_ANA_MST_DEVICE_EN_REG register
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14)
+/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C_DEVICE_EN    0x00000FFFU
+#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M  (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S)
+#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V  0x00000FFFU
+#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S  0
+
+/** LP_I2C_ANA_MST_DATE_REG register
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc)
+/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C_MAT_DATE    0x0FFFFFFFU
+#define LP_I2C_ANA_MST_I2C_MAT_DATE_M  (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S)
+#define LP_I2C_ANA_MST_I2C_MAT_DATE_V  0x0FFFFFFFU
+#define LP_I2C_ANA_MST_I2C_MAT_DATE_S  0
+/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN    (BIT(28))
+#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M  (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S)
+#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V  0x00000001U
+#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S  28
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h
new file mode 100644
index 0000000000..46aedaf634
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h
@@ -0,0 +1,150 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of i2c0_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
+         *  need_des
+         */
+        uint32_t i2c0_ctrl:25;
+        /** i2c0_busy : RO; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t i2c0_busy:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} lp_i2c_ana_mst_i2c0_ctrl_reg_t;
+
+/** Type of i2c0_conf register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
+         *  need_des
+         */
+        uint32_t i2c0_conf:24;
+        /** i2c0_status : RO; bitpos: [31:24]; default: 7;
+         *  reserved
+         */
+        uint32_t i2c0_status:8;
+    };
+    uint32_t val;
+} lp_i2c_ana_mst_i2c0_conf_reg_t;
+
+/** Type of i2c0_data register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** i2c0_rdata : RO; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t i2c0_rdata:8;
+        /** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1;
+         *  need_des
+         */
+        uint32_t i2c0_clk_sel:3;
+        /** i2c_mst_sel : R/W; bitpos: [11]; default: 1;
+         *  need  des
+         */
+        uint32_t i2c_mst_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_i2c_ana_mst_i2c0_data_reg_t;
+
+/** Type of ana_conf1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_conf1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lp_i2c_ana_mst_ana_conf1_reg_t;
+
+/** Type of nouse register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t i2c_mst_nouse:32;
+    };
+    uint32_t val;
+} lp_i2c_ana_mst_nouse_reg_t;
+
+/** Type of device_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** i2c_device_en : R/W; bitpos: [11:0]; default: 0;
+         *  need_des
+         */
+        uint32_t i2c_device_en:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_i2c_ana_mst_device_en_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873;
+         *  need_des
+         */
+        uint32_t i2c_mat_date:28;
+        /** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t i2c_mat_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_i2c_ana_mst_date_reg_t;
+
+
+typedef struct lp_i2c_ana_mst_dev_t {
+    volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
+    volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
+    volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
+    volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1;
+    volatile lp_i2c_ana_mst_nouse_reg_t nouse;
+    volatile lp_i2c_ana_mst_device_en_reg_t device_en;
+    uint32_t reserved_018[249];
+    volatile lp_i2c_ana_mst_date_reg_t date;
+} lp_i2c_ana_mst_dev_t;
+
+extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_io_reg.h b/components/soc/esp32p4/include/soc/lp_io_reg.h
new file mode 100644
index 0000000000..64b5f6c425
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_io_reg.h
@@ -0,0 +1,1263 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_IO_OUT_DATA_REG register
+ *  need des
+ */
+#define LP_IO_OUT_DATA_REG (DR_REG_LP_IO_BASE + 0x0)
+/** LP_IO_LP_GPIO_OUT_DATA : R/W/WTC; bitpos: [7:0]; default: 0;
+ *  set lp gpio output data
+ */
+#define LP_IO_LP_GPIO_OUT_DATA    0x000000FFU
+#define LP_IO_LP_GPIO_OUT_DATA_M  (LP_IO_LP_GPIO_OUT_DATA_V << LP_IO_LP_GPIO_OUT_DATA_S)
+#define LP_IO_LP_GPIO_OUT_DATA_V  0x000000FFU
+#define LP_IO_LP_GPIO_OUT_DATA_S  0
+
+/** LP_IO_OUT_DATA_W1TS_REG register
+ *  need des
+ */
+#define LP_IO_OUT_DATA_W1TS_REG (DR_REG_LP_IO_BASE + 0x4)
+/** LP_IO_LP_GPIO_OUT_DATA_W1TS : WT; bitpos: [7:0]; default: 0;
+ *  set one time output data
+ */
+#define LP_IO_LP_GPIO_OUT_DATA_W1TS    0x000000FFU
+#define LP_IO_LP_GPIO_OUT_DATA_W1TS_M  (LP_IO_LP_GPIO_OUT_DATA_W1TS_V << LP_IO_LP_GPIO_OUT_DATA_W1TS_S)
+#define LP_IO_LP_GPIO_OUT_DATA_W1TS_V  0x000000FFU
+#define LP_IO_LP_GPIO_OUT_DATA_W1TS_S  0
+
+/** LP_IO_OUT_DATA_W1TC_REG register
+ *  need des
+ */
+#define LP_IO_OUT_DATA_W1TC_REG (DR_REG_LP_IO_BASE + 0x8)
+/** LP_IO_LP_GPIO_OUT_DATA_W1TC : WT; bitpos: [7:0]; default: 0;
+ *  clear one time output data
+ */
+#define LP_IO_LP_GPIO_OUT_DATA_W1TC    0x000000FFU
+#define LP_IO_LP_GPIO_OUT_DATA_W1TC_M  (LP_IO_LP_GPIO_OUT_DATA_W1TC_V << LP_IO_LP_GPIO_OUT_DATA_W1TC_S)
+#define LP_IO_LP_GPIO_OUT_DATA_W1TC_V  0x000000FFU
+#define LP_IO_LP_GPIO_OUT_DATA_W1TC_S  0
+
+/** LP_IO_OUT_ENABLE_REG register
+ *  need des
+ */
+#define LP_IO_OUT_ENABLE_REG (DR_REG_LP_IO_BASE + 0xc)
+/** LP_IO_LP_GPIO_ENABLE : R/W/WTC; bitpos: [7:0]; default: 0;
+ *  set lp gpio output data
+ */
+#define LP_IO_LP_GPIO_ENABLE    0x000000FFU
+#define LP_IO_LP_GPIO_ENABLE_M  (LP_IO_LP_GPIO_ENABLE_V << LP_IO_LP_GPIO_ENABLE_S)
+#define LP_IO_LP_GPIO_ENABLE_V  0x000000FFU
+#define LP_IO_LP_GPIO_ENABLE_S  0
+
+/** LP_IO_OUT_ENABLE_W1TS_REG register
+ *  need des
+ */
+#define LP_IO_OUT_ENABLE_W1TS_REG (DR_REG_LP_IO_BASE + 0x10)
+/** LP_IO_LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0;
+ *  set one time output data
+ */
+#define LP_IO_LP_GPIO_ENABLE_W1TS    0x000000FFU
+#define LP_IO_LP_GPIO_ENABLE_W1TS_M  (LP_IO_LP_GPIO_ENABLE_W1TS_V << LP_IO_LP_GPIO_ENABLE_W1TS_S)
+#define LP_IO_LP_GPIO_ENABLE_W1TS_V  0x000000FFU
+#define LP_IO_LP_GPIO_ENABLE_W1TS_S  0
+
+/** LP_IO_OUT_ENABLE_W1TC_REG register
+ *  need des
+ */
+#define LP_IO_OUT_ENABLE_W1TC_REG (DR_REG_LP_IO_BASE + 0x14)
+/** LP_IO_LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0;
+ *  clear one time output data
+ */
+#define LP_IO_LP_GPIO_ENABLE_W1TC    0x000000FFU
+#define LP_IO_LP_GPIO_ENABLE_W1TC_M  (LP_IO_LP_GPIO_ENABLE_W1TC_V << LP_IO_LP_GPIO_ENABLE_W1TC_S)
+#define LP_IO_LP_GPIO_ENABLE_W1TC_V  0x000000FFU
+#define LP_IO_LP_GPIO_ENABLE_W1TC_S  0
+
+/** LP_IO_STATUS_REG register
+ *  need des
+ */
+#define LP_IO_STATUS_REG (DR_REG_LP_IO_BASE + 0x18)
+/** LP_IO_LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0;
+ *  set lp gpio output data
+ */
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT    0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT_M  (LP_IO_LP_GPIO_STATUS_INTERRUPT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_S)
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT_V  0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT_S  0
+
+/** LP_IO_STATUS_W1TS_REG register
+ *  need des
+ */
+#define LP_IO_STATUS_W1TS_REG (DR_REG_LP_IO_BASE + 0x1c)
+/** LP_IO_LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0;
+ *  set one time output data
+ */
+#define LP_IO_LP_GPIO_STATUS_W1TS    0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_W1TS_M  (LP_IO_LP_GPIO_STATUS_W1TS_V << LP_IO_LP_GPIO_STATUS_W1TS_S)
+#define LP_IO_LP_GPIO_STATUS_W1TS_V  0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_W1TS_S  0
+
+/** LP_IO_STATUS_W1TC_REG register
+ *  need des
+ */
+#define LP_IO_STATUS_W1TC_REG (DR_REG_LP_IO_BASE + 0x20)
+/** LP_IO_LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0;
+ *  clear one time output data
+ */
+#define LP_IO_LP_GPIO_STATUS_W1TC    0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_W1TC_M  (LP_IO_LP_GPIO_STATUS_W1TC_V << LP_IO_LP_GPIO_STATUS_W1TC_S)
+#define LP_IO_LP_GPIO_STATUS_W1TC_V  0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_W1TC_S  0
+
+/** LP_IO_IN_REG register
+ *  need des
+ */
+#define LP_IO_IN_REG (DR_REG_LP_IO_BASE + 0x24)
+/** LP_IO_LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO_IN_DATA_NEXT    0x000000FFU
+#define LP_IO_LP_GPIO_IN_DATA_NEXT_M  (LP_IO_LP_GPIO_IN_DATA_NEXT_V << LP_IO_LP_GPIO_IN_DATA_NEXT_S)
+#define LP_IO_LP_GPIO_IN_DATA_NEXT_V  0x000000FFU
+#define LP_IO_LP_GPIO_IN_DATA_NEXT_S  0
+
+/** LP_IO_PIN0_REG register
+ *  need des
+ */
+#define LP_IO_PIN0_REG (DR_REG_LP_IO_BASE + 0x28)
+/** LP_IO_LP_GPIO0_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO0_SYNC_BYPASS_M  (LP_IO_LP_GPIO0_SYNC_BYPASS_V << LP_IO_LP_GPIO0_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO0_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO0_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO0_PAD_DRIVER_M  (LP_IO_LP_GPIO0_PAD_DRIVER_V << LP_IO_LP_GPIO0_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO0_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO0_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO0_INT_TYPE_M  (LP_IO_LP_GPIO0_INT_TYPE_V << LP_IO_LP_GPIO0_INT_TYPE_S)
+#define LP_IO_LP_GPIO0_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO0_INT_TYPE_S  7
+/** LP_IO_LP_GPIO0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO0_WAKEUP_ENABLE_V << LP_IO_LP_GPIO0_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO0_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO0_FILTER_EN_M  (LP_IO_LP_GPIO0_FILTER_EN_V << LP_IO_LP_GPIO0_FILTER_EN_S)
+#define LP_IO_LP_GPIO0_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO0_FILTER_EN_S  11
+
+/** LP_IO_PIN1_REG register
+ *  need des
+ */
+#define LP_IO_PIN1_REG (DR_REG_LP_IO_BASE + 0x2c)
+/** LP_IO_LP_GPIO1_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO1_SYNC_BYPASS_M  (LP_IO_LP_GPIO1_SYNC_BYPASS_V << LP_IO_LP_GPIO1_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO1_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO1_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO1_PAD_DRIVER_M  (LP_IO_LP_GPIO1_PAD_DRIVER_V << LP_IO_LP_GPIO1_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO1_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO1_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO1_INT_TYPE_M  (LP_IO_LP_GPIO1_INT_TYPE_V << LP_IO_LP_GPIO1_INT_TYPE_S)
+#define LP_IO_LP_GPIO1_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO1_INT_TYPE_S  7
+/** LP_IO_LP_GPIO1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO1_WAKEUP_ENABLE_V << LP_IO_LP_GPIO1_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO1_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO1_FILTER_EN_M  (LP_IO_LP_GPIO1_FILTER_EN_V << LP_IO_LP_GPIO1_FILTER_EN_S)
+#define LP_IO_LP_GPIO1_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO1_FILTER_EN_S  11
+
+/** LP_IO_PIN2_REG register
+ *  need des
+ */
+#define LP_IO_PIN2_REG (DR_REG_LP_IO_BASE + 0x30)
+/** LP_IO_LP_GPIO2_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO2_SYNC_BYPASS_M  (LP_IO_LP_GPIO2_SYNC_BYPASS_V << LP_IO_LP_GPIO2_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO2_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO2_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO2_PAD_DRIVER_M  (LP_IO_LP_GPIO2_PAD_DRIVER_V << LP_IO_LP_GPIO2_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO2_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO2_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO2_INT_TYPE_M  (LP_IO_LP_GPIO2_INT_TYPE_V << LP_IO_LP_GPIO2_INT_TYPE_S)
+#define LP_IO_LP_GPIO2_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO2_INT_TYPE_S  7
+/** LP_IO_LP_GPIO2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO2_WAKEUP_ENABLE_V << LP_IO_LP_GPIO2_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO2_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO2_FILTER_EN_M  (LP_IO_LP_GPIO2_FILTER_EN_V << LP_IO_LP_GPIO2_FILTER_EN_S)
+#define LP_IO_LP_GPIO2_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO2_FILTER_EN_S  11
+
+/** LP_IO_PIN3_REG register
+ *  need des
+ */
+#define LP_IO_PIN3_REG (DR_REG_LP_IO_BASE + 0x34)
+/** LP_IO_LP_GPIO3_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO3_SYNC_BYPASS_M  (LP_IO_LP_GPIO3_SYNC_BYPASS_V << LP_IO_LP_GPIO3_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO3_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO3_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO3_PAD_DRIVER_M  (LP_IO_LP_GPIO3_PAD_DRIVER_V << LP_IO_LP_GPIO3_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO3_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO3_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO3_INT_TYPE_M  (LP_IO_LP_GPIO3_INT_TYPE_V << LP_IO_LP_GPIO3_INT_TYPE_S)
+#define LP_IO_LP_GPIO3_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO3_INT_TYPE_S  7
+/** LP_IO_LP_GPIO3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO3_WAKEUP_ENABLE_V << LP_IO_LP_GPIO3_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO3_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO3_FILTER_EN_M  (LP_IO_LP_GPIO3_FILTER_EN_V << LP_IO_LP_GPIO3_FILTER_EN_S)
+#define LP_IO_LP_GPIO3_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO3_FILTER_EN_S  11
+
+/** LP_IO_PIN4_REG register
+ *  need des
+ */
+#define LP_IO_PIN4_REG (DR_REG_LP_IO_BASE + 0x38)
+/** LP_IO_LP_GPIO4_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO4_SYNC_BYPASS_M  (LP_IO_LP_GPIO4_SYNC_BYPASS_V << LP_IO_LP_GPIO4_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO4_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO4_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO4_PAD_DRIVER_M  (LP_IO_LP_GPIO4_PAD_DRIVER_V << LP_IO_LP_GPIO4_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO4_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO4_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO4_INT_TYPE_M  (LP_IO_LP_GPIO4_INT_TYPE_V << LP_IO_LP_GPIO4_INT_TYPE_S)
+#define LP_IO_LP_GPIO4_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO4_INT_TYPE_S  7
+/** LP_IO_LP_GPIO4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO4_WAKEUP_ENABLE_V << LP_IO_LP_GPIO4_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO4_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO4_FILTER_EN_M  (LP_IO_LP_GPIO4_FILTER_EN_V << LP_IO_LP_GPIO4_FILTER_EN_S)
+#define LP_IO_LP_GPIO4_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO4_FILTER_EN_S  11
+
+/** LP_IO_PIN5_REG register
+ *  need des
+ */
+#define LP_IO_PIN5_REG (DR_REG_LP_IO_BASE + 0x3c)
+/** LP_IO_LP_GPIO5_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO5_SYNC_BYPASS_M  (LP_IO_LP_GPIO5_SYNC_BYPASS_V << LP_IO_LP_GPIO5_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO5_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO5_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO5_PAD_DRIVER_M  (LP_IO_LP_GPIO5_PAD_DRIVER_V << LP_IO_LP_GPIO5_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO5_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO5_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO5_INT_TYPE_M  (LP_IO_LP_GPIO5_INT_TYPE_V << LP_IO_LP_GPIO5_INT_TYPE_S)
+#define LP_IO_LP_GPIO5_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO5_INT_TYPE_S  7
+/** LP_IO_LP_GPIO5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO5_WAKEUP_ENABLE_V << LP_IO_LP_GPIO5_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO5_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO5_FILTER_EN_M  (LP_IO_LP_GPIO5_FILTER_EN_V << LP_IO_LP_GPIO5_FILTER_EN_S)
+#define LP_IO_LP_GPIO5_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO5_FILTER_EN_S  11
+
+/** LP_IO_PIN6_REG register
+ *  need des
+ */
+#define LP_IO_PIN6_REG (DR_REG_LP_IO_BASE + 0x40)
+/** LP_IO_LP_GPIO6_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO6_SYNC_BYPASS_M  (LP_IO_LP_GPIO6_SYNC_BYPASS_V << LP_IO_LP_GPIO6_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO6_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO6_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO6_PAD_DRIVER_M  (LP_IO_LP_GPIO6_PAD_DRIVER_V << LP_IO_LP_GPIO6_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO6_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO6_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO6_INT_TYPE_M  (LP_IO_LP_GPIO6_INT_TYPE_V << LP_IO_LP_GPIO6_INT_TYPE_S)
+#define LP_IO_LP_GPIO6_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO6_INT_TYPE_S  7
+/** LP_IO_LP_GPIO6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO6_WAKEUP_ENABLE_V << LP_IO_LP_GPIO6_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO6_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO6_FILTER_EN_M  (LP_IO_LP_GPIO6_FILTER_EN_V << LP_IO_LP_GPIO6_FILTER_EN_S)
+#define LP_IO_LP_GPIO6_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO6_FILTER_EN_S  11
+
+/** LP_IO_PIN7_REG register
+ *  need des
+ */
+#define LP_IO_PIN7_REG (DR_REG_LP_IO_BASE + 0x44)
+/** LP_IO_LP_GPIO7_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_SYNC_BYPASS    0x00000003U
+#define LP_IO_LP_GPIO7_SYNC_BYPASS_M  (LP_IO_LP_GPIO7_SYNC_BYPASS_V << LP_IO_LP_GPIO7_SYNC_BYPASS_S)
+#define LP_IO_LP_GPIO7_SYNC_BYPASS_V  0x00000003U
+#define LP_IO_LP_GPIO7_SYNC_BYPASS_S  0
+/** LP_IO_LP_GPIO7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_PAD_DRIVER    (BIT(2))
+#define LP_IO_LP_GPIO7_PAD_DRIVER_M  (LP_IO_LP_GPIO7_PAD_DRIVER_V << LP_IO_LP_GPIO7_PAD_DRIVER_S)
+#define LP_IO_LP_GPIO7_PAD_DRIVER_V  0x00000001U
+#define LP_IO_LP_GPIO7_PAD_DRIVER_S  2
+/** LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR    (BIT(3))
+#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S)
+#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S  3
+/** LP_IO_LP_GPIO7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_INT_TYPE    0x00000007U
+#define LP_IO_LP_GPIO7_INT_TYPE_M  (LP_IO_LP_GPIO7_INT_TYPE_V << LP_IO_LP_GPIO7_INT_TYPE_S)
+#define LP_IO_LP_GPIO7_INT_TYPE_V  0x00000007U
+#define LP_IO_LP_GPIO7_INT_TYPE_S  7
+/** LP_IO_LP_GPIO7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_WAKEUP_ENABLE    (BIT(10))
+#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO7_WAKEUP_ENABLE_V << LP_IO_LP_GPIO7_WAKEUP_ENABLE_S)
+#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_V  0x00000001U
+#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_S  10
+/** LP_IO_LP_GPIO7_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_FILTER_EN    (BIT(11))
+#define LP_IO_LP_GPIO7_FILTER_EN_M  (LP_IO_LP_GPIO7_FILTER_EN_V << LP_IO_LP_GPIO7_FILTER_EN_S)
+#define LP_IO_LP_GPIO7_FILTER_EN_V  0x00000001U
+#define LP_IO_LP_GPIO7_FILTER_EN_S  11
+
+/** LP_IO_GPIO0_REG register
+ *  need des
+ */
+#define LP_IO_GPIO0_REG (DR_REG_LP_IO_BASE + 0x48)
+/** LP_IO_LP_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO0_MCU_OE_M  (LP_IO_LP_GPIO0_MCU_OE_V << LP_IO_LP_GPIO0_MCU_OE_S)
+#define LP_IO_LP_GPIO0_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO0_MCU_OE_S  0
+/** LP_IO_LP_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO0_SLP_SEL_M  (LP_IO_LP_GPIO0_SLP_SEL_V << LP_IO_LP_GPIO0_SLP_SEL_S)
+#define LP_IO_LP_GPIO0_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO0_SLP_SEL_S  1
+/** LP_IO_LP_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO0_MCU_WPD_M  (LP_IO_LP_GPIO0_MCU_WPD_V << LP_IO_LP_GPIO0_MCU_WPD_S)
+#define LP_IO_LP_GPIO0_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO0_MCU_WPD_S  2
+/** LP_IO_LP_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO0_MCU_WPU_M  (LP_IO_LP_GPIO0_MCU_WPU_V << LP_IO_LP_GPIO0_MCU_WPU_S)
+#define LP_IO_LP_GPIO0_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO0_MCU_WPU_S  3
+/** LP_IO_LP_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO0_MCU_IE_M  (LP_IO_LP_GPIO0_MCU_IE_V << LP_IO_LP_GPIO0_MCU_IE_S)
+#define LP_IO_LP_GPIO0_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO0_MCU_IE_S  4
+/** LP_IO_LP_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO0_MCU_DRV_M  (LP_IO_LP_GPIO0_MCU_DRV_V << LP_IO_LP_GPIO0_MCU_DRV_S)
+#define LP_IO_LP_GPIO0_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO0_MCU_DRV_S  5
+/** LP_IO_LP_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO0_FUN_WPD_M  (LP_IO_LP_GPIO0_FUN_WPD_V << LP_IO_LP_GPIO0_FUN_WPD_S)
+#define LP_IO_LP_GPIO0_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO0_FUN_WPD_S  7
+/** LP_IO_LP_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO0_FUN_WPU_M  (LP_IO_LP_GPIO0_FUN_WPU_V << LP_IO_LP_GPIO0_FUN_WPU_S)
+#define LP_IO_LP_GPIO0_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO0_FUN_WPU_S  8
+/** LP_IO_LP_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO0_FUN_IE_M  (LP_IO_LP_GPIO0_FUN_IE_V << LP_IO_LP_GPIO0_FUN_IE_S)
+#define LP_IO_LP_GPIO0_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO0_FUN_IE_S  9
+/** LP_IO_LP_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO0_FUN_DRV_M  (LP_IO_LP_GPIO0_FUN_DRV_V << LP_IO_LP_GPIO0_FUN_DRV_S)
+#define LP_IO_LP_GPIO0_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO0_FUN_DRV_S  10
+/** LP_IO_LP_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO0_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO0_MCU_SEL_M  (LP_IO_LP_GPIO0_MCU_SEL_V << LP_IO_LP_GPIO0_MCU_SEL_S)
+#define LP_IO_LP_GPIO0_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO0_MCU_SEL_S  12
+
+/** LP_IO_GPIO1_REG register
+ *  need des
+ */
+#define LP_IO_GPIO1_REG (DR_REG_LP_IO_BASE + 0x4c)
+/** LP_IO_LP_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO1_MCU_OE_M  (LP_IO_LP_GPIO1_MCU_OE_V << LP_IO_LP_GPIO1_MCU_OE_S)
+#define LP_IO_LP_GPIO1_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO1_MCU_OE_S  0
+/** LP_IO_LP_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO1_SLP_SEL_M  (LP_IO_LP_GPIO1_SLP_SEL_V << LP_IO_LP_GPIO1_SLP_SEL_S)
+#define LP_IO_LP_GPIO1_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO1_SLP_SEL_S  1
+/** LP_IO_LP_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO1_MCU_WPD_M  (LP_IO_LP_GPIO1_MCU_WPD_V << LP_IO_LP_GPIO1_MCU_WPD_S)
+#define LP_IO_LP_GPIO1_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO1_MCU_WPD_S  2
+/** LP_IO_LP_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO1_MCU_WPU_M  (LP_IO_LP_GPIO1_MCU_WPU_V << LP_IO_LP_GPIO1_MCU_WPU_S)
+#define LP_IO_LP_GPIO1_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO1_MCU_WPU_S  3
+/** LP_IO_LP_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO1_MCU_IE_M  (LP_IO_LP_GPIO1_MCU_IE_V << LP_IO_LP_GPIO1_MCU_IE_S)
+#define LP_IO_LP_GPIO1_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO1_MCU_IE_S  4
+/** LP_IO_LP_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO1_MCU_DRV_M  (LP_IO_LP_GPIO1_MCU_DRV_V << LP_IO_LP_GPIO1_MCU_DRV_S)
+#define LP_IO_LP_GPIO1_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO1_MCU_DRV_S  5
+/** LP_IO_LP_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO1_FUN_WPD_M  (LP_IO_LP_GPIO1_FUN_WPD_V << LP_IO_LP_GPIO1_FUN_WPD_S)
+#define LP_IO_LP_GPIO1_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO1_FUN_WPD_S  7
+/** LP_IO_LP_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO1_FUN_WPU_M  (LP_IO_LP_GPIO1_FUN_WPU_V << LP_IO_LP_GPIO1_FUN_WPU_S)
+#define LP_IO_LP_GPIO1_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO1_FUN_WPU_S  8
+/** LP_IO_LP_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO1_FUN_IE_M  (LP_IO_LP_GPIO1_FUN_IE_V << LP_IO_LP_GPIO1_FUN_IE_S)
+#define LP_IO_LP_GPIO1_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO1_FUN_IE_S  9
+/** LP_IO_LP_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO1_FUN_DRV_M  (LP_IO_LP_GPIO1_FUN_DRV_V << LP_IO_LP_GPIO1_FUN_DRV_S)
+#define LP_IO_LP_GPIO1_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO1_FUN_DRV_S  10
+/** LP_IO_LP_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO1_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO1_MCU_SEL_M  (LP_IO_LP_GPIO1_MCU_SEL_V << LP_IO_LP_GPIO1_MCU_SEL_S)
+#define LP_IO_LP_GPIO1_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO1_MCU_SEL_S  12
+
+/** LP_IO_GPIO2_REG register
+ *  need des
+ */
+#define LP_IO_GPIO2_REG (DR_REG_LP_IO_BASE + 0x50)
+/** LP_IO_LP_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO2_MCU_OE_M  (LP_IO_LP_GPIO2_MCU_OE_V << LP_IO_LP_GPIO2_MCU_OE_S)
+#define LP_IO_LP_GPIO2_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO2_MCU_OE_S  0
+/** LP_IO_LP_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO2_SLP_SEL_M  (LP_IO_LP_GPIO2_SLP_SEL_V << LP_IO_LP_GPIO2_SLP_SEL_S)
+#define LP_IO_LP_GPIO2_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO2_SLP_SEL_S  1
+/** LP_IO_LP_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO2_MCU_WPD_M  (LP_IO_LP_GPIO2_MCU_WPD_V << LP_IO_LP_GPIO2_MCU_WPD_S)
+#define LP_IO_LP_GPIO2_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO2_MCU_WPD_S  2
+/** LP_IO_LP_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO2_MCU_WPU_M  (LP_IO_LP_GPIO2_MCU_WPU_V << LP_IO_LP_GPIO2_MCU_WPU_S)
+#define LP_IO_LP_GPIO2_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO2_MCU_WPU_S  3
+/** LP_IO_LP_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO2_MCU_IE_M  (LP_IO_LP_GPIO2_MCU_IE_V << LP_IO_LP_GPIO2_MCU_IE_S)
+#define LP_IO_LP_GPIO2_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO2_MCU_IE_S  4
+/** LP_IO_LP_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO2_MCU_DRV_M  (LP_IO_LP_GPIO2_MCU_DRV_V << LP_IO_LP_GPIO2_MCU_DRV_S)
+#define LP_IO_LP_GPIO2_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO2_MCU_DRV_S  5
+/** LP_IO_LP_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO2_FUN_WPD_M  (LP_IO_LP_GPIO2_FUN_WPD_V << LP_IO_LP_GPIO2_FUN_WPD_S)
+#define LP_IO_LP_GPIO2_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO2_FUN_WPD_S  7
+/** LP_IO_LP_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO2_FUN_WPU_M  (LP_IO_LP_GPIO2_FUN_WPU_V << LP_IO_LP_GPIO2_FUN_WPU_S)
+#define LP_IO_LP_GPIO2_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO2_FUN_WPU_S  8
+/** LP_IO_LP_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO2_FUN_IE_M  (LP_IO_LP_GPIO2_FUN_IE_V << LP_IO_LP_GPIO2_FUN_IE_S)
+#define LP_IO_LP_GPIO2_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO2_FUN_IE_S  9
+/** LP_IO_LP_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO2_FUN_DRV_M  (LP_IO_LP_GPIO2_FUN_DRV_V << LP_IO_LP_GPIO2_FUN_DRV_S)
+#define LP_IO_LP_GPIO2_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO2_FUN_DRV_S  10
+/** LP_IO_LP_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO2_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO2_MCU_SEL_M  (LP_IO_LP_GPIO2_MCU_SEL_V << LP_IO_LP_GPIO2_MCU_SEL_S)
+#define LP_IO_LP_GPIO2_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO2_MCU_SEL_S  12
+
+/** LP_IO_GPIO3_REG register
+ *  need des
+ */
+#define LP_IO_GPIO3_REG (DR_REG_LP_IO_BASE + 0x54)
+/** LP_IO_LP_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO3_MCU_OE_M  (LP_IO_LP_GPIO3_MCU_OE_V << LP_IO_LP_GPIO3_MCU_OE_S)
+#define LP_IO_LP_GPIO3_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO3_MCU_OE_S  0
+/** LP_IO_LP_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO3_SLP_SEL_M  (LP_IO_LP_GPIO3_SLP_SEL_V << LP_IO_LP_GPIO3_SLP_SEL_S)
+#define LP_IO_LP_GPIO3_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO3_SLP_SEL_S  1
+/** LP_IO_LP_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO3_MCU_WPD_M  (LP_IO_LP_GPIO3_MCU_WPD_V << LP_IO_LP_GPIO3_MCU_WPD_S)
+#define LP_IO_LP_GPIO3_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO3_MCU_WPD_S  2
+/** LP_IO_LP_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO3_MCU_WPU_M  (LP_IO_LP_GPIO3_MCU_WPU_V << LP_IO_LP_GPIO3_MCU_WPU_S)
+#define LP_IO_LP_GPIO3_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO3_MCU_WPU_S  3
+/** LP_IO_LP_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO3_MCU_IE_M  (LP_IO_LP_GPIO3_MCU_IE_V << LP_IO_LP_GPIO3_MCU_IE_S)
+#define LP_IO_LP_GPIO3_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO3_MCU_IE_S  4
+/** LP_IO_LP_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO3_MCU_DRV_M  (LP_IO_LP_GPIO3_MCU_DRV_V << LP_IO_LP_GPIO3_MCU_DRV_S)
+#define LP_IO_LP_GPIO3_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO3_MCU_DRV_S  5
+/** LP_IO_LP_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO3_FUN_WPD_M  (LP_IO_LP_GPIO3_FUN_WPD_V << LP_IO_LP_GPIO3_FUN_WPD_S)
+#define LP_IO_LP_GPIO3_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO3_FUN_WPD_S  7
+/** LP_IO_LP_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO3_FUN_WPU_M  (LP_IO_LP_GPIO3_FUN_WPU_V << LP_IO_LP_GPIO3_FUN_WPU_S)
+#define LP_IO_LP_GPIO3_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO3_FUN_WPU_S  8
+/** LP_IO_LP_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO3_FUN_IE_M  (LP_IO_LP_GPIO3_FUN_IE_V << LP_IO_LP_GPIO3_FUN_IE_S)
+#define LP_IO_LP_GPIO3_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO3_FUN_IE_S  9
+/** LP_IO_LP_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO3_FUN_DRV_M  (LP_IO_LP_GPIO3_FUN_DRV_V << LP_IO_LP_GPIO3_FUN_DRV_S)
+#define LP_IO_LP_GPIO3_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO3_FUN_DRV_S  10
+/** LP_IO_LP_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO3_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO3_MCU_SEL_M  (LP_IO_LP_GPIO3_MCU_SEL_V << LP_IO_LP_GPIO3_MCU_SEL_S)
+#define LP_IO_LP_GPIO3_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO3_MCU_SEL_S  12
+
+/** LP_IO_GPIO4_REG register
+ *  need des
+ */
+#define LP_IO_GPIO4_REG (DR_REG_LP_IO_BASE + 0x58)
+/** LP_IO_LP_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO4_MCU_OE_M  (LP_IO_LP_GPIO4_MCU_OE_V << LP_IO_LP_GPIO4_MCU_OE_S)
+#define LP_IO_LP_GPIO4_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO4_MCU_OE_S  0
+/** LP_IO_LP_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO4_SLP_SEL_M  (LP_IO_LP_GPIO4_SLP_SEL_V << LP_IO_LP_GPIO4_SLP_SEL_S)
+#define LP_IO_LP_GPIO4_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO4_SLP_SEL_S  1
+/** LP_IO_LP_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO4_MCU_WPD_M  (LP_IO_LP_GPIO4_MCU_WPD_V << LP_IO_LP_GPIO4_MCU_WPD_S)
+#define LP_IO_LP_GPIO4_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO4_MCU_WPD_S  2
+/** LP_IO_LP_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO4_MCU_WPU_M  (LP_IO_LP_GPIO4_MCU_WPU_V << LP_IO_LP_GPIO4_MCU_WPU_S)
+#define LP_IO_LP_GPIO4_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO4_MCU_WPU_S  3
+/** LP_IO_LP_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO4_MCU_IE_M  (LP_IO_LP_GPIO4_MCU_IE_V << LP_IO_LP_GPIO4_MCU_IE_S)
+#define LP_IO_LP_GPIO4_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO4_MCU_IE_S  4
+/** LP_IO_LP_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO4_MCU_DRV_M  (LP_IO_LP_GPIO4_MCU_DRV_V << LP_IO_LP_GPIO4_MCU_DRV_S)
+#define LP_IO_LP_GPIO4_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO4_MCU_DRV_S  5
+/** LP_IO_LP_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO4_FUN_WPD_M  (LP_IO_LP_GPIO4_FUN_WPD_V << LP_IO_LP_GPIO4_FUN_WPD_S)
+#define LP_IO_LP_GPIO4_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO4_FUN_WPD_S  7
+/** LP_IO_LP_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO4_FUN_WPU_M  (LP_IO_LP_GPIO4_FUN_WPU_V << LP_IO_LP_GPIO4_FUN_WPU_S)
+#define LP_IO_LP_GPIO4_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO4_FUN_WPU_S  8
+/** LP_IO_LP_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO4_FUN_IE_M  (LP_IO_LP_GPIO4_FUN_IE_V << LP_IO_LP_GPIO4_FUN_IE_S)
+#define LP_IO_LP_GPIO4_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO4_FUN_IE_S  9
+/** LP_IO_LP_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO4_FUN_DRV_M  (LP_IO_LP_GPIO4_FUN_DRV_V << LP_IO_LP_GPIO4_FUN_DRV_S)
+#define LP_IO_LP_GPIO4_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO4_FUN_DRV_S  10
+/** LP_IO_LP_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO4_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO4_MCU_SEL_M  (LP_IO_LP_GPIO4_MCU_SEL_V << LP_IO_LP_GPIO4_MCU_SEL_S)
+#define LP_IO_LP_GPIO4_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO4_MCU_SEL_S  12
+
+/** LP_IO_GPIO5_REG register
+ *  need des
+ */
+#define LP_IO_GPIO5_REG (DR_REG_LP_IO_BASE + 0x5c)
+/** LP_IO_LP_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO5_MCU_OE_M  (LP_IO_LP_GPIO5_MCU_OE_V << LP_IO_LP_GPIO5_MCU_OE_S)
+#define LP_IO_LP_GPIO5_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO5_MCU_OE_S  0
+/** LP_IO_LP_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO5_SLP_SEL_M  (LP_IO_LP_GPIO5_SLP_SEL_V << LP_IO_LP_GPIO5_SLP_SEL_S)
+#define LP_IO_LP_GPIO5_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO5_SLP_SEL_S  1
+/** LP_IO_LP_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO5_MCU_WPD_M  (LP_IO_LP_GPIO5_MCU_WPD_V << LP_IO_LP_GPIO5_MCU_WPD_S)
+#define LP_IO_LP_GPIO5_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO5_MCU_WPD_S  2
+/** LP_IO_LP_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO5_MCU_WPU_M  (LP_IO_LP_GPIO5_MCU_WPU_V << LP_IO_LP_GPIO5_MCU_WPU_S)
+#define LP_IO_LP_GPIO5_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO5_MCU_WPU_S  3
+/** LP_IO_LP_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO5_MCU_IE_M  (LP_IO_LP_GPIO5_MCU_IE_V << LP_IO_LP_GPIO5_MCU_IE_S)
+#define LP_IO_LP_GPIO5_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO5_MCU_IE_S  4
+/** LP_IO_LP_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO5_MCU_DRV_M  (LP_IO_LP_GPIO5_MCU_DRV_V << LP_IO_LP_GPIO5_MCU_DRV_S)
+#define LP_IO_LP_GPIO5_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO5_MCU_DRV_S  5
+/** LP_IO_LP_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO5_FUN_WPD_M  (LP_IO_LP_GPIO5_FUN_WPD_V << LP_IO_LP_GPIO5_FUN_WPD_S)
+#define LP_IO_LP_GPIO5_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO5_FUN_WPD_S  7
+/** LP_IO_LP_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO5_FUN_WPU_M  (LP_IO_LP_GPIO5_FUN_WPU_V << LP_IO_LP_GPIO5_FUN_WPU_S)
+#define LP_IO_LP_GPIO5_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO5_FUN_WPU_S  8
+/** LP_IO_LP_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO5_FUN_IE_M  (LP_IO_LP_GPIO5_FUN_IE_V << LP_IO_LP_GPIO5_FUN_IE_S)
+#define LP_IO_LP_GPIO5_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO5_FUN_IE_S  9
+/** LP_IO_LP_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO5_FUN_DRV_M  (LP_IO_LP_GPIO5_FUN_DRV_V << LP_IO_LP_GPIO5_FUN_DRV_S)
+#define LP_IO_LP_GPIO5_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO5_FUN_DRV_S  10
+/** LP_IO_LP_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO5_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO5_MCU_SEL_M  (LP_IO_LP_GPIO5_MCU_SEL_V << LP_IO_LP_GPIO5_MCU_SEL_S)
+#define LP_IO_LP_GPIO5_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO5_MCU_SEL_S  12
+
+/** LP_IO_GPIO6_REG register
+ *  need des
+ */
+#define LP_IO_GPIO6_REG (DR_REG_LP_IO_BASE + 0x60)
+/** LP_IO_LP_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO6_MCU_OE_M  (LP_IO_LP_GPIO6_MCU_OE_V << LP_IO_LP_GPIO6_MCU_OE_S)
+#define LP_IO_LP_GPIO6_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO6_MCU_OE_S  0
+/** LP_IO_LP_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO6_SLP_SEL_M  (LP_IO_LP_GPIO6_SLP_SEL_V << LP_IO_LP_GPIO6_SLP_SEL_S)
+#define LP_IO_LP_GPIO6_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO6_SLP_SEL_S  1
+/** LP_IO_LP_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO6_MCU_WPD_M  (LP_IO_LP_GPIO6_MCU_WPD_V << LP_IO_LP_GPIO6_MCU_WPD_S)
+#define LP_IO_LP_GPIO6_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO6_MCU_WPD_S  2
+/** LP_IO_LP_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO6_MCU_WPU_M  (LP_IO_LP_GPIO6_MCU_WPU_V << LP_IO_LP_GPIO6_MCU_WPU_S)
+#define LP_IO_LP_GPIO6_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO6_MCU_WPU_S  3
+/** LP_IO_LP_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO6_MCU_IE_M  (LP_IO_LP_GPIO6_MCU_IE_V << LP_IO_LP_GPIO6_MCU_IE_S)
+#define LP_IO_LP_GPIO6_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO6_MCU_IE_S  4
+/** LP_IO_LP_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO6_MCU_DRV_M  (LP_IO_LP_GPIO6_MCU_DRV_V << LP_IO_LP_GPIO6_MCU_DRV_S)
+#define LP_IO_LP_GPIO6_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO6_MCU_DRV_S  5
+/** LP_IO_LP_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO6_FUN_WPD_M  (LP_IO_LP_GPIO6_FUN_WPD_V << LP_IO_LP_GPIO6_FUN_WPD_S)
+#define LP_IO_LP_GPIO6_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO6_FUN_WPD_S  7
+/** LP_IO_LP_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO6_FUN_WPU_M  (LP_IO_LP_GPIO6_FUN_WPU_V << LP_IO_LP_GPIO6_FUN_WPU_S)
+#define LP_IO_LP_GPIO6_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO6_FUN_WPU_S  8
+/** LP_IO_LP_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO6_FUN_IE_M  (LP_IO_LP_GPIO6_FUN_IE_V << LP_IO_LP_GPIO6_FUN_IE_S)
+#define LP_IO_LP_GPIO6_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO6_FUN_IE_S  9
+/** LP_IO_LP_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO6_FUN_DRV_M  (LP_IO_LP_GPIO6_FUN_DRV_V << LP_IO_LP_GPIO6_FUN_DRV_S)
+#define LP_IO_LP_GPIO6_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO6_FUN_DRV_S  10
+/** LP_IO_LP_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO6_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO6_MCU_SEL_M  (LP_IO_LP_GPIO6_MCU_SEL_V << LP_IO_LP_GPIO6_MCU_SEL_S)
+#define LP_IO_LP_GPIO6_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO6_MCU_SEL_S  12
+
+/** LP_IO_GPIO7_REG register
+ *  need des
+ */
+#define LP_IO_GPIO7_REG (DR_REG_LP_IO_BASE + 0x64)
+/** LP_IO_LP_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_MCU_OE    (BIT(0))
+#define LP_IO_LP_GPIO7_MCU_OE_M  (LP_IO_LP_GPIO7_MCU_OE_V << LP_IO_LP_GPIO7_MCU_OE_S)
+#define LP_IO_LP_GPIO7_MCU_OE_V  0x00000001U
+#define LP_IO_LP_GPIO7_MCU_OE_S  0
+/** LP_IO_LP_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_SLP_SEL    (BIT(1))
+#define LP_IO_LP_GPIO7_SLP_SEL_M  (LP_IO_LP_GPIO7_SLP_SEL_V << LP_IO_LP_GPIO7_SLP_SEL_S)
+#define LP_IO_LP_GPIO7_SLP_SEL_V  0x00000001U
+#define LP_IO_LP_GPIO7_SLP_SEL_S  1
+/** LP_IO_LP_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_MCU_WPD    (BIT(2))
+#define LP_IO_LP_GPIO7_MCU_WPD_M  (LP_IO_LP_GPIO7_MCU_WPD_V << LP_IO_LP_GPIO7_MCU_WPD_S)
+#define LP_IO_LP_GPIO7_MCU_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO7_MCU_WPD_S  2
+/** LP_IO_LP_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_MCU_WPU    (BIT(3))
+#define LP_IO_LP_GPIO7_MCU_WPU_M  (LP_IO_LP_GPIO7_MCU_WPU_V << LP_IO_LP_GPIO7_MCU_WPU_S)
+#define LP_IO_LP_GPIO7_MCU_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO7_MCU_WPU_S  3
+/** LP_IO_LP_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_MCU_IE    (BIT(4))
+#define LP_IO_LP_GPIO7_MCU_IE_M  (LP_IO_LP_GPIO7_MCU_IE_V << LP_IO_LP_GPIO7_MCU_IE_S)
+#define LP_IO_LP_GPIO7_MCU_IE_V  0x00000001U
+#define LP_IO_LP_GPIO7_MCU_IE_S  4
+/** LP_IO_LP_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_MCU_DRV    0x00000003U
+#define LP_IO_LP_GPIO7_MCU_DRV_M  (LP_IO_LP_GPIO7_MCU_DRV_V << LP_IO_LP_GPIO7_MCU_DRV_S)
+#define LP_IO_LP_GPIO7_MCU_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO7_MCU_DRV_S  5
+/** LP_IO_LP_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_FUN_WPD    (BIT(7))
+#define LP_IO_LP_GPIO7_FUN_WPD_M  (LP_IO_LP_GPIO7_FUN_WPD_V << LP_IO_LP_GPIO7_FUN_WPD_S)
+#define LP_IO_LP_GPIO7_FUN_WPD_V  0x00000001U
+#define LP_IO_LP_GPIO7_FUN_WPD_S  7
+/** LP_IO_LP_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_FUN_WPU    (BIT(8))
+#define LP_IO_LP_GPIO7_FUN_WPU_M  (LP_IO_LP_GPIO7_FUN_WPU_V << LP_IO_LP_GPIO7_FUN_WPU_S)
+#define LP_IO_LP_GPIO7_FUN_WPU_V  0x00000001U
+#define LP_IO_LP_GPIO7_FUN_WPU_S  8
+/** LP_IO_LP_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_FUN_IE    (BIT(9))
+#define LP_IO_LP_GPIO7_FUN_IE_M  (LP_IO_LP_GPIO7_FUN_IE_V << LP_IO_LP_GPIO7_FUN_IE_S)
+#define LP_IO_LP_GPIO7_FUN_IE_V  0x00000001U
+#define LP_IO_LP_GPIO7_FUN_IE_S  9
+/** LP_IO_LP_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_FUN_DRV    0x00000003U
+#define LP_IO_LP_GPIO7_FUN_DRV_M  (LP_IO_LP_GPIO7_FUN_DRV_V << LP_IO_LP_GPIO7_FUN_DRV_S)
+#define LP_IO_LP_GPIO7_FUN_DRV_V  0x00000003U
+#define LP_IO_LP_GPIO7_FUN_DRV_S  10
+/** LP_IO_LP_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO7_MCU_SEL    0x00000007U
+#define LP_IO_LP_GPIO7_MCU_SEL_M  (LP_IO_LP_GPIO7_MCU_SEL_V << LP_IO_LP_GPIO7_MCU_SEL_S)
+#define LP_IO_LP_GPIO7_MCU_SEL_V  0x00000007U
+#define LP_IO_LP_GPIO7_MCU_SEL_S  12
+
+/** LP_IO_STATUS_INTERRUPT_REG register
+ *  need des
+ */
+#define LP_IO_STATUS_INTERRUPT_REG (DR_REG_LP_IO_BASE + 0x68)
+/** LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT    0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_M  (LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S)
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V  0x000000FFU
+#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** LP_IO_DEBUG_SEL0_REG register
+ *  need des
+ */
+#define LP_IO_DEBUG_SEL0_REG (DR_REG_LP_IO_BASE + 0x6c)
+/** LP_IO_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_DEBUG_SEL0    0x0000007FU
+#define LP_IO_LP_DEBUG_SEL0_M  (LP_IO_LP_DEBUG_SEL0_V << LP_IO_LP_DEBUG_SEL0_S)
+#define LP_IO_LP_DEBUG_SEL0_V  0x0000007FU
+#define LP_IO_LP_DEBUG_SEL0_S  0
+/** LP_IO_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_DEBUG_SEL1    0x0000007FU
+#define LP_IO_LP_DEBUG_SEL1_M  (LP_IO_LP_DEBUG_SEL1_V << LP_IO_LP_DEBUG_SEL1_S)
+#define LP_IO_LP_DEBUG_SEL1_V  0x0000007FU
+#define LP_IO_LP_DEBUG_SEL1_S  7
+/** LP_IO_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_DEBUG_SEL2    0x0000007FU
+#define LP_IO_LP_DEBUG_SEL2_M  (LP_IO_LP_DEBUG_SEL2_V << LP_IO_LP_DEBUG_SEL2_S)
+#define LP_IO_LP_DEBUG_SEL2_V  0x0000007FU
+#define LP_IO_LP_DEBUG_SEL2_S  14
+/** LP_IO_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_DEBUG_SEL3    0x0000007FU
+#define LP_IO_LP_DEBUG_SEL3_M  (LP_IO_LP_DEBUG_SEL3_V << LP_IO_LP_DEBUG_SEL3_S)
+#define LP_IO_LP_DEBUG_SEL3_V  0x0000007FU
+#define LP_IO_LP_DEBUG_SEL3_S  21
+
+/** LP_IO_DEBUG_SEL1_REG register
+ *  need des
+ */
+#define LP_IO_DEBUG_SEL1_REG (DR_REG_LP_IO_BASE + 0x70)
+/** LP_IO_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
+ *  need des
+ */
+#define LP_IO_LP_DEBUG_SEL4    0x0000007FU
+#define LP_IO_LP_DEBUG_SEL4_M  (LP_IO_LP_DEBUG_SEL4_V << LP_IO_LP_DEBUG_SEL4_S)
+#define LP_IO_LP_DEBUG_SEL4_V  0x0000007FU
+#define LP_IO_LP_DEBUG_SEL4_S  0
+
+/** LP_IO_LPI2C_REG register
+ *  need des
+ */
+#define LP_IO_LPI2C_REG (DR_REG_LP_IO_BASE + 0x74)
+/** LP_IO_LP_I2C_SDA_IE : R/W; bitpos: [30]; default: 1;
+ *  need des
+ */
+#define LP_IO_LP_I2C_SDA_IE    (BIT(30))
+#define LP_IO_LP_I2C_SDA_IE_M  (LP_IO_LP_I2C_SDA_IE_V << LP_IO_LP_I2C_SDA_IE_S)
+#define LP_IO_LP_I2C_SDA_IE_V  0x00000001U
+#define LP_IO_LP_I2C_SDA_IE_S  30
+/** LP_IO_LP_I2C_SCL_IE : R/W; bitpos: [31]; default: 1;
+ *  need des
+ */
+#define LP_IO_LP_I2C_SCL_IE    (BIT(31))
+#define LP_IO_LP_I2C_SCL_IE_M  (LP_IO_LP_I2C_SCL_IE_V << LP_IO_LP_I2C_SCL_IE_S)
+#define LP_IO_LP_I2C_SCL_IE_V  0x00000001U
+#define LP_IO_LP_I2C_SCL_IE_S  31
+
+/** LP_IO_DATE_REG register
+ *  need des
+ */
+#define LP_IO_DATE_REG (DR_REG_LP_IO_BASE + 0x3fc)
+/** LP_IO_LP_IO_DATE : R/W; bitpos: [30:0]; default: 35660032;
+ *  need des
+ */
+#define LP_IO_LP_IO_DATE    0x7FFFFFFFU
+#define LP_IO_LP_IO_DATE_M  (LP_IO_LP_IO_DATE_V << LP_IO_LP_IO_DATE_S)
+#define LP_IO_LP_IO_DATE_V  0x7FFFFFFFU
+#define LP_IO_LP_IO_DATE_S  0
+/** LP_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need des
+ */
+#define LP_IO_CLK_EN    (BIT(31))
+#define LP_IO_CLK_EN_M  (LP_IO_CLK_EN_V << LP_IO_CLK_EN_S)
+#define LP_IO_CLK_EN_V  0x00000001U
+#define LP_IO_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_io_struct.h b/components/soc/esp32p4/include/soc/lp_io_struct.h
new file mode 100644
index 0000000000..97404851bb
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_io_struct.h
@@ -0,0 +1,362 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of out_data register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** out_data : R/W/WTC; bitpos: [7:0]; default: 0;
+         *  set lp gpio output data
+         */
+        uint32_t out_data:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_out_data_reg_t;
+
+/** Type of out_data_w1ts register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
+         *  set one time output data
+         */
+        uint32_t out_data_w1ts:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_out_data_w1ts_reg_t;
+
+/** Type of out_data_w1tc register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
+         *  clear one time output data
+         */
+        uint32_t out_data_w1tc:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_out_data_w1tc_reg_t;
+
+/** Type of out_enable register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** enable : R/W/WTC; bitpos: [7:0]; default: 0;
+         *  set lp gpio output data
+         */
+        uint32_t enable:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_out_enable_reg_t;
+
+/** Type of out_enable_w1ts register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [7:0]; default: 0;
+         *  set one time output data
+         */
+        uint32_t enable_w1ts:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_out_enable_w1ts_reg_t;
+
+/** Type of out_enable_w1tc register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [7:0]; default: 0;
+         *  clear one time output data
+         */
+        uint32_t enable_w1tc:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_out_enable_w1tc_reg_t;
+
+/** Type of status register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
+         *  set lp gpio output data
+         */
+        uint32_t status_interrupt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_status_reg_t;
+
+/** Type of status_w1ts register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [7:0]; default: 0;
+         *  set one time output data
+         */
+        uint32_t status_w1ts:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [7:0]; default: 0;
+         *  clear one time output data
+         */
+        uint32_t status_w1tc:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_status_w1tc_reg_t;
+
+/** Type of in register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [7:0]; default: 0;
+         *  need des
+         */
+        uint32_t in_data_next:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_in_reg_t;
+
+/** Type of pin register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** sync_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  need des
+         */
+        uint32_t sync_bypass:2;
+        /** pad_driver : R/W; bitpos: [2]; default: 0;
+         *  need des
+         */
+        uint32_t pad_driver:1;
+        /** edge_wakeup_clr : WT; bitpos: [3]; default: 0;
+         *  need des
+         */
+        uint32_t edge_wakeup_clr:1;
+        uint32_t reserved_4:3;
+        /** int_type : R/W; bitpos: [9:7]; default: 0;
+         *  need des
+         */
+        uint32_t int_type:3;
+        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  need des
+         */
+        uint32_t wakeup_enable:1;
+        /** filter_en : R/W; bitpos: [11]; default: 0;
+         *  need des
+         */
+        uint32_t filter_en:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_io_pin_reg_t;
+
+/** Type of gpio register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  need des
+         */
+        uint32_t mcu_oe:1;
+        /** slp_sel : R/W; bitpos: [1]; default: 0;
+         *  need des
+         */
+        uint32_t slp_sel:1;
+        /** mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  need des
+         */
+        uint32_t mcu_wpd:1;
+        /** mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  need des
+         */
+        uint32_t mcu_wpu:1;
+        /** mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  need des
+         */
+        uint32_t mcu_ie:1;
+        /** mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  need des
+         */
+        uint32_t mcu_drv:2;
+        /** fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  need des
+         */
+        uint32_t fun_wpd:1;
+        /** fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  need des
+         */
+        uint32_t fun_wpu:1;
+        /** fun_ie : R/W; bitpos: [9]; default: 0;
+         *  need des
+         */
+        uint32_t fun_ie:1;
+        /** fun_drv : R/W; bitpos: [11:10]; default: 0;
+         *  need des
+         */
+        uint32_t fun_drv:2;
+        /** mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  need des
+         */
+        uint32_t mcu_sel:3;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} lp_io_gpio_reg_t;
+
+/** Type of status_interrupt register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
+         *  need des
+         */
+        uint32_t status_interrupt_next:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_io_status_interrupt_reg_t;
+
+/** Type of debug_sel0 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** debug_sel0 : R/W; bitpos: [6:0]; default: 0;
+         *  need des
+         */
+        uint32_t debug_sel0:7;
+        /** debug_sel1 : R/W; bitpos: [13:7]; default: 0;
+         *  need des
+         */
+        uint32_t debug_sel1:7;
+        /** debug_sel2 : R/W; bitpos: [20:14]; default: 0;
+         *  need des
+         */
+        uint32_t debug_sel2:7;
+        /** debug_sel3 : R/W; bitpos: [27:21]; default: 0;
+         *  need des
+         */
+        uint32_t debug_sel3:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_io_debug_sel0_reg_t;
+
+/** Type of debug_sel1 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** debug_sel4 : R/W; bitpos: [6:0]; default: 0;
+         *  need des
+         */
+        uint32_t debug_sel4:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_io_debug_sel1_reg_t;
+
+/** Type of lpi2c register
+ *  need des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1;
+         *  need des
+         */
+        uint32_t lp_i2c_sda_ie:1;
+        /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1;
+         *  need des
+         */
+        uint32_t lp_i2c_scl_ie:1;
+    };
+    uint32_t val;
+} lp_io_lpi2c_reg_t;
+
+/** Type of date register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032;
+         *  need des
+         */
+        uint32_t lp_io_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_io_date_reg_t;
+
+
+typedef struct lp_io_dev_t {
+    volatile lp_io_out_data_reg_t out_data;
+    volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
+    volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
+    volatile lp_io_out_enable_reg_t out_enable;
+    volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts;
+    volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc;
+    volatile lp_io_status_reg_t status;
+    volatile lp_io_status_w1ts_reg_t status_w1ts;
+    volatile lp_io_status_w1tc_reg_t status_w1tc;
+    volatile lp_io_in_reg_t in;
+    volatile lp_io_pin_reg_t pin[8];
+    volatile lp_io_gpio_reg_t gpio[8];
+    volatile lp_io_status_interrupt_reg_t status_interrupt;
+    volatile lp_io_debug_sel0_reg_t debug_sel0;
+    volatile lp_io_debug_sel1_reg_t debug_sel1;
+    volatile lp_io_lpi2c_reg_t lpi2c;
+    uint32_t reserved_078[225];
+    volatile lp_io_date_reg_t date;
+} lp_io_dev_t;
+
+extern lp_io_dev_t LP_IO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_sys_reg.h b/components/soc/esp32p4/include/soc/lp_sys_reg.h
new file mode 100644
index 0000000000..5df8429220
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_sys_reg.h
@@ -0,0 +1,1349 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_SYSTEM_REG_LP_SYS_VER_DATE_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SYS_VER_DATE_REG (DR_REG_LP_SYS_BASE + 0x0)
+/** LP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165961;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
+#define LP_SYSTEM_REG_VER_DATE_M  (LP_SYSTEM_REG_VER_DATE_V << LP_SYSTEM_REG_VER_DATE_S)
+#define LP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_VER_DATE_S  0
+
+/** LP_SYSTEM_REG_CLK_SEL_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_CLK_SEL_CTRL_REG (DR_REG_LP_SYS_BASE + 0x4)
+/** LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK    (BIT(16))
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_M  (LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V << LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S)
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V  0x00000001U
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S  16
+/** LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL    (BIT(17))
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_M  (LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V << LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S)
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S  17
+
+/** LP_SYSTEM_REG_SYS_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SYS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x8)
+/** LP_SYSTEM_REG_LP_CORE_DISABLE : R/W; bitpos: [0]; default: 0;
+ *  lp cpu disable
+ */
+#define LP_SYSTEM_REG_LP_CORE_DISABLE    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_M  (LP_SYSTEM_REG_LP_CORE_DISABLE_V << LP_SYSTEM_REG_LP_CORE_DISABLE_S)
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_S  0
+/** LP_SYSTEM_REG_SYS_SW_RST : WT; bitpos: [1]; default: 0;
+ *  digital system software reset bit
+ */
+#define LP_SYSTEM_REG_SYS_SW_RST    (BIT(1))
+#define LP_SYSTEM_REG_SYS_SW_RST_M  (LP_SYSTEM_REG_SYS_SW_RST_V << LP_SYSTEM_REG_SYS_SW_RST_S)
+#define LP_SYSTEM_REG_SYS_SW_RST_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_SW_RST_S  1
+/** LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT    (BIT(2))
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_M  (LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V << LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S)
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V  0x00000001U
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S  2
+/** LP_SYSTEM_REG_DIG_FIB : R/W; bitpos: [10:3]; default: 255;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_DIG_FIB    0x000000FFU
+#define LP_SYSTEM_REG_DIG_FIB_M  (LP_SYSTEM_REG_DIG_FIB_V << LP_SYSTEM_REG_DIG_FIB_S)
+#define LP_SYSTEM_REG_DIG_FIB_V  0x000000FFU
+#define LP_SYSTEM_REG_DIG_FIB_S  3
+/** LP_SYSTEM_REG_IO_MUX_RESET_DISABLE : R/W; bitpos: [11]; default: 0;
+ *  reset disable bit for LP IOMUX
+ */
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE    (BIT(11))
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_M  (LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V << LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S)
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V  0x00000001U
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S  11
+/** LP_SYSTEM_REG_ANA_FIB : RO; bitpos: [20:14]; default: 127;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_ANA_FIB    0x0000007FU
+#define LP_SYSTEM_REG_ANA_FIB_M  (LP_SYSTEM_REG_ANA_FIB_V << LP_SYSTEM_REG_ANA_FIB_S)
+#define LP_SYSTEM_REG_ANA_FIB_V  0x0000007FU
+#define LP_SYSTEM_REG_ANA_FIB_S  14
+/** LP_SYSTEM_REG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_FIB_SEL    0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_M  (LP_SYSTEM_REG_LP_FIB_SEL_V << LP_SYSTEM_REG_LP_FIB_SEL_S)
+#define LP_SYSTEM_REG_LP_FIB_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_S  21
+/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR    (BIT(29))
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S  29
+/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG    (BIT(30))
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S)
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S  30
+/** LP_SYSTEM_REG_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0;
+ *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
+ *  hp_core1
+ */
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL    (BIT(31))
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_M  (LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V << LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S)
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S  31
+
+/** LP_SYSTEM_REG_LP_CLK_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0xc)
+/** LP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_CLK_EN    (BIT(0))
+#define LP_SYSTEM_REG_CLK_EN_M  (LP_SYSTEM_REG_CLK_EN_V << LP_SYSTEM_REG_CLK_EN_S)
+#define LP_SYSTEM_REG_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_CLK_EN_S  0
+/** LP_SYSTEM_REG_LP_FOSC_HP_CKEN : R/W; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN    (BIT(14))
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_M  (LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V << LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S)
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S  14
+
+/** LP_SYSTEM_REG_LP_RST_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_RST_CTRL_REG (DR_REG_LP_SYS_BASE + 0x10)
+/** LP_SYSTEM_REG_ANA_RST_BYPASS : R/W; bitpos: [0]; default: 1;
+ *  analog source reset bypass : wdt,brown out,super wdt,glitch
+ */
+#define LP_SYSTEM_REG_ANA_RST_BYPASS    (BIT(0))
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_M  (LP_SYSTEM_REG_ANA_RST_BYPASS_V << LP_SYSTEM_REG_ANA_RST_BYPASS_S)
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_S  0
+/** LP_SYSTEM_REG_SYS_RST_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
+ */
+#define LP_SYSTEM_REG_SYS_RST_BYPASS    (BIT(1))
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_M  (LP_SYSTEM_REG_SYS_RST_BYPASS_V << LP_SYSTEM_REG_SYS_RST_BYPASS_S)
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_S  1
+/** LP_SYSTEM_REG_EFUSE_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  efuse force no reset control
+ */
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST    (BIT(2))
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_M  (LP_SYSTEM_REG_EFUSE_FORCE_NORST_V << LP_SYSTEM_REG_EFUSE_FORCE_NORST_S)
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_V  0x00000001U
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_S  2
+
+/** LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG (DR_REG_LP_SYS_BASE + 0x18)
+/** LP_SYSTEM_REG_LP_CPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 1343225856;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_M  (LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V << LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S)
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S  0
+
+/** LP_SYSTEM_REG_EXT_WAKEUP1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_REG (DR_REG_LP_SYS_BASE + 0x1c)
+/** LP_SYSTEM_REG_EXT_WAKEUP1_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  Bitmap to select RTC pads for ext wakeup1
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_M  (LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V << LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S  0
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR : WT; bitpos: [16]; default: 0;
+ *  clear ext wakeup1 status
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR    (BIT(16))
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S  16
+
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG (DR_REG_LP_SYS_BASE + 0x20)
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS : RO; bitpos: [15:0]; default: 0;
+ *  ext wakeup1 status
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS    0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V  0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG (DR_REG_LP_SYS_BASE + 0x24)
+/** LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON    (BIT(5))
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S  5
+/** LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON    (BIT(7))
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S  7
+
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG (DR_REG_LP_SYS_BASE + 0x28)
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP    0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V << LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S)
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S  0
+
+/** LP_SYSTEM_REG_LP_STORE0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE0_REG (DR_REG_LP_SYS_BASE + 0x2c)
+/** LP_SYSTEM_REG_LP_SCRATCH0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH0    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH0_M  (LP_SYSTEM_REG_LP_SCRATCH0_V << LP_SYSTEM_REG_LP_SCRATCH0_S)
+#define LP_SYSTEM_REG_LP_SCRATCH0_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH0_S  0
+
+/** LP_SYSTEM_REG_LP_STORE1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE1_REG (DR_REG_LP_SYS_BASE + 0x30)
+/** LP_SYSTEM_REG_LP_SCRATCH1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH1    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH1_M  (LP_SYSTEM_REG_LP_SCRATCH1_V << LP_SYSTEM_REG_LP_SCRATCH1_S)
+#define LP_SYSTEM_REG_LP_SCRATCH1_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH1_S  0
+
+/** LP_SYSTEM_REG_LP_STORE2_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE2_REG (DR_REG_LP_SYS_BASE + 0x34)
+/** LP_SYSTEM_REG_LP_SCRATCH2 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH2    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH2_M  (LP_SYSTEM_REG_LP_SCRATCH2_V << LP_SYSTEM_REG_LP_SCRATCH2_S)
+#define LP_SYSTEM_REG_LP_SCRATCH2_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH2_S  0
+
+/** LP_SYSTEM_REG_LP_STORE3_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE3_REG (DR_REG_LP_SYS_BASE + 0x38)
+/** LP_SYSTEM_REG_LP_SCRATCH3 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH3    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH3_M  (LP_SYSTEM_REG_LP_SCRATCH3_V << LP_SYSTEM_REG_LP_SCRATCH3_S)
+#define LP_SYSTEM_REG_LP_SCRATCH3_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH3_S  0
+
+/** LP_SYSTEM_REG_LP_STORE4_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE4_REG (DR_REG_LP_SYS_BASE + 0x3c)
+/** LP_SYSTEM_REG_LP_SCRATCH4 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH4    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH4_M  (LP_SYSTEM_REG_LP_SCRATCH4_V << LP_SYSTEM_REG_LP_SCRATCH4_S)
+#define LP_SYSTEM_REG_LP_SCRATCH4_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH4_S  0
+
+/** LP_SYSTEM_REG_LP_STORE5_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE5_REG (DR_REG_LP_SYS_BASE + 0x40)
+/** LP_SYSTEM_REG_LP_SCRATCH5 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH5    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH5_M  (LP_SYSTEM_REG_LP_SCRATCH5_V << LP_SYSTEM_REG_LP_SCRATCH5_S)
+#define LP_SYSTEM_REG_LP_SCRATCH5_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH5_S  0
+
+/** LP_SYSTEM_REG_LP_STORE6_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE6_REG (DR_REG_LP_SYS_BASE + 0x44)
+/** LP_SYSTEM_REG_LP_SCRATCH6 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH6    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH6_M  (LP_SYSTEM_REG_LP_SCRATCH6_V << LP_SYSTEM_REG_LP_SCRATCH6_S)
+#define LP_SYSTEM_REG_LP_SCRATCH6_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH6_S  0
+
+/** LP_SYSTEM_REG_LP_STORE7_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE7_REG (DR_REG_LP_SYS_BASE + 0x48)
+/** LP_SYSTEM_REG_LP_SCRATCH7 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH7    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH7_M  (LP_SYSTEM_REG_LP_SCRATCH7_V << LP_SYSTEM_REG_LP_SCRATCH7_S)
+#define LP_SYSTEM_REG_LP_SCRATCH7_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH7_S  0
+
+/** LP_SYSTEM_REG_LP_STORE8_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE8_REG (DR_REG_LP_SYS_BASE + 0x4c)
+/** LP_SYSTEM_REG_LP_SCRATCH8 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH8    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH8_M  (LP_SYSTEM_REG_LP_SCRATCH8_V << LP_SYSTEM_REG_LP_SCRATCH8_S)
+#define LP_SYSTEM_REG_LP_SCRATCH8_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH8_S  0
+
+/** LP_SYSTEM_REG_LP_STORE9_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE9_REG (DR_REG_LP_SYS_BASE + 0x50)
+/** LP_SYSTEM_REG_LP_SCRATCH9 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH9    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH9_M  (LP_SYSTEM_REG_LP_SCRATCH9_V << LP_SYSTEM_REG_LP_SCRATCH9_S)
+#define LP_SYSTEM_REG_LP_SCRATCH9_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH9_S  0
+
+/** LP_SYSTEM_REG_LP_STORE10_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE10_REG (DR_REG_LP_SYS_BASE + 0x54)
+/** LP_SYSTEM_REG_LP_SCRATCH10 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH10    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH10_M  (LP_SYSTEM_REG_LP_SCRATCH10_V << LP_SYSTEM_REG_LP_SCRATCH10_S)
+#define LP_SYSTEM_REG_LP_SCRATCH10_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH10_S  0
+
+/** LP_SYSTEM_REG_LP_STORE11_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE11_REG (DR_REG_LP_SYS_BASE + 0x58)
+/** LP_SYSTEM_REG_LP_SCRATCH11 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH11    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH11_M  (LP_SYSTEM_REG_LP_SCRATCH11_V << LP_SYSTEM_REG_LP_SCRATCH11_S)
+#define LP_SYSTEM_REG_LP_SCRATCH11_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH11_S  0
+
+/** LP_SYSTEM_REG_LP_STORE12_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE12_REG (DR_REG_LP_SYS_BASE + 0x5c)
+/** LP_SYSTEM_REG_LP_SCRATCH12 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH12    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH12_M  (LP_SYSTEM_REG_LP_SCRATCH12_V << LP_SYSTEM_REG_LP_SCRATCH12_S)
+#define LP_SYSTEM_REG_LP_SCRATCH12_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH12_S  0
+
+/** LP_SYSTEM_REG_LP_STORE13_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE13_REG (DR_REG_LP_SYS_BASE + 0x60)
+/** LP_SYSTEM_REG_LP_SCRATCH13 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH13    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH13_M  (LP_SYSTEM_REG_LP_SCRATCH13_V << LP_SYSTEM_REG_LP_SCRATCH13_S)
+#define LP_SYSTEM_REG_LP_SCRATCH13_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH13_S  0
+
+/** LP_SYSTEM_REG_LP_STORE14_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE14_REG (DR_REG_LP_SYS_BASE + 0x64)
+/** LP_SYSTEM_REG_LP_SCRATCH14 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH14    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH14_M  (LP_SYSTEM_REG_LP_SCRATCH14_V << LP_SYSTEM_REG_LP_SCRATCH14_S)
+#define LP_SYSTEM_REG_LP_SCRATCH14_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH14_S  0
+
+/** LP_SYSTEM_REG_LP_STORE15_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE15_REG (DR_REG_LP_SYS_BASE + 0x68)
+/** LP_SYSTEM_REG_LP_SCRATCH15 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH15    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH15_M  (LP_SYSTEM_REG_LP_SCRATCH15_V << LP_SYSTEM_REG_LP_SCRATCH15_S)
+#define LP_SYSTEM_REG_LP_SCRATCH15_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH15_S  0
+
+/** LP_SYSTEM_REG_LP_PROBEA_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBEA_CTRL_REG (DR_REG_LP_SYS_BASE + 0x6c)
+/** LP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_A_MOD_SEL_V << LP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
+/** LP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_A_TOP_SEL_V << LP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
+/** LP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
+#define LP_SYSTEM_REG_PROBE_L_SEL_M  (LP_SYSTEM_REG_PROBE_L_SEL_V << LP_SYSTEM_REG_PROBE_L_SEL_S)
+#define LP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
+#define LP_SYSTEM_REG_PROBE_L_SEL_S  24
+/** LP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
+#define LP_SYSTEM_REG_PROBE_H_SEL_M  (LP_SYSTEM_REG_PROBE_H_SEL_V << LP_SYSTEM_REG_PROBE_H_SEL_S)
+#define LP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
+#define LP_SYSTEM_REG_PROBE_H_SEL_S  26
+/** LP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (LP_SYSTEM_REG_PROBE_GLOBAL_EN_V << LP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
+
+/** LP_SYSTEM_REG_LP_PROBEB_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBEB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x70)
+/** LP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_B_MOD_SEL_V << LP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
+/** LP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_B_TOP_SEL_V << LP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
+/** LP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
+#define LP_SYSTEM_REG_PROBE_B_EN_M  (LP_SYSTEM_REG_PROBE_B_EN_V << LP_SYSTEM_REG_PROBE_B_EN_S)
+#define LP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
+#define LP_SYSTEM_REG_PROBE_B_EN_S  24
+
+/** LP_SYSTEM_REG_LP_PROBE_OUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBE_OUT_REG (DR_REG_LP_SYS_BASE + 0x74)
+/** LP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_M  (LP_SYSTEM_REG_PROBE_TOP_OUT_V << LP_SYSTEM_REG_PROBE_TOP_OUT_S)
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_S  0
+
+/** LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG (DR_REG_LP_SYS_BASE + 0x9c)
+/** LP_SYSTEM_REG_F2S_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN    (BIT(0))
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_M  (LP_SYSTEM_REG_F2S_APB_POSTW_EN_V << LP_SYSTEM_REG_F2S_APB_POSTW_EN_S)
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_V  0x00000001U
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_S  0
+
+/** LP_SYSTEM_REG_USB_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_USB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x100)
+/** LP_SYSTEM_REG_SW_HW_USB_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL    (BIT(0))
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S)
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S  0
+/** LP_SYSTEM_REG_SW_USB_PHY_SEL : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL    (BIT(1))
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_USB_PHY_SEL_S)
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_S  1
+/** LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR : WT; bitpos: [2]; default: 0;
+ *  clear usb wakeup to PMU.
+ */
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR    (BIT(2))
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_M  (LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V << LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S)
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S  2
+/** LP_SYSTEM_REG_USBOTG20_IN_SUSPEND : R/W; bitpos: [3]; default: 0;
+ *  indicate usb otg2.0 is in suspend state.
+ */
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND    (BIT(3))
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_M  (LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V << LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S)
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V  0x00000001U
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S  3
+
+/** LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG (DR_REG_LP_SYS_BASE + 0x10c)
+/** LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP : R/W; bitpos: [7:0]; default: 255;
+ *  Set 1 to power up pad group
+ */
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP    0x000000FFU
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_M  (LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V << LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S)
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V  0x000000FFU
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x110)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S  0
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT    (BIT(1))
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S  1
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x114)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x118)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x11c)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S  0
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT    (BIT(1))
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S  1
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x120)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x124)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0x130)
+/** LP_SYSTEM_REG_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  clock gate enable for hp cpu root 400M clk
+ */
+#define LP_SYSTEM_REG_CPU_CLK_EN    (BIT(0))
+#define LP_SYSTEM_REG_CPU_CLK_EN_M  (LP_SYSTEM_REG_CPU_CLK_EN_V << LP_SYSTEM_REG_CPU_CLK_EN_S)
+#define LP_SYSTEM_REG_CPU_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_CPU_CLK_EN_S  0
+/** LP_SYSTEM_REG_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  clock gate enable for hp sys root 480M clk
+ */
+#define LP_SYSTEM_REG_SYS_CLK_EN    (BIT(1))
+#define LP_SYSTEM_REG_SYS_CLK_EN_M  (LP_SYSTEM_REG_SYS_CLK_EN_V << LP_SYSTEM_REG_SYS_CLK_EN_S)
+#define LP_SYSTEM_REG_SYS_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_CLK_EN_S  1
+
+/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x138)
+/** LP_SYSTEM_REG_PMU_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_M  (LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V << LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x13c)
+/** LP_SYSTEM_REG_PMU_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V << LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_PAD_COMP0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PAD_COMP0_REG (DR_REG_LP_SYS_BASE + 0x148)
+/** LP_SYSTEM_REG_DREF_COMP0 : R/W; bitpos: [2:0]; default: 0;
+ *  pad comp dref
+ */
+#define LP_SYSTEM_REG_DREF_COMP0    0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP0_M  (LP_SYSTEM_REG_DREF_COMP0_V << LP_SYSTEM_REG_DREF_COMP0_S)
+#define LP_SYSTEM_REG_DREF_COMP0_V  0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP0_S  0
+/** LP_SYSTEM_REG_MODE_COMP0 : R/W; bitpos: [3]; default: 0;
+ *  pad comp mode
+ */
+#define LP_SYSTEM_REG_MODE_COMP0    (BIT(3))
+#define LP_SYSTEM_REG_MODE_COMP0_M  (LP_SYSTEM_REG_MODE_COMP0_V << LP_SYSTEM_REG_MODE_COMP0_S)
+#define LP_SYSTEM_REG_MODE_COMP0_V  0x00000001U
+#define LP_SYSTEM_REG_MODE_COMP0_S  3
+/** LP_SYSTEM_REG_XPD_COMP0 : R/W; bitpos: [4]; default: 0;
+ *  pad comp xpd
+ */
+#define LP_SYSTEM_REG_XPD_COMP0    (BIT(4))
+#define LP_SYSTEM_REG_XPD_COMP0_M  (LP_SYSTEM_REG_XPD_COMP0_V << LP_SYSTEM_REG_XPD_COMP0_S)
+#define LP_SYSTEM_REG_XPD_COMP0_V  0x00000001U
+#define LP_SYSTEM_REG_XPD_COMP0_S  4
+
+/** LP_SYSTEM_REG_PAD_COMP1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PAD_COMP1_REG (DR_REG_LP_SYS_BASE + 0x14c)
+/** LP_SYSTEM_REG_DREF_COMP1 : R/W; bitpos: [2:0]; default: 0;
+ *  pad comp dref
+ */
+#define LP_SYSTEM_REG_DREF_COMP1    0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP1_M  (LP_SYSTEM_REG_DREF_COMP1_V << LP_SYSTEM_REG_DREF_COMP1_S)
+#define LP_SYSTEM_REG_DREF_COMP1_V  0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP1_S  0
+/** LP_SYSTEM_REG_MODE_COMP1 : R/W; bitpos: [3]; default: 0;
+ *  pad comp mode
+ */
+#define LP_SYSTEM_REG_MODE_COMP1    (BIT(3))
+#define LP_SYSTEM_REG_MODE_COMP1_M  (LP_SYSTEM_REG_MODE_COMP1_V << LP_SYSTEM_REG_MODE_COMP1_S)
+#define LP_SYSTEM_REG_MODE_COMP1_V  0x00000001U
+#define LP_SYSTEM_REG_MODE_COMP1_S  3
+/** LP_SYSTEM_REG_XPD_COMP1 : R/W; bitpos: [4]; default: 0;
+ *  pad comp xpd
+ */
+#define LP_SYSTEM_REG_XPD_COMP1    (BIT(4))
+#define LP_SYSTEM_REG_XPD_COMP1_M  (LP_SYSTEM_REG_XPD_COMP1_V << LP_SYSTEM_REG_XPD_COMP1_S)
+#define LP_SYSTEM_REG_XPD_COMP1_V  0x00000001U
+#define LP_SYSTEM_REG_XPD_COMP1_S  4
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG (DR_REG_LP_SYS_BASE + 0x154)
+/** LP_SYSTEM_REG_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BURST_LIMIT_AON    0x0000001FU
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_M  (LP_SYSTEM_REG_BURST_LIMIT_AON_V << LP_SYSTEM_REG_BURST_LIMIT_AON_S)
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_V  0x0000001FU
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_S  0
+/** LP_SYSTEM_REG_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_READ_INTERVAL_AON    0x0000007FU
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_M  (LP_SYSTEM_REG_READ_INTERVAL_AON_V << LP_SYSTEM_REG_READ_INTERVAL_AON_S)
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_V  0x0000007FU
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_S  5
+/** LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [21:12]; default: 100;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON    0x000003FFU
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S)
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V  0x000003FFU
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S  12
+/** LP_SYSTEM_REG_LINK_TOUT_THRES_AON : R/W; bitpos: [31:22]; default: 100;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON    0x000003FFU
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S)
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V  0x000003FFU
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S  22
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG (DR_REG_LP_SYS_BASE + 0x158)
+/** LP_SYSTEM_REG_AON_BYPASS : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_AON_BYPASS    (BIT(31))
+#define LP_SYSTEM_REG_AON_BYPASS_M  (LP_SYSTEM_REG_AON_BYPASS_V << LP_SYSTEM_REG_AON_BYPASS_S)
+#define LP_SYSTEM_REG_AON_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_AON_BYPASS_S  31
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG (DR_REG_LP_SYS_BASE + 0x15c)
+/** LP_SYSTEM_REG_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_ADDR_AON    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LINK_ADDR_AON_M  (LP_SYSTEM_REG_LINK_ADDR_AON_V << LP_SYSTEM_REG_LINK_ADDR_AON_S)
+#define LP_SYSTEM_REG_LINK_ADDR_AON_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LINK_ADDR_AON_S  0
+
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG (DR_REG_LP_SYS_BASE + 0x164)
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1    0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V << LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S)
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S  0
+
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x168)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S  0
+
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x16c)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+ *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+ *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID    0x0000001FU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ID_V << LP_SYSTEM_REG_LP_ADDRHOLE_ID_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_V  0x0000001FU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_S  0
+/** LP_SYSTEM_REG_LP_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
+ *  1:write trans, 0: read trans.
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR    (BIT(5))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_WR_V << LP_SYSTEM_REG_LP_ADDRHOLE_WR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_S  5
+/** LP_SYSTEM_REG_LP_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
+ *  1: illegal address access, 0: access without permission
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE    (BIT(6))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S  6
+
+/** LP_SYSTEM_REG_INT_RAW_REG register
+ *  raw interrupt register
+ */
+#define LP_SYSTEM_REG_INT_RAW_REG (DR_REG_LP_SYS_BASE + 0x170)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
+ *  matrix default slave)
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  the raw interrupt status of lp core ahb bus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  the raw interrupt status of lp core  ibus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  the raw interrupt status of lp core  dbus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  the raw interrupt status of etm task ulp
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  the raw interrupt status of slow_clk_tick
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S  6
+
+/** LP_SYSTEM_REG_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define LP_SYSTEM_REG_INT_ST_REG (DR_REG_LP_SYS_BASE + 0x174)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
+ *  matrix default slave)
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of lp core ahb bus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of lp core  ibus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of lp core  dbus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of etm task ulp
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST : RO; bitpos: [6]; default: 0;
+ *  the masked interrupt status of slow_clk_tick
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S  6
+
+/** LP_SYSTEM_REG_INT_ENA_REG register
+ *  masked interrupt register
+ */
+#define LP_SYSTEM_REG_INT_ENA_REG (DR_REG_LP_SYS_BASE + 0x178)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable lp addrhole int
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable idbus addrhole int
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable lp_core_ahb_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable lp_core_ibus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable lp_core_dbus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable etm task ulp int
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable slow_clk_tick int
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S  6
+
+/** LP_SYSTEM_REG_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define LP_SYSTEM_REG_INT_CLR_REG (DR_REG_LP_SYS_BASE + 0x17c)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  write 1 to clear lp addrhole int
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  write 1 to clear idbus addrhole int
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear lp_core_ahb_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear lp_core_ibus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear lp_core_dbus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear etm tasl ulp int
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear slow_clk_tick int
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S  6
+
+/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180)
+/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184)
+/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x188)
+/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x18c)
+/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_CPU_DBG_PC_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_REG (DR_REG_LP_SYS_BASE + 0x190)
+/** LP_SYSTEM_REG_LP_CPU_DBG_PC : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_M  (LP_SYSTEM_REG_LP_CPU_DBG_PC_V << LP_SYSTEM_REG_LP_CPU_DBG_PC_S)
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_S  0
+
+/** LP_SYSTEM_REG_LP_CPU_EXC_PC_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_REG (DR_REG_LP_SYS_BASE + 0x194)
+/** LP_SYSTEM_REG_LP_CPU_EXC_PC : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_M  (LP_SYSTEM_REG_LP_CPU_EXC_PC_V << LP_SYSTEM_REG_LP_CPU_EXC_PC_S)
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_S  0
+
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x198)
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S  0
+
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x19c)
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID    0x0000001FU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V  0x0000001FU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR    (BIT(5))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S  5
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE    (BIT(6))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S  6
+
+/** LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1a0)
+/** LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL : R/W; bitpos: [15:8]; default: 255;
+ *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
+ *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
+ *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
+ *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
+ *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
+ *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
+ *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
+ *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
+ */
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL    0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S)
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V  0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S  8
+/** LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL : R/W; bitpos: [31:24]; default: 255;
+ *  [31] 1'b1: po_rstn bypass sys_sw_rstn
+ *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
+ *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
+ *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
+ *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
+ *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
+ *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
+ *  [24] 1'b1: po_rstn bypass efuse_err_rstn
+ */
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL    0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S)
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V  0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S  24
+
+/** LP_SYSTEM_REG_RNG_DATA_REG register
+ *  rng data register
+ */
+#define LP_SYSTEM_REG_RNG_DATA_REG (DR_REG_LP_SYS_BASE + 0x1a4)
+/** LP_SYSTEM_REG_RND_DATA : RO; bitpos: [31:0]; default: 0;
+ *  result of rng output
+ */
+#define LP_SYSTEM_REG_RND_DATA    0xFFFFFFFFU
+#define LP_SYSTEM_REG_RND_DATA_M  (LP_SYSTEM_REG_RND_DATA_V << LP_SYSTEM_REG_RND_DATA_S)
+#define LP_SYSTEM_REG_RND_DATA_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_RND_DATA_S  0
+
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b0)
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core ahb timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core ahb bus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S  1
+/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN : R/W; bitpos: [17]; default: 1;
+ *  set this field to 1 to enable lp2hp ahb timeout handle
+ */
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN    (BIT(17))
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S  17
+/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES : R/W; bitpos: [22:18]; default: 31;
+ *  This field used to set lp2hp ahb bus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES    0x0000001FU
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V  0x0000001FU
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S  18
+
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b4)
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core ibus timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core ibus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S  1
+
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b8)
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core dbus timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core dbus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S  1
+
+/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG (DR_REG_LP_SYS_BASE + 0x1bc)
+/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
+ *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
+ *  disable ahb err resp.
+ */
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS    0x00000007U
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_M  (LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V << LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S)
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V  0x00000007U
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S  0
+
+/** LP_SYSTEM_REG_RNG_CFG_REG register
+ *  rng cfg register
+ */
+#define LP_SYSTEM_REG_RNG_CFG_REG (DR_REG_LP_SYS_BASE + 0x1c0)
+/** LP_SYSTEM_REG_RNG_TIMER_EN : R/W; bitpos: [0]; default: 1;
+ *  enable rng timer
+ */
+#define LP_SYSTEM_REG_RNG_TIMER_EN    (BIT(0))
+#define LP_SYSTEM_REG_RNG_TIMER_EN_M  (LP_SYSTEM_REG_RNG_TIMER_EN_V << LP_SYSTEM_REG_RNG_TIMER_EN_S)
+#define LP_SYSTEM_REG_RNG_TIMER_EN_V  0x00000001U
+#define LP_SYSTEM_REG_RNG_TIMER_EN_S  0
+/** LP_SYSTEM_REG_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 1;
+ *  configure ng timer pscale
+ */
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE    0x000000FFU
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_M  (LP_SYSTEM_REG_RNG_TIMER_PSCALE_V << LP_SYSTEM_REG_RNG_TIMER_PSCALE_S)
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_V  0x000000FFU
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_S  1
+/** LP_SYSTEM_REG_RNG_SAR_ENABLE : R/W; bitpos: [9]; default: 0;
+ *  enable rng_saradc
+ */
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE    (BIT(9))
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_M  (LP_SYSTEM_REG_RNG_SAR_ENABLE_V << LP_SYSTEM_REG_RNG_SAR_ENABLE_S)
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_V  0x00000001U
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_S  9
+/** LP_SYSTEM_REG_RNG_SAR_DATA : RO; bitpos: [28:16]; default: 0;
+ *  debug rng sar sample cnt
+ */
+#define LP_SYSTEM_REG_RNG_SAR_DATA    0x00001FFFU
+#define LP_SYSTEM_REG_RNG_SAR_DATA_M  (LP_SYSTEM_REG_RNG_SAR_DATA_V << LP_SYSTEM_REG_RNG_SAR_DATA_S)
+#define LP_SYSTEM_REG_RNG_SAR_DATA_V  0x00001FFFU
+#define LP_SYSTEM_REG_RNG_SAR_DATA_S  16
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_sys_struct.h b/components/soc/esp32p4/include/soc/lp_sys_struct.h
new file mode 100644
index 0000000000..f54c249eec
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_sys_struct.h
@@ -0,0 +1,1333 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_sys_ver_date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ver_date : R/W; bitpos: [31:0]; default: 539165961;
+         *  need_des
+         */
+        uint32_t ver_date:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_sys_ver_date_reg_t;
+
+/** Type of clk_sel_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** ena_sw_sel_sys_clk : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t ena_sw_sel_sys_clk:1;
+        /** sw_sys_clk_src_sel : R/W; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t sw_sys_clk_src_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} lp_system_reg_clk_sel_ctrl_reg_t;
+
+/** Type of sys_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_disable : R/W; bitpos: [0]; default: 0;
+         *  lp cpu disable
+         */
+        uint32_t lp_core_disable:1;
+        /** sys_sw_rst : WT; bitpos: [1]; default: 0;
+         *  digital system software reset bit
+         */
+        uint32_t sys_sw_rst:1;
+        /** force_download_boot : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t force_download_boot:1;
+        /** dig_fib : R/W; bitpos: [10:3]; default: 255;
+         *  need_des
+         */
+        uint32_t dig_fib:8;
+        /** io_mux_reset_disable : R/W; bitpos: [11]; default: 0;
+         *  reset disable bit for LP IOMUX
+         */
+        uint32_t io_mux_reset_disable:1;
+        uint32_t reserved_12:2;
+        /** ana_fib : RO; bitpos: [20:14]; default: 127;
+         *  need_des
+         */
+        uint32_t ana_fib:7;
+        /** lp_fib_sel : R/W; bitpos: [28:21]; default: 255;
+         *  need_des
+         */
+        uint32_t lp_fib_sel:8;
+        /** lp_core_etm_wakeup_flag_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_core_etm_wakeup_flag_clr:1;
+        /** lp_core_etm_wakeup_flag : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_core_etm_wakeup_flag:1;
+        /** systimer_stall_sel : R/W; bitpos: [31]; default: 0;
+         *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
+         *  hp_core1
+         */
+        uint32_t systimer_stall_sel:1;
+    };
+    uint32_t val;
+} lp_system_reg_sys_ctrl_reg_t;
+
+/** Type of lp_clk_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:13;
+        /** lp_fosc_hp_cken : R/W; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t lp_fosc_hp_cken:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} lp_system_reg_lp_clk_ctrl_reg_t;
+
+/** Type of lp_rst_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_rst_bypass : R/W; bitpos: [0]; default: 1;
+         *  analog source reset bypass : wdt,brown out,super wdt,glitch
+         */
+        uint32_t ana_rst_bypass:1;
+        /** sys_rst_bypass : R/W; bitpos: [1]; default: 1;
+         *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
+         */
+        uint32_t sys_rst_bypass:1;
+        /** efuse_force_norst : R/W; bitpos: [2]; default: 0;
+         *  efuse force no reset control
+         */
+        uint32_t efuse_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_system_reg_lp_rst_ctrl_reg_t;
+
+/** Type of lp_core_boot_addr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_boot_addr : R/W; bitpos: [31:0]; default: 1343225856;
+         *  need_des
+         */
+        uint32_t lp_cpu_boot_addr:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_boot_addr_reg_t;
+
+/** Type of ext_wakeup1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup1_sel : R/W; bitpos: [15:0]; default: 0;
+         *  Bitmap to select RTC pads for ext wakeup1
+         */
+        uint32_t ext_wakeup1_sel:16;
+        /** ext_wakeup1_status_clr : WT; bitpos: [16]; default: 0;
+         *  clear ext wakeup1 status
+         */
+        uint32_t ext_wakeup1_status_clr:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_system_reg_ext_wakeup1_reg_t;
+
+/** Type of ext_wakeup1_status register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup1_status : RO; bitpos: [15:0]; default: 0;
+         *  ext wakeup1 status
+         */
+        uint32_t ext_wakeup1_status:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_system_reg_ext_wakeup1_status_reg_t;
+
+/** Type of lp_tcm_pwr_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** lp_tcm_rom_clk_force_on : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_clk_force_on:1;
+        uint32_t reserved_6:1;
+        /** lp_tcm_ram_clk_force_on : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_clk_force_on:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_pwr_ctrl_reg_t;
+
+/** Type of boot_addr_hp_lp_reg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** boot_addr_hp_lp : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t boot_addr_hp_lp:32;
+    };
+    uint32_t val;
+} lp_system_reg_boot_addr_hp_lp_reg_reg_t;
+
+/** Type of lp_store0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch0:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store0_reg_t;
+
+/** Type of lp_store1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch1:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store1_reg_t;
+
+/** Type of lp_store2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch2 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch2:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store2_reg_t;
+
+/** Type of lp_store3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch3 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch3:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store3_reg_t;
+
+/** Type of lp_store4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch4 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch4:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store4_reg_t;
+
+/** Type of lp_store5 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch5 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch5:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store5_reg_t;
+
+/** Type of lp_store6 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch6 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch6:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store6_reg_t;
+
+/** Type of lp_store7 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch7 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch7:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store7_reg_t;
+
+/** Type of lp_store8 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch8 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch8:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store8_reg_t;
+
+/** Type of lp_store9 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch9 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch9:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store9_reg_t;
+
+/** Type of lp_store10 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch10 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch10:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store10_reg_t;
+
+/** Type of lp_store11 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch11 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch11:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store11_reg_t;
+
+/** Type of lp_store12 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch12 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch12:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store12_reg_t;
+
+/** Type of lp_store13 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch13 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch13:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store13_reg_t;
+
+/** Type of lp_store14 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch14 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch14:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store14_reg_t;
+
+/** Type of lp_store15 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch15 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch15:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store15_reg_t;
+
+/** Type of lp_probea_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_a_mod_sel:16;
+        /** probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_a_top_sel:8;
+        /** probe_l_sel : R/W; bitpos: [25:24]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_l_sel:2;
+        /** probe_h_sel : R/W; bitpos: [27:26]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_h_sel:2;
+        /** probe_global_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_global_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_system_reg_lp_probea_ctrl_reg_t;
+
+/** Type of lp_probeb_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_b_mod_sel:16;
+        /** probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_b_top_sel:8;
+        /** probe_b_en : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_b_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} lp_system_reg_lp_probeb_ctrl_reg_t;
+
+/** Type of lp_probe_out register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** probe_top_out : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_top_out:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_probe_out_reg_t;
+
+/** Type of f2s_apb_brg_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** f2s_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t f2s_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_system_reg_f2s_apb_brg_cntl_reg_t;
+
+/** Type of usb_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sw_hw_usb_phy_sel : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_hw_usb_phy_sel:1;
+        /** sw_usb_phy_sel : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_usb_phy_sel:1;
+        /** usbotg20_wakeup_clr : WT; bitpos: [2]; default: 0;
+         *  clear usb wakeup to PMU.
+         */
+        uint32_t usbotg20_wakeup_clr:1;
+        /** usbotg20_in_suspend : R/W; bitpos: [3]; default: 0;
+         *  indicate usb otg2.0 is in suspend state.
+         */
+        uint32_t usbotg20_in_suspend:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_system_reg_usb_ctrl_reg_t;
+
+/** Type of ana_xpd_pad_group register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_reg_xpd_pad_group : R/W; bitpos: [7:0]; default: 255;
+         *  Set 1 to power up pad group
+         */
+        uint32_t ana_reg_xpd_pad_group:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_system_reg_ana_xpd_pad_group_reg_t;
+
+/** Type of lp_tcm_ram_rdn_eco_cs register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_ram_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_en:1;
+        /** lp_tcm_ram_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t;
+
+/** Type of lp_tcm_ram_rdn_eco_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_ram_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t;
+
+/** Type of lp_tcm_ram_rdn_eco_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_ram_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t;
+
+/** Type of lp_tcm_rom_rdn_eco_cs register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_rom_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_en:1;
+        /** lp_tcm_rom_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t;
+
+/** Type of lp_tcm_rom_rdn_eco_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_rom_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t;
+
+/** Type of lp_tcm_rom_rdn_eco_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_rom_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t;
+
+/** Type of hp_root_clk_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_clk_en : R/W; bitpos: [0]; default: 1;
+         *  clock gate enable for hp cpu root 400M clk
+         */
+        uint32_t cpu_clk_en:1;
+        /** sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  clock gate enable for hp sys root 480M clk
+         */
+        uint32_t sys_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_system_reg_hp_root_clk_ctrl_reg_t;
+
+/** Type of lp_pmu_rdn_eco_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_pmu_rdn_eco_low_reg_t;
+
+/** Type of lp_pmu_rdn_eco_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t pmu_rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_pmu_rdn_eco_high_reg_t;
+
+/** Type of pad_comp0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dref_comp0 : R/W; bitpos: [2:0]; default: 0;
+         *  pad comp dref
+         */
+        uint32_t dref_comp0:3;
+        /** mode_comp0 : R/W; bitpos: [3]; default: 0;
+         *  pad comp mode
+         */
+        uint32_t mode_comp0:1;
+        /** xpd_comp0 : R/W; bitpos: [4]; default: 0;
+         *  pad comp xpd
+         */
+        uint32_t xpd_comp0:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lp_system_reg_pad_comp0_reg_t;
+
+/** Type of pad_comp1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dref_comp1 : R/W; bitpos: [2:0]; default: 0;
+         *  pad comp dref
+         */
+        uint32_t dref_comp1:3;
+        /** mode_comp1 : R/W; bitpos: [3]; default: 0;
+         *  pad comp mode
+         */
+        uint32_t mode_comp1:1;
+        /** xpd_comp1 : R/W; bitpos: [4]; default: 0;
+         *  pad comp xpd
+         */
+        uint32_t xpd_comp1:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lp_system_reg_pad_comp1_reg_t;
+
+/** Type of backup_dma_cfg0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** burst_limit_aon : R/W; bitpos: [4:0]; default: 10;
+         *  need_des
+         */
+        uint32_t burst_limit_aon:5;
+        /** read_interval_aon : R/W; bitpos: [11:5]; default: 10;
+         *  need_des
+         */
+        uint32_t read_interval_aon:7;
+        /** link_backup_tout_thres_aon : R/W; bitpos: [21:12]; default: 100;
+         *  need_des
+         */
+        uint32_t link_backup_tout_thres_aon:10;
+        /** link_tout_thres_aon : R/W; bitpos: [31:22]; default: 100;
+         *  need_des
+         */
+        uint32_t link_tout_thres_aon:10;
+    };
+    uint32_t val;
+} lp_system_reg_backup_dma_cfg0_reg_t;
+
+/** Type of backup_dma_cfg1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** aon_bypass : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t aon_bypass:1;
+    };
+    uint32_t val;
+} lp_system_reg_backup_dma_cfg1_reg_t;
+
+/** Type of backup_dma_cfg2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** link_addr_aon : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t link_addr_aon:32;
+    };
+    uint32_t val;
+} lp_system_reg_backup_dma_cfg2_reg_t;
+
+/** Type of boot_addr_hp_core1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** boot_addr_hp_core1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t boot_addr_hp_core1:32;
+    };
+    uint32_t val;
+} lp_system_reg_boot_addr_hp_core1_reg_t;
+
+/** Type of hp_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t hp_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_hp_mem_aux_ctrl_reg_t;
+
+/** Type of lp_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t lp_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_mem_aux_ctrl_reg_t;
+
+/** Type of hp_rom_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
+         *  need_des
+         */
+        uint32_t hp_rom_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_hp_rom_aux_ctrl_reg_t;
+
+/** Type of lp_rom_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
+         *  need_des
+         */
+        uint32_t lp_rom_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_rom_aux_ctrl_reg_t;
+
+/** Type of hp_por_rst_bypass_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** hp_po_cnnt_rstn_bypass_ctrl : R/W; bitpos: [15:8]; default: 255;
+         *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
+         *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
+         *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
+         *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
+         *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
+         *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
+         *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
+         *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
+         */
+        uint32_t hp_po_cnnt_rstn_bypass_ctrl:8;
+        uint32_t reserved_16:8;
+        /** hp_po_rstn_bypass_ctrl : R/W; bitpos: [31:24]; default: 255;
+         *  [31] 1'b1: po_rstn bypass sys_sw_rstn
+         *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
+         *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
+         *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
+         *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
+         *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
+         *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
+         *  [24] 1'b1: po_rstn bypass efuse_err_rstn
+         */
+        uint32_t hp_po_rstn_bypass_ctrl:8;
+    };
+    uint32_t val;
+} lp_system_reg_hp_por_rst_bypass_ctrl_reg_t;
+
+/** Type of lp_core_ahb_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_ahb_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable lp core ahb timeout handle
+         */
+        uint32_t lp_core_ahb_timeout_en:1;
+        /** lp_core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set lp core ahb bus timeout  threshold
+         */
+        uint32_t lp_core_ahb_timeout_thres:16;
+        /** lp2hp_ahb_timeout_en : R/W; bitpos: [17]; default: 1;
+         *  set this field to 1 to enable lp2hp ahb timeout handle
+         */
+        uint32_t lp2hp_ahb_timeout_en:1;
+        /** lp2hp_ahb_timeout_thres : R/W; bitpos: [22:18]; default: 31;
+         *  This field used to set lp2hp ahb bus timeout  threshold
+         */
+        uint32_t lp2hp_ahb_timeout_thres:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_ahb_timeout_reg_t;
+
+/** Type of lp_core_ibus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_ibus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable lp core ibus timeout handle
+         */
+        uint32_t lp_core_ibus_timeout_en:1;
+        /** lp_core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set lp core ibus timeout  threshold
+         */
+        uint32_t lp_core_ibus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_ibus_timeout_reg_t;
+
+/** Type of lp_core_dbus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_dbus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable lp core dbus timeout handle
+         */
+        uint32_t lp_core_dbus_timeout_en:1;
+        /** lp_core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set lp core dbus timeout  threshold
+         */
+        uint32_t lp_core_dbus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_dbus_timeout_reg_t;
+
+
+/** Group: status_register */
+/** Type of lp_addrhole_addr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_addrhole_addr:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_addrhole_addr_reg_t;
+
+/** Type of lp_addrhole_info register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_id : RO; bitpos: [4:0]; default: 0;
+         *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+         *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+         *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+         */
+        uint32_t lp_addrhole_id:5;
+        /** lp_addrhole_wr : RO; bitpos: [5]; default: 0;
+         *  1:write trans, 0: read trans.
+         */
+        uint32_t lp_addrhole_wr:1;
+        /** lp_addrhole_secure : RO; bitpos: [6]; default: 0;
+         *  1: illegal address access, 0: access without permission
+         */
+        uint32_t lp_addrhole_secure:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_lp_addrhole_info_reg_t;
+
+/** Type of lp_cpu_dbg_pc register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_dbg_pc : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_dbg_pc:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_cpu_dbg_pc_reg_t;
+
+/** Type of lp_cpu_exc_pc register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_exc_pc : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_exc_pc:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_cpu_exc_pc_reg_t;
+
+/** Type of idbus_addrhole_addr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** idbus_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_addr:32;
+    };
+    uint32_t val;
+} lp_system_reg_idbus_addrhole_addr_reg_t;
+
+/** Type of idbus_addrhole_info register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** idbus_addrhole_id : RO; bitpos: [4:0]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_id:5;
+        /** idbus_addrhole_wr : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_wr:1;
+        /** idbus_addrhole_secure : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_secure:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_idbus_addrhole_info_reg_t;
+
+/** Type of rng_data register
+ *  rng data register
+ */
+typedef union {
+    struct {
+        /** rnd_data : RO; bitpos: [31:0]; default: 0;
+         *  result of rng output
+         */
+        uint32_t rnd_data:32;
+    };
+    uint32_t val;
+} lp_system_reg_rng_data_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  raw interrupt register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
+         *  matrix default slave)
+         */
+        uint32_t lp_addrhole_int_raw:1;
+        /** idbus_addrhole_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+         */
+        uint32_t idbus_addrhole_int_raw:1;
+        /** lp_core_ahb_timeout_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  the raw interrupt status of lp core ahb bus timeout
+         */
+        uint32_t lp_core_ahb_timeout_int_raw:1;
+        /** lp_core_ibus_timeout_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  the raw interrupt status of lp core  ibus timeout
+         */
+        uint32_t lp_core_ibus_timeout_int_raw:1;
+        /** lp_core_dbus_timeout_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  the raw interrupt status of lp core  dbus timeout
+         */
+        uint32_t lp_core_dbus_timeout_int_raw:1;
+        /** etm_task_ulp_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  the raw interrupt status of etm task ulp
+         */
+        uint32_t etm_task_ulp_int_raw:1;
+        /** slow_clk_tick_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  the raw interrupt status of slow_clk_tick
+         */
+        uint32_t slow_clk_tick_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_raw_reg_t;
+
+/** Type of int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
+         *  matrix default slave)
+         */
+        uint32_t lp_addrhole_int_st:1;
+        /** idbus_addrhole_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+         */
+        uint32_t idbus_addrhole_int_st:1;
+        /** lp_core_ahb_timeout_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of lp core ahb bus timeout
+         */
+        uint32_t lp_core_ahb_timeout_int_st:1;
+        /** lp_core_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of lp core  ibus timeout
+         */
+        uint32_t lp_core_ibus_timeout_int_st:1;
+        /** lp_core_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of lp core  dbus timeout
+         */
+        uint32_t lp_core_dbus_timeout_int_st:1;
+        /** etm_task_ulp_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of etm task ulp
+         */
+        uint32_t etm_task_ulp_int_st:1;
+        /** slow_clk_tick_int_st : RO; bitpos: [6]; default: 0;
+         *  the masked interrupt status of slow_clk_tick
+         */
+        uint32_t slow_clk_tick_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_st_reg_t;
+
+/** Type of int_ena register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable lp addrhole int
+         */
+        uint32_t lp_addrhole_int_ena:1;
+        /** idbus_addrhole_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable idbus addrhole int
+         */
+        uint32_t idbus_addrhole_int_ena:1;
+        /** lp_core_ahb_timeout_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable lp_core_ahb_timeout int
+         */
+        uint32_t lp_core_ahb_timeout_int_ena:1;
+        /** lp_core_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable lp_core_ibus_timeout int
+         */
+        uint32_t lp_core_ibus_timeout_int_ena:1;
+        /** lp_core_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable lp_core_dbus_timeout int
+         */
+        uint32_t lp_core_dbus_timeout_int_ena:1;
+        /** etm_task_ulp_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable etm task ulp int
+         */
+        uint32_t etm_task_ulp_int_ena:1;
+        /** slow_clk_tick_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable slow_clk_tick int
+         */
+        uint32_t slow_clk_tick_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to clear lp addrhole int
+         */
+        uint32_t lp_addrhole_int_clr:1;
+        /** idbus_addrhole_int_clr : WT; bitpos: [1]; default: 0;
+         *  write 1 to clear idbus addrhole int
+         */
+        uint32_t idbus_addrhole_int_clr:1;
+        /** lp_core_ahb_timeout_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear lp_core_ahb_timeout int
+         */
+        uint32_t lp_core_ahb_timeout_int_clr:1;
+        /** lp_core_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear lp_core_ibus_timeout int
+         */
+        uint32_t lp_core_ibus_timeout_int_clr:1;
+        /** lp_core_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear lp_core_dbus_timeout int
+         */
+        uint32_t lp_core_dbus_timeout_int_clr:1;
+        /** etm_task_ulp_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear etm tasl ulp int
+         */
+        uint32_t etm_task_ulp_int_clr:1;
+        /** slow_clk_tick_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear slow_clk_tick int
+         */
+        uint32_t slow_clk_tick_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_clr_reg_t;
+
+
+/** Group: control registers */
+/** Type of lp_core_err_resp_dis register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
+         *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
+         *  disable ahb err resp.
+         */
+        uint32_t lp_core_err_resp_dis:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_err_resp_dis_reg_t;
+
+/** Type of rng_cfg register
+ *  rng cfg register
+ */
+typedef union {
+    struct {
+        /** rng_timer_en : R/W; bitpos: [0]; default: 1;
+         *  enable rng timer
+         */
+        uint32_t rng_timer_en:1;
+        /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 1;
+         *  configure ng timer pscale
+         */
+        uint32_t rng_timer_pscale:8;
+        /** rng_sar_enable : R/W; bitpos: [9]; default: 0;
+         *  enable rng_saradc
+         */
+        uint32_t rng_sar_enable:1;
+        uint32_t reserved_10:6;
+        /** rng_sar_data : RO; bitpos: [28:16]; default: 0;
+         *  debug rng sar sample cnt
+         */
+        uint32_t rng_sar_data:13;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_system_reg_rng_cfg_reg_t;
+
+
+typedef struct {
+    volatile lp_system_reg_lp_sys_ver_date_reg_t lp_sys_ver_date;
+    volatile lp_system_reg_clk_sel_ctrl_reg_t clk_sel_ctrl;
+    volatile lp_system_reg_sys_ctrl_reg_t sys_ctrl;
+    volatile lp_system_reg_lp_clk_ctrl_reg_t lp_clk_ctrl;
+    volatile lp_system_reg_lp_rst_ctrl_reg_t lp_rst_ctrl;
+    uint32_t reserved_014;
+    volatile lp_system_reg_lp_core_boot_addr_reg_t lp_core_boot_addr;
+    volatile lp_system_reg_ext_wakeup1_reg_t ext_wakeup1;
+    volatile lp_system_reg_ext_wakeup1_status_reg_t ext_wakeup1_status;
+    volatile lp_system_reg_lp_tcm_pwr_ctrl_reg_t lp_tcm_pwr_ctrl;
+    volatile lp_system_reg_boot_addr_hp_lp_reg_reg_t boot_addr_hp_lp_reg;
+    volatile lp_system_reg_lp_store0_reg_t lp_store0;
+    volatile lp_system_reg_lp_store1_reg_t lp_store1;
+    volatile lp_system_reg_lp_store2_reg_t lp_store2;
+    volatile lp_system_reg_lp_store3_reg_t lp_store3;
+    volatile lp_system_reg_lp_store4_reg_t lp_store4;
+    volatile lp_system_reg_lp_store5_reg_t lp_store5;
+    volatile lp_system_reg_lp_store6_reg_t lp_store6;
+    volatile lp_system_reg_lp_store7_reg_t lp_store7;
+    volatile lp_system_reg_lp_store8_reg_t lp_store8;
+    volatile lp_system_reg_lp_store9_reg_t lp_store9;
+    volatile lp_system_reg_lp_store10_reg_t lp_store10;
+    volatile lp_system_reg_lp_store11_reg_t lp_store11;
+    volatile lp_system_reg_lp_store12_reg_t lp_store12;
+    volatile lp_system_reg_lp_store13_reg_t lp_store13;
+    volatile lp_system_reg_lp_store14_reg_t lp_store14;
+    volatile lp_system_reg_lp_store15_reg_t lp_store15;
+    volatile lp_system_reg_lp_probea_ctrl_reg_t lp_probea_ctrl;
+    volatile lp_system_reg_lp_probeb_ctrl_reg_t lp_probeb_ctrl;
+    volatile lp_system_reg_lp_probe_out_reg_t lp_probe_out;
+    uint32_t reserved_078[9];
+    volatile lp_system_reg_f2s_apb_brg_cntl_reg_t f2s_apb_brg_cntl;
+    uint32_t reserved_0a0[24];
+    volatile lp_system_reg_usb_ctrl_reg_t usb_ctrl;
+    uint32_t reserved_104[2];
+    volatile lp_system_reg_ana_xpd_pad_group_reg_t ana_xpd_pad_group;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t lp_tcm_ram_rdn_eco_cs;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t lp_tcm_ram_rdn_eco_low;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t lp_tcm_ram_rdn_eco_high;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t lp_tcm_rom_rdn_eco_cs;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t lp_tcm_rom_rdn_eco_low;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t lp_tcm_rom_rdn_eco_high;
+    uint32_t reserved_128[2];
+    volatile lp_system_reg_hp_root_clk_ctrl_reg_t hp_root_clk_ctrl;
+    uint32_t reserved_134;
+    volatile lp_system_reg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low;
+    volatile lp_system_reg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high;
+    uint32_t reserved_140[2];
+    volatile lp_system_reg_pad_comp0_reg_t pad_comp0;
+    volatile lp_system_reg_pad_comp1_reg_t pad_comp1;
+    uint32_t reserved_150;
+    volatile lp_system_reg_backup_dma_cfg0_reg_t backup_dma_cfg0;
+    volatile lp_system_reg_backup_dma_cfg1_reg_t backup_dma_cfg1;
+    volatile lp_system_reg_backup_dma_cfg2_reg_t backup_dma_cfg2;
+    uint32_t reserved_160;
+    volatile lp_system_reg_boot_addr_hp_core1_reg_t boot_addr_hp_core1;
+    volatile lp_system_reg_lp_addrhole_addr_reg_t lp_addrhole_addr;
+    volatile lp_system_reg_lp_addrhole_info_reg_t lp_addrhole_info;
+    volatile lp_system_reg_int_raw_reg_t int_raw;
+    volatile lp_system_reg_int_st_reg_t int_st;
+    volatile lp_system_reg_int_ena_reg_t int_ena;
+    volatile lp_system_reg_int_clr_reg_t int_clr;
+    volatile lp_system_reg_hp_mem_aux_ctrl_reg_t hp_mem_aux_ctrl;
+    volatile lp_system_reg_lp_mem_aux_ctrl_reg_t lp_mem_aux_ctrl;
+    volatile lp_system_reg_hp_rom_aux_ctrl_reg_t hp_rom_aux_ctrl;
+    volatile lp_system_reg_lp_rom_aux_ctrl_reg_t lp_rom_aux_ctrl;
+    volatile lp_system_reg_lp_cpu_dbg_pc_reg_t lp_cpu_dbg_pc;
+    volatile lp_system_reg_lp_cpu_exc_pc_reg_t lp_cpu_exc_pc;
+    volatile lp_system_reg_idbus_addrhole_addr_reg_t idbus_addrhole_addr;
+    volatile lp_system_reg_idbus_addrhole_info_reg_t idbus_addrhole_info;
+    volatile lp_system_reg_hp_por_rst_bypass_ctrl_reg_t hp_por_rst_bypass_ctrl;
+    volatile lp_system_reg_rng_data_reg_t rng_data;
+    uint32_t reserved_1a8[2];
+    volatile lp_system_reg_lp_core_ahb_timeout_reg_t lp_core_ahb_timeout;
+    volatile lp_system_reg_lp_core_ibus_timeout_reg_t lp_core_ibus_timeout;
+    volatile lp_system_reg_lp_core_dbus_timeout_reg_t lp_core_dbus_timeout;
+    volatile lp_system_reg_lp_core_err_resp_dis_reg_t lp_core_err_resp_dis;
+    volatile lp_system_reg_rng_cfg_reg_t rng_cfg;
+} lp_system_reg_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_system_reg_dev_t) == 0x1c4, "Invalid size of lp_system_reg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_tee_reg.h b/components/soc/esp32p4/include/soc/lp_tee_reg.h
new file mode 100644
index 0000000000..932c959d04
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_tee_reg.h
@@ -0,0 +1,65 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_TEE_M0_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
+/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define LP_TEE_M0_MODE    0x00000003U
+#define LP_TEE_M0_MODE_M  (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
+#define LP_TEE_M0_MODE_V  0x00000003U
+#define LP_TEE_M0_MODE_S  0
+
+/** LP_TEE_CLOCK_GATE_REG register
+ *  Clock gating register
+ */
+#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
+/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reg_clk_en
+ */
+#define LP_TEE_CLK_EN    (BIT(0))
+#define LP_TEE_CLK_EN_M  (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
+#define LP_TEE_CLK_EN_V  0x00000001U
+#define LP_TEE_CLK_EN_S  0
+
+/** LP_TEE_FORCE_ACC_HP_REG register
+ *  need_des
+ */
+#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
+/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_TEE_FORCE_ACC_HPMEM_EN    (BIT(0))
+#define LP_TEE_FORCE_ACC_HPMEM_EN_M  (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
+#define LP_TEE_FORCE_ACC_HPMEM_EN_V  0x00000001U
+#define LP_TEE_FORCE_ACC_HPMEM_EN_S  0
+
+/** LP_TEE_DATE_REG register
+ *  Version register
+ */
+#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
+/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688;
+ *  reg_tee_date
+ */
+#define LP_TEE_DATE_REG    0x0FFFFFFFU
+#define LP_TEE_DATE_REG_M  (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
+#define LP_TEE_DATE_REG_V  0x0FFFFFFFU
+#define LP_TEE_DATE_REG_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_tee_struct.h b/components/soc/esp32p4/include/soc/lp_tee_struct.h
new file mode 100644
index 0000000000..b769f963c6
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_tee_struct.h
@@ -0,0 +1,95 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Tee mode control register */
+/** Type of m0_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m0_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m0_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_tee_m0_mode_ctrl_reg_t;
+
+
+/** Group: clock gating register */
+/** Type of clock_gate register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reg_clk_en
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_tee_clock_gate_reg_t;
+
+
+/** Group: configure_register */
+/** Type of force_acc_hp register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t force_acc_hpmem_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_tee_force_acc_hp_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date_reg : R/W; bitpos: [27:0]; default: 35672688;
+         *  reg_tee_date
+         */
+        uint32_t date_reg:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_tee_date_reg_t;
+
+
+typedef struct lp_tee_dev_t {
+    volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
+    volatile lp_tee_clock_gate_reg_t clock_gate;
+    uint32_t reserved_008[34];
+    volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
+    uint32_t reserved_094[26];
+    volatile lp_tee_date_reg_t date;
+} lp_tee_dev_t;
+
+extern lp_tee_dev_t LP_TEE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_timer_reg.h b/components/soc/esp32p4/include/soc/lp_timer_reg.h
new file mode 100644
index 0000000000..46d19733a7
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_timer_reg.h
@@ -0,0 +1,342 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_TIMER_TAR0_LOW_REG register
+ *  need_des
+ */
+#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
+/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_TAR_LOW0    0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M  (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
+#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V  0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S  0
+
+/** LP_TIMER_TAR0_HIGH_REG register
+ *  need_des
+ */
+#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
+/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH0    0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M  (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V  0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S  0
+/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_TAR_EN0    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_TAR_EN0_M  (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
+#define LP_TIMER_MAIN_TIMER_TAR_EN0_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_TAR_EN0_S  31
+
+/** LP_TIMER_TAR1_LOW_REG register
+ *  need_des
+ */
+#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
+/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_TAR_LOW1    0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M  (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
+#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V  0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S  0
+
+/** LP_TIMER_TAR1_HIGH_REG register
+ *  need_des
+ */
+#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
+/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH1    0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M  (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V  0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S  0
+/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_TAR_EN1    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_TAR_EN1_M  (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
+#define LP_TIMER_MAIN_TIMER_TAR_EN1_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_TAR_EN1_S  31
+
+/** LP_TIMER_UPDATE_REG register
+ *  need_des
+ */
+#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
+/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_UPDATE    (BIT(28))
+#define LP_TIMER_MAIN_TIMER_UPDATE_M  (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
+#define LP_TIMER_MAIN_TIMER_UPDATE_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_UPDATE_S  28
+/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_XTAL_OFF    (BIT(29))
+#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M  (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
+#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S  29
+/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_SYS_STALL    (BIT(30))
+#define LP_TIMER_MAIN_TIMER_SYS_STALL_M  (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
+#define LP_TIMER_MAIN_TIMER_SYS_STALL_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_SYS_STALL_S  30
+/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_SYS_RST    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_SYS_RST_M  (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
+#define LP_TIMER_MAIN_TIMER_SYS_RST_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_SYS_RST_S  31
+
+/** LP_TIMER_MAIN_BUF0_LOW_REG register
+ *  need_des
+ */
+#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
+/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_BUF0_LOW    0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M  (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
+#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V  0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S  0
+
+/** LP_TIMER_MAIN_BUF0_HIGH_REG register
+ *  need_des
+ */
+#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
+/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_BUF0_HIGH    0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M  (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
+#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V  0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S  0
+
+/** LP_TIMER_MAIN_BUF1_LOW_REG register
+ *  need_des
+ */
+#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
+/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_BUF1_LOW    0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M  (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
+#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V  0xFFFFFFFFU
+#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S  0
+
+/** LP_TIMER_MAIN_BUF1_HIGH_REG register
+ *  need_des
+ */
+#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
+/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_BUF1_HIGH    0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M  (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
+#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V  0x0000FFFFU
+#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S  0
+
+/** LP_TIMER_MAIN_OVERFLOW_REG register
+ *  need_des
+ */
+#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
+/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_ALARM_LOAD    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M  (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
+#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S  31
+
+/** LP_TIMER_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
+/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_OVERFLOW_RAW    (BIT(30))
+#define LP_TIMER_OVERFLOW_RAW_M  (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
+#define LP_TIMER_OVERFLOW_RAW_V  0x00000001U
+#define LP_TIMER_OVERFLOW_RAW_S  30
+/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_SOC_WAKEUP_INT_RAW    (BIT(31))
+#define LP_TIMER_SOC_WAKEUP_INT_RAW_M  (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
+#define LP_TIMER_SOC_WAKEUP_INT_RAW_V  0x00000001U
+#define LP_TIMER_SOC_WAKEUP_INT_RAW_S  31
+
+/** LP_TIMER_INT_ST_REG register
+ *  need_des
+ */
+#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
+/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_OVERFLOW_ST    (BIT(30))
+#define LP_TIMER_OVERFLOW_ST_M  (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
+#define LP_TIMER_OVERFLOW_ST_V  0x00000001U
+#define LP_TIMER_OVERFLOW_ST_S  30
+/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_SOC_WAKEUP_INT_ST    (BIT(31))
+#define LP_TIMER_SOC_WAKEUP_INT_ST_M  (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
+#define LP_TIMER_SOC_WAKEUP_INT_ST_V  0x00000001U
+#define LP_TIMER_SOC_WAKEUP_INT_ST_S  31
+
+/** LP_TIMER_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
+/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_OVERFLOW_ENA    (BIT(30))
+#define LP_TIMER_OVERFLOW_ENA_M  (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
+#define LP_TIMER_OVERFLOW_ENA_V  0x00000001U
+#define LP_TIMER_OVERFLOW_ENA_S  30
+/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_SOC_WAKEUP_INT_ENA    (BIT(31))
+#define LP_TIMER_SOC_WAKEUP_INT_ENA_M  (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
+#define LP_TIMER_SOC_WAKEUP_INT_ENA_V  0x00000001U
+#define LP_TIMER_SOC_WAKEUP_INT_ENA_S  31
+
+/** LP_TIMER_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
+/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_OVERFLOW_CLR    (BIT(30))
+#define LP_TIMER_OVERFLOW_CLR_M  (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
+#define LP_TIMER_OVERFLOW_CLR_V  0x00000001U
+#define LP_TIMER_OVERFLOW_CLR_S  30
+/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_SOC_WAKEUP_INT_CLR    (BIT(31))
+#define LP_TIMER_SOC_WAKEUP_INT_CLR_M  (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
+#define LP_TIMER_SOC_WAKEUP_INT_CLR_V  0x00000001U
+#define LP_TIMER_SOC_WAKEUP_INT_CLR_S  31
+
+/** LP_TIMER_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
+/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW    (BIT(30))
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S  30
+/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_LP_INT_RAW    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M  (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
+#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S  31
+
+/** LP_TIMER_LP_INT_ST_REG register
+ *  need_des
+ */
+#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
+/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST    (BIT(30))
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S  30
+/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_LP_INT_ST    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M  (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
+#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S  31
+
+/** LP_TIMER_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
+/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA    (BIT(30))
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S  30
+/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_LP_INT_ENA    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M  (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
+#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S  31
+
+/** LP_TIMER_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
+/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR    (BIT(30))
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S  30
+/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_MAIN_TIMER_LP_INT_CLR    (BIT(31))
+#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M  (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
+#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V  0x00000001U
+#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S  31
+
+/** LP_TIMER_DATE_REG register
+ *  need_des
+ */
+#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
+/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
+ *  need_des
+ */
+#define LP_TIMER_DATE    0x7FFFFFFFU
+#define LP_TIMER_DATE_M  (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
+#define LP_TIMER_DATE_V  0x7FFFFFFFU
+#define LP_TIMER_DATE_S  0
+/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_TIMER_CLK_EN    (BIT(31))
+#define LP_TIMER_CLK_EN_M  (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
+#define LP_TIMER_CLK_EN_V  0x00000001U
+#define LP_TIMER_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_timer_struct.h b/components/soc/esp32p4/include/soc/lp_timer_struct.h
new file mode 100644
index 0000000000..4809c3d3b9
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_timer_struct.h
@@ -0,0 +1,363 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of tar0_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_low0:32;
+    };
+    uint32_t val;
+} lp_timer_tar0_low_reg_t;
+
+/** Type of tar0_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_high0:16;
+        uint32_t reserved_16:15;
+        /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_en0:1;
+    };
+    uint32_t val;
+} lp_timer_tar0_high_reg_t;
+
+/** Type of tar1_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_low1:32;
+    };
+    uint32_t val;
+} lp_timer_tar1_low_reg_t;
+
+/** Type of tar1_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_high1:16;
+        uint32_t reserved_16:15;
+        /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_en1:1;
+    };
+    uint32_t val;
+} lp_timer_tar1_high_reg_t;
+
+/** Type of update register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** main_timer_update : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_update:1;
+        /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_xtal_off:1;
+        /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_stall:1;
+        /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_rst:1;
+    };
+    uint32_t val;
+} lp_timer_update_reg_t;
+
+/** Type of main_buf0_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf0_low:32;
+    };
+    uint32_t val;
+} lp_timer_main_buf0_low_reg_t;
+
+/** Type of main_buf0_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf0_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_timer_main_buf0_high_reg_t;
+
+/** Type of main_buf1_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf1_low:32;
+    };
+    uint32_t val;
+} lp_timer_main_buf1_low_reg_t;
+
+/** Type of main_buf1_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf1_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_timer_main_buf1_high_reg_t;
+
+/** Type of main_overflow register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_alarm_load:1;
+    };
+    uint32_t val;
+} lp_timer_main_overflow_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_raw:1;
+        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_st:1;
+        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_ena:1;
+        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_clr:1;
+        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_raw:1;
+        /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_st:1;
+        /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_ena:1;
+        /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_clr:1;
+        /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 34672976;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_timer_date_reg_t;
+
+
+typedef struct lp_timer_dev_t {
+    volatile lp_timer_tar0_low_reg_t tar0_low;
+    volatile lp_timer_tar0_high_reg_t tar0_high;
+    volatile lp_timer_tar1_low_reg_t tar1_low;
+    volatile lp_timer_tar1_high_reg_t tar1_high;
+    volatile lp_timer_update_reg_t update;
+    volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
+    volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
+    volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
+    volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
+    volatile lp_timer_main_overflow_reg_t main_overflow;
+    volatile lp_timer_int_raw_reg_t int_raw;
+    volatile lp_timer_int_st_reg_t int_st;
+    volatile lp_timer_int_ena_reg_t int_ena;
+    volatile lp_timer_int_clr_reg_t int_clr;
+    volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_timer_lp_int_st_reg_t lp_int_st;
+    volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
+    uint32_t reserved_048[237];
+    volatile lp_timer_date_reg_t date;
+} lp_timer_dev_t;
+
+extern lp_timer_dev_t LP_TIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_wdt_reg.h b/components/soc/esp32p4/include/soc/lp_wdt_reg.h
new file mode 100644
index 0000000000..f1cfb609e2
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_wdt_reg.h
@@ -0,0 +1,517 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-5730 (better to rename and move to wdt_types.h?)
+/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
+#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
+#define LP_WDT_RTC_WDTCONFIG0_REG          (DR_REG_LP_WDT_BASE + 0x0)
+/* LP_WDT_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define LP_WDT_WDT_EN    (BIT(31))
+#define LP_WDT_WDT_EN_M  (BIT(31))
+#define LP_WDT_WDT_EN_V  0x1
+#define LP_WDT_WDT_EN_S  31
+/* LP_WDT_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
+reset stage en.*/
+#define LP_WDT_WDT_STG0    0x00000007
+#define LP_WDT_WDT_STG0_M  ((LP_WDT_WDT_STG0_V)<<(LP_WDT_WDT_STG0_S))
+#define LP_WDT_WDT_STG0_V  0x7
+#define LP_WDT_WDT_STG0_S  28
+/* LP_WDT_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
+reset stage en.*/
+#define LP_WDT_WDT_STG1    0x00000007
+#define LP_WDT_WDT_STG1_M  ((LP_WDT_WDT_STG1_V)<<(LP_WDT_WDT_STG1_S))
+#define LP_WDT_WDT_STG1_V  0x7
+#define LP_WDT_WDT_STG1_S  25
+/* LP_WDT_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
+reset stage en.*/
+#define LP_WDT_WDT_STG2    0x00000007
+#define LP_WDT_WDT_STG2_M  ((LP_WDT_WDT_STG2_V)<<(LP_WDT_WDT_STG2_S))
+#define LP_WDT_WDT_STG2_V  0x7
+#define LP_WDT_WDT_STG2_S  22
+/* LP_WDT_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
+reset stage en.*/
+#define LP_WDT_WDT_STG3    0x00000007
+#define LP_WDT_WDT_STG3_M  ((LP_WDT_WDT_STG3_V)<<(LP_WDT_WDT_STG3_S))
+#define LP_WDT_WDT_STG3_V  0x7
+#define LP_WDT_WDT_STG3_S  19
+/* LP_WDT_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: CPU reset counter length.*/
+#define LP_WDT_WDT_CPU_RESET_LENGTH    0x00000007
+#define LP_WDT_WDT_CPU_RESET_LENGTH_M  ((LP_WDT_WDT_CPU_RESET_LENGTH_V)<<(LP_WDT_WDT_CPU_RESET_LENGTH_S))
+#define LP_WDT_WDT_CPU_RESET_LENGTH_V  0x7
+#define LP_WDT_WDT_CPU_RESET_LENGTH_S  16
+/* LP_WDT_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
+/*description: system reset counter length.*/
+#define LP_WDT_WDT_SYS_RESET_LENGTH    0x00000007
+#define LP_WDT_WDT_SYS_RESET_LENGTH_M  ((LP_WDT_WDT_SYS_RESET_LENGTH_V)<<(LP_WDT_WDT_SYS_RESET_LENGTH_S))
+#define LP_WDT_WDT_SYS_RESET_LENGTH_V  0x7
+#define LP_WDT_WDT_SYS_RESET_LENGTH_S  13
+/* LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: enable WDT in flash boot.*/
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN    (BIT(12))
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S  12
+/* LP_WDT_WDT_PAUSE_IN_SLP : R/W ;bitpos:[11] ;default: 1'd1 ; */
+/*description: pause WDT in sleep.*/
+#define LP_WDT_WDT_PAUSE_IN_SLP    (BIT(11))
+#define LP_WDT_WDT_PAUSE_IN_SLP_M  (BIT(11))
+#define LP_WDT_WDT_PAUSE_IN_SLP_V  0x1
+#define LP_WDT_WDT_PAUSE_IN_SLP_S  11
+/* LP_WDT_WDT_CHIP_RESET_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: wdt reset whole chip enable.*/
+#define LP_WDT_WDT_CHIP_RESET_EN    (BIT(10))
+#define LP_WDT_WDT_CHIP_RESET_EN_M  (BIT(10))
+#define LP_WDT_WDT_CHIP_RESET_EN_V  0x1
+#define LP_WDT_WDT_CHIP_RESET_EN_S  10
+/* LP_WDT_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[9:2] ;default: 8'd20 ; */
+/*description: chip reset siginal pulse width.*/
+#define LP_WDT_WDT_CHIP_RESET_WIDTH    0x000000FF
+#define LP_WDT_WDT_CHIP_RESET_WIDTH_M  ((LP_WDT_WDT_CHIP_RESET_WIDTH_V)<<(LP_WDT_WDT_CHIP_RESET_WIDTH_S))
+#define LP_WDT_WDT_CHIP_RESET_WIDTH_V  0xFF
+#define LP_WDT_WDT_CHIP_RESET_WIDTH_S  2
+
+#define LP_WDT_RTC_WDTCPURST_REG          (DR_REG_LP_WDT_BASE + 0x4)
+/* LP_WDT_WDT_CORE0CPU_RESET_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: enable WDT reset CORE0 CPU.*/
+#define LP_WDT_WDT_CORE0CPU_RESET_EN    (BIT(31))
+#define LP_WDT_WDT_CORE0CPU_RESET_EN_M  (BIT(31))
+#define LP_WDT_WDT_CORE0CPU_RESET_EN_V  0x1
+#define LP_WDT_WDT_CORE0CPU_RESET_EN_S  31
+/* LP_WDT_WDT_CORE1CPU_RESET_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: enable WDT reset CORE1 CPU.*/
+#define LP_WDT_WDT_CORE1CPU_RESET_EN    (BIT(30))
+#define LP_WDT_WDT_CORE1CPU_RESET_EN_M  (BIT(30))
+#define LP_WDT_WDT_CORE1CPU_RESET_EN_V  0x1
+#define LP_WDT_WDT_CORE1CPU_RESET_EN_S  30
+/* LP_WDT_WDT_CORE2CPU_RESET_EN : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: enable WDT reset CORE2 CPU.*/
+#define LP_WDT_WDT_CORE2CPU_RESET_EN    (BIT(29))
+#define LP_WDT_WDT_CORE2CPU_RESET_EN_M  (BIT(29))
+#define LP_WDT_WDT_CORE2CPU_RESET_EN_V  0x1
+#define LP_WDT_WDT_CORE2CPU_RESET_EN_S  29
+/* LP_WDT_WDT_CORE3CPU_RESET_EN : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: enable WDT reset CORE3 CPU.*/
+#define LP_WDT_WDT_CORE3CPU_RESET_EN    (BIT(28))
+#define LP_WDT_WDT_CORE3CPU_RESET_EN_M  (BIT(28))
+#define LP_WDT_WDT_CORE3CPU_RESET_EN_V  0x1
+#define LP_WDT_WDT_CORE3CPU_RESET_EN_S  28
+/* LP_WDT_WDT_LP_CPU_RESET_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: enable WDT reset LP CPU.*/
+#define LP_WDT_WDT_LP_CPU_RESET_EN    (BIT(27))
+#define LP_WDT_WDT_LP_CPU_RESET_EN_M  (BIT(27))
+#define LP_WDT_WDT_LP_CPU_RESET_EN_V  0x1
+#define LP_WDT_WDT_LP_CPU_RESET_EN_S  27
+/* LP_WDT_WDT_LP_PERI_RESET_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: enable WDT reset LP PERI.*/
+#define LP_WDT_WDT_LP_PERI_RESET_EN    (BIT(26))
+#define LP_WDT_WDT_LP_PERI_RESET_EN_M  (BIT(26))
+#define LP_WDT_WDT_LP_PERI_RESET_EN_V  0x1
+#define LP_WDT_WDT_LP_PERI_RESET_EN_S  26
+
+#define LP_WDT_RTC_WDTCONFIG1_REG          (DR_REG_LP_WDT_BASE + 0x8)
+/* LP_WDT_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
+/*description: .*/
+#define LP_WDT_WDT_STG0_HOLD    0xFFFFFFFF
+#define LP_WDT_WDT_STG0_HOLD_M  ((LP_WDT_WDT_STG0_HOLD_V)<<(LP_WDT_WDT_STG0_HOLD_S))
+#define LP_WDT_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define LP_WDT_WDT_STG0_HOLD_S  0
+
+#define LP_WDT_RTC_WDTCONFIG2_REG          (DR_REG_LP_WDT_BASE + 0xC)
+/* LP_WDT_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: .*/
+#define LP_WDT_WDT_STG1_HOLD    0xFFFFFFFF
+#define LP_WDT_WDT_STG1_HOLD_M  ((LP_WDT_WDT_STG1_HOLD_V)<<(LP_WDT_WDT_STG1_HOLD_S))
+#define LP_WDT_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define LP_WDT_WDT_STG1_HOLD_S  0
+
+#define LP_WDT_RTC_WDTCONFIG3_REG          (DR_REG_LP_WDT_BASE + 0x10)
+/* LP_WDT_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: .*/
+#define LP_WDT_WDT_STG2_HOLD    0xFFFFFFFF
+#define LP_WDT_WDT_STG2_HOLD_M  ((LP_WDT_WDT_STG2_HOLD_V)<<(LP_WDT_WDT_STG2_HOLD_S))
+#define LP_WDT_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define LP_WDT_WDT_STG2_HOLD_S  0
+
+#define LP_WDT_RTC_WDTCONFIG4_REG          (DR_REG_LP_WDT_BASE + 0x14)
+/* LP_WDT_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: .*/
+#define LP_WDT_WDT_STG3_HOLD    0xFFFFFFFF
+#define LP_WDT_WDT_STG3_HOLD_M  ((LP_WDT_WDT_STG3_HOLD_V)<<(LP_WDT_WDT_STG3_HOLD_S))
+#define LP_WDT_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define LP_WDT_WDT_STG3_HOLD_S  0
+
+#define LP_WDT_RTC_WDTFEED_REG          (DR_REG_LP_WDT_BASE + 0x18)
+/* LP_WDT_RTC_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: .*/
+#define LP_WDT_RTC_WDT_FEED    (BIT(31))
+#define LP_WDT_RTC_WDT_FEED_M  (BIT(31))
+#define LP_WDT_RTC_WDT_FEED_V  0x1
+#define LP_WDT_RTC_WDT_FEED_S  31
+
+#define LP_WDT_RTC_WDTWPROTECT_REG          (DR_REG_LP_WDT_BASE + 0x1C)
+/* LP_WDT_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: .*/
+#define LP_WDT_WDT_WKEY    0xFFFFFFFF
+#define LP_WDT_WDT_WKEY_M  ((LP_WDT_WDT_WKEY_V)<<(LP_WDT_WDT_WKEY_S))
+#define LP_WDT_WDT_WKEY_V  0xFFFFFFFF
+#define LP_WDT_WDT_WKEY_S  0
+
+#define LP_WDT_RTC_SWD_CONF_REG          (DR_REG_LP_WDT_BASE + 0x20)
+/* LP_WDT_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: automatically feed swd when int comes.*/
+#define LP_WDT_SWD_AUTO_FEED_EN    (BIT(31))
+#define LP_WDT_SWD_AUTO_FEED_EN_M  (BIT(31))
+#define LP_WDT_SWD_AUTO_FEED_EN_V  0x1
+#define LP_WDT_SWD_AUTO_FEED_EN_S  31
+/* LP_WDT_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: disabel SWD.*/
+#define LP_WDT_SWD_DISABLE    (BIT(30))
+#define LP_WDT_SWD_DISABLE_M  (BIT(30))
+#define LP_WDT_SWD_DISABLE_V  0x1
+#define LP_WDT_SWD_DISABLE_S  30
+/* LP_WDT_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Sw feed swd.*/
+#define LP_WDT_SWD_FEED    (BIT(29))
+#define LP_WDT_SWD_FEED_M  (BIT(29))
+#define LP_WDT_SWD_FEED_V  0x1
+#define LP_WDT_SWD_FEED_S  29
+/* LP_WDT_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: reset swd reset flag.*/
+#define LP_WDT_SWD_RST_FLAG_CLR    (BIT(28))
+#define LP_WDT_SWD_RST_FLAG_CLR_M  (BIT(28))
+#define LP_WDT_SWD_RST_FLAG_CLR_V  0x1
+#define LP_WDT_SWD_RST_FLAG_CLR_S  28
+/* LP_WDT_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
+/*description: adjust signal width send to swd.*/
+#define LP_WDT_SWD_SIGNAL_WIDTH    0x000003FF
+#define LP_WDT_SWD_SIGNAL_WIDTH_M  ((LP_WDT_SWD_SIGNAL_WIDTH_V)<<(LP_WDT_SWD_SIGNAL_WIDTH_S))
+#define LP_WDT_SWD_SIGNAL_WIDTH_V  0x3FF
+#define LP_WDT_SWD_SIGNAL_WIDTH_S  18
+/* LP_WDT_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: swd interrupt for feeding.*/
+#define LP_WDT_SWD_FEED_INT    (BIT(1))
+#define LP_WDT_SWD_FEED_INT_M  (BIT(1))
+#define LP_WDT_SWD_FEED_INT_V  0x1
+#define LP_WDT_SWD_FEED_INT_S  1
+/* LP_WDT_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: swd reset flag.*/
+#define LP_WDT_SWD_RESET_FLAG    (BIT(0))
+#define LP_WDT_SWD_RESET_FLAG_M  (BIT(0))
+#define LP_WDT_SWD_RESET_FLAG_V  0x1
+#define LP_WDT_SWD_RESET_FLAG_S  0
+
+#define LP_WDT_RTC_SWD_WPROTECT_REG          (DR_REG_LP_WDT_BASE + 0x24)
+/* LP_WDT_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
+/*description: swd write protect.*/
+#define LP_WDT_SWD_WKEY    0xFFFFFFFF
+#define LP_WDT_SWD_WKEY_M  ((LP_WDT_SWD_WKEY_V)<<(LP_WDT_SWD_WKEY_S))
+#define LP_WDT_SWD_WKEY_V  0xFFFFFFFF
+#define LP_WDT_SWD_WKEY_S  0
+
+#define LP_WDT_WDT_CLK_EN_REG          (DR_REG_LP_WDT_BASE + 0x28)
+/* LP_WDT_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define LP_WDT_CLK_EN    (BIT(0))
+#define LP_WDT_CLK_EN_M  (BIT(0))
+#define LP_WDT_CLK_EN_V  0x1
+#define LP_WDT_CLK_EN_S  0
+
+#define LP_WDT_INT_ENA_RTC_W1TS_REG          (DR_REG_LP_WDT_BASE + 0x2C)
+/* LP_WDT_RTC_SWD_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define LP_WDT_RTC_SWD_INT_ENA_W1TS    (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ENA_W1TS_M  (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ENA_W1TS_V  0x1
+#define LP_WDT_RTC_SWD_INT_ENA_W1TS_S  1
+/* LP_WDT_RTC_WDT_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define LP_WDT_RTC_WDT_INT_ENA_W1TS    (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ENA_W1TS_M  (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ENA_W1TS_V  0x1
+#define LP_WDT_RTC_WDT_INT_ENA_W1TS_S  0
+
+#define LP_WDT_INT_ENA_RTC_W1TC_REG          (DR_REG_LP_WDT_BASE + 0x30)
+/* LP_WDT_RTC_SWD_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define LP_WDT_RTC_SWD_INT_ENA_W1TC    (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ENA_W1TC_M  (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ENA_W1TC_V  0x1
+#define LP_WDT_RTC_SWD_INT_ENA_W1TC_S  1
+/* LP_WDT_RTC_WDT_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define LP_WDT_RTC_WDT_INT_ENA_W1TC    (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ENA_W1TC_M  (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ENA_W1TC_V  0x1
+#define LP_WDT_RTC_WDT_INT_ENA_W1TC_S  0
+
+#define LP_WDT_INT_ENA_RTC_REG          (DR_REG_LP_WDT_BASE + 0x34)
+/* LP_WDT_RTC_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt.*/
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA    (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_M  (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_V  0x1
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_S  2
+/* LP_WDT_RTC_SWD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define LP_WDT_RTC_SWD_INT_ENA    (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ENA_M  (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ENA_V  0x1
+#define LP_WDT_RTC_SWD_INT_ENA_S  1
+/* LP_WDT_RTC_WDT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define LP_WDT_RTC_WDT_INT_ENA    (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ENA_M  (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ENA_V  0x1
+#define LP_WDT_RTC_WDT_INT_ENA_S  0
+
+#define LP_WDT_INT_RAW_RTC_REG          (DR_REG_LP_WDT_BASE + 0x38)
+/* LP_WDT_RTC_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt raw.*/
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW    (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_M  (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_V  0x1
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_S  2
+/* LP_WDT_RTC_SWD_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: super watch dog interrupt raw.*/
+#define LP_WDT_RTC_SWD_INT_RAW    (BIT(1))
+#define LP_WDT_RTC_SWD_INT_RAW_M  (BIT(1))
+#define LP_WDT_RTC_SWD_INT_RAW_V  0x1
+#define LP_WDT_RTC_SWD_INT_RAW_S  1
+/* LP_WDT_RTC_WDT_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw.*/
+#define LP_WDT_RTC_WDT_INT_RAW    (BIT(0))
+#define LP_WDT_RTC_WDT_INT_RAW_M  (BIT(0))
+#define LP_WDT_RTC_WDT_INT_RAW_V  0x1
+#define LP_WDT_RTC_WDT_INT_RAW_S  0
+
+#define LP_WDT_INT_SWD_ST_RTC_REG          (DR_REG_LP_WDT_BASE + 0x3C)
+/* LP_WDT_RTC_XTAL32K_DEAD_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt state.*/
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST    (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_M  (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_V  0x1
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_S  2
+/* LP_WDT_RTC_SWD_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: super watch dog interrupt state.*/
+#define LP_WDT_RTC_SWD_INT_ST    (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ST_M  (BIT(1))
+#define LP_WDT_RTC_SWD_INT_ST_V  0x1
+#define LP_WDT_RTC_SWD_INT_ST_S  1
+/* LP_WDT_RTC_WDT_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: watch dog interrupt state.*/
+#define LP_WDT_RTC_WDT_INT_ST    (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ST_M  (BIT(0))
+#define LP_WDT_RTC_WDT_INT_ST_V  0x1
+#define LP_WDT_RTC_WDT_INT_ST_S  0
+
+#define LP_WDT_INT_CLR_RTC_REG          (DR_REG_LP_WDT_BASE + 0x40)
+/* LP_WDT_RTC_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state.*/
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR    (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_M  (BIT(2))
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_V  0x1
+#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_S  2
+/* LP_WDT_RTC_SWD_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear super watch dog interrupt state.*/
+#define LP_WDT_RTC_SWD_INT_CLR    (BIT(1))
+#define LP_WDT_RTC_SWD_INT_CLR_M  (BIT(1))
+#define LP_WDT_RTC_SWD_INT_CLR_V  0x1
+#define LP_WDT_RTC_SWD_INT_CLR_S  1
+/* LP_WDT_RTC_WDT_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state.*/
+#define LP_WDT_RTC_WDT_INT_CLR    (BIT(0))
+#define LP_WDT_RTC_WDT_INT_CLR_M  (BIT(0))
+#define LP_WDT_RTC_WDT_INT_CLR_V  0x1
+#define LP_WDT_RTC_WDT_INT_CLR_S  0
+
+#define LP_WDT_RTC_EXT_XTL_CONF_REG          (DR_REG_LP_WDT_BASE + 0x44)
+/* LP_WDT_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define LP_WDT_XTL_EXT_CTR_EN    (BIT(31))
+#define LP_WDT_XTL_EXT_CTR_EN_M  (BIT(31))
+#define LP_WDT_XTL_EXT_CTR_EN_V  0x1
+#define LP_WDT_XTL_EXT_CTR_EN_S  31
+/* LP_WDT_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level; 1: power down XTAL at low level.*/
+#define LP_WDT_XTL_EXT_CTR_LV    (BIT(30))
+#define LP_WDT_XTL_EXT_CTR_LV_M  (BIT(30))
+#define LP_WDT_XTL_EXT_CTR_LV_V  0x1
+#define LP_WDT_XTL_EXT_CTR_LV_S  30
+/* LP_WDT_RTC_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C.*/
+#define LP_WDT_RTC_XTAL32K_GPIO_SEL    (BIT(23))
+#define LP_WDT_RTC_XTAL32K_GPIO_SEL_M  (BIT(23))
+#define LP_WDT_RTC_XTAL32K_GPIO_SEL_V  0x1
+#define LP_WDT_RTC_XTAL32K_GPIO_SEL_S  23
+/* LP_WDT_RTC_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
+/*description: state of 32k_wdt.*/
+#define LP_WDT_RTC_WDT_STATE    0x00000007
+#define LP_WDT_RTC_WDT_STATE_M  ((LP_WDT_RTC_WDT_STATE_V)<<(LP_WDT_RTC_WDT_STATE_S))
+#define LP_WDT_RTC_WDT_STATE_V  0x7
+#define LP_WDT_RTC_WDT_STATE_S  20
+/* LP_WDT_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
+/*description: DAC_XTAL_32K.*/
+#define LP_WDT_DAC_XTAL_32K    0x00000007
+#define LP_WDT_DAC_XTAL_32K_M  ((LP_WDT_DAC_XTAL_32K_V)<<(LP_WDT_DAC_XTAL_32K_S))
+#define LP_WDT_DAC_XTAL_32K_V  0x7
+#define LP_WDT_DAC_XTAL_32K_S  17
+/* LP_WDT_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: XPD_XTAL_32K.*/
+#define LP_WDT_XPD_XTAL_32K    (BIT(16))
+#define LP_WDT_XPD_XTAL_32K_M  (BIT(16))
+#define LP_WDT_XPD_XTAL_32K_V  0x1
+#define LP_WDT_XPD_XTAL_32K_S  16
+/* LP_WDT_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
+/*description: DRES_XTAL_32K.*/
+#define LP_WDT_DRES_XTAL_32K    0x00000007
+#define LP_WDT_DRES_XTAL_32K_M  ((LP_WDT_DRES_XTAL_32K_V)<<(LP_WDT_DRES_XTAL_32K_S))
+#define LP_WDT_DRES_XTAL_32K_V  0x7
+#define LP_WDT_DRES_XTAL_32K_S  13
+/* LP_WDT_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: xtal_32k gm control.*/
+#define LP_WDT_DGM_XTAL_32K    0x00000007
+#define LP_WDT_DGM_XTAL_32K_M  ((LP_WDT_DGM_XTAL_32K_V)<<(LP_WDT_DGM_XTAL_32K_S))
+#define LP_WDT_DGM_XTAL_32K_V  0x7
+#define LP_WDT_DGM_XTAL_32K_S  10
+/* LP_WDT_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 0: single-end buffer 1: differential buffer.*/
+#define LP_WDT_DBUF_XTAL_32K    (BIT(9))
+#define LP_WDT_DBUF_XTAL_32K_M  (BIT(9))
+#define LP_WDT_DBUF_XTAL_32K_V  0x1
+#define LP_WDT_DBUF_XTAL_32K_S  9
+/* LP_WDT_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: apply an internal clock to help xtal 32k to start.*/
+#define LP_WDT_ENCKINIT_XTAL_32K    (BIT(8))
+#define LP_WDT_ENCKINIT_XTAL_32K_M  (BIT(8))
+#define LP_WDT_ENCKINIT_XTAL_32K_V  0x1
+#define LP_WDT_ENCKINIT_XTAL_32K_S  8
+/* LP_WDT_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Xtal 32k xpd control by sw or fsm.*/
+#define LP_WDT_XTAL32K_XPD_FORCE    (BIT(7))
+#define LP_WDT_XTAL32K_XPD_FORCE_M  (BIT(7))
+#define LP_WDT_XTAL32K_XPD_FORCE_V  0x1
+#define LP_WDT_XTAL32K_XPD_FORCE_S  7
+/* LP_WDT_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: xtal 32k switch back xtal when xtal is restarted.*/
+#define LP_WDT_XTAL32K_AUTO_RETURN    (BIT(6))
+#define LP_WDT_XTAL32K_AUTO_RETURN_M  (BIT(6))
+#define LP_WDT_XTAL32K_AUTO_RETURN_V  0x1
+#define LP_WDT_XTAL32K_AUTO_RETURN_S  6
+/* LP_WDT_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: xtal 32k restart xtal when xtal is dead.*/
+#define LP_WDT_XTAL32K_AUTO_RESTART    (BIT(5))
+#define LP_WDT_XTAL32K_AUTO_RESTART_M  (BIT(5))
+#define LP_WDT_XTAL32K_AUTO_RESTART_V  0x1
+#define LP_WDT_XTAL32K_AUTO_RESTART_S  5
+/* LP_WDT_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: xtal 32k switch to back up clock when xtal is dead.*/
+#define LP_WDT_XTAL32K_AUTO_BACKUP    (BIT(4))
+#define LP_WDT_XTAL32K_AUTO_BACKUP_M  (BIT(4))
+#define LP_WDT_XTAL32K_AUTO_BACKUP_V  0x1
+#define LP_WDT_XTAL32K_AUTO_BACKUP_S  4
+/* LP_WDT_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: xtal 32k external xtal clock force on.*/
+#define LP_WDT_XTAL32K_EXT_CLK_FO    (BIT(3))
+#define LP_WDT_XTAL32K_EXT_CLK_FO_M  (BIT(3))
+#define LP_WDT_XTAL32K_EXT_CLK_FO_V  0x1
+#define LP_WDT_XTAL32K_EXT_CLK_FO_S  3
+/* LP_WDT_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog sw reset.*/
+#define LP_WDT_XTAL32K_WDT_RESET    (BIT(2))
+#define LP_WDT_XTAL32K_WDT_RESET_M  (BIT(2))
+#define LP_WDT_XTAL32K_WDT_RESET_V  0x1
+#define LP_WDT_XTAL32K_WDT_RESET_S  2
+/* LP_WDT_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog clock force on.*/
+#define LP_WDT_XTAL32K_WDT_CLK_FO    (BIT(1))
+#define LP_WDT_XTAL32K_WDT_CLK_FO_M  (BIT(1))
+#define LP_WDT_XTAL32K_WDT_CLK_FO_V  0x1
+#define LP_WDT_XTAL32K_WDT_CLK_FO_S  1
+/* LP_WDT_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog enable.*/
+#define LP_WDT_XTAL32K_WDT_EN    (BIT(0))
+#define LP_WDT_XTAL32K_WDT_EN_M  (BIT(0))
+#define LP_WDT_XTAL32K_WDT_EN_V  0x1
+#define LP_WDT_XTAL32K_WDT_EN_S  0
+
+#define LP_WDT_RTC_XTAL32K_CLK_FACTOR_REG          (DR_REG_LP_WDT_BASE + 0x48)
+/* LP_WDT_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: xtal 32k watch dog backup clock factor.*/
+#define LP_WDT_XTAL32K_CLK_FACTOR    0xFFFFFFFF
+#define LP_WDT_XTAL32K_CLK_FACTOR_M  ((LP_WDT_XTAL32K_CLK_FACTOR_V)<<(LP_WDT_XTAL32K_CLK_FACTOR_S))
+#define LP_WDT_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
+#define LP_WDT_XTAL32K_CLK_FACTOR_S  0
+
+#define LP_WDT_RTC_XTAL32K_CONF_REG          (DR_REG_LP_WDT_BASE + 0x5C)
+/* LP_WDT_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: if restarted xtal32k period is smaller than this, it is regarded as stable.*/
+#define LP_WDT_XTAL32K_STABLE_THRES    0x0000000F
+#define LP_WDT_XTAL32K_STABLE_THRES_M  ((LP_WDT_XTAL32K_STABLE_THRES_V)<<(LP_WDT_XTAL32K_STABLE_THRES_S))
+#define LP_WDT_XTAL32K_STABLE_THRES_V  0xF
+#define LP_WDT_XTAL32K_STABLE_THRES_S  28
+/* LP_WDT_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
+/*description: If no clock detected for this amount of time,32k is regarded as dead.*/
+#define LP_WDT_XTAL32K_WDT_TIMEOUT    0x000000FF
+#define LP_WDT_XTAL32K_WDT_TIMEOUT_M  ((LP_WDT_XTAL32K_WDT_TIMEOUT_V)<<(LP_WDT_XTAL32K_WDT_TIMEOUT_S))
+#define LP_WDT_XTAL32K_WDT_TIMEOUT_V  0xFF
+#define LP_WDT_XTAL32K_WDT_TIMEOUT_S  20
+/* LP_WDT_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
+/*description: cycles to wait to repower on xtal 32k.*/
+#define LP_WDT_XTAL32K_RESTART_WAIT    0x0000FFFF
+#define LP_WDT_XTAL32K_RESTART_WAIT_M  ((LP_WDT_XTAL32K_RESTART_WAIT_V)<<(LP_WDT_XTAL32K_RESTART_WAIT_S))
+#define LP_WDT_XTAL32K_RESTART_WAIT_V  0xFFFF
+#define LP_WDT_XTAL32K_RESTART_WAIT_S  4
+/* LP_WDT_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: cycles to wait to return noral xtal 32k.*/
+#define LP_WDT_XTAL32K_RETURN_WAIT    0x0000000F
+#define LP_WDT_XTAL32K_RETURN_WAIT_M  ((LP_WDT_XTAL32K_RETURN_WAIT_V)<<(LP_WDT_XTAL32K_RETURN_WAIT_S))
+#define LP_WDT_XTAL32K_RETURN_WAIT_V  0xF
+#define LP_WDT_XTAL32K_RETURN_WAIT_S  0
+
+#define LP_WDT_RTC_EFUSE_FORCE_REG          (DR_REG_LP_WDT_BASE + 0x60)
+/* LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: lp_wdt flashboot en default choose efuse control bit.*/
+#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE    (BIT(1))
+#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_M  (BIT(1))
+#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_V  0x1
+#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_S  1
+/* LP_WDT_SWD_DISABLE_EFUSE_FORCE : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: swd disable default choose efuse control bit.*/
+#define LP_WDT_SWD_DISABLE_EFUSE_FORCE    (BIT(0))
+#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_M  (BIT(0))
+#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_V  0x1
+#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_wdt_struct.h b/components/soc/esp32p4/include/soc/lp_wdt_struct.h
new file mode 100644
index 0000000000..5d37d8ad9d
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/lp_wdt_struct.h
@@ -0,0 +1,180 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t wdt_chip_reset_width          :    8;  /*chip reset siginal pulse width*/
+            uint32_t wdt_chip_reset_en             :    1;  /*wdt reset whole chip enable*/
+            uint32_t wdt_pause_in_slp              :    1;  /*pause WDT in sleep*/
+            uint32_t wdt_flashboot_mod_en          :    1;  /*enable WDT in flash boot*/
+            uint32_t wdt_sys_reset_length          :    3;  /*system reset counter length*/
+            uint32_t wdt_cpu_reset_length          :    3;  /*CPU reset counter length*/
+            uint32_t wdt_stg3                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
+            uint32_t wdt_stg2                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
+            uint32_t wdt_stg1                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
+            uint32_t wdt_stg0                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
+            uint32_t wdt_en                        :    1;
+        };
+        uint32_t val;
+    } wdtconfig0;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;
+            uint32_t wdt_lp_peri_reset_en          :    1;  /*enable WDT reset LP PERI*/
+            uint32_t wdt_lp_cpu_reset_en           :    1;  /*enable WDT reset LP CPU*/
+            uint32_t wdt_core3cpu_reset_en         :    1;  /*enable WDT reset CORE3 CPU*/
+            uint32_t wdt_core2cpu_reset_en         :    1;  /*enable WDT reset CORE2 CPU*/
+            uint32_t wdt_core1cpu_reset_en         :    1;  /*enable WDT reset CORE1 CPU*/
+            uint32_t wdt_core0cpu_reset_en         :    1;  /*enable WDT reset CORE0 CPU*/
+        };
+        uint32_t val;
+    } wdtcpurst;
+    uint32_t wdtconfig1;
+    uint32_t wdtconfig2;
+    uint32_t wdtconfig3;
+    uint32_t wdtconfig4;
+    union {
+        struct {
+            uint32_t reserved0                     :    31;
+            uint32_t wdt_feed                      :    1;
+        };
+        uint32_t val;
+    } wdtfeed;
+    uint32_t wdtwprotect;
+    union {
+        struct {
+            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
+            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
+            uint32_t reserved2                     :    16;
+            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
+            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
+            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
+            uint32_t swd_disable                   :    1;  /*disabel SWD*/
+            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
+        };
+        uint32_t val;
+    } swd_conf;
+    uint32_t swd_wprotect;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } wdt_clk_en;
+    union {
+        struct {
+            uint32_t wdt                           :    1;  /*enable RTC WDT interrupt*/
+            uint32_t swd                           :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } int_ena_w1ts;
+    union {
+        struct {
+            uint32_t wdt                           :    1;  /*enable RTC WDT interrupt*/
+            uint32_t swd                           :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } int_ena_w1tc;
+    union {
+        struct {
+            uint32_t wdt                           :    1;  /*enable RTC WDT interrupt*/
+            uint32_t swd                           :    1;  /*enable super watch dog interrupt*/
+            uint32_t xtal32k_dead                  :    1;  /*enable xtal32k_dead  interrupt*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t wdt                           :    1;  /*RTC WDT interrupt raw*/
+            uint32_t swd                           :    1;  /*super watch dog interrupt raw*/
+            uint32_t xtal32k_dead                  :    1;  /*xtal32k dead detection interrupt raw*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t wdt                           :    1;  /*watch dog interrupt state*/
+            uint32_t swd                           :    1;  /*super watch dog interrupt state*/
+            uint32_t xtal32k_dead                  :    1;  /*xtal32k dead detection interrupt state*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } int_swd_st;
+    union {
+        struct {
+            uint32_t wdt                           :    1;  /*Clear RTC WDT interrupt state*/
+            uint32_t swd                           :    1;  /*Clear super watch dog interrupt state*/
+            uint32_t xtal32k_dead                  :    1;  /*Clear RTC WDT interrupt state*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t xtal32k_wdt_en                :    1;  /*xtal 32k watch dog enable*/
+            uint32_t xtal32k_wdt_clk_fo            :    1;  /*xtal 32k watch dog clock force on*/
+            uint32_t xtal32k_wdt_reset             :    1;  /*xtal 32k watch dog sw reset*/
+            uint32_t xtal32k_ext_clk_fo            :    1;  /*xtal 32k external xtal clock force on*/
+            uint32_t xtal32k_auto_backup           :    1;  /*xtal 32k switch to back up clock when xtal is dead*/
+            uint32_t xtal32k_auto_restart          :    1;  /*xtal 32k restart xtal when xtal is dead*/
+            uint32_t xtal32k_auto_return           :    1;  /*xtal 32k switch back xtal when xtal is restarted*/
+            uint32_t xtal32k_xpd_force             :    1;  /*Xtal 32k xpd control by sw or fsm*/
+            uint32_t enckinit_xtal_32k             :    1;  /*apply an internal clock to help xtal 32k to start*/
+            uint32_t dbuf_xtal_32k                 :    1;  /*0: single-end buffer 1: differential buffer*/
+            uint32_t dgm_xtal_32k                  :    3;  /*xtal_32k gm control*/
+            uint32_t dres_xtal_32k                 :    3;  /*DRES_XTAL_32K*/
+            uint32_t xpd_xtal_32k                  :    1;  /*XPD_XTAL_32K*/
+            uint32_t dac_xtal_32k                  :    3;  /*DAC_XTAL_32K*/
+            uint32_t wdt_state                     :    3;  /*state of 32k_wdt*/
+            uint32_t xtal32k_gpio_sel              :    1;  /*XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C*/
+            uint32_t reserved24                    :    6;
+            uint32_t xtl_ext_ctr_lv                :    1;  /*0: power down XTAL at high level; 1: power down XTAL at low level*/
+            uint32_t xtl_ext_ctr_en                :    1;
+        };
+        uint32_t val;
+    } ext_xtl_conf;
+    uint32_t xtal32k_clk_factor;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    union {
+        struct {
+            uint32_t xtal32k_return_wait           :    4;  /*cycles to wait to return noral xtal 32k*/
+            uint32_t xtal32k_restart_wait          :    16;  /*cycles to wait to repower on xtal 32k*/
+            uint32_t xtal32k_wdt_timeout           :    8;  /*If no clock detected for this amount of time,32k is regarded as dead*/
+            uint32_t xtal32k_stable_thres          :    4;  /*if restarted xtal32k period is smaller than this, it is regarded as stable*/
+        };
+        uint32_t val;
+    } xtal32k_conf;
+    union {
+        struct {
+            uint32_t swd_disable_efuse_force       :    1;  /*swd disable default choose efuse control bit*/
+            uint32_t wdt_flashboot_efuse_force     :    1;  /*lp_wdt flashboot en default choose efuse control bit*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } efuse_force;
+} lp_wdt_dev_t;
+
+extern lp_wdt_dev_t LP_WDT;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/mem_monitor_reg.h b/components/soc/esp32p4/include/soc/mem_monitor_reg.h
new file mode 100644
index 0000000000..3aec488661
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/mem_monitor_reg.h
@@ -0,0 +1,166 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_MEM_MONITOR_REG_H_
+#define _SOC_MEM_MONITOR_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define MEM_MONITOR_LOG_SETTING_REG          (DR_REG_MEM_MONITOR_BASE + 0x0)
+/* MEM_MONITOR_LOG_DMA_1_ENA : R/W ;bitpos:[31:24] ;default: 8'b0 ; */
+/*description: enable dma_1 log.*/
+#define MEM_MONITOR_LOG_DMA_1_ENA    0x000000FF
+#define MEM_MONITOR_LOG_DMA_1_ENA_M  ((MEM_MONITOR_LOG_DMA_1_ENA_V)<<(MEM_MONITOR_LOG_DMA_1_ENA_S))
+#define MEM_MONITOR_LOG_DMA_1_ENA_V  0xFF
+#define MEM_MONITOR_LOG_DMA_1_ENA_S  24
+/* MEM_MONITOR_LOG_DMA_0_ENA : R/W ;bitpos:[23:16] ;default: 8'b0 ; */
+/*description: enable dma_0 log.*/
+#define MEM_MONITOR_LOG_DMA_0_ENA    0x000000FF
+#define MEM_MONITOR_LOG_DMA_0_ENA_M  ((MEM_MONITOR_LOG_DMA_0_ENA_V)<<(MEM_MONITOR_LOG_DMA_0_ENA_S))
+#define MEM_MONITOR_LOG_DMA_0_ENA_V  0xFF
+#define MEM_MONITOR_LOG_DMA_0_ENA_S  16
+/* MEM_MONITOR_LOG_CORE_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: enable core log.*/
+#define MEM_MONITOR_LOG_CORE_ENA    0x000000FF
+#define MEM_MONITOR_LOG_CORE_ENA_M  ((MEM_MONITOR_LOG_CORE_ENA_V)<<(MEM_MONITOR_LOG_CORE_ENA_S))
+#define MEM_MONITOR_LOG_CORE_ENA_V  0xFF
+#define MEM_MONITOR_LOG_CORE_ENA_S  8
+/* MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END.*/
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(4))
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (BIT(4))
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x1
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  4
+/* MEM_MONITOR_LOG_MODE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYT
+E monitor.*/
+#define MEM_MONITOR_LOG_MODE    0x0000000F
+#define MEM_MONITOR_LOG_MODE_M  ((MEM_MONITOR_LOG_MODE_V)<<(MEM_MONITOR_LOG_MODE_S))
+#define MEM_MONITOR_LOG_MODE_V  0xF
+#define MEM_MONITOR_LOG_MODE_S  0
+
+#define MEM_MONITOR_LOG_SETTING1_REG          (DR_REG_MEM_MONITOR_BASE + 0x4)
+/* MEM_MONITOR_LOG_DMA_3_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: enable dma_3 log.*/
+#define MEM_MONITOR_LOG_DMA_3_ENA    0x000000FF
+#define MEM_MONITOR_LOG_DMA_3_ENA_M  ((MEM_MONITOR_LOG_DMA_3_ENA_V)<<(MEM_MONITOR_LOG_DMA_3_ENA_S))
+#define MEM_MONITOR_LOG_DMA_3_ENA_V  0xFF
+#define MEM_MONITOR_LOG_DMA_3_ENA_S  8
+/* MEM_MONITOR_LOG_DMA_2_ENA : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: enable dma_2 log.*/
+#define MEM_MONITOR_LOG_DMA_2_ENA    0x000000FF
+#define MEM_MONITOR_LOG_DMA_2_ENA_M  ((MEM_MONITOR_LOG_DMA_2_ENA_V)<<(MEM_MONITOR_LOG_DMA_2_ENA_S))
+#define MEM_MONITOR_LOG_DMA_2_ENA_V  0xFF
+#define MEM_MONITOR_LOG_DMA_2_ENA_S  0
+
+#define MEM_MONITOR_LOG_CHECK_DATA_REG          (DR_REG_MEM_MONITOR_BASE + 0x8)
+/* MEM_MONITOR_LOG_CHECK_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The special check data, when write this special data, it will trigger logging..*/
+#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFF
+#define MEM_MONITOR_LOG_CHECK_DATA_M  ((MEM_MONITOR_LOG_CHECK_DATA_V)<<(MEM_MONITOR_LOG_CHECK_DATA_S))
+#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFF
+#define MEM_MONITOR_LOG_CHECK_DATA_S  0
+
+#define MEM_MONITOR_LOG_DATA_MASK_REG          (DR_REG_MEM_MONITOR_BASE + 0xC)
+/* MEM_MONITOR_LOG_DATA_MASK : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BI
+T1 mask second byte, and so on..*/
+#define MEM_MONITOR_LOG_DATA_MASK    0x0000000F
+#define MEM_MONITOR_LOG_DATA_MASK_M  ((MEM_MONITOR_LOG_DATA_MASK_V)<<(MEM_MONITOR_LOG_DATA_MASK_S))
+#define MEM_MONITOR_LOG_DATA_MASK_V  0xF
+#define MEM_MONITOR_LOG_DATA_MASK_S  0
+
+#define MEM_MONITOR_LOG_MIN_REG          (DR_REG_MEM_MONITOR_BASE + 0x10)
+/* MEM_MONITOR_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: the min address of log range.*/
+#define MEM_MONITOR_LOG_MIN    0xFFFFFFFF
+#define MEM_MONITOR_LOG_MIN_M  ((MEM_MONITOR_LOG_MIN_V)<<(MEM_MONITOR_LOG_MIN_S))
+#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFF
+#define MEM_MONITOR_LOG_MIN_S  0
+
+#define MEM_MONITOR_LOG_MAX_REG          (DR_REG_MEM_MONITOR_BASE + 0x14)
+/* MEM_MONITOR_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: the max address of log range.*/
+#define MEM_MONITOR_LOG_MAX    0xFFFFFFFF
+#define MEM_MONITOR_LOG_MAX_M  ((MEM_MONITOR_LOG_MAX_V)<<(MEM_MONITOR_LOG_MAX_S))
+#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFF
+#define MEM_MONITOR_LOG_MAX_S  0
+
+#define MEM_MONITOR_LOG_MEM_START_REG          (DR_REG_MEM_MONITOR_BASE + 0x18)
+/* MEM_MONITOR_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: the start address of writing logging message.*/
+#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFF
+#define MEM_MONITOR_LOG_MEM_START_M  ((MEM_MONITOR_LOG_MEM_START_V)<<(MEM_MONITOR_LOG_MEM_START_S))
+#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFF
+#define MEM_MONITOR_LOG_MEM_START_S  0
+
+#define MEM_MONITOR_LOG_MEM_END_REG          (DR_REG_MEM_MONITOR_BASE + 0x1C)
+/* MEM_MONITOR_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: the end address of writing logging message.*/
+#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFF
+#define MEM_MONITOR_LOG_MEM_END_M  ((MEM_MONITOR_LOG_MEM_END_V)<<(MEM_MONITOR_LOG_MEM_END_S))
+#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFF
+#define MEM_MONITOR_LOG_MEM_END_S  0
+
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG          (DR_REG_MEM_MONITOR_BASE + 0x20)
+/* MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: means next writing address.*/
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFF
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  ((MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V)<<(MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S))
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFF
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
+
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG          (DR_REG_MEM_MONITOR_BASE + 0x24)
+/* MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_ME
+M_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START.*/
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (BIT(0))
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x1
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
+
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG          (DR_REG_MEM_MONITOR_BASE + 0x28)
+/* MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG.*/
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (BIT(1))
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x1
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
+/* MEM_MONITOR_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1 means memory write loop at least one time at the range of MEM_START and MEM_EN
+D.*/
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (BIT(0))
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x1
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
+
+#define MEM_MONITOR_CLOCK_GATE_REG          (DR_REG_MEM_MONITOR_BASE + 0x2C)
+/* MEM_MONITOR_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to force on the clk of mem_monitor register.*/
+#define MEM_MONITOR_CLK_EN    (BIT(0))
+#define MEM_MONITOR_CLK_EN_M  (BIT(0))
+#define MEM_MONITOR_CLK_EN_V  0x1
+#define MEM_MONITOR_CLK_EN_S  0
+
+#define MEM_MONITOR_DATE_REG          (DR_REG_MEM_MONITOR_BASE + 0x3FC)
+/* MEM_MONITOR_DATE : R/W ;bitpos:[27:0] ;default: 28'h2302220 ; */
+/*description: version register.*/
+#define MEM_MONITOR_DATE    0x0FFFFFFF
+#define MEM_MONITOR_DATE_M  ((MEM_MONITOR_DATE_V)<<(MEM_MONITOR_DATE_S))
+#define MEM_MONITOR_DATE_V  0xFFFFFFF
+#define MEM_MONITOR_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_MEM_MONITOR_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/mem_monitor_struct.h b/components/soc/esp32p4/include/soc/mem_monitor_struct.h
new file mode 100644
index 0000000000..463f58aa4e
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/mem_monitor_struct.h
@@ -0,0 +1,328 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_MEM_MONITOR_STRUCT_H_
+#define _SOC_MEM_MONITOR_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reg_log_mode                  :    4;  /*Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE monitor */
+            uint32_t reg_log_mem_loop_enable       :    1;  /*Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END*/
+            uint32_t reserved5                     :    3;  /*reseved*/
+            uint32_t reg_log_core_ena              :    8;  /*enable core log*/
+            uint32_t reg_log_dma_0_ena             :    8;  /*enable dma_0 log*/
+            uint32_t reg_log_dma_1_ena             :    8;  /*enable dma_1 log*/
+        };
+        uint32_t val;
+    } log_setting;
+    union {
+        struct {
+            uint32_t reg_log_dma_2_ena             :    8;  /*enable dma_2 log*/
+            uint32_t reg_log_dma_3_ena             :    8;  /*enable dma_3 log*/
+            uint32_t reserved16                    :    16;  /*reseved*/
+        };
+        uint32_t val;
+    } log_setting1;
+    uint32_t log_check_data;
+    union {
+        struct {
+            uint32_t reg_log_data_mask             :    4;  /*byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on.*/
+            uint32_t reserved4                     :    28;  /*reseved*/
+        };
+        uint32_t val;
+    } log_data_mask;
+    uint32_t log_min;
+    uint32_t log_max;
+    uint32_t log_mem_start;
+    uint32_t log_mem_end;
+    uint32_t log_mem_current_addr;
+    union {
+        struct {
+            uint32_t reg_log_mem_addr_update       :    1;  /*Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START */
+            uint32_t reserved1                     :    31;  /*reseved*/
+        };
+        uint32_t val;
+    } log_mem_addr_update;
+    union {
+        struct {
+            uint32_t reg_log_mem_full_flag         :    1;  /*1 means memory write loop at least one time at the range of MEM_START and MEM_END*/
+            uint32_t reg_clr_log_mem_full_flag     :    1;  /*Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG*/
+            uint32_t reserved2                     :    30;  /*reseved*/
+        };
+        uint32_t val;
+    } log_mem_full_flag;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*Set 1 to force on the clk of mem_monitor register */
+            uint32_t reserved1                     :    31;  /*reseved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t reg_mem_monitor_date          :    28;  /*version register*/
+            uint32_t reserved28                    :    4;  /*reseved*/
+        };
+        uint32_t val;
+    } date;
+} mem_monitor_dev_t;
+extern mem_monitor_dev_t MEM_MONITOR;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_MEM_MONITOR_STRUCT_H_ */
diff --git a/components/soc/esp32p4/include/soc/memprot_defs.h b/components/soc/esp32p4/include/soc/memprot_defs.h
new file mode 100644
index 0000000000..9723f61eb5
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/memprot_defs.h
@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "esp32p4/rom/cache.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef union {
+    struct {
+        uint32_t cat0       : 2;
+        uint32_t cat1       : 2;
+        uint32_t cat2       : 2;
+        uint32_t res0       : 8;
+        uint32_t splitaddr  : 8;
+        uint32_t res1       : 10;
+    };
+    uint32_t val;
+} constrain_reg_fields_t;
+
+#ifndef I_D_SRAM_SEGMENT_SIZE
+#define I_D_SRAM_SEGMENT_SIZE       0x20000
+#endif
+
+#define I_D_SPLIT_LINE_SHIFT        0x9
+#define I_D_FAULT_ADDR_SHIFT        0x2
+
+#define DRAM_SRAM_START             0x3FC7C000
+
+//IRAM0
+
+//16kB (ICACHE)
+#define IRAM0_SRAM_LEVEL_0_LOW      SOC_IRAM_LOW //0x40370000
+#define IRAM0_SRAM_LEVEL_0_HIGH     (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
+
+//128kB (LEVEL 1)
+#define IRAM0_SRAM_LEVEL_1_LOW      (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
+#define IRAM0_SRAM_LEVEL_1_HIGH     (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
+
+//128kB (LEVEL 2)
+#define IRAM0_SRAM_LEVEL_2_LOW      (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
+#define IRAM0_SRAM_LEVEL_2_HIGH     (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
+
+//128kB (LEVEL 3)
+#define IRAM0_SRAM_LEVEL_3_LOW      (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
+#define IRAM0_SRAM_LEVEL_3_HIGH     (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
+
+//permission bits
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R  0x1
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W  0x2
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F  0x4
+
+//DRAM0
+
+//16kB ICACHE not available from DRAM0
+
+//128kB (LEVEL 1)
+#define DRAM0_SRAM_LEVEL_1_LOW      SOC_DRAM_LOW //0x3FC80000
+#define DRAM0_SRAM_LEVEL_1_HIGH     (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
+
+//128kB (LEVEL 2)
+#define DRAM0_SRAM_LEVEL_2_LOW      (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
+#define DRAM0_SRAM_LEVEL_2_HIGH     (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
+
+//128kB (LEVEL 3)
+#define DRAM0_SRAM_LEVEL_3_LOW      (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
+#define DRAM0_SRAM_LEVEL_3_HIGH     (DRAM0_SRAM_LEVEL_3_LOW  + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R  0x1
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W  0x2
+
+//RTC FAST
+
+//permission bits
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R  0x2
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F  0x4
+
+#define AREA_LOW                                                0
+#define AREA_HIGH                                               1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/mmu.h b/components/soc/esp32p4/include/soc/mmu.h
new file mode 100644
index 0000000000..f0eb7f00f4
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/mmu.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/ext_mem_defs.h"
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Defined for flash mmap */
+#define SOC_MMU_REGIONS_COUNT                   1
+#define SOC_MMU_PAGES_PER_REGION                1024
+#define SOC_MMU_IROM0_PAGES_START               (CACHE_IROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
+#define SOC_MMU_ADDR_MASK                       (MMU_VALID - 1)
+#define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
+#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE       FLASH_MMU_TABLE
+#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
+#define SOC_MMU_VADDR0_START_ADDR               (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
+#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/otp_debug_reg.h b/components/soc/esp32p4/include/soc/otp_debug_reg.h
new file mode 100644
index 0000000000..521f116aa0
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/otp_debug_reg.h
@@ -0,0 +1,1600 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** OTP_DEBUG_WR_DIS_REG register
+ *  Otp debuger block0 data register1.
+ */
+#define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0)
+/** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 write disable data.
+ */
+#define OTP_DEBUG_BLOCK0_WR_DIS    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_WR_DIS_M  (OTP_DEBUG_BLOCK0_WR_DIS_V << OTP_DEBUG_BLOCK0_WR_DIS_S)
+#define OTP_DEBUG_BLOCK0_WR_DIS_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_WR_DIS_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP1_W1_REG register
+ *  Otp debuger block0 data register2.
+ */
+#define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4)
+/** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word1 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W1_M  (OTP_DEBUG_BLOCK0_BACKUP1_W1_V << OTP_DEBUG_BLOCK0_BACKUP1_W1_S)
+#define OTP_DEBUG_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W1_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP1_W2_REG register
+ *  Otp debuger block0 data register3.
+ */
+#define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8)
+/** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word2 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W2_M  (OTP_DEBUG_BLOCK0_BACKUP1_W2_V << OTP_DEBUG_BLOCK0_BACKUP1_W2_S)
+#define OTP_DEBUG_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W2_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP1_W3_REG register
+ *  Otp debuger block0 data register4.
+ */
+#define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc)
+/** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word3 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W3_M  (OTP_DEBUG_BLOCK0_BACKUP1_W3_V << OTP_DEBUG_BLOCK0_BACKUP1_W3_S)
+#define OTP_DEBUG_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W3_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP1_W4_REG register
+ *  Otp debuger block0 data register5.
+ */
+#define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10)
+/** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word4 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W4_M  (OTP_DEBUG_BLOCK0_BACKUP1_W4_V << OTP_DEBUG_BLOCK0_BACKUP1_W4_S)
+#define OTP_DEBUG_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W4_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP1_W5_REG register
+ *  Otp debuger block0 data register6.
+ */
+#define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14)
+/** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word5 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W5_M  (OTP_DEBUG_BLOCK0_BACKUP1_W5_V << OTP_DEBUG_BLOCK0_BACKUP1_W5_S)
+#define OTP_DEBUG_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP1_W5_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP2_W1_REG register
+ *  Otp debuger block0 data register7.
+ */
+#define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18)
+/** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word1 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W1_M  (OTP_DEBUG_BLOCK0_BACKUP2_W1_V << OTP_DEBUG_BLOCK0_BACKUP2_W1_S)
+#define OTP_DEBUG_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W1_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP2_W2_REG register
+ *  Otp debuger block0 data register8.
+ */
+#define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c)
+/** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word2 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W2_M  (OTP_DEBUG_BLOCK0_BACKUP2_W2_V << OTP_DEBUG_BLOCK0_BACKUP2_W2_S)
+#define OTP_DEBUG_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W2_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP2_W3_REG register
+ *  Otp debuger block0 data register9.
+ */
+#define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20)
+/** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word3 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W3_M  (OTP_DEBUG_BLOCK0_BACKUP2_W3_V << OTP_DEBUG_BLOCK0_BACKUP2_W3_S)
+#define OTP_DEBUG_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W3_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP2_W4_REG register
+ *  Otp debuger block0 data register10.
+ */
+#define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24)
+/** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word4 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W4_M  (OTP_DEBUG_BLOCK0_BACKUP2_W4_V << OTP_DEBUG_BLOCK0_BACKUP2_W4_S)
+#define OTP_DEBUG_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W4_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP2_W5_REG register
+ *  Otp debuger block0 data register11.
+ */
+#define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28)
+/** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word5 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W5_M  (OTP_DEBUG_BLOCK0_BACKUP2_W5_V << OTP_DEBUG_BLOCK0_BACKUP2_W5_S)
+#define OTP_DEBUG_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP2_W5_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP3_W1_REG register
+ *  Otp debuger block0 data register12.
+ */
+#define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c)
+/** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word1 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W1_M  (OTP_DEBUG_BLOCK0_BACKUP3_W1_V << OTP_DEBUG_BLOCK0_BACKUP3_W1_S)
+#define OTP_DEBUG_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W1_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP3_W2_REG register
+ *  Otp debuger block0 data register13.
+ */
+#define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30)
+/** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word2 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W2_M  (OTP_DEBUG_BLOCK0_BACKUP3_W2_V << OTP_DEBUG_BLOCK0_BACKUP3_W2_S)
+#define OTP_DEBUG_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W2_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP3_W3_REG register
+ *  Otp debuger block0 data register14.
+ */
+#define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34)
+/** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word3 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W3_M  (OTP_DEBUG_BLOCK0_BACKUP3_W3_V << OTP_DEBUG_BLOCK0_BACKUP3_W3_S)
+#define OTP_DEBUG_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W3_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP3_W4_REG register
+ *  Otp debuger block0 data register15.
+ */
+#define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38)
+/** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word4 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W4_M  (OTP_DEBUG_BLOCK0_BACKUP3_W4_V << OTP_DEBUG_BLOCK0_BACKUP3_W4_S)
+#define OTP_DEBUG_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W4_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP3_W5_REG register
+ *  Otp debuger block0 data register16.
+ */
+#define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c)
+/** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word5 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W5_M  (OTP_DEBUG_BLOCK0_BACKUP3_W5_V << OTP_DEBUG_BLOCK0_BACKUP3_W5_S)
+#define OTP_DEBUG_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP3_W5_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP4_W1_REG register
+ *  Otp debuger block0 data register17.
+ */
+#define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40)
+/** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word1 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W1_M  (OTP_DEBUG_BLOCK0_BACKUP4_W1_V << OTP_DEBUG_BLOCK0_BACKUP4_W1_S)
+#define OTP_DEBUG_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W1_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP4_W2_REG register
+ *  Otp debuger block0 data register18.
+ */
+#define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44)
+/** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word2 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W2_M  (OTP_DEBUG_BLOCK0_BACKUP4_W2_V << OTP_DEBUG_BLOCK0_BACKUP4_W2_S)
+#define OTP_DEBUG_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W2_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP4_W3_REG register
+ *  Otp debuger block0 data register19.
+ */
+#define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48)
+/** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word3 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W3_M  (OTP_DEBUG_BLOCK0_BACKUP4_W3_V << OTP_DEBUG_BLOCK0_BACKUP4_W3_S)
+#define OTP_DEBUG_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W3_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP4_W4_REG register
+ *  Otp debuger block0 data register20.
+ */
+#define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c)
+/** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word4 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W4_M  (OTP_DEBUG_BLOCK0_BACKUP4_W4_V << OTP_DEBUG_BLOCK0_BACKUP4_W4_S)
+#define OTP_DEBUG_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W4_S  0
+
+/** OTP_DEBUG_BLK0_BACKUP4_W5_REG register
+ *  Otp debuger block0 data register21.
+ */
+#define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50)
+/** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word5 data.
+ */
+#define OTP_DEBUG_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W5_M  (OTP_DEBUG_BLOCK0_BACKUP4_W5_V << OTP_DEBUG_BLOCK0_BACKUP4_W5_S)
+#define OTP_DEBUG_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK0_BACKUP4_W5_S  0
+
+/** OTP_DEBUG_BLK1_W1_REG register
+ *  Otp debuger block1 data register1.
+ */
+#define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54)
+/** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word1 data.
+ */
+#define OTP_DEBUG_BLOCK1_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W1_M  (OTP_DEBUG_BLOCK1_W1_V << OTP_DEBUG_BLOCK1_W1_S)
+#define OTP_DEBUG_BLOCK1_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W1_S  0
+
+/** OTP_DEBUG_BLK1_W2_REG register
+ *  Otp debuger block1 data register2.
+ */
+#define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58)
+/** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word2 data.
+ */
+#define OTP_DEBUG_BLOCK1_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W2_M  (OTP_DEBUG_BLOCK1_W2_V << OTP_DEBUG_BLOCK1_W2_S)
+#define OTP_DEBUG_BLOCK1_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W2_S  0
+
+/** OTP_DEBUG_BLK1_W3_REG register
+ *  Otp debuger block1 data register3.
+ */
+#define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c)
+/** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word3 data.
+ */
+#define OTP_DEBUG_BLOCK1_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W3_M  (OTP_DEBUG_BLOCK1_W3_V << OTP_DEBUG_BLOCK1_W3_S)
+#define OTP_DEBUG_BLOCK1_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W3_S  0
+
+/** OTP_DEBUG_BLK1_W4_REG register
+ *  Otp debuger block1 data register4.
+ */
+#define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60)
+/** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word4 data.
+ */
+#define OTP_DEBUG_BLOCK1_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W4_M  (OTP_DEBUG_BLOCK1_W4_V << OTP_DEBUG_BLOCK1_W4_S)
+#define OTP_DEBUG_BLOCK1_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W4_S  0
+
+/** OTP_DEBUG_BLK1_W5_REG register
+ *  Otp debuger block1 data register5.
+ */
+#define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64)
+/** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word5 data.
+ */
+#define OTP_DEBUG_BLOCK1_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W5_M  (OTP_DEBUG_BLOCK1_W5_V << OTP_DEBUG_BLOCK1_W5_S)
+#define OTP_DEBUG_BLOCK1_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W5_S  0
+
+/** OTP_DEBUG_BLK1_W6_REG register
+ *  Otp debuger block1 data register6.
+ */
+#define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68)
+/** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word6 data.
+ */
+#define OTP_DEBUG_BLOCK1_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W6_M  (OTP_DEBUG_BLOCK1_W6_V << OTP_DEBUG_BLOCK1_W6_S)
+#define OTP_DEBUG_BLOCK1_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W6_S  0
+
+/** OTP_DEBUG_BLK1_W7_REG register
+ *  Otp debuger block1 data register7.
+ */
+#define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c)
+/** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word7 data.
+ */
+#define OTP_DEBUG_BLOCK1_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W7_M  (OTP_DEBUG_BLOCK1_W7_V << OTP_DEBUG_BLOCK1_W7_S)
+#define OTP_DEBUG_BLOCK1_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W7_S  0
+
+/** OTP_DEBUG_BLK1_W8_REG register
+ *  Otp debuger block1 data register8.
+ */
+#define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70)
+/** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word8 data.
+ */
+#define OTP_DEBUG_BLOCK1_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W8_M  (OTP_DEBUG_BLOCK1_W8_V << OTP_DEBUG_BLOCK1_W8_S)
+#define OTP_DEBUG_BLOCK1_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W8_S  0
+
+/** OTP_DEBUG_BLK1_W9_REG register
+ *  Otp debuger block1 data register9.
+ */
+#define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74)
+/** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word9 data.
+ */
+#define OTP_DEBUG_BLOCK1_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W9_M  (OTP_DEBUG_BLOCK1_W9_V << OTP_DEBUG_BLOCK1_W9_S)
+#define OTP_DEBUG_BLOCK1_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK1_W9_S  0
+
+/** OTP_DEBUG_BLK2_W1_REG register
+ *  Otp debuger block2 data register1.
+ */
+#define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78)
+/** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word1 data.
+ */
+#define OTP_DEBUG_BLOCK2_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W1_M  (OTP_DEBUG_BLOCK2_W1_V << OTP_DEBUG_BLOCK2_W1_S)
+#define OTP_DEBUG_BLOCK2_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W1_S  0
+
+/** OTP_DEBUG_BLK2_W2_REG register
+ *  Otp debuger block2 data register2.
+ */
+#define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c)
+/** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word2 data.
+ */
+#define OTP_DEBUG_BLOCK2_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W2_M  (OTP_DEBUG_BLOCK2_W2_V << OTP_DEBUG_BLOCK2_W2_S)
+#define OTP_DEBUG_BLOCK2_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W2_S  0
+
+/** OTP_DEBUG_BLK2_W3_REG register
+ *  Otp debuger block2 data register3.
+ */
+#define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80)
+/** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word3 data.
+ */
+#define OTP_DEBUG_BLOCK2_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W3_M  (OTP_DEBUG_BLOCK2_W3_V << OTP_DEBUG_BLOCK2_W3_S)
+#define OTP_DEBUG_BLOCK2_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W3_S  0
+
+/** OTP_DEBUG_BLK2_W4_REG register
+ *  Otp debuger block2 data register4.
+ */
+#define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84)
+/** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word4 data.
+ */
+#define OTP_DEBUG_BLOCK2_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W4_M  (OTP_DEBUG_BLOCK2_W4_V << OTP_DEBUG_BLOCK2_W4_S)
+#define OTP_DEBUG_BLOCK2_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W4_S  0
+
+/** OTP_DEBUG_BLK2_W5_REG register
+ *  Otp debuger block2 data register5.
+ */
+#define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88)
+/** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word5 data.
+ */
+#define OTP_DEBUG_BLOCK2_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W5_M  (OTP_DEBUG_BLOCK2_W5_V << OTP_DEBUG_BLOCK2_W5_S)
+#define OTP_DEBUG_BLOCK2_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W5_S  0
+
+/** OTP_DEBUG_BLK2_W6_REG register
+ *  Otp debuger block2 data register6.
+ */
+#define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c)
+/** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word6 data.
+ */
+#define OTP_DEBUG_BLOCK2_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W6_M  (OTP_DEBUG_BLOCK2_W6_V << OTP_DEBUG_BLOCK2_W6_S)
+#define OTP_DEBUG_BLOCK2_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W6_S  0
+
+/** OTP_DEBUG_BLK2_W7_REG register
+ *  Otp debuger block2 data register7.
+ */
+#define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90)
+/** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word7 data.
+ */
+#define OTP_DEBUG_BLOCK2_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W7_M  (OTP_DEBUG_BLOCK2_W7_V << OTP_DEBUG_BLOCK2_W7_S)
+#define OTP_DEBUG_BLOCK2_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W7_S  0
+
+/** OTP_DEBUG_BLK2_W8_REG register
+ *  Otp debuger block2 data register8.
+ */
+#define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94)
+/** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word8 data.
+ */
+#define OTP_DEBUG_BLOCK2_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W8_M  (OTP_DEBUG_BLOCK2_W8_V << OTP_DEBUG_BLOCK2_W8_S)
+#define OTP_DEBUG_BLOCK2_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W8_S  0
+
+/** OTP_DEBUG_BLK2_W9_REG register
+ *  Otp debuger block2 data register9.
+ */
+#define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98)
+/** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word9 data.
+ */
+#define OTP_DEBUG_BLOCK2_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W9_M  (OTP_DEBUG_BLOCK2_W9_V << OTP_DEBUG_BLOCK2_W9_S)
+#define OTP_DEBUG_BLOCK2_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W9_S  0
+
+/** OTP_DEBUG_BLK2_W10_REG register
+ *  Otp debuger block2 data register10.
+ */
+#define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c)
+/** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word10 data.
+ */
+#define OTP_DEBUG_BLOCK2_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W10_M  (OTP_DEBUG_BLOCK2_W10_V << OTP_DEBUG_BLOCK2_W10_S)
+#define OTP_DEBUG_BLOCK2_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W10_S  0
+
+/** OTP_DEBUG_BLK2_W11_REG register
+ *  Otp debuger block2 data register11.
+ */
+#define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0)
+/** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word11 data.
+ */
+#define OTP_DEBUG_BLOCK2_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W11_M  (OTP_DEBUG_BLOCK2_W11_V << OTP_DEBUG_BLOCK2_W11_S)
+#define OTP_DEBUG_BLOCK2_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK2_W11_S  0
+
+/** OTP_DEBUG_BLK3_W1_REG register
+ *  Otp debuger block3 data register1.
+ */
+#define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4)
+/** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word1 data.
+ */
+#define OTP_DEBUG_BLOCK3_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W1_M  (OTP_DEBUG_BLOCK3_W1_V << OTP_DEBUG_BLOCK3_W1_S)
+#define OTP_DEBUG_BLOCK3_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W1_S  0
+
+/** OTP_DEBUG_BLK3_W2_REG register
+ *  Otp debuger block3 data register2.
+ */
+#define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8)
+/** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word2 data.
+ */
+#define OTP_DEBUG_BLOCK3_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W2_M  (OTP_DEBUG_BLOCK3_W2_V << OTP_DEBUG_BLOCK3_W2_S)
+#define OTP_DEBUG_BLOCK3_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W2_S  0
+
+/** OTP_DEBUG_BLK3_W3_REG register
+ *  Otp debuger block3 data register3.
+ */
+#define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac)
+/** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word3 data.
+ */
+#define OTP_DEBUG_BLOCK3_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W3_M  (OTP_DEBUG_BLOCK3_W3_V << OTP_DEBUG_BLOCK3_W3_S)
+#define OTP_DEBUG_BLOCK3_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W3_S  0
+
+/** OTP_DEBUG_BLK3_W4_REG register
+ *  Otp debuger block3 data register4.
+ */
+#define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0)
+/** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word4 data.
+ */
+#define OTP_DEBUG_BLOCK3_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W4_M  (OTP_DEBUG_BLOCK3_W4_V << OTP_DEBUG_BLOCK3_W4_S)
+#define OTP_DEBUG_BLOCK3_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W4_S  0
+
+/** OTP_DEBUG_BLK3_W5_REG register
+ *  Otp debuger block3 data register5.
+ */
+#define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4)
+/** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word5 data.
+ */
+#define OTP_DEBUG_BLOCK3_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W5_M  (OTP_DEBUG_BLOCK3_W5_V << OTP_DEBUG_BLOCK3_W5_S)
+#define OTP_DEBUG_BLOCK3_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W5_S  0
+
+/** OTP_DEBUG_BLK3_W6_REG register
+ *  Otp debuger block3 data register6.
+ */
+#define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8)
+/** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word6 data.
+ */
+#define OTP_DEBUG_BLOCK3_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W6_M  (OTP_DEBUG_BLOCK3_W6_V << OTP_DEBUG_BLOCK3_W6_S)
+#define OTP_DEBUG_BLOCK3_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W6_S  0
+
+/** OTP_DEBUG_BLK3_W7_REG register
+ *  Otp debuger block3 data register7.
+ */
+#define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc)
+/** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word7 data.
+ */
+#define OTP_DEBUG_BLOCK3_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W7_M  (OTP_DEBUG_BLOCK3_W7_V << OTP_DEBUG_BLOCK3_W7_S)
+#define OTP_DEBUG_BLOCK3_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W7_S  0
+
+/** OTP_DEBUG_BLK3_W8_REG register
+ *  Otp debuger block3 data register8.
+ */
+#define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0)
+/** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word8 data.
+ */
+#define OTP_DEBUG_BLOCK3_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W8_M  (OTP_DEBUG_BLOCK3_W8_V << OTP_DEBUG_BLOCK3_W8_S)
+#define OTP_DEBUG_BLOCK3_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W8_S  0
+
+/** OTP_DEBUG_BLK3_W9_REG register
+ *  Otp debuger block3 data register9.
+ */
+#define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4)
+/** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word9 data.
+ */
+#define OTP_DEBUG_BLOCK3_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W9_M  (OTP_DEBUG_BLOCK3_W9_V << OTP_DEBUG_BLOCK3_W9_S)
+#define OTP_DEBUG_BLOCK3_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W9_S  0
+
+/** OTP_DEBUG_BLK3_W10_REG register
+ *  Otp debuger block3 data register10.
+ */
+#define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8)
+/** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word10 data.
+ */
+#define OTP_DEBUG_BLOCK3_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W10_M  (OTP_DEBUG_BLOCK3_W10_V << OTP_DEBUG_BLOCK3_W10_S)
+#define OTP_DEBUG_BLOCK3_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W10_S  0
+
+/** OTP_DEBUG_BLK3_W11_REG register
+ *  Otp debuger block3 data register11.
+ */
+#define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc)
+/** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word11 data.
+ */
+#define OTP_DEBUG_BLOCK3_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W11_M  (OTP_DEBUG_BLOCK3_W11_V << OTP_DEBUG_BLOCK3_W11_S)
+#define OTP_DEBUG_BLOCK3_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK3_W11_S  0
+
+/** OTP_DEBUG_BLK4_W1_REG register
+ *  Otp debuger block4 data register1.
+ */
+#define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0)
+/** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word1 data.
+ */
+#define OTP_DEBUG_BLOCK4_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W1_M  (OTP_DEBUG_BLOCK4_W1_V << OTP_DEBUG_BLOCK4_W1_S)
+#define OTP_DEBUG_BLOCK4_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W1_S  0
+
+/** OTP_DEBUG_BLK4_W2_REG register
+ *  Otp debuger block4 data register2.
+ */
+#define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4)
+/** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word2 data.
+ */
+#define OTP_DEBUG_BLOCK4_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W2_M  (OTP_DEBUG_BLOCK4_W2_V << OTP_DEBUG_BLOCK4_W2_S)
+#define OTP_DEBUG_BLOCK4_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W2_S  0
+
+/** OTP_DEBUG_BLK4_W3_REG register
+ *  Otp debuger block4 data register3.
+ */
+#define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8)
+/** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word3 data.
+ */
+#define OTP_DEBUG_BLOCK4_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W3_M  (OTP_DEBUG_BLOCK4_W3_V << OTP_DEBUG_BLOCK4_W3_S)
+#define OTP_DEBUG_BLOCK4_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W3_S  0
+
+/** OTP_DEBUG_BLK4_W4_REG register
+ *  Otp debuger block4 data register4.
+ */
+#define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc)
+/** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word4 data.
+ */
+#define OTP_DEBUG_BLOCK4_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W4_M  (OTP_DEBUG_BLOCK4_W4_V << OTP_DEBUG_BLOCK4_W4_S)
+#define OTP_DEBUG_BLOCK4_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W4_S  0
+
+/** OTP_DEBUG_BLK4_W5_REG register
+ *  Otp debuger block4 data register5.
+ */
+#define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0)
+/** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word5 data.
+ */
+#define OTP_DEBUG_BLOCK4_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W5_M  (OTP_DEBUG_BLOCK4_W5_V << OTP_DEBUG_BLOCK4_W5_S)
+#define OTP_DEBUG_BLOCK4_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W5_S  0
+
+/** OTP_DEBUG_BLK4_W6_REG register
+ *  Otp debuger block4 data register6.
+ */
+#define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4)
+/** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word6 data.
+ */
+#define OTP_DEBUG_BLOCK4_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W6_M  (OTP_DEBUG_BLOCK4_W6_V << OTP_DEBUG_BLOCK4_W6_S)
+#define OTP_DEBUG_BLOCK4_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W6_S  0
+
+/** OTP_DEBUG_BLK4_W7_REG register
+ *  Otp debuger block4 data register7.
+ */
+#define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8)
+/** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word7 data.
+ */
+#define OTP_DEBUG_BLOCK4_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W7_M  (OTP_DEBUG_BLOCK4_W7_V << OTP_DEBUG_BLOCK4_W7_S)
+#define OTP_DEBUG_BLOCK4_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W7_S  0
+
+/** OTP_DEBUG_BLK4_W8_REG register
+ *  Otp debuger block4 data register8.
+ */
+#define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec)
+/** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word8 data.
+ */
+#define OTP_DEBUG_BLOCK4_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W8_M  (OTP_DEBUG_BLOCK4_W8_V << OTP_DEBUG_BLOCK4_W8_S)
+#define OTP_DEBUG_BLOCK4_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W8_S  0
+
+/** OTP_DEBUG_BLK4_W9_REG register
+ *  Otp debuger block4 data register9.
+ */
+#define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0)
+/** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word9 data.
+ */
+#define OTP_DEBUG_BLOCK4_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W9_M  (OTP_DEBUG_BLOCK4_W9_V << OTP_DEBUG_BLOCK4_W9_S)
+#define OTP_DEBUG_BLOCK4_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W9_S  0
+
+/** OTP_DEBUG_BLK4_W10_REG register
+ *  Otp debuger block4 data registe10.
+ */
+#define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4)
+/** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word10 data.
+ */
+#define OTP_DEBUG_BLOCK4_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W10_M  (OTP_DEBUG_BLOCK4_W10_V << OTP_DEBUG_BLOCK4_W10_S)
+#define OTP_DEBUG_BLOCK4_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W10_S  0
+
+/** OTP_DEBUG_BLK4_W11_REG register
+ *  Otp debuger block4 data register11.
+ */
+#define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8)
+/** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word11 data.
+ */
+#define OTP_DEBUG_BLOCK4_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W11_M  (OTP_DEBUG_BLOCK4_W11_V << OTP_DEBUG_BLOCK4_W11_S)
+#define OTP_DEBUG_BLOCK4_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK4_W11_S  0
+
+/** OTP_DEBUG_BLK5_W1_REG register
+ *  Otp debuger block5 data register1.
+ */
+#define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc)
+/** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word1 data.
+ */
+#define OTP_DEBUG_BLOCK5_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W1_M  (OTP_DEBUG_BLOCK5_W1_V << OTP_DEBUG_BLOCK5_W1_S)
+#define OTP_DEBUG_BLOCK5_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W1_S  0
+
+/** OTP_DEBUG_BLK5_W2_REG register
+ *  Otp debuger block5 data register2.
+ */
+#define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100)
+/** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word2 data.
+ */
+#define OTP_DEBUG_BLOCK5_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W2_M  (OTP_DEBUG_BLOCK5_W2_V << OTP_DEBUG_BLOCK5_W2_S)
+#define OTP_DEBUG_BLOCK5_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W2_S  0
+
+/** OTP_DEBUG_BLK5_W3_REG register
+ *  Otp debuger block5 data register3.
+ */
+#define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104)
+/** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word3 data.
+ */
+#define OTP_DEBUG_BLOCK5_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W3_M  (OTP_DEBUG_BLOCK5_W3_V << OTP_DEBUG_BLOCK5_W3_S)
+#define OTP_DEBUG_BLOCK5_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W3_S  0
+
+/** OTP_DEBUG_BLK5_W4_REG register
+ *  Otp debuger block5 data register4.
+ */
+#define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108)
+/** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word4 data.
+ */
+#define OTP_DEBUG_BLOCK5_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W4_M  (OTP_DEBUG_BLOCK5_W4_V << OTP_DEBUG_BLOCK5_W4_S)
+#define OTP_DEBUG_BLOCK5_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W4_S  0
+
+/** OTP_DEBUG_BLK5_W5_REG register
+ *  Otp debuger block5 data register5.
+ */
+#define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c)
+/** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word5 data.
+ */
+#define OTP_DEBUG_BLOCK5_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W5_M  (OTP_DEBUG_BLOCK5_W5_V << OTP_DEBUG_BLOCK5_W5_S)
+#define OTP_DEBUG_BLOCK5_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W5_S  0
+
+/** OTP_DEBUG_BLK5_W6_REG register
+ *  Otp debuger block5 data register6.
+ */
+#define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110)
+/** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word6 data.
+ */
+#define OTP_DEBUG_BLOCK5_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W6_M  (OTP_DEBUG_BLOCK5_W6_V << OTP_DEBUG_BLOCK5_W6_S)
+#define OTP_DEBUG_BLOCK5_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W6_S  0
+
+/** OTP_DEBUG_BLK5_W7_REG register
+ *  Otp debuger block5 data register7.
+ */
+#define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114)
+/** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word7 data.
+ */
+#define OTP_DEBUG_BLOCK5_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W7_M  (OTP_DEBUG_BLOCK5_W7_V << OTP_DEBUG_BLOCK5_W7_S)
+#define OTP_DEBUG_BLOCK5_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W7_S  0
+
+/** OTP_DEBUG_BLK5_W8_REG register
+ *  Otp debuger block5 data register8.
+ */
+#define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118)
+/** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word8 data.
+ */
+#define OTP_DEBUG_BLOCK5_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W8_M  (OTP_DEBUG_BLOCK5_W8_V << OTP_DEBUG_BLOCK5_W8_S)
+#define OTP_DEBUG_BLOCK5_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W8_S  0
+
+/** OTP_DEBUG_BLK5_W9_REG register
+ *  Otp debuger block5 data register9.
+ */
+#define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c)
+/** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word9 data.
+ */
+#define OTP_DEBUG_BLOCK5_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W9_M  (OTP_DEBUG_BLOCK5_W9_V << OTP_DEBUG_BLOCK5_W9_S)
+#define OTP_DEBUG_BLOCK5_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W9_S  0
+
+/** OTP_DEBUG_BLK5_W10_REG register
+ *  Otp debuger block5 data register10.
+ */
+#define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120)
+/** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word10 data.
+ */
+#define OTP_DEBUG_BLOCK5_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W10_M  (OTP_DEBUG_BLOCK5_W10_V << OTP_DEBUG_BLOCK5_W10_S)
+#define OTP_DEBUG_BLOCK5_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W10_S  0
+
+/** OTP_DEBUG_BLK5_W11_REG register
+ *  Otp debuger block5 data register11.
+ */
+#define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124)
+/** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word11 data.
+ */
+#define OTP_DEBUG_BLOCK5_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W11_M  (OTP_DEBUG_BLOCK5_W11_V << OTP_DEBUG_BLOCK5_W11_S)
+#define OTP_DEBUG_BLOCK5_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK5_W11_S  0
+
+/** OTP_DEBUG_BLK6_W1_REG register
+ *  Otp debuger block6 data register1.
+ */
+#define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128)
+/** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word1 data.
+ */
+#define OTP_DEBUG_BLOCK6_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W1_M  (OTP_DEBUG_BLOCK6_W1_V << OTP_DEBUG_BLOCK6_W1_S)
+#define OTP_DEBUG_BLOCK6_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W1_S  0
+
+/** OTP_DEBUG_BLK6_W2_REG register
+ *  Otp debuger block6 data register2.
+ */
+#define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c)
+/** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word2 data.
+ */
+#define OTP_DEBUG_BLOCK6_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W2_M  (OTP_DEBUG_BLOCK6_W2_V << OTP_DEBUG_BLOCK6_W2_S)
+#define OTP_DEBUG_BLOCK6_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W2_S  0
+
+/** OTP_DEBUG_BLK6_W3_REG register
+ *  Otp debuger block6 data register3.
+ */
+#define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130)
+/** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word3 data.
+ */
+#define OTP_DEBUG_BLOCK6_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W3_M  (OTP_DEBUG_BLOCK6_W3_V << OTP_DEBUG_BLOCK6_W3_S)
+#define OTP_DEBUG_BLOCK6_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W3_S  0
+
+/** OTP_DEBUG_BLK6_W4_REG register
+ *  Otp debuger block6 data register4.
+ */
+#define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134)
+/** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word4 data.
+ */
+#define OTP_DEBUG_BLOCK6_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W4_M  (OTP_DEBUG_BLOCK6_W4_V << OTP_DEBUG_BLOCK6_W4_S)
+#define OTP_DEBUG_BLOCK6_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W4_S  0
+
+/** OTP_DEBUG_BLK6_W5_REG register
+ *  Otp debuger block6 data register5.
+ */
+#define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138)
+/** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word5 data.
+ */
+#define OTP_DEBUG_BLOCK6_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W5_M  (OTP_DEBUG_BLOCK6_W5_V << OTP_DEBUG_BLOCK6_W5_S)
+#define OTP_DEBUG_BLOCK6_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W5_S  0
+
+/** OTP_DEBUG_BLK6_W6_REG register
+ *  Otp debuger block6 data register6.
+ */
+#define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c)
+/** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word6 data.
+ */
+#define OTP_DEBUG_BLOCK6_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W6_M  (OTP_DEBUG_BLOCK6_W6_V << OTP_DEBUG_BLOCK6_W6_S)
+#define OTP_DEBUG_BLOCK6_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W6_S  0
+
+/** OTP_DEBUG_BLK6_W7_REG register
+ *  Otp debuger block6 data register7.
+ */
+#define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140)
+/** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word7 data.
+ */
+#define OTP_DEBUG_BLOCK6_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W7_M  (OTP_DEBUG_BLOCK6_W7_V << OTP_DEBUG_BLOCK6_W7_S)
+#define OTP_DEBUG_BLOCK6_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W7_S  0
+
+/** OTP_DEBUG_BLK6_W8_REG register
+ *  Otp debuger block6 data register8.
+ */
+#define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144)
+/** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word8 data.
+ */
+#define OTP_DEBUG_BLOCK6_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W8_M  (OTP_DEBUG_BLOCK6_W8_V << OTP_DEBUG_BLOCK6_W8_S)
+#define OTP_DEBUG_BLOCK6_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W8_S  0
+
+/** OTP_DEBUG_BLK6_W9_REG register
+ *  Otp debuger block6 data register9.
+ */
+#define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148)
+/** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word9 data.
+ */
+#define OTP_DEBUG_BLOCK6_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W9_M  (OTP_DEBUG_BLOCK6_W9_V << OTP_DEBUG_BLOCK6_W9_S)
+#define OTP_DEBUG_BLOCK6_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W9_S  0
+
+/** OTP_DEBUG_BLK6_W10_REG register
+ *  Otp debuger block6 data register10.
+ */
+#define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c)
+/** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word10 data.
+ */
+#define OTP_DEBUG_BLOCK6_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W10_M  (OTP_DEBUG_BLOCK6_W10_V << OTP_DEBUG_BLOCK6_W10_S)
+#define OTP_DEBUG_BLOCK6_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W10_S  0
+
+/** OTP_DEBUG_BLK6_W11_REG register
+ *  Otp debuger block6 data register11.
+ */
+#define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150)
+/** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word11 data.
+ */
+#define OTP_DEBUG_BLOCK6_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W11_M  (OTP_DEBUG_BLOCK6_W11_V << OTP_DEBUG_BLOCK6_W11_S)
+#define OTP_DEBUG_BLOCK6_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK6_W11_S  0
+
+/** OTP_DEBUG_BLK7_W1_REG register
+ *  Otp debuger block7 data register1.
+ */
+#define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154)
+/** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word1 data.
+ */
+#define OTP_DEBUG_BLOCK7_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W1_M  (OTP_DEBUG_BLOCK7_W1_V << OTP_DEBUG_BLOCK7_W1_S)
+#define OTP_DEBUG_BLOCK7_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W1_S  0
+
+/** OTP_DEBUG_BLK7_W2_REG register
+ *  Otp debuger block7 data register2.
+ */
+#define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158)
+/** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word2 data.
+ */
+#define OTP_DEBUG_BLOCK7_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W2_M  (OTP_DEBUG_BLOCK7_W2_V << OTP_DEBUG_BLOCK7_W2_S)
+#define OTP_DEBUG_BLOCK7_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W2_S  0
+
+/** OTP_DEBUG_BLK7_W3_REG register
+ *  Otp debuger block7 data register3.
+ */
+#define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c)
+/** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word3 data.
+ */
+#define OTP_DEBUG_BLOCK7_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W3_M  (OTP_DEBUG_BLOCK7_W3_V << OTP_DEBUG_BLOCK7_W3_S)
+#define OTP_DEBUG_BLOCK7_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W3_S  0
+
+/** OTP_DEBUG_BLK7_W4_REG register
+ *  Otp debuger block7 data register4.
+ */
+#define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160)
+/** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word4 data.
+ */
+#define OTP_DEBUG_BLOCK7_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W4_M  (OTP_DEBUG_BLOCK7_W4_V << OTP_DEBUG_BLOCK7_W4_S)
+#define OTP_DEBUG_BLOCK7_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W4_S  0
+
+/** OTP_DEBUG_BLK7_W5_REG register
+ *  Otp debuger block7 data register5.
+ */
+#define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164)
+/** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word5 data.
+ */
+#define OTP_DEBUG_BLOCK7_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W5_M  (OTP_DEBUG_BLOCK7_W5_V << OTP_DEBUG_BLOCK7_W5_S)
+#define OTP_DEBUG_BLOCK7_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W5_S  0
+
+/** OTP_DEBUG_BLK7_W6_REG register
+ *  Otp debuger block7 data register6.
+ */
+#define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168)
+/** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word6 data.
+ */
+#define OTP_DEBUG_BLOCK7_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W6_M  (OTP_DEBUG_BLOCK7_W6_V << OTP_DEBUG_BLOCK7_W6_S)
+#define OTP_DEBUG_BLOCK7_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W6_S  0
+
+/** OTP_DEBUG_BLK7_W7_REG register
+ *  Otp debuger block7 data register7.
+ */
+#define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c)
+/** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word7 data.
+ */
+#define OTP_DEBUG_BLOCK7_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W7_M  (OTP_DEBUG_BLOCK7_W7_V << OTP_DEBUG_BLOCK7_W7_S)
+#define OTP_DEBUG_BLOCK7_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W7_S  0
+
+/** OTP_DEBUG_BLK7_W8_REG register
+ *  Otp debuger block7 data register8.
+ */
+#define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170)
+/** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word8 data.
+ */
+#define OTP_DEBUG_BLOCK7_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W8_M  (OTP_DEBUG_BLOCK7_W8_V << OTP_DEBUG_BLOCK7_W8_S)
+#define OTP_DEBUG_BLOCK7_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W8_S  0
+
+/** OTP_DEBUG_BLK7_W9_REG register
+ *  Otp debuger block7 data register9.
+ */
+#define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174)
+/** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word9 data.
+ */
+#define OTP_DEBUG_BLOCK7_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W9_M  (OTP_DEBUG_BLOCK7_W9_V << OTP_DEBUG_BLOCK7_W9_S)
+#define OTP_DEBUG_BLOCK7_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W9_S  0
+
+/** OTP_DEBUG_BLK7_W10_REG register
+ *  Otp debuger block7 data register10.
+ */
+#define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178)
+/** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word10 data.
+ */
+#define OTP_DEBUG_BLOCK7_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W10_M  (OTP_DEBUG_BLOCK7_W10_V << OTP_DEBUG_BLOCK7_W10_S)
+#define OTP_DEBUG_BLOCK7_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W10_S  0
+
+/** OTP_DEBUG_BLK7_W11_REG register
+ *  Otp debuger block7 data register11.
+ */
+#define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c)
+/** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word11 data.
+ */
+#define OTP_DEBUG_BLOCK7_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W11_M  (OTP_DEBUG_BLOCK7_W11_V << OTP_DEBUG_BLOCK7_W11_S)
+#define OTP_DEBUG_BLOCK7_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK7_W11_S  0
+
+/** OTP_DEBUG_BLK8_W1_REG register
+ *  Otp debuger block8 data register1.
+ */
+#define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180)
+/** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word1 data.
+ */
+#define OTP_DEBUG_BLOCK8_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W1_M  (OTP_DEBUG_BLOCK8_W1_V << OTP_DEBUG_BLOCK8_W1_S)
+#define OTP_DEBUG_BLOCK8_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W1_S  0
+
+/** OTP_DEBUG_BLK8_W2_REG register
+ *  Otp debuger block8 data register2.
+ */
+#define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184)
+/** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word2 data.
+ */
+#define OTP_DEBUG_BLOCK8_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W2_M  (OTP_DEBUG_BLOCK8_W2_V << OTP_DEBUG_BLOCK8_W2_S)
+#define OTP_DEBUG_BLOCK8_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W2_S  0
+
+/** OTP_DEBUG_BLK8_W3_REG register
+ *  Otp debuger block8 data register3.
+ */
+#define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188)
+/** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word3 data.
+ */
+#define OTP_DEBUG_BLOCK8_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W3_M  (OTP_DEBUG_BLOCK8_W3_V << OTP_DEBUG_BLOCK8_W3_S)
+#define OTP_DEBUG_BLOCK8_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W3_S  0
+
+/** OTP_DEBUG_BLK8_W4_REG register
+ *  Otp debuger block8 data register4.
+ */
+#define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c)
+/** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word4 data.
+ */
+#define OTP_DEBUG_BLOCK8_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W4_M  (OTP_DEBUG_BLOCK8_W4_V << OTP_DEBUG_BLOCK8_W4_S)
+#define OTP_DEBUG_BLOCK8_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W4_S  0
+
+/** OTP_DEBUG_BLK8_W5_REG register
+ *  Otp debuger block8 data register5.
+ */
+#define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190)
+/** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word5 data.
+ */
+#define OTP_DEBUG_BLOCK8_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W5_M  (OTP_DEBUG_BLOCK8_W5_V << OTP_DEBUG_BLOCK8_W5_S)
+#define OTP_DEBUG_BLOCK8_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W5_S  0
+
+/** OTP_DEBUG_BLK8_W6_REG register
+ *  Otp debuger block8 data register6.
+ */
+#define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194)
+/** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word6 data.
+ */
+#define OTP_DEBUG_BLOCK8_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W6_M  (OTP_DEBUG_BLOCK8_W6_V << OTP_DEBUG_BLOCK8_W6_S)
+#define OTP_DEBUG_BLOCK8_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W6_S  0
+
+/** OTP_DEBUG_BLK8_W7_REG register
+ *  Otp debuger block8 data register7.
+ */
+#define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198)
+/** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word7 data.
+ */
+#define OTP_DEBUG_BLOCK8_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W7_M  (OTP_DEBUG_BLOCK8_W7_V << OTP_DEBUG_BLOCK8_W7_S)
+#define OTP_DEBUG_BLOCK8_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W7_S  0
+
+/** OTP_DEBUG_BLK8_W8_REG register
+ *  Otp debuger block8 data register8.
+ */
+#define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c)
+/** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word8 data.
+ */
+#define OTP_DEBUG_BLOCK8_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W8_M  (OTP_DEBUG_BLOCK8_W8_V << OTP_DEBUG_BLOCK8_W8_S)
+#define OTP_DEBUG_BLOCK8_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W8_S  0
+
+/** OTP_DEBUG_BLK8_W9_REG register
+ *  Otp debuger block8 data register9.
+ */
+#define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0)
+/** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word9 data.
+ */
+#define OTP_DEBUG_BLOCK8_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W9_M  (OTP_DEBUG_BLOCK8_W9_V << OTP_DEBUG_BLOCK8_W9_S)
+#define OTP_DEBUG_BLOCK8_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W9_S  0
+
+/** OTP_DEBUG_BLK8_W10_REG register
+ *  Otp debuger block8 data register10.
+ */
+#define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4)
+/** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word10 data.
+ */
+#define OTP_DEBUG_BLOCK8_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W10_M  (OTP_DEBUG_BLOCK8_W10_V << OTP_DEBUG_BLOCK8_W10_S)
+#define OTP_DEBUG_BLOCK8_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W10_S  0
+
+/** OTP_DEBUG_BLK8_W11_REG register
+ *  Otp debuger block8 data register11.
+ */
+#define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8)
+/** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word11 data.
+ */
+#define OTP_DEBUG_BLOCK8_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W11_M  (OTP_DEBUG_BLOCK8_W11_V << OTP_DEBUG_BLOCK8_W11_S)
+#define OTP_DEBUG_BLOCK8_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK8_W11_S  0
+
+/** OTP_DEBUG_BLK9_W1_REG register
+ *  Otp debuger block9 data register1.
+ */
+#define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac)
+/** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word1 data.
+ */
+#define OTP_DEBUG_BLOCK9_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W1_M  (OTP_DEBUG_BLOCK9_W1_V << OTP_DEBUG_BLOCK9_W1_S)
+#define OTP_DEBUG_BLOCK9_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W1_S  0
+
+/** OTP_DEBUG_BLK9_W2_REG register
+ *  Otp debuger block9 data register2.
+ */
+#define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0)
+/** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word2 data.
+ */
+#define OTP_DEBUG_BLOCK9_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W2_M  (OTP_DEBUG_BLOCK9_W2_V << OTP_DEBUG_BLOCK9_W2_S)
+#define OTP_DEBUG_BLOCK9_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W2_S  0
+
+/** OTP_DEBUG_BLK9_W3_REG register
+ *  Otp debuger block9 data register3.
+ */
+#define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4)
+/** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word3 data.
+ */
+#define OTP_DEBUG_BLOCK9_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W3_M  (OTP_DEBUG_BLOCK9_W3_V << OTP_DEBUG_BLOCK9_W3_S)
+#define OTP_DEBUG_BLOCK9_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W3_S  0
+
+/** OTP_DEBUG_BLK9_W4_REG register
+ *  Otp debuger block9 data register4.
+ */
+#define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8)
+/** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word4 data.
+ */
+#define OTP_DEBUG_BLOCK9_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W4_M  (OTP_DEBUG_BLOCK9_W4_V << OTP_DEBUG_BLOCK9_W4_S)
+#define OTP_DEBUG_BLOCK9_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W4_S  0
+
+/** OTP_DEBUG_BLK9_W5_REG register
+ *  Otp debuger block9 data register5.
+ */
+#define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc)
+/** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word5 data.
+ */
+#define OTP_DEBUG_BLOCK9_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W5_M  (OTP_DEBUG_BLOCK9_W5_V << OTP_DEBUG_BLOCK9_W5_S)
+#define OTP_DEBUG_BLOCK9_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W5_S  0
+
+/** OTP_DEBUG_BLK9_W6_REG register
+ *  Otp debuger block9 data register6.
+ */
+#define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0)
+/** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word6 data.
+ */
+#define OTP_DEBUG_BLOCK9_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W6_M  (OTP_DEBUG_BLOCK9_W6_V << OTP_DEBUG_BLOCK9_W6_S)
+#define OTP_DEBUG_BLOCK9_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W6_S  0
+
+/** OTP_DEBUG_BLK9_W7_REG register
+ *  Otp debuger block9 data register7.
+ */
+#define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4)
+/** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word7 data.
+ */
+#define OTP_DEBUG_BLOCK9_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W7_M  (OTP_DEBUG_BLOCK9_W7_V << OTP_DEBUG_BLOCK9_W7_S)
+#define OTP_DEBUG_BLOCK9_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W7_S  0
+
+/** OTP_DEBUG_BLK9_W8_REG register
+ *  Otp debuger block9 data register8.
+ */
+#define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8)
+/** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word8 data.
+ */
+#define OTP_DEBUG_BLOCK9_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W8_M  (OTP_DEBUG_BLOCK9_W8_V << OTP_DEBUG_BLOCK9_W8_S)
+#define OTP_DEBUG_BLOCK9_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W8_S  0
+
+/** OTP_DEBUG_BLK9_W9_REG register
+ *  Otp debuger block9 data register9.
+ */
+#define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc)
+/** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word9 data.
+ */
+#define OTP_DEBUG_BLOCK9_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W9_M  (OTP_DEBUG_BLOCK9_W9_V << OTP_DEBUG_BLOCK9_W9_S)
+#define OTP_DEBUG_BLOCK9_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W9_S  0
+
+/** OTP_DEBUG_BLK9_W10_REG register
+ *  Otp debuger block9 data register10.
+ */
+#define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0)
+/** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word10 data.
+ */
+#define OTP_DEBUG_BLOCK9_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W10_M  (OTP_DEBUG_BLOCK9_W10_V << OTP_DEBUG_BLOCK9_W10_S)
+#define OTP_DEBUG_BLOCK9_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W10_S  0
+
+/** OTP_DEBUG_BLK9_W11_REG register
+ *  Otp debuger block9 data register11.
+ */
+#define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4)
+/** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word11 data.
+ */
+#define OTP_DEBUG_BLOCK9_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W11_M  (OTP_DEBUG_BLOCK9_W11_V << OTP_DEBUG_BLOCK9_W11_S)
+#define OTP_DEBUG_BLOCK9_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK9_W11_S  0
+
+/** OTP_DEBUG_BLK10_W1_REG register
+ *  Otp debuger block10 data register1.
+ */
+#define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8)
+/** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word1 data.
+ */
+#define OTP_DEBUG_BLOCK10_W1    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W1_M  (OTP_DEBUG_BLOCK10_W1_V << OTP_DEBUG_BLOCK10_W1_S)
+#define OTP_DEBUG_BLOCK10_W1_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W1_S  0
+
+/** OTP_DEBUG_BLK10_W2_REG register
+ *  Otp debuger block10 data register2.
+ */
+#define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc)
+/** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word2 data.
+ */
+#define OTP_DEBUG_BLOCK10_W2    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W2_M  (OTP_DEBUG_BLOCK10_W2_V << OTP_DEBUG_BLOCK10_W2_S)
+#define OTP_DEBUG_BLOCK10_W2_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W2_S  0
+
+/** OTP_DEBUG_BLK10_W3_REG register
+ *  Otp debuger block10 data register3.
+ */
+#define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0)
+/** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word3 data.
+ */
+#define OTP_DEBUG_BLOCK10_W3    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W3_M  (OTP_DEBUG_BLOCK10_W3_V << OTP_DEBUG_BLOCK10_W3_S)
+#define OTP_DEBUG_BLOCK10_W3_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W3_S  0
+
+/** OTP_DEBUG_BLK10_W4_REG register
+ *  Otp debuger block10 data register4.
+ */
+#define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4)
+/** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word4 data.
+ */
+#define OTP_DEBUG_BLOCK10_W4    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W4_M  (OTP_DEBUG_BLOCK10_W4_V << OTP_DEBUG_BLOCK10_W4_S)
+#define OTP_DEBUG_BLOCK10_W4_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W4_S  0
+
+/** OTP_DEBUG_BLK10_W5_REG register
+ *  Otp debuger block10 data register5.
+ */
+#define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8)
+/** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word5 data.
+ */
+#define OTP_DEBUG_BLOCK10_W5    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W5_M  (OTP_DEBUG_BLOCK10_W5_V << OTP_DEBUG_BLOCK10_W5_S)
+#define OTP_DEBUG_BLOCK10_W5_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W5_S  0
+
+/** OTP_DEBUG_BLK10_W6_REG register
+ *  Otp debuger block10 data register6.
+ */
+#define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec)
+/** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word6 data.
+ */
+#define OTP_DEBUG_BLOCK10_W6    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W6_M  (OTP_DEBUG_BLOCK10_W6_V << OTP_DEBUG_BLOCK10_W6_S)
+#define OTP_DEBUG_BLOCK10_W6_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W6_S  0
+
+/** OTP_DEBUG_BLK10_W7_REG register
+ *  Otp debuger block10 data register7.
+ */
+#define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0)
+/** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word7 data.
+ */
+#define OTP_DEBUG_BLOCK10_W7    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W7_M  (OTP_DEBUG_BLOCK10_W7_V << OTP_DEBUG_BLOCK10_W7_S)
+#define OTP_DEBUG_BLOCK10_W7_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W7_S  0
+
+/** OTP_DEBUG_BLK10_W8_REG register
+ *  Otp debuger block10 data register8.
+ */
+#define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4)
+/** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word8 data.
+ */
+#define OTP_DEBUG_BLOCK10_W8    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W8_M  (OTP_DEBUG_BLOCK10_W8_V << OTP_DEBUG_BLOCK10_W8_S)
+#define OTP_DEBUG_BLOCK10_W8_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W8_S  0
+
+/** OTP_DEBUG_BLK10_W9_REG register
+ *  Otp debuger block10 data register9.
+ */
+#define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8)
+/** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word9 data.
+ */
+#define OTP_DEBUG_BLOCK10_W9    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W9_M  (OTP_DEBUG_BLOCK10_W9_V << OTP_DEBUG_BLOCK10_W9_S)
+#define OTP_DEBUG_BLOCK10_W9_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W9_S  0
+
+/** OTP_DEBUG_BLK10_W10_REG register
+ *  Otp debuger block10 data register10.
+ */
+#define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc)
+/** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word10 data.
+ */
+#define OTP_DEBUG_BLOCK19_W10    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK19_W10_M  (OTP_DEBUG_BLOCK19_W10_V << OTP_DEBUG_BLOCK19_W10_S)
+#define OTP_DEBUG_BLOCK19_W10_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK19_W10_S  0
+
+/** OTP_DEBUG_BLK10_W11_REG register
+ *  Otp debuger block10 data register11.
+ */
+#define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200)
+/** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word11 data.
+ */
+#define OTP_DEBUG_BLOCK10_W11    0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W11_M  (OTP_DEBUG_BLOCK10_W11_V << OTP_DEBUG_BLOCK10_W11_S)
+#define OTP_DEBUG_BLOCK10_W11_V  0xFFFFFFFFU
+#define OTP_DEBUG_BLOCK10_W11_S  0
+
+/** OTP_DEBUG_CLK_REG register
+ *  Otp debuger clk_en configuration register.
+ */
+#define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204)
+/** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Force clock on for this register file.
+ */
+#define OTP_DEBUG_CLK_EN    (BIT(0))
+#define OTP_DEBUG_CLK_EN_M  (OTP_DEBUG_CLK_EN_V << OTP_DEBUG_CLK_EN_S)
+#define OTP_DEBUG_CLK_EN_V  0x00000001U
+#define OTP_DEBUG_CLK_EN_S  0
+
+/** OTP_DEBUG_APB2OTP_EN_REG register
+ *  Otp_debuger apb2otp enable configuration register.
+ */
+#define OTP_DEBUG_APB2OTP_EN_REG (DR_REG_OTP_DEBUG_BASE + 0x208)
+/** OTP_DEBUG_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
+ *  Debug mode enable signal.
+ */
+#define OTP_DEBUG_APB2OTP_EN    (BIT(0))
+#define OTP_DEBUG_APB2OTP_EN_M  (OTP_DEBUG_APB2OTP_EN_V << OTP_DEBUG_APB2OTP_EN_S)
+#define OTP_DEBUG_APB2OTP_EN_V  0x00000001U
+#define OTP_DEBUG_APB2OTP_EN_S  0
+
+/** OTP_DEBUG_DATE_REG register
+ *  eFuse version register.
+ */
+#define OTP_DEBUG_DATE_REG (DR_REG_OTP_DEBUG_BASE + 0x20c)
+/** OTP_DEBUG_DATE : R/W; bitpos: [27:0]; default: 539037736;
+ *  Stores otp_debug version.
+ */
+#define OTP_DEBUG_DATE    0x0FFFFFFFU
+#define OTP_DEBUG_DATE_M  (OTP_DEBUG_DATE_V << OTP_DEBUG_DATE_S)
+#define OTP_DEBUG_DATE_V  0x0FFFFFFFU
+#define OTP_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/otp_debug_struct.h b/components/soc/esp32p4/include/soc/otp_debug_struct.h
new file mode 100644
index 0000000000..8166a857cb
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/otp_debug_struct.h
@@ -0,0 +1,2137 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: OTP_DEBUG Block0 Write Disable Data */
+/** Type of wr_dis register
+ *  Otp debuger block0 data register1.
+ */
+typedef union {
+    struct {
+        /** block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t block0_wr_dis:32;
+    };
+    uint32_t val;
+} otp_debug_wr_dis_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup1 Word1 Data */
+/** Type of blk0_backup1_w1 register
+ *  Otp debuger block0 data register2.
+ */
+typedef union {
+    struct {
+        /** block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t block0_backup1_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup1_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup1 Word2 Data */
+/** Type of blk0_backup1_w2 register
+ *  Otp debuger block0 data register3.
+ */
+typedef union {
+    struct {
+        /** block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t block0_backup1_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup1_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup1 Word3 Data */
+/** Type of blk0_backup1_w3 register
+ *  Otp debuger block0 data register4.
+ */
+typedef union {
+    struct {
+        /** block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t block0_backup1_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup1_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup1 Word4 Data */
+/** Type of blk0_backup1_w4 register
+ *  Otp debuger block0 data register5.
+ */
+typedef union {
+    struct {
+        /** block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t block0_backup1_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup1_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup1 Word5 Data */
+/** Type of blk0_backup1_w5 register
+ *  Otp debuger block0 data register6.
+ */
+typedef union {
+    struct {
+        /** block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t block0_backup1_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup1_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup2 Word1 Data */
+/** Type of blk0_backup2_w1 register
+ *  Otp debuger block0 data register7.
+ */
+typedef union {
+    struct {
+        /** block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t block0_backup2_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup2_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup2 Word2 Data */
+/** Type of blk0_backup2_w2 register
+ *  Otp debuger block0 data register8.
+ */
+typedef union {
+    struct {
+        /** block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t block0_backup2_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup2_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup2 Word3 Data */
+/** Type of blk0_backup2_w3 register
+ *  Otp debuger block0 data register9.
+ */
+typedef union {
+    struct {
+        /** block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t block0_backup2_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup2_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup2 Word4 Data */
+/** Type of blk0_backup2_w4 register
+ *  Otp debuger block0 data register10.
+ */
+typedef union {
+    struct {
+        /** block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t block0_backup2_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup2_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup2 Word5 Data */
+/** Type of blk0_backup2_w5 register
+ *  Otp debuger block0 data register11.
+ */
+typedef union {
+    struct {
+        /** block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t block0_backup2_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup2_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup3 Word1 Data */
+/** Type of blk0_backup3_w1 register
+ *  Otp debuger block0 data register12.
+ */
+typedef union {
+    struct {
+        /** block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t block0_backup3_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup3_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup3 Word2 Data */
+/** Type of blk0_backup3_w2 register
+ *  Otp debuger block0 data register13.
+ */
+typedef union {
+    struct {
+        /** block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t block0_backup3_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup3_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup3 Word3 Data */
+/** Type of blk0_backup3_w3 register
+ *  Otp debuger block0 data register14.
+ */
+typedef union {
+    struct {
+        /** block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t block0_backup3_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup3_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup3 Word4 Data */
+/** Type of blk0_backup3_w4 register
+ *  Otp debuger block0 data register15.
+ */
+typedef union {
+    struct {
+        /** block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t block0_backup3_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup3_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup3 Word5 Data */
+/** Type of blk0_backup3_w5 register
+ *  Otp debuger block0 data register16.
+ */
+typedef union {
+    struct {
+        /** block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t block0_backup3_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup3_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup4 Word1 Data */
+/** Type of blk0_backup4_w1 register
+ *  Otp debuger block0 data register17.
+ */
+typedef union {
+    struct {
+        /** block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t block0_backup4_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup4_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup4 Word2 Data */
+/** Type of blk0_backup4_w2 register
+ *  Otp debuger block0 data register18.
+ */
+typedef union {
+    struct {
+        /** block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t block0_backup4_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup4_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup4 Word3 Data */
+/** Type of blk0_backup4_w3 register
+ *  Otp debuger block0 data register19.
+ */
+typedef union {
+    struct {
+        /** block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t block0_backup4_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup4_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup4 Word4 Data */
+/** Type of blk0_backup4_w4 register
+ *  Otp debuger block0 data register20.
+ */
+typedef union {
+    struct {
+        /** block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t block0_backup4_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup4_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block0 Backup4 Word5 Data */
+/** Type of blk0_backup4_w5 register
+ *  Otp debuger block0 data register21.
+ */
+typedef union {
+    struct {
+        /** block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t block0_backup4_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk0_backup4_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word1 Data */
+/** Type of blk1_w1 register
+ *  Otp debuger block1 data register1.
+ */
+typedef union {
+    struct {
+        /** block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t block1_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word2 Data */
+/** Type of blk1_w2 register
+ *  Otp debuger block1 data register2.
+ */
+typedef union {
+    struct {
+        /** block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t block1_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word3 Data */
+/** Type of blk1_w3 register
+ *  Otp debuger block1 data register3.
+ */
+typedef union {
+    struct {
+        /** block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t block1_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word4 Data */
+/** Type of blk1_w4 register
+ *  Otp debuger block1 data register4.
+ */
+typedef union {
+    struct {
+        /** block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t block1_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word5 Data */
+/** Type of blk1_w5 register
+ *  Otp debuger block1 data register5.
+ */
+typedef union {
+    struct {
+        /** block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t block1_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word6 Data */
+/** Type of blk1_w6 register
+ *  Otp debuger block1 data register6.
+ */
+typedef union {
+    struct {
+        /** block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t block1_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word7 Data */
+/** Type of blk1_w7 register
+ *  Otp debuger block1 data register7.
+ */
+typedef union {
+    struct {
+        /** block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t block1_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word8 Data */
+/** Type of blk1_w8 register
+ *  Otp debuger block1 data register8.
+ */
+typedef union {
+    struct {
+        /** block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t block1_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block1 Word9 Data */
+/** Type of blk1_w9 register
+ *  Otp debuger block1 data register9.
+ */
+typedef union {
+    struct {
+        /** block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t block1_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk1_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word1 Data */
+/** Type of blk2_w1 register
+ *  Otp debuger block2 data register1.
+ */
+typedef union {
+    struct {
+        /** block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t block2_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word2 Data */
+/** Type of blk2_w2 register
+ *  Otp debuger block2 data register2.
+ */
+typedef union {
+    struct {
+        /** block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t block2_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word3 Data */
+/** Type of blk2_w3 register
+ *  Otp debuger block2 data register3.
+ */
+typedef union {
+    struct {
+        /** block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t block2_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word4 Data */
+/** Type of blk2_w4 register
+ *  Otp debuger block2 data register4.
+ */
+typedef union {
+    struct {
+        /** block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t block2_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word5 Data */
+/** Type of blk2_w5 register
+ *  Otp debuger block2 data register5.
+ */
+typedef union {
+    struct {
+        /** block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t block2_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word6 Data */
+/** Type of blk2_w6 register
+ *  Otp debuger block2 data register6.
+ */
+typedef union {
+    struct {
+        /** block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t block2_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word7 Data */
+/** Type of blk2_w7 register
+ *  Otp debuger block2 data register7.
+ */
+typedef union {
+    struct {
+        /** block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t block2_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word8 Data */
+/** Type of blk2_w8 register
+ *  Otp debuger block2 data register8.
+ */
+typedef union {
+    struct {
+        /** block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t block2_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word9 Data */
+/** Type of blk2_w9 register
+ *  Otp debuger block2 data register9.
+ */
+typedef union {
+    struct {
+        /** block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t block2_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word10 Data */
+/** Type of blk2_w10 register
+ *  Otp debuger block2 data register10.
+ */
+typedef union {
+    struct {
+        /** block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t block2_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block2 Word11 Data */
+/** Type of blk2_w11 register
+ *  Otp debuger block2 data register11.
+ */
+typedef union {
+    struct {
+        /** block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t block2_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk2_w11_reg_t;
+
+/** Type of blk10_w11 register
+ *  Otp debuger block10 data register11.
+ */
+typedef union {
+    struct {
+        /** block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t block10_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word1 Data */
+/** Type of blk3_w1 register
+ *  Otp debuger block3 data register1.
+ */
+typedef union {
+    struct {
+        /** block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t block3_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word2 Data */
+/** Type of blk3_w2 register
+ *  Otp debuger block3 data register2.
+ */
+typedef union {
+    struct {
+        /** block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t block3_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word3 Data */
+/** Type of blk3_w3 register
+ *  Otp debuger block3 data register3.
+ */
+typedef union {
+    struct {
+        /** block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t block3_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word4 Data */
+/** Type of blk3_w4 register
+ *  Otp debuger block3 data register4.
+ */
+typedef union {
+    struct {
+        /** block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t block3_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word5 Data */
+/** Type of blk3_w5 register
+ *  Otp debuger block3 data register5.
+ */
+typedef union {
+    struct {
+        /** block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t block3_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word6 Data */
+/** Type of blk3_w6 register
+ *  Otp debuger block3 data register6.
+ */
+typedef union {
+    struct {
+        /** block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t block3_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word7 Data */
+/** Type of blk3_w7 register
+ *  Otp debuger block3 data register7.
+ */
+typedef union {
+    struct {
+        /** block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t block3_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word8 Data */
+/** Type of blk3_w8 register
+ *  Otp debuger block3 data register8.
+ */
+typedef union {
+    struct {
+        /** block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t block3_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word9 Data */
+/** Type of blk3_w9 register
+ *  Otp debuger block3 data register9.
+ */
+typedef union {
+    struct {
+        /** block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t block3_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word10 Data */
+/** Type of blk3_w10 register
+ *  Otp debuger block3 data register10.
+ */
+typedef union {
+    struct {
+        /** block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t block3_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block3 Word11 Data */
+/** Type of blk3_w11 register
+ *  Otp debuger block3 data register11.
+ */
+typedef union {
+    struct {
+        /** block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t block3_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk3_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word1 Data */
+/** Type of blk4_w1 register
+ *  Otp debuger block4 data register1.
+ */
+typedef union {
+    struct {
+        /** block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t block4_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word2 Data */
+/** Type of blk4_w2 register
+ *  Otp debuger block4 data register2.
+ */
+typedef union {
+    struct {
+        /** block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t block4_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word3 Data */
+/** Type of blk4_w3 register
+ *  Otp debuger block4 data register3.
+ */
+typedef union {
+    struct {
+        /** block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t block4_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word4 Data */
+/** Type of blk4_w4 register
+ *  Otp debuger block4 data register4.
+ */
+typedef union {
+    struct {
+        /** block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t block4_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word5 Data */
+/** Type of blk4_w5 register
+ *  Otp debuger block4 data register5.
+ */
+typedef union {
+    struct {
+        /** block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t block4_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word6 Data */
+/** Type of blk4_w6 register
+ *  Otp debuger block4 data register6.
+ */
+typedef union {
+    struct {
+        /** block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t block4_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word7 Data */
+/** Type of blk4_w7 register
+ *  Otp debuger block4 data register7.
+ */
+typedef union {
+    struct {
+        /** block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t block4_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word8 Data */
+/** Type of blk4_w8 register
+ *  Otp debuger block4 data register8.
+ */
+typedef union {
+    struct {
+        /** block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t block4_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word9 Data */
+/** Type of blk4_w9 register
+ *  Otp debuger block4 data register9.
+ */
+typedef union {
+    struct {
+        /** block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t block4_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word10 Data */
+/** Type of blk4_w10 register
+ *  Otp debuger block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t block4_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block4 Word11 Data */
+/** Type of blk4_w11 register
+ *  Otp debuger block4 data register11.
+ */
+typedef union {
+    struct {
+        /** block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t block4_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk4_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word1 Data */
+/** Type of blk5_w1 register
+ *  Otp debuger block5 data register1.
+ */
+typedef union {
+    struct {
+        /** block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t block5_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word2 Data */
+/** Type of blk5_w2 register
+ *  Otp debuger block5 data register2.
+ */
+typedef union {
+    struct {
+        /** block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t block5_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word3 Data */
+/** Type of blk5_w3 register
+ *  Otp debuger block5 data register3.
+ */
+typedef union {
+    struct {
+        /** block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t block5_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word4 Data */
+/** Type of blk5_w4 register
+ *  Otp debuger block5 data register4.
+ */
+typedef union {
+    struct {
+        /** block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t block5_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word5 Data */
+/** Type of blk5_w5 register
+ *  Otp debuger block5 data register5.
+ */
+typedef union {
+    struct {
+        /** block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t block5_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word6 Data */
+/** Type of blk5_w6 register
+ *  Otp debuger block5 data register6.
+ */
+typedef union {
+    struct {
+        /** block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t block5_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word7 Data */
+/** Type of blk5_w7 register
+ *  Otp debuger block5 data register7.
+ */
+typedef union {
+    struct {
+        /** block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t block5_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word8 Data */
+/** Type of blk5_w8 register
+ *  Otp debuger block5 data register8.
+ */
+typedef union {
+    struct {
+        /** block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t block5_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word9 Data */
+/** Type of blk5_w9 register
+ *  Otp debuger block5 data register9.
+ */
+typedef union {
+    struct {
+        /** block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t block5_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word10 Data */
+/** Type of blk5_w10 register
+ *  Otp debuger block5 data register10.
+ */
+typedef union {
+    struct {
+        /** block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t block5_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block5 Word11 Data */
+/** Type of blk5_w11 register
+ *  Otp debuger block5 data register11.
+ */
+typedef union {
+    struct {
+        /** block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t block5_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk5_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word1 Data */
+/** Type of blk6_w1 register
+ *  Otp debuger block6 data register1.
+ */
+typedef union {
+    struct {
+        /** block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t block6_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word2 Data */
+/** Type of blk6_w2 register
+ *  Otp debuger block6 data register2.
+ */
+typedef union {
+    struct {
+        /** block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t block6_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word3 Data */
+/** Type of blk6_w3 register
+ *  Otp debuger block6 data register3.
+ */
+typedef union {
+    struct {
+        /** block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t block6_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word4 Data */
+/** Type of blk6_w4 register
+ *  Otp debuger block6 data register4.
+ */
+typedef union {
+    struct {
+        /** block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t block6_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word5 Data */
+/** Type of blk6_w5 register
+ *  Otp debuger block6 data register5.
+ */
+typedef union {
+    struct {
+        /** block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t block6_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word6 Data */
+/** Type of blk6_w6 register
+ *  Otp debuger block6 data register6.
+ */
+typedef union {
+    struct {
+        /** block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t block6_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word7 Data */
+/** Type of blk6_w7 register
+ *  Otp debuger block6 data register7.
+ */
+typedef union {
+    struct {
+        /** block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t block6_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word8 Data */
+/** Type of blk6_w8 register
+ *  Otp debuger block6 data register8.
+ */
+typedef union {
+    struct {
+        /** block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t block6_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word9 Data */
+/** Type of blk6_w9 register
+ *  Otp debuger block6 data register9.
+ */
+typedef union {
+    struct {
+        /** block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t block6_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word10 Data */
+/** Type of blk6_w10 register
+ *  Otp debuger block6 data register10.
+ */
+typedef union {
+    struct {
+        /** block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t block6_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block6 Word11 Data */
+/** Type of blk6_w11 register
+ *  Otp debuger block6 data register11.
+ */
+typedef union {
+    struct {
+        /** block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t block6_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk6_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word1 Data */
+/** Type of blk7_w1 register
+ *  Otp debuger block7 data register1.
+ */
+typedef union {
+    struct {
+        /** block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t block7_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word2 Data */
+/** Type of blk7_w2 register
+ *  Otp debuger block7 data register2.
+ */
+typedef union {
+    struct {
+        /** block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t block7_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word3 Data */
+/** Type of blk7_w3 register
+ *  Otp debuger block7 data register3.
+ */
+typedef union {
+    struct {
+        /** block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t block7_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word4 Data */
+/** Type of blk7_w4 register
+ *  Otp debuger block7 data register4.
+ */
+typedef union {
+    struct {
+        /** block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t block7_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word5 Data */
+/** Type of blk7_w5 register
+ *  Otp debuger block7 data register5.
+ */
+typedef union {
+    struct {
+        /** block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t block7_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word6 Data */
+/** Type of blk7_w6 register
+ *  Otp debuger block7 data register6.
+ */
+typedef union {
+    struct {
+        /** block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t block7_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word7 Data */
+/** Type of blk7_w7 register
+ *  Otp debuger block7 data register7.
+ */
+typedef union {
+    struct {
+        /** block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t block7_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word8 Data */
+/** Type of blk7_w8 register
+ *  Otp debuger block7 data register8.
+ */
+typedef union {
+    struct {
+        /** block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t block7_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word9 Data */
+/** Type of blk7_w9 register
+ *  Otp debuger block7 data register9.
+ */
+typedef union {
+    struct {
+        /** block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t block7_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word10 Data */
+/** Type of blk7_w10 register
+ *  Otp debuger block7 data register10.
+ */
+typedef union {
+    struct {
+        /** block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t block7_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block7 Word11 Data */
+/** Type of blk7_w11 register
+ *  Otp debuger block7 data register11.
+ */
+typedef union {
+    struct {
+        /** block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t block7_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk7_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word1 Data */
+/** Type of blk8_w1 register
+ *  Otp debuger block8 data register1.
+ */
+typedef union {
+    struct {
+        /** block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t block8_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word2 Data */
+/** Type of blk8_w2 register
+ *  Otp debuger block8 data register2.
+ */
+typedef union {
+    struct {
+        /** block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t block8_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word3 Data */
+/** Type of blk8_w3 register
+ *  Otp debuger block8 data register3.
+ */
+typedef union {
+    struct {
+        /** block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t block8_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word4 Data */
+/** Type of blk8_w4 register
+ *  Otp debuger block8 data register4.
+ */
+typedef union {
+    struct {
+        /** block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t block8_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word5 Data */
+/** Type of blk8_w5 register
+ *  Otp debuger block8 data register5.
+ */
+typedef union {
+    struct {
+        /** block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t block8_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word6 Data */
+/** Type of blk8_w6 register
+ *  Otp debuger block8 data register6.
+ */
+typedef union {
+    struct {
+        /** block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t block8_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word7 Data */
+/** Type of blk8_w7 register
+ *  Otp debuger block8 data register7.
+ */
+typedef union {
+    struct {
+        /** block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t block8_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word8 Data */
+/** Type of blk8_w8 register
+ *  Otp debuger block8 data register8.
+ */
+typedef union {
+    struct {
+        /** block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t block8_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word9 Data */
+/** Type of blk8_w9 register
+ *  Otp debuger block8 data register9.
+ */
+typedef union {
+    struct {
+        /** block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t block8_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word10 Data */
+/** Type of blk8_w10 register
+ *  Otp debuger block8 data register10.
+ */
+typedef union {
+    struct {
+        /** block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t block8_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block8 Word11 Data */
+/** Type of blk8_w11 register
+ *  Otp debuger block8 data register11.
+ */
+typedef union {
+    struct {
+        /** block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t block8_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk8_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word1 Data */
+/** Type of blk9_w1 register
+ *  Otp debuger block9 data register1.
+ */
+typedef union {
+    struct {
+        /** block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t block9_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word2 Data */
+/** Type of blk9_w2 register
+ *  Otp debuger block9 data register2.
+ */
+typedef union {
+    struct {
+        /** block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t block9_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word3 Data */
+/** Type of blk9_w3 register
+ *  Otp debuger block9 data register3.
+ */
+typedef union {
+    struct {
+        /** block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t block9_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word4 Data */
+/** Type of blk9_w4 register
+ *  Otp debuger block9 data register4.
+ */
+typedef union {
+    struct {
+        /** block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t block9_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word5 Data */
+/** Type of blk9_w5 register
+ *  Otp debuger block9 data register5.
+ */
+typedef union {
+    struct {
+        /** block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t block9_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word6 Data */
+/** Type of blk9_w6 register
+ *  Otp debuger block9 data register6.
+ */
+typedef union {
+    struct {
+        /** block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t block9_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word7 Data */
+/** Type of blk9_w7 register
+ *  Otp debuger block9 data register7.
+ */
+typedef union {
+    struct {
+        /** block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t block9_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word8 Data */
+/** Type of blk9_w8 register
+ *  Otp debuger block9 data register8.
+ */
+typedef union {
+    struct {
+        /** block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t block9_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word9 Data */
+/** Type of blk9_w9 register
+ *  Otp debuger block9 data register9.
+ */
+typedef union {
+    struct {
+        /** block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t block9_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word10 Data */
+/** Type of blk9_w10 register
+ *  Otp debuger block9 data register10.
+ */
+typedef union {
+    struct {
+        /** block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t block9_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Block9 Word11 Data */
+/** Type of blk9_w11 register
+ *  Otp debuger block9 data register11.
+ */
+typedef union {
+    struct {
+        /** block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t block9_w11:32;
+    };
+    uint32_t val;
+} otp_debug_blk9_w11_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word1 Data */
+/** Type of blk10_w1 register
+ *  Otp debuger block10 data register1.
+ */
+typedef union {
+    struct {
+        /** block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t block10_w1:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w1_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word2 Data */
+/** Type of blk10_w2 register
+ *  Otp debuger block10 data register2.
+ */
+typedef union {
+    struct {
+        /** block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t block10_w2:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w2_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word3 Data */
+/** Type of blk10_w3 register
+ *  Otp debuger block10 data register3.
+ */
+typedef union {
+    struct {
+        /** block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t block10_w3:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w3_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word4 Data */
+/** Type of blk10_w4 register
+ *  Otp debuger block10 data register4.
+ */
+typedef union {
+    struct {
+        /** block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t block10_w4:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w4_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word5 Data */
+/** Type of blk10_w5 register
+ *  Otp debuger block10 data register5.
+ */
+typedef union {
+    struct {
+        /** block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t block10_w5:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w5_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word6 Data */
+/** Type of blk10_w6 register
+ *  Otp debuger block10 data register6.
+ */
+typedef union {
+    struct {
+        /** block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t block10_w6:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w6_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word7 Data */
+/** Type of blk10_w7 register
+ *  Otp debuger block10 data register7.
+ */
+typedef union {
+    struct {
+        /** block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t block10_w7:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w7_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word8 Data */
+/** Type of blk10_w8 register
+ *  Otp debuger block10 data register8.
+ */
+typedef union {
+    struct {
+        /** block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t block10_w8:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w8_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word9 Data */
+/** Type of blk10_w9 register
+ *  Otp debuger block10 data register9.
+ */
+typedef union {
+    struct {
+        /** block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t block10_w9:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w9_reg_t;
+
+
+/** Group: OTP_DEBUG Block10 Word10 Data */
+/** Type of blk10_w10 register
+ *  Otp debuger block10 data register10.
+ */
+typedef union {
+    struct {
+        /** block19_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t block19_w10:32;
+    };
+    uint32_t val;
+} otp_debug_blk10_w10_reg_t;
+
+
+/** Group: OTP_DEBUG Clock_en Configuration Register */
+/** Type of clk register
+ *  Otp debuger clk_en configuration register.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Force clock on for this register file.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} otp_debug_clk_reg_t;
+
+
+/** Group: OTP_DEBUG Apb2otp Enable Singal */
+/** Type of apb2otp_en register
+ *  Otp_debuger apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Debug mode enable signal.
+         */
+        uint32_t apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} otp_debug_apb2otp_en_reg_t;
+
+
+/** Group: OTP_DEBUG Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 539037736;
+         *  Stores otp_debug version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} otp_debug_date_reg_t;
+
+
+typedef struct otp_debug_dev_t {
+    volatile otp_debug_wr_dis_reg_t wr_dis;
+    volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1;
+    volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2;
+    volatile otp_debug_blk0_backup1_w3_reg_t blk0_backup1_w3;
+    volatile otp_debug_blk0_backup1_w4_reg_t blk0_backup1_w4;
+    volatile otp_debug_blk0_backup1_w5_reg_t blk0_backup1_w5;
+    volatile otp_debug_blk0_backup2_w1_reg_t blk0_backup2_w1;
+    volatile otp_debug_blk0_backup2_w2_reg_t blk0_backup2_w2;
+    volatile otp_debug_blk0_backup2_w3_reg_t blk0_backup2_w3;
+    volatile otp_debug_blk0_backup2_w4_reg_t blk0_backup2_w4;
+    volatile otp_debug_blk0_backup2_w5_reg_t blk0_backup2_w5;
+    volatile otp_debug_blk0_backup3_w1_reg_t blk0_backup3_w1;
+    volatile otp_debug_blk0_backup3_w2_reg_t blk0_backup3_w2;
+    volatile otp_debug_blk0_backup3_w3_reg_t blk0_backup3_w3;
+    volatile otp_debug_blk0_backup3_w4_reg_t blk0_backup3_w4;
+    volatile otp_debug_blk0_backup3_w5_reg_t blk0_backup3_w5;
+    volatile otp_debug_blk0_backup4_w1_reg_t blk0_backup4_w1;
+    volatile otp_debug_blk0_backup4_w2_reg_t blk0_backup4_w2;
+    volatile otp_debug_blk0_backup4_w3_reg_t blk0_backup4_w3;
+    volatile otp_debug_blk0_backup4_w4_reg_t blk0_backup4_w4;
+    volatile otp_debug_blk0_backup4_w5_reg_t blk0_backup4_w5;
+    volatile otp_debug_blk1_w1_reg_t blk1_w1;
+    volatile otp_debug_blk1_w2_reg_t blk1_w2;
+    volatile otp_debug_blk1_w3_reg_t blk1_w3;
+    volatile otp_debug_blk1_w4_reg_t blk1_w4;
+    volatile otp_debug_blk1_w5_reg_t blk1_w5;
+    volatile otp_debug_blk1_w6_reg_t blk1_w6;
+    volatile otp_debug_blk1_w7_reg_t blk1_w7;
+    volatile otp_debug_blk1_w8_reg_t blk1_w8;
+    volatile otp_debug_blk1_w9_reg_t blk1_w9;
+    volatile otp_debug_blk2_w1_reg_t blk2_w1;
+    volatile otp_debug_blk2_w2_reg_t blk2_w2;
+    volatile otp_debug_blk2_w3_reg_t blk2_w3;
+    volatile otp_debug_blk2_w4_reg_t blk2_w4;
+    volatile otp_debug_blk2_w5_reg_t blk2_w5;
+    volatile otp_debug_blk2_w6_reg_t blk2_w6;
+    volatile otp_debug_blk2_w7_reg_t blk2_w7;
+    volatile otp_debug_blk2_w8_reg_t blk2_w8;
+    volatile otp_debug_blk2_w9_reg_t blk2_w9;
+    volatile otp_debug_blk2_w10_reg_t blk2_w10;
+    volatile otp_debug_blk2_w11_reg_t blk2_w11;
+    volatile otp_debug_blk3_w1_reg_t blk3_w1;
+    volatile otp_debug_blk3_w2_reg_t blk3_w2;
+    volatile otp_debug_blk3_w3_reg_t blk3_w3;
+    volatile otp_debug_blk3_w4_reg_t blk3_w4;
+    volatile otp_debug_blk3_w5_reg_t blk3_w5;
+    volatile otp_debug_blk3_w6_reg_t blk3_w6;
+    volatile otp_debug_blk3_w7_reg_t blk3_w7;
+    volatile otp_debug_blk3_w8_reg_t blk3_w8;
+    volatile otp_debug_blk3_w9_reg_t blk3_w9;
+    volatile otp_debug_blk3_w10_reg_t blk3_w10;
+    volatile otp_debug_blk3_w11_reg_t blk3_w11;
+    volatile otp_debug_blk4_w1_reg_t blk4_w1;
+    volatile otp_debug_blk4_w2_reg_t blk4_w2;
+    volatile otp_debug_blk4_w3_reg_t blk4_w3;
+    volatile otp_debug_blk4_w4_reg_t blk4_w4;
+    volatile otp_debug_blk4_w5_reg_t blk4_w5;
+    volatile otp_debug_blk4_w6_reg_t blk4_w6;
+    volatile otp_debug_blk4_w7_reg_t blk4_w7;
+    volatile otp_debug_blk4_w8_reg_t blk4_w8;
+    volatile otp_debug_blk4_w9_reg_t blk4_w9;
+    volatile otp_debug_blk4_w10_reg_t blk4_w10;
+    volatile otp_debug_blk4_w11_reg_t blk4_w11;
+    volatile otp_debug_blk5_w1_reg_t blk5_w1;
+    volatile otp_debug_blk5_w2_reg_t blk5_w2;
+    volatile otp_debug_blk5_w3_reg_t blk5_w3;
+    volatile otp_debug_blk5_w4_reg_t blk5_w4;
+    volatile otp_debug_blk5_w5_reg_t blk5_w5;
+    volatile otp_debug_blk5_w6_reg_t blk5_w6;
+    volatile otp_debug_blk5_w7_reg_t blk5_w7;
+    volatile otp_debug_blk5_w8_reg_t blk5_w8;
+    volatile otp_debug_blk5_w9_reg_t blk5_w9;
+    volatile otp_debug_blk5_w10_reg_t blk5_w10;
+    volatile otp_debug_blk5_w11_reg_t blk5_w11;
+    volatile otp_debug_blk6_w1_reg_t blk6_w1;
+    volatile otp_debug_blk6_w2_reg_t blk6_w2;
+    volatile otp_debug_blk6_w3_reg_t blk6_w3;
+    volatile otp_debug_blk6_w4_reg_t blk6_w4;
+    volatile otp_debug_blk6_w5_reg_t blk6_w5;
+    volatile otp_debug_blk6_w6_reg_t blk6_w6;
+    volatile otp_debug_blk6_w7_reg_t blk6_w7;
+    volatile otp_debug_blk6_w8_reg_t blk6_w8;
+    volatile otp_debug_blk6_w9_reg_t blk6_w9;
+    volatile otp_debug_blk6_w10_reg_t blk6_w10;
+    volatile otp_debug_blk6_w11_reg_t blk6_w11;
+    volatile otp_debug_blk7_w1_reg_t blk7_w1;
+    volatile otp_debug_blk7_w2_reg_t blk7_w2;
+    volatile otp_debug_blk7_w3_reg_t blk7_w3;
+    volatile otp_debug_blk7_w4_reg_t blk7_w4;
+    volatile otp_debug_blk7_w5_reg_t blk7_w5;
+    volatile otp_debug_blk7_w6_reg_t blk7_w6;
+    volatile otp_debug_blk7_w7_reg_t blk7_w7;
+    volatile otp_debug_blk7_w8_reg_t blk7_w8;
+    volatile otp_debug_blk7_w9_reg_t blk7_w9;
+    volatile otp_debug_blk7_w10_reg_t blk7_w10;
+    volatile otp_debug_blk7_w11_reg_t blk7_w11;
+    volatile otp_debug_blk8_w1_reg_t blk8_w1;
+    volatile otp_debug_blk8_w2_reg_t blk8_w2;
+    volatile otp_debug_blk8_w3_reg_t blk8_w3;
+    volatile otp_debug_blk8_w4_reg_t blk8_w4;
+    volatile otp_debug_blk8_w5_reg_t blk8_w5;
+    volatile otp_debug_blk8_w6_reg_t blk8_w6;
+    volatile otp_debug_blk8_w7_reg_t blk8_w7;
+    volatile otp_debug_blk8_w8_reg_t blk8_w8;
+    volatile otp_debug_blk8_w9_reg_t blk8_w9;
+    volatile otp_debug_blk8_w10_reg_t blk8_w10;
+    volatile otp_debug_blk8_w11_reg_t blk8_w11;
+    volatile otp_debug_blk9_w1_reg_t blk9_w1;
+    volatile otp_debug_blk9_w2_reg_t blk9_w2;
+    volatile otp_debug_blk9_w3_reg_t blk9_w3;
+    volatile otp_debug_blk9_w4_reg_t blk9_w4;
+    volatile otp_debug_blk9_w5_reg_t blk9_w5;
+    volatile otp_debug_blk9_w6_reg_t blk9_w6;
+    volatile otp_debug_blk9_w7_reg_t blk9_w7;
+    volatile otp_debug_blk9_w8_reg_t blk9_w8;
+    volatile otp_debug_blk9_w9_reg_t blk9_w9;
+    volatile otp_debug_blk9_w10_reg_t blk9_w10;
+    volatile otp_debug_blk9_w11_reg_t blk9_w11;
+    volatile otp_debug_blk10_w1_reg_t blk10_w1;
+    volatile otp_debug_blk10_w2_reg_t blk10_w2;
+    volatile otp_debug_blk10_w3_reg_t blk10_w3;
+    volatile otp_debug_blk10_w4_reg_t blk10_w4;
+    volatile otp_debug_blk10_w5_reg_t blk10_w5;
+    volatile otp_debug_blk10_w6_reg_t blk10_w6;
+    volatile otp_debug_blk10_w7_reg_t blk10_w7;
+    volatile otp_debug_blk10_w8_reg_t blk10_w8;
+    volatile otp_debug_blk10_w9_reg_t blk10_w9;
+    volatile otp_debug_blk10_w10_reg_t blk10_w10;
+    volatile otp_debug_blk10_w11_reg_t blk10_w11;
+    volatile otp_debug_clk_reg_t clk;
+    volatile otp_debug_apb2otp_en_reg_t apb2otp_en;
+    volatile otp_debug_date_reg_t date;
+} otp_debug_dev_t;
+
+extern otp_debug_dev_t OTP_DEBUG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(otp_debug_dev_t) == 0x210, "Invalid size of otp_debug_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/pcr_reg.h b/components/soc/esp32p4/include/soc/pcr_reg.h
new file mode 100644
index 0000000000..7209befa4a
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/pcr_reg.h
@@ -0,0 +1,2065 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PCR_UART0_CONF_REG register
+ *  UART0 configuration register
+ */
+#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
+/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uart0 apb clock
+ */
+#define PCR_UART0_CLK_EN    (BIT(0))
+#define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
+#define PCR_UART0_CLK_EN_V  0x00000001U
+#define PCR_UART0_CLK_EN_S  0
+/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uart0 module
+ */
+#define PCR_UART0_RST_EN    (BIT(1))
+#define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
+#define PCR_UART0_RST_EN_V  0x00000001U
+#define PCR_UART0_RST_EN_S  1
+
+/** PCR_UART0_SCLK_CONF_REG register
+ *  UART0_SCLK configuration register
+ */
+#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
+/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_A    0x0000003FU
+#define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
+#define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
+#define PCR_UART0_SCLK_DIV_A_S  0
+/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_B    0x0000003FU
+#define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
+#define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
+#define PCR_UART0_SCLK_DIV_B_S  6
+/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
+#define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
+#define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_UART0_SCLK_DIV_NUM_S  12
+/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_UART0_SCLK_SEL    0x00000003U
+#define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
+#define PCR_UART0_SCLK_SEL_V  0x00000003U
+#define PCR_UART0_SCLK_SEL_S  20
+/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable uart0 function clock
+ */
+#define PCR_UART0_SCLK_EN    (BIT(22))
+#define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
+#define PCR_UART0_SCLK_EN_V  0x00000001U
+#define PCR_UART0_SCLK_EN_S  22
+
+/** PCR_UART0_PD_CTRL_REG register
+ *  UART0 power control register
+ */
+#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
+/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power down UART0 memory.
+ */
+#define PCR_UART0_MEM_FORCE_PU    (BIT(1))
+#define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
+#define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
+#define PCR_UART0_MEM_FORCE_PU_S  1
+/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power up UART0 memory.
+ */
+#define PCR_UART0_MEM_FORCE_PD    (BIT(2))
+#define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
+#define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
+#define PCR_UART0_MEM_FORCE_PD_S  2
+
+/** PCR_UART1_CONF_REG register
+ *  UART1 configuration register
+ */
+#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
+/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uart1 apb clock
+ */
+#define PCR_UART1_CLK_EN    (BIT(0))
+#define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
+#define PCR_UART1_CLK_EN_V  0x00000001U
+#define PCR_UART1_CLK_EN_S  0
+/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uart1 module
+ */
+#define PCR_UART1_RST_EN    (BIT(1))
+#define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
+#define PCR_UART1_RST_EN_V  0x00000001U
+#define PCR_UART1_RST_EN_S  1
+
+/** PCR_UART1_SCLK_CONF_REG register
+ *  UART1_SCLK configuration register
+ */
+#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
+/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_A    0x0000003FU
+#define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
+#define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
+#define PCR_UART1_SCLK_DIV_A_S  0
+/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_B    0x0000003FU
+#define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
+#define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
+#define PCR_UART1_SCLK_DIV_B_S  6
+/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
+#define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
+#define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_UART1_SCLK_DIV_NUM_S  12
+/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_UART1_SCLK_SEL    0x00000003U
+#define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
+#define PCR_UART1_SCLK_SEL_V  0x00000003U
+#define PCR_UART1_SCLK_SEL_S  20
+/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable uart0 function clock
+ */
+#define PCR_UART1_SCLK_EN    (BIT(22))
+#define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
+#define PCR_UART1_SCLK_EN_V  0x00000001U
+#define PCR_UART1_SCLK_EN_S  22
+
+/** PCR_UART1_PD_CTRL_REG register
+ *  UART1 power control register
+ */
+#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
+/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power down UART1 memory.
+ */
+#define PCR_UART1_MEM_FORCE_PU    (BIT(1))
+#define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
+#define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
+#define PCR_UART1_MEM_FORCE_PU_S  1
+/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power up UART1 memory.
+ */
+#define PCR_UART1_MEM_FORCE_PD    (BIT(2))
+#define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
+#define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
+#define PCR_UART1_MEM_FORCE_PD_S  2
+
+/** PCR_MSPI_CONF_REG register
+ *  MSPI configuration register
+ */
+#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
+/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable mspi clock, include mspi pll clock
+ */
+#define PCR_MSPI_CLK_EN    (BIT(0))
+#define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
+#define PCR_MSPI_CLK_EN_V  0x00000001U
+#define PCR_MSPI_CLK_EN_S  0
+/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset mspi module
+ */
+#define PCR_MSPI_RST_EN    (BIT(1))
+#define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
+#define PCR_MSPI_RST_EN_V  0x00000001U
+#define PCR_MSPI_RST_EN_S  1
+/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable mspi pll clock
+ */
+#define PCR_MSPI_PLL_CLK_EN    (BIT(2))
+#define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
+#define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
+#define PCR_MSPI_PLL_CLK_EN_S  2
+
+/** PCR_MSPI_CLK_CONF_REG register
+ *  MSPI_CLK configuration register
+ */
+#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
+/** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
+ *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  low-speed clock-source such as XTAL/FOSC.
+ */
+#define PCR_MSPI_FAST_LS_DIV_NUM    0x000000FFU
+#define PCR_MSPI_FAST_LS_DIV_NUM_M  (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S)
+#define PCR_MSPI_FAST_LS_DIV_NUM_V  0x000000FFU
+#define PCR_MSPI_FAST_LS_DIV_NUM_S  0
+/** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
+ *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  high-speed clock-source such as SPLL.
+ */
+#define PCR_MSPI_FAST_HS_DIV_NUM    0x000000FFU
+#define PCR_MSPI_FAST_HS_DIV_NUM_M  (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S)
+#define PCR_MSPI_FAST_HS_DIV_NUM_V  0x000000FFU
+#define PCR_MSPI_FAST_HS_DIV_NUM_S  8
+
+/** PCR_I2C_CONF_REG register
+ *  I2C configuration register
+ */
+#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20)
+/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable i2c apb clock
+ */
+#define PCR_I2C_CLK_EN    (BIT(0))
+#define PCR_I2C_CLK_EN_M  (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S)
+#define PCR_I2C_CLK_EN_V  0x00000001U
+#define PCR_I2C_CLK_EN_S  0
+/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset i2c module
+ */
+#define PCR_I2C_RST_EN    (BIT(1))
+#define PCR_I2C_RST_EN_M  (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S)
+#define PCR_I2C_RST_EN_V  0x00000001U
+#define PCR_I2C_RST_EN_S  1
+
+/** PCR_I2C_SCLK_CONF_REG register
+ *  I2C_SCLK configuration register
+ */
+#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
+/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C_SCLK_DIV_A    0x0000003FU
+#define PCR_I2C_SCLK_DIV_A_M  (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S)
+#define PCR_I2C_SCLK_DIV_A_V  0x0000003FU
+#define PCR_I2C_SCLK_DIV_A_S  0
+/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C_SCLK_DIV_B    0x0000003FU
+#define PCR_I2C_SCLK_DIV_B_M  (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S)
+#define PCR_I2C_SCLK_DIV_B_V  0x0000003FU
+#define PCR_I2C_SCLK_DIV_B_S  6
+/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C_SCLK_DIV_NUM    0x000000FFU
+#define PCR_I2C_SCLK_DIV_NUM_M  (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S)
+#define PCR_I2C_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_I2C_SCLK_DIV_NUM_S  12
+/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_I2C_SCLK_SEL    (BIT(20))
+#define PCR_I2C_SCLK_SEL_M  (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S)
+#define PCR_I2C_SCLK_SEL_V  0x00000001U
+#define PCR_I2C_SCLK_SEL_S  20
+/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2c function clock
+ */
+#define PCR_I2C_SCLK_EN    (BIT(22))
+#define PCR_I2C_SCLK_EN_M  (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S)
+#define PCR_I2C_SCLK_EN_V  0x00000001U
+#define PCR_I2C_SCLK_EN_S  22
+
+/** PCR_UHCI_CONF_REG register
+ *  UHCI configuration register
+ */
+#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28)
+/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uhci clock
+ */
+#define PCR_UHCI_CLK_EN    (BIT(0))
+#define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
+#define PCR_UHCI_CLK_EN_V  0x00000001U
+#define PCR_UHCI_CLK_EN_S  0
+/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uhci module
+ */
+#define PCR_UHCI_RST_EN    (BIT(1))
+#define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
+#define PCR_UHCI_RST_EN_V  0x00000001U
+#define PCR_UHCI_RST_EN_S  1
+
+/** PCR_RMT_CONF_REG register
+ *  RMT configuration register
+ */
+#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c)
+/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable rmt apb clock
+ */
+#define PCR_RMT_CLK_EN    (BIT(0))
+#define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
+#define PCR_RMT_CLK_EN_V  0x00000001U
+#define PCR_RMT_CLK_EN_S  0
+/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset rmt module
+ */
+#define PCR_RMT_RST_EN    (BIT(1))
+#define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
+#define PCR_RMT_RST_EN_V  0x00000001U
+#define PCR_RMT_RST_EN_S  1
+
+/** PCR_RMT_SCLK_CONF_REG register
+ *  RMT_SCLK configuration register
+ */
+#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30)
+/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_A    0x0000003FU
+#define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
+#define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
+#define PCR_RMT_SCLK_DIV_A_S  0
+/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_B    0x0000003FU
+#define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
+#define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
+#define PCR_RMT_SCLK_DIV_B_S  6
+/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
+ *  The integral part of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
+#define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
+#define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_RMT_SCLK_DIV_NUM_S  12
+/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
+ *  80MHz, 2: FOSC, 3: XTAL.
+ */
+#define PCR_RMT_SCLK_SEL    0x00000003U
+#define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
+#define PCR_RMT_SCLK_SEL_V  0x00000003U
+#define PCR_RMT_SCLK_SEL_S  20
+/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable rmt function clock
+ */
+#define PCR_RMT_SCLK_EN    (BIT(22))
+#define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
+#define PCR_RMT_SCLK_EN_V  0x00000001U
+#define PCR_RMT_SCLK_EN_S  22
+
+/** PCR_LEDC_CONF_REG register
+ *  LEDC configuration register
+ */
+#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34)
+/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ledc apb clock
+ */
+#define PCR_LEDC_CLK_EN    (BIT(0))
+#define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
+#define PCR_LEDC_CLK_EN_V  0x00000001U
+#define PCR_LEDC_CLK_EN_S  0
+/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ledc module
+ */
+#define PCR_LEDC_RST_EN    (BIT(1))
+#define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
+#define PCR_LEDC_RST_EN_V  0x00000001U
+#define PCR_LEDC_RST_EN_S  1
+
+/** PCR_LEDC_SCLK_CONF_REG register
+ *  LEDC_SCLK configuration register
+ */
+#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
+/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+ *  80MHz, 2: FOSC, 3: XTAL.
+ */
+#define PCR_LEDC_SCLK_SEL    0x00000003U
+#define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
+#define PCR_LEDC_SCLK_SEL_V  0x00000003U
+#define PCR_LEDC_SCLK_SEL_S  20
+/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable ledc function clock
+ */
+#define PCR_LEDC_SCLK_EN    (BIT(22))
+#define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
+#define PCR_LEDC_SCLK_EN_V  0x00000001U
+#define PCR_LEDC_SCLK_EN_S  22
+
+/** PCR_TIMERGROUP0_CONF_REG register
+ *  TIMERGROUP0 configuration register
+ */
+#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c)
+/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable timer_group0 apb clock
+ */
+#define PCR_TG0_CLK_EN    (BIT(0))
+#define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
+#define PCR_TG0_CLK_EN_V  0x00000001U
+#define PCR_TG0_CLK_EN_S  0
+/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset timer_group0 module
+ */
+#define PCR_TG0_RST_EN    (BIT(1))
+#define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
+#define PCR_TG0_RST_EN_V  0x00000001U
+#define PCR_TG0_RST_EN_S  1
+
+/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
+ *  TIMERGROUP0_TIMER_CLK configuration register
+ */
+#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
+/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG0_TIMER_CLK_SEL    0x00000003U
+#define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
+#define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
+#define PCR_TG0_TIMER_CLK_SEL_S  20
+/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 timer clock
+ */
+#define PCR_TG0_TIMER_CLK_EN    (BIT(22))
+#define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
+#define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
+#define PCR_TG0_TIMER_CLK_EN_S  22
+
+/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
+ *  TIMERGROUP0_WDT_CLK configuration register
+ */
+#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44)
+/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG0_WDT_CLK_SEL    0x00000003U
+#define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
+#define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
+#define PCR_TG0_WDT_CLK_SEL_S  20
+/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 wdt clock
+ */
+#define PCR_TG0_WDT_CLK_EN    (BIT(22))
+#define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
+#define PCR_TG0_WDT_CLK_EN_V  0x00000001U
+#define PCR_TG0_WDT_CLK_EN_S  22
+
+/** PCR_TIMERGROUP1_CONF_REG register
+ *  TIMERGROUP1 configuration register
+ */
+#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48)
+/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable timer_group1 apb clock
+ */
+#define PCR_TG1_CLK_EN    (BIT(0))
+#define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
+#define PCR_TG1_CLK_EN_V  0x00000001U
+#define PCR_TG1_CLK_EN_S  0
+/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset timer_group1 module
+ */
+#define PCR_TG1_RST_EN    (BIT(1))
+#define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
+#define PCR_TG1_RST_EN_V  0x00000001U
+#define PCR_TG1_RST_EN_S  1
+
+/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
+ *  TIMERGROUP1_TIMER_CLK configuration register
+ */
+#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c)
+/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG1_TIMER_CLK_SEL    0x00000003U
+#define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
+#define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
+#define PCR_TG1_TIMER_CLK_SEL_S  20
+/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group1 timer clock
+ */
+#define PCR_TG1_TIMER_CLK_EN    (BIT(22))
+#define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
+#define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
+#define PCR_TG1_TIMER_CLK_EN_S  22
+
+/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
+ *  TIMERGROUP1_WDT_CLK configuration register
+ */
+#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50)
+/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG1_WDT_CLK_SEL    0x00000003U
+#define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
+#define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
+#define PCR_TG1_WDT_CLK_SEL_S  20
+/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 wdt clock
+ */
+#define PCR_TG1_WDT_CLK_EN    (BIT(22))
+#define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
+#define PCR_TG1_WDT_CLK_EN_V  0x00000001U
+#define PCR_TG1_WDT_CLK_EN_S  22
+
+/** PCR_SYSTIMER_CONF_REG register
+ *  SYSTIMER configuration register
+ */
+#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54)
+/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable systimer apb clock
+ */
+#define PCR_SYSTIMER_CLK_EN    (BIT(0))
+#define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
+#define PCR_SYSTIMER_CLK_EN_V  0x00000001U
+#define PCR_SYSTIMER_CLK_EN_S  0
+/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset systimer module
+ */
+#define PCR_SYSTIMER_RST_EN    (BIT(1))
+#define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
+#define PCR_SYSTIMER_RST_EN_V  0x00000001U
+#define PCR_SYSTIMER_RST_EN_S  1
+
+/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
+ *  SYSTIMER_FUNC_CLK configuration register
+ */
+#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58)
+/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
+#define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
+#define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
+/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable systimer function clock
+ */
+#define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
+#define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
+#define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
+#define PCR_SYSTIMER_FUNC_CLK_EN_S  22
+
+/** PCR_TWAI0_CONF_REG register
+ *  TWAI0 configuration register
+ */
+#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c)
+/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable twai0 apb clock
+ */
+#define PCR_TWAI0_CLK_EN    (BIT(0))
+#define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
+#define PCR_TWAI0_CLK_EN_V  0x00000001U
+#define PCR_TWAI0_CLK_EN_S  0
+/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset twai0 module
+ */
+#define PCR_TWAI0_RST_EN    (BIT(1))
+#define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
+#define PCR_TWAI0_RST_EN_V  0x00000001U
+#define PCR_TWAI0_RST_EN_S  1
+
+/** PCR_TWAI0_FUNC_CLK_CONF_REG register
+ *  TWAI0_FUNC_CLK configuration register
+ */
+#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
+/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
+#define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
+#define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_TWAI0_FUNC_CLK_SEL_S  20
+/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable twai0 function clock
+ */
+#define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
+#define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
+#define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
+#define PCR_TWAI0_FUNC_CLK_EN_S  22
+
+/** PCR_TWAI1_CONF_REG register
+ *  TWAI1 configuration register
+ */
+#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64)
+/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable twai1 apb clock
+ */
+#define PCR_TWAI1_CLK_EN    (BIT(0))
+#define PCR_TWAI1_CLK_EN_M  (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S)
+#define PCR_TWAI1_CLK_EN_V  0x00000001U
+#define PCR_TWAI1_CLK_EN_S  0
+/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset twai1 module
+ */
+#define PCR_TWAI1_RST_EN    (BIT(1))
+#define PCR_TWAI1_RST_EN_M  (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S)
+#define PCR_TWAI1_RST_EN_V  0x00000001U
+#define PCR_TWAI1_RST_EN_S  1
+
+/** PCR_TWAI1_FUNC_CLK_CONF_REG register
+ *  TWAI1_FUNC_CLK configuration register
+ */
+#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
+/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_TWAI1_FUNC_CLK_SEL    (BIT(20))
+#define PCR_TWAI1_FUNC_CLK_SEL_M  (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S)
+#define PCR_TWAI1_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_TWAI1_FUNC_CLK_SEL_S  20
+/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable twai1 function clock
+ */
+#define PCR_TWAI1_FUNC_CLK_EN    (BIT(22))
+#define PCR_TWAI1_FUNC_CLK_EN_M  (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S)
+#define PCR_TWAI1_FUNC_CLK_EN_V  0x00000001U
+#define PCR_TWAI1_FUNC_CLK_EN_S  22
+
+/** PCR_I2S_CONF_REG register
+ *  I2S configuration register
+ */
+#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
+/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable i2s apb clock
+ */
+#define PCR_I2S_CLK_EN    (BIT(0))
+#define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
+#define PCR_I2S_CLK_EN_V  0x00000001U
+#define PCR_I2S_CLK_EN_S  0
+/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset i2s module
+ */
+#define PCR_I2S_RST_EN    (BIT(1))
+#define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
+#define PCR_I2S_RST_EN_V  0x00000001U
+#define PCR_I2S_RST_EN_S  1
+
+/** PCR_I2S_TX_CLKM_CONF_REG register
+ *  I2S_TX_CLKM configuration register
+ */
+#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
+/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
+ *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
+ *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
+ *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+ *  (n+1)-div] + y * (n+1)-div.
+ */
+#define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
+#define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
+#define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_I2S_TX_CLKM_DIV_NUM_S  12
+/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+ *  I2S_MCLK_in.
+ */
+#define PCR_I2S_TX_CLKM_SEL    0x00000003U
+#define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
+#define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
+#define PCR_I2S_TX_CLKM_SEL_S  20
+/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2s_tx function clock
+ */
+#define PCR_I2S_TX_CLKM_EN    (BIT(22))
+#define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
+#define PCR_I2S_TX_CLKM_EN_V  0x00000001U
+#define PCR_I2S_TX_CLKM_EN_S  22
+
+/** PCR_I2S_TX_CLKM_DIV_CONF_REG register
+ *  I2S_TX_CLKM_DIV configuration register
+ */
+#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
+/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Z is (a-b).
+ */
+#define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
+#define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Z_S  0
+/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
+#define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Y_S  9
+/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
+#define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_X_S  18
+/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_YN1 is 1.
+ */
+#define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
+#define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
+#define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
+#define PCR_I2S_TX_CLKM_DIV_YN1_S  27
+
+/** PCR_I2S_RX_CLKM_CONF_REG register
+ *  I2S_RX_CLKM configuration register
+ */
+#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
+/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
+ *  Integral I2S clock divider value
+ */
+#define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
+#define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
+#define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_I2S_RX_CLKM_DIV_NUM_S  12
+/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+ */
+#define PCR_I2S_RX_CLKM_SEL    0x00000003U
+#define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
+#define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
+#define PCR_I2S_RX_CLKM_SEL_S  20
+/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2s_rx function clock
+ */
+#define PCR_I2S_RX_CLKM_EN    (BIT(22))
+#define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
+#define PCR_I2S_RX_CLKM_EN_V  0x00000001U
+#define PCR_I2S_RX_CLKM_EN_S  22
+/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
+ *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
+ */
+#define PCR_I2S_MCLK_SEL    (BIT(23))
+#define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
+#define PCR_I2S_MCLK_SEL_V  0x00000001U
+#define PCR_I2S_MCLK_SEL_S  23
+
+/** PCR_I2S_RX_CLKM_DIV_CONF_REG register
+ *  I2S_RX_CLKM_DIV configuration register
+ */
+#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
+/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Z is (a-b).
+ */
+#define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
+#define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Z_S  0
+/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
+#define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Y_S  9
+/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
+#define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_X_S  18
+/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_YN1 is 1.
+ */
+#define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
+#define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
+#define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
+#define PCR_I2S_RX_CLKM_DIV_YN1_S  27
+
+/** PCR_SARADC_CONF_REG register
+ *  SARADC configuration register
+ */
+#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
+/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  no use
+ */
+#define PCR_SARADC_CLK_EN    (BIT(0))
+#define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
+#define PCR_SARADC_CLK_EN_V  0x00000001U
+#define PCR_SARADC_CLK_EN_S  0
+/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset function_register of saradc module
+ */
+#define PCR_SARADC_RST_EN    (BIT(1))
+#define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
+#define PCR_SARADC_RST_EN_V  0x00000001U
+#define PCR_SARADC_RST_EN_S  1
+/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable saradc apb clock
+ */
+#define PCR_SARADC_REG_CLK_EN    (BIT(2))
+#define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
+#define PCR_SARADC_REG_CLK_EN_V  0x00000001U
+#define PCR_SARADC_REG_CLK_EN_S  2
+/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  Set 0 to reset apb_register of saradc module
+ */
+#define PCR_SARADC_REG_RST_EN    (BIT(3))
+#define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
+#define PCR_SARADC_REG_RST_EN_V  0x00000001U
+#define PCR_SARADC_REG_RST_EN_S  3
+
+/** PCR_SARADC_CLKM_CONF_REG register
+ *  SARADC_CLKM configuration register
+ */
+#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
+/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_A    0x0000003FU
+#define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
+#define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
+#define PCR_SARADC_CLKM_DIV_A_S  0
+/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_B    0x0000003FU
+#define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
+#define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
+#define PCR_SARADC_CLKM_DIV_B_S  6
+/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
+ *  The integral part of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
+#define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
+#define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_SARADC_CLKM_DIV_NUM_S  12
+/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_SARADC_CLKM_SEL    0x00000003U
+#define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
+#define PCR_SARADC_CLKM_SEL_V  0x00000003U
+#define PCR_SARADC_CLKM_SEL_S  20
+/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable saradc function clock
+ */
+#define PCR_SARADC_CLKM_EN    (BIT(22))
+#define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
+#define PCR_SARADC_CLKM_EN_V  0x00000001U
+#define PCR_SARADC_CLKM_EN_S  22
+
+/** PCR_TSENS_CLK_CONF_REG register
+ *  TSENS_CLK configuration register
+ */
+#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
+/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
+ */
+#define PCR_TSENS_CLK_SEL    (BIT(20))
+#define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
+#define PCR_TSENS_CLK_SEL_V  0x00000001U
+#define PCR_TSENS_CLK_SEL_S  20
+/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable tsens clock
+ */
+#define PCR_TSENS_CLK_EN    (BIT(22))
+#define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
+#define PCR_TSENS_CLK_EN_V  0x00000001U
+#define PCR_TSENS_CLK_EN_S  22
+/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
+ *  Set 0 to reset tsens module
+ */
+#define PCR_TSENS_RST_EN    (BIT(23))
+#define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
+#define PCR_TSENS_RST_EN_V  0x00000001U
+#define PCR_TSENS_RST_EN_S  23
+
+/** PCR_USB_DEVICE_CONF_REG register
+ *  USB_DEVICE configuration register
+ */
+#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
+/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable usb_device clock
+ */
+#define PCR_USB_DEVICE_CLK_EN    (BIT(0))
+#define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
+#define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
+#define PCR_USB_DEVICE_CLK_EN_S  0
+/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset usb_device module
+ */
+#define PCR_USB_DEVICE_RST_EN    (BIT(1))
+#define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
+#define PCR_USB_DEVICE_RST_EN_V  0x00000001U
+#define PCR_USB_DEVICE_RST_EN_S  1
+
+/** PCR_INTMTX_CONF_REG register
+ *  INTMTX configuration register
+ */
+#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
+/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable intmtx clock
+ */
+#define PCR_INTMTX_CLK_EN    (BIT(0))
+#define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
+#define PCR_INTMTX_CLK_EN_V  0x00000001U
+#define PCR_INTMTX_CLK_EN_S  0
+/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset intmtx module
+ */
+#define PCR_INTMTX_RST_EN    (BIT(1))
+#define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
+#define PCR_INTMTX_RST_EN_V  0x00000001U
+#define PCR_INTMTX_RST_EN_S  1
+
+/** PCR_PCNT_CONF_REG register
+ *  PCNT configuration register
+ */
+#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
+/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable pcnt clock
+ */
+#define PCR_PCNT_CLK_EN    (BIT(0))
+#define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
+#define PCR_PCNT_CLK_EN_V  0x00000001U
+#define PCR_PCNT_CLK_EN_S  0
+/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset pcnt module
+ */
+#define PCR_PCNT_RST_EN    (BIT(1))
+#define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
+#define PCR_PCNT_RST_EN_V  0x00000001U
+#define PCR_PCNT_RST_EN_S  1
+
+/** PCR_ETM_CONF_REG register
+ *  ETM configuration register
+ */
+#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
+/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable etm clock
+ */
+#define PCR_ETM_CLK_EN    (BIT(0))
+#define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
+#define PCR_ETM_CLK_EN_V  0x00000001U
+#define PCR_ETM_CLK_EN_S  0
+/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset etm module
+ */
+#define PCR_ETM_RST_EN    (BIT(1))
+#define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
+#define PCR_ETM_RST_EN_V  0x00000001U
+#define PCR_ETM_RST_EN_S  1
+
+/** PCR_PWM_CONF_REG register
+ *  PWM configuration register
+ */
+#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
+/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable pwm clock
+ */
+#define PCR_PWM_CLK_EN    (BIT(0))
+#define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
+#define PCR_PWM_CLK_EN_V  0x00000001U
+#define PCR_PWM_CLK_EN_S  0
+/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset pwm module
+ */
+#define PCR_PWM_RST_EN    (BIT(1))
+#define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
+#define PCR_PWM_RST_EN_V  0x00000001U
+#define PCR_PWM_RST_EN_S  1
+
+/** PCR_PWM_CLK_CONF_REG register
+ *  PWM_CLK configuration register
+ */
+#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
+/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
+ *  The integral part of the frequency divider factor of the pwm function clock.
+ */
+#define PCR_PWM_DIV_NUM    0x000000FFU
+#define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
+#define PCR_PWM_DIV_NUM_V  0x000000FFU
+#define PCR_PWM_DIV_NUM_S  12
+/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+ *  160MHz, 2: XTAL, 3: FOSC.
+ */
+#define PCR_PWM_CLKM_SEL    0x00000003U
+#define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
+#define PCR_PWM_CLKM_SEL_V  0x00000003U
+#define PCR_PWM_CLKM_SEL_S  20
+/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  set this field as 1 to activate pwm clkm.
+ */
+#define PCR_PWM_CLKM_EN    (BIT(22))
+#define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
+#define PCR_PWM_CLKM_EN_V  0x00000001U
+#define PCR_PWM_CLKM_EN_S  22
+
+/** PCR_PARL_IO_CONF_REG register
+ *  PARL_IO configuration register
+ */
+#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
+/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable parl apb clock
+ */
+#define PCR_PARL_CLK_EN    (BIT(0))
+#define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
+#define PCR_PARL_CLK_EN_V  0x00000001U
+#define PCR_PARL_CLK_EN_S  0
+/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset parl apb reg
+ */
+#define PCR_PARL_RST_EN    (BIT(1))
+#define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
+#define PCR_PARL_RST_EN_V  0x00000001U
+#define PCR_PARL_RST_EN_S  1
+
+/** PCR_PARL_CLK_RX_CONF_REG register
+ *  PARL_CLK_RX configuration register
+ */
+#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
+/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  The integral part of the frequency divider factor of the parl rx clock.
+ */
+#define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
+#define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
+#define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
+#define PCR_PARL_CLK_RX_DIV_NUM_S  0
+/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  user clock from pad.
+ */
+#define PCR_PARL_CLK_RX_SEL    0x00000003U
+#define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
+#define PCR_PARL_CLK_RX_SEL_V  0x00000003U
+#define PCR_PARL_CLK_RX_SEL_S  16
+/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
+ *  Set 1 to enable parl rx clock
+ */
+#define PCR_PARL_CLK_RX_EN    (BIT(18))
+#define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
+#define PCR_PARL_CLK_RX_EN_V  0x00000001U
+#define PCR_PARL_CLK_RX_EN_S  18
+/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
+ *  Set 0 to reset parl rx module
+ */
+#define PCR_PARL_RX_RST_EN    (BIT(19))
+#define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
+#define PCR_PARL_RX_RST_EN_V  0x00000001U
+#define PCR_PARL_RX_RST_EN_S  19
+
+/** PCR_PARL_CLK_TX_CONF_REG register
+ *  PARL_CLK_TX configuration register
+ */
+#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
+/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  The integral part of the frequency divider factor of the parl tx clock.
+ */
+#define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
+#define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
+#define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
+#define PCR_PARL_CLK_TX_DIV_NUM_S  0
+/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  user clock from pad.
+ */
+#define PCR_PARL_CLK_TX_SEL    0x00000003U
+#define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
+#define PCR_PARL_CLK_TX_SEL_V  0x00000003U
+#define PCR_PARL_CLK_TX_SEL_S  16
+/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
+ *  Set 1 to enable parl tx clock
+ */
+#define PCR_PARL_CLK_TX_EN    (BIT(18))
+#define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
+#define PCR_PARL_CLK_TX_EN_V  0x00000001U
+#define PCR_PARL_CLK_TX_EN_S  18
+/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
+ *  Set 0 to reset parl tx module
+ */
+#define PCR_PARL_TX_RST_EN    (BIT(19))
+#define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
+#define PCR_PARL_TX_RST_EN_V  0x00000001U
+#define PCR_PARL_TX_RST_EN_S  19
+
+/** PCR_SDIO_SLAVE_CONF_REG register
+ *  SDIO_SLAVE configuration register
+ */
+#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0)
+/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable sdio_slave clock
+ */
+#define PCR_SDIO_SLAVE_CLK_EN    (BIT(0))
+#define PCR_SDIO_SLAVE_CLK_EN_M  (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S)
+#define PCR_SDIO_SLAVE_CLK_EN_V  0x00000001U
+#define PCR_SDIO_SLAVE_CLK_EN_S  0
+/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset sdio_slave module
+ */
+#define PCR_SDIO_SLAVE_RST_EN    (BIT(1))
+#define PCR_SDIO_SLAVE_RST_EN_M  (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S)
+#define PCR_SDIO_SLAVE_RST_EN_V  0x00000001U
+#define PCR_SDIO_SLAVE_RST_EN_S  1
+
+/** PCR_PVT_MONITOR_CONF_REG register
+ *  PVT_MONITOR configuration register
+ */
+#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4)
+/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable apb clock of pvt module
+ */
+#define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
+#define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
+#define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_CLK_EN_S  0
+/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset all pvt monitor module
+ */
+#define PCR_PVT_MONITOR_RST_EN    (BIT(1))
+#define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
+#define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_RST_EN_S  1
+/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable function clock of modem pvt module
+ */
+#define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
+/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to enable function clock of cpu pvt module
+ */
+#define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
+/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Set 1 to enable function clock of hp_peri pvt module
+ */
+#define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
+
+/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
+ *  PVT_MONITOR function clock configuration register
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8)
+/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
+ *  The integral part of the frequency divider factor of the pvt_monitor function clock.
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
+/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
+ *  divided by 3.
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
+/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable source clock of pvt sitex
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
+
+/** PCR_GDMA_CONF_REG register
+ *  GDMA configuration register
+ */
+#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc)
+/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable gdma clock
+ */
+#define PCR_GDMA_CLK_EN    (BIT(0))
+#define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
+#define PCR_GDMA_CLK_EN_V  0x00000001U
+#define PCR_GDMA_CLK_EN_S  0
+/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset gdma module
+ */
+#define PCR_GDMA_RST_EN    (BIT(1))
+#define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
+#define PCR_GDMA_RST_EN_V  0x00000001U
+#define PCR_GDMA_RST_EN_S  1
+
+/** PCR_SPI2_CONF_REG register
+ *  SPI2 configuration register
+ */
+#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0)
+/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable spi2 apb clock
+ */
+#define PCR_SPI2_CLK_EN    (BIT(0))
+#define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
+#define PCR_SPI2_CLK_EN_V  0x00000001U
+#define PCR_SPI2_CLK_EN_S  0
+/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset spi2 module
+ */
+#define PCR_SPI2_RST_EN    (BIT(1))
+#define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
+#define PCR_SPI2_RST_EN_V  0x00000001U
+#define PCR_SPI2_RST_EN_S  1
+
+/** PCR_SPI2_CLKM_CONF_REG register
+ *  SPI2_CLKM configuration register
+ */
+#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4)
+/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_SPI2_CLKM_SEL    0x00000003U
+#define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
+#define PCR_SPI2_CLKM_SEL_V  0x00000003U
+#define PCR_SPI2_CLKM_SEL_S  20
+/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable spi2 function clock
+ */
+#define PCR_SPI2_CLKM_EN    (BIT(22))
+#define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
+#define PCR_SPI2_CLKM_EN_V  0x00000001U
+#define PCR_SPI2_CLKM_EN_S  22
+
+/** PCR_AES_CONF_REG register
+ *  AES configuration register
+ */
+#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8)
+/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable aes clock
+ */
+#define PCR_AES_CLK_EN    (BIT(0))
+#define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
+#define PCR_AES_CLK_EN_V  0x00000001U
+#define PCR_AES_CLK_EN_S  0
+/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset aes module
+ */
+#define PCR_AES_RST_EN    (BIT(1))
+#define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
+#define PCR_AES_RST_EN_V  0x00000001U
+#define PCR_AES_RST_EN_S  1
+
+/** PCR_SHA_CONF_REG register
+ *  SHA configuration register
+ */
+#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
+/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable sha clock
+ */
+#define PCR_SHA_CLK_EN    (BIT(0))
+#define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
+#define PCR_SHA_CLK_EN_V  0x00000001U
+#define PCR_SHA_CLK_EN_S  0
+/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset sha module
+ */
+#define PCR_SHA_RST_EN    (BIT(1))
+#define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
+#define PCR_SHA_RST_EN_V  0x00000001U
+#define PCR_SHA_RST_EN_S  1
+
+/** PCR_RSA_CONF_REG register
+ *  RSA configuration register
+ */
+#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0)
+/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable rsa clock
+ */
+#define PCR_RSA_CLK_EN    (BIT(0))
+#define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
+#define PCR_RSA_CLK_EN_V  0x00000001U
+#define PCR_RSA_CLK_EN_S  0
+/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset rsa module
+ */
+#define PCR_RSA_RST_EN    (BIT(1))
+#define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
+#define PCR_RSA_RST_EN_V  0x00000001U
+#define PCR_RSA_RST_EN_S  1
+
+/** PCR_RSA_PD_CTRL_REG register
+ *  RSA power control register
+ */
+#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4)
+/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down rsa internal memory.
+ */
+#define PCR_RSA_MEM_PD    (BIT(0))
+#define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
+#define PCR_RSA_MEM_PD_V  0x00000001U
+#define PCR_RSA_MEM_PD_S  0
+/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up rsa internal memory
+ */
+#define PCR_RSA_MEM_FORCE_PU    (BIT(1))
+#define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
+#define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
+#define PCR_RSA_MEM_FORCE_PU_S  1
+/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down rsa internal memory.
+ */
+#define PCR_RSA_MEM_FORCE_PD    (BIT(2))
+#define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
+#define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
+#define PCR_RSA_MEM_FORCE_PD_S  2
+
+/** PCR_ECC_CONF_REG register
+ *  ECC configuration register
+ */
+#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8)
+/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ecc clock
+ */
+#define PCR_ECC_CLK_EN    (BIT(0))
+#define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
+#define PCR_ECC_CLK_EN_V  0x00000001U
+#define PCR_ECC_CLK_EN_S  0
+/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ecc module
+ */
+#define PCR_ECC_RST_EN    (BIT(1))
+#define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
+#define PCR_ECC_RST_EN_V  0x00000001U
+#define PCR_ECC_RST_EN_S  1
+
+/** PCR_ECC_PD_CTRL_REG register
+ *  ECC power control register
+ */
+#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc)
+/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down ecc internal memory.
+ */
+#define PCR_ECC_MEM_PD    (BIT(0))
+#define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
+#define PCR_ECC_MEM_PD_V  0x00000001U
+#define PCR_ECC_MEM_PD_S  0
+/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up ecc internal memory
+ */
+#define PCR_ECC_MEM_FORCE_PU    (BIT(1))
+#define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
+#define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
+#define PCR_ECC_MEM_FORCE_PU_S  1
+/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down ecc internal memory.
+ */
+#define PCR_ECC_MEM_FORCE_PD    (BIT(2))
+#define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
+#define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
+#define PCR_ECC_MEM_FORCE_PD_S  2
+
+/** PCR_DS_CONF_REG register
+ *  DS configuration register
+ */
+#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0)
+/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ds clock
+ */
+#define PCR_DS_CLK_EN    (BIT(0))
+#define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
+#define PCR_DS_CLK_EN_V  0x00000001U
+#define PCR_DS_CLK_EN_S  0
+/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ds module
+ */
+#define PCR_DS_RST_EN    (BIT(1))
+#define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
+#define PCR_DS_RST_EN_V  0x00000001U
+#define PCR_DS_RST_EN_S  1
+
+/** PCR_HMAC_CONF_REG register
+ *  HMAC configuration register
+ */
+#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4)
+/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable hmac clock
+ */
+#define PCR_HMAC_CLK_EN    (BIT(0))
+#define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
+#define PCR_HMAC_CLK_EN_V  0x00000001U
+#define PCR_HMAC_CLK_EN_S  0
+/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset hmac module
+ */
+#define PCR_HMAC_RST_EN    (BIT(1))
+#define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
+#define PCR_HMAC_RST_EN_V  0x00000001U
+#define PCR_HMAC_RST_EN_S  1
+
+/** PCR_IOMUX_CONF_REG register
+ *  IOMUX configuration register
+ */
+#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
+/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable iomux apb clock
+ */
+#define PCR_IOMUX_CLK_EN    (BIT(0))
+#define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
+#define PCR_IOMUX_CLK_EN_V  0x00000001U
+#define PCR_IOMUX_CLK_EN_S  0
+/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset iomux module
+ */
+#define PCR_IOMUX_RST_EN    (BIT(1))
+#define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
+#define PCR_IOMUX_RST_EN_V  0x00000001U
+#define PCR_IOMUX_RST_EN_S  1
+
+/** PCR_IOMUX_CLK_CONF_REG register
+ *  IOMUX_CLK configuration register
+ */
+#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
+/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
+#define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
+#define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
+#define PCR_IOMUX_FUNC_CLK_SEL_S  20
+/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable iomux function clock
+ */
+#define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
+#define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
+#define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
+#define PCR_IOMUX_FUNC_CLK_EN_S  22
+
+/** PCR_MEM_MONITOR_CONF_REG register
+ *  MEM_MONITOR configuration register
+ */
+#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
+/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable mem_monitor clock
+ */
+#define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
+#define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
+#define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
+#define PCR_MEM_MONITOR_CLK_EN_S  0
+/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset mem_monitor module
+ */
+#define PCR_MEM_MONITOR_RST_EN    (BIT(1))
+#define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
+#define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
+#define PCR_MEM_MONITOR_RST_EN_S  1
+
+/** PCR_REGDMA_CONF_REG register
+ *  REGDMA configuration register
+ */
+#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
+/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable regdma clock
+ */
+#define PCR_REGDMA_CLK_EN    (BIT(0))
+#define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
+#define PCR_REGDMA_CLK_EN_V  0x00000001U
+#define PCR_REGDMA_CLK_EN_S  0
+/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset regdma module
+ */
+#define PCR_REGDMA_RST_EN    (BIT(1))
+#define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
+#define PCR_REGDMA_RST_EN_V  0x00000001U
+#define PCR_REGDMA_RST_EN_S  1
+
+/** PCR_RETENTION_CONF_REG register
+ *  retention configuration register
+ */
+#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8)
+/** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable retention clock
+ */
+#define PCR_RETENTION_CLK_EN    (BIT(0))
+#define PCR_RETENTION_CLK_EN_M  (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S)
+#define PCR_RETENTION_CLK_EN_V  0x00000001U
+#define PCR_RETENTION_CLK_EN_S  0
+/** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset retention module
+ */
+#define PCR_RETENTION_RST_EN    (BIT(1))
+#define PCR_RETENTION_RST_EN_M  (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S)
+#define PCR_RETENTION_RST_EN_V  0x00000001U
+#define PCR_RETENTION_RST_EN_S  1
+
+/** PCR_TRACE_CONF_REG register
+ *  TRACE configuration register
+ */
+#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc)
+/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable trace clock
+ */
+#define PCR_TRACE_CLK_EN    (BIT(0))
+#define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
+#define PCR_TRACE_CLK_EN_V  0x00000001U
+#define PCR_TRACE_CLK_EN_S  0
+/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset trace module
+ */
+#define PCR_TRACE_RST_EN    (BIT(1))
+#define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
+#define PCR_TRACE_RST_EN_V  0x00000001U
+#define PCR_TRACE_RST_EN_S  1
+
+/** PCR_ASSIST_CONF_REG register
+ *  ASSIST configuration register
+ */
+#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100)
+/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable assist clock
+ */
+#define PCR_ASSIST_CLK_EN    (BIT(0))
+#define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
+#define PCR_ASSIST_CLK_EN_V  0x00000001U
+#define PCR_ASSIST_CLK_EN_S  0
+/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset assist module
+ */
+#define PCR_ASSIST_RST_EN    (BIT(1))
+#define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
+#define PCR_ASSIST_RST_EN_V  0x00000001U
+#define PCR_ASSIST_RST_EN_S  1
+
+/** PCR_CACHE_CONF_REG register
+ *  CACHE configuration register
+ */
+#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104)
+/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable cache clock
+ */
+#define PCR_CACHE_CLK_EN    (BIT(0))
+#define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
+#define PCR_CACHE_CLK_EN_V  0x00000001U
+#define PCR_CACHE_CLK_EN_S  0
+/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset cache module
+ */
+#define PCR_CACHE_RST_EN    (BIT(1))
+#define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
+#define PCR_CACHE_RST_EN_V  0x00000001U
+#define PCR_CACHE_RST_EN_S  1
+
+/** PCR_MODEM_APB_CONF_REG register
+ *  MODEM_APB configuration register
+ */
+#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108)
+/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
+ */
+#define PCR_MODEM_APB_CLK_EN    (BIT(0))
+#define PCR_MODEM_APB_CLK_EN_M  (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S)
+#define PCR_MODEM_APB_CLK_EN_V  0x00000001U
+#define PCR_MODEM_APB_CLK_EN_S  0
+/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this file as 1 to reset modem-subsystem.
+ */
+#define PCR_MODEM_RST_EN    (BIT(1))
+#define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
+#define PCR_MODEM_RST_EN_V  0x00000001U
+#define PCR_MODEM_RST_EN_S  1
+
+/** PCR_TIMEOUT_CONF_REG register
+ *  TIMEOUT configuration register
+ */
+#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c)
+/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset cpu_peri timeout module
+ */
+#define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
+#define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
+#define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
+#define PCR_CPU_TIMEOUT_RST_EN_S  1
+/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
+ */
+#define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
+#define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
+#define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
+#define PCR_HP_TIMEOUT_RST_EN_S  2
+
+/** PCR_SYSCLK_CONF_REG register
+ *  SYSCLK configuration register
+ */
+#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110)
+/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
+ *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
+ *  clock-source such as XTAL/FOSC.
+ */
+#define PCR_LS_DIV_NUM    0x000000FFU
+#define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
+#define PCR_LS_DIV_NUM_V  0x000000FFU
+#define PCR_LS_DIV_NUM_S  0
+/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
+ *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
+ */
+#define PCR_HS_DIV_NUM    0x000000FFU
+#define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
+#define PCR_HS_DIV_NUM_V  0x000000FFU
+#define PCR_HS_DIV_NUM_S  8
+/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
+ */
+#define PCR_SOC_CLK_SEL    0x00000003U
+#define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
+#define PCR_SOC_CLK_SEL_V  0x00000003U
+#define PCR_SOC_CLK_SEL_S  16
+/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40;
+ *  This field indicates the frequency(MHz) of XTAL.
+ */
+#define PCR_CLK_XTAL_FREQ    0x0000007FU
+#define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
+#define PCR_CLK_XTAL_FREQ_V  0x0000007FU
+#define PCR_CLK_XTAL_FREQ_S  24
+
+/** PCR_CPU_WAITI_CONF_REG register
+ *  CPU_WAITI configuration register
+ */
+#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114)
+/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
+ *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
+ */
+#define PCR_CPUPERIOD_SEL    0x00000003U
+#define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
+#define PCR_CPUPERIOD_SEL_V  0x00000003U
+#define PCR_CPUPERIOD_SEL_S  0
+/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
+ *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
+ */
+#define PCR_PLL_FREQ_SEL    (BIT(2))
+#define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
+#define PCR_PLL_FREQ_SEL_V  0x00000001U
+#define PCR_PLL_FREQ_SEL_S  2
+/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to force cpu_waiti_clk enable.
+ */
+#define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
+#define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
+#define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
+/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
+ *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+ *  will close
+ */
+#define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
+#define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define PCR_CPU_WAITI_DELAY_NUM_S  4
+
+/** PCR_CPU_FREQ_CONF_REG register
+ *  CPU_FREQ configuration register
+ */
+#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
+/** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+ *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
+ */
+#define PCR_CPU_LS_DIV_NUM    0x000000FFU
+#define PCR_CPU_LS_DIV_NUM_M  (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S)
+#define PCR_CPU_LS_DIV_NUM_V  0x000000FFU
+#define PCR_CPU_LS_DIV_NUM_S  0
+/** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
+ *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
+ */
+#define PCR_CPU_HS_DIV_NUM    0x000000FFU
+#define PCR_CPU_HS_DIV_NUM_M  (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S)
+#define PCR_CPU_HS_DIV_NUM_V  0x000000FFU
+#define PCR_CPU_HS_DIV_NUM_S  8
+/** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0;
+ *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
+ *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
+ */
+#define PCR_CPU_HS_120M_FORCE    (BIT(16))
+#define PCR_CPU_HS_120M_FORCE_M  (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S)
+#define PCR_CPU_HS_120M_FORCE_V  0x00000001U
+#define PCR_CPU_HS_120M_FORCE_S  16
+
+/** PCR_AHB_FREQ_CONF_REG register
+ *  AHB_FREQ configuration register
+ */
+#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
+/** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
+ *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+ *  low-speed clock-source such as XTAL/FOSC, and should be used together with
+ *  PCR_CPU_LS_DIV_NUM.
+ */
+#define PCR_AHB_LS_DIV_NUM    0x000000FFU
+#define PCR_AHB_LS_DIV_NUM_M  (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S)
+#define PCR_AHB_LS_DIV_NUM_V  0x000000FFU
+#define PCR_AHB_LS_DIV_NUM_S  0
+/** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
+ *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
+ *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
+ */
+#define PCR_AHB_HS_DIV_NUM    0x000000FFU
+#define PCR_AHB_HS_DIV_NUM_M  (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S)
+#define PCR_AHB_HS_DIV_NUM_V  0x000000FFU
+#define PCR_AHB_HS_DIV_NUM_S  8
+
+/** PCR_APB_FREQ_CONF_REG register
+ *  APB_FREQ configuration register
+ */
+#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120)
+/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
+ *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
+ *  recover to the previous frequency when a new access appears on apb-bus. Set as one
+ *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
+ *  that enable this function will reduce performance. Users can set this field as zero
+ *  to disable the auto-decrease-apb-freq function. By default, this function is
+ *  disable.
+ */
+#define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
+#define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
+#define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
+#define PCR_APB_DECREASE_DIV_NUM_S  0
+/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+ *  div1(default)/div2/div4 of clk_ahb.
+ */
+#define PCR_APB_DIV_NUM    0x000000FFU
+#define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
+#define PCR_APB_DIV_NUM_V  0x000000FFU
+#define PCR_APB_DIV_NUM_S  8
+
+/** PCR_SYSCLK_FREQ_QUERY_0_REG register
+ *  SYSCLK frequency query 0 register
+ */
+#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124)
+/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20;
+ *  This field indicates the frequency(MHz) of FOSC.
+ */
+#define PCR_FOSC_FREQ    0x000000FFU
+#define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
+#define PCR_FOSC_FREQ_V  0x000000FFU
+#define PCR_FOSC_FREQ_S  0
+/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480;
+ *  This field indicates the frequency(MHz) of SPLL.
+ */
+#define PCR_PLL_FREQ    0x000003FFU
+#define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
+#define PCR_PLL_FREQ_V  0x000003FFU
+#define PCR_PLL_FREQ_S  8
+
+/** PCR_PLL_DIV_CLK_EN_REG register
+ *  SPLL DIV clock-gating configuration register
+ */
+#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128)
+/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
+ *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_240M_CLK_EN    (BIT(0))
+#define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
+#define PCR_PLL_240M_CLK_EN_V  0x00000001U
+#define PCR_PLL_240M_CLK_EN_S  0
+/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
+ *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_160M_CLK_EN    (BIT(1))
+#define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
+#define PCR_PLL_160M_CLK_EN_V  0x00000001U
+#define PCR_PLL_160M_CLK_EN_S  1
+/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
+ *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_120M_CLK_EN    (BIT(2))
+#define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
+#define PCR_PLL_120M_CLK_EN_V  0x00000001U
+#define PCR_PLL_120M_CLK_EN_S  2
+/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
+ *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_80M_CLK_EN    (BIT(3))
+#define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
+#define PCR_PLL_80M_CLK_EN_V  0x00000001U
+#define PCR_PLL_80M_CLK_EN_S  3
+/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
+ *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_48M_CLK_EN    (BIT(4))
+#define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
+#define PCR_PLL_48M_CLK_EN_V  0x00000001U
+#define PCR_PLL_48M_CLK_EN_S  4
+/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
+ *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_40M_CLK_EN    (BIT(5))
+#define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
+#define PCR_PLL_40M_CLK_EN_V  0x00000001U
+#define PCR_PLL_40M_CLK_EN_S  5
+/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
+ *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_20M_CLK_EN    (BIT(6))
+#define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
+#define PCR_PLL_20M_CLK_EN_V  0x00000001U
+#define PCR_PLL_20M_CLK_EN_S  6
+
+/** PCR_CTRL_CLK_OUT_EN_REG register
+ *  CLK_OUT_EN configuration register
+ */
+#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c)
+/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable 20m clock
+ */
+#define PCR_CLK20_OEN    (BIT(0))
+#define PCR_CLK20_OEN_M  (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S)
+#define PCR_CLK20_OEN_V  0x00000001U
+#define PCR_CLK20_OEN_S  0
+/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1;
+ *  Set 1 to enable 22m clock
+ */
+#define PCR_CLK22_OEN    (BIT(1))
+#define PCR_CLK22_OEN_M  (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S)
+#define PCR_CLK22_OEN_V  0x00000001U
+#define PCR_CLK22_OEN_S  1
+/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable 44m clock
+ */
+#define PCR_CLK44_OEN    (BIT(2))
+#define PCR_CLK44_OEN_M  (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S)
+#define PCR_CLK44_OEN_V  0x00000001U
+#define PCR_CLK44_OEN_S  2
+/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to enable bb clock
+ */
+#define PCR_CLK_BB_OEN    (BIT(3))
+#define PCR_CLK_BB_OEN_M  (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S)
+#define PCR_CLK_BB_OEN_V  0x00000001U
+#define PCR_CLK_BB_OEN_S  3
+/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1;
+ *  Set 1 to enable 80m clock
+ */
+#define PCR_CLK80_OEN    (BIT(4))
+#define PCR_CLK80_OEN_M  (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S)
+#define PCR_CLK80_OEN_V  0x00000001U
+#define PCR_CLK80_OEN_S  4
+/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1;
+ *  Set 1 to enable 160m clock
+ */
+#define PCR_CLK160_OEN    (BIT(5))
+#define PCR_CLK160_OEN_M  (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S)
+#define PCR_CLK160_OEN_V  0x00000001U
+#define PCR_CLK160_OEN_S  5
+/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1;
+ *  Set 1 to enable 320m clock
+ */
+#define PCR_CLK_320M_OEN    (BIT(6))
+#define PCR_CLK_320M_OEN_M  (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S)
+#define PCR_CLK_320M_OEN_V  0x00000001U
+#define PCR_CLK_320M_OEN_S  6
+/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define PCR_CLK_ADC_INF_OEN    (BIT(7))
+#define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
+#define PCR_CLK_ADC_INF_OEN_V  0x00000001U
+#define PCR_CLK_ADC_INF_OEN_S  7
+/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define PCR_CLK_DAC_CPU_OEN    (BIT(8))
+#define PCR_CLK_DAC_CPU_OEN_M  (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S)
+#define PCR_CLK_DAC_CPU_OEN_V  0x00000001U
+#define PCR_CLK_DAC_CPU_OEN_S  8
+/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1;
+ *  Set 1 to enable 40x_bb clock
+ */
+#define PCR_CLK40X_BB_OEN    (BIT(9))
+#define PCR_CLK40X_BB_OEN_M  (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S)
+#define PCR_CLK40X_BB_OEN_V  0x00000001U
+#define PCR_CLK40X_BB_OEN_S  9
+/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1;
+ *  Set 1 to enable xtal clock
+ */
+#define PCR_CLK_XTAL_OEN    (BIT(10))
+#define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
+#define PCR_CLK_XTAL_OEN_V  0x00000001U
+#define PCR_CLK_XTAL_OEN_S  10
+
+/** PCR_CTRL_TICK_CONF_REG register
+ *  TICK configuration register
+ */
+#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130)
+/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
+ *  ******* Description ***********
+ */
+#define PCR_XTAL_TICK_NUM    0x000000FFU
+#define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
+#define PCR_XTAL_TICK_NUM_V  0x000000FFU
+#define PCR_XTAL_TICK_NUM_S  0
+/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
+ *  ******* Description ***********
+ */
+#define PCR_FOSC_TICK_NUM    0x000000FFU
+#define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
+#define PCR_FOSC_TICK_NUM_V  0x000000FFU
+#define PCR_FOSC_TICK_NUM_S  8
+/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
+ *  ******* Description ***********
+ */
+#define PCR_TICK_ENABLE    (BIT(16))
+#define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
+#define PCR_TICK_ENABLE_V  0x00000001U
+#define PCR_TICK_ENABLE_S  16
+/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
+ *  ******* Description ***********
+ */
+#define PCR_RST_TICK_CNT    (BIT(17))
+#define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
+#define PCR_RST_TICK_CNT_V  0x00000001U
+#define PCR_RST_TICK_CNT_S  17
+
+/** PCR_CTRL_32K_CONF_REG register
+ *  32KHz clock configuration register
+ */
+#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134)
+/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and
+ *  timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+ */
+#define PCR_32K_SEL    0x00000003U
+#define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
+#define PCR_32K_SEL_V  0x00000003U
+#define PCR_32K_SEL_S  0
+
+/** PCR_SRAM_POWER_CONF_REG register
+ *  HP SRAM/ROM configuration register
+ */
+#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138)
+/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15;
+ *  Set this bit to force power up SRAM
+ */
+#define PCR_SRAM_FORCE_PU    0x0000000FU
+#define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
+#define PCR_SRAM_FORCE_PU_V  0x0000000FU
+#define PCR_SRAM_FORCE_PU_S  0
+/** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0;
+ *  Set this bit to force power down SRAM.
+ */
+#define PCR_SRAM_FORCE_PD    0x0000000FU
+#define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
+#define PCR_SRAM_FORCE_PD_V  0x0000000FU
+#define PCR_SRAM_FORCE_PD_S  4
+/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
+ *  gate-clock will be used when accessing the SRAM.
+ */
+#define PCR_SRAM_CLKGATE_FORCE_ON    0x0000000FU
+#define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
+#define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000000FU
+#define PCR_SRAM_CLKGATE_FORCE_ON_S  8
+/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7;
+ *  Set this bit to force power up ROM
+ */
+#define PCR_ROM_FORCE_PU    0x00000007U
+#define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
+#define PCR_ROM_FORCE_PU_V  0x00000007U
+#define PCR_ROM_FORCE_PU_S  12
+/** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0;
+ *  Set this bit to force power down ROM.
+ */
+#define PCR_ROM_FORCE_PD    0x00000007U
+#define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
+#define PCR_ROM_FORCE_PD_V  0x00000007U
+#define PCR_ROM_FORCE_PD_S  15
+/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
+ *  gate-clock will be used when accessing the ROM.
+ */
+#define PCR_ROM_CLKGATE_FORCE_ON    0x00000007U
+#define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
+#define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000007U
+#define PCR_ROM_CLKGATE_FORCE_ON_S  18
+
+/** PCR_RESET_EVENT_BYPASS_REG register
+ *  reset event bypass backdoor configuration register
+ */
+#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
+/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
+ *  This field is used to control reset event relationship for
+ *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
+ *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
+ *  will not only be reset by power-reset, but also some reset event.
+ */
+#define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
+#define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
+#define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
+#define PCR_RESET_EVENT_BYPASS_APM_S  0
+/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  This field is used to control reset event relationship for system-bus. 1: system
+ *  bus (including arbiter/router) will only be reset by power-reset. some reset event
+ *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
+ *  power-reset, but also some reset event.
+ */
+#define PCR_RESET_EVENT_BYPASS    (BIT(1))
+#define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
+#define PCR_RESET_EVENT_BYPASS_V  0x00000001U
+#define PCR_RESET_EVENT_BYPASS_S  1
+
+/** PCR_FPGA_DEBUG_REG register
+ *  fpga debug register
+ */
+#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
+/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Only used in fpga debug.
+ */
+#define PCR_FPGA_DEBUG    0xFFFFFFFFU
+#define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
+#define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
+#define PCR_FPGA_DEBUG_S  0
+
+/** PCR_CLOCK_GATE_REG register
+ *  PCR clock gating configure register
+ */
+#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
+/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to force on clock gating.
+ */
+#define PCR_CLK_EN    (BIT(0))
+#define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
+#define PCR_CLK_EN_V  0x00000001U
+#define PCR_CLK_EN_S  0
+
+/** PCR_DATE_REG register
+ *  Date register.
+ */
+#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
+/** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496;
+ *  PCR version information.
+ */
+#define PCR_DATE    0x0FFFFFFFU
+#define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
+#define PCR_DATE_V  0x0FFFFFFFU
+#define PCR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/periph_defs.h b/components/soc/esp32p4/include/soc/periph_defs.h
new file mode 100644
index 0000000000..2d6c1eaf8c
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/periph_defs.h
@@ -0,0 +1,223 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PERIPH_MSPI_MODULE                      = 0,
+    PERIPH_DUALMSPI_MODULE,
+    PERIPH_EMAC_MODULE,
+    PERIPH_MIPI_DSI_MODULE,
+    PERIPH_MIPI_CSI_MODULE,
+    PERIPH_I2C0_MODULE,
+    PERIPH_I2C1_MODULE,
+    PERIPH_I2S0_MODULE,
+    PERIPH_I2S1_MODULE,
+    PERIPH_I2S2_MODULE,
+
+    PERIPH_LCD_MODULE                       = 10,
+    PERIPH_UART0_MODULE,
+    PERIPH_UART1_MODULE,
+    PERIPH_UART2_MODULE,
+    PERIPH_UART3_MODULE,
+    PERIPH_UART4_MODULE,
+    PERIPH_TWAI0_MODULE,
+    PERIPH_TWAI1_MODULE,
+    PERIPH_TWAI2_MODULE,
+    PERIPH_GPSPI_MODULE,
+
+    PERIPH_GPSPI2_MODULE                    = 20,
+    PERIPH_GPSPI3_MODULE,
+    PERIPH_PARLIO_MODULE,
+    PERIPH_I3C_MODULE,
+    PERIPH_CAM_MODULE,
+    PERIPH_MCPWM0_MODULE,
+    PERIPH_MCPWM1_MODULE,
+    PERIPH_TIMG0_MODULE,
+    PERIPH_TIMG1_MODULE,
+    PERIPH_SYSTIMER_MODULE,
+
+    PERIPH_LEDC_MODULE                      = 30,
+    PERIPH_RMT_MODULE,
+    PERIPH_SARADC_MODULE,
+    PERIPH_PVT_MODULE,
+    PERIPH_AES_MODULE,
+    PERIPH_DS_MODULE,
+    PERIPH_ECC_MODULE,
+    PERIPH_HMAC_MODULE,
+    PERIPH_RSA_MODULE,
+    PERIPH_SEC_MODULE,
+
+    PERIPH_SHA_MODULE                       = 40,
+    PERIPH_ECDSA_MODULE,
+    PERIPH_ISP_MODULE,
+    PERIPH_SDMMC_MODULE,
+    PERIPH_GDMA_MODULE,
+    PERIPH_GMAC_MODULE,
+    PERIPH_JPEG_MODULE,
+    PERIPH_DMA2D_MODULE,
+    PERIPH_PPA_MODULE,
+    PERIPH_AHB_PDMA_MODULE,
+    PERIPH_AXI_PDMA_MODULE,
+    PERIPH_UHCI_MODULE,
+    PERIPH_PCNT_MODULE,
+
+    PERIPH_MODULE_MAX
+} periph_module_t;
+
+typedef enum {
+    LP_PERIPH_I2C0_MODULE = 0,
+    LP_PERIPH_UART0_MODULE,
+    LP_PERIPH_MODULE_MAX,
+} lp_periph_module_t;
+
+typedef enum {
+    ETS_LP_RTC_INTR_SOURCE                  = 0,
+    ETS_LP_WDT_INTR_SOURCE,
+    ETS_LP_TIMER_REG0_INTR_SOURCE,
+    ETS_LP_TIMER_REG1_INTR_SOURCE,
+    ETS_MB_HP_INTR_SOURCE,
+    ETS_MB_LP_INTR_SOURCE,
+    ETS_PMU_0_INTR_SOURCE,
+    ETS_PMU_1_INTR_SOURCE,
+    ETS_LP_ANAPERI_INTR_SOURCE,
+    ETS_LP_ADC_INTR_SOURCE,
+    ETS_LP_GPIO_INTR_SOURCE,
+    ETS_LP_I2C_INTR_SOURCE,
+    ETS_LP_I2S_INTR_SOURCE,
+    ETS_LP_SPI_INTR_SOURCE,
+    ETS_LP_TOUCH_INTR_SOURCE,
+    ETS_LP_TSENS_INTR_SOURCE,
+    ETS_LP_UART_INTR_SOURCE,
+    ETS_LP_EFUSE_INTR_SOURCE,
+    ETS_LP_SW_INTR_SOURCE,
+    ETS_LP_SYSREG_INTR_SOURCE,
+    ETS_LP_HUK_INTR_SOURCE,
+    ETS_SYS_ICM_INTR_SOURCE,
+    ETS_USB_DEVICE_INTR_SOURCE,
+    ETS_SDIO_HOST_INTR_SOURCE,
+    ETS_GDMA_INTR_SOURCE,
+    ETS_SPI2_INTR_SOURCE,
+    ETS_SPI3_INTR_SOURCE,
+    ETS_I2S0_INTR_SOURCE,
+    ETS_I2S1_INTR_SOURCE,
+    ETS_I2S2_INTR_SOURCE,
+    ETS_UHCI0_INTR_SOURCE,
+    ETS_UART0_INTR_SOURCE,
+    ETS_UART1_INTR_SOURCE,
+    ETS_UART2_INTR_SOURCE,
+    ETS_UART3_INTR_SOURCE,
+    ETS_UART4_INTR_SOURCE,
+    ETS_LCD_CAM_INTR_SOURCE,
+    ETS_ADC_INTR_SOURCE,
+    ETS_PWM0_INTR_SOURCE,
+    ETS_PWM1_INTR_SOURCE,
+    ETS_CAN0_INTR_SOURCE,
+    ETS_CAN1_INTR_SOURCE,
+    ETS_CAN2_INTR_SOURCE,
+    ETS_RMT_INTR_SOURCE,
+    ETS_I2C0_INTR_SOURCE,
+    ETS_I2C1_INTR_SOURCE,
+    ETS_TIMERGROUP0_T0_INTR_SOURCE,
+    ETS_TIMERGROUP0_T1_INTR_SOURCE,
+    ETS_TIMERGROUP0_WDT_INTR_SOURCE,
+    ETS_TIMERGROUP1_T0_INTR_SOURCE,
+    ETS_TIMERGROUP1_T1_INTR_SOURCE,
+    ETS_TIMERGROUP1_WDT_INTR_SOURCE,
+    ETS_LEDC_INTR_SOURCE,
+    ETS_SYSTIMER_TARGET0_INTR_SOURCE,
+    ETS_SYSTIMER_TARGET1_INTR_SOURCE,
+    ETS_SYSTIMER_TARGET2_INTR_SOURCE,
+    ETS_AHB_PDMA_IN_CH0_INTR_SOURCE,
+    ETS_AHB_PDMA_IN_CH1_INTR_SOURCE,
+    ETS_AHB_PDMA_IN_CH2_INTR_SOURCE,
+    ETS_AHB_PDMA_OUT_CH0_INTR_SOURCE,
+    ETS_AHB_PDMA_OUT_CH1_INTR_SOURCE,
+    ETS_AHB_PDMA_OUT_CH2_INTR_SOURCE,
+    ETS_AXI_PDMA_IN_CH0_INTR_SOURCE,
+    ETS_AXI_PDMA_IN_CH1_INTR_SOURCE,
+    ETS_AXI_PDMA_IN_CH2_INTR_SOURCE,
+    ETS_AXI_PDMA_OUT_CH0_INTR_SOURCE,
+    ETS_AXI_PDMA_OUT_CH1_INTR_SOURCE,
+
+    ETS_AXI_PDMA_OUT_CH2_INTR_SOURCE,
+    ETS_RSA_INTA_SOURCE,
+    ETS_AES_INTR_SOURCE,
+    ETS_SHA_INTR_SOURCE,
+    ETS_ECC_INTR_SOURCE,
+    ETS_ECDSA_INTR_SOURCE,
+    ETS_KM_INTR_SOURCE,
+    ETS_GPIO_INTR0_SOURCE,
+
+    ETS_GPIO_INTR1_SOURCE,
+    ETS_GPIO_INTR2_SOURCE,
+    ETS_GPIO_INTR3_SOURCE,
+    ETS_GPIO_PAD_COMP_INTR_SOURCE,
+    ETS_CPU_INT_FROM_CPU0_INTR_SOURCE,
+    ETS_CPU_INT_FROM_CPU1_INTR_SOURCE,
+    ETS_CPU_INT_FROM_CPU2_INTR_SOURCE,
+    ETS_CPU_INT_FROM_CPU3_INTR_SOURCE,
+    ETS_CACHE_INTR_SOURCE,
+    ETS_MSPI_INTR_SOURCE,
+    ETS_CSI_BRIDGE_INTR_SOURCE,
+
+    ETS_DSI_BRIDGE_INTR_SOURCE,
+    ETS_CSI_INTR_SOURCE,
+    ETS_DSI_INTR_SOURCE,
+    ETS_GMII_PHY_INTR_SOURCE,
+    ETS_LPI_INTR_SOURCE,
+    ETS_PMT_INTR_SOURCE,
+    ETS_SBD_INTR_SOURCE,
+    ETS_USB_OTG_INTR_SOURCE,
+    ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
+
+    ETS_JPEG_INTR_SOURCE,
+    ETS_PPA_INTR_SOURCE,
+    ETS_CORE0_TRACE_INTR_SOURCE,
+    ETS_CORE1_TRACE_INTR_SOURCE,
+    ETS_HP_CORE_CTRL_INTR_SOURCE,
+    ETS_ISP_INTR_SOURCE,
+    ETS_I3C_MST_INTR_SOURCE,
+    ETS_I3C_SLV_INTR_SOURCE,
+    ETS_USB_OTG11_CH0_INTR_SOURCE,
+    ETS_DMA2D_IN_CH0_INTR_SOURCE,
+
+    ETS_DMA2D_IN_CH1_INTR_SOURCE,
+    ETS_DMA2D_OUT_CH0_INTR_SOURCE,
+    ETS_DMA2D_OUT_CH1_INTR_SOURCE,
+    ETS_DMA2D_OUT_CH2_INTR_SOURCE,
+    ETS_PSRAM_MSPI_INTR_SOURCE,
+    ETS_HP_SYSREG_INTR_SOURCE,
+    ETS_PCNT_INTR_SOURCE,
+
+    ETS_HP_PAU_INTR_SOURCE,
+    ETS_HP_PARLIO_RX_INTR_SOURCE,
+    ETS_HP_PARLIO_TX_INTR_SOURCE,
+    ETS_H264_DMA2D_OUT_CH0_INTR_SOURCE,
+    ETS_H264_DMA2D_OUT_CH1_INTR_SOURCE,
+    ETS_H264_DMA2D_OUT_CH2_INTR_SOURCE,
+    ETS_H264_DMA2D_OUT_CH3_INTR_SOURCE,
+    ETS_H264_DMA2D_OUT_CH4_INTR_SOURCE,
+    ETS_H264_DMA2D_IN_CH0_INTR_SOURCE,
+    ETS_H264_DMA2D_IN_CH1_INTR_SOURCE,
+
+    ETS_H264_DMA2D_IN_CH2_INTR_SOURCE,
+    ETS_H264_DMA2D_IN_CH3_INTR_SOURCE,
+    ETS_H264_DMA2D_IN_CH4_INTR_SOURCE,
+    ETS_H264_DMA2D_IN_CH5_INTR_SOURCE,
+    ETS_H264_REG_INTR_SOURCE,
+    ETS_ASSIST_DEBUG_INTR_SOURCE,
+
+    ETS_MAX_INTR_SOURCE,                        /**< number of interrupt sources */
+} periph_interrput_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/plic_reg.h b/components/soc/esp32p4/include/soc/plic_reg.h
new file mode 100644
index 0000000000..3ee0ca70ed
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/plic_reg.h
@@ -0,0 +1,631 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PLIC_MXINT_CONF_REG       ( 0x200013FC )
+#define PLIC_UXINT_CONF_REG       ( 0x200017FC )
+
+#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
+#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
+
+/*PLIC MX*/
+#define PLIC_MXINT_ENABLE_REG          (DR_REG_PLIC_MX_BASE + 0x0)
+/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT_ENABLE    0xFFFFFFFF
+#define PLIC_CPU_MXINT_ENABLE_M  ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S))
+#define PLIC_CPU_MXINT_ENABLE_V  0xFFFFFFFF
+#define PLIC_CPU_MXINT_ENABLE_S  0
+
+#define PLIC_MXINT_TYPE_REG          (DR_REG_PLIC_MX_BASE + 0x4)
+/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT_TYPE    0xFFFFFFFF
+#define PLIC_CPU_MXINT_TYPE_M  ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S))
+#define PLIC_CPU_MXINT_TYPE_V  0xFFFFFFFF
+#define PLIC_CPU_MXINT_TYPE_S  0
+
+#define PLIC_MXINT_CLEAR_REG          (DR_REG_PLIC_MX_BASE + 0x8)
+/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT_CLEAR    0xFFFFFFFF
+#define PLIC_CPU_MXINT_CLEAR_M  ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S))
+#define PLIC_CPU_MXINT_CLEAR_V  0xFFFFFFFF
+#define PLIC_CPU_MXINT_CLEAR_S  0
+
+#define PLIC_EMIP_STATUS_REG          (DR_REG_PLIC_MX_BASE + 0xC)
+/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_EIP_STATUS    0xFFFFFFFF
+#define PLIC_CPU_EIP_STATUS_M  ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
+#define PLIC_CPU_EIP_STATUS_V  0xFFFFFFFF
+#define PLIC_CPU_EIP_STATUS_S  0
+
+#define PLIC_MXINT0_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x10)
+/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT0_PRI    0x0000000F
+#define PLIC_CPU_MXINT0_PRI_M  ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S))
+#define PLIC_CPU_MXINT0_PRI_V  0xF
+#define PLIC_CPU_MXINT0_PRI_S  0
+
+#define PLIC_MXINT1_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x14)
+/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT1_PRI    0x0000000F
+#define PLIC_CPU_MXINT1_PRI_M  ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S))
+#define PLIC_CPU_MXINT1_PRI_V  0xF
+#define PLIC_CPU_MXINT1_PRI_S  0
+
+#define PLIC_MXINT2_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x18)
+/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT2_PRI    0x0000000F
+#define PLIC_CPU_MXINT2_PRI_M  ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S))
+#define PLIC_CPU_MXINT2_PRI_V  0xF
+#define PLIC_CPU_MXINT2_PRI_S  0
+
+#define PLIC_MXINT3_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x1C)
+/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT3_PRI    0x0000000F
+#define PLIC_CPU_MXINT3_PRI_M  ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S))
+#define PLIC_CPU_MXINT3_PRI_V  0xF
+#define PLIC_CPU_MXINT3_PRI_S  0
+
+#define PLIC_MXINT4_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x20)
+/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT4_PRI    0x0000000F
+#define PLIC_CPU_MXINT4_PRI_M  ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S))
+#define PLIC_CPU_MXINT4_PRI_V  0xF
+#define PLIC_CPU_MXINT4_PRI_S  0
+
+#define PLIC_MXINT5_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x24)
+/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT5_PRI    0x0000000F
+#define PLIC_CPU_MXINT5_PRI_M  ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S))
+#define PLIC_CPU_MXINT5_PRI_V  0xF
+#define PLIC_CPU_MXINT5_PRI_S  0
+
+#define PLIC_MXINT6_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x28)
+/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT6_PRI    0x0000000F
+#define PLIC_CPU_MXINT6_PRI_M  ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S))
+#define PLIC_CPU_MXINT6_PRI_V  0xF
+#define PLIC_CPU_MXINT6_PRI_S  0
+
+#define PLIC_MXINT7_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x2C)
+/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT7_PRI    0x0000000F
+#define PLIC_CPU_MXINT7_PRI_M  ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S))
+#define PLIC_CPU_MXINT7_PRI_V  0xF
+#define PLIC_CPU_MXINT7_PRI_S  0
+
+#define PLIC_MXINT8_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x30)
+/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT8_PRI    0x0000000F
+#define PLIC_CPU_MXINT8_PRI_M  ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S))
+#define PLIC_CPU_MXINT8_PRI_V  0xF
+#define PLIC_CPU_MXINT8_PRI_S  0
+
+#define PLIC_MXINT9_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x34)
+/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT9_PRI    0x0000000F
+#define PLIC_CPU_MXINT9_PRI_M  ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S))
+#define PLIC_CPU_MXINT9_PRI_V  0xF
+#define PLIC_CPU_MXINT9_PRI_S  0
+
+#define PLIC_MXINT10_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x38)
+/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT10_PRI    0x0000000F
+#define PLIC_CPU_MXINT10_PRI_M  ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S))
+#define PLIC_CPU_MXINT10_PRI_V  0xF
+#define PLIC_CPU_MXINT10_PRI_S  0
+
+#define PLIC_MXINT11_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x3C)
+/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT11_PRI    0x0000000F
+#define PLIC_CPU_MXINT11_PRI_M  ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S))
+#define PLIC_CPU_MXINT11_PRI_V  0xF
+#define PLIC_CPU_MXINT11_PRI_S  0
+
+#define PLIC_MXINT12_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x40)
+/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT12_PRI    0x0000000F
+#define PLIC_CPU_MXINT12_PRI_M  ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S))
+#define PLIC_CPU_MXINT12_PRI_V  0xF
+#define PLIC_CPU_MXINT12_PRI_S  0
+
+#define PLIC_MXINT13_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x44)
+/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT13_PRI    0x0000000F
+#define PLIC_CPU_MXINT13_PRI_M  ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S))
+#define PLIC_CPU_MXINT13_PRI_V  0xF
+#define PLIC_CPU_MXINT13_PRI_S  0
+
+#define PLIC_MXINT14_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x48)
+/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT14_PRI    0x0000000F
+#define PLIC_CPU_MXINT14_PRI_M  ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S))
+#define PLIC_CPU_MXINT14_PRI_V  0xF
+#define PLIC_CPU_MXINT14_PRI_S  0
+
+#define PLIC_MXINT15_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x4C)
+/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT15_PRI    0x0000000F
+#define PLIC_CPU_MXINT15_PRI_M  ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S))
+#define PLIC_CPU_MXINT15_PRI_V  0xF
+#define PLIC_CPU_MXINT15_PRI_S  0
+
+#define PLIC_MXINT16_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x50)
+/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT16_PRI    0x0000000F
+#define PLIC_CPU_MXINT16_PRI_M  ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S))
+#define PLIC_CPU_MXINT16_PRI_V  0xF
+#define PLIC_CPU_MXINT16_PRI_S  0
+
+#define PLIC_MXINT17_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x54)
+/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT17_PRI    0x0000000F
+#define PLIC_CPU_MXINT17_PRI_M  ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S))
+#define PLIC_CPU_MXINT17_PRI_V  0xF
+#define PLIC_CPU_MXINT17_PRI_S  0
+
+#define PLIC_MXINT18_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x58)
+/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT18_PRI    0x0000000F
+#define PLIC_CPU_MXINT18_PRI_M  ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S))
+#define PLIC_CPU_MXINT18_PRI_V  0xF
+#define PLIC_CPU_MXINT18_PRI_S  0
+
+#define PLIC_MXINT19_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x5C)
+/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT19_PRI    0x0000000F
+#define PLIC_CPU_MXINT19_PRI_M  ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S))
+#define PLIC_CPU_MXINT19_PRI_V  0xF
+#define PLIC_CPU_MXINT19_PRI_S  0
+
+#define PLIC_MXINT20_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x60)
+/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT20_PRI    0x0000000F
+#define PLIC_CPU_MXINT20_PRI_M  ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S))
+#define PLIC_CPU_MXINT20_PRI_V  0xF
+#define PLIC_CPU_MXINT20_PRI_S  0
+
+#define PLIC_MXINT21_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x64)
+/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT21_PRI    0x0000000F
+#define PLIC_CPU_MXINT21_PRI_M  ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S))
+#define PLIC_CPU_MXINT21_PRI_V  0xF
+#define PLIC_CPU_MXINT21_PRI_S  0
+
+#define PLIC_MXINT22_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x68)
+/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT22_PRI    0x0000000F
+#define PLIC_CPU_MXINT22_PRI_M  ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S))
+#define PLIC_CPU_MXINT22_PRI_V  0xF
+#define PLIC_CPU_MXINT22_PRI_S  0
+
+#define PLIC_MXINT23_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x6C)
+/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT23_PRI    0x0000000F
+#define PLIC_CPU_MXINT23_PRI_M  ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S))
+#define PLIC_CPU_MXINT23_PRI_V  0xF
+#define PLIC_CPU_MXINT23_PRI_S  0
+
+#define PLIC_MXINT24_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x70)
+/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT24_PRI    0x0000000F
+#define PLIC_CPU_MXINT24_PRI_M  ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S))
+#define PLIC_CPU_MXINT24_PRI_V  0xF
+#define PLIC_CPU_MXINT24_PRI_S  0
+
+#define PLIC_MXINT25_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x74)
+/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT25_PRI    0x0000000F
+#define PLIC_CPU_MXINT25_PRI_M  ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S))
+#define PLIC_CPU_MXINT25_PRI_V  0xF
+#define PLIC_CPU_MXINT25_PRI_S  0
+
+#define PLIC_MXINT26_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x78)
+/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT26_PRI    0x0000000F
+#define PLIC_CPU_MXINT26_PRI_M  ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S))
+#define PLIC_CPU_MXINT26_PRI_V  0xF
+#define PLIC_CPU_MXINT26_PRI_S  0
+
+#define PLIC_MXINT27_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x7C)
+/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT27_PRI    0x0000000F
+#define PLIC_CPU_MXINT27_PRI_M  ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S))
+#define PLIC_CPU_MXINT27_PRI_V  0xF
+#define PLIC_CPU_MXINT27_PRI_S  0
+
+#define PLIC_MXINT28_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x80)
+/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT28_PRI    0x0000000F
+#define PLIC_CPU_MXINT28_PRI_M  ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S))
+#define PLIC_CPU_MXINT28_PRI_V  0xF
+#define PLIC_CPU_MXINT28_PRI_S  0
+
+#define PLIC_MXINT29_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x84)
+/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT29_PRI    0x0000000F
+#define PLIC_CPU_MXINT29_PRI_M  ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S))
+#define PLIC_CPU_MXINT29_PRI_V  0xF
+#define PLIC_CPU_MXINT29_PRI_S  0
+
+#define PLIC_MXINT30_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x88)
+/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT30_PRI    0x0000000F
+#define PLIC_CPU_MXINT30_PRI_M  ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S))
+#define PLIC_CPU_MXINT30_PRI_V  0xF
+#define PLIC_CPU_MXINT30_PRI_S  0
+
+#define PLIC_MXINT31_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x8C)
+/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT31_PRI    0x0000000F
+#define PLIC_CPU_MXINT31_PRI_M  ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S))
+#define PLIC_CPU_MXINT31_PRI_V  0xF
+#define PLIC_CPU_MXINT31_PRI_S  0
+
+#define PLIC_MXINT_THRESH_REG          (DR_REG_PLIC_MX_BASE + 0x90)
+/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
+/*description: .*/
+#define PLIC_CPU_MXINT_THRESH    0x000000FF
+#define PLIC_CPU_MXINT_THRESH_M  ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S))
+#define PLIC_CPU_MXINT_THRESH_V  0xFF
+#define PLIC_CPU_MXINT_THRESH_S  0
+
+#define PLIC_MXINT_CLAIM_REG         (DR_REG_PLIC_MX_BASE + 0x94)
+/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/
+#define PLIC_CPU_MXINT_CLAIM    0xFFFFFFFF
+#define PLIC_CPU_MXINT_CLAIM_M  ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S))
+#define PLIC_CPU_MXINT_CLAIM_V  0xFFFFFFFF
+#define PLIC_CPU_MXINT_CLAIM_S  0
+
+/*PLIC UX*/
+#define PLIC_UXINT_ENABLE_REG          (DR_REG_PLIC_UX_BASE + 0x0)
+/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT_ENABLE    0xFFFFFFFF
+#define PLIC_CPU_UXINT_ENABLE_M  ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S))
+#define PLIC_CPU_UXINT_ENABLE_V  0xFFFFFFFF
+#define PLIC_CPU_UXINT_ENABLE_S  0
+
+#define PLIC_UXINT_TYPE_REG          (DR_REG_PLIC_UX_BASE + 0x4)
+/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT_TYPE    0xFFFFFFFF
+#define PLIC_CPU_UXINT_TYPE_M  ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S))
+#define PLIC_CPU_UXINT_TYPE_V  0xFFFFFFFF
+#define PLIC_CPU_UXINT_TYPE_S  0
+
+#define PLIC_UXINT_CLEAR_REG          (DR_REG_PLIC_UX_BASE + 0x8)
+/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT_CLEAR    0xFFFFFFFF
+#define PLIC_CPU_UXINT_CLEAR_M  ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S))
+#define PLIC_CPU_UXINT_CLEAR_V  0xFFFFFFFF
+#define PLIC_CPU_UXINT_CLEAR_S  0
+
+#define PLIC_EUIP_STATUS_REG          (DR_REG_PLIC_UX_BASE + 0xC)
+/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define PLIC_CPU_EIP_STATUS    0xFFFFFFFF
+#define PLIC_CPU_EIP_STATUS_M  ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
+#define PLIC_CPU_EIP_STATUS_V  0xFFFFFFFF
+#define PLIC_CPU_EIP_STATUS_S  0
+
+#define PLIC_UXINT0_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x10)
+/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT0_PRI    0x0000000F
+#define PLIC_CPU_UXINT0_PRI_M  ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S))
+#define PLIC_CPU_UXINT0_PRI_V  0xF
+#define PLIC_CPU_UXINT0_PRI_S  0
+
+#define PLIC_UXINT1_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x14)
+/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT1_PRI    0x0000000F
+#define PLIC_CPU_UXINT1_PRI_M  ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S))
+#define PLIC_CPU_UXINT1_PRI_V  0xF
+#define PLIC_CPU_UXINT1_PRI_S  0
+
+#define PLIC_UXINT2_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x18)
+/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT2_PRI    0x0000000F
+#define PLIC_CPU_UXINT2_PRI_M  ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S))
+#define PLIC_CPU_UXINT2_PRI_V  0xF
+#define PLIC_CPU_UXINT2_PRI_S  0
+
+#define PLIC_UXINT3_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x1C)
+/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT3_PRI    0x0000000F
+#define PLIC_CPU_UXINT3_PRI_M  ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S))
+#define PLIC_CPU_UXINT3_PRI_V  0xF
+#define PLIC_CPU_UXINT3_PRI_S  0
+
+#define PLIC_UXINT4_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x20)
+/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT4_PRI    0x0000000F
+#define PLIC_CPU_UXINT4_PRI_M  ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S))
+#define PLIC_CPU_UXINT4_PRI_V  0xF
+#define PLIC_CPU_UXINT4_PRI_S  0
+
+#define PLIC_UXINT5_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x24)
+/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT5_PRI    0x0000000F
+#define PLIC_CPU_UXINT5_PRI_M  ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S))
+#define PLIC_CPU_UXINT5_PRI_V  0xF
+#define PLIC_CPU_UXINT5_PRI_S  0
+
+#define PLIC_UXINT6_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x28)
+/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT6_PRI    0x0000000F
+#define PLIC_CPU_UXINT6_PRI_M  ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S))
+#define PLIC_CPU_UXINT6_PRI_V  0xF
+#define PLIC_CPU_UXINT6_PRI_S  0
+
+#define PLIC_UXINT7_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x2C)
+/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT7_PRI    0x0000000F
+#define PLIC_CPU_UXINT7_PRI_M  ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S))
+#define PLIC_CPU_UXINT7_PRI_V  0xF
+#define PLIC_CPU_UXINT7_PRI_S  0
+
+#define PLIC_UXINT8_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x30)
+/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT8_PRI    0x0000000F
+#define PLIC_CPU_UXINT8_PRI_M  ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S))
+#define PLIC_CPU_UXINT8_PRI_V  0xF
+#define PLIC_CPU_UXINT8_PRI_S  0
+
+#define PLIC_UXINT9_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x34)
+/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT9_PRI    0x0000000F
+#define PLIC_CPU_UXINT9_PRI_M  ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S))
+#define PLIC_CPU_UXINT9_PRI_V  0xF
+#define PLIC_CPU_UXINT9_PRI_S  0
+
+#define PLIC_UXINT10_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x38)
+/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT10_PRI    0x0000000F
+#define PLIC_CPU_UXINT10_PRI_M  ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S))
+#define PLIC_CPU_UXINT10_PRI_V  0xF
+#define PLIC_CPU_UXINT10_PRI_S  0
+
+#define PLIC_UXINT11_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x3C)
+/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT11_PRI    0x0000000F
+#define PLIC_CPU_UXINT11_PRI_M  ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S))
+#define PLIC_CPU_UXINT11_PRI_V  0xF
+#define PLIC_CPU_UXINT11_PRI_S  0
+
+#define PLIC_UXINT12_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x40)
+/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT12_PRI    0x0000000F
+#define PLIC_CPU_UXINT12_PRI_M  ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S))
+#define PLIC_CPU_UXINT12_PRI_V  0xF
+#define PLIC_CPU_UXINT12_PRI_S  0
+
+#define PLIC_UXINT13_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x44)
+/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT13_PRI    0x0000000F
+#define PLIC_CPU_UXINT13_PRI_M  ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S))
+#define PLIC_CPU_UXINT13_PRI_V  0xF
+#define PLIC_CPU_UXINT13_PRI_S  0
+
+#define PLIC_UXINT14_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x48)
+/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT14_PRI    0x0000000F
+#define PLIC_CPU_UXINT14_PRI_M  ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S))
+#define PLIC_CPU_UXINT14_PRI_V  0xF
+#define PLIC_CPU_UXINT14_PRI_S  0
+
+#define PLIC_UXINT15_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x4C)
+/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT15_PRI    0x0000000F
+#define PLIC_CPU_UXINT15_PRI_M  ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S))
+#define PLIC_CPU_UXINT15_PRI_V  0xF
+#define PLIC_CPU_UXINT15_PRI_S  0
+
+#define PLIC_UXINT16_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x50)
+/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT16_PRI    0x0000000F
+#define PLIC_CPU_UXINT16_PRI_M  ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S))
+#define PLIC_CPU_UXINT16_PRI_V  0xF
+#define PLIC_CPU_UXINT16_PRI_S  0
+
+#define PLIC_UXINT17_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x54)
+/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT17_PRI    0x0000000F
+#define PLIC_CPU_UXINT17_PRI_M  ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S))
+#define PLIC_CPU_UXINT17_PRI_V  0xF
+#define PLIC_CPU_UXINT17_PRI_S  0
+
+#define PLIC_UXINT18_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x58)
+/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT18_PRI    0x0000000F
+#define PLIC_CPU_UXINT18_PRI_M  ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S))
+#define PLIC_CPU_UXINT18_PRI_V  0xF
+#define PLIC_CPU_UXINT18_PRI_S  0
+
+#define PLIC_UXINT19_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x5C)
+/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT19_PRI    0x0000000F
+#define PLIC_CPU_UXINT19_PRI_M  ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S))
+#define PLIC_CPU_UXINT19_PRI_V  0xF
+#define PLIC_CPU_UXINT19_PRI_S  0
+
+#define PLIC_UXINT20_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x60)
+/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT20_PRI    0x0000000F
+#define PLIC_CPU_UXINT20_PRI_M  ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S))
+#define PLIC_CPU_UXINT20_PRI_V  0xF
+#define PLIC_CPU_UXINT20_PRI_S  0
+
+#define PLIC_UXINT21_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x64)
+/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT21_PRI    0x0000000F
+#define PLIC_CPU_UXINT21_PRI_M  ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S))
+#define PLIC_CPU_UXINT21_PRI_V  0xF
+#define PLIC_CPU_UXINT21_PRI_S  0
+
+#define PLIC_UXINT22_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x68)
+/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT22_PRI    0x0000000F
+#define PLIC_CPU_UXINT22_PRI_M  ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S))
+#define PLIC_CPU_UXINT22_PRI_V  0xF
+#define PLIC_CPU_UXINT22_PRI_S  0
+
+#define PLIC_UXINT23_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x6C)
+/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT23_PRI    0x0000000F
+#define PLIC_CPU_UXINT23_PRI_M  ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S))
+#define PLIC_CPU_UXINT23_PRI_V  0xF
+#define PLIC_CPU_UXINT23_PRI_S  0
+
+#define PLIC_UXINT24_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x70)
+/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT24_PRI    0x0000000F
+#define PLIC_CPU_UXINT24_PRI_M  ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S))
+#define PLIC_CPU_UXINT24_PRI_V  0xF
+#define PLIC_CPU_UXINT24_PRI_S  0
+
+#define PLIC_UXINT25_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x74)
+/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT25_PRI    0x0000000F
+#define PLIC_CPU_UXINT25_PRI_M  ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S))
+#define PLIC_CPU_UXINT25_PRI_V  0xF
+#define PLIC_CPU_UXINT25_PRI_S  0
+
+#define PLIC_UXINT26_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x78)
+/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT26_PRI    0x0000000F
+#define PLIC_CPU_UXINT26_PRI_M  ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S))
+#define PLIC_CPU_UXINT26_PRI_V  0xF
+#define PLIC_CPU_UXINT26_PRI_S  0
+
+#define PLIC_UXINT27_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x7C)
+/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT27_PRI    0x0000000F
+#define PLIC_CPU_UXINT27_PRI_M  ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S))
+#define PLIC_CPU_UXINT27_PRI_V  0xF
+#define PLIC_CPU_UXINT27_PRI_S  0
+
+#define PLIC_UXINT28_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x80)
+/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT28_PRI    0x0000000F
+#define PLIC_CPU_UXINT28_PRI_M  ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S))
+#define PLIC_CPU_UXINT28_PRI_V  0xF
+#define PLIC_CPU_UXINT28_PRI_S  0
+
+#define PLIC_UXINT29_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x84)
+/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT29_PRI    0x0000000F
+#define PLIC_CPU_UXINT29_PRI_M  ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S))
+#define PLIC_CPU_UXINT29_PRI_V  0xF
+#define PLIC_CPU_UXINT29_PRI_S  0
+
+#define PLIC_UXINT30_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x88)
+/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT30_PRI    0x0000000F
+#define PLIC_CPU_UXINT30_PRI_M  ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S))
+#define PLIC_CPU_UXINT30_PRI_V  0xF
+#define PLIC_CPU_UXINT30_PRI_S  0
+
+#define PLIC_UXINT31_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x8C)
+/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT31_PRI    0x0000000F
+#define PLIC_CPU_UXINT31_PRI_M  ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S))
+#define PLIC_CPU_UXINT31_PRI_V  0xF
+#define PLIC_CPU_UXINT31_PRI_S  0
+
+#define PLIC_UXINT_THRESH_REG          (DR_REG_PLIC_UX_BASE + 0x90)
+/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT_THRESH    0x000000FF
+#define PLIC_CPU_UXINT_THRESH_M  ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S))
+#define PLIC_CPU_UXINT_THRESH_V  0xFF
+#define PLIC_CPU_UXINT_THRESH_S  0
+
+#define PLIC_UXINT_CLAIM_REG         (DR_REG_PLIC_UX_BASE + 0x94)
+/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define PLIC_CPU_UXINT_CLAIM    0xFFFFFFFF
+#define PLIC_CPU_UXINT_CLAIM_M  ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S))
+#define PLIC_CPU_UXINT_CLAIM_V  0xFFFFFFFF
+#define PLIC_CPU_UXINT_CLAIM_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
new file mode 100644
index 0000000000..c4b995c52a
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
@@ -0,0 +1,68 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_ICG_MAP_H_
+#define _SOC_ICG_MAP_H_
+
+#define PMU_ICG_APB_ENA_CAN0                               18
+#define PMU_ICG_APB_ENA_CAN1                               19
+#define PMU_ICG_APB_ENA_GDMA                               1
+#define PMU_ICG_APB_ENA_I2C                                13
+#define PMU_ICG_APB_ENA_I2S                                4
+#define PMU_ICG_APB_ENA_INTMTX                             3
+#define PMU_ICG_APB_ENA_IOMUX                              26
+#define PMU_ICG_APB_ENA_LEDC                               14
+#define PMU_ICG_APB_ENA_MEM_MONITOR                        25
+#define PMU_ICG_APB_ENA_MSPI                               5
+#define PMU_ICG_APB_ENA_PARL                               23
+#define PMU_ICG_APB_ENA_PCNT                               20
+#define PMU_ICG_APB_ENA_PVT_MONITOR                        27
+#define PMU_ICG_APB_ENA_PWM                                21
+#define PMU_ICG_APB_ENA_REGDMA                             24
+#define PMU_ICG_APB_ENA_RMT                                15
+#define PMU_ICG_APB_ENA_SARADC                             9
+#define PMU_ICG_APB_ENA_SEC                                0
+#define PMU_ICG_APB_ENA_SOC_ETM                            22
+#define PMU_ICG_APB_ENA_SPI2                               2
+#define PMU_ICG_APB_ENA_SYSTIMER                           16
+#define PMU_ICG_APB_ENA_TG0                                11
+#define PMU_ICG_APB_ENA_TG1                                12
+#define PMU_ICG_APB_ENA_UART0                              6
+#define PMU_ICG_APB_ENA_UART1                              7
+#define PMU_ICG_APB_ENA_UHCI                               8
+#define PMU_ICG_APB_ENA_USB_DEVICE                         17
+#define PMU_ICG_FUNC_ENA_CAN0                              31
+#define PMU_ICG_FUNC_ENA_CAN1                              30
+#define PMU_ICG_FUNC_ENA_I2C                               29
+#define PMU_ICG_FUNC_ENA_I2S_RX                            2
+#define PMU_ICG_FUNC_ENA_I2S_TX                            7
+#define PMU_ICG_FUNC_ENA_IOMUX                             28
+#define PMU_ICG_FUNC_ENA_LEDC                              27
+#define PMU_ICG_FUNC_ENA_MEM_MONITOR                       10
+#define PMU_ICG_FUNC_ENA_MSPI                              26
+#define PMU_ICG_FUNC_ENA_PARL_RX                           25
+#define PMU_ICG_FUNC_ENA_PARL_TX                           24
+#define PMU_ICG_FUNC_ENA_PVT_MONITOR                       23
+#define PMU_ICG_FUNC_ENA_PWM                               22
+#define PMU_ICG_FUNC_ENA_RMT                               21
+#define PMU_ICG_FUNC_ENA_SARADC                            20
+#define PMU_ICG_FUNC_ENA_SEC                               19
+#define PMU_ICG_FUNC_ENA_SPI2                              1
+#define PMU_ICG_FUNC_ENA_SYSTIMER                          18
+#define PMU_ICG_FUNC_ENA_TG0                               14
+#define PMU_ICG_FUNC_ENA_TG1                               13
+#define PMU_ICG_FUNC_ENA_TSENS                             12
+#define PMU_ICG_FUNC_ENA_UART0                             3
+#define PMU_ICG_FUNC_ENA_UART1                             4
+#define PMU_ICG_FUNC_ENA_USB_DEVICE                        6
+#define PMU_ICG_FUNC_ENA_GDMA                              0
+#define PMU_ICG_FUNC_ENA_SOC_ETM                           16
+#define PMU_ICG_FUNC_ENA_REGDMA                            8
+#define PMU_ICG_FUNC_ENA_RETENTION                         9
+#define PMU_ICG_FUNC_ENA_SDIO_SLAVE                        11
+#define PMU_ICG_FUNC_ENA_UHCI                              5
+#define PMU_ICG_FUNC_ENA_HPCORE                            17
+#define PMU_ICG_FUNC_ENA_HPBUS                             15
+#endif  /* _SOC_ICG_MAP_H_ */
diff --git a/components/soc/esp32p4/include/soc/pwm_reg.h b/components/soc/esp32p4/include/soc/pwm_reg.h
new file mode 100644
index 0000000000..e526c38e60
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/pwm_reg.h
@@ -0,0 +1,4514 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MCPWM_CLK_CFG_REG register
+ *  PWM clock prescaler register.
+ */
+#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0)
+/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
+ *  (PWM_CLK_PRESCALE + 1).
+ */
+#define MCPWM_CLK_PRESCALE    0x000000FFU
+#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
+#define MCPWM_CLK_PRESCALE_V  0x000000FFU
+#define MCPWM_CLK_PRESCALE_S  0
+
+/** MCPWM_TIMER0_CFG0_REG register
+ *  PWM timer0 period and update method configuration register.
+ */
+#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER0_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer0
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer0 period.\\0:
+ *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+ *  zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER0_CFG1_REG register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8)
+/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+ *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+ *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+ *  stops at the next TEP.\\TEP here and below means the event that happens when the
+ *  timer equals to period
+ */
+#define MCPWM_TIMER0_START    0x00000007U
+#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
+#define MCPWM_TIMER0_START_V  0x00000007U
+#define MCPWM_TIMER0_START_S  0
+/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+ *  Decrease mode\\3: Up-down mode
+ */
+#define MCPWM_TIMER0_MOD    0x00000003U
+#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
+#define MCPWM_TIMER0_MOD_V  0x00000003U
+#define MCPWM_TIMER0_MOD_S  3
+
+/** MCPWM_TIMER0_SYNC_REG register
+ *  PWM timer$n sync function configuration register.
+ */
+#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc)
+/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer$n reloading with phase on sync input
+ *  event is enabled.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
+#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
+#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+ *  Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer$n reload on sync event.
+ */
+#define MCPWM_TIMER0_PHASE    0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
+#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_S  4
+/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+ *  Increase\\1: Decrease
+ */
+#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
+#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER0_STATUS_REG register
+ *  PWM timer$n status register.
+ */
+#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10)
+/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer$n counter value.
+ */
+#define MCPWM_TIMER0_VALUE    0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
+#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_S  0
+/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+ */
+#define MCPWM_TIMER0_DIRECTION    (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
+#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_DIRECTION_S  16
+
+/** MCPWM_TIMER1_CFG0_REG register
+ *  PWM timer1 period and update method configuration register.
+ */
+#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER1_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer1
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer1 period.\\0:
+ *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+ *  zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER1_CFG1_REG register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18)
+/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+ *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+ *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+ *  stops at the next TEP.\\TEP here and below means the event that happens when the
+ *  timer equals to period
+ */
+#define MCPWM_TIMER1_START    0x00000007U
+#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
+#define MCPWM_TIMER1_START_V  0x00000007U
+#define MCPWM_TIMER1_START_S  0
+/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+ *  Decrease mode\\3: Up-down mode
+ */
+#define MCPWM_TIMER1_MOD    0x00000003U
+#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
+#define MCPWM_TIMER1_MOD_V  0x00000003U
+#define MCPWM_TIMER1_MOD_S  3
+
+/** MCPWM_TIMER1_SYNC_REG register
+ *  PWM timer$n sync function configuration register.
+ */
+#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c)
+/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer$n reloading with phase on sync input
+ *  event is enabled.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
+#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
+#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+ *  Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer$n reload on sync event.
+ */
+#define MCPWM_TIMER1_PHASE    0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
+#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_S  4
+/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+ *  Increase\\1: Decrease
+ */
+#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
+#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER1_STATUS_REG register
+ *  PWM timer$n status register.
+ */
+#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20)
+/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer$n counter value.
+ */
+#define MCPWM_TIMER1_VALUE    0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
+#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_S  0
+/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+ */
+#define MCPWM_TIMER1_DIRECTION    (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
+#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_DIRECTION_S  16
+
+/** MCPWM_TIMER2_CFG0_REG register
+ *  PWM timer2 period and update method configuration register.
+ */
+#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER2_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer2
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer2 period.\\0:
+ *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+ *  zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER2_CFG1_REG register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28)
+/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+ *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+ *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+ *  stops at the next TEP.\\TEP here and below means the event that happens when the
+ *  timer equals to period
+ */
+#define MCPWM_TIMER2_START    0x00000007U
+#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
+#define MCPWM_TIMER2_START_V  0x00000007U
+#define MCPWM_TIMER2_START_S  0
+/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+ *  Decrease mode\\3: Up-down mode
+ */
+#define MCPWM_TIMER2_MOD    0x00000003U
+#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
+#define MCPWM_TIMER2_MOD_V  0x00000003U
+#define MCPWM_TIMER2_MOD_S  3
+
+/** MCPWM_TIMER2_SYNC_REG register
+ *  PWM timer$n sync function configuration register.
+ */
+#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c)
+/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer$n reloading with phase on sync input
+ *  event is enabled.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
+#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
+#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+ *  Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer$n reload on sync event.
+ */
+#define MCPWM_TIMER2_PHASE    0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
+#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_S  4
+/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+ *  Increase\\1: Decrease
+ */
+#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
+#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER2_STATUS_REG register
+ *  PWM timer$n status register.
+ */
+#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30)
+/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer$n counter value.
+ */
+#define MCPWM_TIMER2_VALUE    0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
+#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_S  0
+/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+ */
+#define MCPWM_TIMER2_DIRECTION    (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
+#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_DIRECTION_S  16
+
+/** MCPWM_TIMER_SYNCI_CFG_REG register
+ *  Synchronization input selection register for PWM timers.
+ */
+#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34)
+/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
+ *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+ *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+ */
+#define MCPWM_TIMER0_SYNCISEL    0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
+#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_S  0
+/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
+ *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
+ *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+ *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+ */
+#define MCPWM_TIMER1_SYNCISEL    0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
+#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
+ *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+ *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+ */
+#define MCPWM_TIMER2_SYNCISEL    0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
+#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
+ *  Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
+ *  Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
+ *  Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+
+/** MCPWM_OPERATOR_TIMERSEL_REG register
+ *  PWM operator's timer select register
+ */
+#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38)
+/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
+ *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
+ *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
+ *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+
+/** MCPWM_GEN0_STMP_CFG_REG register
+ *  Generator0 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 0 time stamp A's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 0 time stamp B's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0:
+ *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+ *  reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0:
+ *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+ *  reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN0_TSTMP_A_REG register
+ *  Generator$n time stamp A's shadow register
+ */
+#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40)
+/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp A's shadow register.
+ */
+#define MCPWM_CMPR0_A    0x0000FFFFU
+#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
+#define MCPWM_CMPR0_A_V  0x0000FFFFU
+#define MCPWM_CMPR0_A_S  0
+
+/** MCPWM_GEN0_TSTMP_B_REG register
+ *  Generator$n time stamp B's shadow register
+ */
+#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44)
+/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp B's shadow register.
+ */
+#define MCPWM_CMPR0_B    0x0000FFFFU
+#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
+#define MCPWM_CMPR0_B_V  0x0000FFFFU
+#define MCPWM_CMPR0_B_S  0
+
+/** MCPWM_GEN0_CFG0_REG register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48)
+/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator $n's active register.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator $n event_t0, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN0_T0_SEL    0x00000007U
+#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
+#define MCPWM_GEN0_T0_SEL_V  0x00000007U
+#define MCPWM_GEN0_T0_SEL_S  4
+/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator $n event_t1, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN0_T1_SEL    0x00000007U
+#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
+#define MCPWM_GEN0_T1_SEL_V  0x00000007U
+#define MCPWM_GEN0_T1_SEL_S  7
+
+/** MCPWM_GEN0_FORCE_REG register
+ *  Generator$n output signal force mode register.
+ */
+#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c)
+/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator$n.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+ *  update. TEA/B here and below means an event generated when the timer's value equals
+ *  to that of register A/B.
+ */
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
+#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
+#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN0_A_REG register
+ *  PWM$n output signal A actions configuration register
+ */
+#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50)
+/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEZ    0x00000003U
+#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
+#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_UTEZ_S  0
+/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEP    0x00000003U
+#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
+#define MCPWM_GEN0_A_UTEP_V  0x00000003U
+#define MCPWM_GEN0_A_UTEP_S  2
+/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEA    0x00000003U
+#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
+#define MCPWM_GEN0_A_UTEA_V  0x00000003U
+#define MCPWM_GEN0_A_UTEA_S  4
+/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEB    0x00000003U
+#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
+#define MCPWM_GEN0_A_UTEB_V  0x00000003U
+#define MCPWM_GEN0_A_UTEB_S  6
+/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UT0    0x00000003U
+#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
+#define MCPWM_GEN0_A_UT0_V  0x00000003U
+#define MCPWM_GEN0_A_UT0_S  8
+/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UT1    0x00000003U
+#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
+#define MCPWM_GEN0_A_UT1_V  0x00000003U
+#define MCPWM_GEN0_A_UT1_S  10
+/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEZ    0x00000003U
+#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
+#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_DTEZ_S  12
+/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEP    0x00000003U
+#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
+#define MCPWM_GEN0_A_DTEP_V  0x00000003U
+#define MCPWM_GEN0_A_DTEP_S  14
+/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEA    0x00000003U
+#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
+#define MCPWM_GEN0_A_DTEA_V  0x00000003U
+#define MCPWM_GEN0_A_DTEA_S  16
+/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEB    0x00000003U
+#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
+#define MCPWM_GEN0_A_DTEB_V  0x00000003U
+#define MCPWM_GEN0_A_DTEB_S  18
+/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DT0    0x00000003U
+#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
+#define MCPWM_GEN0_A_DT0_V  0x00000003U
+#define MCPWM_GEN0_A_DT0_S  20
+/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DT1    0x00000003U
+#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
+#define MCPWM_GEN0_A_DT1_V  0x00000003U
+#define MCPWM_GEN0_A_DT1_S  22
+
+/** MCPWM_GEN0_B_REG register
+ *  PWM$n output signal B actions configuration register
+ */
+#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54)
+/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEZ    0x00000003U
+#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
+#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_UTEZ_S  0
+/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEP    0x00000003U
+#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
+#define MCPWM_GEN0_B_UTEP_V  0x00000003U
+#define MCPWM_GEN0_B_UTEP_S  2
+/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEA    0x00000003U
+#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
+#define MCPWM_GEN0_B_UTEA_V  0x00000003U
+#define MCPWM_GEN0_B_UTEA_S  4
+/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEB    0x00000003U
+#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
+#define MCPWM_GEN0_B_UTEB_V  0x00000003U
+#define MCPWM_GEN0_B_UTEB_S  6
+/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UT0    0x00000003U
+#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
+#define MCPWM_GEN0_B_UT0_V  0x00000003U
+#define MCPWM_GEN0_B_UT0_S  8
+/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UT1    0x00000003U
+#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
+#define MCPWM_GEN0_B_UT1_V  0x00000003U
+#define MCPWM_GEN0_B_UT1_S  10
+/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEZ    0x00000003U
+#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
+#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_DTEZ_S  12
+/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEP    0x00000003U
+#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
+#define MCPWM_GEN0_B_DTEP_V  0x00000003U
+#define MCPWM_GEN0_B_DTEP_S  14
+/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEA    0x00000003U
+#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
+#define MCPWM_GEN0_B_DTEA_V  0x00000003U
+#define MCPWM_GEN0_B_DTEA_S  16
+/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEB    0x00000003U
+#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
+#define MCPWM_GEN0_B_DTEB_V  0x00000003U
+#define MCPWM_GEN0_B_DTEB_S  18
+/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DT0    0x00000003U
+#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
+#define MCPWM_GEN0_B_DT0_V  0x00000003U
+#define MCPWM_GEN0_B_DT0_S  20
+/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DT1    0x00000003U
+#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
+#define MCPWM_GEN0_B_DT1_V  0x00000003U
+#define MCPWM_GEN0_B_DT1_S  22
+
+/** MCPWM_DT0_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
+/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
+#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_S  0
+/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
+#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_S  4
+/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+ *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB0_DEB_MODE    (BIT(8))
+#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
+#define MCPWM_DB0_DEB_MODE_V  0x00000001U
+#define MCPWM_DB0_DEB_MODE_S  8
+/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
+#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_A_OUTSWAP_S  9
+/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
+#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_B_OUTSWAP_S  10
+/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB0_RED_INSEL    (BIT(11))
+#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
+#define MCPWM_DB0_RED_INSEL_V  0x00000001U
+#define MCPWM_DB0_RED_INSEL_S  11
+/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB0_FED_INSEL    (BIT(12))
+#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
+#define MCPWM_DB0_FED_INSEL_V  0x00000001U
+#define MCPWM_DB0_FED_INSEL_S  12
+/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
+#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_RED_OUTINVERT_S  13
+/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
+#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_FED_OUTINVERT_S  14
+/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
+#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_A_OUTBYPASS_S  15
+/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
+#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_B_OUTBYPASS_S  16
+/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+ */
+#define MCPWM_DB0_CLK_SEL    (BIT(17))
+#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
+#define MCPWM_DB0_CLK_SEL_V  0x00000001U
+#define MCPWM_DB0_CLK_SEL_S  17
+
+/** MCPWM_DT0_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
+/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB0_FED    0x0000FFFFU
+#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
+#define MCPWM_DB0_FED_V  0x0000FFFFU
+#define MCPWM_DB0_FED_S  0
+
+/** MCPWM_DT0_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
+/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB0_RED    0x0000FFFFU
+#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
+#define MCPWM_DB0_RED_V  0x0000FFFFU
+#define MCPWM_DB0_RED_S  0
+
+/** MCPWM_CARRIER0_CFG_REG register
+ *  Carrier$n configuration register
+ */
+#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64)
+/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+ */
+#define MCPWM_CHOPPER0_EN    (BIT(0))
+#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
+#define MCPWM_CHOPPER0_EN_V  0x00000001U
+#define MCPWM_CHOPPER0_EN_S  0
+/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
+#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_S  1
+/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+ */
+#define MCPWM_CHOPPER0_DUTY    0x00000007U
+#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
+#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER0_DUTY_S  5
+/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
+#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_S  8
+/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
+#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_OUT_INVERT_S  12
+/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
+#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_IN_INVERT_S  13
+
+/** MCPWM_FH0_CFG0_REG register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68)
+/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_SW_CBC    (BIT(0))
+#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
+#define MCPWM_TZ0_SW_CBC_V  0x00000001U
+#define MCPWM_TZ0_SW_CBC_S  0
+/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F2_CBC    (BIT(1))
+#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
+#define MCPWM_TZ0_F2_CBC_V  0x00000001U
+#define MCPWM_TZ0_F2_CBC_S  1
+/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F1_CBC    (BIT(2))
+#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
+#define MCPWM_TZ0_F1_CBC_V  0x00000001U
+#define MCPWM_TZ0_F1_CBC_S  2
+/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F0_CBC    (BIT(3))
+#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
+#define MCPWM_TZ0_F0_CBC_V  0x00000001U
+#define MCPWM_TZ0_F0_CBC_S  3
+/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_SW_OST    (BIT(4))
+#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
+#define MCPWM_TZ0_SW_OST_V  0x00000001U
+#define MCPWM_TZ0_SW_OST_S  4
+/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F2_OST    (BIT(5))
+#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
+#define MCPWM_TZ0_F2_OST_V  0x00000001U
+#define MCPWM_TZ0_F2_OST_S  5
+/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F1_OST    (BIT(6))
+#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
+#define MCPWM_TZ0_F1_OST_V  0x00000001U
+#define MCPWM_TZ0_F1_OST_S  6
+/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F0_OST    (BIT(7))
+#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
+#define MCPWM_TZ0_F0_OST_V  0x00000001U
+#define MCPWM_TZ0_F0_OST_S  7
+/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_CBC_D    0x00000003U
+#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
+#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_D_S  8
+/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_CBC_U    0x00000003U
+#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
+#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_U_S  10
+/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_OST_D    0x00000003U
+#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
+#define MCPWM_TZ0_A_OST_D_V  0x00000003U
+#define MCPWM_TZ0_A_OST_D_S  12
+/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_OST_U    0x00000003U
+#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
+#define MCPWM_TZ0_A_OST_U_V  0x00000003U
+#define MCPWM_TZ0_A_OST_U_S  14
+/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_CBC_D    0x00000003U
+#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
+#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_D_S  16
+/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_CBC_U    0x00000003U
+#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
+#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_U_S  18
+/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_OST_D    0x00000003U
+#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
+#define MCPWM_TZ0_B_OST_D_V  0x00000003U
+#define MCPWM_TZ0_B_OST_D_S  20
+/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_OST_U    0x00000003U
+#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
+#define MCPWM_TZ0_B_OST_U_V  0x00000003U
+#define MCPWM_TZ0_B_OST_U_S  22
+
+/** MCPWM_FH0_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c)
+/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ0_CLR_OST    (BIT(0))
+#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
+#define MCPWM_TZ0_CLR_OST_V  0x00000001U
+#define MCPWM_TZ0_CLR_OST_S  0
+/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+ *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ0_CBCPULSE    0x00000003U
+#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
+#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ0_CBCPULSE_S  1
+/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
+#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ0_FORCE_CBC_S  3
+/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ0_FORCE_OST    (BIT(4))
+#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
+#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ0_FORCE_OST_S  4
+
+/** MCPWM_FH0_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70)
+/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+ *  action\\1: On going
+ */
+#define MCPWM_TZ0_CBC_ON    (BIT(0))
+#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
+#define MCPWM_TZ0_CBC_ON_V  0x00000001U
+#define MCPWM_TZ0_CBC_ON_S  0
+/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+ *  going
+ */
+#define MCPWM_TZ0_OST_ON    (BIT(1))
+#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
+#define MCPWM_TZ0_OST_ON_V  0x00000001U
+#define MCPWM_TZ0_OST_ON_S  1
+
+/** MCPWM_GEN1_STMP_CFG_REG register
+ *  Generator1 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 1 time stamp A's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 1 time stamp B's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0:
+ *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+ *  reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0:
+ *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+ *  reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN1_TSTMP_A_REG register
+ *  Generator$n time stamp A's shadow register
+ */
+#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78)
+/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp A's shadow register.
+ */
+#define MCPWM_CMPR1_A    0x0000FFFFU
+#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
+#define MCPWM_CMPR1_A_V  0x0000FFFFU
+#define MCPWM_CMPR1_A_S  0
+
+/** MCPWM_GEN1_TSTMP_B_REG register
+ *  Generator$n time stamp B's shadow register
+ */
+#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c)
+/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp B's shadow register.
+ */
+#define MCPWM_CMPR1_B    0x0000FFFFU
+#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
+#define MCPWM_CMPR1_B_V  0x0000FFFFU
+#define MCPWM_CMPR1_B_S  0
+
+/** MCPWM_GEN1_CFG0_REG register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80)
+/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator $n's active register.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator $n event_t0, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN1_T0_SEL    0x00000007U
+#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
+#define MCPWM_GEN1_T0_SEL_V  0x00000007U
+#define MCPWM_GEN1_T0_SEL_S  4
+/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator $n event_t1, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN1_T1_SEL    0x00000007U
+#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
+#define MCPWM_GEN1_T1_SEL_V  0x00000007U
+#define MCPWM_GEN1_T1_SEL_S  7
+
+/** MCPWM_GEN1_FORCE_REG register
+ *  Generator$n output signal force mode register.
+ */
+#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84)
+/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator$n.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+ *  update. TEA/B here and below means an event generated when the timer's value equals
+ *  to that of register A/B.
+ */
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
+#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
+#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN1_A_REG register
+ *  PWM$n output signal A actions configuration register
+ */
+#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88)
+/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEZ    0x00000003U
+#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
+#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_UTEZ_S  0
+/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEP    0x00000003U
+#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
+#define MCPWM_GEN1_A_UTEP_V  0x00000003U
+#define MCPWM_GEN1_A_UTEP_S  2
+/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEA    0x00000003U
+#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
+#define MCPWM_GEN1_A_UTEA_V  0x00000003U
+#define MCPWM_GEN1_A_UTEA_S  4
+/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEB    0x00000003U
+#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
+#define MCPWM_GEN1_A_UTEB_V  0x00000003U
+#define MCPWM_GEN1_A_UTEB_S  6
+/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UT0    0x00000003U
+#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
+#define MCPWM_GEN1_A_UT0_V  0x00000003U
+#define MCPWM_GEN1_A_UT0_S  8
+/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UT1    0x00000003U
+#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
+#define MCPWM_GEN1_A_UT1_V  0x00000003U
+#define MCPWM_GEN1_A_UT1_S  10
+/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEZ    0x00000003U
+#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
+#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_DTEZ_S  12
+/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEP    0x00000003U
+#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
+#define MCPWM_GEN1_A_DTEP_V  0x00000003U
+#define MCPWM_GEN1_A_DTEP_S  14
+/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEA    0x00000003U
+#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
+#define MCPWM_GEN1_A_DTEA_V  0x00000003U
+#define MCPWM_GEN1_A_DTEA_S  16
+/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEB    0x00000003U
+#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
+#define MCPWM_GEN1_A_DTEB_V  0x00000003U
+#define MCPWM_GEN1_A_DTEB_S  18
+/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DT0    0x00000003U
+#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
+#define MCPWM_GEN1_A_DT0_V  0x00000003U
+#define MCPWM_GEN1_A_DT0_S  20
+/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DT1    0x00000003U
+#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
+#define MCPWM_GEN1_A_DT1_V  0x00000003U
+#define MCPWM_GEN1_A_DT1_S  22
+
+/** MCPWM_GEN1_B_REG register
+ *  PWM$n output signal B actions configuration register
+ */
+#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c)
+/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEZ    0x00000003U
+#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
+#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_UTEZ_S  0
+/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEP    0x00000003U
+#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
+#define MCPWM_GEN1_B_UTEP_V  0x00000003U
+#define MCPWM_GEN1_B_UTEP_S  2
+/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEA    0x00000003U
+#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
+#define MCPWM_GEN1_B_UTEA_V  0x00000003U
+#define MCPWM_GEN1_B_UTEA_S  4
+/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEB    0x00000003U
+#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
+#define MCPWM_GEN1_B_UTEB_V  0x00000003U
+#define MCPWM_GEN1_B_UTEB_S  6
+/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UT0    0x00000003U
+#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
+#define MCPWM_GEN1_B_UT0_V  0x00000003U
+#define MCPWM_GEN1_B_UT0_S  8
+/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UT1    0x00000003U
+#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
+#define MCPWM_GEN1_B_UT1_V  0x00000003U
+#define MCPWM_GEN1_B_UT1_S  10
+/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEZ    0x00000003U
+#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
+#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_DTEZ_S  12
+/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEP    0x00000003U
+#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
+#define MCPWM_GEN1_B_DTEP_V  0x00000003U
+#define MCPWM_GEN1_B_DTEP_S  14
+/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEA    0x00000003U
+#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
+#define MCPWM_GEN1_B_DTEA_V  0x00000003U
+#define MCPWM_GEN1_B_DTEA_S  16
+/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEB    0x00000003U
+#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
+#define MCPWM_GEN1_B_DTEB_V  0x00000003U
+#define MCPWM_GEN1_B_DTEB_S  18
+/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DT0    0x00000003U
+#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
+#define MCPWM_GEN1_B_DT0_V  0x00000003U
+#define MCPWM_GEN1_B_DT0_S  20
+/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DT1    0x00000003U
+#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
+#define MCPWM_GEN1_B_DT1_V  0x00000003U
+#define MCPWM_GEN1_B_DT1_S  22
+
+/** MCPWM_DT1_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
+/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
+#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_S  0
+/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
+#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_S  4
+/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+ *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB1_DEB_MODE    (BIT(8))
+#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
+#define MCPWM_DB1_DEB_MODE_V  0x00000001U
+#define MCPWM_DB1_DEB_MODE_S  8
+/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
+#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_A_OUTSWAP_S  9
+/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
+#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_B_OUTSWAP_S  10
+/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB1_RED_INSEL    (BIT(11))
+#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
+#define MCPWM_DB1_RED_INSEL_V  0x00000001U
+#define MCPWM_DB1_RED_INSEL_S  11
+/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB1_FED_INSEL    (BIT(12))
+#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
+#define MCPWM_DB1_FED_INSEL_V  0x00000001U
+#define MCPWM_DB1_FED_INSEL_S  12
+/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
+#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_RED_OUTINVERT_S  13
+/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
+#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_FED_OUTINVERT_S  14
+/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
+#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_A_OUTBYPASS_S  15
+/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
+#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_B_OUTBYPASS_S  16
+/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+ */
+#define MCPWM_DB1_CLK_SEL    (BIT(17))
+#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
+#define MCPWM_DB1_CLK_SEL_V  0x00000001U
+#define MCPWM_DB1_CLK_SEL_S  17
+
+/** MCPWM_DT1_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
+/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB1_FED    0x0000FFFFU
+#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
+#define MCPWM_DB1_FED_V  0x0000FFFFU
+#define MCPWM_DB1_FED_S  0
+
+/** MCPWM_DT1_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
+/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB1_RED    0x0000FFFFU
+#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
+#define MCPWM_DB1_RED_V  0x0000FFFFU
+#define MCPWM_DB1_RED_S  0
+
+/** MCPWM_CARRIER1_CFG_REG register
+ *  Carrier$n configuration register
+ */
+#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c)
+/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+ */
+#define MCPWM_CHOPPER1_EN    (BIT(0))
+#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
+#define MCPWM_CHOPPER1_EN_V  0x00000001U
+#define MCPWM_CHOPPER1_EN_S  0
+/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
+#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_S  1
+/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+ */
+#define MCPWM_CHOPPER1_DUTY    0x00000007U
+#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
+#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER1_DUTY_S  5
+/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
+#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_S  8
+/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
+#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_OUT_INVERT_S  12
+/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
+#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_IN_INVERT_S  13
+
+/** MCPWM_FH1_CFG0_REG register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0)
+/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_SW_CBC    (BIT(0))
+#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
+#define MCPWM_TZ1_SW_CBC_V  0x00000001U
+#define MCPWM_TZ1_SW_CBC_S  0
+/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F2_CBC    (BIT(1))
+#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
+#define MCPWM_TZ1_F2_CBC_V  0x00000001U
+#define MCPWM_TZ1_F2_CBC_S  1
+/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F1_CBC    (BIT(2))
+#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
+#define MCPWM_TZ1_F1_CBC_V  0x00000001U
+#define MCPWM_TZ1_F1_CBC_S  2
+/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F0_CBC    (BIT(3))
+#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
+#define MCPWM_TZ1_F0_CBC_V  0x00000001U
+#define MCPWM_TZ1_F0_CBC_S  3
+/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_SW_OST    (BIT(4))
+#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
+#define MCPWM_TZ1_SW_OST_V  0x00000001U
+#define MCPWM_TZ1_SW_OST_S  4
+/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F2_OST    (BIT(5))
+#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
+#define MCPWM_TZ1_F2_OST_V  0x00000001U
+#define MCPWM_TZ1_F2_OST_S  5
+/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F1_OST    (BIT(6))
+#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
+#define MCPWM_TZ1_F1_OST_V  0x00000001U
+#define MCPWM_TZ1_F1_OST_S  6
+/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F0_OST    (BIT(7))
+#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
+#define MCPWM_TZ1_F0_OST_V  0x00000001U
+#define MCPWM_TZ1_F0_OST_S  7
+/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_CBC_D    0x00000003U
+#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
+#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_D_S  8
+/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_CBC_U    0x00000003U
+#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
+#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_U_S  10
+/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_OST_D    0x00000003U
+#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
+#define MCPWM_TZ1_A_OST_D_V  0x00000003U
+#define MCPWM_TZ1_A_OST_D_S  12
+/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_OST_U    0x00000003U
+#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
+#define MCPWM_TZ1_A_OST_U_V  0x00000003U
+#define MCPWM_TZ1_A_OST_U_S  14
+/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_CBC_D    0x00000003U
+#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
+#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_D_S  16
+/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_CBC_U    0x00000003U
+#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
+#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_U_S  18
+/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_OST_D    0x00000003U
+#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
+#define MCPWM_TZ1_B_OST_D_V  0x00000003U
+#define MCPWM_TZ1_B_OST_D_S  20
+/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_OST_U    0x00000003U
+#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
+#define MCPWM_TZ1_B_OST_U_V  0x00000003U
+#define MCPWM_TZ1_B_OST_U_S  22
+
+/** MCPWM_FH1_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4)
+/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ1_CLR_OST    (BIT(0))
+#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
+#define MCPWM_TZ1_CLR_OST_V  0x00000001U
+#define MCPWM_TZ1_CLR_OST_S  0
+/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+ *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ1_CBCPULSE    0x00000003U
+#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
+#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ1_CBCPULSE_S  1
+/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
+#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ1_FORCE_CBC_S  3
+/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ1_FORCE_OST    (BIT(4))
+#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
+#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ1_FORCE_OST_S  4
+
+/** MCPWM_FH1_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8)
+/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+ *  action\\1: On going
+ */
+#define MCPWM_TZ1_CBC_ON    (BIT(0))
+#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
+#define MCPWM_TZ1_CBC_ON_V  0x00000001U
+#define MCPWM_TZ1_CBC_ON_S  0
+/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+ *  going
+ */
+#define MCPWM_TZ1_OST_ON    (BIT(1))
+#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
+#define MCPWM_TZ1_OST_ON_V  0x00000001U
+#define MCPWM_TZ1_OST_ON_S  1
+
+/** MCPWM_GEN2_STMP_CFG_REG register
+ *  Generator2 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 2 time stamp A's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 2 time stamp B's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0:
+ *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+ *  reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0:
+ *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+ *  reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN2_TSTMP_A_REG register
+ *  Generator$n time stamp A's shadow register
+ */
+#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0)
+/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp A's shadow register.
+ */
+#define MCPWM_CMPR2_A    0x0000FFFFU
+#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
+#define MCPWM_CMPR2_A_V  0x0000FFFFU
+#define MCPWM_CMPR2_A_S  0
+
+/** MCPWM_GEN2_TSTMP_B_REG register
+ *  Generator$n time stamp B's shadow register
+ */
+#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4)
+/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp B's shadow register.
+ */
+#define MCPWM_CMPR2_B    0x0000FFFFU
+#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
+#define MCPWM_CMPR2_B_V  0x0000FFFFU
+#define MCPWM_CMPR2_B_S  0
+
+/** MCPWM_GEN2_CFG0_REG register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8)
+/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator $n's active register.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator $n event_t0, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN2_T0_SEL    0x00000007U
+#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
+#define MCPWM_GEN2_T0_SEL_V  0x00000007U
+#define MCPWM_GEN2_T0_SEL_S  4
+/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator $n event_t1, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN2_T1_SEL    0x00000007U
+#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
+#define MCPWM_GEN2_T1_SEL_V  0x00000007U
+#define MCPWM_GEN2_T1_SEL_S  7
+
+/** MCPWM_GEN2_FORCE_REG register
+ *  Generator$n output signal force mode register.
+ */
+#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc)
+/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator$n.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+ *  update. TEA/B here and below means an event generated when the timer's value equals
+ *  to that of register A/B.
+ */
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
+#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
+#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN2_A_REG register
+ *  PWM$n output signal A actions configuration register
+ */
+#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0)
+/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEZ    0x00000003U
+#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
+#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_UTEZ_S  0
+/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEP    0x00000003U
+#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
+#define MCPWM_GEN2_A_UTEP_V  0x00000003U
+#define MCPWM_GEN2_A_UTEP_S  2
+/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEA    0x00000003U
+#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
+#define MCPWM_GEN2_A_UTEA_V  0x00000003U
+#define MCPWM_GEN2_A_UTEA_S  4
+/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEB    0x00000003U
+#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
+#define MCPWM_GEN2_A_UTEB_V  0x00000003U
+#define MCPWM_GEN2_A_UTEB_S  6
+/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UT0    0x00000003U
+#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
+#define MCPWM_GEN2_A_UT0_V  0x00000003U
+#define MCPWM_GEN2_A_UT0_S  8
+/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UT1    0x00000003U
+#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
+#define MCPWM_GEN2_A_UT1_V  0x00000003U
+#define MCPWM_GEN2_A_UT1_S  10
+/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEZ    0x00000003U
+#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
+#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_DTEZ_S  12
+/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEP    0x00000003U
+#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
+#define MCPWM_GEN2_A_DTEP_V  0x00000003U
+#define MCPWM_GEN2_A_DTEP_S  14
+/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEA    0x00000003U
+#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
+#define MCPWM_GEN2_A_DTEA_V  0x00000003U
+#define MCPWM_GEN2_A_DTEA_S  16
+/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEB    0x00000003U
+#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
+#define MCPWM_GEN2_A_DTEB_V  0x00000003U
+#define MCPWM_GEN2_A_DTEB_S  18
+/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DT0    0x00000003U
+#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
+#define MCPWM_GEN2_A_DT0_V  0x00000003U
+#define MCPWM_GEN2_A_DT0_S  20
+/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DT1    0x00000003U
+#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
+#define MCPWM_GEN2_A_DT1_V  0x00000003U
+#define MCPWM_GEN2_A_DT1_S  22
+
+/** MCPWM_GEN2_B_REG register
+ *  PWM$n output signal B actions configuration register
+ */
+#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4)
+/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEZ    0x00000003U
+#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
+#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_UTEZ_S  0
+/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEP    0x00000003U
+#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
+#define MCPWM_GEN2_B_UTEP_V  0x00000003U
+#define MCPWM_GEN2_B_UTEP_S  2
+/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEA    0x00000003U
+#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
+#define MCPWM_GEN2_B_UTEA_V  0x00000003U
+#define MCPWM_GEN2_B_UTEA_S  4
+/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEB    0x00000003U
+#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
+#define MCPWM_GEN2_B_UTEB_V  0x00000003U
+#define MCPWM_GEN2_B_UTEB_S  6
+/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UT0    0x00000003U
+#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
+#define MCPWM_GEN2_B_UT0_V  0x00000003U
+#define MCPWM_GEN2_B_UT0_S  8
+/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UT1    0x00000003U
+#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
+#define MCPWM_GEN2_B_UT1_V  0x00000003U
+#define MCPWM_GEN2_B_UT1_S  10
+/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEZ    0x00000003U
+#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
+#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_DTEZ_S  12
+/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEP    0x00000003U
+#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
+#define MCPWM_GEN2_B_DTEP_V  0x00000003U
+#define MCPWM_GEN2_B_DTEP_S  14
+/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEA    0x00000003U
+#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
+#define MCPWM_GEN2_B_DTEA_V  0x00000003U
+#define MCPWM_GEN2_B_DTEA_S  16
+/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEB    0x00000003U
+#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
+#define MCPWM_GEN2_B_DTEB_V  0x00000003U
+#define MCPWM_GEN2_B_DTEB_S  18
+/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DT0    0x00000003U
+#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
+#define MCPWM_GEN2_B_DT0_V  0x00000003U
+#define MCPWM_GEN2_B_DT0_S  20
+/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DT1    0x00000003U
+#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
+#define MCPWM_GEN2_B_DT1_V  0x00000003U
+#define MCPWM_GEN2_B_DT1_S  22
+
+/** MCPWM_DT2_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
+/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
+#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_S  0
+/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
+#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_S  4
+/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+ *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB2_DEB_MODE    (BIT(8))
+#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
+#define MCPWM_DB2_DEB_MODE_V  0x00000001U
+#define MCPWM_DB2_DEB_MODE_S  8
+/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
+#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_A_OUTSWAP_S  9
+/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
+#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_B_OUTSWAP_S  10
+/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB2_RED_INSEL    (BIT(11))
+#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
+#define MCPWM_DB2_RED_INSEL_V  0x00000001U
+#define MCPWM_DB2_RED_INSEL_S  11
+/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB2_FED_INSEL    (BIT(12))
+#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
+#define MCPWM_DB2_FED_INSEL_V  0x00000001U
+#define MCPWM_DB2_FED_INSEL_S  12
+/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
+#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_RED_OUTINVERT_S  13
+/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
+#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_FED_OUTINVERT_S  14
+/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
+#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_A_OUTBYPASS_S  15
+/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
+#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_B_OUTBYPASS_S  16
+/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+ */
+#define MCPWM_DB2_CLK_SEL    (BIT(17))
+#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
+#define MCPWM_DB2_CLK_SEL_V  0x00000001U
+#define MCPWM_DB2_CLK_SEL_S  17
+
+/** MCPWM_DT2_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
+/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB2_FED    0x0000FFFFU
+#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
+#define MCPWM_DB2_FED_V  0x0000FFFFU
+#define MCPWM_DB2_FED_S  0
+
+/** MCPWM_DT2_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
+/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB2_RED    0x0000FFFFU
+#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
+#define MCPWM_DB2_RED_V  0x0000FFFFU
+#define MCPWM_DB2_RED_S  0
+
+/** MCPWM_CARRIER2_CFG_REG register
+ *  Carrier$n configuration register
+ */
+#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4)
+/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+ */
+#define MCPWM_CHOPPER2_EN    (BIT(0))
+#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
+#define MCPWM_CHOPPER2_EN_V  0x00000001U
+#define MCPWM_CHOPPER2_EN_S  0
+/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
+#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_S  1
+/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+ */
+#define MCPWM_CHOPPER2_DUTY    0x00000007U
+#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
+#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER2_DUTY_S  5
+/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
+#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_S  8
+/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
+#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_OUT_INVERT_S  12
+/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
+#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_IN_INVERT_S  13
+
+/** MCPWM_FH2_CFG0_REG register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8)
+/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_SW_CBC    (BIT(0))
+#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
+#define MCPWM_TZ2_SW_CBC_V  0x00000001U
+#define MCPWM_TZ2_SW_CBC_S  0
+/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F2_CBC    (BIT(1))
+#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
+#define MCPWM_TZ2_F2_CBC_V  0x00000001U
+#define MCPWM_TZ2_F2_CBC_S  1
+/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F1_CBC    (BIT(2))
+#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
+#define MCPWM_TZ2_F1_CBC_V  0x00000001U
+#define MCPWM_TZ2_F1_CBC_S  2
+/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F0_CBC    (BIT(3))
+#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
+#define MCPWM_TZ2_F0_CBC_V  0x00000001U
+#define MCPWM_TZ2_F0_CBC_S  3
+/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_SW_OST    (BIT(4))
+#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
+#define MCPWM_TZ2_SW_OST_V  0x00000001U
+#define MCPWM_TZ2_SW_OST_S  4
+/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F2_OST    (BIT(5))
+#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
+#define MCPWM_TZ2_F2_OST_V  0x00000001U
+#define MCPWM_TZ2_F2_OST_S  5
+/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F1_OST    (BIT(6))
+#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
+#define MCPWM_TZ2_F1_OST_V  0x00000001U
+#define MCPWM_TZ2_F1_OST_S  6
+/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F0_OST    (BIT(7))
+#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
+#define MCPWM_TZ2_F0_OST_V  0x00000001U
+#define MCPWM_TZ2_F0_OST_S  7
+/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_CBC_D    0x00000003U
+#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
+#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_D_S  8
+/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_CBC_U    0x00000003U
+#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
+#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_U_S  10
+/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_OST_D    0x00000003U
+#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
+#define MCPWM_TZ2_A_OST_D_V  0x00000003U
+#define MCPWM_TZ2_A_OST_D_S  12
+/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_OST_U    0x00000003U
+#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
+#define MCPWM_TZ2_A_OST_U_V  0x00000003U
+#define MCPWM_TZ2_A_OST_U_S  14
+/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_CBC_D    0x00000003U
+#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
+#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_D_S  16
+/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_CBC_U    0x00000003U
+#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
+#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_U_S  18
+/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_OST_D    0x00000003U
+#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
+#define MCPWM_TZ2_B_OST_D_V  0x00000003U
+#define MCPWM_TZ2_B_OST_D_S  20
+/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_OST_U    0x00000003U
+#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
+#define MCPWM_TZ2_B_OST_U_V  0x00000003U
+#define MCPWM_TZ2_B_OST_U_S  22
+
+/** MCPWM_FH2_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc)
+/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ2_CLR_OST    (BIT(0))
+#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
+#define MCPWM_TZ2_CLR_OST_V  0x00000001U
+#define MCPWM_TZ2_CLR_OST_S  0
+/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+ *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ2_CBCPULSE    0x00000003U
+#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
+#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ2_CBCPULSE_S  1
+/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
+#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ2_FORCE_CBC_S  3
+/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ2_FORCE_OST    (BIT(4))
+#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
+#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ2_FORCE_OST_S  4
+
+/** MCPWM_FH2_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0)
+/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+ *  action\\1: On going
+ */
+#define MCPWM_TZ2_CBC_ON    (BIT(0))
+#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
+#define MCPWM_TZ2_CBC_ON_V  0x00000001U
+#define MCPWM_TZ2_CBC_ON_S  0
+/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+ *  going
+ */
+#define MCPWM_TZ2_OST_ON    (BIT(1))
+#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
+#define MCPWM_TZ2_OST_ON_V  0x00000001U
+#define MCPWM_TZ2_OST_ON_S  1
+
+/** MCPWM_FAULT_DETECT_REG register
+ *  Fault detection configuration and status register
+ */
+#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4)
+/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
+ */
+#define MCPWM_F0_EN    (BIT(0))
+#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
+#define MCPWM_F0_EN_V  0x00000001U
+#define MCPWM_F0_EN_S  0
+/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
+ */
+#define MCPWM_F1_EN    (BIT(1))
+#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
+#define MCPWM_F1_EN_V  0x00000001U
+#define MCPWM_F1_EN_S  1
+/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
+ */
+#define MCPWM_F2_EN    (BIT(2))
+#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
+#define MCPWM_F2_EN_V  0x00000001U
+#define MCPWM_F2_EN_S  2
+/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
+ *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
+ *  low\\1: Level high
+ */
+#define MCPWM_F0_POLE    (BIT(3))
+#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
+#define MCPWM_F0_POLE_V  0x00000001U
+#define MCPWM_F0_POLE_S  3
+/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
+ *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
+ *  low\\1: Level high
+ */
+#define MCPWM_F1_POLE    (BIT(4))
+#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
+#define MCPWM_F1_POLE_V  0x00000001U
+#define MCPWM_F1_POLE_S  4
+/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
+ *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
+ *  low\\1: Level high
+ */
+#define MCPWM_F2_POLE    (BIT(5))
+#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
+#define MCPWM_F2_POLE_V  0x00000001U
+#define MCPWM_F2_POLE_S  5
+/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
+ *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
+ */
+#define MCPWM_EVENT_F0    (BIT(6))
+#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
+#define MCPWM_EVENT_F0_V  0x00000001U
+#define MCPWM_EVENT_F0_S  6
+/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
+ *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
+ */
+#define MCPWM_EVENT_F1    (BIT(7))
+#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
+#define MCPWM_EVENT_F1_V  0x00000001U
+#define MCPWM_EVENT_F1_S  7
+/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
+ *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
+ */
+#define MCPWM_EVENT_F2    (BIT(8))
+#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
+#define MCPWM_EVENT_F2_V  0x00000001U
+#define MCPWM_EVENT_F2_S  8
+
+/** MCPWM_CAP_TIMER_CFG_REG register
+ *  Capture timer configuration register
+ */
+#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8)
+/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP_TIMER_EN    (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
+#define MCPWM_CAP_TIMER_EN_V  0x00000001U
+#define MCPWM_CAP_TIMER_EN_S  0
+/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP_SYNCI_EN    (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
+#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
+#define MCPWM_CAP_SYNCI_EN_S  1
+/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
+ *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
+ *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
+ */
+#define MCPWM_CAP_SYNCI_SEL    0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
+#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
+ *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
+ *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
+ *  value in phase register
+ */
+#define MCPWM_CAP_SYNC_SW    (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
+#define MCPWM_CAP_SYNC_SW_V  0x00000001U
+#define MCPWM_CAP_SYNC_SW_S  5
+
+/** MCPWM_CAP_TIMER_PHASE_REG register
+ *  Capture timer sync phase register
+ */
+#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec)
+/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
+ *  Configures phase value for capture timer sync operation.
+ */
+#define MCPWM_CAP_PHASE    0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_S  0
+
+/** MCPWM_CAP_CH0_CFG_REG register
+ *  Capture channel 0 configuration register
+ */
+#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 0 after prescaling is used.\\0:
+ *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+ *  Enable capture on the positive edge
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on possitive edge of CAP0. Prescale value =
+ *  PWM_CAP0_PRESCALE + 1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0:
+ *  Normal\\1: Invert
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+ *  software forced capture on channel 0
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH1_CFG_REG register
+ *  Capture channel 1 configuration register
+ */
+#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 1 after prescaling is used.\\0:
+ *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+ *  Enable capture on the positive edge
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on possitive edge of CAP1. Prescale value =
+ *  PWM_CAP1_PRESCALE + 1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0:
+ *  Normal\\1: Invert
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+ *  software forced capture on channel 1
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH2_CFG_REG register
+ *  Capture channel 2 configuration register
+ */
+#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 2 after prescaling is used.\\0:
+ *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+ *  Enable capture on the positive edge
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on possitive edge of CAP2. Prescale value =
+ *  PWM_CAP2_PRESCALE + 1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0:
+ *  Normal\\1: Invert
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+ *  software forced capture on channel 2
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH0_REG register
+ *  CAP0 capture value register
+ */
+#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP0
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH1_REG register
+ *  CAP1 capture value register
+ */
+#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP1
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH2_REG register
+ *  CAP2 capture value register
+ */
+#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP2
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_STATUS_REG register
+ *  Last capture trigger edge information register
+ */
+#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108)
+/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
+ *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
+ */
+#define MCPWM_CAP0_EDGE    (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
+#define MCPWM_CAP0_EDGE_V  0x00000001U
+#define MCPWM_CAP0_EDGE_S  0
+/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
+ *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
+ */
+#define MCPWM_CAP1_EDGE    (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
+#define MCPWM_CAP1_EDGE_V  0x00000001U
+#define MCPWM_CAP1_EDGE_S  1
+/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
+ *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
+ */
+#define MCPWM_CAP2_EDGE    (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
+#define MCPWM_CAP2_EDGE_V  0x00000001U
+#define MCPWM_CAP2_EDGE_S  2
+
+/** MCPWM_UPDATE_CFG_REG register
+ *  Generator Update configuration register
+ */
+#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c)
+/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether or not to enable global update for all active registers in MCPWM
+ *  module.\\0: Disable\\1: Enable
+ */
+#define MCPWM_GLOBAL_UP_EN    (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
+#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
+#define MCPWM_GLOBAL_UP_EN_S  0
+/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of global forced update for all active registers in MCPWM
+ *  module. A toggle (software invert its value) will trigger a global forced update.
+ *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
+ */
+#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
+#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator$n.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_OP0_UP_EN    (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
+#define MCPWM_OP0_UP_EN_V  0x00000001U
+#define MCPWM_OP0_UP_EN_S  2
+/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator0. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
+ */
+#define MCPWM_OP0_FORCE_UP    (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
+#define MCPWM_OP0_FORCE_UP_V  0x00000001U
+#define MCPWM_OP0_FORCE_UP_S  3
+/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator$n.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_OP1_UP_EN    (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
+#define MCPWM_OP1_UP_EN_V  0x00000001U
+#define MCPWM_OP1_UP_EN_S  4
+/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator1. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
+ */
+#define MCPWM_OP1_FORCE_UP    (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
+#define MCPWM_OP1_FORCE_UP_V  0x00000001U
+#define MCPWM_OP1_FORCE_UP_S  5
+/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator$n.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_OP2_UP_EN    (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
+#define MCPWM_OP2_UP_EN_V  0x00000001U
+#define MCPWM_OP2_UP_EN_S  6
+/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator2. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
+ */
+#define MCPWM_OP2_FORCE_UP    (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
+#define MCPWM_OP2_FORCE_UP_V  0x00000001U
+#define MCPWM_OP2_FORCE_UP_S  7
+
+/** MCPWM_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110)
+/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ENA    (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
+#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_INT_ENA_S  9
+/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ENA    (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
+#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_INT_ENA_S  10
+/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ENA    (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
+#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_INT_ENA_S  11
+/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
+ */
+#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
+#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ENA_S  15
+/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
+ */
+#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
+#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ENA_S  16
+/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
+ */
+#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
+#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ENA_S  17
+/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
+ */
+#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
+#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ENA_S  18
+/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
+ */
+#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
+#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ENA_S  19
+/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
+ */
+#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
+#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ENA_S  20
+/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
+#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ENA_S  21
+/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
+#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ENA_S  22
+/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
+#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ENA_S  23
+/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
+#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ENA_S  24
+/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
+#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ENA_S  25
+/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
+#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ENA_S  26
+/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_ENA    (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
+#define MCPWM_CAP0_INT_ENA_V  0x00000001U
+#define MCPWM_CAP0_INT_ENA_S  27
+/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_ENA    (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
+#define MCPWM_CAP1_INT_ENA_V  0x00000001U
+#define MCPWM_CAP1_INT_ENA_S  28
+/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_ENA    (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
+#define MCPWM_CAP2_INT_ENA_V  0x00000001U
+#define MCPWM_CAP2_INT_ENA_S  29
+
+/** MCPWM_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114)
+/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+ *  starts.
+ */
+#define MCPWM_FAULT0_INT_RAW    (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
+#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_INT_RAW_S  9
+/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+ *  starts.
+ */
+#define MCPWM_FAULT1_INT_RAW    (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
+#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_INT_RAW_S  10
+/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+ *  starts.
+ */
+#define MCPWM_FAULT2_INT_RAW    (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
+#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_INT_RAW_S  11
+/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+ *  clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+ *  clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+ *  clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
+#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_RAW_S  15
+/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
+#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_RAW_S  16
+/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
+#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_RAW_S  17
+/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
+#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_RAW_S  18
+/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
+#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_RAW_S  19
+/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
+#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_RAW_S  20
+/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
+#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_RAW_S  21
+/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
+#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_RAW_S  22
+/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
+#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_RAW_S  23
+/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
+#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
+#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_RAW_S  24
+/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
+#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
+#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_RAW_S  25
+/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
+#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
+#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_RAW_S  26
+/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP0.
+ */
+#define MCPWM_CAP0_INT_RAW    (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
+#define MCPWM_CAP0_INT_RAW_V  0x00000001U
+#define MCPWM_CAP0_INT_RAW_S  27
+/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP1.
+ */
+#define MCPWM_CAP1_INT_RAW    (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
+#define MCPWM_CAP1_INT_RAW_V  0x00000001U
+#define MCPWM_CAP1_INT_RAW_S  28
+/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP2.
+ */
+#define MCPWM_CAP2_INT_RAW    (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
+#define MCPWM_CAP2_INT_RAW_V  0x00000001U
+#define MCPWM_CAP2_INT_RAW_S  29
+
+/** MCPWM_INT_ST_REG register
+ *  Interrupt masked status register
+ */
+#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118)
+/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ST    (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
+#define MCPWM_FAULT0_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_INT_ST_S  9
+/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ST    (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
+#define MCPWM_FAULT1_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_INT_ST_S  10
+/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ST    (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
+#define MCPWM_FAULT2_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_INT_ST_S  11
+/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
+#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ST_S  15
+/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
+#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ST_S  16
+/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
+#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ST_S  17
+/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
+#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ST_S  18
+/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
+#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ST_S  19
+/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
+#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ST_S  20
+/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
+#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ST_S  21
+/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
+#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ST_S  22
+/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
+#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ST_S  23
+/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
+#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ST_S  24
+/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
+#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ST_S  25
+/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
+#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ST_S  26
+/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_ST    (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
+#define MCPWM_CAP0_INT_ST_V  0x00000001U
+#define MCPWM_CAP0_INT_ST_S  27
+/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_ST    (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
+#define MCPWM_CAP1_INT_ST_V  0x00000001U
+#define MCPWM_CAP1_INT_ST_S  28
+/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_ST    (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
+#define MCPWM_CAP2_INT_ST_V  0x00000001U
+#define MCPWM_CAP2_INT_ST_S  29
+
+/** MCPWM_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c)
+/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_CLR    (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
+#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_INT_CLR_S  9
+/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_CLR    (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
+#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_INT_CLR_S  10
+/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_CLR    (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
+#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_INT_CLR_S  11
+/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
+#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_CLR_S  15
+/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
+#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_CLR_S  16
+/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
+#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_CLR_S  17
+/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
+#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_CLR_S  18
+/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
+#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_CLR_S  19
+/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
+#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_CLR_S  20
+/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
+#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_CLR_S  21
+/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
+#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_CLR_S  22
+/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
+#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_CLR_S  23
+/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
+#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
+#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_CLR_S  24
+/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
+#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
+#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_CLR_S  25
+/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
+#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
+#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_CLR_S  26
+/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_CLR    (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
+#define MCPWM_CAP0_INT_CLR_V  0x00000001U
+#define MCPWM_CAP0_INT_CLR_S  27
+/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_CLR    (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
+#define MCPWM_CAP1_INT_CLR_V  0x00000001U
+#define MCPWM_CAP1_INT_CLR_S  28
+/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_CLR    (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
+#define MCPWM_CAP2_INT_CLR_V  0x00000001U
+#define MCPWM_CAP2_INT_CLR_S  29
+
+/** MCPWM_EVT_EN_REG register
+ *  Event enable register
+ */
+#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120)
+/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
+#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
+#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_STOP_EN_S  0
+/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
+#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
+#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_STOP_EN_S  1
+/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
+#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
+#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_STOP_EN_S  2
+/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable timer0 equal zero event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
+#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
+#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
+/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable timer1 equal zero event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
+#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
+#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
+/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable timer2 equal zero event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
+#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
+#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
+/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable timer0 equal period event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
+#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
+#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEP_EN_S  6
+/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable timer1 equal period event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
+#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
+#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEP_EN_S  7
+/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable timer2 equal period event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
+#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
+#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEP_EN_S  8
+/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal a event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
+#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
+#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEA_EN_S  9
+/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal a event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
+#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
+#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEA_EN_S  10
+/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal a event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
+#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
+#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEA_EN_S  11
+/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal b event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
+#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
+#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEB_EN_S  12
+/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal b event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
+#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
+#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEB_EN_S  13
+/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal b event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
+#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
+#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEB_EN_S  14
+/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_F0_EN    (BIT(15))
+#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
+#define MCPWM_EVT_F0_EN_V  0x00000001U
+#define MCPWM_EVT_F0_EN_S  15
+/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_F1_EN    (BIT(16))
+#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
+#define MCPWM_EVT_F1_EN_V  0x00000001U
+#define MCPWM_EVT_F1_EN_S  16
+/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_F2_EN    (BIT(17))
+#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
+#define MCPWM_EVT_F2_EN_V  0x00000001U
+#define MCPWM_EVT_F2_EN_S  17
+/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
+#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
+#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F0_CLR_EN_S  18
+/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
+#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
+#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F1_CLR_EN_S  19
+/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
+#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
+#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F2_CLR_EN_S  20
+/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
+#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
+#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_CBC_EN_S  21
+/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
+#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
+#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_CBC_EN_S  22
+/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
+#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
+#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_CBC_EN_S  23
+/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
+#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
+#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_OST_EN_S  24
+/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
+#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
+#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_OST_EN_S  25
+/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
+#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
+#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_OST_EN_S  26
+/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_CAP0_EN    (BIT(27))
+#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
+#define MCPWM_EVT_CAP0_EN_V  0x00000001U
+#define MCPWM_EVT_CAP0_EN_S  27
+/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_CAP1_EN    (BIT(28))
+#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
+#define MCPWM_EVT_CAP1_EN_V  0x00000001U
+#define MCPWM_EVT_CAP1_EN_S  28
+/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_CAP2_EN    (BIT(29))
+#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
+#define MCPWM_EVT_CAP2_EN_V  0x00000001U
+#define MCPWM_EVT_CAP2_EN_S  29
+
+/** MCPWM_TASK_EN_REG register
+ *  Task enable register
+ */
+#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124)
+/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
+#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
+#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
+/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
+#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
+#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
+/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
+#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
+#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
+/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
+#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
+#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
+/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
+#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
+#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
+/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
+#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
+#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
+/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable all PWM generate stop task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
+#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
+#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
+#define MCPWM_TASK_GEN_STOP_EN_S  6
+/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
+#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
+#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
+/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
+#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
+#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
+/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
+#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
+#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
+/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable timer0 period update task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
+/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable timer1 period update task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
+/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable timer2 period update task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
+/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
+#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
+#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ0_OST_EN_S  13
+/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
+#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
+#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ1_OST_EN_S  14
+/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
+#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
+#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ2_OST_EN_S  15
+/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
+#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
+#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR0_OST_EN_S  16
+/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
+#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
+#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR1_OST_EN_S  17
+/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
+#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
+#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR2_OST_EN_S  18
+/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CAP0_EN    (BIT(19))
+#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
+#define MCPWM_TASK_CAP0_EN_V  0x00000001U
+#define MCPWM_TASK_CAP0_EN_S  19
+/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CAP1_EN    (BIT(20))
+#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
+#define MCPWM_TASK_CAP1_EN_V  0x00000001U
+#define MCPWM_TASK_CAP1_EN_S  20
+/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CAP2_EN    (BIT(21))
+#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
+#define MCPWM_TASK_CAP2_EN_V  0x00000001U
+#define MCPWM_TASK_CAP2_EN_S  21
+
+/** MCPWM_EVT_EN2_REG register
+ *  Event enable register2
+ */
+#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x128)
+/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEE1_EN    (BIT(0))
+#define MCPWM_EVT_OP0_TEE1_EN_M  (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S)
+#define MCPWM_EVT_OP0_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEE1_EN_S  0
+/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEE1_EN    (BIT(1))
+#define MCPWM_EVT_OP1_TEE1_EN_M  (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S)
+#define MCPWM_EVT_OP1_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEE1_EN_S  1
+/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEE1_EN    (BIT(2))
+#define MCPWM_EVT_OP2_TEE1_EN_M  (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S)
+#define MCPWM_EVT_OP2_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEE1_EN_S  2
+/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEE2_EN    (BIT(3))
+#define MCPWM_EVT_OP0_TEE2_EN_M  (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S)
+#define MCPWM_EVT_OP0_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEE2_EN_S  3
+/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEE2_EN    (BIT(4))
+#define MCPWM_EVT_OP1_TEE2_EN_M  (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S)
+#define MCPWM_EVT_OP1_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEE2_EN_S  4
+/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEE2_EN    (BIT(5))
+#define MCPWM_EVT_OP2_TEE2_EN_M  (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S)
+#define MCPWM_EVT_OP2_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEE2_EN_S  5
+
+/** MCPWM_OP0_TSTMP_E1_REG register
+ *  Generator0 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x12c)
+/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator0 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
+#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_S  0
+
+/** MCPWM_OP0_TSTMP_E2_REG register
+ *  Generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x130)
+/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP0_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E2_M  (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S)
+#define MCPWM_OP0_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E2_S  0
+
+/** MCPWM_OP1_TSTMP_E1_REG register
+ *  Generator1 timer stamp E1 value register
+ */
+#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x134)
+/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator1 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
+#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_S  0
+
+/** MCPWM_OP1_TSTMP_E2_REG register
+ *  Generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x138)
+/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP1_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E2_M  (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S)
+#define MCPWM_OP1_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E2_S  0
+
+/** MCPWM_OP2_TSTMP_E1_REG register
+ *  Generator2 timer stamp E1 value register
+ */
+#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x13c)
+/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator2 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
+#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_S  0
+
+/** MCPWM_OP2_TSTMP_E2_REG register
+ *  Generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x140)
+/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP2_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E2_M  (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S)
+#define MCPWM_OP2_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E2_S  0
+
+/** MCPWM_CLK_REG register
+ *  Global configuration register
+ */
+#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x144)
+/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+ *  when application writes registers\\1: Force open the clock gate for register
+ */
+#define MCPWM_CLK_EN    (BIT(0))
+#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
+#define MCPWM_CLK_EN_V  0x00000001U
+#define MCPWM_CLK_EN_S  0
+
+/** MCPWM_VERSION_REG register
+ *  Version register.
+ */
+#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x148)
+/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968;
+ *  Configures the version.
+ */
+#define MCPWM_DATE    0x0FFFFFFFU
+#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
+#define MCPWM_DATE_V  0x0FFFFFFFU
+#define MCPWM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/pwm_struct.h b/components/soc/esp32p4/include/soc/pwm_struct.h
new file mode 100644
index 0000000000..f48bd4cf69
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/pwm_struct.h
@@ -0,0 +1,2166 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_cfg */
+/** Type of clk_cfg register
+ *  PWM clock prescaler register.
+ */
+typedef union {
+    struct {
+        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
+         *  (PWM_CLK_PRESCALE + 1).
+         */
+        uint32_t clk_prescale:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_clk_cfg_reg_t;
+
+
+/** Group: timer */
+/** Type of timern_cfg0 register
+ *  PWM timern period and update method configuration register.
+ */
+typedef union {
+    struct {
+        /** timer0_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of timern, so that the period of PT0_clk = Period of
+         *  PWM_clk * (PWM_TIMERn_PRESCALE + 1)
+         */
+        uint32_t timer0_prescale:8;
+        /** timer0_period : R/W; bitpos: [23:8]; default: 255;
+         *  Configures the period shadow of PWM timern
+         */
+        uint32_t timer0_period:16;
+        /** timer0_period_upmethod : R/W; bitpos: [25:24]; default: 0;
+         *  Configures the update method for active register of PWM timern period.\\0:
+         *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+         *  zero event
+         */
+        uint32_t timer0_period_upmethod:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg0_reg_t;
+
+/** Type of timer0_cfg1 register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+typedef union {
+    struct {
+        /** timer0_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+         *  stops at the next TEP.\\TEP here and below means the event that happens when the
+         *  timer equals to period
+         */
+        uint32_t timer0_start:3;
+        /** timer0_mod : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+         *  Decrease mode\\3: Up-down mode
+         */
+        uint32_t timer0_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg1_reg_t;
+
+/** Type of timer0_sync register
+ *  PWM timer$n sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer0_synci_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer$n reloading with phase on sync input
+         *  event is enabled.\\0: Disable\\1: Enable
+         */
+        uint32_t timer0_synci_en:1;
+        /** timer0_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of software sync. Toggling this bit will trigger a
+         *  software sync.
+         */
+        uint32_t timer0_sync_sw:1;
+        /** timer0_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+         *  Invalid, sync_out selects noting
+         */
+        uint32_t timer0_synco_sel:2;
+        /** timer0_phase : R/W; bitpos: [19:4]; default: 0;
+         *  Configures the phase for timer$n reload on sync event.
+         */
+        uint32_t timer0_phase:16;
+        /** timer0_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+         *  Increase\\1: Decrease
+         */
+        uint32_t timer0_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timer_sync_reg_t;
+
+/** Type of timer0_status register
+ *  PWM timer$n status register.
+ */
+typedef union {
+    struct {
+        /** timer0_value : RO; bitpos: [15:0]; default: 0;
+         *  Represents current PWM timer$n counter value.
+         */
+        uint32_t timer0_value:16;
+        /** timer0_direction : RO; bitpos: [16]; default: 0;
+         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+         */
+        uint32_t timer0_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timer_status_reg_t;
+
+/** Type of timer1_cfg1 register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+typedef union {
+    struct {
+        /** timer1_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+         *  stops at the next TEP.\\TEP here and below means the event that happens when the
+         *  timer equals to period
+         */
+        uint32_t timer1_start:3;
+        /** timer1_mod : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+         *  Decrease mode\\3: Up-down mode
+         */
+        uint32_t timer1_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timer1_cfg1_reg_t;
+
+/** Type of timer1_sync register
+ *  PWM timer$n sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer1_synci_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer$n reloading with phase on sync input
+         *  event is enabled.\\0: Disable\\1: Enable
+         */
+        uint32_t timer1_synci_en:1;
+        /** timer1_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of software sync. Toggling this bit will trigger a
+         *  software sync.
+         */
+        uint32_t timer1_sync_sw:1;
+        /** timer1_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+         *  Invalid, sync_out selects noting
+         */
+        uint32_t timer1_synco_sel:2;
+        /** timer1_phase : R/W; bitpos: [19:4]; default: 0;
+         *  Configures the phase for timer$n reload on sync event.
+         */
+        uint32_t timer1_phase:16;
+        /** timer1_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+         *  Increase\\1: Decrease
+         */
+        uint32_t timer1_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timer1_sync_reg_t;
+
+/** Type of timer1_status register
+ *  PWM timer$n status register.
+ */
+typedef union {
+    struct {
+        /** timer1_value : RO; bitpos: [15:0]; default: 0;
+         *  Represents current PWM timer$n counter value.
+         */
+        uint32_t timer1_value:16;
+        /** timer1_direction : RO; bitpos: [16]; default: 0;
+         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+         */
+        uint32_t timer1_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timer1_status_reg_t;
+
+/** Type of timer2_cfg1 register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+typedef union {
+    struct {
+        /** timer2_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+         *  stops at the next TEP.\\TEP here and below means the event that happens when the
+         *  timer equals to period
+         */
+        uint32_t timer2_start:3;
+        /** timer2_mod : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+         *  Decrease mode\\3: Up-down mode
+         */
+        uint32_t timer2_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timer2_cfg1_reg_t;
+
+/** Type of timer2_sync register
+ *  PWM timer$n sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer2_synci_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer$n reloading with phase on sync input
+         *  event is enabled.\\0: Disable\\1: Enable
+         */
+        uint32_t timer2_synci_en:1;
+        /** timer2_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of software sync. Toggling this bit will trigger a
+         *  software sync.
+         */
+        uint32_t timer2_sync_sw:1;
+        /** timer2_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+         *  Invalid, sync_out selects noting
+         */
+        uint32_t timer2_synco_sel:2;
+        /** timer2_phase : R/W; bitpos: [19:4]; default: 0;
+         *  Configures the phase for timer$n reload on sync event.
+         */
+        uint32_t timer2_phase:16;
+        /** timer2_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+         *  Increase\\1: Decrease
+         */
+        uint32_t timer2_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timer2_sync_reg_t;
+
+/** Type of timer2_status register
+ *  PWM timer$n status register.
+ */
+typedef union {
+    struct {
+        /** timer2_value : RO; bitpos: [15:0]; default: 0;
+         *  Represents current PWM timer$n counter value.
+         */
+        uint32_t timer2_value:16;
+        /** timer2_direction : RO; bitpos: [16]; default: 0;
+         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+         */
+        uint32_t timer2_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timer2_status_reg_t;
+
+
+/** Group: timer_synci_cfg */
+/** Type of timer_synci_cfg register
+ *  Synchronization input selection register for PWM timers.
+ */
+typedef union {
+    struct {
+        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer0_syncisel:3;
+        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
+         *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer1_syncisel:3;
+        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer2_syncisel:3;
+        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci0_invert:1;
+        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci1_invert:1;
+        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci2_invert:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} mcpwm_timer_synci_cfg_reg_t;
+
+
+/** Group: operator_timersel */
+/** Type of operator_timersel register
+ *  PWM operator's timer select register
+ */
+typedef union {
+    struct {
+        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator0_timersel:2;
+        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator1_timersel:2;
+        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator2_timersel:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_operator_timersel_reg_t;
+
+
+/** Group: operators */
+/** Type of genn_stmp_cfg register
+ *  Generatorn time stamp registers A and B transfer status and update method register
+ */
+typedef union {
+    struct {
+        /** cmpr0_a_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the update method for PWM generator n time stamp A's active
+         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmpr0_a_upmethod:4;
+        /** cmpr0_b_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the update method for PWM generator n time stamp B's active
+         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmpr0_b_upmethod:4;
+        /** cmpr0_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
+         *  Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0:
+         *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+         *  reg is filled and waiting to be transferred to A's active reg
+         */
+        uint32_t cmpr0_a_shdw_full:1;
+        /** cmpr0_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
+         *  Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0:
+         *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+         *  reg is filled and waiting to be transferred to B's active reg
+         */
+        uint32_t cmpr0_b_shdw_full:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_stmp_cfg_reg_t;
+
+/** Type of gen0_tstmp_a register
+ *  Generator$n time stamp A's shadow register
+ */
+typedef union {
+    struct {
+        /** cmpr0_a : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the value of PWM generator $n time stamp A's shadow register.
+         */
+        uint32_t cmpr0_a:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_tstmp_a_reg_t;
+
+/** Type of gen0_tstmp_b register
+ *  Generator$n time stamp B's shadow register
+ */
+typedef union {
+    struct {
+        /** cmpr0_b : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the value of PWM generator $n time stamp B's shadow register.
+         */
+        uint32_t cmpr0_b:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_tstmp_b_reg_t;
+
+/** Type of gen0_cfg0 register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+typedef union {
+    struct {
+        /** gen0_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for PWM generator $n's active register.\\0:
+         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t gen0_cfg_upmethod:4;
+        /** gen0_t0_sel : R/W; bitpos: [6:4]; default: 0;
+         *  Configures source selection for PWM generator $n event_t0, take effect
+         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+         *  Invalid, Select nothing
+         */
+        uint32_t gen0_t0_sel:3;
+        /** gen0_t1_sel : R/W; bitpos: [9:7]; default: 0;
+         *  Configures source selection for PWM generator $n event_t1, take effect
+         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+         *  Invalid, Select nothing
+         */
+        uint32_t gen0_t1_sel:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_cfg0_reg_t;
+
+/** Type of gen0_force register
+ *  Generator$n output signal force mode register.
+ */
+typedef union {
+    struct {
+        /** gen0_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
+         *  Configures update method for continuous software force of PWM generator$n.\\0:
+         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+         *  update. TEA/B here and below means an event generated when the timer's value equals
+         *  to that of register A/B.
+         */
+        uint32_t gen0_cntuforce_upmethod:6;
+        /** gen0_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+         *  High\\3: Disabled
+         */
+        uint32_t gen0_a_cntuforce_mode:2;
+        /** gen0_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+         *  High\\3: Disabled
+         */
+        uint32_t gen0_b_cntuforce_mode:2;
+        /** gen0_a_nciforce : R/W; bitpos: [10]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for
+         *  PWM$n A, a toggle will trigger a force event.
+         */
+        uint32_t gen0_a_nciforce:1;
+        /** gen0_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+         *  Disabled\\1: Low\\2: High\\3: Disabled
+         */
+        uint32_t gen0_a_nciforce_mode:2;
+        /** gen0_b_nciforce : R/W; bitpos: [13]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for
+         *  PWM$n B, a toggle will trigger a force event.
+         */
+        uint32_t gen0_b_nciforce:1;
+        /** gen0_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+         *  Disabled\\1: Low\\2: High\\3: Disabled
+         */
+        uint32_t gen0_b_nciforce_mode:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_force_reg_t;
+
+/** Type of gen0_a register
+ *  PWM$n output signal A actions configuration register
+ */
+typedef union {
+    struct {
+        /** gen0_a_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_utez:2;
+        /** gen0_a_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_utep:2;
+        /** gen0_a_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_utea:2;
+        /** gen0_a_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_uteb:2;
+        /** gen0_a_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_ut0:2;
+        /** gen0_a_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_ut1:2;
+        /** gen0_a_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_dtez:2;
+        /** gen0_a_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_dtep:2;
+        /** gen0_a_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_dtea:2;
+        /** gen0_a_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_dteb:2;
+        /** gen0_a_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_dt0:2;
+        /** gen0_a_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_a_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_gen_a_reg_t;
+
+/** Type of gen0_b register
+ *  PWM$n output signal B actions configuration register
+ */
+typedef union {
+    struct {
+        /** gen0_b_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_utez:2;
+        /** gen0_b_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_utep:2;
+        /** gen0_b_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_utea:2;
+        /** gen0_b_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_uteb:2;
+        /** gen0_b_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_ut0:2;
+        /** gen0_b_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_ut1:2;
+        /** gen0_b_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_dtez:2;
+        /** gen0_b_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_dtep:2;
+        /** gen0_b_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_dtea:2;
+        /** gen0_b_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_dteb:2;
+        /** gen0_b_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_dt0:2;
+        /** gen0_b_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen0_b_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_gen_b_reg_t;
+
+/** Type of dt0_cfg register
+ *  Dead time configuration register
+ */
+typedef union {
+    struct {
+        /** db0_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for FED (Falling edge delay) active register.\\0:
+         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t db0_fed_upmethod:4;
+        /** db0_red_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures update method for RED (rising edge delay) active register.\\0:
+         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t db0_red_upmethod:4;
+        /** db0_deb_mode : R/W; bitpos: [8]; default: 0;
+         *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+         *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+         */
+        uint32_t db0_deb_mode:1;
+        /** db0_a_outswap : R/W; bitpos: [9]; default: 0;
+         *  Configures S6 in table.
+         */
+        uint32_t db0_a_outswap:1;
+        /** db0_b_outswap : R/W; bitpos: [10]; default: 0;
+         *  Configures S7 in table.
+         */
+        uint32_t db0_b_outswap:1;
+        /** db0_red_insel : R/W; bitpos: [11]; default: 0;
+         *  Configures S4 in table.
+         */
+        uint32_t db0_red_insel:1;
+        /** db0_fed_insel : R/W; bitpos: [12]; default: 0;
+         *  Configures S5 in table.
+         */
+        uint32_t db0_fed_insel:1;
+        /** db0_red_outinvert : R/W; bitpos: [13]; default: 0;
+         *  Configures S2 in table.
+         */
+        uint32_t db0_red_outinvert:1;
+        /** db0_fed_outinvert : R/W; bitpos: [14]; default: 0;
+         *  Configures S3 in table.
+         */
+        uint32_t db0_fed_outinvert:1;
+        /** db0_a_outbypass : R/W; bitpos: [15]; default: 1;
+         *  Configures S1 in table.
+         */
+        uint32_t db0_a_outbypass:1;
+        /** db0_b_outbypass : R/W; bitpos: [16]; default: 1;
+         *  Configures S0 in table.
+         */
+        uint32_t db0_b_outbypass:1;
+        /** db0_clk_sel : R/W; bitpos: [17]; default: 0;
+         *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+         */
+        uint32_t db0_clk_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} mcpwm_dt_cfg_reg_t;
+
+/** Type of dt0_fed_cfg register
+ *  Falling edge delay (FED) shadow register
+ */
+typedef union {
+    struct {
+        /** db0_fed : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for FED.
+         */
+        uint32_t db0_fed:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_fed_cfg_reg_t;
+
+/** Type of dt0_red_cfg register
+ *  Rising edge delay (RED) shadow register
+ */
+typedef union {
+    struct {
+        /** db0_red : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for RED.
+         */
+        uint32_t db0_red:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_red_cfg_reg_t;
+
+/** Type of carrier0_cfg register
+ *  Carrier$n configuration register
+ */
+typedef union {
+    struct {
+        /** chopper0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+         */
+        uint32_t chopper0_en:1;
+        /** chopper0_prescale : R/W; bitpos: [4:1]; default: 0;
+         *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+         *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+         */
+        uint32_t chopper0_prescale:4;
+        /** chopper0_duty : R/W; bitpos: [7:5]; default: 0;
+         *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+         */
+        uint32_t chopper0_duty:3;
+        /** chopper0_oshtwth : R/W; bitpos: [11:8]; default: 0;
+         *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+         */
+        uint32_t chopper0_oshtwth:4;
+        /** chopper0_out_invert : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+         *  submodule.\\0: Normal\\1: Invert
+         */
+        uint32_t chopper0_out_invert:1;
+        /** chopper0_in_invert : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+         *  submodule.\\0: Normal\\1: Invert
+         */
+        uint32_t chopper0_in_invert:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} mcpwm_carrier_cfg_reg_t;
+
+/** Type of fh0_cfg0 register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+typedef union {
+    struct {
+        /** tz0_sw_cbc : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_sw_cbc:1;
+        /** tz0_f2_cbc : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_f2_cbc:1;
+        /** tz0_f1_cbc : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_f1_cbc:1;
+        /** tz0_f0_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_f0_cbc:1;
+        /** tz0_sw_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable software force one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_sw_ost:1;
+        /** tz0_f2_ost : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_f2_ost:1;
+        /** tz0_f1_ost : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_f1_ost:1;
+        /** tz0_f0_ost : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz0_f0_ost:1;
+        /** tz0_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_a_cbc_d:2;
+        /** tz0_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_a_cbc_u:2;
+        /** tz0_a_ost_d : R/W; bitpos: [13:12]; default: 0;
+         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_a_ost_d:2;
+        /** tz0_a_ost_u : R/W; bitpos: [15:14]; default: 0;
+         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_a_ost_u:2;
+        /** tz0_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_b_cbc_d:2;
+        /** tz0_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_b_cbc_u:2;
+        /** tz0_b_ost_d : R/W; bitpos: [21:20]; default: 0;
+         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_b_ost_d:2;
+        /** tz0_b_ost_u : R/W; bitpos: [23:22]; default: 0;
+         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz0_b_ost_u:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg0_reg_t;
+
+/** Type of fh0_cfg1 register
+ *  Software triggers for fault handler actions configuration register
+ */
+typedef union {
+    struct {
+        /** tz0_clr_ost : R/W; bitpos: [0]; default: 0;
+         *  Configures the generation of software one-shot mode action clear. A toggle
+         *  (software negate its value) triggers a clear for on going one-shot mode action.
+         */
+        uint32_t tz0_clr_ost:1;
+        /** tz0_cbcpulse : R/W; bitpos: [2:1]; default: 0;
+         *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+         *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+         */
+        uint32_t tz0_cbcpulse:2;
+        /** tz0_force_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of software cycle-by-cycle mode action. A toggle
+         *  (software negate its value) triggers a cycle-by-cycle mode action.
+         */
+        uint32_t tz0_force_cbc:1;
+        /** tz0_force_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures the generation of software one-shot mode action. A toggle (software
+         *  negate its value) triggers a one-shot mode action.
+         */
+        uint32_t tz0_force_ost:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg1_reg_t;
+
+/** Type of fh0_status register
+ *  Fault events status register
+ */
+typedef union {
+    struct {
+        /** tz0_cbc_on : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+         *  action\\1: On going
+         */
+        uint32_t tz0_cbc_on:1;
+        /** tz0_ost_on : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+         *  going
+         */
+        uint32_t tz0_ost_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mcpwm_fh_status_reg_t;
+
+/** Group: fault_detect */
+/** Type of fault_detect register
+ *  Fault detection configuration and status register
+ */
+typedef union {
+    struct {
+        /** f0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f0_en:1;
+        /** f1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f1_en:1;
+        /** f2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f2_en:1;
+        /** f0_pole : R/W; bitpos: [3]; default: 0;
+         *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f0_pole:1;
+        /** f1_pole : R/W; bitpos: [4]; default: 0;
+         *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f1_pole:1;
+        /** f2_pole : R/W; bitpos: [5]; default: 0;
+         *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f2_pole:1;
+        /** event_f0 : RO; bitpos: [6]; default: 0;
+         *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f0:1;
+        /** event_f1 : RO; bitpos: [7]; default: 0;
+         *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f1:1;
+        /** event_f2 : RO; bitpos: [8]; default: 0;
+         *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f2:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} mcpwm_fault_detect_reg_t;
+
+
+/** Group: cap_timer_cfg */
+/** Type of cap_timer_cfg register
+ *  Capture timer configuration register
+ */
+typedef union {
+    struct {
+        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
+         */
+        uint32_t cap_timer_en:1;
+        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
+         */
+        uint32_t cap_synci_en:1;
+        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
+         *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
+         *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
+         *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
+         */
+        uint32_t cap_synci_sel:3;
+        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
+         *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
+         *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
+         *  value in phase register
+         */
+        uint32_t cap_sync_sw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_cfg_reg_t;
+
+
+/** Group: cap_timer_phase */
+/** Type of cap_timer_phase register
+ *  Capture timer sync phase register
+ */
+typedef union {
+    struct {
+        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
+         *  Configures phase value for capture timer sync operation.
+         */
+        uint32_t cap_phase:32;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_phase_reg_t;
+
+
+/** Group: cap_chn_cfg */
+/** Type of cap_chn_cfg register
+ *  Capture channel n configuration register
+ */
+typedef union {
+    struct {
+        /** cap0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable
+         */
+        uint32_t cap0_en:1;
+        /** cap0_mode : R/W; bitpos: [2:1]; default: 0;
+         *  Configures which edge of capture on channel n after prescaling is used.\\0:
+         *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+         *  Enable capture on the positive edge
+         */
+        uint32_t cap0_mode:2;
+        /** cap0_prescale : R/W; bitpos: [10:3]; default: 0;
+         *  Configures prescale value on possitive edge of CAPn. Prescale value =
+         *  PWM_CAPn_PRESCALE + 1
+         */
+        uint32_t cap0_prescale:8;
+        /** cap0_in_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0:
+         *  Normal\\1: Invert
+         */
+        uint32_t cap0_in_invert:1;
+        /** cap0_sw : WT; bitpos: [12]; default: 0;
+         *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+         *  software forced capture on channel n
+         */
+        uint32_t cap0_sw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_cfg_reg_t;
+
+
+/** Group: cap_chn */
+/** Type of cap_chn register
+ *  CAPn capture value register
+ */
+typedef union {
+    struct {
+        /** cap0_value : RO; bitpos: [31:0]; default: 0;
+         *  Represents value of last capture on CAPn
+         */
+        uint32_t cap0_value:32;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_reg_t;
+
+
+/** Group: cap_status */
+/** Type of cap_status register
+ *  Last capture trigger edge information register
+ */
+typedef union {
+    struct {
+        /** cap0_edge : RO; bitpos: [0]; default: 0;
+         *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap0_edge:1;
+        /** cap1_edge : RO; bitpos: [1]; default: 0;
+         *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap1_edge:1;
+        /** cap2_edge : RO; bitpos: [2]; default: 0;
+         *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap2_edge:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} mcpwm_cap_status_reg_t;
+
+
+/** Group: update_cfg */
+/** Type of update_cfg register
+ *  Generator Update configuration register
+ */
+typedef union {
+    struct {
+        /** global_up_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not to enable global update for all active registers in MCPWM
+         *  module.\\0: Disable\\1: Enable
+         */
+        uint32_t global_up_en:1;
+        /** global_force_up : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of global forced update for all active registers in MCPWM
+         *  module. A toggle (software invert its value) will trigger a global forced update.
+         *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
+         */
+        uint32_t global_force_up:1;
+        /** op0_up_en : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op0_up_en:1;
+        /** op0_force_up : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator0. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
+         */
+        uint32_t op0_force_up:1;
+        /** op1_up_en : R/W; bitpos: [4]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op1_up_en:1;
+        /** op1_force_up : R/W; bitpos: [5]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator1. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
+         */
+        uint32_t op1_force_up:1;
+        /** op2_up_en : R/W; bitpos: [6]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op2_up_en:1;
+        /** op2_force_up : R/W; bitpos: [7]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator2. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
+         */
+        uint32_t op2_force_up:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_update_cfg_reg_t;
+
+
+/** Group: int_ena */
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_ena:1;
+        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_ena:1;
+        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_ena:1;
+        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_ena:1;
+        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_ena:1;
+        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_ena:1;
+        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_ena:1;
+        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_ena:1;
+        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_ena:1;
+        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_ena:1;
+        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_ena:1;
+        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_ena:1;
+        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_ena:1;
+        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_ena:1;
+        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_ena:1;
+        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
+         */
+        uint32_t cmpr0_tea_int_ena:1;
+        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
+         */
+        uint32_t cmpr1_tea_int_ena:1;
+        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
+         */
+        uint32_t cmpr2_tea_int_ena:1;
+        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
+         */
+        uint32_t cmpr0_teb_int_ena:1;
+        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
+         */
+        uint32_t cmpr1_teb_int_ena:1;
+        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
+         */
+        uint32_t cmpr2_teb_int_ena:1;
+        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM0.
+         */
+        uint32_t tz0_cbc_int_ena:1;
+        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM1.
+         */
+        uint32_t tz1_cbc_int_ena:1;
+        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM2.
+         */
+        uint32_t tz2_cbc_int_ena:1;
+        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_ena:1;
+        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_ena:1;
+        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_ena:1;
+        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_ena:1;
+        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_ena:1;
+        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_ena:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_ena_reg_t;
+
+
+/** Group: int_raw */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  0 stops.
+         */
+        uint32_t timer0_stop_int_raw:1;
+        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  1 stops.
+         */
+        uint32_t timer1_stop_int_raw:1;
+        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  2 stops.
+         */
+        uint32_t timer2_stop_int_raw:1;
+        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEZ event.
+         */
+        uint32_t timer0_tez_int_raw:1;
+        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEZ event.
+         */
+        uint32_t timer1_tez_int_raw:1;
+        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEZ event.
+         */
+        uint32_t timer2_tez_int_raw:1;
+        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEP event.
+         */
+        uint32_t timer0_tep_int_raw:1;
+        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEP event.
+         */
+        uint32_t timer1_tep_int_raw:1;
+        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEP event.
+         */
+        uint32_t timer2_tep_int_raw:1;
+        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  starts.
+         */
+        uint32_t fault0_int_raw:1;
+        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  starts.
+         */
+        uint32_t fault1_int_raw:1;
+        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  starts.
+         */
+        uint32_t fault2_int_raw:1;
+        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  clears.
+         */
+        uint32_t fault0_clr_int_raw:1;
+        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  clears.
+         */
+        uint32_t fault1_clr_int_raw:1;
+        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  clears.
+         */
+        uint32_t fault2_clr_int_raw:1;
+        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_raw:1;
+        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_raw:1;
+        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_raw:1;
+        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_raw:1;
+        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_raw:1;
+        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_raw:1;
+        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_raw:1;
+        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_raw:1;
+        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_raw:1;
+        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_raw:1;
+        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_raw:1;
+        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_raw:1;
+        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP0.
+         */
+        uint32_t cap0_int_raw:1;
+        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP1.
+         */
+        uint32_t cap1_int_raw:1;
+        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP2.
+         */
+        uint32_t cap2_int_raw:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_raw_reg_t;
+
+
+/** Group: int_st */
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 0 stops.
+         */
+        uint32_t timer0_stop_int_st:1;
+        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 1 stops.
+         */
+        uint32_t timer1_stop_int_st:1;
+        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 2 stops.
+         */
+        uint32_t timer2_stop_int_st:1;
+        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_st:1;
+        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_st:1;
+        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_st:1;
+        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_st:1;
+        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_st:1;
+        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_st:1;
+        /** fault0_int_st : RO; bitpos: [9]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 starts.
+         */
+        uint32_t fault0_int_st:1;
+        /** fault1_int_st : RO; bitpos: [10]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 starts.
+         */
+        uint32_t fault1_int_st:1;
+        /** fault2_int_st : RO; bitpos: [11]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 starts.
+         */
+        uint32_t fault2_int_st:1;
+        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 clears.
+         */
+        uint32_t fault0_clr_int_st:1;
+        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 clears.
+         */
+        uint32_t fault1_clr_int_st:1;
+        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 clears.
+         */
+        uint32_t fault2_clr_int_st:1;
+        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_st:1;
+        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_st:1;
+        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_st:1;
+        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_st:1;
+        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_st:1;
+        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_st:1;
+        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_st:1;
+        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_st:1;
+        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_st:1;
+        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_st:1;
+        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_st:1;
+        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_st:1;
+        /** cap0_int_st : RO; bitpos: [27]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP0.
+         */
+        uint32_t cap0_int_st:1;
+        /** cap1_int_st : RO; bitpos: [28]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP1.
+         */
+        uint32_t cap1_int_st:1;
+        /** cap2_int_st : RO; bitpos: [29]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP2.
+         */
+        uint32_t cap2_int_st:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_st_reg_t;
+
+
+/** Group: int_clr */
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_clr:1;
+        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_clr:1;
+        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_clr:1;
+        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_clr:1;
+        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_clr:1;
+        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_clr:1;
+        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_clr:1;
+        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_clr:1;
+        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_clr:1;
+        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_clr:1;
+        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_clr:1;
+        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_clr:1;
+        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_clr:1;
+        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_clr:1;
+        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_clr:1;
+        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_clr:1;
+        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_clr:1;
+        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_clr:1;
+        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_clr:1;
+        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_clr:1;
+        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_clr:1;
+        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM0.
+         */
+        uint32_t tz0_cbc_int_clr:1;
+        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM1.
+         */
+        uint32_t tz1_cbc_int_clr:1;
+        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM2.
+         */
+        uint32_t tz2_cbc_int_clr:1;
+        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_clr:1;
+        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_clr:1;
+        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_clr:1;
+        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_clr:1;
+        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_clr:1;
+        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_clr:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_clr_reg_t;
+
+
+/** Group: evt_en */
+/** Type of evt_en register
+ *  Event enable register
+ */
+typedef union {
+    struct {
+        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer0_stop_en:1;
+        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer1_stop_en:1;
+        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer2_stop_en:1;
+        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable timer0 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer0_tez_en:1;
+        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable timer1 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer1_tez_en:1;
+        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable timer2 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer2_tez_en:1;
+        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable timer0 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer0_tep_en:1;
+        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer1 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer1_tep_en:1;
+        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer2 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer2_tep_en:1;
+        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tea_en:1;
+        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tea_en:1;
+        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tea_en:1;
+        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_teb_en:1;
+        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_teb_en:1;
+        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_teb_en:1;
+        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f0_en:1;
+        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f1_en:1;
+        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f2_en:1;
+        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f0_clr_en:1;
+        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f1_clr_en:1;
+        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f2_clr_en:1;
+        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz0_cbc_en:1;
+        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz1_cbc_en:1;
+        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz2_cbc_en:1;
+        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz0_ost_en:1;
+        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz1_ost_en:1;
+        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz2_ost_en:1;
+        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap0_en:1;
+        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap1_en:1;
+        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap2_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_evt_en_reg_t;
+
+
+/** Group: task_en */
+/** Type of task_en register
+ *  Task enable register
+ */
+typedef union {
+    struct {
+        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr0_a_up_en:1;
+        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr1_a_up_en:1;
+        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr2_a_up_en:1;
+        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr0_b_up_en:1;
+        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr1_b_up_en:1;
+        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr2_b_up_en:1;
+        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable all PWM generate stop task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_gen_stop_en:1;
+        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer0_sync_en:1;
+        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer1_sync_en:1;
+        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer2_sync_en:1;
+        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable timer0 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer0_period_up_en:1;
+        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable timer1 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer1_period_up_en:1;
+        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable timer2 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer2_period_up_en:1;
+        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz0_ost_en:1;
+        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz1_ost_en:1;
+        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz2_ost_en:1;
+        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr0_ost_en:1;
+        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr1_ost_en:1;
+        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr2_ost_en:1;
+        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap0_en:1;
+        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap1_en:1;
+        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap2_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} mcpwm_task_en_reg_t;
+
+
+/** Group: evt_en2 */
+/** Type of evt_en2 register
+ *  Event enable register2
+ */
+typedef union {
+    struct {
+        /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tee1_en:1;
+        /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tee1_en:1;
+        /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tee1_en:1;
+        /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tee2_en:1;
+        /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tee2_en:1;
+        /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tee2_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_evt_en2_reg_t;
+
+
+/** Group: Configuration register */
+/** Type of opn_tstmp_e1 register
+ *  Generatorn timer stamp E1 value register
+ */
+typedef union {
+    struct {
+        /** op0_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures generatorn timer stamp E1 value register
+         */
+        uint32_t op0_tstmp_e1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_op_tstmp_e1_reg_t;
+
+/** Type of op0_tstmp_e2 register
+ *  Generator$n timer stamp E2 value register
+ */
+typedef union {
+    struct {
+        /** op0_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures generator$n timer stamp E2 value register
+         */
+        uint32_t op0_tstmp_e2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_op_tstmp_e2_reg_t;
+
+/** Type of clk register
+ *  Global configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+         *  when application writes registers\\1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mcpwm_clk_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35725968;
+         *  Configures the version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mcpwm_version_reg_t;
+
+typedef struct {
+    volatile mcpwm_timer_cfg0_reg_t cfg0;
+    volatile mcpwm_timer_cfg1_reg_t cfg1;
+    volatile mcpwm_timer_sync_reg_t sync;
+    volatile mcpwm_timer_status_reg_t status;
+} mcpwm_timer_regs_t;
+
+typedef struct {
+    volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
+    volatile mcpwm_gen_tstmp_a_reg_t gen_tstmp_a;
+    volatile mcpwm_gen_tstmp_b_reg_t gen_tstmp_b;
+    volatile mcpwm_gen_cfg0_reg_t gen_cfg0;
+    volatile mcpwm_gen_force_reg_t gen_force;
+    volatile mcpwm_gen_a_reg_t gen_a;
+    volatile mcpwm_gen_b_reg_t gen_b;
+    volatile mcpwm_dt_cfg_reg_t dt_cfg;
+    volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
+    volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg;
+    volatile mcpwm_carrier_cfg_reg_t carrier_cfg;
+    volatile mcpwm_fh_cfg0_reg_t fh_cfg0;
+    volatile mcpwm_fh_cfg1_reg_t fh_cfg1;
+    volatile mcpwm_fh_status_reg_t fh_status;
+} mcpwm_operator_reg_t;
+
+typedef struct {
+    volatile mcpwm_op_tstmp_e1_reg_t tstmp_e1;
+    volatile mcpwm_op_tstmp_e2_reg_t tstmp_e2;
+} mcpwm_operator_tstmp_reg_t;
+
+typedef struct {
+    volatile mcpwm_clk_cfg_reg_t clk_cfg;
+    volatile mcpwm_timer_regs_t timer[3];
+    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
+    volatile mcpwm_operator_timersel_reg_t operator_timersel;
+    volatile mcpwm_operator_reg_t operators[3];
+    volatile mcpwm_fault_detect_reg_t fault_detect;
+    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
+    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
+    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
+    volatile mcpwm_cap_chn_reg_t cap_chn[3];
+    volatile mcpwm_cap_status_reg_t cap_status;
+    volatile mcpwm_update_cfg_reg_t update_cfg;
+    volatile mcpwm_int_ena_reg_t int_ena;
+    volatile mcpwm_int_raw_reg_t int_raw;
+    volatile mcpwm_int_st_reg_t int_st;
+    volatile mcpwm_int_clr_reg_t int_clr;
+    volatile mcpwm_evt_en_reg_t evt_en;
+    volatile mcpwm_task_en_reg_t task_en;
+    volatile mcpwm_evt_en2_reg_t evt_en2;
+    volatile mcpwm_operator_tstmp_reg_t op_tstmp[3];
+    volatile mcpwm_clk_reg_t clk;
+    volatile mcpwm_version_reg_t version;
+} mcpwm_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h
new file mode 100644
index 0000000000..cfe4730526
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/reg_base.h
@@ -0,0 +1,229 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//#define DR_REG_PLIC_MX_BASE                     0x20001000
+//#define DR_REG_PLIC_UX_BASE                     0x20001400
+//#define DR_REG_CLINT_M_BASE                     0x20001800
+//#define DR_REG_CLINT_U_BASE                     0x20001C00
+
+/* Basic address */
+#define DR_REG_HPCPUTCP_BASE          0x3FF00000
+#define DR_REG_HPPERIPH0_BASE         0x50000000
+#define DR_REG_HPPERIPH1_BASE         0x500C0000
+#define DR_REG_LPAON_BASE             0x50110000
+#define DR_REG_LPPERIPH_BASE          0x50120000
+
+/* This is raw module base from digital team
+ * some of them may not be used in rom
+ * just keep them for a reference
+ */
+/*
+ * @module: CPU-PERIPHERAL
+ *
+ * @base: 0x3FF00000
+ *
+ * @size: 128KB
+ */
+#define DR_REG_TRACE0_BASE            (DR_REG_HPCPUTCP_BASE + 0x4000)
+#define DR_REG_TRACE1_BASE            (DR_REG_HPCPUTCP_BASE + 0x5000)
+#define DR_REG_CPU_BUS_MON_BASE       (DR_REG_HPCPUTCP_BASE + 0x6000)
+#define DR_REG_L2MEM_MON_BASE         (DR_REG_HPCPUTCP_BASE + 0xE000)
+#define DR_REG_TCM_MON_BASE           (DR_REG_HPCPUTCP_BASE + 0xF000)
+#define DR_REG_CACHE_BASE             (DR_REG_HPCPUTCP_BASE + 0x10000)
+
+/*
+ * @module: PERIPHERAL0
+ *
+ * @base: 0x50000000
+ *
+ * @size: 768KB
+ */
+#define DR_REG_USB2_BASE              (DR_REG_HPPERIPH0_BASE + 0x0)
+#define DR_REG_USB11_BASE             (DR_REG_HPPERIPH0_BASE + 0x40000)
+#define DR_REG_USB_WRAP_BASE          (DR_REG_HPPERIPH0_BASE + 0x80000)
+#define DR_REG_GDMA_BASE              (DR_REG_HPPERIPH0_BASE + 0x81000)
+#define DR_REG_REGDMA_BASE            (DR_REG_HPPERIPH0_BASE + 0x82000)
+#define DR_REG_SDMMC_BASE             (DR_REG_HPPERIPH0_BASE + 0x83000)
+#define DR_REG_H264_CORE_BASE         (DR_REG_HPPERIPH0_BASE + 0x84000)
+#define DR_REG_AHB_PDMA_BASE          (DR_REG_HPPERIPH0_BASE + 0x85000)
+#define DR_REG_JPEG_BASE              (DR_REG_HPPERIPH0_BASE + 0x86000)
+#define DR_REG_PPA_BASE               (DR_REG_HPPERIPH0_BASE + 0x87000)
+#define DR_REG_DMA2D_BASE             (DR_REG_HPPERIPH0_BASE + 0x88000)
+#define DR_REG_KEY_MANAGER_BASE       (DR_REG_HPPERIPH0_BASE + 0x89000)
+#define DR_REG_AXI_DMA_BASE           (DR_REG_HPPERIPH0_BASE + 0x8A000)
+#define DR_REG_SPI0_BASE              (DR_REG_HPPERIPH0_BASE + 0x8C000)
+#define DR_REG_SPI1_BASE              (DR_REG_HPPERIPH0_BASE + 0x8D000)
+#define DR_REG_PSRAM_MSPI0_BASE       (DR_REG_HPPERIPH0_BASE + 0x8E000)
+#define DR_REG_PSRAM_MSPI1_BASE       (DR_REG_HPPERIPH0_BASE + 0x8F000)
+#define DR_REG_CRYPTO_BASE            (DR_REG_HPPERIPH0_BASE + 0x90000)
+#define DR_REG_GMAC_BASE              (DR_REG_HPPERIPH0_BASE + 0x98000)
+#define DR_REG_USBPHY_BASE            (DR_REG_HPPERIPH0_BASE + 0x9C000)
+#define DR_REG_DDRPHY_BASE            (DR_REG_HPPERIPH0_BASE + 0x9D000)
+#define DR_REG_PVT_BASE               (DR_REG_HPPERIPH0_BASE + 0x9E000)
+#define DR_REG_CSI_HOST_BASE          (DR_REG_HPPERIPH0_BASE + 0x9F000)
+#define DR_REG_DSI_HOST_BASE          (DR_REG_HPPERIPH0_BASE + 0xA0000)
+#define DR_REG_ISP_BASE               (DR_REG_HPPERIPH0_BASE + 0xA1000)
+#define DR_REG_RMT_BASE               (DR_REG_HPPERIPH0_BASE + 0xA2000)
+#define DR_REG_BITSCRAM_BASE          (DR_REG_HPPERIPH0_BASE + 0xA3000)
+#define DR_REG_AXI_ICM_BASE           (DR_REG_HPPERIPH0_BASE + 0xA4000)
+#define DR_REG_HP_PERI_PMS_BASE       (DR_REG_HPPERIPH0_BASE + 0xA5000)
+#define DR_REG_LP2HP_PERI_PMS_BASE    (DR_REG_HPPERIPH0_BASE + 0xA5800)
+#define DR_REG_DMA_PMS_BASE           (DR_REG_HPPERIPH0_BASE + 0xA6000)
+#define DR_REG_H264_DMA_2D_BASE       (DR_REG_HPPERIPH0_BASE + 0xA7000)
+/*
+ * @module: PERIPHERAL1
+ *
+ * @base: 0x500C0000
+ *
+ * @size: 256KB
+ */
+#define DR_REG_MCPWM0_BASE            (DR_REG_HPPERIPH1_BASE + 0x0)
+#define DR_REG_MCPWM1_BASE            (DR_REG_HPPERIPH1_BASE + 0x1000)
+#define DR_REG_TIMG0_BASE             (DR_REG_HPPERIPH1_BASE + 0x2000)
+#define DR_REG_TIMG1_BASE             (DR_REG_HPPERIPH1_BASE + 0x3000)
+#define DR_REG_I2C0_BASE              (DR_REG_HPPERIPH1_BASE + 0x4000)
+#define DR_REG_I2C1_BASE              (DR_REG_HPPERIPH1_BASE + 0x5000)
+#define DR_REG_I2S0_BASE              (DR_REG_HPPERIPH1_BASE + 0x6000)
+#define DR_REG_I2S1_BASE              (DR_REG_HPPERIPH1_BASE + 0x7000)
+#define DR_REG_I2S2_BASE              (DR_REG_HPPERIPH1_BASE + 0x8000)
+#define DR_REG_PCNT_BASE              (DR_REG_HPPERIPH1_BASE + 0x9000)
+#define DR_REG_UART0_BASE             (DR_REG_HPPERIPH1_BASE + 0xA000)
+#define DR_REG_UART1_BASE             (DR_REG_HPPERIPH1_BASE + 0xB000)
+#define DR_REG_UART2_BASE             (DR_REG_HPPERIPH1_BASE + 0xC000)
+#define DR_REG_UART3_BASE             (DR_REG_HPPERIPH1_BASE + 0xD000)
+#define DR_REG_UART4_BASE             (DR_REG_HPPERIPH1_BASE + 0xE000)
+#define DR_REG_PARIO_BASE             (DR_REG_HPPERIPH1_BASE + 0xF000)
+#define DR_REG_SPI2_BASE              (DR_REG_HPPERIPH1_BASE + 0x10000)
+#define DR_REG_SPI3_BASE              (DR_REG_HPPERIPH1_BASE + 0x11000)
+#define DR_REG_USB2JTAG_BASE          (DR_REG_HPPERIPH1_BASE + 0x12000)
+#define DR_REG_LEDC_BASE              (DR_REG_HPPERIPH1_BASE + 0x13000)
+#define DR_REG_ETM_BASE               (DR_REG_HPPERIPH1_BASE + 0x15000)
+#define DR_REG_INTR_BASE              (DR_REG_HPPERIPH1_BASE + 0x16000)
+#define DR_REG_TWAI0_BASE             (DR_REG_HPPERIPH1_BASE + 0x17000)
+#define DR_REG_TWAI1_BASE             (DR_REG_HPPERIPH1_BASE + 0x18000)
+#define DR_REG_TWAI2_BASE             (DR_REG_HPPERIPH1_BASE + 0x19000)
+#define DR_REG_I3C_MST_BASE           (DR_REG_HPPERIPH1_BASE + 0x1A000)
+#define DR_REG_I3C_SLV_BASE           (DR_REG_HPPERIPH1_BASE + 0x1B000)
+#define DR_REG_LCDCAM_BASE            (DR_REG_HPPERIPH1_BASE + 0x1C000)
+#define DR_REG_ADC_BASE               (DR_REG_HPPERIPH1_BASE + 0x1E000)
+#define DR_REG_UHCI_BASE              (DR_REG_HPPERIPH1_BASE + 0x1F000)
+#define DR_REG_GPIO_BASE              (DR_REG_HPPERIPH1_BASE + 0x20000)
+#define DR_REG_GPIO_SD_BASE           (DR_REG_HPPERIPH1_BASE + 0x20F00)
+#define DR_REG_IO_MUX_BASE            (DR_REG_HPPERIPH1_BASE + 0x21000)
+#define DR_REG_SYSTIMER_BASE          (DR_REG_HPPERIPH1_BASE + 0x22000)
+#define DR_REG_MEM_MON_BASE           (DR_REG_HPPERIPH1_BASE + 0x23000)
+#define DR_REG_AUDIO_ADDC_BASE        (DR_REG_HPPERIPH1_BASE + 0x24000)
+#define DR_REG_HP_SYS_BASE            (DR_REG_HPPERIPH1_BASE + 0x25000)
+#define DR_REG_HP_SYS_CLKRST_BASE     (DR_REG_HPPERIPH1_BASE + 0x26000)
+
+/*
+ * @module: LP AON
+ *
+ * @base: 0x50110000
+ *
+ * @size: 64KB
+ */
+#define DR_REG_LP_SYS_BASE            (DR_REG_LPAON_BASE + 0x0)
+#define DR_REG_LP_AONCLKRST_BASE      (DR_REG_LPAON_BASE + 0x1000)
+#define DR_REG_LP_TIMER_BASE          (DR_REG_LPAON_BASE + 0x2000)
+#define DR_REG_LP_ANAPERI_BASE        (DR_REG_LPAON_BASE + 0x3000)
+#define DR_REG_LP_HUK_BASE            (DR_REG_LPAON_BASE + 0x4000)
+#define DR_REG_PMU_BASE               (DR_REG_LPAON_BASE + 0x5000)
+#define DR_REG_LP_WDT_BASE            (DR_REG_LPAON_BASE + 0x6000)
+#define DR_REG_LP_MB_BASE             (DR_REG_LPAON_BASE + 0x8000)
+#define DR_REG_RTC_BASE               (DR_REG_LPAON_BASE + 0x9000)
+
+/*
+ * @module: LP PERI
+ *
+ * @base: 0x50120000
+ *
+ * @size: 64KB
+ */
+#define DR_REG_LP_PERI_CLKRST_BASE    (DR_REG_LPPERIPH_BASE + 0x0)
+#define DR_REG_LP_PERI_BASE           (DR_REG_LPPERIPH_BASE + 0x0)
+#define DR_REG_LP_UART_BASE           (DR_REG_LPPERIPH_BASE + 0x1000)
+#define DR_REG_LP_I2C_BASE            (DR_REG_LPPERIPH_BASE + 0x2000)
+#define DR_REG_LP_SPI_BASE            (DR_REG_LPPERIPH_BASE + 0x3000)
+#define DR_REG_LP_I2C_MST_BASE        (DR_REG_LPPERIPH_BASE + 0x4000)
+#define DR_REG_LP_I2S_BASE            (DR_REG_LPPERIPH_BASE + 0x5000)
+#define DR_REG_LP_ADC_BASE            (DR_REG_LPPERIPH_BASE + 0x7000)
+#define DR_REG_LP_TOUCH_BASE          (DR_REG_LPPERIPH_BASE + 0x8000)
+#define DR_REG_LP_GPIO_BASE           (DR_REG_LPPERIPH_BASE + 0xA000)
+#define DR_REG_LP_INTR_BASE           (DR_REG_LPPERIPH_BASE + 0xC000)
+#define DR_REG_LP_IOMUX_BASE          0 // just for compile, need remove later
+#define DR_REG_EFUSE_BASE             (DR_REG_LPPERIPH_BASE + 0xD000)
+#define DR_REG_LP_PERI_PMS_BASE       (DR_REG_LPPERIPH_BASE + 0xE000)
+#define DR_REG_HP2LP_PERI_PMS_BASE    (DR_REG_LPPERIPH_BASE + 0xE800)
+#define DR_REG_LP_TSENSOR_BASE        (DR_REG_LPPERIPH_BASE + 0xF000)
+
+/* this is some module helper MACROs for quick module reference
+ * including some module(renamed) address
+ */
+#define DR_REG_UART_BASE                        DR_REG_UART0_BASE
+// ESP32P4-TODO: check this
+#define DR_REG_I2C_EXT_BASE                     0x60004000
+#define DR_REG_UHCI0_BASE                       DR_REG_UHCI_BASE
+#define DR_REG_TIMERGROUP0_BASE                 DR_REG_TIMG0_BASE
+#define DR_REG_TIMERGROUP1_BASE                 DR_REG_TIMG1_BASE
+#define DR_REG_I2S_BASE                         DR_REG_I2S0_BASE
+// ESP32P4-TODO: check this
+#define DR_REG_APB_SARADC_BASE                  0x6000E000
+#define DR_REG_USB_SERIAL_JTAG_BASE             DR_REG_USB2JTAG_BASE
+#define DR_REG_INTERRUPT_MATRIX_BASE            DR_REG_INTR_BASE
+// ESP32P4-TODO: check this
+#define DR_REG_ATOMIC_BASE                      0x60011000
+// ESP32P4-TODO: check this
+#define DR_REG_SOC_ETM_BASE                     DR_REG_ETM_BASE
+#define DR_REG_MCPWM_BASE                       DR_REG_MCPWM0_BASE
+#define DR_REG_PARL_IO_BASE                     DR_REG_PARIO_BASE
+#define DR_REG_PVT_MONITOR_BASE                 DR_REG_PVT_BASE
+#define DR_REG_AES_BASE                         (DR_REG_CRYPTO_BASE + 0x0)
+#define DR_REG_SHA_BASE                         (DR_REG_CRYPTO_BASE + 0x1000)
+#define DR_REG_RSA_BASE                         (DR_REG_CRYPTO_BASE + 0x2000)
+#define DR_REG_ECC_MULT_BASE                    (DR_REG_CRYPTO_BASE + 0x3000)
+#define DR_REG_DS_BASE                          (DR_REG_CRYPTO_BASE + 0x4000)
+#define DR_REG_DIGITAL_SIGNATURE_BASE           DR_REG_DS_BASE
+#define DR_REG_HMAC_BASE                        (DR_REG_CRYPTO_BASE + 0x5000)
+#define DR_REG_ECDSA_BASE                       (DR_REG_CRYPTO_BASE + 0x6000)
+// ESP32P4-TODO: check this
+#define DR_REG_GPIO_EXT_BASE                    0x60091f00 //ESP32C6-TODO
+#define DR_REG_MEM_MONITOR_BASE                 DR_REG_L2MEM_MON_BASE
+// ESP32P4-TODO: check this
+#define DR_REG_PAU_BASE                         0x60093000
+// ESP32P4-TODO: check this
+#define DR_REG_HP_SYSTEM_BASE                   0x60095000
+// ESP32P4-TODO: should remove this
+#define DR_REG_SYSTEM_BASE                      DR_REG_HP_SYS_BASE
+// ESP32P4-TODO: should remove this
+#define DR_REG_RTCCNTL_BASE                     0x60008000
+// ESP32P4-TODO: should remove this
+#define DR_REG_AES_XTS_BASE                     0x600CC000
+#define DR_REG_PCR_BASE                         0x60096000
+#define DR_REG_TEE_BASE                         0x60098000
+#define DR_REG_HP_APM_BASE                      0x60099000
+#define DR_REG_LP_APM0_BASE                     0x60099800
+#define DR_REG_MISC_BASE                        0x6009F000
+
+#define DR_REG_HP_CLKRST_BASE                   DR_REG_HP_SYS_CLKRST_BASE
+#define DR_REG_DSPI_MEM_BASE                    (DR_REG_PSRAM_MSPI0_BASE)
+#define DR_REG_INTERRUPT_CORE0_BASE             DR_REG_INTR_BASE
+#define DR_REG_INTERRUPT_CORE1_BASE             (DR_REG_INTR_BASE + 0x800)
+
+#define DR_REG_LP_CLKRST_BASE                   0x600B0400
+#define DR_REG_LP_AON_BASE                      0x600B1000
+#define DR_REG_LP_IO_BASE                       0x600B2000
+#define DR_REG_LP_I2C_ANA_MST_BASE              0x600B2400
+#define DR_REG_LPPERI_BASE                      DR_REG_LP_PERI_CLKRST_BASE
+#define DR_REG_LP_ANALOG_PERI_BASE              0x600B2C00
+#define DR_REG_LP_TEE_BASE                      0x600B3400
+#define DR_REG_LP_APM_BASE                      0x600B3800
+#define DR_REG_OPT_DEBUG_BASE                   0x600B3C00
+
+#define DR_REG_TRACE_BASE                       0x600C0000
+#define DR_REG_ASSIST_DEBUG_BASE                0x3FF06000
+#define DR_REG_CPU_BUS_MONITOR_BASE             0x600C2000
+#define DR_REG_INTPRI_BASE                      0x600C5000
diff --git a/components/soc/esp32p4/include/soc/regi2c_bbpll.h b/components/soc/esp32p4/include/soc/regi2c_bbpll.h
new file mode 100644
index 0000000000..0b0cb7af45
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/regi2c_bbpll.h
@@ -0,0 +1,175 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_bbpll.h
+ * @brief Register definitions for digital PLL (BBPLL)
+ *
+ * This file lists register fields of BBPLL, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * rtc_clk_cpu_freq_set function in rtc_clk.c.
+ */
+
+#define I2C_BBPLL           0x66
+#define I2C_BBPLL_HOSTID    0
+
+#define I2C_BBPLL_IR_CAL_DELAY        0
+#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
+#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
+
+#define I2C_BBPLL_IR_CAL_CK_DIV        0
+#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
+#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
+
+#define I2C_BBPLL_IR_CAL_EXT_CAP        1
+#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
+#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
+
+#define I2C_BBPLL_IR_CAL_ENX_CAP        1
+#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
+#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
+
+#define I2C_BBPLL_IR_CAL_RSTB        1
+#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
+#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
+
+#define I2C_BBPLL_IR_CAL_START        1
+#define I2C_BBPLL_IR_CAL_START_MSB    6
+#define I2C_BBPLL_IR_CAL_START_LSB    6
+
+#define I2C_BBPLL_IR_CAL_UNSTOP        1
+#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
+#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
+
+#define I2C_BBPLL_OC_REF_DIV        2
+#define I2C_BBPLL_OC_REF_DIV_MSB    3
+#define I2C_BBPLL_OC_REF_DIV_LSB    0
+
+#define I2C_BBPLL_OC_DCHGP        2
+#define I2C_BBPLL_OC_DCHGP_MSB    6
+#define I2C_BBPLL_OC_DCHGP_LSB    4
+
+#define I2C_BBPLL_OC_ENB_FCAL        2
+#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
+#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_BBPLL_OC_DIV_7_0        3
+#define I2C_BBPLL_OC_DIV_7_0_MSB    7
+#define I2C_BBPLL_OC_DIV_7_0_LSB    0
+
+#define I2C_BBPLL_RSTB_DIV_ADC        4
+#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
+#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
+
+#define I2C_BBPLL_MODE_HF        4
+#define I2C_BBPLL_MODE_HF_MSB    1
+#define I2C_BBPLL_MODE_HF_LSB    1
+
+#define I2C_BBPLL_DIV_ADC        4
+#define I2C_BBPLL_DIV_ADC_MSB    3
+#define I2C_BBPLL_DIV_ADC_LSB    2
+
+#define I2C_BBPLL_DIV_DAC        4
+#define I2C_BBPLL_DIV_DAC_MSB    4
+#define I2C_BBPLL_DIV_DAC_LSB    4
+
+#define I2C_BBPLL_DIV_CPU        4
+#define I2C_BBPLL_DIV_CPU_MSB    5
+#define I2C_BBPLL_DIV_CPU_LSB    5
+
+#define I2C_BBPLL_OC_ENB_VCON        4
+#define I2C_BBPLL_OC_ENB_VCON_MSB    6
+#define I2C_BBPLL_OC_ENB_VCON_LSB    6
+
+#define I2C_BBPLL_OC_TSCHGP        4
+#define I2C_BBPLL_OC_TSCHGP_MSB    7
+#define I2C_BBPLL_OC_TSCHGP_LSB    7
+
+#define I2C_BBPLL_OC_DR1        5
+#define I2C_BBPLL_OC_DR1_MSB    2
+#define I2C_BBPLL_OC_DR1_LSB    0
+
+#define I2C_BBPLL_OC_DR3        5
+#define I2C_BBPLL_OC_DR3_MSB    6
+#define I2C_BBPLL_OC_DR3_LSB    4
+
+#define I2C_BBPLL_EN_USB        5
+#define I2C_BBPLL_EN_USB_MSB    7
+#define I2C_BBPLL_EN_USB_LSB    7
+
+#define I2C_BBPLL_OC_DCUR        6
+#define I2C_BBPLL_OC_DCUR_MSB    2
+#define I2C_BBPLL_OC_DCUR_LSB    0
+
+#define I2C_BBPLL_INC_CUR        6
+#define I2C_BBPLL_INC_CUR_MSB    3
+#define I2C_BBPLL_INC_CUR_LSB    3
+
+#define I2C_BBPLL_OC_DHREF_SEL        6
+#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
+#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
+
+#define I2C_BBPLL_OC_DLREF_SEL        6
+#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
+#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
+
+#define I2C_BBPLL_OR_CAL_CAP        8
+#define I2C_BBPLL_OR_CAL_CAP_MSB    3
+#define I2C_BBPLL_OR_CAL_CAP_LSB    0
+
+#define I2C_BBPLL_OR_CAL_UDF        8
+#define I2C_BBPLL_OR_CAL_UDF_MSB    4
+#define I2C_BBPLL_OR_CAL_UDF_LSB    4
+
+#define I2C_BBPLL_OR_CAL_OVF        8
+#define I2C_BBPLL_OR_CAL_OVF_MSB    5
+#define I2C_BBPLL_OR_CAL_OVF_LSB    5
+
+#define I2C_BBPLL_OR_CAL_END        8
+#define I2C_BBPLL_OR_CAL_END_MSB    6
+#define I2C_BBPLL_OR_CAL_END_LSB    6
+
+#define I2C_BBPLL_OR_LOCK        8
+#define I2C_BBPLL_OR_LOCK_MSB    7
+#define I2C_BBPLL_OR_LOCK_LSB    7
+
+#define I2C_BBPLL_OC_VCO_DBIAS        9
+#define I2C_BBPLL_OC_VCO_DBIAS_MSB    1
+#define I2C_BBPLL_OC_VCO_DBIAS_LSB    0
+
+#define I2C_BBPLL_BBADC_DELAY2        9
+#define I2C_BBPLL_BBADC_DELAY2_MSB    3
+#define I2C_BBPLL_BBADC_DELAY2_LSB    2
+
+#define I2C_BBPLL_BBADC_DVDD        9
+#define I2C_BBPLL_BBADC_DVDD_MSB    5
+#define I2C_BBPLL_BBADC_DVDD_LSB    4
+
+#define I2C_BBPLL_BBADC_DREF        9
+#define I2C_BBPLL_BBADC_DREF_MSB    7
+#define I2C_BBPLL_BBADC_DREF_LSB    6
+
+#define I2C_BBPLL_BBADC_DCUR        10
+#define I2C_BBPLL_BBADC_DCUR_MSB    1
+#define I2C_BBPLL_BBADC_DCUR_LSB    0
+
+#define I2C_BBPLL_BBADC_INPUT_SHORT        10
+#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
+#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
+
+#define I2C_BBPLL_ENT_PLL        10
+#define I2C_BBPLL_ENT_PLL_MSB    3
+#define I2C_BBPLL_ENT_PLL_LSB    3
+
+#define I2C_BBPLL_DTEST        10
+#define I2C_BBPLL_DTEST_MSB    5
+#define I2C_BBPLL_DTEST_LSB    4
+
+#define I2C_BBPLL_ENT_ADC        10
+#define I2C_BBPLL_ENT_ADC_MSB    7
+#define I2C_BBPLL_ENT_ADC_LSB    6
diff --git a/components/soc/esp32p4/include/soc/regi2c_bias.h b/components/soc/esp32p4/include/soc/regi2c_bias.h
new file mode 100644
index 0000000000..fba5d6dbb5
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/regi2c_bias.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_bias.h
+ * @brief Register definitions for bias
+ *
+ * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * bootloader_hardware_init function in bootloader_esp32c6.c.
+ */
+
+#define I2C_BIAS            0X6A
+#define I2C_BIAS_HOSTID     0
+
+#define I2C_BIAS_DREG_1P1_PVT 1
+#define I2C_BIAS_DREG_1P1_PVT_MSB 3
+#define I2C_BIAS_DREG_1P1_PVT_LSB 0
diff --git a/components/soc/esp32p4/include/soc/regi2c_brownout.h b/components/soc/esp32p4/include/soc/regi2c_brownout.h
new file mode 100644
index 0000000000..6a5ca15769
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/regi2c_brownout.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_brownout.h
+ * @brief Register definitions for brownout detector
+ *
+ * This file lists register fields of the brownout detector, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h.
+ */
+
+#define I2C_BOD            0x61
+#define I2C_BOD_HOSTID     0
+
+#define I2C_BOD_THRESHOLD           0x5
+#define I2C_BOD_THRESHOLD_MSB       2
+#define I2C_BOD_THRESHOLD_LSB       0
diff --git a/components/soc/esp32p4/include/soc/regi2c_defs.h b/components/soc/esp32p4/include/soc/regi2c_defs.h
new file mode 100644
index 0000000000..f9a2415bda
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/regi2c_defs.h
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_bit_defs.h"
+
+/* Analog function control register */
+#define I2C_MST_ANA_CONF0_REG          0x600AF818
+#define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
+#define I2C_MST_BBPLL_STOP_FORCE_LOW   (BIT(3))
+#define I2C_MST_BBPLL_CAL_DONE         (BIT(24))
+
+
+#define ANA_CONFIG_REG  0x600AF81C
+#define ANA_CONFIG_S    (8)
+#define ANA_CONFIG_M    (0x3FF)
+
+#define ANA_I2C_SAR_FORCE_PD BIT(18)
+#define ANA_I2C_BBPLL_M      BIT(17) /* Clear to enable BBPLL */
+
+
+#define ANA_CONFIG2_REG  0x600AF820
+#define ANA_CONFIG2_M    BIT(18)
+
+#define ANA_I2C_SAR_FORCE_PU BIT(16)
+
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#define REGI2C_ANA_CALI_PD_WORKAROUND    1
+#define REGI2C_ANA_CALI_BYTE_NUM         8
diff --git a/components/soc/esp32p4/include/soc/regi2c_dig_reg.h b/components/soc/esp32p4/include/soc/regi2c_dig_reg.h
new file mode 100644
index 0000000000..8b277dfcd6
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/regi2c_dig_reg.h
@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_dig_reg.h
+ * @brief Register definitions for digital to get rtc voltage & digital voltage
+ *        by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
+ */
+
+#define I2C_DIG_REG 0x6D
+#define I2C_DIG_REG_HOSTID 0
+
+#define I2C_DIG_REG_EXT_RTC_DREG    4
+#define I2C_DIG_REG_EXT_RTC_DREG_MSB    4
+#define I2C_DIG_REG_EXT_RTC_DREG_LSB    0
+
+#define I2C_DIG_REG_ENX_RTC_DREG    4
+#define I2C_DIG_REG_ENX_RTC_DREG_MSB    7
+#define I2C_DIG_REG_ENX_RTC_DREG_LSB    7
+
+#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP    5
+#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB    4
+#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB    0
+
+#define I2C_DIG_REG_ENIF_RTC_DREG    5
+#define I2C_DIG_REG_ENIF_RTC_DREG_MSB    7
+#define I2C_DIG_REG_ENIF_RTC_DREG_LSB    7
+
+#define I2C_DIG_REG_EXT_DIG_DREG    6
+#define I2C_DIG_REG_EXT_DIG_DREG_MSB    4
+#define I2C_DIG_REG_EXT_DIG_DREG_LSB    0
+
+#define I2C_DIG_REG_ENX_DIG_DREG    6
+#define I2C_DIG_REG_ENX_DIG_DREG_MSB    7
+#define I2C_DIG_REG_ENX_DIG_DREG_LSB    7
+
+#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP    7
+#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB    4
+#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB    0
+
+#define I2C_DIG_REG_ENIF_DIG_DREG    7
+#define I2C_DIG_REG_ENIF_DIG_DREG_MSB    7
+#define I2C_DIG_REG_ENIF_DIG_DREG_LSB    7
+
+#define I2C_DIG_REG_OR_EN_CONT_CAL 9
+#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
+#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
+
+#define I2C_DIG_REG_XPD_RTC_REG 13
+#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
+#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
+
+#define I2C_DIG_REG_XPD_DIG_REG 13
+#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
+#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
+
+#define I2C_DIG_REG_SCK_DCAP	14
+#define I2C_DIG_REG_SCK_DCAP_MSB	7
+#define I2C_DIG_REG_SCK_DCAP_LSB	0
diff --git a/components/soc/esp32p4/include/soc/regi2c_lp_bias.h b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h
new file mode 100644
index 0000000000..5ca1c6833e
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_lp_bias.h
+ * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
+ *
+ * This file lists register fields of low power dbais, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * rtc_init function in rtc_init.c.
+ */
+
+#define I2C_ULP 0x61
+#define I2C_ULP_HOSTID 0
+
+#define I2C_ULP_IR_RESETB 0
+#define I2C_ULP_IR_RESETB_MSB 0
+#define I2C_ULP_IR_RESETB_LSB 0
+
+#define I2C_ULP_IR_FORCE_XPD_CK 0
+#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
+#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
+
+#define I2C_ULP_IR_FORCE_XPD_IPH 0
+#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
+#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
+
+#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
+#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
+#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
+
+#define I2C_ULP_O_DONE_FLAG 3
+#define I2C_ULP_O_DONE_FLAG_MSB 0
+#define I2C_ULP_O_DONE_FLAG_LSB 0
+
+#define I2C_ULP_BG_O_DONE_FLAG 3
+#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
+#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
+
+#define I2C_ULP_OCODE 4
+#define I2C_ULP_OCODE_MSB 7
+#define I2C_ULP_OCODE_LSB 0
+
+#define I2C_ULP_IR_FORCE_CODE 5
+#define I2C_ULP_IR_FORCE_CODE_MSB 6
+#define I2C_ULP_IR_FORCE_CODE_LSB 6
+
+#define I2C_ULP_EXT_CODE 6
+#define I2C_ULP_EXT_CODE_MSB 7
+#define I2C_ULP_EXT_CODE_LSB 0
diff --git a/components/soc/esp32p4/include/soc/regi2c_saradc.h b/components/soc/esp32p4/include/soc/regi2c_saradc.h
new file mode 100644
index 0000000000..ea76c6620d
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/regi2c_saradc.h
@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_saradc.h
+ * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
+ *
+ * This file lists register fields of SAR, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * function in adc_ll.h.
+ */
+
+#define I2C_SAR_ADC            0X69
+#define I2C_SAR_ADC_HOSTID     0
+
+#define ADC_SAR1_ENCAL_GND_ADDR 0x7
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
+
+#define ADC_SAR2_ENCAL_GND_ADDR 0x7
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR1_DREF_ADDR  0x2
+#define ADC_SAR1_DREF_ADDR_MSB  0x6
+#define ADC_SAR1_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR2_DREF_ADDR  0x5
+#define ADC_SAR2_DREF_ADDR_MSB  0x6
+#define ADC_SAR2_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
+
+#define ADC_SARADC_DTEST_RTC_ADDR 0x7
+#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
+#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
+
+#define ADC_SARADC_ENT_TSENS_ADDR 0x7
+#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
+#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
+
+#define ADC_SARADC_ENT_RTC_ADDR 0x7
+#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
+#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
+
+#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
+#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
+
+#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
+#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
+
+#define I2C_SARADC_TSENS_DAC 0x6
+#define I2C_SARADC_TSENS_DAC_MSB 3
+#define I2C_SARADC_TSENS_DAC_LSB 0
diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h
new file mode 100644
index 0000000000..5a4e577205
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/reset_reasons.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+//+-----------------------------------------------Terminology---------------------------------------------+
+//|                                                                                                       |
+//| CPU Reset:    Reset CPU core only, once reset done, CPU will execute from reset vector                |
+//|                                                                                                       |
+//| Core Reset:   Reset the whole digital system except RTC sub-system                                    |
+//|                                                                                                       |
+//| System Reset: Reset the whole digital system, including RTC sub-system                                |
+//|                                                                                                       |
+//| Chip Reset:   Reset the whole chip, including the analog part                                         |
+//|                                                                                                       |
+//+-------------------------------------------------------------------------------------------------------+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// TODO: IDF-5719
+/**
+ * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
+ * @note refer to TRM: <Reset and Clock> chapter
+ */
+typedef enum {
+    RESET_REASON_CHIP_POWER_ON   = 0x01, // Power on reset
+    RESET_REASON_CHIP_BROWN_OUT  = 0x01, // VDD voltage is not stable and resets the chip
+    RESET_REASON_CHIP_SUPER_WDT  = 0x01, // Super watch dog resets the chip
+    RESET_REASON_CORE_SW         = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
+    RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
+    RESET_REASON_CORE_MWDT0      = 0x07, // Main watch dog 0 resets digital core
+    RESET_REASON_CORE_MWDT1      = 0x08, // Main watch dog 1 resets digital core
+    RESET_REASON_CORE_RTC_WDT    = 0x09, // RTC watch dog resets digital core
+    RESET_REASON_CPU0_MWDT0      = 0x0B, // Main watch dog 0 resets CPU 0
+    RESET_REASON_CPU0_SW         = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
+    RESET_REASON_CPU0_RTC_WDT    = 0x0D, // RTC watch dog resets CPU 0
+    RESET_REASON_SYS_BROWN_OUT   = 0x0F, // VDD voltage is not stable and resets the digital core
+    RESET_REASON_SYS_RTC_WDT     = 0x10, // RTC watch dog resets digital core and rtc module
+    RESET_REASON_CPU0_MWDT1      = 0x11, // Main watch dog 1 resets CPU 0
+    RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
+    RESET_REASON_SYS_CLK_GLITCH  = 0x13, // Glitch on clock resets the digital core and rtc module
+    RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core
+    RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
+} soc_reset_reason_t;
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/rtc.h b/components/soc/esp32p4/include/soc/rtc.h
new file mode 100644
index 0000000000..407e6d636e
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/rtc.h
@@ -0,0 +1,529 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/clk_tree_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file rtc.h
+ * @brief Low-level RTC power, clock functions.
+ *
+ * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
+ * RTC_CNTL peripheral handles many functions:
+ * - enables/disables clocks and power to various parts of the chip; this is
+ *   done using direct register access (forcing power up or power down) or by
+ *   allowing state machines to control power and clocks automatically
+ * - handles sleep and wakeup functions
+ * - maintains a 48-bit counter which can be used for timekeeping
+ *
+ * These functions are not thread safe, and should not be viewed as high level
+ * APIs. For example, while this file provides a function which can switch
+ * CPU frequency, this function is on its own is not sufficient to implement
+ * frequency switching in ESP-IDF context: some coordination with RTOS,
+ * peripheral drivers, and WiFi/BT stacks is also required.
+ *
+ * These functions will normally not be used in applications directly.
+ * ESP-IDF provides, or will provide, drivers and other facilities to use
+ * RTC subsystem functionality.
+ *
+ * The functions are loosely split into the following groups:
+ * - rtc_clk: clock switching, calibration
+ * - rtc_time: reading RTC counter, conversion between counter values and time
+ */
+
+#define MHZ (1000000)
+
+#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles)  (cycles << 10)
+#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles)   (cycles << 12)
+#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles)   (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
+
+#define OTHER_BLOCKS_POWERUP        1
+#define OTHER_BLOCKS_WAIT           1
+
+// TODO: IDF-5781
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ */
+#define RTC_CNTL_DBIAS_SLP  5 //sleep dig_dbias & rtc_dbias
+#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
+#define RTC_CNTL_DBIAS_0V95 16
+#define RTC_CNTL_DBIAS_1V00 18
+#define RTC_CNTL_DBIAS_1V05 20
+#define RTC_CNTL_DBIAS_1V10 23
+#define RTC_CNTL_DBIAS_1V15 25
+#define RTC_CNTL_DBIAS_1V20 28
+#define RTC_CNTL_DBIAS_1V25 30
+#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
+
+/* Delays for various clock sources to be enabled/switched.
+ * All values are in microseconds.
+ */
+#define SOC_DELAY_RTC_FAST_CLK_SWITCH       3
+#define SOC_DELAY_RTC_SLOW_CLK_SWITCH       300
+#define SOC_DELAY_RC_FAST_ENABLE            50
+#define SOC_DELAY_RC_FAST_DIGI_SWITCH       5
+#define SOC_DELAY_RC32K_ENABLE              300
+
+/* Core voltage: // TODO: IDF-5781
+ * Currently, ESP32C6 never adjust its wake voltage in runtime
+ * Only sets dig/rtc voltage dbias at startup time
+ */
+#define DIG_DBIAS_80M       RTC_CNTL_DBIAS_1V20
+#define DIG_DBIAS_160M      RTC_CNTL_DBIAS_1V20
+#define DIG_DBIAS_XTAL      RTC_CNTL_DBIAS_1V10
+#define DIG_DBIAS_2M        RTC_CNTL_DBIAS_1V00
+
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
+#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
+#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
+
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT  100
+#define RTC_CNTL_SCK_DCAP_DEFAULT    128
+#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
+
+/* Various delays to be programmed into power control state machines */
+#define RTC_CNTL_XTL_BUF_WAIT_SLP_US            (250)
+#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES        (1)
+#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES           (4)
+#define RTC_CNTL_WAKEUP_DELAY_CYCLES            (5)
+#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES    (1)
+#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES       (1)
+#define RTC_CNTL_MIN_SLP_VAL_MIN                (2)
+
+/*
+set sleep_init default param
+*/
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT  5
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP  0
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT  15
+#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_SLEEP_ON  0
+#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT  1
+#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT  0
+#define RTC_CNTL_PD_CUR_SLEEP_ON  0
+#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT  1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
+
+/*
+The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
+storing in efuse (based on ATE 5k ECO3 chips)
+*/
+#define K_RTC_MID_MUL10000 215
+#define K_DIG_MID_MUL10000 213
+#define V_RTC_MID_MUL10000  10800
+#define V_DIG_MID_MUL10000  10860
+
+/**
+ * @brief Possible main XTAL frequency values.
+ *
+ * Enum values should be equal to frequency in MHz.
+ */
+typedef enum {
+    RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
+} rtc_xtal_freq_t;
+
+/**
+ * @brief CPU clock configuration structure
+ */
+typedef struct rtc_cpu_freq_config_s {
+    soc_cpu_clk_src_t source;       //!< The clock from which CPU clock is derived
+    uint32_t source_freq_mhz;       //!< Source clock frequency
+    uint32_t div;                   //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div
+    uint32_t freq_mhz;              //!< CPU clock frequency
+} rtc_cpu_freq_config_t;
+
+#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
+
+#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
+#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
+
+/**
+ * @brief Clock source to be calibrated using rtc_clk_cal function
+ *
+ * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL
+ *       However, this is not true on ESP32C6. The conversion to register field values is explicitly done in
+ *       rtc_clk_cal_internal
+ */
+typedef enum {
+    RTC_CAL_RTC_MUX = -1,                                  //!< Currently selected RTC_SLOW_CLK
+    RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW,        //!< Internal 150kHz RC oscillator
+    RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K,            //!< Internal 32kHz RC oscillator, as one type of 32k clock
+    RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K,       //!< External 32kHz XTAL, as one type of 32k clock
+    RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW,  //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
+    RTC_CAL_RC_FAST                                        //!< Internal 20MHz RC oscillator
+} rtc_cal_sel_t;
+
+/**
+ * Initialization parameters for rtc_clk_init
+ */
+typedef struct {
+    rtc_xtal_freq_t xtal_freq : 8;             //!< Main XTAL frequency
+    uint32_t cpu_freq_mhz : 10;                //!< CPU frequency to set, in MHz
+    soc_rtc_fast_clk_src_t fast_clk_src : 2;   //!< RTC_FAST_CLK clock source to choose
+    soc_rtc_slow_clk_src_t slow_clk_src : 3;   //!< RTC_SLOW_CLK clock source to choose
+    uint32_t clk_rtc_clk_div : 8;
+    uint32_t clk_8m_clk_div : 3;               //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency)
+    uint32_t slow_clk_dcap : 8;                //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
+    uint32_t clk_8m_dfreq : 8;                 //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
+    uint32_t rc32k_dfreq : 10;                 //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency)
+} rtc_clk_config_t;
+
+/**
+ * Default initializer for rtc_clk_config_t
+ */
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
+    .cpu_freq_mhz = 80, \
+    .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
+    .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
+    .clk_rtc_clk_div = 0, \
+    .clk_8m_clk_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+    .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
+}
+
+/**
+ * Initialize clocks and set CPU frequency
+ *
+ * @param cfg clock configuration as rtc_clk_config_t
+ */
+void rtc_clk_init(rtc_clk_config_t cfg);
+
+/**
+ * @brief Get main XTAL frequency
+ *
+ * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
+ * rtc_clk_init function
+ *
+ * @return XTAL frequency, one of rtc_xtal_freq_t
+ */
+rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
+
+/**
+ * @brief Update XTAL frequency
+ *
+ * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
+ * after startup.
+ *
+ * @param xtal_freq New frequency value
+ */
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
+
+/**
+ * @brief Enable or disable 32 kHz XTAL oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_32k_enable(bool en);
+
+/**
+ * @brief Configure 32 kHz XTAL oscillator to accept external clock signal
+ */
+void rtc_clk_32k_enable_external(void);
+
+/**
+ * @brief Get the state of 32k XTAL oscillator
+ * @return true if 32k XTAL oscillator has been enabled
+ */
+bool rtc_clk_32k_enabled(void);
+
+/**
+ * @brief Enable 32k oscillator, configuring it for fast startup time.
+ * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
+ * must be called one the 32k XTAL oscillator has started up. This function
+ * will initially disable the 32k XTAL oscillator, so it should not be called
+ * when the system is using 32k XTAL as RTC_SLOW_CLK.
+ *
+ * @param cycle Number of 32kHz cycles to bootstrap external crystal.
+ *              If 0, no square wave will be used to bootstrap crystal oscillation.
+ */
+void rtc_clk_32k_bootstrap(uint32_t cycle);
+
+/**
+ * @brief Enable or disable 32 kHz internal rc oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_rc32k_enable(bool enable);
+
+/**
+ * @brief Enable or disable 8 MHz internal oscillator
+ *
+ * @param clk_8m_en true to enable 8MHz generator
+ */
+void rtc_clk_8m_enable(bool clk_8m_en);
+
+/**
+ * @brief Get the state of 8 MHz internal oscillator
+ * @return true if the oscillator is enabled
+ */
+bool rtc_clk_8m_enabled(void);
+
+/**
+ * @brief Select source for RTC_SLOW_CLK
+ * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src);
+
+/**
+ * @brief Get the RTC_SLOW_CLK source
+ * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
+
+/**
+ * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
+ *
+ * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000
+ * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
+ * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768
+ * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768
+ *
+ * rtc_clk_cal function can be used to get more precise value by comparing
+ * RTC_SLOW_CLK frequency to the frequency of main XTAL.
+ *
+ * @return RTC_SLOW_CLK frequency, in Hz
+ */
+uint32_t rtc_clk_slow_freq_get_hz(void);
+
+/**
+ * @brief Select source for RTC_FAST_CLK
+ * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src);
+
+/**
+ * @brief Get the RTC_FAST_CLK source
+ * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void);
+
+/**
+ * @brief Get CPU frequency config for a given frequency
+ * @param freq_mhz  Frequency in MHz
+ * @param[out] out_config Output, CPU frequency configuration structure
+ * @return true if frequency can be obtained, false otherwise
+ */
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * This function sets CPU frequency according to the given configuration
+ * structure. It enables PLLs, if necessary.
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Switch CPU frequency (optimized for speed)
+ *
+ * This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
+ * It works faster because it does not disable PLLs when switching from PLL to
+ * XTAL and does not enabled them when switching back. If PLL is not already
+ * enabled when this function is called to switch from XTAL to PLL frequency,
+ * or the PLL which is enabled is the wrong one, this function will fall back
+ * to calling rtc_clk_cpu_freq_set_config.
+ *
+ * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
+ * so it is less safe to use it e.g. from a panic handler (when memory might
+ * be corrupted).
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Get the currently used CPU frequency configuration
+ * @param[out] out_config  Output, CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU clock source to XTAL
+ *
+ * Short form for filling in rtc_cpu_freq_config_t structure and calling
+ * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
+ * Assumes that XTAL frequency has been determined — don't call in startup code.
+ *
+ * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
+ * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
+ */
+void rtc_clk_cpu_freq_set_xtal(void);
+
+/**
+ * @brief Get the current APB frequency.
+ * @return The calculated APB frequency value, in Hz.
+ */
+uint32_t rtc_clk_apb_freq_get(void);
+
+/**
+ * @brief Clock calibration function used by rtc_clk_cal
+ *
+ * Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
+ * This feature counts the number of XTAL clock cycles within a given number of
+ * RTC_SLOW_CLK cycles.
+ *
+ * Slow clock calibration feature has two modes of operation: one-off and cycling.
+ * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
+ * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
+ * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
+ * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
+ * enabled using TIMG_RTC_CALI_START bit.
+ *
+ * @param cal_clk which clock to calibrate
+ * @param slowclk_cycles number of slow clock cycles to count
+ * @return number of XTAL clock cycles within the given number of slow clock cycles
+ */
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
+
+/**
+ * @brief Measure RTC slow clock's period, based on main XTAL frequency
+ *
+ * This function will time out and return 0 if the time for the given number
+ * of cycles to be counted exceeds the expected time twice. This may happen if
+ * 32k XTAL is being calibrated, but the oscillator has not started up (due to
+ * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
+ *
+ * @note When 32k CLK is being calibrated, this function will check the accuracy
+ * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if
+ * the check fails, then consider this an invalid 32k clock and return 0. This
+ * check can filter some jamming signal.
+ *
+ * @param cal_clk  clock to be measured
+ * @param slow_clk_cycles  number of slow clock cycles to average
+ * @return average slow clock period in microseconds, Q13.19 fixed point format,
+ *         or 0 if calibration has timed out
+ */
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
+ * @param time_in_us Time interval in microseconds
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return number of slow clock cycles
+ */
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
+
+/**
+ * @brief Convert time interval from RTC_SLOW_CLK to microseconds
+ * @param time_in_us Time interval in RTC_SLOW_CLK cycles
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return time interval in microseconds
+ */
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
+
+/**
+ * @brief Get current value of RTC counter
+ *
+ * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
+ * cycles. Counter value is not writable by software. The value is not adjusted
+ * when switching to a different RTC_SLOW_CLK source.
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter
+ */
+uint64_t rtc_time_get(void);
+
+/**
+ * @brief Busy loop until next RTC_SLOW_CLK cycle
+ *
+ * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
+ * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
+ * one RTC_SLOW_CLK cycle later.
+ */
+void rtc_clk_wait_for_slow_cycle(void);
+
+/**
+ * @brief Enable the rtc digital 8M clock
+ *
+ * This function is used to enable the digital rtc 8M clock to support peripherals.
+ * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
+ */
+void rtc_dig_clk8m_enable(void);
+
+/**
+ * @brief Disable the rtc digital 8M clock
+ *
+ * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
+ */
+void rtc_dig_clk8m_disable(void);
+
+/**
+ * @brief Get whether the rtc digital 8M clock is enabled
+ */
+bool rtc_dig_8m_enabled(void);
+
+/**
+ * @brief Calculate the real clock value after the clock calibration
+ *
+ * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal`
+ * @return Frequency of the clock in Hz
+ */
+uint32_t rtc_clk_freq_cal(uint32_t cal_val);
+
+
+// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
+// **WARNING**: The following are only for backwards compatibility.
+// Please use the declarations in soc/clk_tree_defs.h instead.
+/**
+ * @brief CPU clock source
+ */
+typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
+#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL  //!< XTAL
+#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL    //!< PLL (480M)
+#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
+
+/**
+ * @brief RTC SLOW_CLK frequency values
+ */
+typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
+#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW         //!< Internal 150 kHz RC oscillator
+#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K    //!< External 32 kHz XTAL
+
+/**
+ * @brief RTC FAST_CLK frequency values
+ */
+typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
+
+/* Alias of frequency related macros */
+#define RTC_FAST_CLK_FREQ_APPROX    SOC_CLK_RC_FAST_FREQ_APPROX
+#define RTC_FAST_CLK_FREQ_8M        SOC_CLK_RC_FAST_FREQ_APPROX
+#define RTC_SLOW_CLK_FREQ_150K      SOC_CLK_RC_SLOW_FREQ_APPROX
+#define RTC_SLOW_CLK_FREQ_32K       SOC_CLK_XTAL32K_FREQ_APPROX
+
+/* Alias of deprecated function names */
+#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq)
+#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get()
+#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq)
+#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get()
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/rtc_io_channel.h b/components/soc/esp32p4/include/soc/rtc_io_channel.h
new file mode 100644
index 0000000000..a3e2090e3b
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/rtc_io_channel.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+//RTC GPIO channels
+#define RTCIO_GPIO0_CHANNEL         0   //RTCIO_CHANNEL_0
+#define RTCIO_CHANNEL_0_GPIO_NUM    0
+
+#define RTCIO_GPIO1_CHANNEL         1   //RTCIO_CHANNEL_1
+#define RTCIO_CHANNEL_1_GPIO_NUM    1
+
+#define RTCIO_GPIO2_CHANNEL         2   //RTCIO_CHANNEL_2
+#define RTCIO_CHANNEL_2_GPIO_NUM    2
+
+#define RTCIO_GPIO3_CHANNEL         3   //RTCIO_CHANNEL_3
+#define RTCIO_CHANNEL_3_GPIO_NUM    3
+
+#define RTCIO_GPIO4_CHANNEL         4   //RTCIO_CHANNEL_4
+#define RTCIO_CHANNEL_4_GPIO_NUM    4
+
+#define RTCIO_GPIO5_CHANNEL         5   //RTCIO_CHANNEL_5
+#define RTCIO_CHANNEL_5_GPIO_NUM    5
+
+#define RTCIO_GPIO6_CHANNEL         6   //RTCIO_CHANNEL_6
+#define RTCIO_CHANNEL_6_GPIO_NUM    6
+
+#define RTCIO_GPIO7_CHANNEL         7   //RTCIO_CHANNEL_7
+#define RTCIO_CHANNEL_7_GPIO_NUM    7
diff --git a/components/soc/esp32p4/include/soc/rtc_io_reg.h b/components/soc/esp32p4/include/soc/rtc_io_reg.h
new file mode 100644
index 0000000000..a687a96dec
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/rtc_io_reg.h
@@ -0,0 +1,8 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/lp_io_reg.h"
diff --git a/components/soc/esp32p4/include/soc/rtc_io_struct.h b/components/soc/esp32p4/include/soc/rtc_io_struct.h
new file mode 100644
index 0000000000..67de8aadad
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/rtc_io_struct.h
@@ -0,0 +1,19 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/lp_io_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef lp_io_dev_t     rtc_io_dev_t;
+#define RTCIO           LP_IO
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/sdio_slave_pins.h b/components/soc/esp32p4/include/soc/sdio_slave_pins.h
new file mode 100644
index 0000000000..e7f4d11db2
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/sdio_slave_pins.h
@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  18
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  19
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0   20
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1   21
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2   22
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3   23
+#define SDIO_SLAVE_SLOT0_FUNC               0
diff --git a/components/soc/esp32p4/include/soc/sdmmc_pins.h b/components/soc/esp32p4/include/soc/sdmmc_pins.h
new file mode 100644
index 0000000000..1399d210fb
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/sdmmc_pins.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_SDMMC_PINS_H_
+#define _SOC_SDMMC_PINS_H_
+
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK  39
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD  40
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0   41
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1   42
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2   43
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3   44
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4   45
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5   46
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6   47
+#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7   48
+#define SDMMC_SLOT0_FUNC               0
+
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK  53
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD  54
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0   55
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1   56
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2   57
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3   58
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D4   59
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D5   60
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D6   61
+#define SDMMC_SLOT1_IOMUX_PIN_NUM_D7   62
+#define SDMMC_SLOT1_FUNC               0
+
+#endif /* _SOC_SDMMC_PINS_H_ */
diff --git a/components/soc/esp32p4/include/soc/slc_reg.h b/components/soc/esp32p4/include/soc/slc_reg.h
new file mode 100644
index 0000000000..d47cf53dbe
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/slc_reg.h
@@ -0,0 +1,4301 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SDIO_SLCCONF0_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLCCONF0_REG (DR_REG_SLC_BASE + 0x0)
+/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to reset tx fsm in dma slc0.
+ */
+#define SDIO_SLC0_TX_RST    (BIT(0))
+#define SDIO_SLC0_TX_RST_M  (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S)
+#define SDIO_SLC0_TX_RST_V  0x00000001U
+#define SDIO_SLC0_TX_RST_S  0
+/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to reset rx fsm in dma slc0.
+ */
+#define SDIO_SLC0_RX_RST    (BIT(1))
+#define SDIO_SLC0_RX_RST_M  (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S)
+#define SDIO_SLC0_RX_RST_V  0x00000001U
+#define SDIO_SLC0_RX_RST_S  1
+/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0;
+ *  reset the command fifo of AHB bus of sdio slave
+ */
+#define SDIO_SLC_AHBM_FIFO_RST    (BIT(2))
+#define SDIO_SLC_AHBM_FIFO_RST_M  (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S)
+#define SDIO_SLC_AHBM_FIFO_RST_V  0x00000001U
+#define SDIO_SLC_AHBM_FIFO_RST_S  2
+/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0;
+ *  reset the AHB bus of sdio slave
+ */
+#define SDIO_SLC_AHBM_RST    (BIT(3))
+#define SDIO_SLC_AHBM_RST_M  (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S)
+#define SDIO_SLC_AHBM_RST_V  0x00000001U
+#define SDIO_SLC_AHBM_RST_S  3
+/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0;
+ *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
+ */
+#define SDIO_SLC0_TX_LOOP_TEST    (BIT(4))
+#define SDIO_SLC0_TX_LOOP_TEST_M  (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S)
+#define SDIO_SLC0_TX_LOOP_TEST_V  0x00000001U
+#define SDIO_SLC0_TX_LOOP_TEST_S  4
+/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0;
+ *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
+ */
+#define SDIO_SLC0_RX_LOOP_TEST    (BIT(5))
+#define SDIO_SLC0_RX_LOOP_TEST_M  (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S)
+#define SDIO_SLC0_RX_LOOP_TEST_V  0x00000001U
+#define SDIO_SLC0_RX_LOOP_TEST_S  5
+/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0;
+ *  Set 1 to enable change the owner bit of rx link descriptor
+ */
+#define SDIO_SLC0_RX_AUTO_WRBACK    (BIT(6))
+#define SDIO_SLC0_RX_AUTO_WRBACK_M  (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S)
+#define SDIO_SLC0_RX_AUTO_WRBACK_V  0x00000001U
+#define SDIO_SLC0_RX_AUTO_WRBACK_S  6
+/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_NO_RESTART_CLR    (BIT(7))
+#define SDIO_SLC0_RX_NO_RESTART_CLR_M  (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S)
+#define SDIO_SLC0_RX_NO_RESTART_CLR_V  0x00000001U
+#define SDIO_SLC0_RX_NO_RESTART_CLR_S  7
+/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1;
+ *  0- AHB burst type is single when slave read rx-descriptor from memory through
+ *  slc0,1-AHB burst type is not single when slave read rx-descriptor from memory
+ *  through slc0
+ */
+#define SDIO_SLC0_RXDSCR_BURST_EN    (BIT(8))
+#define SDIO_SLC0_RXDSCR_BURST_EN_M  (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S)
+#define SDIO_SLC0_RXDSCR_BURST_EN_V  0x00000001U
+#define SDIO_SLC0_RXDSCR_BURST_EN_S  8
+/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1;
+ *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
+ *  is not single when slave receives data from memory
+ */
+#define SDIO_SLC0_RXDATA_BURST_EN    (BIT(9))
+#define SDIO_SLC0_RXDATA_BURST_EN_M  (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S)
+#define SDIO_SLC0_RXDATA_BURST_EN_V  0x00000001U
+#define SDIO_SLC0_RXDATA_BURST_EN_S  9
+/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1;
+ *  enable the function that when host reading packet retries, slc1 will automatically
+ *  jump to the start descriptor of the previous packet.
+ */
+#define SDIO_SLC0_RXLINK_AUTO_RET    (BIT(10))
+#define SDIO_SLC0_RXLINK_AUTO_RET_M  (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S)
+#define SDIO_SLC0_RXLINK_AUTO_RET_V  0x00000001U
+#define SDIO_SLC0_RXLINK_AUTO_RET_S  10
+/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1;
+ *  enable the function that when host sending packet retries, slc1 will automatically
+ *  jump to the start descriptor of the previous packet.
+ */
+#define SDIO_SLC0_TXLINK_AUTO_RET    (BIT(11))
+#define SDIO_SLC0_TXLINK_AUTO_RET_M  (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S)
+#define SDIO_SLC0_TXLINK_AUTO_RET_V  0x00000001U
+#define SDIO_SLC0_TXLINK_AUTO_RET_S  11
+/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1;
+ *  0- AHB burst type is single when slave read tx-descriptor from memory through
+ *  slc0,1-AHB burst type is not single when slave read tx-descriptor from memory
+ *  through slc0
+ */
+#define SDIO_SLC0_TXDSCR_BURST_EN    (BIT(12))
+#define SDIO_SLC0_TXDSCR_BURST_EN_M  (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S)
+#define SDIO_SLC0_TXDSCR_BURST_EN_V  0x00000001U
+#define SDIO_SLC0_TXDSCR_BURST_EN_S  12
+/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1;
+ *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
+ *  single when slave send data to memory
+ */
+#define SDIO_SLC0_TXDATA_BURST_EN    (BIT(13))
+#define SDIO_SLC0_TXDATA_BURST_EN_M  (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S)
+#define SDIO_SLC0_TXDATA_BURST_EN_V  0x00000001U
+#define SDIO_SLC0_TXDATA_BURST_EN_S  13
+/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1;
+ *  auto clear slc0_token1 enable
+ */
+#define SDIO_SLC0_TOKEN_AUTO_CLR    (BIT(14))
+#define SDIO_SLC0_TOKEN_AUTO_CLR_M  (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S)
+#define SDIO_SLC0_TOKEN_AUTO_CLR_V  0x00000001U
+#define SDIO_SLC0_TOKEN_AUTO_CLR_S  14
+/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN_SEL    (BIT(15))
+#define SDIO_SLC0_TOKEN_SEL_M  (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S)
+#define SDIO_SLC0_TOKEN_SEL_V  0x00000001U
+#define SDIO_SLC0_TOKEN_SEL_S  15
+/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to reset tx fsm in dma slc0.
+ */
+#define SDIO_SLC1_TX_RST    (BIT(16))
+#define SDIO_SLC1_TX_RST_M  (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S)
+#define SDIO_SLC1_TX_RST_V  0x00000001U
+#define SDIO_SLC1_TX_RST_S  16
+/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0;
+ *  Set 1 to reset rx fsm in dma slc0.
+ */
+#define SDIO_SLC1_RX_RST    (BIT(17))
+#define SDIO_SLC1_RX_RST_M  (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S)
+#define SDIO_SLC1_RX_RST_V  0x00000001U
+#define SDIO_SLC1_RX_RST_S  17
+/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_WR_RETRY_MASK_EN    (BIT(18))
+#define SDIO_SLC0_WR_RETRY_MASK_EN_M  (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S)
+#define SDIO_SLC0_WR_RETRY_MASK_EN_V  0x00000001U
+#define SDIO_SLC0_WR_RETRY_MASK_EN_S  18
+/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_WR_RETRY_MASK_EN    (BIT(19))
+#define SDIO_SLC1_WR_RETRY_MASK_EN_M  (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S)
+#define SDIO_SLC1_WR_RETRY_MASK_EN_V  0x00000001U
+#define SDIO_SLC1_WR_RETRY_MASK_EN_S  19
+/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1;
+ *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
+ */
+#define SDIO_SLC1_TX_LOOP_TEST    (BIT(20))
+#define SDIO_SLC1_TX_LOOP_TEST_M  (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S)
+#define SDIO_SLC1_TX_LOOP_TEST_V  0x00000001U
+#define SDIO_SLC1_TX_LOOP_TEST_S  20
+/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1;
+ *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
+ */
+#define SDIO_SLC1_RX_LOOP_TEST    (BIT(21))
+#define SDIO_SLC1_RX_LOOP_TEST_M  (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S)
+#define SDIO_SLC1_RX_LOOP_TEST_V  0x00000001U
+#define SDIO_SLC1_RX_LOOP_TEST_S  21
+/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0;
+ *  Set 1 to enable change the owner bit of rx link descriptor
+ */
+#define SDIO_SLC1_RX_AUTO_WRBACK    (BIT(22))
+#define SDIO_SLC1_RX_AUTO_WRBACK_M  (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S)
+#define SDIO_SLC1_RX_AUTO_WRBACK_V  0x00000001U
+#define SDIO_SLC1_RX_AUTO_WRBACK_S  22
+/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0;
+ *  ******* Description ***********
+ */
+#define SDIO_SLC1_RX_NO_RESTART_CLR    (BIT(23))
+#define SDIO_SLC1_RX_NO_RESTART_CLR_M  (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S)
+#define SDIO_SLC1_RX_NO_RESTART_CLR_V  0x00000001U
+#define SDIO_SLC1_RX_NO_RESTART_CLR_S  23
+/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1;
+ *  0- AHB burst type is single when slave read rx-descriptor from memory through
+ *  slc1,1-AHB burst type is not single when slave read rx-descriptor from memory
+ *  through slc1
+ */
+#define SDIO_SLC1_RXDSCR_BURST_EN    (BIT(24))
+#define SDIO_SLC1_RXDSCR_BURST_EN_M  (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S)
+#define SDIO_SLC1_RXDSCR_BURST_EN_V  0x00000001U
+#define SDIO_SLC1_RXDSCR_BURST_EN_S  24
+/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1;
+ *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
+ *  is not single when slave receives data from memory
+ */
+#define SDIO_SLC1_RXDATA_BURST_EN    (BIT(25))
+#define SDIO_SLC1_RXDATA_BURST_EN_M  (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S)
+#define SDIO_SLC1_RXDATA_BURST_EN_V  0x00000001U
+#define SDIO_SLC1_RXDATA_BURST_EN_S  25
+/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1;
+ *  enable the function that when host reading packet retries, slc1 will automatically
+ *  jump to the start descriptor of the previous packet.
+ */
+#define SDIO_SLC1_RXLINK_AUTO_RET    (BIT(26))
+#define SDIO_SLC1_RXLINK_AUTO_RET_M  (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S)
+#define SDIO_SLC1_RXLINK_AUTO_RET_V  0x00000001U
+#define SDIO_SLC1_RXLINK_AUTO_RET_S  26
+/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1;
+ *  enable the function that when host sending packet retries, slc1 will automatically
+ *  jump to the start descriptor of the previous packet.
+ */
+#define SDIO_SLC1_TXLINK_AUTO_RET    (BIT(27))
+#define SDIO_SLC1_TXLINK_AUTO_RET_M  (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S)
+#define SDIO_SLC1_TXLINK_AUTO_RET_V  0x00000001U
+#define SDIO_SLC1_TXLINK_AUTO_RET_S  27
+/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1;
+ *  0- AHB burst type is single when slave read tx-descriptor from memory through
+ *  slc1,1-AHB burst type is not single when slave read tx-descriptor from memory
+ *  through slc1
+ */
+#define SDIO_SLC1_TXDSCR_BURST_EN    (BIT(28))
+#define SDIO_SLC1_TXDSCR_BURST_EN_M  (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S)
+#define SDIO_SLC1_TXDSCR_BURST_EN_V  0x00000001U
+#define SDIO_SLC1_TXDSCR_BURST_EN_S  28
+/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1;
+ *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
+ *  single when slave send data to memory
+ */
+#define SDIO_SLC1_TXDATA_BURST_EN    (BIT(29))
+#define SDIO_SLC1_TXDATA_BURST_EN_M  (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S)
+#define SDIO_SLC1_TXDATA_BURST_EN_V  0x00000001U
+#define SDIO_SLC1_TXDATA_BURST_EN_S  29
+/** SDIO_SLC1_TOKEN_AUTO_CLR : R/W; bitpos: [30]; default: 1;
+ *  auto clear slc1_token1 enable
+ */
+#define SDIO_SLC1_TOKEN_AUTO_CLR    (BIT(30))
+#define SDIO_SLC1_TOKEN_AUTO_CLR_M  (SDIO_SLC1_TOKEN_AUTO_CLR_V << SDIO_SLC1_TOKEN_AUTO_CLR_S)
+#define SDIO_SLC1_TOKEN_AUTO_CLR_V  0x00000001U
+#define SDIO_SLC1_TOKEN_AUTO_CLR_S  30
+/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN_SEL    (BIT(31))
+#define SDIO_SLC1_TOKEN_SEL_M  (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S)
+#define SDIO_SLC1_TOKEN_SEL_V  0x00000001U
+#define SDIO_SLC1_TOKEN_SEL_S  31
+
+/** SDIO_SLC0INT_RAW_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
+/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT0_INT_RAW    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M  (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S  0
+/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT1_INT_RAW    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M  (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S  1
+/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT2_INT_RAW    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M  (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S  2
+/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT3_INT_RAW    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M  (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S  3
+/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT4_INT_RAW    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M  (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S  4
+/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT5_INT_RAW    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M  (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S  5
+/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT6_INT_RAW    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M  (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S  6
+/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT7_INT_RAW    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M  (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S  7
+/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_START_INT_RAW    (BIT(8))
+#define SDIO_SLC0_RX_START_INT_RAW_M  (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S)
+#define SDIO_SLC0_RX_START_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_RX_START_INT_RAW_S  8
+/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_START_INT_RAW    (BIT(9))
+#define SDIO_SLC0_TX_START_INT_RAW_M  (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S)
+#define SDIO_SLC0_TX_START_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TX_START_INT_RAW_S  9
+/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_UDF_INT_RAW    (BIT(10))
+#define SDIO_SLC0_RX_UDF_INT_RAW_M  (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S)
+#define SDIO_SLC0_RX_UDF_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_RX_UDF_INT_RAW_S  10
+/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_OVF_INT_RAW    (BIT(11))
+#define SDIO_SLC0_TX_OVF_INT_RAW_M  (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S)
+#define SDIO_SLC0_TX_OVF_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TX_OVF_INT_RAW_S  11
+/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(12))
+#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M  (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S)
+#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S  12
+/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(13))
+#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M  (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S)
+#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S  13
+/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit of slc0 finishing receiving data to one buffer
+ */
+#define SDIO_SLC0_TX_DONE_INT_RAW    (BIT(14))
+#define SDIO_SLC0_TX_DONE_INT_RAW_M  (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S)
+#define SDIO_SLC0_TX_DONE_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TX_DONE_INT_RAW_S  14
+/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit of slc0 finishing receiving data
+ */
+#define SDIO_SLC0_TX_SUC_EOF_INT_RAW    (BIT(15))
+#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M  (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S)
+#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S  15
+/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw interrupt bit of slc0 finishing sending data from one buffer
+ */
+#define SDIO_SLC0_RX_DONE_INT_RAW    (BIT(16))
+#define SDIO_SLC0_RX_DONE_INT_RAW_M  (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S)
+#define SDIO_SLC0_RX_DONE_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_RX_DONE_INT_RAW_S  16
+/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw interrupt bit of slc0 finishing sending data
+ */
+#define SDIO_SLC0_RX_EOF_INT_RAW    (BIT(17))
+#define SDIO_SLC0_RX_EOF_INT_RAW_M  (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S)
+#define SDIO_SLC0_RX_EOF_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_RX_EOF_INT_RAW_S  17
+/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOHOST_INT_RAW    (BIT(18))
+#define SDIO_SLC0_TOHOST_INT_RAW_M  (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S)
+#define SDIO_SLC0_TOHOST_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TOHOST_INT_RAW_S  18
+/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw interrupt bit of slc0 tx link descriptor error
+ */
+#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW    (BIT(19))
+#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M  (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S)
+#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S  19
+/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw interrupt bit of slc0 rx link descriptor error
+ */
+#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW    (BIT(20))
+#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M  (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S)
+#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S  20
+/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S)
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
+/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_RD_ACK_INT_RAW    (BIT(22))
+#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M  (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S)
+#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S  22
+/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW    (BIT(23))
+#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M  (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S)
+#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S  23
+/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERR_EOF_INT_RAW    (BIT(24))
+#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M  (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S)
+#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S  24
+/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_DTC_INT_RAW    (BIT(25))
+#define SDIO_CMD_DTC_INT_RAW_M  (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S)
+#define SDIO_CMD_DTC_INT_RAW_V  0x00000001U
+#define SDIO_CMD_DTC_INT_RAW_S  25
+/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW    (BIT(26))
+#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M  (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S)
+#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S  26
+/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW    (BIT(27))
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S)
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V  0x00000001U
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S  27
+/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_HDA_RECV_DONE_INT_RAW    (BIT(28))
+#define SDIO_HDA_RECV_DONE_INT_RAW_M  (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S)
+#define SDIO_HDA_RECV_DONE_INT_RAW_V  0x00000001U
+#define SDIO_HDA_RECV_DONE_INT_RAW_S  28
+
+/** SDIO_SLC0INT_ST_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
+/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT0_INT_ST    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT0_INT_ST_M  (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT0_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT0_INT_ST_S  0
+/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT1_INT_ST    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT1_INT_ST_M  (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT1_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT1_INT_ST_S  1
+/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT2_INT_ST    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT2_INT_ST_M  (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT2_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT2_INT_ST_S  2
+/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT3_INT_ST    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT3_INT_ST_M  (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT3_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT3_INT_ST_S  3
+/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT4_INT_ST    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT4_INT_ST_M  (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT4_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT4_INT_ST_S  4
+/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT5_INT_ST    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT5_INT_ST_M  (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT5_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT5_INT_ST_S  5
+/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT6_INT_ST    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT6_INT_ST_M  (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT6_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT6_INT_ST_S  6
+/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT7_INT_ST    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT7_INT_ST_M  (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT7_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT7_INT_ST_S  7
+/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_START_INT_ST    (BIT(8))
+#define SDIO_SLC0_RX_START_INT_ST_M  (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S)
+#define SDIO_SLC0_RX_START_INT_ST_V  0x00000001U
+#define SDIO_SLC0_RX_START_INT_ST_S  8
+/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_START_INT_ST    (BIT(9))
+#define SDIO_SLC0_TX_START_INT_ST_M  (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S)
+#define SDIO_SLC0_TX_START_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TX_START_INT_ST_S  9
+/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_UDF_INT_ST    (BIT(10))
+#define SDIO_SLC0_RX_UDF_INT_ST_M  (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S)
+#define SDIO_SLC0_RX_UDF_INT_ST_V  0x00000001U
+#define SDIO_SLC0_RX_UDF_INT_ST_S  10
+/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_OVF_INT_ST    (BIT(11))
+#define SDIO_SLC0_TX_OVF_INT_ST_M  (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S)
+#define SDIO_SLC0_TX_OVF_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TX_OVF_INT_ST_S  11
+/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST    (BIT(12))
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S)
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S  12
+/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST    (BIT(13))
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S)
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S  13
+/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DONE_INT_ST    (BIT(14))
+#define SDIO_SLC0_TX_DONE_INT_ST_M  (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S)
+#define SDIO_SLC0_TX_DONE_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TX_DONE_INT_ST_S  14
+/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST    (BIT(15))
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M  (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S)
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S  15
+/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DONE_INT_ST    (BIT(16))
+#define SDIO_SLC0_RX_DONE_INT_ST_M  (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S)
+#define SDIO_SLC0_RX_DONE_INT_ST_V  0x00000001U
+#define SDIO_SLC0_RX_DONE_INT_ST_S  16
+/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_EOF_INT_ST    (BIT(17))
+#define SDIO_SLC0_RX_EOF_INT_ST_M  (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S)
+#define SDIO_SLC0_RX_EOF_INT_ST_V  0x00000001U
+#define SDIO_SLC0_RX_EOF_INT_ST_S  17
+/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOHOST_INT_ST    (BIT(18))
+#define SDIO_SLC0_TOHOST_INT_ST_M  (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S)
+#define SDIO_SLC0_TOHOST_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TOHOST_INT_ST_S  18
+/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST    (BIT(19))
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S)
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S  19
+/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST    (BIT(20))
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S)
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V  0x00000001U
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S  20
+/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST    (BIT(21))
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S)
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
+/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST    (BIT(22))
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M  (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S)
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V  0x00000001U
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S  22
+/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST    (BIT(23))
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S)
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V  0x00000001U
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S  23
+/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST    (BIT(24))
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M  (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S)
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V  0x00000001U
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S  24
+/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_DTC_INT_ST    (BIT(25))
+#define SDIO_CMD_DTC_INT_ST_M  (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S)
+#define SDIO_CMD_DTC_INT_ST_V  0x00000001U
+#define SDIO_CMD_DTC_INT_ST_S  25
+/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST    (BIT(26))
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S)
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V  0x00000001U
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S  26
+/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST    (BIT(27))
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S)
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V  0x00000001U
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S  27
+/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_HDA_RECV_DONE_INT_ST    (BIT(28))
+#define SDIO_HDA_RECV_DONE_INT_ST_M  (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S)
+#define SDIO_HDA_RECV_DONE_INT_ST_V  0x00000001U
+#define SDIO_HDA_RECV_DONE_INT_ST_S  28
+
+/** SDIO_SLC0INT_ENA_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0INT_ENA_REG (DR_REG_SLC_BASE + 0xc)
+/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M  (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S  0
+/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M  (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S  1
+/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M  (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S  2
+/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M  (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S  3
+/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M  (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S  4
+/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M  (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S  5
+/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M  (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S  6
+/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M  (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S  7
+/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_START_INT_ENA    (BIT(8))
+#define SDIO_SLC0_RX_START_INT_ENA_M  (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S)
+#define SDIO_SLC0_RX_START_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_RX_START_INT_ENA_S  8
+/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_START_INT_ENA    (BIT(9))
+#define SDIO_SLC0_TX_START_INT_ENA_M  (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S)
+#define SDIO_SLC0_TX_START_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TX_START_INT_ENA_S  9
+/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_UDF_INT_ENA    (BIT(10))
+#define SDIO_SLC0_RX_UDF_INT_ENA_M  (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S)
+#define SDIO_SLC0_RX_UDF_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_RX_UDF_INT_ENA_S  10
+/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_OVF_INT_ENA    (BIT(11))
+#define SDIO_SLC0_TX_OVF_INT_ENA_M  (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S)
+#define SDIO_SLC0_TX_OVF_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TX_OVF_INT_ENA_S  11
+/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(12))
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S)
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S  12
+/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(13))
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S)
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S  13
+/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DONE_INT_ENA    (BIT(14))
+#define SDIO_SLC0_TX_DONE_INT_ENA_M  (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S)
+#define SDIO_SLC0_TX_DONE_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TX_DONE_INT_ENA_S  14
+/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA    (BIT(15))
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M  (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S)
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S  15
+/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DONE_INT_ENA    (BIT(16))
+#define SDIO_SLC0_RX_DONE_INT_ENA_M  (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S)
+#define SDIO_SLC0_RX_DONE_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_RX_DONE_INT_ENA_S  16
+/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_EOF_INT_ENA    (BIT(17))
+#define SDIO_SLC0_RX_EOF_INT_ENA_M  (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S)
+#define SDIO_SLC0_RX_EOF_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_RX_EOF_INT_ENA_S  17
+/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOHOST_INT_ENA    (BIT(18))
+#define SDIO_SLC0_TOHOST_INT_ENA_M  (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S)
+#define SDIO_SLC0_TOHOST_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TOHOST_INT_ENA_S  18
+/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA    (BIT(19))
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S)
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S  19
+/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA    (BIT(20))
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S)
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S  20
+/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S)
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
+/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA    (BIT(22))
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M  (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S)
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S  22
+/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA    (BIT(23))
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S)
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S  23
+/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA    (BIT(24))
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M  (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S)
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S  24
+/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_DTC_INT_ENA    (BIT(25))
+#define SDIO_CMD_DTC_INT_ENA_M  (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S)
+#define SDIO_CMD_DTC_INT_ENA_V  0x00000001U
+#define SDIO_CMD_DTC_INT_ENA_S  25
+/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA    (BIT(26))
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S)
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S  26
+/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA    (BIT(27))
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S)
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V  0x00000001U
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S  27
+/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_HDA_RECV_DONE_INT_ENA    (BIT(28))
+#define SDIO_HDA_RECV_DONE_INT_ENA_M  (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S)
+#define SDIO_HDA_RECV_DONE_INT_ENA_V  0x00000001U
+#define SDIO_HDA_RECV_DONE_INT_ENA_S  28
+
+/** SDIO_SLC0INT_CLR_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
+/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT0_INT_CLR    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M  (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S  0
+/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT1_INT_CLR    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M  (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S  1
+/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT2_INT_CLR    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M  (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S  2
+/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT3_INT_CLR    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M  (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S  3
+/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT4_INT_CLR    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M  (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S  4
+/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT5_INT_CLR    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M  (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S  5
+/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT6_INT_CLR    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M  (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S  6
+/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT7_INT_CLR    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M  (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S  7
+/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_START_INT_CLR    (BIT(8))
+#define SDIO_SLC0_RX_START_INT_CLR_M  (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S)
+#define SDIO_SLC0_RX_START_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_RX_START_INT_CLR_S  8
+/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_START_INT_CLR    (BIT(9))
+#define SDIO_SLC0_TX_START_INT_CLR_M  (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S)
+#define SDIO_SLC0_TX_START_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TX_START_INT_CLR_S  9
+/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_UDF_INT_CLR    (BIT(10))
+#define SDIO_SLC0_RX_UDF_INT_CLR_M  (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S)
+#define SDIO_SLC0_RX_UDF_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_RX_UDF_INT_CLR_S  10
+/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_OVF_INT_CLR    (BIT(11))
+#define SDIO_SLC0_TX_OVF_INT_CLR_M  (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S)
+#define SDIO_SLC0_TX_OVF_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TX_OVF_INT_CLR_S  11
+/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(12))
+#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M  (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S)
+#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S  12
+/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(13))
+#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M  (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S)
+#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S  13
+/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DONE_INT_CLR    (BIT(14))
+#define SDIO_SLC0_TX_DONE_INT_CLR_M  (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S)
+#define SDIO_SLC0_TX_DONE_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TX_DONE_INT_CLR_S  14
+/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SUC_EOF_INT_CLR    (BIT(15))
+#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M  (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S)
+#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S  15
+/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DONE_INT_CLR    (BIT(16))
+#define SDIO_SLC0_RX_DONE_INT_CLR_M  (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S)
+#define SDIO_SLC0_RX_DONE_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_RX_DONE_INT_CLR_S  16
+/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_EOF_INT_CLR    (BIT(17))
+#define SDIO_SLC0_RX_EOF_INT_CLR_M  (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S)
+#define SDIO_SLC0_RX_EOF_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_RX_EOF_INT_CLR_S  17
+/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOHOST_INT_CLR    (BIT(18))
+#define SDIO_SLC0_TOHOST_INT_CLR_M  (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S)
+#define SDIO_SLC0_TOHOST_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TOHOST_INT_CLR_S  18
+/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR    (BIT(19))
+#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M  (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S)
+#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S  19
+/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR    (BIT(20))
+#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M  (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S)
+#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S  20
+/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S)
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
+/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_RD_ACK_INT_CLR    (BIT(22))
+#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M  (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S)
+#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S  22
+/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR    (BIT(23))
+#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M  (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S)
+#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S  23
+/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERR_EOF_INT_CLR    (BIT(24))
+#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M  (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S)
+#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S  24
+/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_DTC_INT_CLR    (BIT(25))
+#define SDIO_CMD_DTC_INT_CLR_M  (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S)
+#define SDIO_CMD_DTC_INT_CLR_V  0x00000001U
+#define SDIO_CMD_DTC_INT_CLR_S  25
+/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR    (BIT(26))
+#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M  (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S)
+#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S  26
+/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR    (BIT(27))
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S)
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V  0x00000001U
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S  27
+/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_HDA_RECV_DONE_INT_CLR    (BIT(28))
+#define SDIO_HDA_RECV_DONE_INT_CLR_M  (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S)
+#define SDIO_HDA_RECV_DONE_INT_CLR_V  0x00000001U
+#define SDIO_HDA_RECV_DONE_INT_CLR_S  28
+
+/** SDIO_SLC1INT_RAW_REG register
+ *  reserved
+ */
+#define SDIO_SLC1INT_RAW_REG (DR_REG_SLC_BASE + 0x14)
+/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT8_INT_RAW    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M  (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S  0
+/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT9_INT_RAW    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M  (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S  1
+/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT10_INT_RAW    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M  (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S  2
+/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT11_INT_RAW    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M  (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S  3
+/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT12_INT_RAW    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M  (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S  4
+/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT13_INT_RAW    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M  (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S  5
+/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT14_INT_RAW    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M  (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S  6
+/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT15_INT_RAW    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M  (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S)
+#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S  7
+/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_START_INT_RAW    (BIT(8))
+#define SDIO_SLC1_RX_START_INT_RAW_M  (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S)
+#define SDIO_SLC1_RX_START_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_RX_START_INT_RAW_S  8
+/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_START_INT_RAW    (BIT(9))
+#define SDIO_SLC1_TX_START_INT_RAW_M  (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S)
+#define SDIO_SLC1_TX_START_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TX_START_INT_RAW_S  9
+/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_UDF_INT_RAW    (BIT(10))
+#define SDIO_SLC1_RX_UDF_INT_RAW_M  (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S)
+#define SDIO_SLC1_RX_UDF_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_RX_UDF_INT_RAW_S  10
+/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_OVF_INT_RAW    (BIT(11))
+#define SDIO_SLC1_TX_OVF_INT_RAW_M  (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S)
+#define SDIO_SLC1_TX_OVF_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TX_OVF_INT_RAW_S  11
+/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW    (BIT(12))
+#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M  (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S)
+#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S  12
+/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW    (BIT(13))
+#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M  (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S)
+#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S  13
+/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DONE_INT_RAW    (BIT(14))
+#define SDIO_SLC1_TX_DONE_INT_RAW_M  (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S)
+#define SDIO_SLC1_TX_DONE_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TX_DONE_INT_RAW_S  14
+/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SUC_EOF_INT_RAW    (BIT(15))
+#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M  (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S)
+#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S  15
+/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DONE_INT_RAW    (BIT(16))
+#define SDIO_SLC1_RX_DONE_INT_RAW_M  (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S)
+#define SDIO_SLC1_RX_DONE_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_RX_DONE_INT_RAW_S  16
+/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_EOF_INT_RAW    (BIT(17))
+#define SDIO_SLC1_RX_EOF_INT_RAW_M  (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S)
+#define SDIO_SLC1_RX_EOF_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_RX_EOF_INT_RAW_S  17
+/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOHOST_INT_RAW    (BIT(18))
+#define SDIO_SLC1_TOHOST_INT_RAW_M  (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S)
+#define SDIO_SLC1_TOHOST_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TOHOST_INT_RAW_S  18
+/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW    (BIT(19))
+#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M  (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S)
+#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S  19
+/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW    (BIT(20))
+#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M  (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S)
+#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S  20
+/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S)
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S  21
+/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_HOST_RD_ACK_INT_RAW    (BIT(22))
+#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M  (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S)
+#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S  22
+/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW    (BIT(23))
+#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M  (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S)
+#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S  23
+/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERR_EOF_INT_RAW    (BIT(24))
+#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M  (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S)
+#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V  0x00000001U
+#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S  24
+
+/** SDIO_SLC1INT_ST_REG register
+ *  reserved
+ */
+#define SDIO_SLC1INT_ST_REG (DR_REG_SLC_BASE + 0x18)
+/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT8_INT_ST    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT8_INT_ST_M  (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT8_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT8_INT_ST_S  0
+/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT9_INT_ST    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT9_INT_ST_M  (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT9_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT9_INT_ST_S  1
+/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT10_INT_ST    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT10_INT_ST_M  (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT10_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT10_INT_ST_S  2
+/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT11_INT_ST    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT11_INT_ST_M  (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT11_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT11_INT_ST_S  3
+/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT12_INT_ST    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT12_INT_ST_M  (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT12_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT12_INT_ST_S  4
+/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT13_INT_ST    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT13_INT_ST_M  (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT13_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT13_INT_ST_S  5
+/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT14_INT_ST    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT14_INT_ST_M  (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT14_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT14_INT_ST_S  6
+/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT15_INT_ST    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT15_INT_ST_M  (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S)
+#define SDIO_SLC_FRHOST_BIT15_INT_ST_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT15_INT_ST_S  7
+/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_START_INT_ST    (BIT(8))
+#define SDIO_SLC1_RX_START_INT_ST_M  (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S)
+#define SDIO_SLC1_RX_START_INT_ST_V  0x00000001U
+#define SDIO_SLC1_RX_START_INT_ST_S  8
+/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_START_INT_ST    (BIT(9))
+#define SDIO_SLC1_TX_START_INT_ST_M  (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S)
+#define SDIO_SLC1_TX_START_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TX_START_INT_ST_S  9
+/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_UDF_INT_ST    (BIT(10))
+#define SDIO_SLC1_RX_UDF_INT_ST_M  (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S)
+#define SDIO_SLC1_RX_UDF_INT_ST_V  0x00000001U
+#define SDIO_SLC1_RX_UDF_INT_ST_S  10
+/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_OVF_INT_ST    (BIT(11))
+#define SDIO_SLC1_TX_OVF_INT_ST_M  (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S)
+#define SDIO_SLC1_TX_OVF_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TX_OVF_INT_ST_S  11
+/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST    (BIT(12))
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S)
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S  12
+/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST    (BIT(13))
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S)
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S  13
+/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DONE_INT_ST    (BIT(14))
+#define SDIO_SLC1_TX_DONE_INT_ST_M  (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S)
+#define SDIO_SLC1_TX_DONE_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TX_DONE_INT_ST_S  14
+/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST    (BIT(15))
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M  (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S)
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S  15
+/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DONE_INT_ST    (BIT(16))
+#define SDIO_SLC1_RX_DONE_INT_ST_M  (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S)
+#define SDIO_SLC1_RX_DONE_INT_ST_V  0x00000001U
+#define SDIO_SLC1_RX_DONE_INT_ST_S  16
+/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_EOF_INT_ST    (BIT(17))
+#define SDIO_SLC1_RX_EOF_INT_ST_M  (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S)
+#define SDIO_SLC1_RX_EOF_INT_ST_V  0x00000001U
+#define SDIO_SLC1_RX_EOF_INT_ST_S  17
+/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOHOST_INT_ST    (BIT(18))
+#define SDIO_SLC1_TOHOST_INT_ST_M  (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S)
+#define SDIO_SLC1_TOHOST_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TOHOST_INT_ST_S  18
+/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST    (BIT(19))
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S)
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S  19
+/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST    (BIT(20))
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S)
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V  0x00000001U
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S  20
+/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST    (BIT(21))
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S)
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S  21
+/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST    (BIT(22))
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M  (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S)
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V  0x00000001U
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S  22
+/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST    (BIT(23))
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S)
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V  0x00000001U
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S  23
+/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST    (BIT(24))
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M  (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S)
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V  0x00000001U
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S  24
+
+/** SDIO_SLC1INT_ENA_REG register
+ *  reserved
+ */
+#define SDIO_SLC1INT_ENA_REG (DR_REG_SLC_BASE + 0x1c)
+/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M  (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S  0
+/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M  (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S  1
+/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M  (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S  2
+/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M  (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S  3
+/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M  (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S  4
+/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M  (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S  5
+/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M  (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S  6
+/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M  (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S)
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S  7
+/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_START_INT_ENA    (BIT(8))
+#define SDIO_SLC1_RX_START_INT_ENA_M  (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S)
+#define SDIO_SLC1_RX_START_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_RX_START_INT_ENA_S  8
+/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_START_INT_ENA    (BIT(9))
+#define SDIO_SLC1_TX_START_INT_ENA_M  (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S)
+#define SDIO_SLC1_TX_START_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TX_START_INT_ENA_S  9
+/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_UDF_INT_ENA    (BIT(10))
+#define SDIO_SLC1_RX_UDF_INT_ENA_M  (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S)
+#define SDIO_SLC1_RX_UDF_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_RX_UDF_INT_ENA_S  10
+/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_OVF_INT_ENA    (BIT(11))
+#define SDIO_SLC1_TX_OVF_INT_ENA_M  (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S)
+#define SDIO_SLC1_TX_OVF_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TX_OVF_INT_ENA_S  11
+/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(12))
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S)
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S  12
+/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(13))
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S)
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S  13
+/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DONE_INT_ENA    (BIT(14))
+#define SDIO_SLC1_TX_DONE_INT_ENA_M  (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S)
+#define SDIO_SLC1_TX_DONE_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TX_DONE_INT_ENA_S  14
+/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA    (BIT(15))
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M  (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S)
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S  15
+/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DONE_INT_ENA    (BIT(16))
+#define SDIO_SLC1_RX_DONE_INT_ENA_M  (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S)
+#define SDIO_SLC1_RX_DONE_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_RX_DONE_INT_ENA_S  16
+/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_EOF_INT_ENA    (BIT(17))
+#define SDIO_SLC1_RX_EOF_INT_ENA_M  (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S)
+#define SDIO_SLC1_RX_EOF_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_RX_EOF_INT_ENA_S  17
+/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOHOST_INT_ENA    (BIT(18))
+#define SDIO_SLC1_TOHOST_INT_ENA_M  (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S)
+#define SDIO_SLC1_TOHOST_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TOHOST_INT_ENA_S  18
+/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA    (BIT(19))
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S)
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S  19
+/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA    (BIT(20))
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S)
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S  20
+/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S)
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S  21
+/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA    (BIT(22))
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M  (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S)
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S  22
+/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA    (BIT(23))
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S)
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S  23
+/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA    (BIT(24))
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M  (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S)
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V  0x00000001U
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S  24
+
+/** SDIO_SLC1INT_CLR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1INT_CLR_REG (DR_REG_SLC_BASE + 0x20)
+/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT8_INT_CLR    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M  (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S  0
+/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT9_INT_CLR    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M  (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S  1
+/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT10_INT_CLR    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M  (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S  2
+/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT11_INT_CLR    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M  (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S  3
+/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT12_INT_CLR    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M  (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S  4
+/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT13_INT_CLR    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M  (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S  5
+/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT14_INT_CLR    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M  (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S  6
+/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT15_INT_CLR    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M  (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S)
+#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S  7
+/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_START_INT_CLR    (BIT(8))
+#define SDIO_SLC1_RX_START_INT_CLR_M  (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S)
+#define SDIO_SLC1_RX_START_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_RX_START_INT_CLR_S  8
+/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_START_INT_CLR    (BIT(9))
+#define SDIO_SLC1_TX_START_INT_CLR_M  (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S)
+#define SDIO_SLC1_TX_START_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TX_START_INT_CLR_S  9
+/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_UDF_INT_CLR    (BIT(10))
+#define SDIO_SLC1_RX_UDF_INT_CLR_M  (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S)
+#define SDIO_SLC1_RX_UDF_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_RX_UDF_INT_CLR_S  10
+/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_OVF_INT_CLR    (BIT(11))
+#define SDIO_SLC1_TX_OVF_INT_CLR_M  (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S)
+#define SDIO_SLC1_TX_OVF_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TX_OVF_INT_CLR_S  11
+/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR    (BIT(12))
+#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M  (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S)
+#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S  12
+/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR    (BIT(13))
+#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M  (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S)
+#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S  13
+/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DONE_INT_CLR    (BIT(14))
+#define SDIO_SLC1_TX_DONE_INT_CLR_M  (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S)
+#define SDIO_SLC1_TX_DONE_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TX_DONE_INT_CLR_S  14
+/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SUC_EOF_INT_CLR    (BIT(15))
+#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M  (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S)
+#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S  15
+/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DONE_INT_CLR    (BIT(16))
+#define SDIO_SLC1_RX_DONE_INT_CLR_M  (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S)
+#define SDIO_SLC1_RX_DONE_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_RX_DONE_INT_CLR_S  16
+/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_EOF_INT_CLR    (BIT(17))
+#define SDIO_SLC1_RX_EOF_INT_CLR_M  (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S)
+#define SDIO_SLC1_RX_EOF_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_RX_EOF_INT_CLR_S  17
+/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOHOST_INT_CLR    (BIT(18))
+#define SDIO_SLC1_TOHOST_INT_CLR_M  (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S)
+#define SDIO_SLC1_TOHOST_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TOHOST_INT_CLR_S  18
+/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR    (BIT(19))
+#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M  (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S)
+#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S  19
+/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR    (BIT(20))
+#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M  (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S)
+#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S  20
+/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S)
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S  21
+/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_HOST_RD_ACK_INT_CLR    (BIT(22))
+#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M  (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S)
+#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S  22
+/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR    (BIT(23))
+#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M  (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S)
+#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S  23
+/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERR_EOF_INT_CLR    (BIT(24))
+#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M  (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S)
+#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V  0x00000001U
+#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S  24
+
+/** SDIO_SLCRX_STATUS_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLCRX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
+/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_FULL    (BIT(0))
+#define SDIO_SLC0_RX_FULL_M  (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S)
+#define SDIO_SLC0_RX_FULL_V  0x00000001U
+#define SDIO_SLC0_RX_FULL_S  0
+/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_EMPTY    (BIT(1))
+#define SDIO_SLC0_RX_EMPTY_M  (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S)
+#define SDIO_SLC0_RX_EMPTY_V  0x00000001U
+#define SDIO_SLC0_RX_EMPTY_S  1
+/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0;
+ *  the current buffer length when slc0 reads data from rx link
+ */
+#define SDIO_SLC0_RX_BUF_LEN    0x00003FFFU
+#define SDIO_SLC0_RX_BUF_LEN_M  (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S)
+#define SDIO_SLC0_RX_BUF_LEN_V  0x00003FFFU
+#define SDIO_SLC0_RX_BUF_LEN_S  2
+/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_FULL    (BIT(16))
+#define SDIO_SLC1_RX_FULL_M  (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S)
+#define SDIO_SLC1_RX_FULL_V  0x00000001U
+#define SDIO_SLC1_RX_FULL_S  16
+/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_EMPTY    (BIT(17))
+#define SDIO_SLC1_RX_EMPTY_M  (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S)
+#define SDIO_SLC1_RX_EMPTY_V  0x00000001U
+#define SDIO_SLC1_RX_EMPTY_S  17
+/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0;
+ *  the current buffer length when slc1 reads data from rx link
+ */
+#define SDIO_SLC1_RX_BUF_LEN    0x00003FFFU
+#define SDIO_SLC1_RX_BUF_LEN_M  (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S)
+#define SDIO_SLC1_RX_BUF_LEN_V  0x00003FFFU
+#define SDIO_SLC1_RX_BUF_LEN_S  18
+
+/** SDIO_SLC0RXFIFO_PUSH_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28)
+/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXFIFO_WDATA    0x000001FFU
+#define SDIO_SLC0_RXFIFO_WDATA_M  (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S)
+#define SDIO_SLC0_RXFIFO_WDATA_V  0x000001FFU
+#define SDIO_SLC0_RXFIFO_WDATA_S  0
+/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXFIFO_PUSH    (BIT(16))
+#define SDIO_SLC0_RXFIFO_PUSH_M  (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S)
+#define SDIO_SLC0_RXFIFO_PUSH_V  0x00000001U
+#define SDIO_SLC0_RXFIFO_PUSH_S  16
+
+/** SDIO_SLC1RXFIFO_PUSH_REG register
+ *  reserved
+ */
+#define SDIO_SLC1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2c)
+/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXFIFO_WDATA    0x000001FFU
+#define SDIO_SLC1_RXFIFO_WDATA_M  (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S)
+#define SDIO_SLC1_RXFIFO_WDATA_V  0x000001FFU
+#define SDIO_SLC1_RXFIFO_WDATA_S  0
+/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXFIFO_PUSH    (BIT(16))
+#define SDIO_SLC1_RXFIFO_PUSH_M  (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S)
+#define SDIO_SLC1_RXFIFO_PUSH_V  0x00000001U
+#define SDIO_SLC1_RXFIFO_PUSH_S  16
+
+/** SDIO_SLCTX_STATUS_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLCTX_STATUS_REG (DR_REG_SLC_BASE + 0x30)
+/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_FULL    (BIT(0))
+#define SDIO_SLC0_TX_FULL_M  (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S)
+#define SDIO_SLC0_TX_FULL_V  0x00000001U
+#define SDIO_SLC0_TX_FULL_S  0
+/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_EMPTY    (BIT(1))
+#define SDIO_SLC0_TX_EMPTY_M  (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S)
+#define SDIO_SLC0_TX_EMPTY_V  0x00000001U
+#define SDIO_SLC0_TX_EMPTY_S  1
+/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_FULL    (BIT(16))
+#define SDIO_SLC1_TX_FULL_M  (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S)
+#define SDIO_SLC1_TX_FULL_V  0x00000001U
+#define SDIO_SLC1_TX_FULL_S  16
+/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_EMPTY    (BIT(17))
+#define SDIO_SLC1_TX_EMPTY_M  (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S)
+#define SDIO_SLC1_TX_EMPTY_V  0x00000001U
+#define SDIO_SLC1_TX_EMPTY_S  17
+
+/** SDIO_SLC0TXFIFO_POP_REG register
+ *  reserved
+ */
+#define SDIO_SLC0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34)
+/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024;
+ *  reserved
+ */
+#define SDIO_SLC0_TXFIFO_RDATA    0x000007FFU
+#define SDIO_SLC0_TXFIFO_RDATA_M  (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S)
+#define SDIO_SLC0_TXFIFO_RDATA_V  0x000007FFU
+#define SDIO_SLC0_TXFIFO_RDATA_S  0
+/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXFIFO_POP    (BIT(16))
+#define SDIO_SLC0_TXFIFO_POP_M  (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S)
+#define SDIO_SLC0_TXFIFO_POP_V  0x00000001U
+#define SDIO_SLC0_TXFIFO_POP_S  16
+
+/** SDIO_SLC1TXFIFO_POP_REG register
+ *  reserved
+ */
+#define SDIO_SLC1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38)
+/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024;
+ *  reserved
+ */
+#define SDIO_SLC1_TXFIFO_RDATA    0x000007FFU
+#define SDIO_SLC1_TXFIFO_RDATA_M  (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S)
+#define SDIO_SLC1_TXFIFO_RDATA_V  0x000007FFU
+#define SDIO_SLC1_TXFIFO_RDATA_S  0
+/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXFIFO_POP    (BIT(16))
+#define SDIO_SLC1_TXFIFO_POP_M  (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S)
+#define SDIO_SLC1_TXFIFO_POP_V  0x00000001U
+#define SDIO_SLC1_TXFIFO_POP_S  16
+
+/** SDIO_SLC0RX_LINK_REG register
+ *  reserved
+ */
+#define SDIO_SLC0RX_LINK_REG (DR_REG_SLC_BASE + 0x3c)
+/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_STOP    (BIT(28))
+#define SDIO_SLC0_RXLINK_STOP_M  (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S)
+#define SDIO_SLC0_RXLINK_STOP_V  0x00000001U
+#define SDIO_SLC0_RXLINK_STOP_S  28
+/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_START    (BIT(29))
+#define SDIO_SLC0_RXLINK_START_M  (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S)
+#define SDIO_SLC0_RXLINK_START_V  0x00000001U
+#define SDIO_SLC0_RXLINK_START_S  29
+/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_RESTART    (BIT(30))
+#define SDIO_SLC0_RXLINK_RESTART_M  (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S)
+#define SDIO_SLC0_RXLINK_RESTART_V  0x00000001U
+#define SDIO_SLC0_RXLINK_RESTART_S  30
+/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_PARK    (BIT(31))
+#define SDIO_SLC0_RXLINK_PARK_M  (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S)
+#define SDIO_SLC0_RXLINK_PARK_V  0x00000001U
+#define SDIO_SLC0_RXLINK_PARK_S  31
+
+/** SDIO_SLC0RX_LINK_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x40)
+/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_ADDR_M  (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S)
+#define SDIO_SLC0_RXLINK_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_ADDR_S  0
+
+/** SDIO_SLC0TX_LINK_REG register
+ *  reserved
+ */
+#define SDIO_SLC0TX_LINK_REG (DR_REG_SLC_BASE + 0x44)
+/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_STOP    (BIT(28))
+#define SDIO_SLC0_TXLINK_STOP_M  (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S)
+#define SDIO_SLC0_TXLINK_STOP_V  0x00000001U
+#define SDIO_SLC0_TXLINK_STOP_S  28
+/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_START    (BIT(29))
+#define SDIO_SLC0_TXLINK_START_M  (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S)
+#define SDIO_SLC0_TXLINK_START_V  0x00000001U
+#define SDIO_SLC0_TXLINK_START_S  29
+/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_RESTART    (BIT(30))
+#define SDIO_SLC0_TXLINK_RESTART_M  (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S)
+#define SDIO_SLC0_TXLINK_RESTART_V  0x00000001U
+#define SDIO_SLC0_TXLINK_RESTART_S  30
+/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_PARK    (BIT(31))
+#define SDIO_SLC0_TXLINK_PARK_M  (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S)
+#define SDIO_SLC0_TXLINK_PARK_V  0x00000001U
+#define SDIO_SLC0_TXLINK_PARK_S  31
+
+/** SDIO_SLC0TX_LINK_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x48)
+/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_ADDR_M  (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S)
+#define SDIO_SLC0_TXLINK_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_ADDR_S  0
+
+/** SDIO_SLC1RX_LINK_REG register
+ *  reserved
+ */
+#define SDIO_SLC1RX_LINK_REG (DR_REG_SLC_BASE + 0x4c)
+/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_BT_PACKET    (BIT(20))
+#define SDIO_SLC1_BT_PACKET_M  (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S)
+#define SDIO_SLC1_BT_PACKET_V  0x00000001U
+#define SDIO_SLC1_BT_PACKET_S  20
+/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_STOP    (BIT(28))
+#define SDIO_SLC1_RXLINK_STOP_M  (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S)
+#define SDIO_SLC1_RXLINK_STOP_V  0x00000001U
+#define SDIO_SLC1_RXLINK_STOP_S  28
+/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_START    (BIT(29))
+#define SDIO_SLC1_RXLINK_START_M  (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S)
+#define SDIO_SLC1_RXLINK_START_V  0x00000001U
+#define SDIO_SLC1_RXLINK_START_S  29
+/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_RESTART    (BIT(30))
+#define SDIO_SLC1_RXLINK_RESTART_M  (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S)
+#define SDIO_SLC1_RXLINK_RESTART_V  0x00000001U
+#define SDIO_SLC1_RXLINK_RESTART_S  30
+/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_PARK    (BIT(31))
+#define SDIO_SLC1_RXLINK_PARK_M  (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S)
+#define SDIO_SLC1_RXLINK_PARK_V  0x00000001U
+#define SDIO_SLC1_RXLINK_PARK_S  31
+
+/** SDIO_SLC1RX_LINK_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x50)
+/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_ADDR    0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_ADDR_M  (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S)
+#define SDIO_SLC1_RXLINK_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_ADDR_S  0
+
+/** SDIO_SLC1TX_LINK_REG register
+ *  reserved
+ */
+#define SDIO_SLC1TX_LINK_REG (DR_REG_SLC_BASE + 0x54)
+/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_STOP    (BIT(28))
+#define SDIO_SLC1_TXLINK_STOP_M  (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S)
+#define SDIO_SLC1_TXLINK_STOP_V  0x00000001U
+#define SDIO_SLC1_TXLINK_STOP_S  28
+/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_START    (BIT(29))
+#define SDIO_SLC1_TXLINK_START_M  (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S)
+#define SDIO_SLC1_TXLINK_START_V  0x00000001U
+#define SDIO_SLC1_TXLINK_START_S  29
+/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_RESTART    (BIT(30))
+#define SDIO_SLC1_TXLINK_RESTART_M  (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S)
+#define SDIO_SLC1_TXLINK_RESTART_V  0x00000001U
+#define SDIO_SLC1_TXLINK_RESTART_S  30
+/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_PARK    (BIT(31))
+#define SDIO_SLC1_TXLINK_PARK_M  (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S)
+#define SDIO_SLC1_TXLINK_PARK_V  0x00000001U
+#define SDIO_SLC1_TXLINK_PARK_S  31
+
+/** SDIO_SLC1TX_LINK_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x58)
+/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_ADDR    0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_ADDR_M  (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S)
+#define SDIO_SLC1_TXLINK_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_ADDR_S  0
+
+/** SDIO_SLCINTVEC_TOHOST_REG register
+ *  reserved
+ */
+#define SDIO_SLCINTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x5c)
+/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOHOST_INTVEC    0x000000FFU
+#define SDIO_SLC0_TOHOST_INTVEC_M  (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S)
+#define SDIO_SLC0_TOHOST_INTVEC_V  0x000000FFU
+#define SDIO_SLC0_TOHOST_INTVEC_S  0
+/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOHOST_INTVEC    0x000000FFU
+#define SDIO_SLC1_TOHOST_INTVEC_M  (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S)
+#define SDIO_SLC1_TOHOST_INTVEC_V  0x000000FFU
+#define SDIO_SLC1_TOHOST_INTVEC_S  16
+
+/** SDIO_SLC0TOKEN0_REG register
+ *  reserved
+ */
+#define SDIO_SLC0TOKEN0_REG (DR_REG_SLC_BASE + 0x60)
+/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_WDATA    0x00000FFFU
+#define SDIO_SLC0_TOKEN0_WDATA_M  (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S)
+#define SDIO_SLC0_TOKEN0_WDATA_V  0x00000FFFU
+#define SDIO_SLC0_TOKEN0_WDATA_S  0
+/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_WR    (BIT(12))
+#define SDIO_SLC0_TOKEN0_WR_M  (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S)
+#define SDIO_SLC0_TOKEN0_WR_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_WR_S  12
+/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_INC    (BIT(13))
+#define SDIO_SLC0_TOKEN0_INC_M  (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S)
+#define SDIO_SLC0_TOKEN0_INC_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_INC_S  13
+/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_INC_MORE    (BIT(14))
+#define SDIO_SLC0_TOKEN0_INC_MORE_M  (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S)
+#define SDIO_SLC0_TOKEN0_INC_MORE_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_INC_MORE_S  14
+/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0    0x00000FFFU
+#define SDIO_SLC0_TOKEN0_M  (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S)
+#define SDIO_SLC0_TOKEN0_V  0x00000FFFU
+#define SDIO_SLC0_TOKEN0_S  16
+
+/** SDIO_SLC0TOKEN1_REG register
+ *  reserved
+ */
+#define SDIO_SLC0TOKEN1_REG (DR_REG_SLC_BASE + 0x64)
+/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0;
+ *  slc0 token1 wdata
+ */
+#define SDIO_SLC0_TOKEN1_WDATA    0x00000FFFU
+#define SDIO_SLC0_TOKEN1_WDATA_M  (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S)
+#define SDIO_SLC0_TOKEN1_WDATA_V  0x00000FFFU
+#define SDIO_SLC0_TOKEN1_WDATA_S  0
+/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0;
+ *  update slc0_token1_wdata into slc0 token1
+ */
+#define SDIO_SLC0_TOKEN1_WR    (BIT(12))
+#define SDIO_SLC0_TOKEN1_WR_M  (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S)
+#define SDIO_SLC0_TOKEN1_WR_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_WR_S  12
+/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0;
+ *  slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1
+ */
+#define SDIO_SLC0_TOKEN1_INC    (BIT(13))
+#define SDIO_SLC0_TOKEN1_INC_M  (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S)
+#define SDIO_SLC0_TOKEN1_INC_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_INC_S  13
+/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0;
+ *  slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add
+ *  slc0_token1_wdata to slc0_token1
+ */
+#define SDIO_SLC0_TOKEN1_INC_MORE    (BIT(14))
+#define SDIO_SLC0_TOKEN1_INC_MORE_M  (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S)
+#define SDIO_SLC0_TOKEN1_INC_MORE_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_INC_MORE_S  14
+/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN1    0x00000FFFU
+#define SDIO_SLC0_TOKEN1_M  (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S)
+#define SDIO_SLC0_TOKEN1_V  0x00000FFFU
+#define SDIO_SLC0_TOKEN1_S  16
+
+/** SDIO_SLC1TOKEN0_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC1TOKEN0_REG (DR_REG_SLC_BASE + 0x68)
+/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_WDATA    0x00000FFFU
+#define SDIO_SLC1_TOKEN0_WDATA_M  (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S)
+#define SDIO_SLC1_TOKEN0_WDATA_V  0x00000FFFU
+#define SDIO_SLC1_TOKEN0_WDATA_S  0
+/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_WR    (BIT(12))
+#define SDIO_SLC1_TOKEN0_WR_M  (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S)
+#define SDIO_SLC1_TOKEN0_WR_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_WR_S  12
+/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0;
+ *  Add 1 to  slc1_token0
+ */
+#define SDIO_SLC1_TOKEN0_INC    (BIT(13))
+#define SDIO_SLC1_TOKEN0_INC_M  (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S)
+#define SDIO_SLC1_TOKEN0_INC_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_INC_S  13
+/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0;
+ *  Add  slc1_token0_wdata to  slc1_token0
+ */
+#define SDIO_SLC1_TOKEN0_INC_MORE    (BIT(14))
+#define SDIO_SLC1_TOKEN0_INC_MORE_M  (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S)
+#define SDIO_SLC1_TOKEN0_INC_MORE_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_INC_MORE_S  14
+/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0    0x00000FFFU
+#define SDIO_SLC1_TOKEN0_M  (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S)
+#define SDIO_SLC1_TOKEN0_V  0x00000FFFU
+#define SDIO_SLC1_TOKEN0_S  16
+
+/** SDIO_SLC1TOKEN1_REG register
+ *  reserved
+ */
+#define SDIO_SLC1TOKEN1_REG (DR_REG_SLC_BASE + 0x6c)
+/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_WDATA    0x00000FFFU
+#define SDIO_SLC1_TOKEN1_WDATA_M  (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S)
+#define SDIO_SLC1_TOKEN1_WDATA_V  0x00000FFFU
+#define SDIO_SLC1_TOKEN1_WDATA_S  0
+/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0;
+ *  update slc1_token1_wdata into slc1 token1
+ */
+#define SDIO_SLC1_TOKEN1_WR    (BIT(12))
+#define SDIO_SLC1_TOKEN1_WR_M  (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S)
+#define SDIO_SLC1_TOKEN1_WR_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_WR_S  12
+/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_INC    (BIT(13))
+#define SDIO_SLC1_TOKEN1_INC_M  (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S)
+#define SDIO_SLC1_TOKEN1_INC_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_INC_S  13
+/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_INC_MORE    (BIT(14))
+#define SDIO_SLC1_TOKEN1_INC_MORE_M  (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S)
+#define SDIO_SLC1_TOKEN1_INC_MORE_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_INC_MORE_S  14
+/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1    0x00000FFFU
+#define SDIO_SLC1_TOKEN1_M  (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S)
+#define SDIO_SLC1_TOKEN1_V  0x00000FFFU
+#define SDIO_SLC1_TOKEN1_S  16
+
+/** SDIO_SLCCONF1_REG register
+ *  reserved
+ */
+#define SDIO_SLCCONF1_REG (DR_REG_SLC_BASE + 0x70)
+/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_CHECK_OWNER    (BIT(0))
+#define SDIO_SLC0_CHECK_OWNER_M  (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S)
+#define SDIO_SLC0_CHECK_OWNER_V  0x00000001U
+#define SDIO_SLC0_CHECK_OWNER_S  0
+/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_CHECK_SUM_EN    (BIT(1))
+#define SDIO_SLC0_TX_CHECK_SUM_EN_M  (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S)
+#define SDIO_SLC0_TX_CHECK_SUM_EN_V  0x00000001U
+#define SDIO_SLC0_TX_CHECK_SUM_EN_S  1
+/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_CHECK_SUM_EN    (BIT(2))
+#define SDIO_SLC0_RX_CHECK_SUM_EN_M  (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S)
+#define SDIO_SLC0_RX_CHECK_SUM_EN_V  0x00000001U
+#define SDIO_SLC0_RX_CHECK_SUM_EN_S  2
+/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1;
+ *  reserved
+ */
+#define SDIO_SDIO_CMD_HOLD_EN    (BIT(3))
+#define SDIO_SDIO_CMD_HOLD_EN_M  (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S)
+#define SDIO_SDIO_CMD_HOLD_EN_V  0x00000001U
+#define SDIO_SDIO_CMD_HOLD_EN_S  3
+/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_LEN_AUTO_CLR    (BIT(4))
+#define SDIO_SLC0_LEN_AUTO_CLR_M  (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S)
+#define SDIO_SLC0_LEN_AUTO_CLR_V  0x00000001U
+#define SDIO_SLC0_LEN_AUTO_CLR_S  4
+/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_STITCH_EN    (BIT(5))
+#define SDIO_SLC0_TX_STITCH_EN_M  (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S)
+#define SDIO_SLC0_TX_STITCH_EN_V  0x00000001U
+#define SDIO_SLC0_TX_STITCH_EN_S  5
+/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_STITCH_EN    (BIT(6))
+#define SDIO_SLC0_RX_STITCH_EN_M  (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S)
+#define SDIO_SLC0_RX_STITCH_EN_V  0x00000001U
+#define SDIO_SLC0_RX_STITCH_EN_S  6
+/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_CHECK_OWNER    (BIT(16))
+#define SDIO_SLC1_CHECK_OWNER_M  (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S)
+#define SDIO_SLC1_CHECK_OWNER_V  0x00000001U
+#define SDIO_SLC1_CHECK_OWNER_S  16
+/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_CHECK_SUM_EN    (BIT(17))
+#define SDIO_SLC1_TX_CHECK_SUM_EN_M  (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S)
+#define SDIO_SLC1_TX_CHECK_SUM_EN_V  0x00000001U
+#define SDIO_SLC1_TX_CHECK_SUM_EN_S  17
+/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_CHECK_SUM_EN    (BIT(18))
+#define SDIO_SLC1_RX_CHECK_SUM_EN_M  (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S)
+#define SDIO_SLC1_RX_CHECK_SUM_EN_V  0x00000001U
+#define SDIO_SLC1_RX_CHECK_SUM_EN_S  18
+/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_HOST_INT_LEVEL_SEL    (BIT(19))
+#define SDIO_HOST_INT_LEVEL_SEL_M  (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S)
+#define SDIO_HOST_INT_LEVEL_SEL_V  0x00000001U
+#define SDIO_HOST_INT_LEVEL_SEL_S  19
+/** SDIO_SLC1_TX_STITCH_EN : R/W; bitpos: [20]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_STITCH_EN    (BIT(20))
+#define SDIO_SLC1_TX_STITCH_EN_M  (SDIO_SLC1_TX_STITCH_EN_V << SDIO_SLC1_TX_STITCH_EN_S)
+#define SDIO_SLC1_TX_STITCH_EN_V  0x00000001U
+#define SDIO_SLC1_TX_STITCH_EN_S  20
+/** SDIO_SLC1_RX_STITCH_EN : R/W; bitpos: [21]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_STITCH_EN    (BIT(21))
+#define SDIO_SLC1_RX_STITCH_EN_M  (SDIO_SLC1_RX_STITCH_EN_V << SDIO_SLC1_RX_STITCH_EN_S)
+#define SDIO_SLC1_RX_STITCH_EN_V  0x00000001U
+#define SDIO_SLC1_RX_STITCH_EN_S  21
+/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_CLK_EN    (BIT(22))
+#define SDIO_SDIO_CLK_EN_M  (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S)
+#define SDIO_SDIO_CLK_EN_V  0x00000001U
+#define SDIO_SDIO_CLK_EN_S  22
+
+/** SDIO_SLC0_STATE0_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_STATE0_REG (DR_REG_SLC_BASE + 0x74)
+/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_STATE0    0xFFFFFFFFU
+#define SDIO_SLC0_STATE0_M  (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S)
+#define SDIO_SLC0_STATE0_V  0xFFFFFFFFU
+#define SDIO_SLC0_STATE0_S  0
+
+/** SDIO_SLC0_STATE1_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_STATE1_REG (DR_REG_SLC_BASE + 0x78)
+/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0;
+ *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
+ *  rx_link fsm state, [30:24] rx_fifo_cnt
+ */
+#define SDIO_SLC0_STATE1    0xFFFFFFFFU
+#define SDIO_SLC0_STATE1_M  (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S)
+#define SDIO_SLC0_STATE1_V  0xFFFFFFFFU
+#define SDIO_SLC0_STATE1_S  0
+
+/** SDIO_SLC1_STATE0_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC1_STATE0_REG (DR_REG_SLC_BASE + 0x7c)
+/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_STATE0    0xFFFFFFFFU
+#define SDIO_SLC1_STATE0_M  (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S)
+#define SDIO_SLC1_STATE0_V  0xFFFFFFFFU
+#define SDIO_SLC1_STATE0_S  0
+
+/** SDIO_SLC1_STATE1_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC1_STATE1_REG (DR_REG_SLC_BASE + 0x80)
+/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0;
+ *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
+ *  rx_link fsm state, [30:24] rx_fifo_cnt
+ */
+#define SDIO_SLC1_STATE1    0xFFFFFFFFU
+#define SDIO_SLC1_STATE1_M  (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S)
+#define SDIO_SLC1_STATE1_V  0xFFFFFFFFU
+#define SDIO_SLC1_STATE1_S  0
+
+/** SDIO_SLCBRIDGE_CONF_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLCBRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x84)
+/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32;
+ *  reserved
+ */
+#define SDIO_SLC_TXEOF_ENA    0x0000003FU
+#define SDIO_SLC_TXEOF_ENA_M  (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S)
+#define SDIO_SLC_TXEOF_ENA_V  0x0000003FU
+#define SDIO_SLC_TXEOF_ENA_S  0
+/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7;
+ *  reserved
+ */
+#define SDIO_SLC_FIFO_MAP_ENA    0x0000000FU
+#define SDIO_SLC_FIFO_MAP_ENA_M  (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S)
+#define SDIO_SLC_FIFO_MAP_ENA_V  0x0000000FU
+#define SDIO_SLC_FIFO_MAP_ENA_S  8
+/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DUMMY_MODE    (BIT(12))
+#define SDIO_SLC0_TX_DUMMY_MODE_M  (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S)
+#define SDIO_SLC0_TX_DUMMY_MODE_V  0x00000001U
+#define SDIO_SLC0_TX_DUMMY_MODE_S  12
+/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC_HDA_MAP_128K    (BIT(13))
+#define SDIO_SLC_HDA_MAP_128K_M  (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S)
+#define SDIO_SLC_HDA_MAP_128K_V  0x00000001U
+#define SDIO_SLC_HDA_MAP_128K_S  13
+/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DUMMY_MODE    (BIT(14))
+#define SDIO_SLC1_TX_DUMMY_MODE_M  (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S)
+#define SDIO_SLC1_TX_DUMMY_MODE_V  0x00000001U
+#define SDIO_SLC1_TX_DUMMY_MODE_S  14
+/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10;
+ *  reserved
+ */
+#define SDIO_SLC_TX_PUSH_IDLE_NUM    0x0000FFFFU
+#define SDIO_SLC_TX_PUSH_IDLE_NUM_M  (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S)
+#define SDIO_SLC_TX_PUSH_IDLE_NUM_V  0x0000FFFFU
+#define SDIO_SLC_TX_PUSH_IDLE_NUM_S  16
+
+/** SDIO_SLC0_TO_EOF_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88)
+/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TO_EOF_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TO_EOF_DES_ADDR_M  (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S)
+#define SDIO_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TO_EOF_DES_ADDR_S  0
+
+/** SDIO_SLC0_TX_EOF_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8c)
+/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M  (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S)
+#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S  0
+
+/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x90)
+/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M  (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S)
+#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S  0
+
+/** SDIO_SLC1_TO_EOF_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x94)
+/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TO_EOF_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC1_TO_EOF_DES_ADDR_M  (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S)
+#define SDIO_SLC1_TO_EOF_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC1_TO_EOF_DES_ADDR_S  0
+
+/** SDIO_SLC1_TX_EOF_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x98)
+/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M  (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S)
+#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S  0
+
+/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x9c)
+/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M  (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S)
+#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S  0
+
+/** SDIO_SLC_AHB_TEST_REG register
+ *  reserved
+ */
+#define SDIO_SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0xa0)
+/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_AHB_TESTMODE    0x00000007U
+#define SDIO_SLC_AHB_TESTMODE_M  (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S)
+#define SDIO_SLC_AHB_TESTMODE_V  0x00000007U
+#define SDIO_SLC_AHB_TESTMODE_S  0
+/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_AHB_TESTADDR    0x00000003U
+#define SDIO_SLC_AHB_TESTADDR_M  (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S)
+#define SDIO_SLC_AHB_TESTADDR_V  0x00000003U
+#define SDIO_SLC_AHB_TESTADDR_S  4
+
+/** SDIO_SLC_SDIO_ST_REG register
+ *  reserved
+ */
+#define SDIO_SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0xa4)
+/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_ST    0x00000007U
+#define SDIO_CMD_ST_M  (SDIO_CMD_ST_V << SDIO_CMD_ST_S)
+#define SDIO_CMD_ST_V  0x00000007U
+#define SDIO_CMD_ST_S  0
+/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0;
+ *  reserved
+ */
+#define SDIO_FUNC_ST    0x0000000FU
+#define SDIO_FUNC_ST_M  (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S)
+#define SDIO_FUNC_ST_V  0x0000000FU
+#define SDIO_FUNC_ST_S  4
+/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_WAKEUP    (BIT(8))
+#define SDIO_SDIO_WAKEUP_M  (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S)
+#define SDIO_SDIO_WAKEUP_V  0x00000001U
+#define SDIO_SDIO_WAKEUP_S  8
+/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0;
+ *  reserved
+ */
+#define SDIO_BUS_ST    0x00000007U
+#define SDIO_BUS_ST_M  (SDIO_BUS_ST_V << SDIO_BUS_ST_S)
+#define SDIO_BUS_ST_V  0x00000007U
+#define SDIO_BUS_ST_S  12
+/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_FUNC1_ACC_STATE    0x0000001FU
+#define SDIO_FUNC1_ACC_STATE_M  (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S)
+#define SDIO_FUNC1_ACC_STATE_V  0x0000001FU
+#define SDIO_FUNC1_ACC_STATE_S  16
+/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0;
+ *  reserved
+ */
+#define SDIO_FUNC2_ACC_STATE    0x0000001FU
+#define SDIO_FUNC2_ACC_STATE_M  (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S)
+#define SDIO_FUNC2_ACC_STATE_V  0x0000001FU
+#define SDIO_FUNC2_ACC_STATE_S  24
+
+/** SDIO_SLC_RX_DSCR_CONF_REG register
+ *  reserved
+ */
+#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xa8)
+/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN_NO_REPLACE    (BIT(0))
+#define SDIO_SLC0_TOKEN_NO_REPLACE_M  (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S)
+#define SDIO_SLC0_TOKEN_NO_REPLACE_V  0x00000001U
+#define SDIO_SLC0_TOKEN_NO_REPLACE_S  0
+/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_INFOR_NO_REPLACE    (BIT(1))
+#define SDIO_SLC0_INFOR_NO_REPLACE_M  (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S)
+#define SDIO_SLC0_INFOR_NO_REPLACE_V  0x00000001U
+#define SDIO_SLC0_INFOR_NO_REPLACE_S  1
+/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0;
+ *  slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next
+ *  pop doesn't occur after 255 cycles since the current pop
+ */
+#define SDIO_SLC0_RX_FILL_MODE    (BIT(2))
+#define SDIO_SLC0_RX_FILL_MODE_M  (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S)
+#define SDIO_SLC0_RX_FILL_MODE_V  0x00000001U
+#define SDIO_SLC0_RX_FILL_MODE_S  2
+/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1;
+ *  0-slc0 rx_push_eof, 1-slc0 rx_pop_eof
+ */
+#define SDIO_SLC0_RX_EOF_MODE    (BIT(3))
+#define SDIO_SLC0_RX_EOF_MODE_M  (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S)
+#define SDIO_SLC0_RX_EOF_MODE_V  0x00000001U
+#define SDIO_SLC0_RX_EOF_MODE_S  3
+/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_FILL_EN    (BIT(4))
+#define SDIO_SLC0_RX_FILL_EN_M  (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S)
+#define SDIO_SLC0_RX_FILL_EN_V  0x00000001U
+#define SDIO_SLC0_RX_FILL_EN_S  4
+/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128;
+ *  reserved
+ */
+#define SDIO_SLC0_RD_RETRY_THRESHOLD    0x000007FFU
+#define SDIO_SLC0_RD_RETRY_THRESHOLD_M  (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S)
+#define SDIO_SLC0_RD_RETRY_THRESHOLD_V  0x000007FFU
+#define SDIO_SLC0_RD_RETRY_THRESHOLD_S  5
+/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN_NO_REPLACE    (BIT(16))
+#define SDIO_SLC1_TOKEN_NO_REPLACE_M  (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S)
+#define SDIO_SLC1_TOKEN_NO_REPLACE_V  0x00000001U
+#define SDIO_SLC1_TOKEN_NO_REPLACE_S  16
+/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_INFOR_NO_REPLACE    (BIT(17))
+#define SDIO_SLC1_INFOR_NO_REPLACE_M  (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S)
+#define SDIO_SLC1_INFOR_NO_REPLACE_V  0x00000001U
+#define SDIO_SLC1_INFOR_NO_REPLACE_S  17
+/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0;
+ *  slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next
+ *  pop doesn't occur after 255 cycles since the current pop
+ */
+#define SDIO_SLC1_RX_FILL_MODE    (BIT(18))
+#define SDIO_SLC1_RX_FILL_MODE_M  (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S)
+#define SDIO_SLC1_RX_FILL_MODE_V  0x00000001U
+#define SDIO_SLC1_RX_FILL_MODE_S  18
+/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1;
+ *  0-slc1 rx_push_eof, 1-slc1 rx_pop_eof
+ */
+#define SDIO_SLC1_RX_EOF_MODE    (BIT(19))
+#define SDIO_SLC1_RX_EOF_MODE_M  (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S)
+#define SDIO_SLC1_RX_EOF_MODE_V  0x00000001U
+#define SDIO_SLC1_RX_EOF_MODE_S  19
+/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_FILL_EN    (BIT(20))
+#define SDIO_SLC1_RX_FILL_EN_M  (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S)
+#define SDIO_SLC1_RX_FILL_EN_V  0x00000001U
+#define SDIO_SLC1_RX_FILL_EN_S  20
+/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128;
+ *  reserved
+ */
+#define SDIO_SLC1_RD_RETRY_THRESHOLD    0x000007FFU
+#define SDIO_SLC1_RD_RETRY_THRESHOLD_M  (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S)
+#define SDIO_SLC1_RD_RETRY_THRESHOLD_V  0x000007FFU
+#define SDIO_SLC1_RD_RETRY_THRESHOLD_S  21
+
+/** SDIO_SLC0_TXLINK_DSCR_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xac)
+/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_DSCR    0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_DSCR_M  (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S)
+#define SDIO_SLC0_TXLINK_DSCR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_DSCR_S  0
+
+/** SDIO_SLC0_TXLINK_DSCR_BF0_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xb0)
+/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_DSCR_BF0    0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_DSCR_BF0_M  (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S)
+#define SDIO_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_DSCR_BF0_S  0
+
+/** SDIO_SLC0_TXLINK_DSCR_BF1_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xb4)
+/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TXLINK_DSCR_BF1    0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_DSCR_BF1_M  (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S)
+#define SDIO_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFFU
+#define SDIO_SLC0_TXLINK_DSCR_BF1_S  0
+
+/** SDIO_SLC0_RXLINK_DSCR_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xb8)
+/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
+ *  the third word of slc0 link descriptor, or known as the next descriptor address
+ */
+#define SDIO_SLC0_RXLINK_DSCR    0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_DSCR_M  (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S)
+#define SDIO_SLC0_RXLINK_DSCR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_DSCR_S  0
+
+/** SDIO_SLC0_RXLINK_DSCR_BF0_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xbc)
+/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_DSCR_BF0    0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_DSCR_BF0_M  (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S)
+#define SDIO_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_DSCR_BF0_S  0
+
+/** SDIO_SLC0_RXLINK_DSCR_BF1_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xc0)
+/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RXLINK_DSCR_BF1    0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_DSCR_BF1_M  (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S)
+#define SDIO_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFFU
+#define SDIO_SLC0_RXLINK_DSCR_BF1_S  0
+
+/** SDIO_SLC1_TXLINK_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xc4)
+/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_DSCR    0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_DSCR_M  (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S)
+#define SDIO_SLC1_TXLINK_DSCR_V  0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_DSCR_S  0
+
+/** SDIO_SLC1_TXLINK_DSCR_BF0_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xc8)
+/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_DSCR_BF0    0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_DSCR_BF0_M  (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S)
+#define SDIO_SLC1_TXLINK_DSCR_BF0_V  0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_DSCR_BF0_S  0
+
+/** SDIO_SLC1_TXLINK_DSCR_BF1_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xcc)
+/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TXLINK_DSCR_BF1    0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_DSCR_BF1_M  (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S)
+#define SDIO_SLC1_TXLINK_DSCR_BF1_V  0xFFFFFFFFU
+#define SDIO_SLC1_TXLINK_DSCR_BF1_S  0
+
+/** SDIO_SLC1_RXLINK_DSCR_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xd0)
+/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
+ *  the third word of slc1 link descriptor, or known as the next descriptor address
+ */
+#define SDIO_SLC1_RXLINK_DSCR    0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_DSCR_M  (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S)
+#define SDIO_SLC1_RXLINK_DSCR_V  0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_DSCR_S  0
+
+/** SDIO_SLC1_RXLINK_DSCR_BF0_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xd4)
+/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_DSCR_BF0    0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_DSCR_BF0_M  (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S)
+#define SDIO_SLC1_RXLINK_DSCR_BF0_V  0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_DSCR_BF0_S  0
+
+/** SDIO_SLC1_RXLINK_DSCR_BF1_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xd8)
+/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RXLINK_DSCR_BF1    0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_DSCR_BF1_M  (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S)
+#define SDIO_SLC1_RXLINK_DSCR_BF1_V  0xFFFFFFFFU
+#define SDIO_SLC1_RXLINK_DSCR_BF1_S  0
+
+/** SDIO_SLC0_TX_ERREOF_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xdc)
+/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M  (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S)
+#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S  0
+
+/** SDIO_SLC1_TX_ERREOF_DES_ADDR_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xe0)
+/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M  (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S)
+#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S  0
+
+/** SDIO_SLC_TOKEN_LAT_REG register
+ *  reserved
+ */
+#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xe4)
+/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN    0x00000FFFU
+#define SDIO_SLC0_TOKEN_M  (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S)
+#define SDIO_SLC0_TOKEN_V  0x00000FFFU
+#define SDIO_SLC0_TOKEN_S  0
+/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN    0x00000FFFU
+#define SDIO_SLC1_TOKEN_M  (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S)
+#define SDIO_SLC1_TOKEN_V  0x00000FFFU
+#define SDIO_SLC1_TOKEN_S  16
+
+/** SDIO_SLC_TX_DSCR_CONF_REG register
+ *  reserved
+ */
+#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xe8)
+/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128;
+ *  reserved
+ */
+#define SDIO_SLC_WR_RETRY_THRESHOLD    0x000007FFU
+#define SDIO_SLC_WR_RETRY_THRESHOLD_M  (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S)
+#define SDIO_SLC_WR_RETRY_THRESHOLD_V  0x000007FFU
+#define SDIO_SLC_WR_RETRY_THRESHOLD_S  0
+
+/** SDIO_SLC_CMD_INFOR0_REG register
+ *  reserved
+ */
+#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xec)
+/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_CONTENT0    0xFFFFFFFFU
+#define SDIO_CMD_CONTENT0_M  (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S)
+#define SDIO_CMD_CONTENT0_V  0xFFFFFFFFU
+#define SDIO_CMD_CONTENT0_S  0
+
+/** SDIO_SLC_CMD_INFOR1_REG register
+ *  reserved
+ */
+#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xf0)
+/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_CONTENT1    0xFFFFFFFFU
+#define SDIO_CMD_CONTENT1_M  (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S)
+#define SDIO_CMD_CONTENT1_V  0xFFFFFFFFU
+#define SDIO_CMD_CONTENT1_S  0
+
+/** SDIO_SLC0_LEN_CONF_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xf4)
+/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_LEN_WDATA    0x000FFFFFU
+#define SDIO_SLC0_LEN_WDATA_M  (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S)
+#define SDIO_SLC0_LEN_WDATA_V  0x000FFFFFU
+#define SDIO_SLC0_LEN_WDATA_S  0
+/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_LEN_WR    (BIT(20))
+#define SDIO_SLC0_LEN_WR_M  (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S)
+#define SDIO_SLC0_LEN_WR_V  0x00000001U
+#define SDIO_SLC0_LEN_WR_S  20
+/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_LEN_INC    (BIT(21))
+#define SDIO_SLC0_LEN_INC_M  (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S)
+#define SDIO_SLC0_LEN_INC_V  0x00000001U
+#define SDIO_SLC0_LEN_INC_S  21
+/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_LEN_INC_MORE    (BIT(22))
+#define SDIO_SLC0_LEN_INC_MORE_M  (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S)
+#define SDIO_SLC0_LEN_INC_MORE_V  0x00000001U
+#define SDIO_SLC0_LEN_INC_MORE_S  22
+/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_PACKET_LOAD_EN    (BIT(23))
+#define SDIO_SLC0_RX_PACKET_LOAD_EN_M  (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S)
+#define SDIO_SLC0_RX_PACKET_LOAD_EN_V  0x00000001U
+#define SDIO_SLC0_RX_PACKET_LOAD_EN_S  23
+/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_PACKET_LOAD_EN    (BIT(24))
+#define SDIO_SLC0_TX_PACKET_LOAD_EN_M  (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S)
+#define SDIO_SLC0_TX_PACKET_LOAD_EN_V  0x00000001U
+#define SDIO_SLC0_TX_PACKET_LOAD_EN_S  24
+/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_GET_USED_DSCR    (BIT(25))
+#define SDIO_SLC0_RX_GET_USED_DSCR_M  (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S)
+#define SDIO_SLC0_RX_GET_USED_DSCR_V  0x00000001U
+#define SDIO_SLC0_RX_GET_USED_DSCR_S  25
+/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_GET_USED_DSCR    (BIT(26))
+#define SDIO_SLC0_TX_GET_USED_DSCR_M  (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S)
+#define SDIO_SLC0_TX_GET_USED_DSCR_V  0x00000001U
+#define SDIO_SLC0_TX_GET_USED_DSCR_S  26
+/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_NEW_PKT_IND    (BIT(27))
+#define SDIO_SLC0_RX_NEW_PKT_IND_M  (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S)
+#define SDIO_SLC0_RX_NEW_PKT_IND_V  0x00000001U
+#define SDIO_SLC0_RX_NEW_PKT_IND_S  27
+/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_NEW_PKT_IND    (BIT(28))
+#define SDIO_SLC0_TX_NEW_PKT_IND_M  (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S)
+#define SDIO_SLC0_TX_NEW_PKT_IND_V  0x00000001U
+#define SDIO_SLC0_TX_NEW_PKT_IND_S  28
+/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST    (BIT(29))
+#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M  (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S)
+#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V  0x00000001U
+#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S  29
+/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST    (BIT(30))
+#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M  (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S)
+#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V  0x00000001U
+#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S  30
+
+/** SDIO_SLC0_LENGTH_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_LENGTH_REG (DR_REG_SLC_BASE + 0xf8)
+/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_LEN    0x000FFFFFU
+#define SDIO_SLC0_LEN_M  (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S)
+#define SDIO_SLC0_LEN_V  0x000FFFFFU
+#define SDIO_SLC0_LEN_S  0
+
+/** SDIO_SLC0_TXPKT_H_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xfc)
+/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S)
+#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_TXPKT_E_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x100)
+/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S)
+#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_RXPKT_H_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0x104)
+/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S)
+#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_RXPKT_E_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x108)
+/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S)
+#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_TXPKTU_H_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x10c)
+/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S)
+#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_TXPKTU_E_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x110)
+/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S)
+#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_RXPKTU_H_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x114)
+/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S)
+#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_RXPKTU_E_DSCR_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x118)
+/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S)
+#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S  0
+
+/** SDIO_SLC_SEQ_POSITION_REG register
+ *  reserved
+ */
+#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x11c)
+/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9;
+ *  reserved
+ */
+#define SDIO_SLC0_SEQ_POSITION    0x000000FFU
+#define SDIO_SLC0_SEQ_POSITION_M  (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S)
+#define SDIO_SLC0_SEQ_POSITION_V  0x000000FFU
+#define SDIO_SLC0_SEQ_POSITION_S  0
+/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5;
+ *  reserved
+ */
+#define SDIO_SLC1_SEQ_POSITION    0x000000FFU
+#define SDIO_SLC1_SEQ_POSITION_M  (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S)
+#define SDIO_SLC1_SEQ_POSITION_V  0x000000FFU
+#define SDIO_SLC1_SEQ_POSITION_S  8
+
+/** SDIO_SLC0_DSCR_REC_CONF_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x120)
+/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DSCR_REC_LIM    0x000003FFU
+#define SDIO_SLC0_RX_DSCR_REC_LIM_M  (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S)
+#define SDIO_SLC0_RX_DSCR_REC_LIM_V  0x000003FFU
+#define SDIO_SLC0_RX_DSCR_REC_LIM_S  0
+
+/** SDIO_SLC_SDIO_CRC_ST0_REG register
+ *  reserved
+ */
+#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x124)
+/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_DAT0_CRC_ERR_CNT    0x000000FFU
+#define SDIO_DAT0_CRC_ERR_CNT_M  (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S)
+#define SDIO_DAT0_CRC_ERR_CNT_V  0x000000FFU
+#define SDIO_DAT0_CRC_ERR_CNT_S  0
+/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0;
+ *  reserved
+ */
+#define SDIO_DAT1_CRC_ERR_CNT    0x000000FFU
+#define SDIO_DAT1_CRC_ERR_CNT_M  (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S)
+#define SDIO_DAT1_CRC_ERR_CNT_V  0x000000FFU
+#define SDIO_DAT1_CRC_ERR_CNT_S  8
+/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0;
+ *  reserved
+ */
+#define SDIO_DAT2_CRC_ERR_CNT    0x000000FFU
+#define SDIO_DAT2_CRC_ERR_CNT_M  (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S)
+#define SDIO_DAT2_CRC_ERR_CNT_V  0x000000FFU
+#define SDIO_DAT2_CRC_ERR_CNT_S  16
+/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define SDIO_DAT3_CRC_ERR_CNT    0x000000FFU
+#define SDIO_DAT3_CRC_ERR_CNT_M  (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S)
+#define SDIO_DAT3_CRC_ERR_CNT_V  0x000000FFU
+#define SDIO_DAT3_CRC_ERR_CNT_S  24
+
+/** SDIO_SLC_SDIO_CRC_ST1_REG register
+ *  reserved
+ */
+#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x128)
+/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_CRC_ERR_CNT    0x000000FFU
+#define SDIO_CMD_CRC_ERR_CNT_M  (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S)
+#define SDIO_CMD_CRC_ERR_CNT_V  0x000000FFU
+#define SDIO_CMD_CRC_ERR_CNT_S  0
+/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define SDIO_ERR_CNT_CLR    (BIT(31))
+#define SDIO_ERR_CNT_CLR_M  (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S)
+#define SDIO_ERR_CNT_CLR_V  0x00000001U
+#define SDIO_ERR_CNT_CLR_S  31
+
+/** SDIO_SLC0_EOF_START_DES_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x12c)
+/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_EOF_START_DES_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_EOF_START_DES_ADDR_M  (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S)
+#define SDIO_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_EOF_START_DES_ADDR_S  0
+
+/** SDIO_SLC0_PUSH_DSCR_ADDR_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x130)
+/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
+ */
+#define SDIO_SLC0_RX_PUSH_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M  (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S)
+#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_DONE_DSCR_ADDR_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x134)
+/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  the current descriptor address when slc0 finishes reading data from one buffer,
+ *  aligned with word
+ */
+#define SDIO_SLC0_RX_DONE_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M  (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S)
+#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_SUB_START_DES_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x138)
+/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
+ */
+#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR    0xFFFFFFFFU
+#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M  (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S)
+#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFFU
+#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
+
+/** SDIO_SLC0_DSCR_CNT_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x13c)
+/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0;
+ *  the number of descriptors got by slc0 when it tries to read data from memory
+ */
+#define SDIO_SLC0_RX_DSCR_CNT_LAT    0x000003FFU
+#define SDIO_SLC0_RX_DSCR_CNT_LAT_M  (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S)
+#define SDIO_SLC0_RX_DSCR_CNT_LAT_V  0x000003FFU
+#define SDIO_SLC0_RX_DSCR_CNT_LAT_S  0
+/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_GET_EOF_OCC    (BIT(16))
+#define SDIO_SLC0_RX_GET_EOF_OCC_M  (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S)
+#define SDIO_SLC0_RX_GET_EOF_OCC_V  0x00000001U
+#define SDIO_SLC0_RX_GET_EOF_OCC_S  16
+
+/** SDIO_SLC0_LEN_LIM_CONF_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLC0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x140)
+/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504;
+ *  reserved
+ */
+#define SDIO_SLC0_LEN_LIM    0x000FFFFFU
+#define SDIO_SLC0_LEN_LIM_M  (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S)
+#define SDIO_SLC0_LEN_LIM_V  0x000FFFFFU
+#define SDIO_SLC0_LEN_LIM_S  0
+
+/** SDIO_SLC0INT_ST1_REG register
+ *  reserved
+ */
+#define SDIO_SLC0INT_ST1_REG (DR_REG_SLC_BASE + 0x144)
+/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT0_INT_ST1    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M  (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S  0
+/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT1_INT_ST1    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M  (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S  1
+/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT2_INT_ST1    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M  (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S  2
+/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT3_INT_ST1    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M  (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S  3
+/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT4_INT_ST1    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M  (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S  4
+/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT5_INT_ST1    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M  (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S  5
+/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT6_INT_ST1    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M  (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S  6
+/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT7_INT_ST1    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M  (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S  7
+/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_START_INT_ST1    (BIT(8))
+#define SDIO_SLC0_RX_START_INT_ST1_M  (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S)
+#define SDIO_SLC0_RX_START_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_RX_START_INT_ST1_S  8
+/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_START_INT_ST1    (BIT(9))
+#define SDIO_SLC0_TX_START_INT_ST1_M  (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S)
+#define SDIO_SLC0_TX_START_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TX_START_INT_ST1_S  9
+/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_UDF_INT_ST1    (BIT(10))
+#define SDIO_SLC0_RX_UDF_INT_ST1_M  (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S)
+#define SDIO_SLC0_RX_UDF_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_RX_UDF_INT_ST1_S  10
+/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_OVF_INT_ST1    (BIT(11))
+#define SDIO_SLC0_TX_OVF_INT_ST1_M  (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S)
+#define SDIO_SLC0_TX_OVF_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TX_OVF_INT_ST1_S  11
+/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1    (BIT(12))
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S)
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S  12
+/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1    (BIT(13))
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S)
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S  13
+/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DONE_INT_ST1    (BIT(14))
+#define SDIO_SLC0_TX_DONE_INT_ST1_M  (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S)
+#define SDIO_SLC0_TX_DONE_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TX_DONE_INT_ST1_S  14
+/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST1    (BIT(15))
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M  (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S)
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S  15
+/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DONE_INT_ST1    (BIT(16))
+#define SDIO_SLC0_RX_DONE_INT_ST1_M  (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S)
+#define SDIO_SLC0_RX_DONE_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_RX_DONE_INT_ST1_S  16
+/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_EOF_INT_ST1    (BIT(17))
+#define SDIO_SLC0_RX_EOF_INT_ST1_M  (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S)
+#define SDIO_SLC0_RX_EOF_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_RX_EOF_INT_ST1_S  17
+/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOHOST_INT_ST1    (BIT(18))
+#define SDIO_SLC0_TOHOST_INT_ST1_M  (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S)
+#define SDIO_SLC0_TOHOST_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TOHOST_INT_ST1_S  18
+/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1    (BIT(19))
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S)
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S  19
+/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1    (BIT(20))
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S)
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S  20
+/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S)
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
+/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST1    (BIT(22))
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M  (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S)
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S  22
+/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1    (BIT(23))
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S)
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S  23
+/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST1    (BIT(24))
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M  (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S)
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S  24
+/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_DTC_INT_ST1    (BIT(25))
+#define SDIO_CMD_DTC_INT_ST1_M  (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S)
+#define SDIO_CMD_DTC_INT_ST1_V  0x00000001U
+#define SDIO_CMD_DTC_INT_ST1_S  25
+/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1    (BIT(26))
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S)
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S  26
+/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1    (BIT(27))
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S)
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V  0x00000001U
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S  27
+/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_HDA_RECV_DONE_INT_ST1    (BIT(28))
+#define SDIO_HDA_RECV_DONE_INT_ST1_M  (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S)
+#define SDIO_HDA_RECV_DONE_INT_ST1_V  0x00000001U
+#define SDIO_HDA_RECV_DONE_INT_ST1_S  28
+
+/** SDIO_SLC0INT_ENA1_REG register
+ *  reserved
+ */
+#define SDIO_SLC0INT_ENA1_REG (DR_REG_SLC_BASE + 0x148)
+/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA1    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S  0
+/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA1    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S  1
+/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA1    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S  2
+/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA1    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S  3
+/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA1    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S  4
+/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA1    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S  5
+/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA1    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S  6
+/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA1    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S  7
+/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_START_INT_ENA1    (BIT(8))
+#define SDIO_SLC0_RX_START_INT_ENA1_M  (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S)
+#define SDIO_SLC0_RX_START_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_RX_START_INT_ENA1_S  8
+/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_START_INT_ENA1    (BIT(9))
+#define SDIO_SLC0_TX_START_INT_ENA1_M  (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S)
+#define SDIO_SLC0_TX_START_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TX_START_INT_ENA1_S  9
+/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_UDF_INT_ENA1    (BIT(10))
+#define SDIO_SLC0_RX_UDF_INT_ENA1_M  (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S)
+#define SDIO_SLC0_RX_UDF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_RX_UDF_INT_ENA1_S  10
+/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_OVF_INT_ENA1    (BIT(11))
+#define SDIO_SLC0_TX_OVF_INT_ENA1_M  (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S)
+#define SDIO_SLC0_TX_OVF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TX_OVF_INT_ENA1_S  11
+/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(12))
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S)
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
+/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(13))
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S)
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
+/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DONE_INT_ENA1    (BIT(14))
+#define SDIO_SLC0_TX_DONE_INT_ENA1_M  (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S)
+#define SDIO_SLC0_TX_DONE_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TX_DONE_INT_ENA1_S  14
+/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1    (BIT(15))
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M  (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S)
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S  15
+/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DONE_INT_ENA1    (BIT(16))
+#define SDIO_SLC0_RX_DONE_INT_ENA1_M  (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S)
+#define SDIO_SLC0_RX_DONE_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_RX_DONE_INT_ENA1_S  16
+/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_EOF_INT_ENA1    (BIT(17))
+#define SDIO_SLC0_RX_EOF_INT_ENA1_M  (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S)
+#define SDIO_SLC0_RX_EOF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_RX_EOF_INT_ENA1_S  17
+/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TOHOST_INT_ENA1    (BIT(18))
+#define SDIO_SLC0_TOHOST_INT_ENA1_M  (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S)
+#define SDIO_SLC0_TOHOST_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TOHOST_INT_ENA1_S  18
+/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1    (BIT(19))
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S)
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
+/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1    (BIT(20))
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S)
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
+/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S)
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
+/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1    (BIT(22))
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M  (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S)
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S  22
+/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1    (BIT(23))
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S)
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
+/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1    (BIT(24))
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M  (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S)
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S  24
+/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define SDIO_CMD_DTC_INT_ENA1    (BIT(25))
+#define SDIO_CMD_DTC_INT_ENA1_M  (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S)
+#define SDIO_CMD_DTC_INT_ENA1_V  0x00000001U
+#define SDIO_CMD_DTC_INT_ENA1_S  25
+/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1    (BIT(26))
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S)
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
+/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1    (BIT(27))
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S)
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V  0x00000001U
+#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S  27
+/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define SDIO_HDA_RECV_DONE_INT_ENA1    (BIT(28))
+#define SDIO_HDA_RECV_DONE_INT_ENA1_M  (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S)
+#define SDIO_HDA_RECV_DONE_INT_ENA1_V  0x00000001U
+#define SDIO_HDA_RECV_DONE_INT_ENA1_S  28
+
+/** SDIO_SLC1INT_ST1_REG register
+ *  reserved
+ */
+#define SDIO_SLC1INT_ST1_REG (DR_REG_SLC_BASE + 0x14c)
+/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT8_INT_ST1    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M  (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S  0
+/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT9_INT_ST1    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M  (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S  1
+/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT10_INT_ST1    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M  (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S  2
+/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT11_INT_ST1    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M  (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S  3
+/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT12_INT_ST1    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M  (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S  4
+/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT13_INT_ST1    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M  (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S  5
+/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT14_INT_ST1    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M  (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S  6
+/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT15_INT_ST1    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M  (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S)
+#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S  7
+/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_START_INT_ST1    (BIT(8))
+#define SDIO_SLC1_RX_START_INT_ST1_M  (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S)
+#define SDIO_SLC1_RX_START_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_RX_START_INT_ST1_S  8
+/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_START_INT_ST1    (BIT(9))
+#define SDIO_SLC1_TX_START_INT_ST1_M  (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S)
+#define SDIO_SLC1_TX_START_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TX_START_INT_ST1_S  9
+/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_UDF_INT_ST1    (BIT(10))
+#define SDIO_SLC1_RX_UDF_INT_ST1_M  (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S)
+#define SDIO_SLC1_RX_UDF_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_RX_UDF_INT_ST1_S  10
+/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_OVF_INT_ST1    (BIT(11))
+#define SDIO_SLC1_TX_OVF_INT_ST1_M  (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S)
+#define SDIO_SLC1_TX_OVF_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TX_OVF_INT_ST1_S  11
+/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1    (BIT(12))
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S)
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S  12
+/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1    (BIT(13))
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S)
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S  13
+/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DONE_INT_ST1    (BIT(14))
+#define SDIO_SLC1_TX_DONE_INT_ST1_M  (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S)
+#define SDIO_SLC1_TX_DONE_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TX_DONE_INT_ST1_S  14
+/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST1    (BIT(15))
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M  (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S)
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S  15
+/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DONE_INT_ST1    (BIT(16))
+#define SDIO_SLC1_RX_DONE_INT_ST1_M  (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S)
+#define SDIO_SLC1_RX_DONE_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_RX_DONE_INT_ST1_S  16
+/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_EOF_INT_ST1    (BIT(17))
+#define SDIO_SLC1_RX_EOF_INT_ST1_M  (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S)
+#define SDIO_SLC1_RX_EOF_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_RX_EOF_INT_ST1_S  17
+/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOHOST_INT_ST1    (BIT(18))
+#define SDIO_SLC1_TOHOST_INT_ST1_M  (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S)
+#define SDIO_SLC1_TOHOST_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TOHOST_INT_ST1_S  18
+/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1    (BIT(19))
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S)
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S  19
+/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1    (BIT(20))
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S)
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S  20
+/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S)
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S  21
+/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST1    (BIT(22))
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M  (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S)
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S  22
+/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1    (BIT(23))
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S)
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S  23
+/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST1    (BIT(24))
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M  (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S)
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V  0x00000001U
+#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S  24
+
+/** SDIO_SLC1INT_ENA1_REG register
+ *  reserved
+ */
+#define SDIO_SLC1INT_ENA1_REG (DR_REG_SLC_BASE + 0x150)
+/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA1    (BIT(0))
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S  0
+/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA1    (BIT(1))
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S  1
+/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA1    (BIT(2))
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S  2
+/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA1    (BIT(3))
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S  3
+/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA1    (BIT(4))
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S  4
+/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA1    (BIT(5))
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S  5
+/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA1    (BIT(6))
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S  6
+/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA1    (BIT(7))
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S)
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V  0x00000001U
+#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S  7
+/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_START_INT_ENA1    (BIT(8))
+#define SDIO_SLC1_RX_START_INT_ENA1_M  (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S)
+#define SDIO_SLC1_RX_START_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_RX_START_INT_ENA1_S  8
+/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_START_INT_ENA1    (BIT(9))
+#define SDIO_SLC1_TX_START_INT_ENA1_M  (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S)
+#define SDIO_SLC1_TX_START_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TX_START_INT_ENA1_S  9
+/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_UDF_INT_ENA1    (BIT(10))
+#define SDIO_SLC1_RX_UDF_INT_ENA1_M  (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S)
+#define SDIO_SLC1_RX_UDF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_RX_UDF_INT_ENA1_S  10
+/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_OVF_INT_ENA1    (BIT(11))
+#define SDIO_SLC1_TX_OVF_INT_ENA1_M  (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S)
+#define SDIO_SLC1_TX_OVF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TX_OVF_INT_ENA1_S  11
+/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1    (BIT(12))
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S)
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S  12
+/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1    (BIT(13))
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S)
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S  13
+/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DONE_INT_ENA1    (BIT(14))
+#define SDIO_SLC1_TX_DONE_INT_ENA1_M  (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S)
+#define SDIO_SLC1_TX_DONE_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TX_DONE_INT_ENA1_S  14
+/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1    (BIT(15))
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M  (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S)
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S  15
+/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DONE_INT_ENA1    (BIT(16))
+#define SDIO_SLC1_RX_DONE_INT_ENA1_M  (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S)
+#define SDIO_SLC1_RX_DONE_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_RX_DONE_INT_ENA1_S  16
+/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_EOF_INT_ENA1    (BIT(17))
+#define SDIO_SLC1_RX_EOF_INT_ENA1_M  (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S)
+#define SDIO_SLC1_RX_EOF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_RX_EOF_INT_ENA1_S  17
+/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TOHOST_INT_ENA1    (BIT(18))
+#define SDIO_SLC1_TOHOST_INT_ENA1_M  (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S)
+#define SDIO_SLC1_TOHOST_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TOHOST_INT_ENA1_S  18
+/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1    (BIT(19))
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S)
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S  19
+/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1    (BIT(20))
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S)
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S  20
+/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S)
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S  21
+/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1    (BIT(22))
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M  (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S)
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S  22
+/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1    (BIT(23))
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S)
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S  23
+/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1    (BIT(24))
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M  (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S)
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V  0x00000001U
+#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S  24
+
+/** SDIO_SLC0_TX_SHAREMEM_START_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x154)
+/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S)
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S  0
+
+/** SDIO_SLC0_TX_SHAREMEM_END_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x158)
+/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S)
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S  0
+
+/** SDIO_SLC0_RX_SHAREMEM_START_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x15c)
+/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S)
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S  0
+
+/** SDIO_SLC0_RX_SHAREMEM_END_REG register
+ *  reserved
+ */
+#define SDIO_SLC0_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x160)
+/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S)
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S  0
+
+/** SDIO_SLC1_TX_SHAREMEM_START_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x164)
+/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S)
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S  0
+
+/** SDIO_SLC1_TX_SHAREMEM_END_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x168)
+/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S)
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S  0
+
+/** SDIO_SLC1_RX_SHAREMEM_START_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x16c)
+/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S)
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S  0
+
+/** SDIO_SLC1_RX_SHAREMEM_END_REG register
+ *  reserved
+ */
+#define SDIO_SLC1_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x170)
+/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S)
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S  0
+
+/** SDIO_HDA_TX_SHAREMEM_START_REG register
+ *  reserved
+ */
+#define SDIO_HDA_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x174)
+/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S)
+#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S  0
+
+/** SDIO_HDA_RX_SHAREMEM_START_REG register
+ *  reserved
+ */
+#define SDIO_HDA_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x178)
+/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
+#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S)
+#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
+#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S  0
+
+/** SDIO_SLC_BURST_LEN_REG register
+ *  reserved
+ */
+#define SDIO_SLC_BURST_LEN_REG (DR_REG_SLC_BASE + 0x17c)
+/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1;
+ *  0-incr4,1-incr8
+ */
+#define SDIO_SLC0_TXDATA_BURST_LEN    (BIT(0))
+#define SDIO_SLC0_TXDATA_BURST_LEN_M  (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S)
+#define SDIO_SLC0_TXDATA_BURST_LEN_V  0x00000001U
+#define SDIO_SLC0_TXDATA_BURST_LEN_S  0
+/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1;
+ *  0-incr4,1-incr8
+ */
+#define SDIO_SLC0_RXDATA_BURST_LEN    (BIT(1))
+#define SDIO_SLC0_RXDATA_BURST_LEN_M  (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S)
+#define SDIO_SLC0_RXDATA_BURST_LEN_V  0x00000001U
+#define SDIO_SLC0_RXDATA_BURST_LEN_S  1
+/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1;
+ *  0-incr4,1-incr8
+ */
+#define SDIO_SLC1_TXDATA_BURST_LEN    (BIT(2))
+#define SDIO_SLC1_TXDATA_BURST_LEN_M  (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S)
+#define SDIO_SLC1_TXDATA_BURST_LEN_V  0x00000001U
+#define SDIO_SLC1_TXDATA_BURST_LEN_S  2
+/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1;
+ *  0-incr4,1-incr8
+ */
+#define SDIO_SLC1_RXDATA_BURST_LEN    (BIT(3))
+#define SDIO_SLC1_RXDATA_BURST_LEN_M  (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S)
+#define SDIO_SLC1_RXDATA_BURST_LEN_V  0x00000001U
+#define SDIO_SLC1_RXDATA_BURST_LEN_S  3
+
+/** SDIO_SLCDATE_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLCDATE_REG (DR_REG_SLC_BASE + 0x1f8)
+/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400;
+ *  reserved
+ */
+#define SDIO_SLC_DATE    0xFFFFFFFFU
+#define SDIO_SLC_DATE_M  (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S)
+#define SDIO_SLC_DATE_V  0xFFFFFFFFU
+#define SDIO_SLC_DATE_S  0
+
+/** SDIO_SLCID_REG register
+ *  ******* Description ***********
+ */
+#define SDIO_SLCID_REG (DR_REG_SLC_BASE + 0x1fc)
+/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256;
+ *  reserved
+ */
+#define SDIO_SLC_ID    0xFFFFFFFFU
+#define SDIO_SLC_ID_M  (SDIO_SLC_ID_V << SDIO_SLC_ID_S)
+#define SDIO_SLC_ID_V  0xFFFFFFFFU
+#define SDIO_SLC_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/slc_struct.h b/components/soc/esp32p4/include/soc/slc_struct.h
new file mode 100644
index 0000000000..7d57757704
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/slc_struct.h
@@ -0,0 +1,3253 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration registers */
+/** Type of slcconf0 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_tx_rst : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to reset tx fsm in dma slc0.
+         */
+        uint32_t slc0_tx_rst:1;
+        /** slc0_rx_rst : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to reset rx fsm in dma slc0.
+         */
+        uint32_t slc0_rx_rst:1;
+        /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0;
+         *  reset the command fifo of AHB bus of sdio slave
+         */
+        uint32_t slc_ahbm_fifo_rst:1;
+        /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0;
+         *  reset the AHB bus of sdio slave
+         */
+        uint32_t slc_ahbm_rst:1;
+        /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0;
+         *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
+         */
+        uint32_t slc0_tx_loop_test:1;
+        /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0;
+         *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
+         */
+        uint32_t slc0_rx_loop_test:1;
+        /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0;
+         *  Set 1 to enable change the owner bit of rx link descriptor
+         */
+        uint32_t slc0_rx_auto_wrback:1;
+        /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_no_restart_clr:1;
+        /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1;
+         *  0- AHB burst type is single when slave read rx-descriptor from memory through
+         *  slc0,1-AHB burst type is not single when slave read rx-descriptor from memory
+         *  through slc0
+         */
+        uint32_t slc0_rxdscr_burst_en:1;
+        /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1;
+         *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
+         *  is not single when slave receives data from memory
+         */
+        uint32_t slc0_rxdata_burst_en:1;
+        /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1;
+         *  enable the function that when host reading packet retries, slc1 will automatically
+         *  jump to the start descriptor of the previous packet.
+         */
+        uint32_t slc0_rxlink_auto_ret:1;
+        /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1;
+         *  enable the function that when host sending packet retries, slc1 will automatically
+         *  jump to the start descriptor of the previous packet.
+         */
+        uint32_t slc0_txlink_auto_ret:1;
+        /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1;
+         *  0- AHB burst type is single when slave read tx-descriptor from memory through
+         *  slc0,1-AHB burst type is not single when slave read tx-descriptor from memory
+         *  through slc0
+         */
+        uint32_t slc0_txdscr_burst_en:1;
+        /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1;
+         *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
+         *  single when slave send data to memory
+         */
+        uint32_t slc0_txdata_burst_en:1;
+        /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1;
+         *  auto clear slc0_token1 enable
+         */
+        uint32_t slc0_token_auto_clr:1;
+        /** slc0_token_sel : R/W; bitpos: [15]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_token_sel:1;
+        /** slc1_tx_rst : R/W; bitpos: [16]; default: 0;
+         *  Set 1 to reset tx fsm in dma slc0.
+         */
+        uint32_t slc1_tx_rst:1;
+        /** slc1_rx_rst : R/W; bitpos: [17]; default: 0;
+         *  Set 1 to reset rx fsm in dma slc0.
+         */
+        uint32_t slc1_rx_rst:1;
+        /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_wr_retry_mask_en:1;
+        /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_wr_retry_mask_en:1;
+        /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1;
+         *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
+         */
+        uint32_t slc1_tx_loop_test:1;
+        /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1;
+         *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
+         */
+        uint32_t slc1_rx_loop_test:1;
+        /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0;
+         *  Set 1 to enable change the owner bit of rx link descriptor
+         */
+        uint32_t slc1_rx_auto_wrback:1;
+        /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0;
+         *  ******* Description ***********
+         */
+        uint32_t slc1_rx_no_restart_clr:1;
+        /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1;
+         *  0- AHB burst type is single when slave read rx-descriptor from memory through
+         *  slc1,1-AHB burst type is not single when slave read rx-descriptor from memory
+         *  through slc1
+         */
+        uint32_t slc1_rxdscr_burst_en:1;
+        /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1;
+         *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
+         *  is not single when slave receives data from memory
+         */
+        uint32_t slc1_rxdata_burst_en:1;
+        /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1;
+         *  enable the function that when host reading packet retries, slc1 will automatically
+         *  jump to the start descriptor of the previous packet.
+         */
+        uint32_t slc1_rxlink_auto_ret:1;
+        /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1;
+         *  enable the function that when host sending packet retries, slc1 will automatically
+         *  jump to the start descriptor of the previous packet.
+         */
+        uint32_t slc1_txlink_auto_ret:1;
+        /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1;
+         *  0- AHB burst type is single when slave read tx-descriptor from memory through
+         *  slc1,1-AHB burst type is not single when slave read tx-descriptor from memory
+         *  through slc1
+         */
+        uint32_t slc1_txdscr_burst_en:1;
+        /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1;
+         *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
+         *  single when slave send data to memory
+         */
+        uint32_t slc1_txdata_burst_en:1;
+        /** slc1_token_auto_clr : R/W; bitpos: [30]; default: 1;
+         *  auto clear slc1_token1 enable
+         */
+        uint32_t slc1_token_auto_clr:1;
+        /** slc1_token_sel : R/W; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_token_sel:1;
+    };
+    uint32_t val;
+} sdio_slcconf0_reg_t;
+
+/** Type of slc0rxfifo_push register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxfifo_wdata:9;
+        uint32_t reserved_9:7;
+        /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxfifo_push:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} sdio_slc0rxfifo_push_reg_t;
+
+/** Type of slc1rxfifo_push register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxfifo_wdata:9;
+        uint32_t reserved_9:7;
+        /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxfifo_push:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} sdio_slc1rxfifo_push_reg_t;
+
+/** Type of slc0rx_link register
+ *  reserved
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxlink_stop:1;
+        /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxlink_start:1;
+        /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxlink_restart:1;
+        /** slc0_rxlink_park : RO; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_rxlink_park:1;
+    };
+    uint32_t val;
+} sdio_slc0rx_link_reg_t;
+
+/** Type of slc0rx_link_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxlink_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0rx_link_addr_reg_t;
+
+/** Type of slc0tx_link register
+ *  reserved
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txlink_stop:1;
+        /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txlink_start:1;
+        /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txlink_restart:1;
+        /** slc0_txlink_park : RO; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_txlink_park:1;
+    };
+    uint32_t val;
+} sdio_slc0tx_link_reg_t;
+
+/** Type of slc0tx_link_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txlink_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0tx_link_addr_reg_t;
+
+/** Type of slc1rx_link register
+ *  reserved
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** slc1_bt_packet : R/W; bitpos: [20]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_bt_packet:1;
+        uint32_t reserved_21:7;
+        /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxlink_stop:1;
+        /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxlink_start:1;
+        /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxlink_restart:1;
+        /** slc1_rxlink_park : RO; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_rxlink_park:1;
+    };
+    uint32_t val;
+} sdio_slc1rx_link_reg_t;
+
+/** Type of slc1rx_link_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxlink_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1rx_link_addr_reg_t;
+
+/** Type of slc1tx_link register
+ *  reserved
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txlink_stop:1;
+        /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txlink_start:1;
+        /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txlink_restart:1;
+        /** slc1_txlink_park : RO; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_txlink_park:1;
+    };
+    uint32_t val;
+} sdio_slc1tx_link_reg_t;
+
+/** Type of slc1tx_link_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txlink_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1tx_link_addr_reg_t;
+
+/** Type of slcintvec_tohost register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tohost_intvec:8;
+        uint32_t reserved_8:8;
+        /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tohost_intvec:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} sdio_slcintvec_tohost_reg_t;
+
+/** Type of slc0token0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_wdata:12;
+        /** slc0_token0_wr : WT; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_wr:1;
+        /** slc0_token0_inc : WT; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_inc:1;
+        /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_inc_more:1;
+        uint32_t reserved_15:1;
+        /** slc0_token0 : RO; bitpos: [27:16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sdio_slc0token0_reg_t;
+
+/** Type of slc0token1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0;
+         *  slc0 token1 wdata
+         */
+        uint32_t slc0_token1_wdata:12;
+        /** slc0_token1_wr : WT; bitpos: [12]; default: 0;
+         *  update slc0_token1_wdata into slc0 token1
+         */
+        uint32_t slc0_token1_wr:1;
+        /** slc0_token1_inc : WT; bitpos: [13]; default: 0;
+         *  slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1
+         */
+        uint32_t slc0_token1_inc:1;
+        /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0;
+         *  slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add
+         *  slc0_token1_wdata to slc0_token1
+         */
+        uint32_t slc0_token1_inc_more:1;
+        uint32_t reserved_15:1;
+        /** slc0_token1 : RO; bitpos: [27:16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token1:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sdio_slc0token1_reg_t;
+
+/** Type of slc1token0 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_wdata:12;
+        /** slc1_token0_wr : WT; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_wr:1;
+        /** slc1_token0_inc : WT; bitpos: [13]; default: 0;
+         *  Add 1 to  slc1_token0
+         */
+        uint32_t slc1_token0_inc:1;
+        /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0;
+         *  Add  slc1_token0_wdata to  slc1_token0
+         */
+        uint32_t slc1_token0_inc_more:1;
+        uint32_t reserved_15:1;
+        /** slc1_token0 : RO; bitpos: [27:16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sdio_slc1token0_reg_t;
+
+/** Type of slc1token1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_wdata:12;
+        /** slc1_token1_wr : WT; bitpos: [12]; default: 0;
+         *  update slc1_token1_wdata into slc1 token1
+         */
+        uint32_t slc1_token1_wr:1;
+        /** slc1_token1_inc : WT; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_inc:1;
+        /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_inc_more:1;
+        uint32_t reserved_15:1;
+        /** slc1_token1 : RO; bitpos: [27:16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sdio_slc1token1_reg_t;
+
+/** Type of slcconf1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_check_owner : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_check_owner:1;
+        /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_check_sum_en:1;
+        /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_check_sum_en:1;
+        /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1;
+         *  reserved
+         */
+        uint32_t sdio_cmd_hold_en:1;
+        /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_len_auto_clr:1;
+        /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_tx_stitch_en:1;
+        /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_rx_stitch_en:1;
+        uint32_t reserved_7:9;
+        /** slc1_check_owner : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_check_owner:1;
+        /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_check_sum_en:1;
+        /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_check_sum_en:1;
+        /** host_int_level_sel : R/W; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t host_int_level_sel:1;
+        /** slc1_tx_stitch_en : R/W; bitpos: [20]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_tx_stitch_en:1;
+        /** slc1_rx_stitch_en : R/W; bitpos: [21]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_rx_stitch_en:1;
+        /** sdio_clk_en : R/W; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} sdio_slcconf1_reg_t;
+
+/** Type of slcbridge_conf register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32;
+         *  reserved
+         */
+        uint32_t slc_txeof_ena:6;
+        uint32_t reserved_6:2;
+        /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7;
+         *  reserved
+         */
+        uint32_t slc_fifo_map_ena:4;
+        /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_tx_dummy_mode:1;
+        /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1;
+         *  reserved
+         */
+        uint32_t slc_hda_map_128k:1;
+        /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_tx_dummy_mode:1;
+        uint32_t reserved_15:1;
+        /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10;
+         *  reserved
+         */
+        uint32_t slc_tx_push_idle_num:16;
+    };
+    uint32_t val;
+} sdio_slcbridge_conf_reg_t;
+
+/** Type of slc0_to_eof_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_to_eof_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_to_eof_des_addr_reg_t;
+
+/** Type of slc0_tx_eof_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_suc_eof_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_tx_eof_des_addr_reg_t;
+
+/** Type of slc0_to_eof_bfr_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_to_eof_bfr_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_to_eof_bfr_des_addr_reg_t;
+
+/** Type of slc1_to_eof_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_to_eof_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_to_eof_des_addr_reg_t;
+
+/** Type of slc1_tx_eof_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_suc_eof_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_tx_eof_des_addr_reg_t;
+
+/** Type of slc1_to_eof_bfr_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_to_eof_bfr_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_to_eof_bfr_des_addr_reg_t;
+
+/** Type of slc_rx_dscr_conf register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token_no_replace:1;
+        /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_infor_no_replace:1;
+        /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0;
+         *  slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next
+         *  pop doesn't occur after 255 cycles since the current pop
+         */
+        uint32_t slc0_rx_fill_mode:1;
+        /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1;
+         *  0-slc0 rx_push_eof, 1-slc0 rx_pop_eof
+         */
+        uint32_t slc0_rx_eof_mode:1;
+        /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_rx_fill_en:1;
+        /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128;
+         *  reserved
+         */
+        uint32_t slc0_rd_retry_threshold:11;
+        /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_token_no_replace:1;
+        /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_infor_no_replace:1;
+        /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0;
+         *  slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next
+         *  pop doesn't occur after 255 cycles since the current pop
+         */
+        uint32_t slc1_rx_fill_mode:1;
+        /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1;
+         *  0-slc1 rx_push_eof, 1-slc1 rx_pop_eof
+         */
+        uint32_t slc1_rx_eof_mode:1;
+        /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_rx_fill_en:1;
+        /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128;
+         *  reserved
+         */
+        uint32_t slc1_rd_retry_threshold:11;
+    };
+    uint32_t val;
+} sdio_slc_rx_dscr_conf_reg_t;
+
+/** Type of slc_tx_dscr_conf register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128;
+         *  reserved
+         */
+        uint32_t slc_wr_retry_threshold:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} sdio_slc_tx_dscr_conf_reg_t;
+
+/** Type of slc0_len_conf register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_len_wdata:20;
+        /** slc0_len_wr : WT; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_len_wr:1;
+        /** slc0_len_inc : WT; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_len_inc:1;
+        /** slc0_len_inc_more : WT; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_len_inc_more:1;
+        /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_packet_load_en:1;
+        /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_packet_load_en:1;
+        /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_get_used_dscr:1;
+        /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_get_used_dscr:1;
+        /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_new_pkt_ind:1;
+        /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_tx_new_pkt_ind:1;
+        /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_packet_load_en_st:1;
+        /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_packet_load_en_st:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} sdio_slc0_len_conf_reg_t;
+
+/** Type of slc0_txpkt_h_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_pkt_h_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_txpkt_h_dscr_reg_t;
+
+/** Type of slc0_txpkt_e_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_pkt_e_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_txpkt_e_dscr_reg_t;
+
+/** Type of slc0_rxpkt_h_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_pkt_h_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_rxpkt_h_dscr_reg_t;
+
+/** Type of slc0_rxpkt_e_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_pkt_e_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_rxpkt_e_dscr_reg_t;
+
+/** Type of slc0_txpktu_h_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_pkt_start_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_txpktu_h_dscr_reg_t;
+
+/** Type of slc0_txpktu_e_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_pkt_end_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_txpktu_e_dscr_reg_t;
+
+/** Type of slc0_rxpktu_h_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_pkt_start_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_rxpktu_h_dscr_reg_t;
+
+/** Type of slc0_rxpktu_e_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_pkt_end_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_rxpktu_e_dscr_reg_t;
+
+/** Type of slc_seq_position register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9;
+         *  reserved
+         */
+        uint32_t slc0_seq_position:8;
+        /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5;
+         *  reserved
+         */
+        uint32_t slc1_seq_position:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} sdio_slc_seq_position_reg_t;
+
+/** Type of slc0_dscr_rec_conf register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023;
+         *  reserved
+         */
+        uint32_t slc0_rx_dscr_rec_lim:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} sdio_slc0_dscr_rec_conf_reg_t;
+
+/** Type of slc_sdio_crc_st1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_crc_err_cnt:8;
+        uint32_t reserved_8:23;
+        /** err_cnt_clr : R/W; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t err_cnt_clr:1;
+    };
+    uint32_t val;
+} sdio_slc_sdio_crc_st1_reg_t;
+
+/** Type of slc0_len_lim_conf register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504;
+         *  reserved
+         */
+        uint32_t slc0_len_lim:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sdio_slc0_len_lim_conf_reg_t;
+
+/** Type of slc0_tx_sharemem_start register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_slc0_tx_sharemem_start_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_tx_sharemem_start_reg_t;
+
+/** Type of slc0_tx_sharemem_end register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t sdio_slc0_tx_sharemem_end_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_tx_sharemem_end_reg_t;
+
+/** Type of slc0_rx_sharemem_start register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_slc0_rx_sharemem_start_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_rx_sharemem_start_reg_t;
+
+/** Type of slc0_rx_sharemem_end register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t sdio_slc0_rx_sharemem_end_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_rx_sharemem_end_reg_t;
+
+/** Type of slc1_tx_sharemem_start register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_slc1_tx_sharemem_start_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_tx_sharemem_start_reg_t;
+
+/** Type of slc1_tx_sharemem_end register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t sdio_slc1_tx_sharemem_end_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_tx_sharemem_end_reg_t;
+
+/** Type of slc1_rx_sharemem_start register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_slc1_rx_sharemem_start_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_rx_sharemem_start_reg_t;
+
+/** Type of slc1_rx_sharemem_end register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t sdio_slc1_rx_sharemem_end_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_rx_sharemem_end_reg_t;
+
+/** Type of hda_tx_sharemem_start register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_hda_tx_sharemem_start_addr:32;
+    };
+    uint32_t val;
+} sdio_hda_tx_sharemem_start_reg_t;
+
+/** Type of hda_rx_sharemem_start register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_hda_rx_sharemem_start_addr:32;
+    };
+    uint32_t val;
+} sdio_hda_rx_sharemem_start_reg_t;
+
+/** Type of slc_burst_len register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1;
+         *  0-incr4,1-incr8
+         */
+        uint32_t slc0_txdata_burst_len:1;
+        /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1;
+         *  0-incr4,1-incr8
+         */
+        uint32_t slc0_rxdata_burst_len:1;
+        /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1;
+         *  0-incr4,1-incr8
+         */
+        uint32_t slc1_txdata_burst_len:1;
+        /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1;
+         *  0-incr4,1-incr8
+         */
+        uint32_t slc1_rxdata_burst_len:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sdio_slc_burst_len_reg_t;
+
+/** Type of slcid register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc_id : R/W; bitpos: [31:0]; default: 256;
+         *  reserved
+         */
+        uint32_t slc_id:32;
+    };
+    uint32_t val;
+} sdio_slcid_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of slc0int_raw register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit0_int_raw:1;
+        /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit1_int_raw:1;
+        /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit2_int_raw:1;
+        /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit3_int_raw:1;
+        /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit4_int_raw:1;
+        /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit5_int_raw:1;
+        /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit6_int_raw:1;
+        /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit7_int_raw:1;
+        /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_start_int_raw:1;
+        /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_start_int_raw:1;
+        /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_udf_int_raw:1;
+        /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_ovf_int_raw:1;
+        /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_1to0_int_raw:1;
+        /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token1_1to0_int_raw:1;
+        /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt bit of slc0 finishing receiving data to one buffer
+         */
+        uint32_t slc0_tx_done_int_raw:1;
+        /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt bit of slc0 finishing receiving data
+         */
+        uint32_t slc0_tx_suc_eof_int_raw:1;
+        /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw interrupt bit of slc0 finishing sending data from one buffer
+         */
+        uint32_t slc0_rx_done_int_raw:1;
+        /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw interrupt bit of slc0 finishing sending data
+         */
+        uint32_t slc0_rx_eof_int_raw:1;
+        /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tohost_int_raw:1;
+        /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw interrupt bit of slc0 tx link descriptor error
+         */
+        uint32_t slc0_tx_dscr_err_int_raw:1;
+        /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw interrupt bit of slc0 rx link descriptor error
+         */
+        uint32_t slc0_rx_dscr_err_int_raw:1;
+        /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_empty_int_raw:1;
+        /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_rd_ack_int_raw:1;
+        /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_wr_retry_done_int_raw:1;
+        /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_err_eof_int_raw:1;
+        /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_dtc_int_raw:1;
+        /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_quick_eof_int_raw:1;
+        /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_pop_eof_err_int_raw:1;
+        /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t hda_recv_done_int_raw:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sdio_slc0int_raw_reg_t;
+
+/** Type of slc0int_st register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit0_int_st:1;
+        /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit1_int_st:1;
+        /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit2_int_st:1;
+        /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit3_int_st:1;
+        /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit4_int_st:1;
+        /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit5_int_st:1;
+        /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit6_int_st:1;
+        /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit7_int_st:1;
+        /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_start_int_st:1;
+        /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_start_int_st:1;
+        /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_udf_int_st:1;
+        /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_ovf_int_st:1;
+        /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_1to0_int_st:1;
+        /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token1_1to0_int_st:1;
+        /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_done_int_st:1;
+        /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_suc_eof_int_st:1;
+        /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_done_int_st:1;
+        /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_eof_int_st:1;
+        /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tohost_int_st:1;
+        /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_err_int_st:1;
+        /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_dscr_err_int_st:1;
+        /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_empty_int_st:1;
+        /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_rd_ack_int_st:1;
+        /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_wr_retry_done_int_st:1;
+        /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_err_eof_int_st:1;
+        /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_dtc_int_st:1;
+        /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_quick_eof_int_st:1;
+        /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_pop_eof_err_int_st:1;
+        /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t hda_recv_done_int_st:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sdio_slc0int_st_reg_t;
+
+/** Type of slc0int_ena register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit0_int_ena:1;
+        /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit1_int_ena:1;
+        /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit2_int_ena:1;
+        /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit3_int_ena:1;
+        /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit4_int_ena:1;
+        /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit5_int_ena:1;
+        /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit6_int_ena:1;
+        /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit7_int_ena:1;
+        /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_start_int_ena:1;
+        /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_start_int_ena:1;
+        /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_udf_int_ena:1;
+        /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_ovf_int_ena:1;
+        /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_1to0_int_ena:1;
+        /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token1_1to0_int_ena:1;
+        /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_done_int_ena:1;
+        /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_suc_eof_int_ena:1;
+        /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_done_int_ena:1;
+        /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_eof_int_ena:1;
+        /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tohost_int_ena:1;
+        /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_err_int_ena:1;
+        /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_dscr_err_int_ena:1;
+        /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_empty_int_ena:1;
+        /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_rd_ack_int_ena:1;
+        /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_wr_retry_done_int_ena:1;
+        /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_err_eof_int_ena:1;
+        /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_dtc_int_ena:1;
+        /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_quick_eof_int_ena:1;
+        /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_pop_eof_err_int_ena:1;
+        /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t hda_recv_done_int_ena:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sdio_slc0int_ena_reg_t;
+
+/** Type of slc0int_clr register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit0_int_clr:1;
+        /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit1_int_clr:1;
+        /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit2_int_clr:1;
+        /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit3_int_clr:1;
+        /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit4_int_clr:1;
+        /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit5_int_clr:1;
+        /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit6_int_clr:1;
+        /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit7_int_clr:1;
+        /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_start_int_clr:1;
+        /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_start_int_clr:1;
+        /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_udf_int_clr:1;
+        /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_ovf_int_clr:1;
+        /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_1to0_int_clr:1;
+        /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token1_1to0_int_clr:1;
+        /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_done_int_clr:1;
+        /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_suc_eof_int_clr:1;
+        /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_done_int_clr:1;
+        /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_eof_int_clr:1;
+        /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tohost_int_clr:1;
+        /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_err_int_clr:1;
+        /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_dscr_err_int_clr:1;
+        /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_empty_int_clr:1;
+        /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_rd_ack_int_clr:1;
+        /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_wr_retry_done_int_clr:1;
+        /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_err_eof_int_clr:1;
+        /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_dtc_int_clr:1;
+        /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_quick_eof_int_clr:1;
+        /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_pop_eof_err_int_clr:1;
+        /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t hda_recv_done_int_clr:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sdio_slc0int_clr_reg_t;
+
+/** Type of slc1int_raw register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit8_int_raw:1;
+        /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit9_int_raw:1;
+        /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit10_int_raw:1;
+        /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit11_int_raw:1;
+        /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit12_int_raw:1;
+        /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit13_int_raw:1;
+        /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit14_int_raw:1;
+        /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit15_int_raw:1;
+        /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_start_int_raw:1;
+        /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_start_int_raw:1;
+        /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_udf_int_raw:1;
+        /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_ovf_int_raw:1;
+        /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_1to0_int_raw:1;
+        /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_1to0_int_raw:1;
+        /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_done_int_raw:1;
+        /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_suc_eof_int_raw:1;
+        /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_done_int_raw:1;
+        /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_eof_int_raw:1;
+        /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tohost_int_raw:1;
+        /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_err_int_raw:1;
+        /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_dscr_err_int_raw:1;
+        /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_empty_int_raw:1;
+        /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_host_rd_ack_int_raw:1;
+        /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_wr_retry_done_int_raw:1;
+        /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_err_eof_int_raw:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdio_slc1int_raw_reg_t;
+
+/** Type of slc1int_st register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit8_int_st:1;
+        /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit9_int_st:1;
+        /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit10_int_st:1;
+        /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit11_int_st:1;
+        /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit12_int_st:1;
+        /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit13_int_st:1;
+        /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit14_int_st:1;
+        /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit15_int_st:1;
+        /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_start_int_st:1;
+        /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_start_int_st:1;
+        /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_udf_int_st:1;
+        /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_ovf_int_st:1;
+        /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_1to0_int_st:1;
+        /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_1to0_int_st:1;
+        /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_done_int_st:1;
+        /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_suc_eof_int_st:1;
+        /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_done_int_st:1;
+        /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_eof_int_st:1;
+        /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tohost_int_st:1;
+        /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_err_int_st:1;
+        /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_dscr_err_int_st:1;
+        /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_empty_int_st:1;
+        /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_host_rd_ack_int_st:1;
+        /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_wr_retry_done_int_st:1;
+        /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_err_eof_int_st:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdio_slc1int_st_reg_t;
+
+/** Type of slc1int_ena register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit8_int_ena:1;
+        /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit9_int_ena:1;
+        /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit10_int_ena:1;
+        /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit11_int_ena:1;
+        /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit12_int_ena:1;
+        /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit13_int_ena:1;
+        /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit14_int_ena:1;
+        /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit15_int_ena:1;
+        /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_start_int_ena:1;
+        /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_start_int_ena:1;
+        /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_udf_int_ena:1;
+        /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_ovf_int_ena:1;
+        /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_1to0_int_ena:1;
+        /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_1to0_int_ena:1;
+        /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_done_int_ena:1;
+        /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_suc_eof_int_ena:1;
+        /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_done_int_ena:1;
+        /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_eof_int_ena:1;
+        /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tohost_int_ena:1;
+        /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_err_int_ena:1;
+        /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_dscr_err_int_ena:1;
+        /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_empty_int_ena:1;
+        /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_host_rd_ack_int_ena:1;
+        /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_wr_retry_done_int_ena:1;
+        /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_err_eof_int_ena:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdio_slc1int_ena_reg_t;
+
+/** Type of slc1int_clr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit8_int_clr:1;
+        /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit9_int_clr:1;
+        /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit10_int_clr:1;
+        /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit11_int_clr:1;
+        /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit12_int_clr:1;
+        /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit13_int_clr:1;
+        /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit14_int_clr:1;
+        /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit15_int_clr:1;
+        /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_start_int_clr:1;
+        /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_start_int_clr:1;
+        /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_udf_int_clr:1;
+        /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_ovf_int_clr:1;
+        /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_1to0_int_clr:1;
+        /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_1to0_int_clr:1;
+        /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_done_int_clr:1;
+        /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_suc_eof_int_clr:1;
+        /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_done_int_clr:1;
+        /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_eof_int_clr:1;
+        /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tohost_int_clr:1;
+        /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_err_int_clr:1;
+        /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_dscr_err_int_clr:1;
+        /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_empty_int_clr:1;
+        /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_host_rd_ack_int_clr:1;
+        /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_wr_retry_done_int_clr:1;
+        /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_err_eof_int_clr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdio_slc1int_clr_reg_t;
+
+/** Type of slc0int_st1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit0_int_st1:1;
+        /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit1_int_st1:1;
+        /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit2_int_st1:1;
+        /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit3_int_st1:1;
+        /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit4_int_st1:1;
+        /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit5_int_st1:1;
+        /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit6_int_st1:1;
+        /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit7_int_st1:1;
+        /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_start_int_st1:1;
+        /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_start_int_st1:1;
+        /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_udf_int_st1:1;
+        /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_ovf_int_st1:1;
+        /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_1to0_int_st1:1;
+        /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token1_1to0_int_st1:1;
+        /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_done_int_st1:1;
+        /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_suc_eof_int_st1:1;
+        /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_done_int_st1:1;
+        /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_eof_int_st1:1;
+        /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tohost_int_st1:1;
+        /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_err_int_st1:1;
+        /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_dscr_err_int_st1:1;
+        /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_empty_int_st1:1;
+        /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_rd_ack_int_st1:1;
+        /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_wr_retry_done_int_st1:1;
+        /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_err_eof_int_st1:1;
+        /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_dtc_int_st1:1;
+        /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_quick_eof_int_st1:1;
+        /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_pop_eof_err_int_st1:1;
+        /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t hda_recv_done_int_st1:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sdio_slc0int_st1_reg_t;
+
+/** Type of slc0int_ena1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit0_int_ena1:1;
+        /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit1_int_ena1:1;
+        /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit2_int_ena1:1;
+        /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit3_int_ena1:1;
+        /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit4_int_ena1:1;
+        /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit5_int_ena1:1;
+        /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit6_int_ena1:1;
+        /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit7_int_ena1:1;
+        /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_start_int_ena1:1;
+        /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_start_int_ena1:1;
+        /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_udf_int_ena1:1;
+        /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_ovf_int_ena1:1;
+        /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token0_1to0_int_ena1:1;
+        /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token1_1to0_int_ena1:1;
+        /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_done_int_ena1:1;
+        /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_suc_eof_int_ena1:1;
+        /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_done_int_ena1:1;
+        /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_eof_int_ena1:1;
+        /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tohost_int_ena1:1;
+        /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_err_int_ena1:1;
+        /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_dscr_err_int_ena1:1;
+        /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_dscr_empty_int_ena1:1;
+        /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_rd_ack_int_ena1:1;
+        /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_wr_retry_done_int_ena1:1;
+        /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_err_eof_int_ena1:1;
+        /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_dtc_int_ena1:1;
+        /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_quick_eof_int_ena1:1;
+        /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_host_pop_eof_err_int_ena1:1;
+        /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t hda_recv_done_int_ena1:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sdio_slc0int_ena1_reg_t;
+
+/** Type of slc1int_st1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit8_int_st1:1;
+        /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit9_int_st1:1;
+        /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit10_int_st1:1;
+        /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit11_int_st1:1;
+        /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit12_int_st1:1;
+        /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit13_int_st1:1;
+        /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit14_int_st1:1;
+        /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit15_int_st1:1;
+        /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_start_int_st1:1;
+        /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_start_int_st1:1;
+        /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_udf_int_st1:1;
+        /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_ovf_int_st1:1;
+        /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_1to0_int_st1:1;
+        /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_1to0_int_st1:1;
+        /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_done_int_st1:1;
+        /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_suc_eof_int_st1:1;
+        /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_done_int_st1:1;
+        /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_eof_int_st1:1;
+        /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tohost_int_st1:1;
+        /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_err_int_st1:1;
+        /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_dscr_err_int_st1:1;
+        /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_empty_int_st1:1;
+        /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_host_rd_ack_int_st1:1;
+        /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_wr_retry_done_int_st1:1;
+        /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_err_eof_int_st1:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdio_slc1int_st1_reg_t;
+
+/** Type of slc1int_ena1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit8_int_ena1:1;
+        /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit9_int_ena1:1;
+        /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit10_int_ena1:1;
+        /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit11_int_ena1:1;
+        /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit12_int_ena1:1;
+        /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit13_int_ena1:1;
+        /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit14_int_ena1:1;
+        /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_frhost_bit15_int_ena1:1;
+        /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_start_int_ena1:1;
+        /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_start_int_ena1:1;
+        /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_udf_int_ena1:1;
+        /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_ovf_int_ena1:1;
+        /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token0_1to0_int_ena1:1;
+        /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token1_1to0_int_ena1:1;
+        /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_done_int_ena1:1;
+        /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_suc_eof_int_ena1:1;
+        /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_done_int_ena1:1;
+        /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_eof_int_ena1:1;
+        /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tohost_int_ena1:1;
+        /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_err_int_ena1:1;
+        /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_dscr_err_int_ena1:1;
+        /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_dscr_empty_int_ena1:1;
+        /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_host_rd_ack_int_ena1:1;
+        /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_wr_retry_done_int_ena1:1;
+        /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_err_eof_int_ena1:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdio_slc1int_ena1_reg_t;
+
+
+/** Group: Status registers */
+/** Type of slcrx_status register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_rx_full : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_full:1;
+        /** slc0_rx_empty : RO; bitpos: [1]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_rx_empty:1;
+        /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0;
+         *  the current buffer length when slc0 reads data from rx link
+         */
+        uint32_t slc0_rx_buf_len:14;
+        /** slc1_rx_full : RO; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rx_full:1;
+        /** slc1_rx_empty : RO; bitpos: [17]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_rx_empty:1;
+        /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0;
+         *  the current buffer length when slc1 reads data from rx link
+         */
+        uint32_t slc1_rx_buf_len:14;
+    };
+    uint32_t val;
+} sdio_slcrx_status_reg_t;
+
+/** Type of slctx_status register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_tx_full : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_full:1;
+        /** slc0_tx_empty : RO; bitpos: [1]; default: 1;
+         *  reserved
+         */
+        uint32_t slc0_tx_empty:1;
+        uint32_t reserved_2:14;
+        /** slc1_tx_full : RO; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_full:1;
+        /** slc1_tx_empty : RO; bitpos: [17]; default: 1;
+         *  reserved
+         */
+        uint32_t slc1_tx_empty:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdio_slctx_status_reg_t;
+
+/** Type of slc0_state0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_state0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_state0:32;
+    };
+    uint32_t val;
+} sdio_slc0_state0_reg_t;
+
+/** Type of slc0_state1 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_state1 : RO; bitpos: [31:0]; default: 0;
+         *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
+         *  rx_link fsm state, [30:24] rx_fifo_cnt
+         */
+        uint32_t slc0_state1:32;
+    };
+    uint32_t val;
+} sdio_slc0_state1_reg_t;
+
+/** Type of slc1_state0 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc1_state0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_state0:32;
+    };
+    uint32_t val;
+} sdio_slc1_state0_reg_t;
+
+/** Type of slc1_state1 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc1_state1 : RO; bitpos: [31:0]; default: 0;
+         *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
+         *  rx_link fsm state, [30:24] rx_fifo_cnt
+         */
+        uint32_t slc1_state1:32;
+    };
+    uint32_t val;
+} sdio_slc1_state1_reg_t;
+
+/** Type of slc_sdio_st register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** cmd_st : RO; bitpos: [2:0]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_st:3;
+        uint32_t reserved_3:1;
+        /** func_st : RO; bitpos: [7:4]; default: 0;
+         *  reserved
+         */
+        uint32_t func_st:4;
+        /** sdio_wakeup : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t sdio_wakeup:1;
+        uint32_t reserved_9:3;
+        /** bus_st : RO; bitpos: [14:12]; default: 0;
+         *  reserved
+         */
+        uint32_t bus_st:3;
+        uint32_t reserved_15:1;
+        /** func1_acc_state : RO; bitpos: [20:16]; default: 0;
+         *  reserved
+         */
+        uint32_t func1_acc_state:5;
+        uint32_t reserved_21:3;
+        /** func2_acc_state : RO; bitpos: [28:24]; default: 0;
+         *  reserved
+         */
+        uint32_t func2_acc_state:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sdio_slc_sdio_st_reg_t;
+
+/** Type of slc0_txlink_dscr register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txlink_dscr:32;
+    };
+    uint32_t val;
+} sdio_slc0_txlink_dscr_reg_t;
+
+/** Type of slc0_txlink_dscr_bf0 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txlink_dscr_bf0:32;
+    };
+    uint32_t val;
+} sdio_slc0_txlink_dscr_bf0_reg_t;
+
+/** Type of slc0_txlink_dscr_bf1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txlink_dscr_bf1:32;
+    };
+    uint32_t val;
+} sdio_slc0_txlink_dscr_bf1_reg_t;
+
+/** Type of slc0_rxlink_dscr register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0;
+         *  the third word of slc0 link descriptor, or known as the next descriptor address
+         */
+        uint32_t slc0_rxlink_dscr:32;
+    };
+    uint32_t val;
+} sdio_slc0_rxlink_dscr_reg_t;
+
+/** Type of slc0_rxlink_dscr_bf0 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxlink_dscr_bf0:32;
+    };
+    uint32_t val;
+} sdio_slc0_rxlink_dscr_bf0_reg_t;
+
+/** Type of slc0_rxlink_dscr_bf1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rxlink_dscr_bf1:32;
+    };
+    uint32_t val;
+} sdio_slc0_rxlink_dscr_bf1_reg_t;
+
+/** Type of slc1_txlink_dscr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txlink_dscr:32;
+    };
+    uint32_t val;
+} sdio_slc1_txlink_dscr_reg_t;
+
+/** Type of slc1_txlink_dscr_bf0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txlink_dscr_bf0:32;
+    };
+    uint32_t val;
+} sdio_slc1_txlink_dscr_bf0_reg_t;
+
+/** Type of slc1_txlink_dscr_bf1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txlink_dscr_bf1:32;
+    };
+    uint32_t val;
+} sdio_slc1_txlink_dscr_bf1_reg_t;
+
+/** Type of slc1_rxlink_dscr register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0;
+         *  the third word of slc1 link descriptor, or known as the next descriptor address
+         */
+        uint32_t slc1_rxlink_dscr:32;
+    };
+    uint32_t val;
+} sdio_slc1_rxlink_dscr_reg_t;
+
+/** Type of slc1_rxlink_dscr_bf0 register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxlink_dscr_bf0:32;
+    };
+    uint32_t val;
+} sdio_slc1_rxlink_dscr_bf0_reg_t;
+
+/** Type of slc1_rxlink_dscr_bf1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_rxlink_dscr_bf1:32;
+    };
+    uint32_t val;
+} sdio_slc1_rxlink_dscr_bf1_reg_t;
+
+/** Type of slc0_tx_erreof_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_tx_err_eof_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_tx_erreof_des_addr_reg_t;
+
+/** Type of slc1_tx_erreof_des_addr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_tx_err_eof_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc1_tx_erreof_des_addr_reg_t;
+
+/** Type of slc_token_lat register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_token : RO; bitpos: [11:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_token:12;
+        uint32_t reserved_12:4;
+        /** slc1_token : RO; bitpos: [27:16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_token:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sdio_slc_token_lat_reg_t;
+
+/** Type of slc_cmd_infor0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** cmd_content0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_content0:32;
+    };
+    uint32_t val;
+} sdio_slc_cmd_infor0_reg_t;
+
+/** Type of slc_cmd_infor1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** cmd_content1 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t cmd_content1:32;
+    };
+    uint32_t val;
+} sdio_slc_cmd_infor1_reg_t;
+
+/** Type of slc0_length register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_len : RO; bitpos: [19:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_len:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sdio_slc0_length_reg_t;
+
+/** Type of slc_sdio_crc_st0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t dat0_crc_err_cnt:8;
+        /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0;
+         *  reserved
+         */
+        uint32_t dat1_crc_err_cnt:8;
+        /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0;
+         *  reserved
+         */
+        uint32_t dat2_crc_err_cnt:8;
+        /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t dat3_crc_err_cnt:8;
+    };
+    uint32_t val;
+} sdio_slc_sdio_crc_st0_reg_t;
+
+/** Type of slc0_eof_start_des register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_eof_start_des_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_eof_start_des_reg_t;
+
+/** Type of slc0_push_dscr_addr register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0;
+         *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
+         */
+        uint32_t slc0_rx_push_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_push_dscr_addr_reg_t;
+
+/** Type of slc0_done_dscr_addr register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0;
+         *  the current descriptor address when slc0 finishes reading data from one buffer,
+         *  aligned with word
+         */
+        uint32_t slc0_rx_done_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_done_dscr_addr_reg_t;
+
+/** Type of slc0_sub_start_des register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
+         *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
+         */
+        uint32_t slc0_sub_pac_start_dscr_addr:32;
+    };
+    uint32_t val;
+} sdio_slc0_sub_start_des_reg_t;
+
+/** Type of slc0_dscr_cnt register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0;
+         *  the number of descriptors got by slc0 when it tries to read data from memory
+         */
+        uint32_t slc0_rx_dscr_cnt_lat:10;
+        uint32_t reserved_10:6;
+        /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_rx_get_eof_occ:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} sdio_slc0_dscr_cnt_reg_t;
+
+
+/** Group: Debud registers */
+/** Type of slc0txfifo_pop register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024;
+         *  reserved
+         */
+        uint32_t slc0_txfifo_rdata:11;
+        uint32_t reserved_11:5;
+        /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc0_txfifo_pop:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} sdio_slc0txfifo_pop_reg_t;
+
+/** Type of slc1txfifo_pop register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024;
+         *  reserved
+         */
+        uint32_t slc1_txfifo_rdata:11;
+        uint32_t reserved_11:5;
+        /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t slc1_txfifo_pop:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} sdio_slc1txfifo_pop_reg_t;
+
+/** Type of slc_ahb_test register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_ahb_testmode:3;
+        uint32_t reserved_3:1;
+        /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
+         *  reserved
+         */
+        uint32_t slc_ahb_testaddr:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} sdio_slc_ahb_test_reg_t;
+
+
+/** Group: Version registers */
+/** Type of slcdate register
+ *  ******* Description ***********
+ */
+typedef union {
+    struct {
+        /** slc_date : R/W; bitpos: [31:0]; default: 554182400;
+         *  reserved
+         */
+        uint32_t slc_date:32;
+    };
+    uint32_t val;
+} sdio_slcdate_reg_t;
+
+
+typedef struct slc_dev_t {
+    volatile sdio_slcconf0_reg_t slcconf0;
+    volatile sdio_slc0int_raw_reg_t slc0int_raw;
+    volatile sdio_slc0int_st_reg_t slc0int_st;
+    volatile sdio_slc0int_ena_reg_t slc0int_ena;
+    volatile sdio_slc0int_clr_reg_t slc0int_clr;
+    volatile sdio_slc1int_raw_reg_t slc1int_raw;
+    volatile sdio_slc1int_st_reg_t slc1int_st;
+    volatile sdio_slc1int_ena_reg_t slc1int_ena;
+    volatile sdio_slc1int_clr_reg_t slc1int_clr;
+    volatile sdio_slcrx_status_reg_t slcrx_status;
+    volatile sdio_slc0rxfifo_push_reg_t slc0rxfifo_push;
+    volatile sdio_slc1rxfifo_push_reg_t slc1rxfifo_push;
+    volatile sdio_slctx_status_reg_t slctx_status;
+    volatile sdio_slc0txfifo_pop_reg_t slc0txfifo_pop;
+    volatile sdio_slc1txfifo_pop_reg_t slc1txfifo_pop;
+    volatile sdio_slc0rx_link_reg_t slc0rx_link;
+    volatile sdio_slc0rx_link_addr_reg_t slc0rx_link_addr;
+    volatile sdio_slc0tx_link_reg_t slc0tx_link;
+    volatile sdio_slc0tx_link_addr_reg_t slc0tx_link_addr;
+    volatile sdio_slc1rx_link_reg_t slc1rx_link;
+    volatile sdio_slc1rx_link_addr_reg_t slc1rx_link_addr;
+    volatile sdio_slc1tx_link_reg_t slc1tx_link;
+    volatile sdio_slc1tx_link_addr_reg_t slc1tx_link_addr;
+    volatile sdio_slcintvec_tohost_reg_t slcintvec_tohost;
+    volatile sdio_slc0token0_reg_t slc0token0;
+    volatile sdio_slc0token1_reg_t slc0token1;
+    volatile sdio_slc1token0_reg_t slc1token0;
+    volatile sdio_slc1token1_reg_t slc1token1;
+    volatile sdio_slcconf1_reg_t slcconf1;
+    volatile sdio_slc0_state0_reg_t slc0_state0;
+    volatile sdio_slc0_state1_reg_t slc0_state1;
+    volatile sdio_slc1_state0_reg_t slc1_state0;
+    volatile sdio_slc1_state1_reg_t slc1_state1;
+    volatile sdio_slcbridge_conf_reg_t slcbridge_conf;
+    volatile sdio_slc0_to_eof_des_addr_reg_t slc0_to_eof_des_addr;
+    volatile sdio_slc0_tx_eof_des_addr_reg_t slc0_tx_eof_des_addr;
+    volatile sdio_slc0_to_eof_bfr_des_addr_reg_t slc0_to_eof_bfr_des_addr;
+    volatile sdio_slc1_to_eof_des_addr_reg_t slc1_to_eof_des_addr;
+    volatile sdio_slc1_tx_eof_des_addr_reg_t slc1_tx_eof_des_addr;
+    volatile sdio_slc1_to_eof_bfr_des_addr_reg_t slc1_to_eof_bfr_des_addr;
+    volatile sdio_slc_ahb_test_reg_t slc_ahb_test;
+    volatile sdio_slc_sdio_st_reg_t slc_sdio_st;
+    volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf;
+    volatile sdio_slc0_txlink_dscr_reg_t slc0_txlink_dscr;
+    volatile sdio_slc0_txlink_dscr_bf0_reg_t slc0_txlink_dscr_bf0;
+    volatile sdio_slc0_txlink_dscr_bf1_reg_t slc0_txlink_dscr_bf1;
+    volatile sdio_slc0_rxlink_dscr_reg_t slc0_rxlink_dscr;
+    volatile sdio_slc0_rxlink_dscr_bf0_reg_t slc0_rxlink_dscr_bf0;
+    volatile sdio_slc0_rxlink_dscr_bf1_reg_t slc0_rxlink_dscr_bf1;
+    volatile sdio_slc1_txlink_dscr_reg_t slc1_txlink_dscr;
+    volatile sdio_slc1_txlink_dscr_bf0_reg_t slc1_txlink_dscr_bf0;
+    volatile sdio_slc1_txlink_dscr_bf1_reg_t slc1_txlink_dscr_bf1;
+    volatile sdio_slc1_rxlink_dscr_reg_t slc1_rxlink_dscr;
+    volatile sdio_slc1_rxlink_dscr_bf0_reg_t slc1_rxlink_dscr_bf0;
+    volatile sdio_slc1_rxlink_dscr_bf1_reg_t slc1_rxlink_dscr_bf1;
+    volatile sdio_slc0_tx_erreof_des_addr_reg_t slc0_tx_erreof_des_addr;
+    volatile sdio_slc1_tx_erreof_des_addr_reg_t slc1_tx_erreof_des_addr;
+    volatile sdio_slc_token_lat_reg_t slc_token_lat;
+    volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf;
+    volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0;
+    volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1;
+    volatile sdio_slc0_len_conf_reg_t slc0_len_conf;
+    volatile sdio_slc0_length_reg_t slc0_length;
+    volatile sdio_slc0_txpkt_h_dscr_reg_t slc0_txpkt_h_dscr;
+    volatile sdio_slc0_txpkt_e_dscr_reg_t slc0_txpkt_e_dscr;
+    volatile sdio_slc0_rxpkt_h_dscr_reg_t slc0_rxpkt_h_dscr;
+    volatile sdio_slc0_rxpkt_e_dscr_reg_t slc0_rxpkt_e_dscr;
+    volatile sdio_slc0_txpktu_h_dscr_reg_t slc0_txpktu_h_dscr;
+    volatile sdio_slc0_txpktu_e_dscr_reg_t slc0_txpktu_e_dscr;
+    volatile sdio_slc0_rxpktu_h_dscr_reg_t slc0_rxpktu_h_dscr;
+    volatile sdio_slc0_rxpktu_e_dscr_reg_t slc0_rxpktu_e_dscr;
+    volatile sdio_slc_seq_position_reg_t slc_seq_position;
+    volatile sdio_slc0_dscr_rec_conf_reg_t slc0_dscr_rec_conf;
+    volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0;
+    volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1;
+    volatile sdio_slc0_eof_start_des_reg_t slc0_eof_start_des;
+    volatile sdio_slc0_push_dscr_addr_reg_t slc0_push_dscr_addr;
+    volatile sdio_slc0_done_dscr_addr_reg_t slc0_done_dscr_addr;
+    volatile sdio_slc0_sub_start_des_reg_t slc0_sub_start_des;
+    volatile sdio_slc0_dscr_cnt_reg_t slc0_dscr_cnt;
+    volatile sdio_slc0_len_lim_conf_reg_t slc0_len_lim_conf;
+    volatile sdio_slc0int_st1_reg_t slc0int_st1;
+    volatile sdio_slc0int_ena1_reg_t slc0int_ena1;
+    volatile sdio_slc1int_st1_reg_t slc1int_st1;
+    volatile sdio_slc1int_ena1_reg_t slc1int_ena1;
+    volatile sdio_slc0_tx_sharemem_start_reg_t slc0_tx_sharemem_start;
+    volatile sdio_slc0_tx_sharemem_end_reg_t slc0_tx_sharemem_end;
+    volatile sdio_slc0_rx_sharemem_start_reg_t slc0_rx_sharemem_start;
+    volatile sdio_slc0_rx_sharemem_end_reg_t slc0_rx_sharemem_end;
+    volatile sdio_slc1_tx_sharemem_start_reg_t slc1_tx_sharemem_start;
+    volatile sdio_slc1_tx_sharemem_end_reg_t slc1_tx_sharemem_end;
+    volatile sdio_slc1_rx_sharemem_start_reg_t slc1_rx_sharemem_start;
+    volatile sdio_slc1_rx_sharemem_end_reg_t slc1_rx_sharemem_end;
+    volatile sdio_hda_tx_sharemem_start_reg_t hda_tx_sharemem_start;
+    volatile sdio_hda_rx_sharemem_start_reg_t hda_rx_sharemem_start;
+    volatile sdio_slc_burst_len_reg_t slc_burst_len;
+    uint32_t reserved_180[30];
+    volatile sdio_slcdate_reg_t slcdate;
+    volatile sdio_slcid_reg_t slcid;
+} slc_dev_t;
+
+extern slc_dev_t SLC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
new file mode 100644
index 0000000000..26f56a0d21
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/soc.h
@@ -0,0 +1,260 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#include "esp_assert.h"
+#endif
+
+#include "esp_bit_defs.h"
+#include "reg_base.h"
+
+#define PRO_CPU_NUM (0)
+
+#define REG_UHCI_BASE(i)                        (DR_REG_UHCI0_BASE)                      // only one UHCI on C6
+#define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x1000)        // UART0 and UART1
+#define UART_FIFO_AHB_REG(i)                    (REG_UART_BASE(i) + 0x0)
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1000)         // only one I2S on C6
+#define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
+#define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
+#define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE + (i) * 0x1000)        // GPSPI2 and GPSPI3
+#define REG_I2C_BASE(i)                         (DR_REG_I2C0_BASE + (i) * 0x1000)
+#define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE + (i) * 0x1000)
+#define REG_TWAI_BASE(i)                        (DR_REG_TWAI0_BASE + (i) * 0x1000)        // TWAI0 and TWAI1
+
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr) (addr)
+
+#ifndef __ASSEMBLER__
+
+//write value to register
+#define REG_WRITE(_r, _v)  do {                                                                                        \
+            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
+        } while(0)
+
+//read value from register
+#define REG_READ(_r) ({                                                                                                \
+            (*(volatile uint32_t *)(_r));                                                                              \
+        })
+
+//get bit or get bits from register
+#define REG_GET_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
+        })
+
+//set bit or set bits to register
+#define REG_SET_BIT(_r, _b)  do {                                                                                      \
+            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b);                                            \
+        } while(0)
+
+//clear bit or clear bits of register
+#define REG_CLR_BIT(_r, _b)  do {                                                                                      \
+            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b));                                         \
+        } while(0)
+
+//set bits of register controlled by mask
+#define REG_SET_BITS(_r, _b, _m) do {                                                                                  \
+            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m));                           \
+        } while(0)
+
+//get field from register, uses field _S & _V to determine mask
+#define REG_GET_FIELD(_r, _f) ({                                                                                       \
+            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
+        })
+
+//set field of a register from variable, uses field _S & _V to determine mask
+#define REG_SET_FIELD(_r, _f, _v) do {                                                                                 \
+            REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))));                  \
+        } while(0)
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//read value from register
+#define READ_PERI_REG(addr) ({                                                                                         \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
+        })
+
+//write value to register
+#define WRITE_PERI_REG(addr, val) do {                                                                                 \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
+        } while(0)
+
+//clear bits of register controlled by mask
+#define CLEAR_PERI_REG_MASK(reg, mask)  do {                                                                           \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
+        } while(0)
+
+//set bits of register controlled by mask
+#define SET_PERI_REG_MASK(reg, mask) do {                                                                              \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
+        } while(0)
+
+//get bits of register controlled by mask
+#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            (READ_PERI_REG(reg) & (mask));                                                                             \
+        })
+
+//get bits of register controlled by highest bit and lowest bit
+#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
+            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
+        })
+
+//set bits of register controlled by mask and shift
+#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do {                                                                \
+            WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) );      \
+        } while(0)
+
+//get field of register
+#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
+            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
+        })
+
+#endif /* !__ASSEMBLER__ */
+//}}
+
+//Periheral Clock {{
+#define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
+#define  CPU_CLK_FREQ                                APB_CLK_FREQ
+#define  APB_CLK_FREQ                                ( 40*1000000 )
+#define  MODEM_APB_CLK_FREQ                          ( 80*1000000 )
+#define  REF_CLK_FREQ                                ( 1000000 )
+#define  XTAL_CLK_FREQ                               (40*1000000)
+#define  GPIO_MATRIX_DELAY_NS                        0
+//}}
+
+/* Overall memory map */
+/* Note: We should not use MACROs similar in cache_memory.h
+ * those are defined during run-time. But the MACROs here
+ * should be defined statically!
+ */
+
+#define SOC_IROM_LOW    0x40000000
+#define SOC_IROM_HIGH   0x44000000
+#define SOC_DROM_LOW    0x40000000
+#define SOC_DROM_HIGH   0x44000000
+
+#define SOC_SINGLE_BANK_LOW  0x40000000
+#define SOC_SINGLE_BANK_HIGH 0x44000000
+#define SOC_DUAL_BANK_LOW    0x48000000
+#define SOC_DUAL_BANK_HIGH   0x4c000000
+#define SOC_EXT_DBRAM_DATA_LOW 0x4a000000
+#define SOC_EXT_DBRAM_DATA_HIGH 0x4c000000
+
+#define SOC_IROM_MASK_LOW  0x4fc00000
+#define SOC_IROM_MASK_HIGH 0x4fc20000
+#define SOC_DROM_MASK_LOW  0x4fc00000
+#define SOC_DROM_MASK_HIGH 0x4fc20000
+#define SOC_TCM_LOW     0x30100000
+#define SOC_TCM_HIGH    0x30102000
+#define SOC_IRAM_LOW    0x4ff00000
+#define SOC_IRAM_HIGH   0x4ffc0000
+#define SOC_DRAM_LOW    0x4ff00000
+#define SOC_DRAM_HIGH   0x4ffc0000
+#define SOC_RTC_IRAM_LOW  0x50108000 // ESP32-P4 only has 32k LP memory
+#define SOC_RTC_IRAM_HIGH 0x50110000
+#define SOC_RTC_DRAM_LOW  0x50108000
+#define SOC_RTC_DRAM_HIGH 0x50110000
+#define SOC_RTC_DATA_LOW  0x50108000
+#define SOC_RTC_DATA_HIGH 0x50110000
+
+#define SOC_LP_ROM_LOW    0x50100000
+#define SOC_LP_ROM_HIGH   0x50104000
+
+#define SOC_LP_RAM_LOW    0x50108000
+#define SOC_LP_RAM_HIGH   0x50110000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW    0x4ff00000
+#define SOC_DIRAM_IRAM_HIGH   0x4ffc0000
+#define SOC_DIRAM_DRAM_LOW    0x4ff00000
+#define SOC_DIRAM_DRAM_HIGH   0x4ffc0000
+#define SOC_DIRAM_ROM_RESERVE_HIGH 0x4ff40000
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW  0x4ff00000
+#define SOC_DMA_HIGH 0x4ffc0000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW     0x4ff00000
+#define SOC_BYTE_ACCESSIBLE_HIGH    0x4ffc0000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW        0x4ff00000
+#define SOC_MEM_INTERNAL_HIGH       0x4ffc0000
+#define SOC_MEM_INTERNAL_LOW1       0x4ff00000
+#define SOC_MEM_INTERNAL_HIGH1      0x4ffc0000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_DUAL_BANK_HIGH - SOC_DUAL_BANK_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+#define CPU_PERIPH_LOW     0x3ff00000
+#define CPU_PERIPH_HIGH    0x3ff20000
+
+// Region of address space that holds peripherals, HP APB peripherals
+#define SOC_PERIPHERAL_LOW 0x50000000
+#define SOC_PERIPHERAL_HIGH 0x50100000
+
+#define SOC_LP_PERIPH_LOW  0x50110000
+#define SOC_LP_PERIPH_HIGH 0x50130000
+
+// Debug region, not used by software
+#define SOC_DEBUG_LOW 0x20000000
+#define SOC_DEBUG_HIGH 0x28000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START         0x4ff5abd0
+#define SOC_ROM_STACK_SIZE          0x2000
+
+//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
+//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
+
+//CPU0 Interrupt number reserved in riscv/vector.S, not touch this.
+#define ETS_T1_WDT_INUM                         24
+#define ETS_CACHEERR_INUM                       25
+#define ETS_MEMPROT_ERR_INUM                    26
+//CPU0 Max valid interrupt number
+#define ETS_MAX_INUM                            31
+
+//CPU0 Interrupt number used in ROM, should be cancelled in SDK
+#define ETS_SLC_INUM                            1
+#define ETS_UART0_INUM                          5
+#define ETS_UART1_INUM                          5
+#define ETS_SPI2_INUM                           1
+//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
+#define ETS_GPIO_INUM       4
+
+//Other interrupt number should be managed by the user
+
+//Invalid interrupt for number interrupt matrix
+#define ETS_INVALID_INUM                        0
+
+//Interrupt medium level, used for INT WDT for example
+#define SOC_INTERRUPT_LEVEL_MEDIUM              4
+
+// Interrupt number for the Interrupt watchdog
+#define ETS_INT_WDT_INUM                         (ETS_T1_WDT_INUM)
diff --git a/components/soc/esp32p4/include/soc/soc_etm_source.h b/components/soc/esp32p4/include/soc/soc_etm_source.h
new file mode 100644
index 0000000000..4b64ac3c6c
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/soc_etm_source.h
@@ -0,0 +1,532 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// =============================
+// Auto generate by python(mako)
+// =============================
+
+#define GPIO_EVT_CH0_RISE_EDGE 1
+#define GPIO_EVT_CH1_RISE_EDGE 2
+#define GPIO_EVT_CH2_RISE_EDGE 3
+#define GPIO_EVT_CH3_RISE_EDGE 4
+#define GPIO_EVT_CH4_RISE_EDGE 5
+#define GPIO_EVT_CH5_RISE_EDGE 6
+#define GPIO_EVT_CH6_RISE_EDGE 7
+#define GPIO_EVT_CH7_RISE_EDGE 8
+#define GPIO_EVT_CH0_FALL_EDGE 9
+#define GPIO_EVT_CH1_FALL_EDGE 10
+#define GPIO_EVT_CH2_FALL_EDGE 11
+#define GPIO_EVT_CH3_FALL_EDGE 12
+#define GPIO_EVT_CH4_FALL_EDGE 13
+#define GPIO_EVT_CH5_FALL_EDGE 14
+#define GPIO_EVT_CH6_FALL_EDGE 15
+#define GPIO_EVT_CH7_FALL_EDGE 16
+#define GPIO_EVT_CH0_ANY_EDGE 17
+#define GPIO_EVT_CH1_ANY_EDGE 18
+#define GPIO_EVT_CH2_ANY_EDGE 19
+#define GPIO_EVT_CH3_ANY_EDGE 20
+#define GPIO_EVT_CH4_ANY_EDGE 21
+#define GPIO_EVT_CH5_ANY_EDGE 22
+#define GPIO_EVT_CH6_ANY_EDGE 23
+#define GPIO_EVT_CH7_ANY_EDGE 24
+#define GPIO_EVT_ZERO_DET_POS0 25
+#define GPIO_EVT_ZERO_DET_NEG0 26
+#define GPIO_EVT_ZERO_DET_POS1 27
+#define GPIO_EVT_ZERO_DET_NEG1 28
+#define LEDC_EVT_DUTY_CHNG_END_CH0 29
+#define LEDC_EVT_DUTY_CHNG_END_CH1 30
+#define LEDC_EVT_DUTY_CHNG_END_CH2 31
+#define LEDC_EVT_DUTY_CHNG_END_CH3 32
+#define LEDC_EVT_DUTY_CHNG_END_CH4 33
+#define LEDC_EVT_DUTY_CHNG_END_CH5 34
+#define LEDC_EVT_DUTY_CHNG_END_CH6 35
+#define LEDC_EVT_DUTY_CHNG_END_CH7 36
+#define LEDC_EVT_OVF_CNT_PLS_CH0 37
+#define LEDC_EVT_OVF_CNT_PLS_CH1 38
+#define LEDC_EVT_OVF_CNT_PLS_CH2 39
+#define LEDC_EVT_OVF_CNT_PLS_CH3 40
+#define LEDC_EVT_OVF_CNT_PLS_CH4 41
+#define LEDC_EVT_OVF_CNT_PLS_CH5 42
+#define LEDC_EVT_OVF_CNT_PLS_CH6 43
+#define LEDC_EVT_OVF_CNT_PLS_CH7 44
+#define LEDC_EVT_TIME_OVF_TIMER0 45
+#define LEDC_EVT_TIME_OVF_TIMER1 46
+#define LEDC_EVT_TIME_OVF_TIMER2 47
+#define LEDC_EVT_TIME_OVF_TIMER3 48
+#define LEDC_EVT_TIMER0_CMP 49
+#define LEDC_EVT_TIMER1_CMP 50
+#define LEDC_EVT_TIMER2_CMP 51
+#define LEDC_EVT_TIMER3_CMP 52
+#define PCNT_EVT_CNT_EQ_THRESH 53
+#define PCNT_EVT_CNT_EQ_LMT 54
+#define PCNT_EVT_CNT_EQ_ZERO 55
+#define TG0_EVT_CNT_CMP_TIMER0 56
+#define TG0_EVT_CNT_CMP_TIMER1 57
+#define TG1_EVT_CNT_CMP_TIMER0 58
+#define TG1_EVT_CNT_CMP_TIMER1 59
+#define SYSTIMER_EVT_CNT_CMP0 60
+#define SYSTIMER_EVT_CNT_CMP1 61
+#define SYSTIMER_EVT_CNT_CMP2 62
+#define RMT_EVT_TX_END 63
+#define RMT_EVT_TX_LOOP 64
+#define RMT_EVT_RX_END 65
+#define RMT_EVT_TX_THRESH 66
+#define RMT_EVT_RX_THRESH 67
+#define MCPWM0_EVT_TIMER0_STOP 68
+#define MCPWM0_EVT_TIMER1_STOP 69
+#define MCPWM0_EVT_TIMER2_STOP 70
+#define MCPWM0_EVT_TIMER0_TEZ 71
+#define MCPWM0_EVT_TIMER1_TEZ 72
+#define MCPWM0_EVT_TIMER2_TEZ 73
+#define MCPWM0_EVT_TIMER0_TEP 74
+#define MCPWM0_EVT_TIMER1_TEP 75
+#define MCPWM0_EVT_TIMER2_TEP 76
+#define MCPWM0_EVT_OP0_TEA 77
+#define MCPWM0_EVT_OP1_TEA 78
+#define MCPWM0_EVT_OP2_TEA 79
+#define MCPWM0_EVT_OP0_TEB 80
+#define MCPWM0_EVT_OP1_TEB 81
+#define MCPWM0_EVT_OP2_TEB 82
+#define MCPWM0_EVT_F0 83
+#define MCPWM0_EVT_F1 84
+#define MCPWM0_EVT_F2 85
+#define MCPWM0_EVT_F0_CLR 86
+#define MCPWM0_EVT_F1_CLR 87
+#define MCPWM0_EVT_F2_CLR 88
+#define MCPWM0_EVT_TZ0_CBC 89
+#define MCPWM0_EVT_TZ1_CBC 90
+#define MCPWM0_EVT_TZ2_CBC 91
+#define MCPWM0_EVT_TZ0_OST 92
+#define MCPWM0_EVT_TZ1_OST 93
+#define MCPWM0_EVT_TZ2_OST 94
+#define MCPWM0_EVT_CAP0 95
+#define MCPWM0_EVT_CAP1 96
+#define MCPWM0_EVT_CAP2 97
+#define MCPWM0_EVT_OP0_TEE1 98
+#define MCPWM0_EVT_OP1_TEE1 99
+#define MCPWM0_EVT_OP2_TEE1 100
+#define MCPWM0_EVT_OP0_TEE2 101
+#define MCPWM0_EVT_OP1_TEE2 102
+#define MCPWM0_EVT_OP2_TEE2 103
+#define MCPWM1_EVT_TIMER0_STOP 104
+#define MCPWM1_EVT_TIMER1_STOP 105
+#define MCPWM1_EVT_TIMER2_STOP 106
+#define MCPWM1_EVT_TIMER0_TEZ 107
+#define MCPWM1_EVT_TIMER1_TEZ 108
+#define MCPWM1_EVT_TIMER2_TEZ 109
+#define MCPWM1_EVT_TIMER0_TEP 110
+#define MCPWM1_EVT_TIMER1_TEP 111
+#define MCPWM1_EVT_TIMER2_TEP 112
+#define MCPWM1_EVT_OP0_TEA 113
+#define MCPWM1_EVT_OP1_TEA 114
+#define MCPWM1_EVT_OP2_TEA 115
+#define MCPWM1_EVT_OP0_TEB 116
+#define MCPWM1_EVT_OP1_TEB 117
+#define MCPWM1_EVT_OP2_TEB 118
+#define MCPWM1_EVT_F0 119
+#define MCPWM1_EVT_F1 120
+#define MCPWM1_EVT_F2 121
+#define MCPWM1_EVT_F0_CLR 122
+#define MCPWM1_EVT_F1_CLR 123
+#define MCPWM1_EVT_F2_CLR 124
+#define MCPWM1_EVT_TZ0_CBC 125
+#define MCPWM1_EVT_TZ1_CBC 126
+#define MCPWM1_EVT_TZ2_CBC 127
+#define MCPWM1_EVT_TZ0_OST 128
+#define MCPWM1_EVT_TZ1_OST 129
+#define MCPWM1_EVT_TZ2_OST 130
+#define MCPWM1_EVT_CAP0 131
+#define MCPWM1_EVT_CAP1 132
+#define MCPWM1_EVT_CAP2 133
+#define MCPWM1_EVT_OP0_TEE1 134
+#define MCPWM1_EVT_OP1_TEE1 135
+#define MCPWM1_EVT_OP2_TEE1 136
+#define MCPWM1_EVT_OP0_TEE2 137
+#define MCPWM1_EVT_OP1_TEE2 138
+#define MCPWM1_EVT_OP2_TEE2 139
+#define ADC_EVT_CONV_CMPLT0 140
+#define ADC_EVT_EQ_ABOVE_THRESH0 141
+#define ADC_EVT_EQ_ABOVE_THRESH1 142
+#define ADC_EVT_EQ_BELOW_THRESH0 143
+#define ADC_EVT_EQ_BELOW_THRESH1 144
+#define ADC_EVT_RESULT_DONE0 145
+#define ADC_EVT_STOPPED0 146
+#define ADC_EVT_STARTED0 147
+#define REGDMA_EVT_DONE0 148
+#define REGDMA_EVT_DONE1 149
+#define REGDMA_EVT_DONE2 150
+#define REGDMA_EVT_DONE3 151
+#define REGDMA_EVT_ERR0 152
+#define REGDMA_EVT_ERR1 153
+#define REGDMA_EVT_ERR2 154
+#define REGDMA_EVT_ERR3 155
+#define PDMA_EVT_TX_DONE 156
+#define PDMA_EVT_OUT_EOF 157
+#define PDMA_EVT_IN_SUC_EOF 158
+#define PDMA_EVT_FULL_OR_EMPTY 159
+#define PDMA_EVT_ALL_DONE 160
+#define PDMA_EVT_RX_DONE 161
+#define TMPSNSR_EVT_OVER_LIMIT 162
+#define UART_EVT_REC_DATA_OVF0 163
+#define UART_EVT_REC_DATA_OVF1 164
+#define UART_EVT_TX_DONE0 165
+#define UART_EVT_TX_DONE1 166
+#define UART_EVT_TIMEOUT0 167
+#define UART_EVT_TIMEOUT1 168
+#define UART_EVT_ERR0 169
+#define UART_EVT_ERR1 170
+#define UART_EVT_CTS0 171
+#define UART_EVT_CTS1 172
+#define UART_EVT_TX_EMPTY0 173
+#define UART_EVT_TX_EMPTY1 174
+#define UART_EVT_AT_PATTERNS0 175
+#define UART_EVT_AT_PATTERNS1 176
+#define SPI_EVT_STOPPED 177
+#define I2S0_EVT_RX_DONE 178
+#define I2S0_EVT_TX_DONE 179
+#define I2S0_EVT_X_WORDS_RECEIVED 180
+#define I2S0_EVT_X_WORDS_SENT 181
+#define I2S1_EVT_RX_DONE 182
+#define I2S1_EVT_TX_DONE 183
+#define I2S1_EVT_X_WORDS_RECEIVED 184
+#define I2S1_EVT_X_WORDS_SENT 185
+#define I2S2_EVT_RX_DONE 186
+#define I2S2_EVT_TX_DONE 187
+#define I2S2_EVT_X_WORDS_RECEIVED 188
+#define I2S2_EVT_X_WORDS_SENT 189
+#define I2C_EVT_TRANS_DONE 190
+#define LCDCAM_EVT_TRANS_DONE 191
+#define CAN_EVT_TRANS_DONE 192
+#define ULP_EVT_ERR_INTR 193
+#define ULP_EVT_HALT 194
+#define ULP_EVT_START_INTR 195
+#define RTC_EVT_TICK 196
+#define RTC_EVT_OVF 197
+#define RTC_EVT_CMP 198
+#define GDMA_AHB_EVT_IN_DONE_CH0 199
+#define GDMA_AHB_EVT_IN_DONE_CH1 200
+#define GDMA_AHB_EVT_IN_DONE_CH2 201
+#define GDMA_AHB_EVT_IN_SUC_EOF_CH0 202
+#define GDMA_AHB_EVT_IN_SUC_EOF_CH1 203
+#define GDMA_AHB_EVT_IN_SUC_EOF_CH2 204
+#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 205
+#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 206
+#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 207
+#define GDMA_AHB_EVT_IN_FIFO_FULL_CH0 208
+#define GDMA_AHB_EVT_IN_FIFO_FULL_CH1 209
+#define GDMA_AHB_EVT_IN_FIFO_FULL_CH2 210
+#define GDMA_AHB_EVT_OUT_DONE_CH0 211
+#define GDMA_AHB_EVT_OUT_DONE_CH1 212
+#define GDMA_AHB_EVT_OUT_DONE_CH2 213
+#define GDMA_AHB_EVT_OUT_EOF_CH0 214
+#define GDMA_AHB_EVT_OUT_EOF_CH1 215
+#define GDMA_AHB_EVT_OUT_EOF_CH2 216
+#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 217
+#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 218
+#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 219
+#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 220
+#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 221
+#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 222
+#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 223
+#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 224
+#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH2 225
+#define GDMA_AXI_EVT_IN_DONE_CH0 226
+#define GDMA_AXI_EVT_IN_DONE_CH1 227
+#define GDMA_AXI_EVT_IN_DONE_CH2 228
+#define GDMA_AXI_EVT_IN_DONE_CH3 229
+#define GDMA_AXI_EVT_IN_DONE_CH4 230
+#define GDMA_AXI_EVT_IN_SUC_EOF_CH0 231
+#define GDMA_AXI_EVT_IN_SUC_EOF_CH1 232
+#define GDMA_AXI_EVT_IN_SUC_EOF_CH2 233
+#define GDMA_AXI_EVT_IN_SUC_EOF_CH3 234
+#define GDMA_AXI_EVT_IN_SUC_EOF_CH4 235
+#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH0 236
+#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH1 237
+#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH2 238
+#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH3 239
+#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH4 240
+#define GDMA_AXI_EVT_IN_FIFO_FULL_CH0 241
+#define GDMA_AXI_EVT_IN_FIFO_FULL_CH1 242
+#define GDMA_AXI_EVT_IN_FIFO_FULL_CH2 243
+#define GDMA_AXI_EVT_IN_FIFO_FULL_CH3 244
+#define GDMA_AXI_EVT_IN_FIFO_FULL_CH4 245
+#define GDMA_AXI_EVT_OUT_DONE_CH0 246
+#define GDMA_AXI_EVT_OUT_DONE_CH1 247
+#define GDMA_AXI_EVT_OUT_DONE_CH2 248
+#define GDMA_AXI_EVT_OUT_DONE_CH3 249
+#define GDMA_AXI_EVT_OUT_DONE_CH4 250
+#define GDMA_AXI_EVT_OUT_EOF_CH0 251
+#define GDMA_AXI_EVT_OUT_EOF_CH1 252
+#define GDMA_AXI_EVT_OUT_EOF_CH2 253
+#define GDMA_AXI_EVT_OUT_EOF_CH3 254
+#define GDMA_AXI_EVT_OUT_EOF_CH4 255
+#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH0 256
+#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH1 257
+#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH2 258
+#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH3 259
+#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH4 260
+#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0 261
+#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1 262
+#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2 263
+#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH3 264
+#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH4 265
+#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH0 266
+#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH1 267
+#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH2 268
+#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH3 269
+#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH4 270
+#define PMU_EVT_SLEEP_WEEKUP 271
+#define DMA2D_EVT_IN_DONE_CH0 272
+#define DMA2D_EVT_IN_DONE_CH1 273
+#define DMA2D_EVT_IN_SUC_EOF_CH0 274
+#define DMA2D_EVT_IN_SUC_EOF_CH1 275
+#define DMA2D_EVT_OUT_DONE_CH0 276
+#define DMA2D_EVT_OUT_DONE_CH1 277
+#define DMA2D_EVT_OUT_DONE_CH2 278
+#define DMA2D_EVT_OUT_EOF_CH0 279
+#define DMA2D_EVT_OUT_EOF_CH1 280
+#define DMA2D_EVT_OUT_EOF_CH2 281
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH0 282
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH1 283
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH2 284
+
+#define GPIO_TASK_CH0_SET 1
+#define GPIO_TASK_CH1_SET 2
+#define GPIO_TASK_CH2_SET 3
+#define GPIO_TASK_CH3_SET 4
+#define GPIO_TASK_CH4_SET 5
+#define GPIO_TASK_CH5_SET 6
+#define GPIO_TASK_CH6_SET 7
+#define GPIO_TASK_CH7_SET 8
+#define GPIO_TASK_CH0_CLEAR 9
+#define GPIO_TASK_CH1_CLEAR 10
+#define GPIO_TASK_CH2_CLEAR 11
+#define GPIO_TASK_CH3_CLEAR 12
+#define GPIO_TASK_CH4_CLEAR 13
+#define GPIO_TASK_CH5_CLEAR 14
+#define GPIO_TASK_CH6_CLEAR 15
+#define GPIO_TASK_CH7_CLEAR 16
+#define GPIO_TASK_CH0_TOGGLE 17
+#define GPIO_TASK_CH1_TOGGLE 18
+#define GPIO_TASK_CH2_TOGGLE 19
+#define GPIO_TASK_CH3_TOGGLE 20
+#define GPIO_TASK_CH4_TOGGLE 21
+#define GPIO_TASK_CH5_TOGGLE 22
+#define GPIO_TASK_CH6_TOGGLE 23
+#define GPIO_TASK_CH7_TOGGLE 24
+#define LEDC_TASK_TIMER0_RES_UPDATE 25
+#define LEDC_TASK_TIMER1_RES_UPDATE 26
+#define LEDC_TASK_TIMER2_RES_UPDATE 27
+#define LEDC_TASK_TIMER3_RES_UPDATE 28
+#define LEDC_TASK_RSV0 29
+#define LEDC_TASK_RSV1 30
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6 37
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7 38
+#define LEDC_TASK_TIMER0_CAP 39
+#define LEDC_TASK_TIMER1_CAP 40
+#define LEDC_TASK_TIMER2_CAP 41
+#define LEDC_TASK_TIMER3_CAP 42
+#define LEDC_TASK_SIG_OUT_DIS_CH0 43
+#define LEDC_TASK_SIG_OUT_DIS_CH1 44
+#define LEDC_TASK_SIG_OUT_DIS_CH2 45
+#define LEDC_TASK_SIG_OUT_DIS_CH3 46
+#define LEDC_TASK_SIG_OUT_DIS_CH4 47
+#define LEDC_TASK_SIG_OUT_DIS_CH5 48
+#define LEDC_TASK_SIG_OUT_DIS_CH6 49
+#define LEDC_TASK_SIG_OUT_DIS_CH7 50
+#define LEDC_TASK_OVF_CNT_RST_CH0 51
+#define LEDC_TASK_OVF_CNT_RST_CH1 52
+#define LEDC_TASK_OVF_CNT_RST_CH2 53
+#define LEDC_TASK_OVF_CNT_RST_CH3 54
+#define LEDC_TASK_OVF_CNT_RST_CH4 55
+#define LEDC_TASK_OVF_CNT_RST_CH5 56
+#define LEDC_TASK_OVF_CNT_RST_CH6 57
+#define LEDC_TASK_OVF_CNT_RST_CH7 58
+#define LEDC_TASK_TIMER0_RST 59
+#define LEDC_TASK_TIMER1_RST 60
+#define LEDC_TASK_TIMER2_RST 61
+#define LEDC_TASK_TIMER3_RST 62
+#define LEDC_TASK_TIMER0_RESUME 63
+#define LEDC_TASK_TIMER1_RESUME 64
+#define LEDC_TASK_TIMER2_RESUME 65
+#define LEDC_TASK_TIMER3_RESUME 66
+#define LEDC_TASK_TIMER0_PAUSE 67
+#define LEDC_TASK_TIMER1_PAUSE 68
+#define LEDC_TASK_TIMER2_PAUSE 69
+#define LEDC_TASK_TIMER3_PAUSE 70
+#define LEDC_TASK_GAMMA_RESTART_CH0 71
+#define LEDC_TASK_GAMMA_RESTART_CH1 72
+#define LEDC_TASK_GAMMA_RESTART_CH2 73
+#define LEDC_TASK_GAMMA_RESTART_CH3 74
+#define LEDC_TASK_GAMMA_RESTART_CH4 75
+#define LEDC_TASK_GAMMA_RESTART_CH5 76
+#define LEDC_TASK_GAMMA_RESTART_CH6 77
+#define LEDC_TASK_GAMMA_RESTART_CH7 78
+#define LEDC_TASK_GAMMA_PAUSE_CH0 79
+#define LEDC_TASK_GAMMA_PAUSE_CH1 80
+#define LEDC_TASK_GAMMA_PAUSE_CH2 81
+#define LEDC_TASK_GAMMA_PAUSE_CH3 82
+#define LEDC_TASK_GAMMA_PAUSE_CH4 83
+#define LEDC_TASK_GAMMA_PAUSE_CH5 84
+#define LEDC_TASK_GAMMA_PAUSE_CH6 85
+#define LEDC_TASK_GAMMA_PAUSE_CH7 86
+#define LEDC_TASK_GAMMA_RESUME_CH0 87
+#define LEDC_TASK_GAMMA_RESUME_CH1 88
+#define LEDC_TASK_GAMMA_RESUME_CH2 89
+#define LEDC_TASK_GAMMA_RESUME_CH3 90
+#define LEDC_TASK_GAMMA_RESUME_CH4 91
+#define LEDC_TASK_GAMMA_RESUME_CH5 92
+#define LEDC_TASK_GAMMA_RESUME_CH6 93
+#define LEDC_TASK_GAMMA_RESUME_CH7 94
+#define PCNT_TASK_START 95
+#define PCNT_TASK_STOP 96
+#define PCNT_TASK_CNT_INC 97
+#define PCNT_TASK_CNT_DEC 98
+#define PCNT_TASK_CNT_RST 99
+#define TG0_TASK_CNT_START_TIMER0 100
+#define TG0_TASK_ALARM_START_TIMER0 101
+#define TG0_TASK_CNT_STOP_TIMER0 102
+#define TG0_TASK_CNT_RELOAD_TIMER0 103
+#define TG0_TASK_CNT_CAP_TIMER0 104
+#define TG0_TASK_CNT_START_TIMER1 105
+#define TG0_TASK_ALARM_START_TIMER1 106
+#define TG0_TASK_CNT_STOP_TIMER1 107
+#define TG0_TASK_CNT_RELOAD_TIMER1 108
+#define TG0_TASK_CNT_CAP_TIMER1 109
+#define TG1_TASK_CNT_START_TIMER0 110
+#define TG1_TASK_ALARM_START_TIMER0 111
+#define TG1_TASK_CNT_STOP_TIMER0 112
+#define TG1_TASK_CNT_RELOAD_TIMER0 113
+#define TG1_TASK_CNT_CAP_TIMER0 114
+#define TG1_TASK_CNT_START_TIMER1 115
+#define TG1_TASK_ALARM_START_TIMER1 116
+#define TG1_TASK_CNT_STOP_TIMER1 117
+#define TG1_TASK_CNT_RELOAD_TIMER1 118
+#define TG1_TASK_CNT_CAP_TIMER1 119
+#define RMT_TASK_TX_START 120
+#define RMT_TASK_TX_STOP 121
+#define RMT_TASK_RX_DONE 122
+#define RMT_TASK_RX_START 123
+#define MCPWM0_TASK_CMPR0_A_UP 124
+#define MCPWM0_TASK_CMPR1_A_UP 125
+#define MCPWM0_TASK_CMPR2_A_UP 126
+#define MCPWM0_TASK_CMPR0_B_UP 127
+#define MCPWM0_TASK_CMPR1_B_UP 128
+#define MCPWM0_TASK_CMPR2_B_UP 129
+#define MCPWM0_TASK_GEN_STOP 130
+#define MCPWM0_TASK_TIMER0_SYN 131
+#define MCPWM0_TASK_TIMER1_SYN 132
+#define MCPWM0_TASK_TIMER2_SYN 133
+#define MCPWM0_TASK_TIMER0_PERIOD_UP 134
+#define MCPWM0_TASK_TIMER1_PERIOD_UP 135
+#define MCPWM0_TASK_TIMER2_PERIOD_UP 136
+#define MCPWM0_TASK_TZ0_OST 137
+#define MCPWM0_TASK_TZ1_OST 138
+#define MCPWM0_TASK_TZ2_OST 139
+#define MCPWM0_TASK_CLR0_OST 140
+#define MCPWM0_TASK_CLR1_OST 141
+#define MCPWM0_TASK_CLR2_OST 142
+#define MCPWM0_TASK_CAP0 143
+#define MCPWM0_TASK_CAP1 144
+#define MCPWM0_TASK_CAP2 145
+#define MCPWM1_TASK_CMPR0_A_UP 146
+#define MCPWM1_TASK_CMPR1_A_UP 147
+#define MCPWM1_TASK_CMPR2_A_UP 148
+#define MCPWM1_TASK_CMPR0_B_UP 149
+#define MCPWM1_TASK_CMPR1_B_UP 150
+#define MCPWM1_TASK_CMPR2_B_UP 151
+#define MCPWM1_TASK_GEN_STOP 152
+#define MCPWM1_TASK_TIMER0_SYN 153
+#define MCPWM1_TASK_TIMER1_SYN 154
+#define MCPWM1_TASK_TIMER2_SYN 155
+#define MCPWM1_TASK_TIMER0_PERIOD_UP 156
+#define MCPWM1_TASK_TIMER1_PERIOD_UP 157
+#define MCPWM1_TASK_TIMER2_PERIOD_UP 158
+#define MCPWM1_TASK_TZ0_OST 159
+#define MCPWM1_TASK_TZ1_OST 160
+#define MCPWM1_TASK_TZ2_OST 161
+#define MCPWM1_TASK_CLR0_OST 162
+#define MCPWM1_TASK_CLR1_OST 163
+#define MCPWM1_TASK_CLR2_OST 164
+#define MCPWM1_TASK_CAP0 165
+#define MCPWM1_TASK_CAP1 166
+#define MCPWM1_TASK_CAP2 167
+#define ADC_TASK_SAMPLE0 168
+#define ADC_TASK_SAMPLE1 169
+#define ADC_TASK_START0 170
+#define ADC_TASK_STOP0 171
+#define REGDMA_TASK_START0 172
+#define REGDMA_TASK_START1 173
+#define REGDMA_TASK_START2 174
+#define REGDMA_TASK_START3 175
+#define PDMA_TASK_START_TX 176
+#define PDMA_TASK_START_RX 177
+#define PDMA_TASK_STOP 178
+#define TMPSNSR_TASK_START_SAMPLE 179
+#define TMPSNSR_TASK_STOP_SAMPLE 180
+#define UART_TASK_TX_START0 181
+#define UART_TASK_TX_START1 182
+#define UART_TASK_TX_STOP0 183
+#define UART_TASK_TX_STOP1 184
+#define UART_TASK_RX_START0 185
+#define UART_TASK_RX_START1 186
+#define UART_TASK_RX_STOP0 187
+#define UART_TASK_RX_STOP1 188
+#define SPI_TASK_TX_START 189
+#define SPI_TASK_SLAVE_HD 190
+#define SPI_TASK_STOP 191
+#define I2S0_TASK_START_RX 192
+#define I2S0_TASK_START_TX 193
+#define I2S0_TASK_STOP_RX 194
+#define I2S0_TASK_STOP_TX 195
+#define I2S1_TASK_START_RX 196
+#define I2S1_TASK_START_TX 197
+#define I2S1_TASK_STOP_RX 198
+#define I2S1_TASK_STOP_TX 199
+#define I2S2_TASK_START_RX 200
+#define I2S2_TASK_START_TX 201
+#define I2S2_TASK_STOP_RX 202
+#define I2S2_TASK_STOP_TX 203
+#define I2C_TASK_START_TRANS 204
+#define CAN_TASK_TRANS_START 205
+#define ULP_TASK_WAKEUP_CPU 206
+#define ULP_TASK_INT_CPU 207
+#define RTC_TASK_START 208
+#define RTC_TASK_STOP 209
+#define RTC_TASK_CLR 210
+#define RTC_TASK_TRIGGERFLW 211
+#define GDMA_AHB_TASK_IN_START_CH0 212
+#define GDMA_AHB_TASK_IN_START_CH1 213
+#define GDMA_AHB_TASK_IN_START_CH2 214
+#define GDMA_AHB_TASK_OUT_START_CH0 215
+#define GDMA_AHB_TASK_OUT_START_CH1 216
+#define GDMA_AHB_TASK_OUT_START_CH2 217
+#define GDMA_AXI_TASK_IN_START_CH0 218
+#define GDMA_AXI_TASK_IN_START_CH1 219
+#define GDMA_AXI_TASK_IN_START_CH2 220
+#define GDMA_AXI_TASK_IN_START_CH3 221
+#define GDMA_AXI_TASK_IN_START_CH4 222
+#define GDMA_AXI_TASK_OUT_START_CH0 223
+#define GDMA_AXI_TASK_OUT_START_CH1 224
+#define GDMA_AXI_TASK_OUT_START_CH2 225
+#define GDMA_AXI_TASK_OUT_START_CH3 226
+#define GDMA_AXI_TASK_OUT_START_CH4 227
+#define PMU_TASK_SLEEP_REQ 228
+#define DMA2D_TASK_IN_START_CH0 229
+#define DMA2D_TASK_IN_START_CH1 230
+#define DMA2D_TASK_IN_DSCR_READY_CH0 231
+#define DMA2D_TASK_IN_DSCR_READY_CH1 232
+#define DMA2D_TASK_OUT_START_CH0 233
+#define DMA2D_TASK_OUT_START_CH1 234
+#define DMA2D_TASK_OUT_START_CH2 235
+#define DMA2D_TASK_OUT_DSCR_READY_CH0 236
+#define DMA2D_TASK_OUT_DSCR_READY_CH1 237
+#define DMA2D_TASK_OUT_DSCR_READY_CH2 238
diff --git a/components/soc/esp32p4/include/soc/soc_pins.h b/components/soc/esp32p4/include/soc/soc_pins.h
new file mode 100644
index 0000000000..73842452c1
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/soc_pins.h
@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Pin definition header file. The long term plan is to have a single soc_pins.h for all
+ * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
+ * peripheral and include them here to avoid developing conflicts in those header files.
+ */
+
+#pragma once
+
+#include "soc/gpio_pins.h"
+#include "soc/spi_pins.h"
+#include "soc/sdmmc_pins.h"
diff --git a/components/soc/esp32p4/include/soc/spi_mem_reg.h b/components/soc/esp32p4/include/soc/spi_mem_reg.h
new file mode 100644
index 0000000000..3c58d02d89
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/spi_mem_reg.h
@@ -0,0 +1,3448 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_MEM_REG_H_
+#define _SOC_SPI_MEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_READ    (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
+bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WREN    (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when the bit is set. The
+ bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WRDI    (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
+e cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDID    (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered when the bit is
+ set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDSR    (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will be triggered when t
+he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
+ble..*/
+#define SPI_MEM_FLASH_WRSR    (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
+tion  will be triggered when the bit is set. The bit will be cleared once the op
+eration done .1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PP    (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_SE    (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
+ is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_BE    (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_CE    (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
+. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_DP    (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
+e or high performance mode and obtains the devices ID. The bit will be cleared o
+nce the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RES    (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
+ion done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_HPM    (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
+ion will be triggered when the bit is set. The bit will be cleared once the oper
+ation done.1: enable 0: disable..*/
+#define SPI_MEM_USR    (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode, it is set to indicate that program/erase operation will be trigger
+ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
+peration done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PE    (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
+te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
+ate, 6:write data state, 7: done state, 8: read data end state..*/
+#define SPI_MEM_SLV_ST    0x0000000F
+#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
+#define SPI_MEM_SLV_ST_V  0xF
+#define SPI_MEM_SLV_ST_S  4
+/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
+, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
+nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
+#define SPI_MEM_MST_ST    0x0000000F
+#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
+#define SPI_MEM_MST_ST_V  0xF
+#define SPI_MEM_MST_ST_S  0
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
+address, the bit24-bit31 are the byte length of a transfer..*/
+#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
+/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
+lways 1. 0: Others..*/
+#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
+/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
+s 1. 0: Others..*/
+#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_QIO    (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_DIO    (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
+isable..*/
+#define SPI_MEM_WRSR_2B    (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
+#define SPI_MEM_WP_REG    (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
+#define SPI_MEM_D_POL    (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
+#define SPI_MEM_Q_POL    (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
+spi_mem_flash_res bit. 1: enable 0: disable..*/
+#define SPI_MEM_RESANDRES    (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
+UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
+#define SPI_MEM_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
+e.*/
+#define SPI_MEM_TX_CRC_EN    (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
+e low..*/
+#define SPI_MEM_FCS_CRC_EN    (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_OCT    (BIT(9))
+#define SPI_MEM_FCMD_OCT_M  (BIT(9))
+#define SPI_MEM_FCMD_OCT_V  0x1
+#define SPI_MEM_FCMD_OCT_S  9
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
+#define SPI_MEM_FADDR_OCT    (BIT(6))
+#define SPI_MEM_FADDR_OCT_M  (BIT(6))
+#define SPI_MEM_FADDR_OCT_V  0x1
+#define SPI_MEM_FADDR_OCT_S  6
+/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
+#define SPI_MEM_FDIN_OCT    (BIT(5))
+#define SPI_MEM_FDIN_OCT_M  (BIT(5))
+#define SPI_MEM_FDIN_OCT_V  0x1
+#define SPI_MEM_FDIN_OCT_S  5
+/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
+#define SPI_MEM_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
+#define SPI_MEM_FDOUT_OCT_V  0x1
+#define SPI_MEM_FDOUT_OCT_S  4
+/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
+is output by the MSPI controller in the second half part of dummy phase. It is u
+sed to pre-drive flash..*/
+#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
+#define SPI_MEM_FDUMMY_WOUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_WOUT_V  0x1
+#define SPI_MEM_FDUMMY_WOUT_S  3
+/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
+s output by the MSPI controller in the first half part of dummy phase. It is use
+d to mask invalid SPI_DQS in the half part of dummy phase..*/
+#define SPI_MEM_FDUMMY_RIN    (BIT(2))
+#define SPI_MEM_FDUMMY_RIN_M  (BIT(2))
+#define SPI_MEM_FDUMMY_RIN_V  0x1
+#define SPI_MEM_FDUMMY_RIN_S  2
+/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_IO[7:0] is output by the MSPI controller..*/
+#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
+/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_DQS is output by the MSPI controller..*/
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
+/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+ send signals to AXI. Set this bit to reset these FIFO..*/
+#define SPI_MEM_TXFIFO_RST    (BIT(31))
+#define SPI_MEM_TXFIFO_RST_M  (BIT(31))
+#define SPI_MEM_TXFIFO_RST_V  0x1
+#define SPI_MEM_TXFIFO_RST_S  31
+/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+ receive signals from AXI.  Set this bit to reset these FIFO..*/
+#define SPI_MEM_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
+bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+in  tx_bus_fifo_l2..*/
+#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
+#define SPI_MEM_FAST_WRITE_EN_M  (BIT(29))
+#define SPI_MEM_FAST_WRITE_EN_V  0x1
+#define SPI_MEM_FAST_WRITE_EN_S  29
+/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
+the same time..*/
+#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
+#define SPI_MEM_DUAL_RAM_EN_M  (BIT(28))
+#define SPI_MEM_DUAL_RAM_EN_V  0x1
+#define SPI_MEM_DUAL_RAM_EN_S  28
+/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
+cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
+ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
+cessed at the same time..*/
+#define SPI_MEM_RAM0_EN    (BIT(27))
+#define SPI_MEM_RAM0_EN_M  (BIT(27))
+#define SPI_MEM_RAM0_EN_V  0x1
+#define SPI_MEM_RAM0_EN_S  27
+/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Write Splice-transfer..*/
+#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
+#define SPI_MEM_AW_SPLICE_EN_M  (BIT(26))
+#define SPI_MEM_AW_SPLICE_EN_V  0x1
+#define SPI_MEM_AW_SPLICE_EN_S  26
+/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Read Splice-transfer..*/
+#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
+#define SPI_MEM_AR_SPLICE_EN_M  (BIT(25))
+#define SPI_MEM_AR_SPLICE_EN_V  0x1
+#define SPI_MEM_AR_SPLICE_EN_S  25
+/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+ when there is a ECC error in AXI read data. The ECC error information is record
+ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
+#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
+#define SPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
+#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x1
+#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
+/* SPI_MEM_SPI_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
+eply AXI read data to AXI bus when all the read data is available..*/
+#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST    (BIT(23))
+#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_M  (BIT(23))
+#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_V  0x1
+#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_S  23
+/* SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
+#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
+#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V  0x1
+#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S  22
+/* SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
+y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
+#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
+#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V  0x1
+#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S  21
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
+12) SPI_CLK cycles..*/
+#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is alwasy on..*/
+#define SPI_MEM_CLK_MODE    0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
+/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
+#define SPI_MEM_SYNC_RESET    (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
+ clock cycles..*/
+#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
+fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
+whether there is an ECC region or not..*/
+#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
+#define SPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
+#define SPI_MEM_SPLIT_TRANS_EN_V  0x1
+#define SPI_MEM_SPLIT_TRANS_EN_S  24
+/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
+n accesses flash..*/
+#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
+/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */
+/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
+hen accesses flash..*/
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
+/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+ mode when accessed flash..*/
+#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
+th SPI_MEM_CS_HOLD bit..*/
+#define SPI_MEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
+M_CS_SETUP bit..*/
+#define SPI_MEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+ clock..*/
+#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_CLKCNT_N    0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_CLKCNT_H    0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_CLKCNT_L    0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation..*/
+#define SPI_MEM_USR_COMMAND    (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation..*/
+#define SPI_MEM_USR_ADDR    (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation..*/
+#define SPI_MEM_USR_DUMMY    (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation..*/
+#define SPI_MEM_USR_MISO    (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation..*/
+#define SPI_MEM_USR_MOSI    (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable..*/
+#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+1: enable 0: disable..*/
+#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
+: enable 0: disable..*/
+#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals..*/
+#define SPI_MEM_FWRITE_QIO    (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals..*/
+#define SPI_MEM_FWRITE_DIO    (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QUAD    (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DUAL    (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
+#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_SETUP    (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_HOLD    (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
+/*description: SPI0 USR_CMD read or write data byte length -1.*/
+#define SPI_MEM_USR_DBYTELEN    0x00000007
+#define SPI_MEM_USR_DBYTELEN_M  ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S))
+#define SPI_MEM_USR_DBYTELEN_V  0x7
+#define SPI_MEM_USR_DBYTELEN_S  6
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
+cle_num-1)..*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command..*/
+#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
+it..*/
+#define SPI_MEM_WB_MODE    0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
+#define SPI_MEM_STATUS    0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: SPI_CS line keep low when the bit is set..*/
+#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
+#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0,  sram is connected to SUBPINs..*/
+#define SPI_MEM_SSUB_PIN    (BIT(8))
+#define SPI_MEM_SSUB_PIN_M  (BIT(8))
+#define SPI_MEM_SSUB_PIN_V  0x1
+#define SPI_MEM_SSUB_PIN_S  8
+/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0,  flash is connected to SUBPINs..*/
+#define SPI_MEM_FSUB_PIN    (BIT(7))
+#define SPI_MEM_FSUB_PIN_M  (BIT(7))
+#define SPI_MEM_FSUB_PIN_V  0x1
+#define SPI_MEM_FSUB_PIN_S  7
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS1_DIS    (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS0_DIS    (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1, the value of crc32..*/
+#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
+/* SPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
+_ERR will be replied to BRESP/RRESP..*/
+#define SPI_MEM_SPI_CLOSE_AXI_INF_EN    (BIT(31))
+#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_M  (BIT(31))
+#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_V  0x1
+#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_S  31
+/* SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: Set this bit to check AXI read/write the same address region..*/
+#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
+#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x1
+#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_qio..*/
+#define SPI_MEM_FADDR_QUAD    (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
+e same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDOUT_QUAD    (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDIN_QUAD    (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_dio..*/
+#define SPI_MEM_FADDR_DUAL    (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+ same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDOUT_DUAL    (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDIN_DUAL    (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
+#define SPI_MEM_AXI_REQ_EN    (BIT(0))
+#define SPI_MEM_AXI_REQ_EN_M  (BIT(0))
+#define SPI_MEM_AXI_REQ_EN_V  0x1
+#define SPI_MEM_AXI_REQ_EN_S  0
+
+#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
+/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
+e. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
+/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: reserved.*/
+#define SPI_MEM_SRAM_OCT    (BIT(21))
+#define SPI_MEM_SRAM_OCT_M  (BIT(21))
+#define SPI_MEM_SRAM_OCT_V  0x1
+#define SPI_MEM_SRAM_OCT_S  21
+/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
+#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
+/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
+he register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
+#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
+/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
+. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
+/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
+nd..*/
+#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
+/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
+ operations..*/
+#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
+/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
+e operations..*/
+#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
+/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
+le.*/
+#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_V  0x1
+#define SPI_MEM_USR_SRAM_QIO_S  2
+/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
+le.*/
+#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_V  0x1
+#define SPI_MEM_USR_SRAM_DIO_S  1
+/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
+able, 0:disable..*/
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
+
+#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
+/* SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
+] are always 1. 0: Others..*/
+#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_S  31
+/* SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
+e always 1. 0: Others..*/
+#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_S  30
+/* SPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDOUT_HEX    (BIT(27))
+#define SPI_MEM_SDOUT_HEX_M  (BIT(27))
+#define SPI_MEM_SDOUT_HEX_V  0x1
+#define SPI_MEM_SDOUT_HEX_S  27
+/* SPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDIN_HEX    (BIT(26))
+#define SPI_MEM_SDIN_HEX_M  (BIT(26))
+#define SPI_MEM_SDIN_HEX_V  0x1
+#define SPI_MEM_SDIN_HEX_S  26
+/* SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_IO[7:0] is output by the MSPI controller..*/
+#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
+#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/* SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_DQS is output by the MSPI controller..*/
+#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
+#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
+the signal level of SPI bus is output by the MSPI controller..*/
+#define SPI_MEM_SDUMMY_WOUT    (BIT(23))
+#define SPI_MEM_SDUMMY_WOUT_M  (BIT(23))
+#define SPI_MEM_SDUMMY_WOUT_V  0x1
+#define SPI_MEM_SDUMMY_WOUT_S  23
+/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
+he signal level of SPI bus is output by the MSPI controller..*/
+#define SPI_MEM_SDUMMY_RIN    (BIT(22))
+#define SPI_MEM_SDUMMY_RIN_M  (BIT(22))
+#define SPI_MEM_SDUMMY_RIN_V  0x1
+#define SPI_MEM_SDUMMY_RIN_S  22
+/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SCMD_OCT    (BIT(21))
+#define SPI_MEM_SCMD_OCT_M  (BIT(21))
+#define SPI_MEM_SCMD_OCT_V  0x1
+#define SPI_MEM_SCMD_OCT_S  21
+/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SADDR_OCT    (BIT(20))
+#define SPI_MEM_SADDR_OCT_M  (BIT(20))
+#define SPI_MEM_SADDR_OCT_V  0x1
+#define SPI_MEM_SADDR_OCT_S  20
+/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDOUT_OCT    (BIT(19))
+#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
+#define SPI_MEM_SDOUT_OCT_V  0x1
+#define SPI_MEM_SDOUT_OCT_S  19
+/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDIN_OCT    (BIT(18))
+#define SPI_MEM_SDIN_OCT_M  (BIT(18))
+#define SPI_MEM_SDIN_OCT_V  0x1
+#define SPI_MEM_SDIN_OCT_S  18
+/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SCMD_QUAD    (BIT(17))
+#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
+#define SPI_MEM_SCMD_QUAD_V  0x1
+#define SPI_MEM_SCMD_QUAD_S  17
+/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SADDR_QUAD    (BIT(16))
+#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
+#define SPI_MEM_SADDR_QUAD_V  0x1
+#define SPI_MEM_SADDR_QUAD_S  16
+/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SDOUT_QUAD    (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_V  0x1
+#define SPI_MEM_SDOUT_QUAD_S  15
+/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SDIN_QUAD    (BIT(14))
+#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
+#define SPI_MEM_SDIN_QUAD_V  0x1
+#define SPI_MEM_SDIN_QUAD_S  14
+/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SADDR_DUAL    (BIT(12))
+#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
+#define SPI_MEM_SADDR_DUAL_V  0x1
+#define SPI_MEM_SADDR_DUAL_S  12
+/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SDOUT_DUAL    (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_V  0x1
+#define SPI_MEM_SDOUT_DUAL_S  11
+/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SDIN_DUAL    (BIT(10))
+#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
+#define SPI_MEM_SDIN_DUAL_V  0x1
+#define SPI_MEM_SDIN_DUAL_S  10
+/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */
+/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
+_mode bit..*/
+#define SPI_MEM_SWB_MODE    0x000000FF
+#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
+#define SPI_MEM_SWB_MODE_V  0xFF
+#define SPI_MEM_SWB_MODE_S  2
+/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on..*/
+#define SPI_MEM_SCLK_MODE    0x00000003
+#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
+#define SPI_MEM_SCLK_MODE_V  0x3
+#define SPI_MEM_SCLK_MODE_S  0
+
+#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
+ sram. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the read command value of command phase
+ for sram..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
+ The register value shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the write command value of command phas
+e for sram..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
+/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
+lk is divided from system clock..*/
+#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
+/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
+lk frequency is system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_SCLKCNT_N    0x000000FF
+#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
+#define SPI_MEM_SCLKCNT_N_V  0xFF
+#define SPI_MEM_SCLKCNT_N_S  16
+/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_SCLKCNT_H    0x000000FF
+#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
+#define SPI_MEM_SCLKCNT_H_V  0xFF
+#define SPI_MEM_SCLKCNT_H_S  8
+/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_SCLKCNT_L    0x000000FF
+#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
+#define SPI_MEM_SCLKCNT_L_V  0xFF
+#define SPI_MEM_SCLKCNT_L_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
+/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
+#define SPI_MEM_LOCK_DELAY_TIME    0x0000001F
+#define SPI_MEM_LOCK_DELAY_TIME_M  ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S))
+#define SPI_MEM_LOCK_DELAY_TIME_V  0x1F
+#define SPI_MEM_LOCK_DELAY_TIME_S  7
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF0    0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF1    0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF2    0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF3    0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF4    0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF5    0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF6    0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF7    0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF8    0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF9    0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF10    0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF11    0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF12    0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF13    0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF14    0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF15    0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: The command value to wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_CMD    0x0000FFFF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFFFF
+#define SPI_MEM_WAITI_CMD_S  16
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is
+ 8..*/
+#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
+#define SPI_MEM_WAITI_CMD_2B_M  (BIT(9))
+#define SPI_MEM_WAITI_CMD_2B_V  0x1
+#define SPI_MEM_WAITI_CMD_2B_S  9
+/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI
+_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+SPI_MEM_WAITI_ADDR_EN is cleared..*/
+#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S))
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x3
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
+/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out ad
+dress in RDSR or read SUS command transfer..*/
+#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
+#define SPI_MEM_WAITI_ADDR_EN_M  (BIT(2))
+#define SPI_MEM_WAITI_ADDR_EN_V  0x1
+#define SPI_MEM_WAITI_ADDR_EN_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when wait flash idle (RDSR).*/
+#define SPI_MEM_WAITI_DUMMY    (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
+ Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
+Suspend/Resume are not supported..*/
+#define SPI_MEM_WAITI_EN    (BIT(0))
+#define SPI_MEM_WAITI_EN_M  (BIT(0))
+#define SPI_MEM_WAITI_EN_V  0x1
+#define SPI_MEM_WAITI_EN_S  0
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
+/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
+/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
+ it will be treated as check pass..*/
+#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
+#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
+#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
+#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
+s of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PES_END_EN    (BIT(24))
+#define SPI_MEM_PES_END_EN_M  (BIT(24))
+#define SPI_MEM_PES_END_EN_V  0x1
+#define SPI_MEM_PES_END_EN_S  24
+/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
+ of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PER_END_EN    (BIT(23))
+#define SPI_MEM_PER_END_EN_M  (BIT(23))
+#define SPI_MEM_PER_END_EN_V  0x1
+#define SPI_MEM_PER_END_EN_S  23
+/* SPI_MEM_SPI_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
+hen check flash SUS/SUS1/SUS2 status bit.*/
+#define SPI_MEM_SPI_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI_MEM_SPI_FMEM_RD_SUS_2B_M  (BIT(22))
+#define SPI_MEM_SPI_FMEM_RD_SUS_2B_V  0x1
+#define SPI_MEM_SPI_FMEM_RD_SUS_2B_S  22
+/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
+/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
+2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
+#define SPI_MEM_PESR_END_MSK    0x0000FFFF
+#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
+#define SPI_MEM_PESR_END_MSK_V  0xFFFF
+#define SPI_MEM_PESR_END_MSK_S  6
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable Auto-suspending function..*/
+#define SPI_MEM_FLASH_PES_EN    (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
+pplication should send PER after PES is done..*/
+#define SPI_MEM_PES_PER_EN    (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase suspend command is sent. 0: SPI1 does not wait after program erase
+ suspend command is sent..*/
+#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase resume command is sent. 0: SPI1 does not wait after program erase
+resume command is sent..*/
+#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit, program erase suspend operation will be triggered whe
+n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+isable..*/
+#define SPI_MEM_FLASH_PES    (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit, program erase suspend operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: di
+sable..*/
+#define SPI_MEM_FLASH_PER    (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
+/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
+/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
+..*/
+#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
+#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */
+/*description: Program/Erase suspend command..*/
+#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFFFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */
+/*description: Program/Erase resume command..*/
+#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFFFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  16
+/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng
+th of Program/Erase Suspend/Resume command is 8..*/
+#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI_MEM_FLASH_PESR_CMD_2B_M  (BIT(15))
+#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x1
+#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
+/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
+#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_V  0x1
+#define SPI_MEM_SPI0_LOCK_EN_S  7
+/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
+#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_128_S  6
+/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
+#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_128_S  5
+/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
+mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+after DP command is sent..*/
+#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_128_S  4
+/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after RES command is sent..*/
+#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_128_S  3
+/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after HPM command is sent..*/
+#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_128_S  2
+/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
+#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
+#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend, only used in SPI1..*/
+#define SPI_MEM_FLASH_SUS    (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
+/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_ENA    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
+/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
+/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ENA_S  5
+/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ENA_S  4
+/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
+/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_V  0x1
+#define SPI_MEM_WPE_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
+/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
+/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
+/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
+#define SPI_MEM_ECC_ERR_INT_CLR_S  5
+/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_MST_ST_END_INT_CLR_S  4
+/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
+/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_V  0x1
+#define SPI_MEM_WPE_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
+/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+chip is loosing power and RTC module sends out brown out close flash request to
+SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ and MSPI returns to idle state. 0: Others..*/
+#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+ address is invalid by compared to MMU configuration. 0: Others..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
+ite flash request is received. 0: Others..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+address is invalid by compared to MMU configuration. 0: Others..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
+/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
+is rejected. 0: Others..*/
+#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
+/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
+et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
+ times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
+. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
+his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
+ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
+I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
+RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
+d, this bit will not be triggered..*/
+#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
+#define SPI_MEM_ECC_ERR_INT_RAW_S  5
+/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
+is changed from non idle state to idle state. 0: Others..*/
+#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_MST_ST_END_INT_RAW_S  4
+/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
+is changed from non idle state to idle state. It means that SPI_CS raises high.
+0: Others.*/
+#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
+/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
+E is sent and flash is already idle. 0: Others..*/
+#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_V  0x1
+#define SPI_MEM_WPE_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
+mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
+#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
+mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
+#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
+/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ST_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
+/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ST_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_ST_S  6
+/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ST_S  5
+/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ST_S  4
+/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ST_S  3
+/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_V  0x1
+#define SPI_MEM_WPE_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ST    (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ST    (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
+/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
+..*/
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_SPI_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S  26
+/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to flash..*/
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to flash..*/
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the panda device..*/
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_SPI_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S  1
+/* SPI_MEM_SPI_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define SPI_MEM_SPI_FMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_SPI_FMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_SPI_FMEM_DDR_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_EN_S  0
+
+#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD8)
+/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
+]}..*/
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
+, 1'b0}..*/
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_SPI_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S  26
+/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to external RAM..*/
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to external RAM..*/
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the DDR psram..*/
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_SPI_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S  1
+/* SPI_MEM_SPI_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define SPI_MEM_SPI_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_SPI_SMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_DDR_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_EN_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x100)
+/* SPI_MEM_SPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_FMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS0_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS0_ECC_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS0_ECC_S  2
+/* SPI_MEM_SPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_S  1
+/* SPI_MEM_SPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x104)
+/* SPI_MEM_SPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_FMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS1_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS1_ECC_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS1_ECC_S  2
+/* SPI_MEM_SPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_S  1
+/* SPI_MEM_SPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x108)
+/* SPI_MEM_SPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_FMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS2_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS2_ECC_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS2_ECC_S  2
+/* SPI_MEM_SPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_S  1
+/* SPI_MEM_SPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10C)
+/* SPI_MEM_SPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_FMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS3_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_FMEM_PMS3_ECC_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS3_ECC_S  2
+/* SPI_MEM_SPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_S  1
+/* SPI_MEM_SPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x110)
+/* SPI_MEM_SPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S))
+#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x114)
+/* SPI_MEM_SPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S))
+#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x118)
+/* SPI_MEM_SPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S))
+#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x11C)
+/* SPI_MEM_SPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */
+/*description: SPI1 flash PMS section $n start address value.*/
+#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S))
+#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x120)
+/* SPI_MEM_SPI_FMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_FMEM_PMS0_SIZE    0x00007FFF
+#define SPI_MEM_SPI_FMEM_PMS0_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS0_SIZE_S))
+#define SPI_MEM_SPI_FMEM_PMS0_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_FMEM_PMS0_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x124)
+/* SPI_MEM_SPI_FMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_FMEM_PMS1_SIZE    0x00007FFF
+#define SPI_MEM_SPI_FMEM_PMS1_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS1_SIZE_S))
+#define SPI_MEM_SPI_FMEM_PMS1_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_FMEM_PMS1_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x128)
+/* SPI_MEM_SPI_FMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_FMEM_PMS2_SIZE    0x00007FFF
+#define SPI_MEM_SPI_FMEM_PMS2_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS2_SIZE_S))
+#define SPI_MEM_SPI_FMEM_PMS2_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_FMEM_PMS2_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x12C)
+/* SPI_MEM_SPI_FMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_FMEM_PMS3_SIZE    0x00007FFF
+#define SPI_MEM_SPI_FMEM_PMS3_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS3_SIZE_S))
+#define SPI_MEM_SPI_FMEM_PMS3_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_FMEM_PMS3_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x130)
+/* SPI_MEM_SPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_SMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS0_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS0_ECC_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS0_ECC_S  2
+/* SPI_MEM_SPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_S  1
+/* SPI_MEM_SPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x134)
+/* SPI_MEM_SPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_SMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS1_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS1_ECC_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS1_ECC_S  2
+/* SPI_MEM_SPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_S  1
+/* SPI_MEM_SPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x138)
+/* SPI_MEM_SPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_SMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS2_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS2_ECC_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS2_ECC_S  2
+/* SPI_MEM_SPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_S  1
+/* SPI_MEM_SPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x13C)
+/* SPI_MEM_SPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SPI_SMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS3_ECC_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_PMS3_ECC_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS3_ECC_S  2
+/* SPI_MEM_SPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_S  1
+/* SPI_MEM_SPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_V  0x1
+#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x140)
+/* SPI_MEM_SPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S))
+#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x144)
+/* SPI_MEM_SPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S))
+#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x148)
+/* SPI_MEM_SPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S))
+#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14C)
+/* SPI_MEM_SPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */
+/*description: SPI1 external RAM PMS section $n start address value.*/
+#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S    0x07FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S))
+#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V  0x7FFFFFF
+#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x150)
+/* SPI_MEM_SPI_SMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_SMEM_PMS0_SIZE    0x00007FFF
+#define SPI_MEM_SPI_SMEM_PMS0_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS0_SIZE_S))
+#define SPI_MEM_SPI_SMEM_PMS0_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_SMEM_PMS0_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x154)
+/* SPI_MEM_SPI_SMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_SMEM_PMS1_SIZE    0x00007FFF
+#define SPI_MEM_SPI_SMEM_PMS1_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS1_SIZE_S))
+#define SPI_MEM_SPI_SMEM_PMS1_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_SMEM_PMS1_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x158)
+/* SPI_MEM_SPI_SMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_SMEM_PMS2_SIZE    0x00007FFF
+#define SPI_MEM_SPI_SMEM_PMS2_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS2_SIZE_S))
+#define SPI_MEM_SPI_SMEM_PMS2_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_SMEM_PMS2_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x15C)
+/* SPI_MEM_SPI_SMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
+/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SPI_SMEM_PMS3_SIZE    0x00007FFF
+#define SPI_MEM_SPI_SMEM_PMS3_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS3_SIZE_S))
+#define SPI_MEM_SPI_SMEM_PMS3_SIZE_V  0x7FFF
+#define SPI_MEM_SPI_SMEM_PMS3_SIZE_S  0
+
+#define SPI_MEM_PMS_REJECT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x164)
+/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
+/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+ error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_IVD    (BIT(31))
+#define SPI_MEM_PMS_IVD_M  (BIT(31))
+#define SPI_MEM_PMS_IVD_V  0x1
+#define SPI_MEM_PMS_IVD_S  31
+/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
+ is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
+#define SPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
+#define SPI_MEM_PMS_MULTI_HIT_V  0x1
+#define SPI_MEM_PMS_MULTI_HIT_S  30
+/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_ST    (BIT(29))
+#define SPI_MEM_PMS_ST_M  (BIT(29))
+#define SPI_MEM_PMS_ST_V  0x1
+#define SPI_MEM_PMS_ST_S  29
+/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
+_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_LD    (BIT(28))
+#define SPI_MEM_PMS_LD_M  (BIT(28))
+#define SPI_MEM_PMS_LD_V  0x1
+#define SPI_MEM_PMS_LD_S  28
+/* SPI_MEM_PM_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
+#define SPI_MEM_PM_EN    (BIT(27))
+#define SPI_MEM_PM_EN_M  (BIT(27))
+#define SPI_MEM_PM_EN_V  0x1
+#define SPI_MEM_PM_EN_S  27
+/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_REJECT_ADDR    0x07FFFFFF
+#define SPI_MEM_REJECT_ADDR_M  ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S))
+#define SPI_MEM_REJECT_ADDR_V  0x7FFFFFF
+#define SPI_MEM_REJECT_ADDR_S  0
+
+#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x168)
+/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */
+/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
+ to byte 0 bit 0 to byte 15 bit 7).*/
+#define SPI_MEM_ECC_ERR_BITS    0x0000007F
+#define SPI_MEM_ECC_ERR_BITS_M  ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S))
+#define SPI_MEM_ECC_ERR_BITS_V  0x7F
+#define SPI_MEM_ECC_ERR_BITS_S  25
+/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
+ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
+R record the first ECC error information..*/
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
+#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
+#define SPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
+#define SPI_MEM_USR_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_USR_ECC_ADDR_EN_S  21
+/* SPI_MEM_SPI_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
+is bit should be 0. Otherwise, this bit should be 1..*/
+#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_M  (BIT(20))
+#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_S  20
+/* SPI_MEM_SPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+1024 bytes. 3: 2048 bytes..*/
+#define SPI_MEM_SPI_FMEM_PAGE_SIZE    0x00000003
+#define SPI_MEM_SPI_FMEM_PAGE_SIZE_M  ((SPI_MEM_SPI_FMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_FMEM_PAGE_SIZE_S))
+#define SPI_MEM_SPI_FMEM_PAGE_SIZE_V  0x3
+#define SPI_MEM_SPI_FMEM_PAGE_SIZE_S  18
+/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
+h..*/
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S  17
+/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */
+/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
+upt..*/
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM    0x0000003F
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S))
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V  0x3F
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S  11
+/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[10:5] ;default: 6'd0 ; */
+/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define SPI_MEM_ECC_ERR_CNT    0x0000003F
+#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
+#define SPI_MEM_ECC_ERR_CNT_V  0x3F
+#define SPI_MEM_ECC_ERR_CNT_S  5
+
+#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x16C)
+/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define SPI_MEM_ECC_ERR_ADDR    0x07FFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
+#define SPI_MEM_ECC_ERR_ADDR_V  0x7FFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_S  0
+
+#define SPI_MEM_AXI_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x170)
+/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
+ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
+H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
+#define SPI_MEM_AXI_ERR_ADDR    0x07FFFFFF
+#define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
+#define SPI_MEM_AXI_ERR_ADDR_V  0x7FFFFFF
+#define SPI_MEM_AXI_ERR_ADDR_S  0
+
+#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x174)
+/* SPI_MEM_SPI_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
+ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
+#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_M  (BIT(20))
+#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_S  20
+/* SPI_MEM_SPI_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */
+/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
+es. 2: 1024 bytes. 3: 2048 bytes..*/
+#define SPI_MEM_SPI_SMEM_PAGE_SIZE    0x00000003
+#define SPI_MEM_SPI_SMEM_PAGE_SIZE_M  ((SPI_MEM_SPI_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_SMEM_PAGE_SIZE_S))
+#define SPI_MEM_SPI_SMEM_PAGE_SIZE_V  0x3
+#define SPI_MEM_SPI_SMEM_PAGE_SIZE_S  18
+/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
+rnal RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S  17
+
+#define SPI_MEM_SPI_SMEM_AXI_ADDR_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x178)
+/* SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
+and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
+#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
+#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
+#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+/* SPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M  (BIT(30))
+#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S  30
+/* SPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY    (BIT(29))
+#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_M  (BIT(29))
+#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_S  29
+/* SPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
+/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY    (BIT(28))
+#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_M  (BIT(28))
+#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_S  28
+/* SPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY    (BIT(27))
+#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_M  (BIT(27))
+#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_S  27
+/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+ and SPI0 transfers are done. 0: Others..*/
+#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
+#define SPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
+#define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
+#define SPI_MEM_ALL_FIFO_EMPTY_S  26
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x180)
+/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
+#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
+#define SPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
+#define SPI_MEM_TIMING_CALI_UPDATE_V  0x1
+#define SPI_MEM_TIMING_CALI_UPDATE_S  6
+/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
+lash..*/
+#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
+#define SPI_MEM_DLL_TIMING_CALI_V  0x1
+#define SPI_MEM_DLL_TIMING_CALI_S  5
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
+#define SPI_MEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations..*/
+#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x184)
+/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DINS_MODE    0x00000007
+#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
+#define SPI_MEM_DINS_MODE_V  0x7
+#define SPI_MEM_DINS_MODE_S  24
+/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN7_MODE    0x00000007
+#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
+#define SPI_MEM_DIN7_MODE_V  0x7
+#define SPI_MEM_DIN7_MODE_S  21
+/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN6_MODE    0x00000007
+#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
+#define SPI_MEM_DIN6_MODE_V  0x7
+#define SPI_MEM_DIN6_MODE_S  18
+/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN5_MODE    0x00000007
+#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
+#define SPI_MEM_DIN5_MODE_V  0x7
+#define SPI_MEM_DIN5_MODE_S  15
+/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN4_MODE    0x00000007
+#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
+#define SPI_MEM_DIN4_MODE_V  0x7
+#define SPI_MEM_DIN4_MODE_S  12
+/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN3_MODE    0x00000007
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x7
+#define SPI_MEM_DIN3_MODE_S  9
+/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN2_MODE    0x00000007
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x7
+#define SPI_MEM_DIN2_MODE_S  6
+/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN1_MODE    0x00000007
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x7
+#define SPI_MEM_DIN1_MODE_S  3
+/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN0_MODE    0x00000007
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x7
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x188)
+/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DINS_NUM    0x00000003
+#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
+#define SPI_MEM_DINS_NUM_V  0x3
+#define SPI_MEM_DINS_NUM_S  16
+/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN7_NUM    0x00000003
+#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
+#define SPI_MEM_DIN7_NUM_V  0x3
+#define SPI_MEM_DIN7_NUM_S  14
+/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN6_NUM    0x00000003
+#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
+#define SPI_MEM_DIN6_NUM_V  0x3
+#define SPI_MEM_DIN6_NUM_S  12
+/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN5_NUM    0x00000003
+#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
+#define SPI_MEM_DIN5_NUM_V  0x3
+#define SPI_MEM_DIN5_NUM_S  10
+/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN4_NUM    0x00000003
+#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
+#define SPI_MEM_DIN4_NUM_V  0x3
+#define SPI_MEM_DIN4_NUM_S  8
+/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN3_NUM    0x00000003
+#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
+#define SPI_MEM_DIN3_NUM_V  0x3
+#define SPI_MEM_DIN3_NUM_S  6
+/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN2_NUM    0x00000003
+#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
+#define SPI_MEM_DIN2_NUM_V  0x3
+#define SPI_MEM_DIN2_NUM_S  4
+/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN1_NUM    0x00000003
+#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
+#define SPI_MEM_DIN1_NUM_V  0x3
+#define SPI_MEM_DIN1_NUM_S  2
+/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN0_NUM    0x00000003
+#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
+#define SPI_MEM_DIN0_NUM_V  0x3
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18C)
+/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_DOUTS_MODE_S  8
+/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_DOUT7_MODE_S  7
+/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_DOUT6_MODE_S  6
+/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_DOUT5_MODE_S  5
+/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_DOUT4_MODE_S  4
+/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x190)
+/* SPI_MEM_SPI_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
+XT_RAM..*/
+#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_M  (BIT(5))
+#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_V  0x1
+#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_S  5
+/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_SPI_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
+ations..*/
+#define SPI_MEM_SPI_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_V  0x1
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_S  1
+/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
+ns..*/
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x194)
+/* SPI_MEM_SPI_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DINS_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DINS_MODE_M  ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S))
+#define SPI_MEM_SPI_SMEM_DINS_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DINS_MODE_S  24
+/* SPI_MEM_SPI_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN7_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN7_MODE_M  ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN7_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN7_MODE_S  21
+/* SPI_MEM_SPI_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN6_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN6_MODE_M  ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN6_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN6_MODE_S  18
+/* SPI_MEM_SPI_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN5_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN5_MODE_M  ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN5_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN5_MODE_S  15
+/* SPI_MEM_SPI_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN4_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN4_MODE_M  ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN4_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN4_MODE_S  12
+/* SPI_MEM_SPI_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN3_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN3_MODE_M  ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN3_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN3_MODE_S  9
+/* SPI_MEM_SPI_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN2_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN2_MODE_M  ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN2_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN2_MODE_S  6
+/* SPI_MEM_SPI_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN1_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN1_MODE_M  ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN1_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN1_MODE_S  3
+/* SPI_MEM_SPI_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN0_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN0_MODE_M  ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN0_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x198)
+/* SPI_MEM_SPI_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DINS_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DINS_NUM_M  ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S))
+#define SPI_MEM_SPI_SMEM_DINS_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DINS_NUM_S  16
+/* SPI_MEM_SPI_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN7_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN7_NUM_M  ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN7_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN7_NUM_S  14
+/* SPI_MEM_SPI_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN6_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN6_NUM_M  ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN6_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN6_NUM_S  12
+/* SPI_MEM_SPI_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN5_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN5_NUM_M  ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN5_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN5_NUM_S  10
+/* SPI_MEM_SPI_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN4_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN4_NUM_M  ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN4_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN4_NUM_S  8
+/* SPI_MEM_SPI_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN3_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN3_NUM_M  ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN3_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN3_NUM_S  6
+/* SPI_MEM_SPI_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN2_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN2_NUM_M  ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN2_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN2_NUM_S  4
+/* SPI_MEM_SPI_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN1_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN1_NUM_M  ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN1_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN1_NUM_S  2
+/* SPI_MEM_SPI_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN0_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN0_NUM_M  ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN0_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN0_NUM_S  0
+
+#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x19C)
+/* SPI_MEM_SPI_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S  8
+/* SPI_MEM_SPI_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S  7
+/* SPI_MEM_SPI_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S  6
+/* SPI_MEM_SPI_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S  5
+/* SPI_MEM_SPI_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S  4
+/* SPI_MEM_SPI_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S  3
+/* SPI_MEM_SPI_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S  2
+/* SPI_MEM_SPI_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S  1
+/* SPI_MEM_SPI_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A0)
+/* SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+ transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
+er whether there is an ECC region or not..*/
+#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
+#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_S  31
+/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
+SPI core clock cycles..*/
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
+n accesses external RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
+/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
+en accesses external RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
+ycles in ECC mode when accessed external RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S  12
+/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */
+/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
+re combined with spi_mem_cs_hold bit..*/
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S  7
+/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
+/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
+pi_mem_cs_setup bit..*/
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S))
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S  2
+/* SPI_MEM_SPI_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
+le..*/
+#define SPI_MEM_SPI_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_V  0x1
+#define SPI_MEM_SPI_SMEM_CS_HOLD_S  1
+/* SPI_MEM_SPI_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
+isable..*/
+#define SPI_MEM_SPI_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_SPI_SMEM_CS_SETUP_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_CS_SETUP_V  0x1
+#define SPI_MEM_SPI_SMEM_CS_SETUP_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_HEX_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A4)
+/* SPI_MEM_SPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_M  ((SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S))
+#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S  24
+/* SPI_MEM_SPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN15_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN15_MODE_M  ((SPI_MEM_SPI_SMEM_DIN15_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN15_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN15_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN15_MODE_S  21
+/* SPI_MEM_SPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN14_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN14_MODE_M  ((SPI_MEM_SPI_SMEM_DIN14_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN14_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN14_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN14_MODE_S  18
+/* SPI_MEM_SPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN13_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN13_MODE_M  ((SPI_MEM_SPI_SMEM_DIN13_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN13_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN13_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN13_MODE_S  15
+/* SPI_MEM_SPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN12_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN12_MODE_M  ((SPI_MEM_SPI_SMEM_DIN12_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN12_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN12_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN12_MODE_S  12
+/* SPI_MEM_SPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN11_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN11_MODE_M  ((SPI_MEM_SPI_SMEM_DIN11_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN11_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN11_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN11_MODE_S  9
+/* SPI_MEM_SPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN10_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN10_MODE_M  ((SPI_MEM_SPI_SMEM_DIN10_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN10_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN10_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN10_MODE_S  6
+/* SPI_MEM_SPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN09_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN09_MODE_M  ((SPI_MEM_SPI_SMEM_DIN09_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN09_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN09_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN09_MODE_S  3
+/* SPI_MEM_SPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DIN08_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN08_MODE_M  ((SPI_MEM_SPI_SMEM_DIN08_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN08_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN08_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN08_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_HEX_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A8)
+/* SPI_MEM_SPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_M  ((SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S))
+#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S  16
+/* SPI_MEM_SPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN15_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN15_NUM_M  ((SPI_MEM_SPI_SMEM_DIN15_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN15_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN15_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN15_NUM_S  14
+/* SPI_MEM_SPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN14_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN14_NUM_M  ((SPI_MEM_SPI_SMEM_DIN14_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN14_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN14_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN14_NUM_S  12
+/* SPI_MEM_SPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN13_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN13_NUM_M  ((SPI_MEM_SPI_SMEM_DIN13_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN13_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN13_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN13_NUM_S  10
+/* SPI_MEM_SPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN12_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN12_NUM_M  ((SPI_MEM_SPI_SMEM_DIN12_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN12_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN12_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN12_NUM_S  8
+/* SPI_MEM_SPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN11_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN11_NUM_M  ((SPI_MEM_SPI_SMEM_DIN11_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN11_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN11_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN11_NUM_S  6
+/* SPI_MEM_SPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN10_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN10_NUM_M  ((SPI_MEM_SPI_SMEM_DIN10_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN10_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN10_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN10_NUM_S  4
+/* SPI_MEM_SPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN09_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN09_NUM_M  ((SPI_MEM_SPI_SMEM_DIN09_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN09_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN09_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN09_NUM_S  2
+/* SPI_MEM_SPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SPI_SMEM_DIN08_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN08_NUM_M  ((SPI_MEM_SPI_SMEM_DIN08_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN08_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN08_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN08_NUM_S  0
+
+#define SPI_MEM_SPI_SMEM_DOUT_HEX_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1AC)
+/* SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE    (BIT(8))
+#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_M  (BIT(8))
+#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_S  8
+/* SPI_MEM_SPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT15_MODE    (BIT(7))
+#define SPI_MEM_SPI_SMEM_DOUT15_MODE_M  (BIT(7))
+#define SPI_MEM_SPI_SMEM_DOUT15_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT15_MODE_S  7
+/* SPI_MEM_SPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT14_MODE    (BIT(6))
+#define SPI_MEM_SPI_SMEM_DOUT14_MODE_M  (BIT(6))
+#define SPI_MEM_SPI_SMEM_DOUT14_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT14_MODE_S  6
+/* SPI_MEM_SPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT13_MODE    (BIT(5))
+#define SPI_MEM_SPI_SMEM_DOUT13_MODE_M  (BIT(5))
+#define SPI_MEM_SPI_SMEM_DOUT13_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT13_MODE_S  5
+/* SPI_MEM_SPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT12_MODE    (BIT(4))
+#define SPI_MEM_SPI_SMEM_DOUT12_MODE_M  (BIT(4))
+#define SPI_MEM_SPI_SMEM_DOUT12_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT12_MODE_S  4
+/* SPI_MEM_SPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT11_MODE    (BIT(3))
+#define SPI_MEM_SPI_SMEM_DOUT11_MODE_M  (BIT(3))
+#define SPI_MEM_SPI_SMEM_DOUT11_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT11_MODE_S  3
+/* SPI_MEM_SPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT10_MODE    (BIT(2))
+#define SPI_MEM_SPI_SMEM_DOUT10_MODE_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_DOUT10_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT10_MODE_S  2
+/* SPI_MEM_SPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT09_MODE    (BIT(1))
+#define SPI_MEM_SPI_SMEM_DOUT09_MODE_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_DOUT09_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT09_MODE_S  1
+/* SPI_MEM_SPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SPI_SMEM_DOUT08_MODE    (BIT(0))
+#define SPI_MEM_SPI_SMEM_DOUT08_MODE_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_DOUT08_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT08_MODE_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x200)
+/* SPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
+#define SPI_MEM_SPI_CLK_EN    (BIT(0))
+#define SPI_MEM_SPI_CLK_EN_M  (BIT(0))
+#define SPI_MEM_SPI_CLK_EN_V  0x1
+#define SPI_MEM_SPI_CLK_EN_S  0
+
+#define SPI_MEM_XTS_PLAIN_BASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x300)
+/* SPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This field is only used to generate include file in c case. This field is useles
+s. Please do not use this field..*/
+#define SPI_MEM_SPI_XTS_PLAIN    0xFFFFFFFF
+#define SPI_MEM_SPI_XTS_PLAIN_M  ((SPI_MEM_SPI_XTS_PLAIN_V)<<(SPI_MEM_SPI_XTS_PLAIN_S))
+#define SPI_MEM_SPI_XTS_PLAIN_V  0xFFFFFFFF
+#define SPI_MEM_SPI_XTS_PLAIN_S  0
+
+#define SPI_MEM_XTS_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
+/* SPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the line-size parameter which will be used in manual encryption
+ calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
+ 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
+#define SPI_MEM_SPI_XTS_LINESIZE    0x00000003
+#define SPI_MEM_SPI_XTS_LINESIZE_M  ((SPI_MEM_SPI_XTS_LINESIZE_V)<<(SPI_MEM_SPI_XTS_LINESIZE_S))
+#define SPI_MEM_SPI_XTS_LINESIZE_V  0x3
+#define SPI_MEM_SPI_XTS_LINESIZE_S  0
+
+#define SPI_MEM_XTS_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
+/* SPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit stores the destination parameter which will be used in manual encryptio
+n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
+used..*/
+#define SPI_MEM_SPI_XTS_DESTINATION    (BIT(0))
+#define SPI_MEM_SPI_XTS_DESTINATION_M  (BIT(0))
+#define SPI_MEM_SPI_XTS_DESTINATION_V  0x1
+#define SPI_MEM_SPI_XTS_DESTINATION_S  0
+
+#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
+/* SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits stores the physical-address parameter which will be used in manual enc
+ryption calculation. This value should aligned with byte number decided by line-
+size parameter..*/
+#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFF
+#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M  ((SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S))
+#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V  0x3FFFFFF
+#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S  0
+
+#define SPI_MEM_XTS_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
+/* SPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to trigger the process of manual encryption calculation. This actio
+n should only be asserted when manual encryption status is 0. After this action,
+ manual encryption status becomes 1. After calculation is done, manual encryptio
+n status becomes 2..*/
+#define SPI_MEM_SPI_XTS_TRIGGER    (BIT(0))
+#define SPI_MEM_SPI_XTS_TRIGGER_M  (BIT(0))
+#define SPI_MEM_SPI_XTS_TRIGGER_V  0x1
+#define SPI_MEM_SPI_XTS_TRIGGER_S  0
+
+#define SPI_MEM_XTS_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
+/* SPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to release encrypted result to mspi. This action should only be ass
+erted when manual encryption status is 2. After this action, manual encryption s
+tatus will become 3..*/
+#define SPI_MEM_SPI_XTS_RELEASE    (BIT(0))
+#define SPI_MEM_SPI_XTS_RELEASE_M  (BIT(0))
+#define SPI_MEM_SPI_XTS_RELEASE_V  0x1
+#define SPI_MEM_SPI_XTS_RELEASE_S  0
+
+#define SPI_MEM_XTS_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
+/* SPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
+en manual encryption status is 3. After this action, manual encryption status wi
+ll become 0..*/
+#define SPI_MEM_SPI_XTS_DESTROY    (BIT(0))
+#define SPI_MEM_SPI_XTS_DESTROY_M  (BIT(0))
+#define SPI_MEM_SPI_XTS_DESTROY_V  0x1
+#define SPI_MEM_SPI_XTS_DESTROY_S  0
+
+#define SPI_MEM_XTS_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
+/* SPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+ calculation, 2: encryption calculation is done but the encrypted result is invi
+sible to mspi, 3: the encrypted result is visible to mspi..*/
+#define SPI_MEM_SPI_XTS_STATE    0x00000003
+#define SPI_MEM_SPI_XTS_STATE_M  ((SPI_MEM_SPI_XTS_STATE_V)<<(SPI_MEM_SPI_XTS_STATE_S))
+#define SPI_MEM_SPI_XTS_STATE_V  0x3
+#define SPI_MEM_SPI_XTS_STATE_S  0
+
+#define SPI_MEM_XTS_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
+/* SPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
+/*description: This bits stores the last modified-time of manual encryption feature..*/
+#define SPI_MEM_SPI_XTS_DATE    0x3FFFFFFF
+#define SPI_MEM_SPI_XTS_DATE_M  ((SPI_MEM_SPI_XTS_DATE_V)<<(SPI_MEM_SPI_XTS_DATE_S))
+#define SPI_MEM_SPI_XTS_DATE_V  0x3FFFFFFF
+#define SPI_MEM_SPI_XTS_DATE_S  0
+
+#define SPI_MEM_MMU_ITEM_CONTENT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x37C)
+/* SPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: MSPI-MMU item content.*/
+#define SPI_MEM_SPI_MMU_ITEM_CONTENT    0xFFFFFFFF
+#define SPI_MEM_SPI_MMU_ITEM_CONTENT_M  ((SPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(SPI_MEM_SPI_MMU_ITEM_CONTENT_S))
+#define SPI_MEM_SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFF
+#define SPI_MEM_SPI_MMU_ITEM_CONTENT_S  0
+
+#define SPI_MEM_MMU_ITEM_INDEX_REG(i)          (REG_SPI_MEM_BASE(i) + 0x380)
+/* SPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: MSPI-MMU item index.*/
+#define SPI_MEM_SPI_MMU_ITEM_INDEX    0xFFFFFFFF
+#define SPI_MEM_SPI_MMU_ITEM_INDEX_M  ((SPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(SPI_MEM_SPI_MMU_ITEM_INDEX_S))
+#define SPI_MEM_SPI_MMU_ITEM_INDEX_V  0xFFFFFFFF
+#define SPI_MEM_SPI_MMU_ITEM_INDEX_S  0
+
+#define SPI_MEM_MMU_POWER_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x384)
+/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
+#define SPI_MEM_RDN_RESULT    (BIT(31))
+#define SPI_MEM_RDN_RESULT_M  (BIT(31))
+#define SPI_MEM_RDN_RESULT_V  0x1
+#define SPI_MEM_RDN_RESULT_S  31
+/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: ECO register enable bit.*/
+#define SPI_MEM_RDN_ENA    (BIT(30))
+#define SPI_MEM_RDN_ENA_M  (BIT(30))
+#define SPI_MEM_RDN_ENA_V  0x1
+#define SPI_MEM_RDN_ENA_S  30
+/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */
+/*description: MMU PSRAM aux control register.*/
+#define SPI_MEM_AUX_CTRL    0x00003FFF
+#define SPI_MEM_AUX_CTRL_M  ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S))
+#define SPI_MEM_AUX_CTRL_V  0x3FFF
+#define SPI_MEM_AUX_CTRL_S  16
+/* SPI_MEM_SPI_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
+/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/
+#define SPI_MEM_SPI_MMU_PAGE_SIZE    0x00000003
+#define SPI_MEM_SPI_MMU_PAGE_SIZE_M  ((SPI_MEM_SPI_MMU_PAGE_SIZE_V)<<(SPI_MEM_SPI_MMU_PAGE_SIZE_S))
+#define SPI_MEM_SPI_MMU_PAGE_SIZE_V  0x3
+#define SPI_MEM_SPI_MMU_PAGE_SIZE_S  3
+/* SPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
+ controlled by rtc..*/
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PU    (BIT(2))
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_V  0x1
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_S  2
+/* SPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to force mmu-memory powerdown.*/
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PD    (BIT(1))
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_V  0x1
+#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_S  1
+/* SPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable mmu-memory clock force on.*/
+#define SPI_MEM_SPI_MMU_MEM_FORCE_ON    (BIT(0))
+#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_V  0x1
+#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_S  0
+
+#define SPI_MEM_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
+/* SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
+T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
+#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
+#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V  0x1
+#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S  4
+/* SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
+ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
+ing key 1..*/
+#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
+#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V  0x1
+#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S  3
+/* SPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
+7: The bigger the number is, the more secure the cryption is. (Note that the per
+formance of cryption will decrease together with this number increasing).*/
+#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL    0x00000007
+#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M  ((SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S))
+#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V  0x7
+#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S  0
+
+#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F0)
+/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO high register.*/
+#define SPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_HIGH_M  ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
+#define SPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_HIGH_S  0
+
+#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F4)
+/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO low register.*/
+#define SPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_LOW_M  ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S))
+#define SPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_LOW_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2212091 ; */
+/*description: SPI0 register version..*/
+#define SPI_MEM_DATE    0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/spi_mem_struct.h b/components/soc/esp32p4/include/soc/spi_mem_struct.h
new file mode 100644
index 0000000000..888ad4e031
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/spi_mem_struct.h
@@ -0,0 +1,1139 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
+            uint32_t slv_st                        :    4;  /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
+            uint32_t reserved8                     :    9;  /*reserved*/
+            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t usr                           :    1;  /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
+            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/
+            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/
+            uint32_t fdummy_rin                    :    1;  /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/
+            uint32_t fdummy_wout                   :    1;  /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/
+            uint32_t fdout_oct                     :    1;  /*Apply 8 signals during write-data phase 1:enable 0: disable*/
+            uint32_t fdin_oct                      :    1;  /*Apply 8 signals during read-data phase 1:enable 0: disable*/
+            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during address phase 1:enable 0: disable*/
+            uint32_t reserved7                     :    1;  /*reserved*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable*/
+            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
+            uint32_t reserved16                    :    2;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
+            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
+            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t reserved25                    :    5;  /*reserved*/
+            uint32_t dqs_ie_always_on              :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
+            uint32_t data_ie_always_on             :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
+            uint32_t reserved2                     :    9;  /*reserved*/
+            uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
+            uint32_t reg_aw_size0_1_support_en     :    1;  /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/
+            uint32_t reg_axi_rdata_back_fast       :    1;  /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/
+            uint32_t rresp_ecc_err_en              :    1;  /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/
+            uint32_t ar_splice_en                  :    1;  /*Set this bit to enable AXI Read Splice-transfer.*/
+            uint32_t aw_splice_en                  :    1;  /*Set this bit to enable AXI Write Splice-transfer.*/
+            uint32_t ram0_en                       :    1;  /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
+            uint32_t dual_ram_en                   :    1;  /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
+            uint32_t fast_write_en                 :    1;  /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.*/
+            uint32_t rxfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.*/
+            uint32_t txfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/
+            uint32_t cs_hold_time                  :    5;  /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/
+            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/
+            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
+            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
+            uint32_t reserved15                    :    9;  /*reserved*/
+            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset                    :    1;  /*The spi0_mst_st and spi0_slv_st will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
+            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
+            uint32_t clk_equ_sysclk                :    1;  /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t ck_out_edge                   :    1;  /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16                    :    8;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t usr_dbytelen                  :    3;  /*SPI0 USR_CMD read or write data byte length -1*/
+            uint32_t reserved9                     :    17;  /*reserved*/
+            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t reserved_30;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t reserved0                     :    5;  /*reserved*/
+            uint32_t fsub_pin                      :    1;  /*For SPI0,  flash is connected to SUBPINs.*/
+            uint32_t ssub_pin                      :    1;  /*For SPI0,  sram is connected to SUBPINs.*/
+            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle     0: spi clk line is low when idle */
+            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;
+    union {
+        struct {
+            uint32_t axi_req_en                    :    1;  /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
+            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
+            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
+            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9                     :    21;  /*reserved*/
+            uint32_t reg_same_aw_ar_addr_chk_en    :    1;  /*Set this bit to check AXI read/write the same address region.*/
+            uint32_t reg_close_axi_inf_en          :    1;  /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    union {
+        struct {
+            uint32_t usr_saddr_4byte               :    1;  /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
+            uint32_t usr_sram_dio                  :    1;  /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
+            uint32_t usr_sram_qio                  :    1;  /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
+            uint32_t usr_wr_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
+            uint32_t usr_rd_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
+            uint32_t sram_usr_rcmd                 :    1;  /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
+            uint32_t sram_rdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved12                    :    2;  /*reserved*/
+            uint32_t sram_addr_bitlen              :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
+            uint32_t sram_usr_wcmd                 :    1;  /*For SPI0, In the external RAM mode cache write sram for user define command*/
+            uint32_t sram_oct                      :    1;  /*reserved*/
+            uint32_t sram_wdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_sctrl;
+    union {
+        struct {
+            uint32_t sclk_mode                     :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+            uint32_t swb_mode                      :    8;  /*Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t sdin_dual                     :    1;  /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t sdout_dual                    :    1;  /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t saddr_dual                    :    1;  /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t reserved13                    :    1;  /*reserved*/
+            uint32_t sdin_quad                     :    1;  /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t sdout_quad                    :    1;  /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t saddr_quad                    :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t scmd_quad                     :    1;  /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t sdin_oct                      :    1;  /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t sdout_oct                     :    1;  /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t saddr_oct                     :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t scmd_oct                      :    1;  /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t sdummy_rin                    :    1;  /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
+            uint32_t sdummy_wout                   :    1;  /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
+            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/
+            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/
+            uint32_t sdin_hex                      :    1;  /*For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. */
+            uint32_t sdout_hex                     :    1;  /*For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. */
+            uint32_t reserved28                    :    2;  /*reserved*/
+            uint32_t dqs_ie_always_on              :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
+            uint32_t data_ie_always_on             :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
+        };
+        uint32_t val;
+    } sram_cmd;
+    union {
+        struct {
+            uint32_t sram_usr_rd_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t sram_usr_rd_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_drd_cmd;
+    union {
+        struct {
+            uint32_t usr_wr_cmd_value              :    16;  /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_wr_cmd_bitlen             :    4;  /*For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_dwr_cmd;
+    union {
+        struct {
+            uint32_t cnt_l                         :    8;  /*For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.*/
+            uint32_t cnt_h                         :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t cnt_n                         :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*reserved*/
+            uint32_t equ_sysclk                    :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
+        };
+        uint32_t val;
+    } sram_clk;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;  /*reserved*/
+            uint32_t lock_delay_time               :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];
+    union {
+        struct {
+            uint32_t waiti_en                      :    1;  /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/
+            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
+            uint32_t waiti_addr_en                 :    1;  /*1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/
+            uint32_t waiti_addr_cyclelen           :    2;  /*When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/
+            uint32_t reserved5                     :    4;  /*reserved*/
+            uint32_t waiti_cmd_2b                  :    1;  /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/
+            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t waiti_cmd                     :    16;  /*The command value to wait flash idle(RDSR).*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
+            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
+            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
+            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
+            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_pes_command             :    16;  /*Program/Erase suspend command.*/
+            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
+            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
+            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
+            uint32_t reserved8                     :    7;  /*reserved*/
+            uint32_t flash_pesr_cmd_2b             :    1;  /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/
+            uint32_t flash_per_command             :    16;  /*Program/Erase resume command.*/
+        };
+        uint32_t val;
+    } sus_status;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    union {
+        struct {
+            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject_en                 :    1;  /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err_en           :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved10                    :    17;  /*reserved*/
+            uint32_t dqs0_afifo_ovf_en             :    1;  /*The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/
+            uint32_t dqs1_afifo_ovf_en             :    1;  /*The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/
+            uint32_t bus_fifo1_udf_en              :    1;  /*The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/
+            uint32_t bus_fifo0_udf_en              :    1;  /*The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err                       :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject                    :    1;  /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved10                    :    17;  /*reserved*/
+            uint32_t dqs0_afifo_ovf                :    1;  /*The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/
+            uint32_t dqs1_afifo_ovf                :    1;  /*The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/
+            uint32_t bus_fifo1_udf                 :    1;  /*The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/
+            uint32_t bus_fifo0_udf                 :    1;  /*The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
+            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
+            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/
+            uint32_t ecc_err                       :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
+            uint32_t pms_reject                    :    1;  /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/
+            uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
+            uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t reserved10                    :    17;  /*reserved*/
+            uint32_t dqs0_afifo_ovf                :    1;  /*The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow.*/
+            uint32_t dqs1_afifo_ovf                :    1;  /*The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow.*/
+            uint32_t bus_fifo1_udf                 :    1;  /*The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow.*/
+            uint32_t bus_fifo0_udf                 :    1;  /*The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow.*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err                       :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject                    :    1;  /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved10                    :    17;  /*reserved*/
+            uint32_t dqs0_afifo_ovf                :    1;  /*The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/
+            uint32_t dqs1_afifo_ovf                :    1;  /*The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/
+            uint32_t bus_fifo1_udf                 :    1;  /*The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/
+            uint32_t bus_fifo0_udf                 :    1;  /*The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_d0;
+    union {
+        struct {
+            uint32_t fmem_ddr_en                   :    1;  /*1: in DDR mode,  0 in SDR mode*/
+            uint32_t fmem_var_dummy                :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
+            uint32_t fmem_ddr_rdat_swp             :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
+            uint32_t fmem_ddr_wdat_swp             :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
+            uint32_t fmem_ddr_cmd_dis              :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
+            uint32_t fmem_outminbytelen            :    7;  /*It is the minimum output data length in the panda device.*/
+            uint32_t fmem_tx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
+            uint32_t fmem_rx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/
+            uint32_t fmem_usr_ddr_dqs_thd          :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
+            uint32_t fmem_ddr_dqs_loop             :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t fmem_clk_diff_en              :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t fmem_dqs_ca_in                :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t fmem_hyperbus_dummy_2x        :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
+            uint32_t fmem_clk_diff_inv             :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
+            uint32_t fmem_octa_ram_addr            :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t fmem_hyperbus_ca              :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } ddr;
+    union {
+        struct {
+            uint32_t ddr_en                        :    1;  /*1: in DDR mode,  0 in SDR mode*/
+            uint32_t var_dummy                     :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
+            uint32_t ddr_rdat_swp                  :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
+            uint32_t ddr_wdat_swp                  :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
+            uint32_t ddr_cmd_dis                   :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
+            uint32_t outminbytelen                 :    7;  /*It is the minimum output data length in the DDR psram.*/
+            uint32_t tx_ddr_msk_en                 :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/
+            uint32_t rx_ddr_msk_en                 :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/
+            uint32_t usr_ddr_dqs_thd               :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
+            uint32_t ddr_dqs_loop                  :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t clk_diff_en                   :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t dqs_ca_in                     :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t hyperbus_dummy_2x             :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
+            uint32_t clk_diff_inv                  :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
+            uint32_t octa_ram_addr                 :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t hyperbus_ca                   :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ddr;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    union {
+        struct {
+            uint32_t fmem_pms0_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t fmem_pms0_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t fmem_pms0_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_attr;
+    union {
+        struct {
+            uint32_t fmem_pms1_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t fmem_pms1_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t fmem_pms1_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_attr;
+    union {
+        struct {
+            uint32_t fmem_pms2_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t fmem_pms2_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t fmem_pms2_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_attr;
+    union {
+        struct {
+            uint32_t fmem_pms3_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t fmem_pms3_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t fmem_pms3_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_attr;
+    union {
+        struct {
+            uint32_t fmem_pms0_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_addr;
+    union {
+        struct {
+            uint32_t fmem_pms1_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_addr;
+    union {
+        struct {
+            uint32_t fmem_pms2_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_addr;
+    union {
+        struct {
+            uint32_t fmem_pms3_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_addr;
+    union {
+        struct {
+            uint32_t fmem_pms0_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_size;
+    union {
+        struct {
+            uint32_t fmem_pms1_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_size;
+    union {
+        struct {
+            uint32_t fmem_pms2_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_size;
+    union {
+        struct {
+            uint32_t fmem_pms3_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_size;
+    union {
+        struct {
+            uint32_t pms0_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t pms0_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t pms0_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_attr;
+    union {
+        struct {
+            uint32_t pms1_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t pms1_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t pms1_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_attr;
+    union {
+        struct {
+            uint32_t pms2_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t pms2_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t pms2_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_attr;
+    union {
+        struct {
+            uint32_t pms3_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
+            uint32_t pms3_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
+            uint32_t pms3_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_attr;
+    union {
+        struct {
+            uint32_t pms0_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_addr;
+    union {
+        struct {
+            uint32_t pms1_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_addr;
+    union {
+        struct {
+            uint32_t pms2_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_addr;
+    union {
+        struct {
+            uint32_t pms3_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_addr;
+    union {
+        struct {
+            uint32_t pms0_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_size;
+    union {
+        struct {
+            uint32_t pms1_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_size;
+    union {
+        struct {
+            uint32_t pms2_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_size;
+    union {
+        struct {
+            uint32_t pms3_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_size;
+    uint32_t reserved_160;
+    union {
+        struct {
+            uint32_t reject_addr                   :    26;  /*This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pm_en                         :    1;  /*Set this bit to enable SPI0/1 transfer permission control function.*/
+            uint32_t reserved27                    :    1;  /*reserved*/
+            uint32_t pms_ld                        :    1;  /*1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_st                        :    1;  /*1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_multi_hit                 :    1;  /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_ivd                       :    1;  /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+        };
+        uint32_t val;
+    } pms_reject;
+    union {
+        struct {
+            uint32_t reserved0                     :    11;  /*reserved*/
+            uint32_t ecc_err_int_num               :    6;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t fmem_ecc_err_int_en           :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
+            uint32_t fmem_page_size                :    2;  /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t fmem_ecc_addr_en              :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/
+            uint32_t usr_ecc_addr_en               :    1;  /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t ecc_continue_record_err_en    :    1;  /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/
+            uint32_t ecc_err_bits                  :    7;  /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/
+        };
+        uint32_t val;
+    } ecc_ctrl;
+    union {
+        struct {
+            uint32_t ecc_err_addr                  :    26;  /*This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
+            uint32_t ecc_err_cnt                   :    6;  /*This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
+        };
+        uint32_t val;
+    } ecc_err_addr;
+    union {
+        struct {
+            uint32_t axi_err_addr                  :    26;  /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
+            uint32_t all_fifo_empty                :    1;  /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
+            uint32_t reg_rdata_afifo_rempty        :    1;  /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
+            uint32_t reg_raddr_afifo_rempty        :    1;  /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
+            uint32_t reg_wdata_afifo_rempty        :    1;  /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
+            uint32_t reg_wblen_afifo_rempty        :    1;  /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
+            uint32_t reg_all_axi_trans_afifo_empty :    1;  /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/
+        };
+        uint32_t val;
+    } axi_err_addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    17;  /*reserved*/
+            uint32_t ecc_err_int_en                :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
+            uint32_t page_size                     :    2;  /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t ecc_addr_en                   :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ecc_ctrl;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    union {
+        struct {
+            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/
+            uint32_t timing_cali_update            :    1;  /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/
+            uint32_t reserved7                     :    25;  /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t timing_clk_ena                :    1;  /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali                   :    1;  /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_dout_mode;
+    union {
+        struct {
+            uint32_t cs_setup                      :    1;  /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
+            uint32_t cs_hold                       :    1;  /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
+            uint32_t cs_setup_time                 :    5;  /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t cs_hold_time                  :    5;  /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t ecc_cs_hold_time              :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/
+            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
+            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
+            uint32_t reserved17                    :    8;  /*reserved*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
+        };
+        uint32_t val;
+    } spi_smem_ac;
+    union {
+        struct {
+            uint32_t din08_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din09_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din10_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din11_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din12_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din13_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din14_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din15_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t dins_hex_mode                 :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_hex_mode;
+    union {
+        struct {
+            uint32_t din08_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din09_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din10_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din11_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din12_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din13_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din14_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din15_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t dins_hex_num                  :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_hex_num;
+    union {
+        struct {
+            uint32_t dout08_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout09_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout10_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout11_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout12_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout13_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout14_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout15_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t douts_hex_mode                :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_dout_hex_mode;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t xts_plain_base;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    union {
+        struct {
+            uint32_t reg_xts_linesize              :    2;  /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_linesize;
+    union {
+        struct {
+            uint32_t reg_xts_destination           :    1;  /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_destination;
+    union {
+        struct {
+            uint32_t reg_xts_physical_address      :    26;  /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_physical_address;
+    union {
+        struct {
+            uint32_t reg_xts_trigger               :    1;  /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_trigger;
+    union {
+        struct {
+            uint32_t reg_xts_release               :    1;  /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_release;
+    union {
+        struct {
+            uint32_t reg_xts_destroy               :    1;  /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_destroy;
+    union {
+        struct {
+            uint32_t reg_xts_state                 :    2;  /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_state;
+    union {
+        struct {
+            uint32_t reg_xts_date                  :    30;  /*This bits stores the last modified-time of manual encryption feature.*/
+            uint32_t reserved30                    :    2;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_date;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t mmu_item_content;
+    uint32_t mmu_item_index;
+    union {
+        struct {
+            uint32_t mem_force_on                  :    1;  /*Set this bit to enable mmu-memory clock force on*/
+            uint32_t mem_force_pd                  :    1;  /*Set this bit to force mmu-memory powerdown*/
+            uint32_t mem_force_pu                  :    1;  /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/
+            uint32_t reserved3                     :    13;  /*reserved*/
+            uint32_t aux_ctrl                      :    14;  /*MMU PSRAM aux control register*/
+            uint32_t rdn_ena                       :    1;  /*ECO register enable bit*/
+            uint32_t rdn_result                    :    1;  /*MSPI module clock domain and AXI clock domain ECO register result register*/
+        };
+        uint32_t val;
+    } mmu_power_ctrl;
+    union {
+        struct {
+            uint32_t crtyp_security_level          :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
+            uint32_t crtyp_calc_d_dpa_en           :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
+            uint32_t crtyp_dpa_selectister         :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } dpa_ctrl;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t registeredrnd_eco_high;
+    uint32_t registeredrnd_eco_low;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI0 register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/spi_pins.h b/components/soc/esp32p4/include/soc/spi_pins.h
new file mode 100644
index 0000000000..bdfce943a2
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/spi_pins.h
@@ -0,0 +1,26 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_SPI_PINS_H_
+#define _SOC_SPI_PINS_H_
+
+#define SPI_FUNC_NUM            0
+#define SPI_IOMUX_PIN_NUM_HD    12
+#define SPI_IOMUX_PIN_NUM_CS    14
+#define SPI_IOMUX_PIN_NUM_MOSI  16
+#define SPI_IOMUX_PIN_NUM_CLK   15
+#define SPI_IOMUX_PIN_NUM_MISO  17
+#define SPI_IOMUX_PIN_NUM_WP    13
+
+#define SPI2_FUNC_NUM           2
+#define SPI2_IOMUX_PIN_NUM_MISO 2
+#define SPI2_IOMUX_PIN_NUM_HD   4
+#define SPI2_IOMUX_PIN_NUM_WP   5
+#define SPI2_IOMUX_PIN_NUM_CLK  6
+#define SPI2_IOMUX_PIN_NUM_MOSI 7
+#define SPI2_IOMUX_PIN_NUM_CS   10
+
+#endif
diff --git a/components/soc/esp32p4/include/soc/sys_clkrst_reg.h b/components/soc/esp32p4/include/soc/sys_clkrst_reg.h
new file mode 100644
index 0000000000..202223cf00
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/sys_clkrst_reg.h
@@ -0,0 +1,1118 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYS_CLKRST_REG_H_
+#define _SOC_SYS_CLKRST_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define SYS_CLKRST_SYS_CLK_VER_DATE_REG          (DR_REG_SYS_CLKRST_BASE + 0x0)
+/* SYS_CLKRST_VER_DATE : R/W ;bitpos:[31:0] ;default: 32'h20210610 ; */
+/*description: .*/
+#define SYS_CLKRST_VER_DATE    0xFFFFFFFF
+#define SYS_CLKRST_VER_DATE_M  ((SYS_CLKRST_VER_DATE_V)<<(SYS_CLKRST_VER_DATE_S))
+#define SYS_CLKRST_VER_DATE_V  0xFFFFFFFF
+#define SYS_CLKRST_VER_DATE_S  0
+
+#define SYS_CLKRST_SYS_ICM_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x4)
+/* SYS_CLKRST_SYS_ICM_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: system icm clock enable.*/
+#define SYS_CLKRST_SYS_ICM_APB_CLK_EN    (BIT(0))
+#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_S  0
+
+#define SYS_CLKRST_JPEG_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x8)
+/* SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_JPEG_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_JPEG_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_JPEG_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_JPEG_CLK_DIV_NUM_M  ((SYS_CLKRST_JPEG_CLK_DIV_NUM_V)<<(SYS_CLKRST_JPEG_CLK_DIV_NUM_S))
+#define SYS_CLKRST_JPEG_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_JPEG_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_JPEG_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_JPEG_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_JPEG_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_JPEG_FORCE_NORST_V  0x1
+#define SYS_CLKRST_JPEG_FORCE_NORST_S  5
+/* SYS_CLKRST_JPEG_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_JPEG_RSTN    (BIT(4))
+#define SYS_CLKRST_JPEG_RSTN_M  (BIT(4))
+#define SYS_CLKRST_JPEG_RSTN_V  0x1
+#define SYS_CLKRST_JPEG_RSTN_S  4
+/* SYS_CLKRST_JPEG_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_JPEG_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_JPEG_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_JPEG_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_JPEG_APB_CLK_EN_S  3
+/* SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_JPEG_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_JPEG_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_JPEG_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_JPEG_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_JPEG_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_JPEG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_JPEG_CLK_EN    (BIT(0))
+#define SYS_CLKRST_JPEG_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_JPEG_CLK_EN_V  0x1
+#define SYS_CLKRST_JPEG_CLK_EN_S  0
+
+#define SYS_CLKRST_GFX_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0xC)
+/* SYS_CLKRST_GFX_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_GFX_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_GFX_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GFX_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_GFX_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_GFX_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_GFX_CLK_DIV_NUM_M  ((SYS_CLKRST_GFX_CLK_DIV_NUM_V)<<(SYS_CLKRST_GFX_CLK_DIV_NUM_S))
+#define SYS_CLKRST_GFX_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_GFX_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_GFX_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_GFX_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_GFX_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_GFX_FORCE_NORST_V  0x1
+#define SYS_CLKRST_GFX_FORCE_NORST_S  5
+/* SYS_CLKRST_GFX_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_GFX_RSTN    (BIT(4))
+#define SYS_CLKRST_GFX_RSTN_M  (BIT(4))
+#define SYS_CLKRST_GFX_RSTN_V  0x1
+#define SYS_CLKRST_GFX_RSTN_S  4
+/* SYS_CLKRST_GFX_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_GFX_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_GFX_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_GFX_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_GFX_APB_CLK_EN_S  3
+/* SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_GFX_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_GFX_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_GFX_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_GFX_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_GFX_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_GFX_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_GFX_CLK_EN    (BIT(0))
+#define SYS_CLKRST_GFX_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_GFX_CLK_EN_V  0x1
+#define SYS_CLKRST_GFX_CLK_EN_S  0
+
+#define SYS_CLKRST_PSRAM_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x10)
+/* SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_PSRAM_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_PSRAM_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_M  ((SYS_CLKRST_PSRAM_CLK_DIV_NUM_V)<<(SYS_CLKRST_PSRAM_CLK_DIV_NUM_S))
+#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_PSRAM_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_PSRAM_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_PSRAM_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_PSRAM_FORCE_NORST_V  0x1
+#define SYS_CLKRST_PSRAM_FORCE_NORST_S  5
+/* SYS_CLKRST_PSRAM_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_PSRAM_RSTN    (BIT(4))
+#define SYS_CLKRST_PSRAM_RSTN_M  (BIT(4))
+#define SYS_CLKRST_PSRAM_RSTN_V  0x1
+#define SYS_CLKRST_PSRAM_RSTN_S  4
+/* SYS_CLKRST_PSRAM_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_PSRAM_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_PSRAM_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_PSRAM_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_PSRAM_APB_CLK_EN_S  3
+/* SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_PSRAM_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_PSRAM_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_PSRAM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_PSRAM_CLK_EN    (BIT(0))
+#define SYS_CLKRST_PSRAM_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_PSRAM_CLK_EN_V  0x1
+#define SYS_CLKRST_PSRAM_CLK_EN_S  0
+
+#define SYS_CLKRST_MSPI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x14)
+/* SYS_CLKRST_MSPI_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_MSPI_FORCE_NORST    (BIT(2))
+#define SYS_CLKRST_MSPI_FORCE_NORST_M  (BIT(2))
+#define SYS_CLKRST_MSPI_FORCE_NORST_V  0x1
+#define SYS_CLKRST_MSPI_FORCE_NORST_S  2
+/* SYS_CLKRST_MSPI_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_MSPI_RSTN    (BIT(1))
+#define SYS_CLKRST_MSPI_RSTN_M  (BIT(1))
+#define SYS_CLKRST_MSPI_RSTN_V  0x1
+#define SYS_CLKRST_MSPI_RSTN_S  1
+/* SYS_CLKRST_MSPI_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_MSPI_APB_CLK_EN    (BIT(0))
+#define SYS_CLKRST_MSPI_APB_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_MSPI_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_MSPI_APB_CLK_EN_S  0
+
+#define SYS_CLKRST_DSI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x18)
+/* SYS_CLKRST_DSI_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_DSI_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_DSI_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_DSI_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_DSI_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_DSI_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_DSI_CLK_DIV_NUM_M  ((SYS_CLKRST_DSI_CLK_DIV_NUM_V)<<(SYS_CLKRST_DSI_CLK_DIV_NUM_S))
+#define SYS_CLKRST_DSI_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_DSI_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_DSI_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_DSI_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_DSI_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_DSI_FORCE_NORST_V  0x1
+#define SYS_CLKRST_DSI_FORCE_NORST_S  5
+/* SYS_CLKRST_DSI_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_DSI_RSTN    (BIT(4))
+#define SYS_CLKRST_DSI_RSTN_M  (BIT(4))
+#define SYS_CLKRST_DSI_RSTN_V  0x1
+#define SYS_CLKRST_DSI_RSTN_S  4
+/* SYS_CLKRST_DSI_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_DSI_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_DSI_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_DSI_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_DSI_APB_CLK_EN_S  3
+/* SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_DSI_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_DSI_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_DSI_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_DSI_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_DSI_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_DSI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_DSI_CLK_EN    (BIT(0))
+#define SYS_CLKRST_DSI_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_DSI_CLK_EN_V  0x1
+#define SYS_CLKRST_DSI_CLK_EN_S  0
+
+#define SYS_CLKRST_CSI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x1C)
+/* SYS_CLKRST_CSI_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_CSI_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_CSI_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_CSI_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_CSI_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_CSI_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_CSI_CLK_DIV_NUM_M  ((SYS_CLKRST_CSI_CLK_DIV_NUM_V)<<(SYS_CLKRST_CSI_CLK_DIV_NUM_S))
+#define SYS_CLKRST_CSI_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_CSI_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_CSI_BRG_RSTN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_CSI_BRG_RSTN    (BIT(6))
+#define SYS_CLKRST_CSI_BRG_RSTN_M  (BIT(6))
+#define SYS_CLKRST_CSI_BRG_RSTN_V  0x1
+#define SYS_CLKRST_CSI_BRG_RSTN_S  6
+/* SYS_CLKRST_CSI_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_CSI_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_CSI_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_CSI_FORCE_NORST_V  0x1
+#define SYS_CLKRST_CSI_FORCE_NORST_S  5
+/* SYS_CLKRST_CSI_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_CSI_RSTN    (BIT(4))
+#define SYS_CLKRST_CSI_RSTN_M  (BIT(4))
+#define SYS_CLKRST_CSI_RSTN_V  0x1
+#define SYS_CLKRST_CSI_RSTN_S  4
+/* SYS_CLKRST_CSI_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_CSI_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_CSI_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_CSI_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_CSI_APB_CLK_EN_S  3
+/* SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_CSI_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_CSI_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_CSI_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_CSI_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_CSI_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_CSI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_CSI_CLK_EN    (BIT(0))
+#define SYS_CLKRST_CSI_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_CSI_CLK_EN_V  0x1
+#define SYS_CLKRST_CSI_CLK_EN_S  0
+
+#define SYS_CLKRST_USB_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x20)
+/* SYS_CLKRST_USB_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_USB_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_USB_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_USB_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_USB_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_USB_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_USB_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_USB_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_USB_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_USB_CLK_DIV_NUM_M  ((SYS_CLKRST_USB_CLK_DIV_NUM_V)<<(SYS_CLKRST_USB_CLK_DIV_NUM_S))
+#define SYS_CLKRST_USB_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_USB_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_USB_PHY_FORCE_NORST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Usb phy software force no reset.*/
+#define SYS_CLKRST_USB_PHY_FORCE_NORST    (BIT(7))
+#define SYS_CLKRST_USB_PHY_FORCE_NORST_M  (BIT(7))
+#define SYS_CLKRST_USB_PHY_FORCE_NORST_V  0x1
+#define SYS_CLKRST_USB_PHY_FORCE_NORST_S  7
+/* SYS_CLKRST_USB_FORCE_NORST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Usb software force no reset.*/
+#define SYS_CLKRST_USB_FORCE_NORST    (BIT(6))
+#define SYS_CLKRST_USB_FORCE_NORST_M  (BIT(6))
+#define SYS_CLKRST_USB_FORCE_NORST_V  0x1
+#define SYS_CLKRST_USB_FORCE_NORST_S  6
+/* SYS_CLKRST_USB_PHY_RSTN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: Usb phy software reset : low active.*/
+#define SYS_CLKRST_USB_PHY_RSTN    (BIT(5))
+#define SYS_CLKRST_USB_PHY_RSTN_M  (BIT(5))
+#define SYS_CLKRST_USB_PHY_RSTN_V  0x1
+#define SYS_CLKRST_USB_PHY_RSTN_S  5
+/* SYS_CLKRST_USB_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: Usb software reset : low active.*/
+#define SYS_CLKRST_USB_RSTN    (BIT(4))
+#define SYS_CLKRST_USB_RSTN_M  (BIT(4))
+#define SYS_CLKRST_USB_RSTN_V  0x1
+#define SYS_CLKRST_USB_RSTN_S  4
+/* SYS_CLKRST_USB_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_USB_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_USB_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_USB_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_USB_APB_CLK_EN_S  3
+/* SYS_CLKRST_USB_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_USB_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_USB_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_USB_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_USB_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_USB_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_USB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_USB_CLK_EN    (BIT(0))
+#define SYS_CLKRST_USB_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_USB_CLK_EN_V  0x1
+#define SYS_CLKRST_USB_CLK_EN_S  0
+
+#define SYS_CLKRST_GMAC_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x24)
+/* SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'b0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_GMAC_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_GMAC_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_GMAC_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_GMAC_CLK_DIV_NUM_M  ((SYS_CLKRST_GMAC_CLK_DIV_NUM_V)<<(SYS_CLKRST_GMAC_CLK_DIV_NUM_S))
+#define SYS_CLKRST_GMAC_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_GMAC_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_GMAC_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_GMAC_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_GMAC_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_GMAC_FORCE_NORST_V  0x1
+#define SYS_CLKRST_GMAC_FORCE_NORST_S  5
+/* SYS_CLKRST_GMAC_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_GMAC_RSTN    (BIT(4))
+#define SYS_CLKRST_GMAC_RSTN_M  (BIT(4))
+#define SYS_CLKRST_GMAC_RSTN_V  0x1
+#define SYS_CLKRST_GMAC_RSTN_S  4
+/* SYS_CLKRST_GMAC_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_GMAC_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_GMAC_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_GMAC_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_GMAC_APB_CLK_EN_S  3
+/* SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_GMAC_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_GMAC_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_GMAC_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_GMAC_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_GMAC_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_GMAC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_GMAC_CLK_EN    (BIT(0))
+#define SYS_CLKRST_GMAC_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_GMAC_CLK_EN_V  0x1
+#define SYS_CLKRST_GMAC_CLK_EN_S  0
+
+#define SYS_CLKRST_SDMMC_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x28)
+/* SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_SDMMC_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_SDMMC_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_M  ((SYS_CLKRST_SDMMC_CLK_DIV_NUM_V)<<(SYS_CLKRST_SDMMC_CLK_DIV_NUM_S))
+#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_SDMMC_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_SDMMC_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_SDMMC_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_SDMMC_FORCE_NORST_V  0x1
+#define SYS_CLKRST_SDMMC_FORCE_NORST_S  5
+/* SYS_CLKRST_SDMMC_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_SDMMC_RSTN    (BIT(4))
+#define SYS_CLKRST_SDMMC_RSTN_M  (BIT(4))
+#define SYS_CLKRST_SDMMC_RSTN_V  0x1
+#define SYS_CLKRST_SDMMC_RSTN_S  4
+/* SYS_CLKRST_SDMMC_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_SDMMC_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_SDMMC_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_SDMMC_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_SDMMC_APB_CLK_EN_S  3
+/* SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_SDMMC_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_SDMMC_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_SDMMC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_SDMMC_CLK_EN    (BIT(0))
+#define SYS_CLKRST_SDMMC_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_SDMMC_CLK_EN_V  0x1
+#define SYS_CLKRST_SDMMC_CLK_EN_S  0
+
+#define SYS_CLKRST_DDRC_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x2C)
+/* SYS_CLKRST_DDRC_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_DDRC_FORCE_NORST    (BIT(2))
+#define SYS_CLKRST_DDRC_FORCE_NORST_M  (BIT(2))
+#define SYS_CLKRST_DDRC_FORCE_NORST_V  0x1
+#define SYS_CLKRST_DDRC_FORCE_NORST_S  2
+/* SYS_CLKRST_DDRC_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_DDRC_RSTN    (BIT(1))
+#define SYS_CLKRST_DDRC_RSTN_M  (BIT(1))
+#define SYS_CLKRST_DDRC_RSTN_V  0x1
+#define SYS_CLKRST_DDRC_RSTN_S  1
+/* SYS_CLKRST_DDRC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_DDRC_CLK_EN    (BIT(0))
+#define SYS_CLKRST_DDRC_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_DDRC_CLK_EN_V  0x1
+#define SYS_CLKRST_DDRC_CLK_EN_S  0
+
+#define SYS_CLKRST_GDMA_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x30)
+/* SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: current clock divider number.*/
+#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_GDMA_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: clock phase offset compare to hp clock sync signal.*/
+#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_GDMA_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: clock divider number.*/
+#define SYS_CLKRST_GDMA_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_GDMA_CLK_DIV_NUM_M  ((SYS_CLKRST_GDMA_CLK_DIV_NUM_V)<<(SYS_CLKRST_GDMA_CLK_DIV_NUM_S))
+#define SYS_CLKRST_GDMA_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_GDMA_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_GDMA_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: software force no reset.*/
+#define SYS_CLKRST_GDMA_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_GDMA_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_GDMA_FORCE_NORST_V  0x1
+#define SYS_CLKRST_GDMA_FORCE_NORST_S  5
+/* SYS_CLKRST_GDMA_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: software reset : low active.*/
+#define SYS_CLKRST_GDMA_RSTN    (BIT(4))
+#define SYS_CLKRST_GDMA_RSTN_M  (BIT(4))
+#define SYS_CLKRST_GDMA_RSTN_V  0x1
+#define SYS_CLKRST_GDMA_RSTN_S  4
+/* SYS_CLKRST_GDMA_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: apb clock enable.*/
+#define SYS_CLKRST_GDMA_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_GDMA_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_GDMA_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_GDMA_APB_CLK_EN_S  3
+/* SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: clock force sync enable : clock output only available when clock is synced.*/
+#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_GDMA_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
+#define SYS_CLKRST_GDMA_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_GDMA_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_GDMA_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_GDMA_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_GDMA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock output enable.*/
+#define SYS_CLKRST_GDMA_CLK_EN    (BIT(0))
+#define SYS_CLKRST_GDMA_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_GDMA_CLK_EN_V  0x1
+#define SYS_CLKRST_GDMA_CLK_EN_S  0
+
+#define SYS_CLKRST_USBOTG_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x34)
+/* SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_USBOTG_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_M  ((SYS_CLKRST_USBOTG_CLK_DIV_NUM_V)<<(SYS_CLKRST_USBOTG_CLK_DIV_NUM_S))
+#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_USBOTG_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_USBOTG_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_USBOTG_FORCE_NORST_V  0x1
+#define SYS_CLKRST_USBOTG_FORCE_NORST_S  5
+/* SYS_CLKRST_USBOTG_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_RSTN    (BIT(4))
+#define SYS_CLKRST_USBOTG_RSTN_M  (BIT(4))
+#define SYS_CLKRST_USBOTG_RSTN_V  0x1
+#define SYS_CLKRST_USBOTG_RSTN_S  4
+/* SYS_CLKRST_USBOTG_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_APB_CLK_EN    (BIT(3))
+#define SYS_CLKRST_USBOTG_APB_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_USBOTG_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_USBOTG_APB_CLK_EN_S  3
+/* SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_USBOTG_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_USBOTG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_USBOTG_CLK_EN    (BIT(0))
+#define SYS_CLKRST_USBOTG_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_USBOTG_CLK_EN_V  0x1
+#define SYS_CLKRST_USBOTG_CLK_EN_S  0
+
+#define SYS_CLKRST_SDIO_SLAVE_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x38)
+/* SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM    0x000000FF
+#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_S))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_V  0xFF
+#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_S  24
+/* SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET    0x000000FF
+#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_S))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_V  0xFF
+#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_S  16
+/* SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM    0x000000FF
+#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_M  ((SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_S))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_V  0xFF
+#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_S  8
+/* SYS_CLKRST_SDIO_SLAVE_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST    (BIT(5))
+#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_M  (BIT(5))
+#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_V  0x1
+#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_S  5
+/* SYS_CLKRST_SDIO_SLAVE_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_RSTN    (BIT(4))
+#define SYS_CLKRST_SDIO_SLAVE_RSTN_M  (BIT(4))
+#define SYS_CLKRST_SDIO_SLAVE_RSTN_V  0x1
+#define SYS_CLKRST_SDIO_SLAVE_RSTN_S  4
+/* SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN    (BIT(2))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_M  (BIT(2))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_V  0x1
+#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_S  2
+/* SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN    (BIT(1))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_M  (BIT(1))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_V  0x1
+#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_S  1
+/* SYS_CLKRST_SDIO_SLAVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_CLK_EN    (BIT(0))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_V  0x1
+#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_S  0
+
+#define SYS_CLKRST_ISP_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x40)
+/* SYS_CLKRST_ISP_CLK_DIV_NUM : R/W ;bitpos:[6:3] ;default: 4'd1 ; */
+/*description: .*/
+#define SYS_CLKRST_ISP_CLK_DIV_NUM    0x0000000F
+#define SYS_CLKRST_ISP_CLK_DIV_NUM_M  ((SYS_CLKRST_ISP_CLK_DIV_NUM_V)<<(SYS_CLKRST_ISP_CLK_DIV_NUM_S))
+#define SYS_CLKRST_ISP_CLK_DIV_NUM_V  0xF
+#define SYS_CLKRST_ISP_CLK_DIV_NUM_S  3
+/* SYS_CLKRST_ISP_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_ISP_FORCE_NORST    (BIT(2))
+#define SYS_CLKRST_ISP_FORCE_NORST_M  (BIT(2))
+#define SYS_CLKRST_ISP_FORCE_NORST_V  0x1
+#define SYS_CLKRST_ISP_FORCE_NORST_S  2
+/* SYS_CLKRST_ISP_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_ISP_RSTN    (BIT(1))
+#define SYS_CLKRST_ISP_RSTN_M  (BIT(1))
+#define SYS_CLKRST_ISP_RSTN_V  0x1
+#define SYS_CLKRST_ISP_RSTN_S  1
+/* SYS_CLKRST_ISP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_ISP_CLK_EN    (BIT(0))
+#define SYS_CLKRST_ISP_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_ISP_CLK_EN_V  0x1
+#define SYS_CLKRST_ISP_CLK_EN_S  0
+
+#define SYS_CLKRST_DMA2D_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x44)
+/* SYS_CLKRST_DMA2D_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_DMA2D_FORCE_NORST    (BIT(2))
+#define SYS_CLKRST_DMA2D_FORCE_NORST_M  (BIT(2))
+#define SYS_CLKRST_DMA2D_FORCE_NORST_V  0x1
+#define SYS_CLKRST_DMA2D_FORCE_NORST_S  2
+/* SYS_CLKRST_DMA2D_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_DMA2D_RSTN    (BIT(1))
+#define SYS_CLKRST_DMA2D_RSTN_M  (BIT(1))
+#define SYS_CLKRST_DMA2D_RSTN_V  0x1
+#define SYS_CLKRST_DMA2D_RSTN_S  1
+/* SYS_CLKRST_DMA2D_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_DMA2D_CLK_EN    (BIT(0))
+#define SYS_CLKRST_DMA2D_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_DMA2D_CLK_EN_V  0x1
+#define SYS_CLKRST_DMA2D_CLK_EN_S  0
+
+#define SYS_CLKRST_PPA_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x48)
+/* SYS_CLKRST_PPA_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PPA_FORCE_NORST    (BIT(2))
+#define SYS_CLKRST_PPA_FORCE_NORST_M  (BIT(2))
+#define SYS_CLKRST_PPA_FORCE_NORST_V  0x1
+#define SYS_CLKRST_PPA_FORCE_NORST_S  2
+/* SYS_CLKRST_PPA_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_PPA_RSTN    (BIT(1))
+#define SYS_CLKRST_PPA_RSTN_M  (BIT(1))
+#define SYS_CLKRST_PPA_RSTN_V  0x1
+#define SYS_CLKRST_PPA_RSTN_S  1
+/* SYS_CLKRST_PPA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_PPA_CLK_EN    (BIT(0))
+#define SYS_CLKRST_PPA_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_PPA_CLK_EN_V  0x1
+#define SYS_CLKRST_PPA_CLK_EN_S  0
+
+#define SYS_CLKRST_GDMA_DBG_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x50)
+/* SYS_CLKRST_DEBUG_CH_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_DEBUG_CH_NUM    0x00000003
+#define SYS_CLKRST_DEBUG_CH_NUM_M  ((SYS_CLKRST_DEBUG_CH_NUM_V)<<(SYS_CLKRST_DEBUG_CH_NUM_S))
+#define SYS_CLKRST_DEBUG_CH_NUM_V  0x3
+#define SYS_CLKRST_DEBUG_CH_NUM_S  0
+
+#define SYS_CLKRST_GMAC_PTP_RD0_REG          (DR_REG_SYS_CLKRST_BASE + 0x54)
+/* SYS_CLKRST_PTP_TIMESTAMP_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_PTP_TIMESTAMP_LO    0xFFFFFFFF
+#define SYS_CLKRST_PTP_TIMESTAMP_LO_M  ((SYS_CLKRST_PTP_TIMESTAMP_LO_V)<<(SYS_CLKRST_PTP_TIMESTAMP_LO_S))
+#define SYS_CLKRST_PTP_TIMESTAMP_LO_V  0xFFFFFFFF
+#define SYS_CLKRST_PTP_TIMESTAMP_LO_S  0
+
+#define SYS_CLKRST_GMAC_PTP_RD1_REG          (DR_REG_SYS_CLKRST_BASE + 0x58)
+/* SYS_CLKRST_PTP_TIMESTAMP_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_PTP_TIMESTAMP_HI    0xFFFFFFFF
+#define SYS_CLKRST_PTP_TIMESTAMP_HI_M  ((SYS_CLKRST_PTP_TIMESTAMP_HI_V)<<(SYS_CLKRST_PTP_TIMESTAMP_HI_S))
+#define SYS_CLKRST_PTP_TIMESTAMP_HI_V  0xFFFFFFFF
+#define SYS_CLKRST_PTP_TIMESTAMP_HI_S  0
+
+#define SYS_CLKRST_GMAC_PTP_PPS_REG          (DR_REG_SYS_CLKRST_BASE + 0x5C)
+/* SYS_CLKRST_PTP_PPS : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_PTP_PPS    (BIT(0))
+#define SYS_CLKRST_PTP_PPS_M  (BIT(0))
+#define SYS_CLKRST_PTP_PPS_V  0x1
+#define SYS_CLKRST_PTP_PPS_S  0
+
+#define SYS_CLKRST_GMAC_CLK_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x60)
+/* SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON    (BIT(13))
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_M  (BIT(13))
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_V  0x1
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_S  13
+/* SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON    (BIT(12))
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_M  (BIT(12))
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_V  0x1
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_S  12
+/* SYS_CLKRST_GMAC_FUNC_RX_CLK_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN    (BIT(11))
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_M  (BIT(11))
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_V  0x1
+#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_S  11
+/* SYS_CLKRST_GMAC_FUNC_TX_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN    (BIT(10))
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_M  (BIT(10))
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_V  0x1
+#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_S  10
+/* SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON    (BIT(9))
+#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_M  (BIT(9))
+#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_V  0x1
+#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_S  9
+/* SYS_CLKRST_REVMII_PMA_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_REVMII_PMA_CLK_EN    (BIT(8))
+#define SYS_CLKRST_REVMII_PMA_CLK_EN_M  (BIT(8))
+#define SYS_CLKRST_REVMII_PMA_CLK_EN_V  0x1
+#define SYS_CLKRST_REVMII_PMA_CLK_EN_S  8
+/* SYS_CLKRST_RMII_CLK_PORT_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_RMII_CLK_PORT_SEL    (BIT(7))
+#define SYS_CLKRST_RMII_CLK_PORT_SEL_M  (BIT(7))
+#define SYS_CLKRST_RMII_CLK_PORT_SEL_V  0x1
+#define SYS_CLKRST_RMII_CLK_PORT_SEL_S  7
+/* SYS_CLKRST_SBD_FLOWCTRL : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_SBD_FLOWCTRL    (BIT(6))
+#define SYS_CLKRST_SBD_FLOWCTRL_M  (BIT(6))
+#define SYS_CLKRST_SBD_FLOWCTRL_V  0x1
+#define SYS_CLKRST_SBD_FLOWCTRL_S  6
+/* SYS_CLKRST_PHY_INTF_SEL : R/W ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_INTF_SEL    0x00000007
+#define SYS_CLKRST_PHY_INTF_SEL_M  ((SYS_CLKRST_PHY_INTF_SEL_V)<<(SYS_CLKRST_PHY_INTF_SEL_S))
+#define SYS_CLKRST_PHY_INTF_SEL_V  0x7
+#define SYS_CLKRST_PHY_INTF_SEL_S  3
+/* SYS_CLKRST_PTP_REF_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PTP_REF_CLK_SEL    (BIT(2))
+#define SYS_CLKRST_PTP_REF_CLK_SEL_M  (BIT(2))
+#define SYS_CLKRST_PTP_REF_CLK_SEL_V  0x1
+#define SYS_CLKRST_PTP_REF_CLK_SEL_S  2
+/* SYS_CLKRST_REVERSE_GMAC_TX : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_REVERSE_GMAC_TX    (BIT(1))
+#define SYS_CLKRST_REVERSE_GMAC_TX_M  (BIT(1))
+#define SYS_CLKRST_REVERSE_GMAC_TX_V  0x1
+#define SYS_CLKRST_REVERSE_GMAC_TX_S  1
+/* SYS_CLKRST_REVERSE_GMAC_RX : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_REVERSE_GMAC_RX    (BIT(0))
+#define SYS_CLKRST_REVERSE_GMAC_RX_M  (BIT(0))
+#define SYS_CLKRST_REVERSE_GMAC_RX_V  0x1
+#define SYS_CLKRST_REVERSE_GMAC_RX_S  0
+
+#define SYS_CLKRST_OTG_PHY_CLK_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x64)
+/* SYS_CLKRST_OTG_EXT_PHY_SEL : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_OTG_EXT_PHY_SEL    (BIT(10))
+#define SYS_CLKRST_OTG_EXT_PHY_SEL_M  (BIT(10))
+#define SYS_CLKRST_OTG_EXT_PHY_SEL_V  0x1
+#define SYS_CLKRST_OTG_EXT_PHY_SEL_S  10
+/* SYS_CLKRST_PHY_REF_CLK_SEL : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_REF_CLK_SEL    (BIT(9))
+#define SYS_CLKRST_PHY_REF_CLK_SEL_M  (BIT(9))
+#define SYS_CLKRST_PHY_REF_CLK_SEL_V  0x1
+#define SYS_CLKRST_PHY_REF_CLK_SEL_S  9
+/* SYS_CLKRST_PHY_RESET_FORCE_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_RESET_FORCE_EN    (BIT(8))
+#define SYS_CLKRST_PHY_RESET_FORCE_EN_M  (BIT(8))
+#define SYS_CLKRST_PHY_RESET_FORCE_EN_V  0x1
+#define SYS_CLKRST_PHY_RESET_FORCE_EN_S  8
+/* SYS_CLKRST_PHY_RSTN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_RSTN    (BIT(7))
+#define SYS_CLKRST_PHY_RSTN_M  (BIT(7))
+#define SYS_CLKRST_PHY_RSTN_V  0x1
+#define SYS_CLKRST_PHY_RSTN_S  7
+/* SYS_CLKRST_PHY_PLL_FORCE_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_PLL_FORCE_EN    (BIT(6))
+#define SYS_CLKRST_PHY_PLL_FORCE_EN_M  (BIT(6))
+#define SYS_CLKRST_PHY_PLL_FORCE_EN_V  0x1
+#define SYS_CLKRST_PHY_PLL_FORCE_EN_S  6
+/* SYS_CLKRST_PHY_PLL_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_PLL_EN    (BIT(5))
+#define SYS_CLKRST_PHY_PLL_EN_M  (BIT(5))
+#define SYS_CLKRST_PHY_PLL_EN_V  0x1
+#define SYS_CLKRST_PHY_PLL_EN_S  5
+/* SYS_CLKRST_PHY_SUSPEND_FORCE_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN    (BIT(4))
+#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_M  (BIT(4))
+#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_V  0x1
+#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_S  4
+/* SYS_CLKRST_PHY_SUSPENDM : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_PHY_SUSPENDM    (BIT(3))
+#define SYS_CLKRST_PHY_SUSPENDM_M  (BIT(3))
+#define SYS_CLKRST_PHY_SUSPENDM_V  0x1
+#define SYS_CLKRST_PHY_SUSPENDM_S  3
+/* SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN    (BIT(2))
+#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_M  (BIT(2))
+#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_V  0x1
+#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_S  2
+/* SYS_CLKRST_OTG_SUSPENDM : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_OTG_SUSPENDM    (BIT(1))
+#define SYS_CLKRST_OTG_SUSPENDM_M  (BIT(1))
+#define SYS_CLKRST_OTG_SUSPENDM_V  0x1
+#define SYS_CLKRST_OTG_SUSPENDM_S  1
+/* SYS_CLKRST_OTG_PHY_REFCLK_MODE : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_OTG_PHY_REFCLK_MODE    (BIT(0))
+#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_M  (BIT(0))
+#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_V  0x1
+#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_S  0
+
+#define SYS_CLKRST_SYS_PERI_APB_POSTW_CNTL_REG          (DR_REG_SYS_CLKRST_BASE + 0x68)
+/* SYS_CLKRST_DSI_HOST_APB_POSTW_EN : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN    (BIT(6))
+#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_M  (BIT(6))
+#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_V  0x1
+#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_S  6
+/* SYS_CLKRST_CSI_HOST_APB_POSTW_EN : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN    (BIT(5))
+#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_M  (BIT(5))
+#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_V  0x1
+#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_S  5
+/* SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN    (BIT(4))
+#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_M  (BIT(4))
+#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_V  0x1
+#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_S  4
+/* SYS_CLKRST_USB11_APB_POSTW_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_USB11_APB_POSTW_EN    (BIT(3))
+#define SYS_CLKRST_USB11_APB_POSTW_EN_M  (BIT(3))
+#define SYS_CLKRST_USB11_APB_POSTW_EN_V  0x1
+#define SYS_CLKRST_USB11_APB_POSTW_EN_S  3
+/* SYS_CLKRST_DMA2D_APB_POSTW_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_DMA2D_APB_POSTW_EN    (BIT(2))
+#define SYS_CLKRST_DMA2D_APB_POSTW_EN_M  (BIT(2))
+#define SYS_CLKRST_DMA2D_APB_POSTW_EN_V  0x1
+#define SYS_CLKRST_DMA2D_APB_POSTW_EN_S  2
+/* SYS_CLKRST_JPEG_APB_POSTW_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_JPEG_APB_POSTW_EN    (BIT(1))
+#define SYS_CLKRST_JPEG_APB_POSTW_EN_M  (BIT(1))
+#define SYS_CLKRST_JPEG_APB_POSTW_EN_V  0x1
+#define SYS_CLKRST_JPEG_APB_POSTW_EN_S  1
+/* SYS_CLKRST_GMAC_APB_POSTW_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_GMAC_APB_POSTW_EN    (BIT(0))
+#define SYS_CLKRST_GMAC_APB_POSTW_EN_M  (BIT(0))
+#define SYS_CLKRST_GMAC_APB_POSTW_EN_V  0x1
+#define SYS_CLKRST_GMAC_APB_POSTW_EN_S  0
+
+#define SYS_CLKRST_SYS_LSLP_MEM_PD_REG          (DR_REG_SYS_CLKRST_BASE + 0x6C)
+/* SYS_CLKRST_JPEG_SDSLP_MEM_PD : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_JPEG_SDSLP_MEM_PD    (BIT(4))
+#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_M  (BIT(4))
+#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_V  0x1
+#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_S  4
+/* SYS_CLKRST_JPEG_DSLP_MEM_PD : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_JPEG_DSLP_MEM_PD    (BIT(3))
+#define SYS_CLKRST_JPEG_DSLP_MEM_PD_M  (BIT(3))
+#define SYS_CLKRST_JPEG_DSLP_MEM_PD_V  0x1
+#define SYS_CLKRST_JPEG_DSLP_MEM_PD_S  3
+/* SYS_CLKRST_JPEG_LSLP_MEM_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_JPEG_LSLP_MEM_PD    (BIT(2))
+#define SYS_CLKRST_JPEG_LSLP_MEM_PD_M  (BIT(2))
+#define SYS_CLKRST_JPEG_LSLP_MEM_PD_V  0x1
+#define SYS_CLKRST_JPEG_LSLP_MEM_PD_S  2
+/* SYS_CLKRST_PPA_LSLP_MEM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_PPA_LSLP_MEM_PD    (BIT(1))
+#define SYS_CLKRST_PPA_LSLP_MEM_PD_M  (BIT(1))
+#define SYS_CLKRST_PPA_LSLP_MEM_PD_V  0x1
+#define SYS_CLKRST_PPA_LSLP_MEM_PD_S  1
+/* SYS_CLKRST_DMA2D_LSLP_MEM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_DMA2D_LSLP_MEM_PD    (BIT(0))
+#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_M  (BIT(0))
+#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_V  0x1
+#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_S  0
+
+#define SYS_CLKRST_ECO_CELL_EN_AND_DATA_REG          (DR_REG_SYS_CLKRST_BASE + 0x70)
+/* SYS_CLKRST_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_CLK_EN    (BIT(3))
+#define SYS_CLKRST_CLK_EN_M  (BIT(3))
+#define SYS_CLKRST_CLK_EN_V  0x1
+#define SYS_CLKRST_CLK_EN_S  3
+/* SYS_CLKRST_BIT_IN : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_BIT_IN    (BIT(2))
+#define SYS_CLKRST_BIT_IN_M  (BIT(2))
+#define SYS_CLKRST_BIT_IN_V  0x1
+#define SYS_CLKRST_BIT_IN_S  2
+/* SYS_CLKRST_BIT_OUT : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_BIT_OUT    (BIT(1))
+#define SYS_CLKRST_BIT_OUT_M  (BIT(1))
+#define SYS_CLKRST_BIT_OUT_V  0x1
+#define SYS_CLKRST_BIT_OUT_S  1
+/* SYS_CLKRST_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: .*/
+#define SYS_CLKRST_EN    (BIT(0))
+#define SYS_CLKRST_EN_M  (BIT(0))
+#define SYS_CLKRST_EN_V  0x1
+#define SYS_CLKRST_EN_S  0
+
+#define SYS_CLKRST_USB_MEM_AUX_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x74)
+/* SYS_CLKRST_OTG_PHY_BISTEN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_OTG_PHY_BISTEN    (BIT(15))
+#define SYS_CLKRST_OTG_PHY_BISTEN_M  (BIT(15))
+#define SYS_CLKRST_OTG_PHY_BISTEN_V  0x1
+#define SYS_CLKRST_OTG_PHY_BISTEN_S  15
+/* SYS_CLKRST_OTG_PHY_TEST_DONE : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_OTG_PHY_TEST_DONE    (BIT(14))
+#define SYS_CLKRST_OTG_PHY_TEST_DONE_M  (BIT(14))
+#define SYS_CLKRST_OTG_PHY_TEST_DONE_V  0x1
+#define SYS_CLKRST_OTG_PHY_TEST_DONE_S  14
+/* SYS_CLKRST_USB_MEM_AUX_CTRL : R/W ;bitpos:[13:0] ;default: 14'h1320 ; */
+/*description: .*/
+#define SYS_CLKRST_USB_MEM_AUX_CTRL    0x00003FFF
+#define SYS_CLKRST_USB_MEM_AUX_CTRL_M  ((SYS_CLKRST_USB_MEM_AUX_CTRL_V)<<(SYS_CLKRST_USB_MEM_AUX_CTRL_S))
+#define SYS_CLKRST_USB_MEM_AUX_CTRL_V  0x3FFF
+#define SYS_CLKRST_USB_MEM_AUX_CTRL_S  0
+
+#define SYS_CLKRST_DUAL_MSPI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x78)
+/* SYS_CLKRST_DUAL_MSPI_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST    (BIT(2))
+#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_M  (BIT(2))
+#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_V  0x1
+#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_S  2
+/* SYS_CLKRST_DUAL_MSPI_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_DUAL_MSPI_RSTN    (BIT(1))
+#define SYS_CLKRST_DUAL_MSPI_RSTN_M  (BIT(1))
+#define SYS_CLKRST_DUAL_MSPI_RSTN_V  0x1
+#define SYS_CLKRST_DUAL_MSPI_RSTN_S  1
+/* SYS_CLKRST_DUAL_MSPI_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN    (BIT(0))
+#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_M  (BIT(0))
+#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_V  0x1
+#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_S  0
+
+#define SYS_CLKRST_HP_PERI_RDN_ECO_CS_REG          (DR_REG_SYS_CLKRST_BASE + 0x7C)
+/* SYS_CLKRST_HP_PERI_RDN_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT    (BIT(1))
+#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_M  (BIT(1))
+#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_V  0x1
+#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_S  1
+/* SYS_CLKRST_HP_PERI_RDN_ECO_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_HP_PERI_RDN_ECO_EN    (BIT(0))
+#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_M  (BIT(0))
+#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_V  0x1
+#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_S  0
+
+#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_REG          (DR_REG_SYS_CLKRST_BASE + 0x80)
+/* SYS_CLKRST_HP_PERI_RDN_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW    0xFFFFFFFF
+#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_M  ((SYS_CLKRST_HP_PERI_RDN_ECO_LOW_V)<<(SYS_CLKRST_HP_PERI_RDN_ECO_LOW_S))
+#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_V  0xFFFFFFFF
+#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_S  0
+
+#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_REG          (DR_REG_SYS_CLKRST_BASE + 0x84)
+/* SYS_CLKRST_HP_PERI_RDN_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: .*/
+#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH    0xFFFFFFFF
+#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_M  ((SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_V)<<(SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_S))
+#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_V  0xFFFFFFFF
+#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYS_CLKRST_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/system_reg.h b/components/soc/esp32p4/include/soc/system_reg.h
new file mode 100644
index 0000000000..195ca330c6
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/system_reg.h
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "soc/hp_system_reg.h"
diff --git a/components/soc/esp32p4/include/soc/systimer_reg.h b/components/soc/esp32p4/include/soc/systimer_reg.h
new file mode 100644
index 0000000000..f7ea02d025
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/systimer_reg.h
@@ -0,0 +1,558 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTIMER_CONF_REG register
+ *  SYSTIMER_CONF.
+ */
+#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
+/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
+ *  systimer clock force on
+ */
+#define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
+#define SYSTIMER_SYSTIMER_CLK_FO_M  (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
+#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001
+#define SYSTIMER_SYSTIMER_CLK_FO_S  0
+/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
+ *  target2 work enable
+ */
+#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
+#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET2_WORK_EN_S  22
+/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
+ *  target1 work enable
+ */
+#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
+#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET1_WORK_EN_S  23
+/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
+ *  target0 work enable
+ */
+#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
+#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET0_WORK_EN_S  24
+/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
+ *  If timer unit1 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
+/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
+ *  If timer unit1 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
+/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
+ *  If timer unit0 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
+/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  If timer unit0 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
+/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
+ *  timer unit1 work enable
+ */
+#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
+/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
+ *  timer unit0 work enable
+ */
+#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
+/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  register file clk gating
+ */
+#define SYSTIMER_CLK_EN    (BIT(31))
+#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
+#define SYSTIMER_CLK_EN_V  0x00000001
+#define SYSTIMER_CLK_EN_S  31
+
+/** SYSTIMER_UNIT0_OP_REG register
+ *  SYSTIMER_UNIT0_OP.
+ */
+#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
+/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  reg_timer_unit0_value_valid
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer_unit0
+ */
+#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
+
+/** SYSTIMER_UNIT1_OP_REG register
+ *  SYSTIMER_UNIT1_OP.
+ */
+#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
+/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer unit1
+ */
+#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
+
+/** SYSTIMER_UNIT0_LOAD_HI_REG register
+ *  SYSTIMER_UNIT0_LOAD_HI.
+ */
+#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
+/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit0 load high 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT0_LOAD_LO_REG register
+ *  SYSTIMER_UNIT0_LOAD_LO.
+ */
+#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
+/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit0 load low 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
+
+/** SYSTIMER_UNIT1_LOAD_HI_REG register
+ *  SYSTIMER_UNIT1_LOAD_HI.
+ */
+#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
+/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit1 load high 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT1_LOAD_LO_REG register
+ *  SYSTIMER_UNIT1_LOAD_LO.
+ */
+#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
+/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit1 load low 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
+
+/** SYSTIMER_TARGET0_HI_REG register
+ *  SYSTIMER_TARGET0_HI.
+ */
+#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
+/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget0 high 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
+#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI_S  0
+
+/** SYSTIMER_TARGET0_LO_REG register
+ *  SYSTIMER_TARGET0_LO.
+ */
+#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
+/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget0 low 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
+#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO_S  0
+
+/** SYSTIMER_TARGET1_HI_REG register
+ *  SYSTIMER_TARGET1_HI.
+ */
+#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
+/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget1 high 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
+#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI_S  0
+
+/** SYSTIMER_TARGET1_LO_REG register
+ *  SYSTIMER_TARGET1_LO.
+ */
+#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
+/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget1 low 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
+#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO_S  0
+
+/** SYSTIMER_TARGET2_HI_REG register
+ *  SYSTIMER_TARGET2_HI.
+ */
+#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
+/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget2 high 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
+#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI_S  0
+
+/** SYSTIMER_TARGET2_LO_REG register
+ *  SYSTIMER_TARGET2_LO.
+ */
+#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
+/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget2 low 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
+#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO_S  0
+
+/** SYSTIMER_TARGET0_CONF_REG register
+ *  SYSTIMER_TARGET0_CONF.
+ */
+#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
+/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target0 period
+ */
+#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
+#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_S  0
+/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target0 to period mode
+ */
+#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET1_CONF_REG register
+ *  SYSTIMER_TARGET1_CONF.
+ */
+#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
+/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target1 period
+ */
+#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
+#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_S  0
+/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target1 to period mode
+ */
+#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET2_CONF_REG register
+ *  SYSTIMER_TARGET2_CONF.
+ */
+#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
+/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target2 period
+ */
+#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
+#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_S  0
+/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target2 to period mode
+ */
+#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_UNIT0_VALUE_HI_REG register
+ *  SYSTIMER_UNIT0_VALUE_HI.
+ */
+#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
+/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 32bit
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT0_VALUE_LO_REG register
+ *  SYSTIMER_UNIT0_VALUE_LO.
+ */
+#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
+/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bit
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
+
+/** SYSTIMER_UNIT1_VALUE_HI_REG register
+ *  SYSTIMER_UNIT1_VALUE_HI.
+ */
+#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
+/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 32bit
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT1_VALUE_LO_REG register
+ *  SYSTIMER_UNIT1_VALUE_LO.
+ */
+#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
+/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bit
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
+
+/** SYSTIMER_COMP0_LOAD_REG register
+ *  SYSTIMER_COMP0_LOAD.
+ */
+#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
+/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp0 load value
+ */
+#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
+#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP0_LOAD_S  0
+
+/** SYSTIMER_COMP1_LOAD_REG register
+ *  SYSTIMER_COMP1_LOAD.
+ */
+#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
+/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp1 load value
+ */
+#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
+#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP1_LOAD_S  0
+
+/** SYSTIMER_COMP2_LOAD_REG register
+ *  SYSTIMER_COMP2_LOAD.
+ */
+#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
+/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp2 load value
+ */
+#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
+#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP2_LOAD_S  0
+
+/** SYSTIMER_UNIT0_LOAD_REG register
+ *  SYSTIMER_UNIT0_LOAD.
+ */
+#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
+/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit0 load value
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
+
+/** SYSTIMER_UNIT1_LOAD_REG register
+ *  SYSTIMER_UNIT1_LOAD.
+ */
+#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
+/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit1 load value
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
+
+/** SYSTIMER_INT_ENA_REG register
+ *  SYSTIMER_INT_ENA.
+ */
+#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
+/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  interupt0 enable
+ */
+#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
+#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ENA_S  0
+/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  interupt1 enable
+ */
+#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
+#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ENA_S  1
+/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  interupt2 enable
+ */
+#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
+#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ENA_S  2
+
+/** SYSTIMER_INT_RAW_REG register
+ *  SYSTIMER_INT_RAW.
+ */
+#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
+/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  interupt0 raw
+ */
+#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
+#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET0_INT_RAW_S  0
+/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  interupt1 raw
+ */
+#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
+#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET1_INT_RAW_S  1
+/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  interupt2 raw
+ */
+#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
+#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET2_INT_RAW_S  2
+
+/** SYSTIMER_INT_CLR_REG register
+ *  SYSTIMER_INT_CLR.
+ */
+#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
+/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  interupt0 clear
+ */
+#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
+#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET0_INT_CLR_S  0
+/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  interupt1 clear
+ */
+#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
+#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET1_INT_CLR_S  1
+/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  interupt2 clear
+ */
+#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
+#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET2_INT_CLR_S  2
+
+/** SYSTIMER_INT_ST_REG register
+ *  SYSTIMER_INT_ST.
+ */
+#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
+/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  reg_target0_int_st
+ */
+#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
+#define SYSTIMER_TARGET0_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ST_S  0
+/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  reg_target1_int_st
+ */
+#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
+#define SYSTIMER_TARGET1_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ST_S  1
+/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  reg_target2_int_st
+ */
+#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
+#define SYSTIMER_TARGET2_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ST_S  2
+
+/** SYSTIMER_DATE_REG register
+ *  SYSTIMER_DATE.
+ */
+#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
+/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377;
+ *  reg_date
+ */
+#define SYSTIMER_DATE    0xFFFFFFFF
+#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
+#define SYSTIMER_DATE_V  0xFFFFFFFF
+#define SYSTIMER_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/systimer_struct.h b/components/soc/esp32p4/include/soc/systimer_struct.h
new file mode 100644
index 0000000000..cd4cf5d507
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/systimer_struct.h
@@ -0,0 +1,375 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Configuration Register */
+/** Type of conf register
+ *  SYSTIMER_CONF.
+ */
+typedef union {
+    struct {
+        /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
+         *  systimer clock force on
+         */
+        uint32_t systimer_clk_fo: 1;
+        uint32_t reserved_1: 21;
+        /** target2_work_en : R/W; bitpos: [22]; default: 0;
+         *  target2 work enable
+         */
+        uint32_t target2_work_en: 1;
+        /** target1_work_en : R/W; bitpos: [23]; default: 0;
+         *  target1 work enable
+         */
+        uint32_t target1_work_en: 1;
+        /** target0_work_en : R/W; bitpos: [24]; default: 0;
+         *  target0 work enable
+         */
+        uint32_t target0_work_en: 1;
+        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
+         *  If timer unit1 is stalled when core1 stalled
+         */
+        uint32_t timer_unit1_core1_stall_en: 1;
+        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
+         *  If timer unit1 is stalled when core0 stalled
+         */
+        uint32_t timer_unit1_core0_stall_en: 1;
+        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
+         *  If timer unit0 is stalled when core1 stalled
+         */
+        uint32_t timer_unit0_core1_stall_en: 1;
+        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
+         *  If timer unit0 is stalled when core0 stalled
+         */
+        uint32_t timer_unit0_core0_stall_en: 1;
+        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
+         *  timer unit1 work enable
+         */
+        uint32_t timer_unit1_work_en: 1;
+        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
+         *  timer unit0 work enable
+         */
+        uint32_t timer_unit0_work_en: 1;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  register file clk gating
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} systimer_conf_reg_t;
+
+/** Type of unit_op register
+ *  SYSTIMER_UNIT_OP.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 29;
+        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
+         *  reg_timer_unit0_value_valid
+         */
+        uint32_t timer_unit_value_valid: 1;
+        /** timer_unit_update : WT; bitpos: [30]; default: 0;
+         *  update timer_unit0
+         */
+        uint32_t timer_unit_update: 1;
+        uint32_t reserved31: 1;
+    };
+    uint32_t val;
+} systimer_unit_op_reg_t;
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer unit load high 32 bit
+             */
+            uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer unit load low 32 bit
+             */
+            uint32_t timer_unit_load_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_load_val_reg_t;
+
+/** Type of target register
+ *  SYSTIMER_TARGET.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer target high 32 bit
+             */
+            uint32_t timer_target_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer target low 32 bit
+             */
+            uint32_t timer_target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_target_val_reg_t;
+
+/** Type of target_conf register
+ *  SYSTIMER_TARGET_CONF.
+ */
+typedef union {
+    struct {
+        /** target_period : R/W; bitpos: [25:0]; default: 0;
+         *  target period
+         */
+        uint32_t target_period: 26;
+        uint32_t reserved_26: 4;
+        /** target_period_mode : R/W; bitpos: [30]; default: 0;
+         *  Set target to period mode
+         */
+        uint32_t target_period_mode: 1;
+        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
+         *  select which unit to compare
+         */
+        uint32_t target_timer_unit_sel: 1;
+    };
+    uint32_t val;
+} systimer_target_conf_reg_t;
+
+/** Type of unit_value_hi register
+ *  SYSTIMER_UNIT_VALUE_HI.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
+             *  timer read value high 20bit
+             */
+            uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
+             *  timer read value low 32bit
+             */
+            uint32_t timer_unit_value_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_value_reg_t;
+
+/** Type of comp_load register
+ *  SYSTIMER_COMP_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_comp_load : WT; bitpos: [0]; default: 0;
+         *  timer comp load value
+         */
+        uint32_t timer_comp_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_comp_load_reg_t;
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_unit_load : WT; bitpos: [0]; default: 0;
+         *  timer unit load value
+         */
+        uint32_t timer_unit_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_unit_load_reg_t;
+
+/** Interrupt Register */
+/** Type of int_ena register
+ *  SYSTIMER_INT_ENA.
+ */
+typedef union {
+    struct {
+        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  interupt0 enable
+         */
+        uint32_t target0_int_ena: 1;
+        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  interupt1 enable
+         */
+        uint32_t target1_int_ena: 1;
+        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  interupt2 enable
+         */
+        uint32_t target2_int_ena: 1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  SYSTIMER_INT_RAW.
+ */
+typedef union {
+    struct {
+        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  interupt0 raw
+         */
+        uint32_t target0_int_raw: 1;
+        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  interupt1 raw
+         */
+        uint32_t target1_int_raw: 1;
+        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  interupt2 raw
+         */
+        uint32_t target2_int_raw: 1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  SYSTIMER_INT_CLR.
+ */
+typedef union {
+    struct {
+        /** target0_int_clr : WT; bitpos: [0]; default: 0;
+         *  interupt0 clear
+         */
+        uint32_t target0_int_clr: 1;
+        /** target1_int_clr : WT; bitpos: [1]; default: 0;
+         *  interupt1 clear
+         */
+        uint32_t target1_int_clr: 1;
+        /** target2_int_clr : WT; bitpos: [2]; default: 0;
+         *  interupt2 clear
+         */
+        uint32_t target2_int_clr: 1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_clr_reg_t;
+
+/** Type of int_st register
+ *  SYSTIMER_INT_ST.
+ */
+typedef union {
+    struct {
+        /** target0_int_st : RO; bitpos: [0]; default: 0;
+         *  reg_target0_int_st
+         */
+        uint32_t target0_int_st: 1;
+        /** target1_int_st : RO; bitpos: [1]; default: 0;
+         *  reg_target1_int_st
+         */
+        uint32_t target1_int_st: 1;
+        /** target2_int_st : RO; bitpos: [2]; default: 0;
+         *  reg_target2_int_st
+         */
+        uint32_t target2_int_st: 1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_st_reg_t;
+
+
+/** Version Register */
+/** Type of date register
+ *  SYSTIMER_DATE.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 33579377;
+         *  reg_date
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} systimer_date_reg_t;
+
+
+typedef struct systimer_dev_t {
+    volatile systimer_conf_reg_t conf;
+    volatile systimer_unit_op_reg_t unit_op[2];
+    volatile systimer_unit_load_val_reg_t unit_load_val[2];
+    volatile systimer_target_val_reg_t target_val[3];
+    volatile systimer_target_conf_reg_t target_conf[3];
+    volatile systimer_unit_value_reg_t unit_val[2];
+    volatile systimer_comp_load_reg_t comp_load[3];
+    volatile systimer_unit_load_reg_t unit_load[2];
+    volatile systimer_int_ena_reg_t int_ena;
+    volatile systimer_int_raw_reg_t int_raw;
+    volatile systimer_int_clr_reg_t int_clr;
+    volatile systimer_int_st_reg_t int_st;
+    uint32_t reserved_074;
+    uint32_t reserved_078;
+    uint32_t reserved_07c;
+    uint32_t reserved_080;
+    uint32_t reserved_084;
+    uint32_t reserved_088;
+    uint32_t reserved_08c;
+    uint32_t reserved_090;
+    uint32_t reserved_094;
+    uint32_t reserved_098;
+    uint32_t reserved_09c;
+    uint32_t reserved_0a0;
+    uint32_t reserved_0a4;
+    uint32_t reserved_0a8;
+    uint32_t reserved_0ac;
+    uint32_t reserved_0b0;
+    uint32_t reserved_0b4;
+    uint32_t reserved_0b8;
+    uint32_t reserved_0bc;
+    uint32_t reserved_0c0;
+    uint32_t reserved_0c4;
+    uint32_t reserved_0c8;
+    uint32_t reserved_0cc;
+    uint32_t reserved_0d0;
+    uint32_t reserved_0d4;
+    uint32_t reserved_0d8;
+    uint32_t reserved_0dc;
+    uint32_t reserved_0e0;
+    uint32_t reserved_0e4;
+    uint32_t reserved_0e8;
+    uint32_t reserved_0ec;
+    uint32_t reserved_0f0;
+    uint32_t reserved_0f4;
+    uint32_t reserved_0f8;
+    volatile systimer_date_reg_t date;
+} systimer_dev_t;
+
+extern systimer_dev_t SYSTIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/tee_reg.h b/components/soc/esp32p4/include/soc/tee_reg.h
new file mode 100644
index 0000000000..553ad23442
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/tee_reg.h
@@ -0,0 +1,455 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_M0_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M0_MODE    0x00000003U
+#define TEE_M0_MODE_M  (TEE_M0_MODE_V << TEE_M0_MODE_S)
+#define TEE_M0_MODE_V  0x00000003U
+#define TEE_M0_MODE_S  0
+
+/** TEE_M1_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M1_MODE    0x00000003U
+#define TEE_M1_MODE_M  (TEE_M1_MODE_V << TEE_M1_MODE_S)
+#define TEE_M1_MODE_V  0x00000003U
+#define TEE_M1_MODE_S  0
+
+/** TEE_M2_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M2_MODE    0x00000003U
+#define TEE_M2_MODE_M  (TEE_M2_MODE_V << TEE_M2_MODE_S)
+#define TEE_M2_MODE_V  0x00000003U
+#define TEE_M2_MODE_S  0
+
+/** TEE_M3_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
+/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M3_MODE    0x00000003U
+#define TEE_M3_MODE_M  (TEE_M3_MODE_V << TEE_M3_MODE_S)
+#define TEE_M3_MODE_V  0x00000003U
+#define TEE_M3_MODE_S  0
+
+/** TEE_M4_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
+/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M4_MODE    0x00000003U
+#define TEE_M4_MODE_M  (TEE_M4_MODE_V << TEE_M4_MODE_S)
+#define TEE_M4_MODE_V  0x00000003U
+#define TEE_M4_MODE_S  0
+
+/** TEE_M5_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
+/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M5_MODE    0x00000003U
+#define TEE_M5_MODE_M  (TEE_M5_MODE_V << TEE_M5_MODE_S)
+#define TEE_M5_MODE_V  0x00000003U
+#define TEE_M5_MODE_S  0
+
+/** TEE_M6_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
+/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M6_MODE    0x00000003U
+#define TEE_M6_MODE_M  (TEE_M6_MODE_V << TEE_M6_MODE_S)
+#define TEE_M6_MODE_V  0x00000003U
+#define TEE_M6_MODE_S  0
+
+/** TEE_M7_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
+/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M7_MODE    0x00000003U
+#define TEE_M7_MODE_M  (TEE_M7_MODE_V << TEE_M7_MODE_S)
+#define TEE_M7_MODE_V  0x00000003U
+#define TEE_M7_MODE_S  0
+
+/** TEE_M8_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
+/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M8_MODE    0x00000003U
+#define TEE_M8_MODE_M  (TEE_M8_MODE_V << TEE_M8_MODE_S)
+#define TEE_M8_MODE_V  0x00000003U
+#define TEE_M8_MODE_S  0
+
+/** TEE_M9_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
+/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M9_MODE    0x00000003U
+#define TEE_M9_MODE_M  (TEE_M9_MODE_V << TEE_M9_MODE_S)
+#define TEE_M9_MODE_V  0x00000003U
+#define TEE_M9_MODE_S  0
+
+/** TEE_M10_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28)
+/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M10_MODE    0x00000003U
+#define TEE_M10_MODE_M  (TEE_M10_MODE_V << TEE_M10_MODE_S)
+#define TEE_M10_MODE_V  0x00000003U
+#define TEE_M10_MODE_S  0
+
+/** TEE_M11_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c)
+/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M11_MODE    0x00000003U
+#define TEE_M11_MODE_M  (TEE_M11_MODE_V << TEE_M11_MODE_S)
+#define TEE_M11_MODE_V  0x00000003U
+#define TEE_M11_MODE_S  0
+
+/** TEE_M12_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30)
+/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M12_MODE    0x00000003U
+#define TEE_M12_MODE_M  (TEE_M12_MODE_V << TEE_M12_MODE_S)
+#define TEE_M12_MODE_V  0x00000003U
+#define TEE_M12_MODE_S  0
+
+/** TEE_M13_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34)
+/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M13_MODE    0x00000003U
+#define TEE_M13_MODE_M  (TEE_M13_MODE_V << TEE_M13_MODE_S)
+#define TEE_M13_MODE_V  0x00000003U
+#define TEE_M13_MODE_S  0
+
+/** TEE_M14_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38)
+/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M14_MODE    0x00000003U
+#define TEE_M14_MODE_M  (TEE_M14_MODE_V << TEE_M14_MODE_S)
+#define TEE_M14_MODE_V  0x00000003U
+#define TEE_M14_MODE_S  0
+
+/** TEE_M15_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c)
+/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M15_MODE    0x00000003U
+#define TEE_M15_MODE_M  (TEE_M15_MODE_V << TEE_M15_MODE_S)
+#define TEE_M15_MODE_V  0x00000003U
+#define TEE_M15_MODE_S  0
+
+/** TEE_M16_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40)
+/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M16_MODE    0x00000003U
+#define TEE_M16_MODE_M  (TEE_M16_MODE_V << TEE_M16_MODE_S)
+#define TEE_M16_MODE_V  0x00000003U
+#define TEE_M16_MODE_S  0
+
+/** TEE_M17_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44)
+/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M17_MODE    0x00000003U
+#define TEE_M17_MODE_M  (TEE_M17_MODE_V << TEE_M17_MODE_S)
+#define TEE_M17_MODE_V  0x00000003U
+#define TEE_M17_MODE_S  0
+
+/** TEE_M18_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48)
+/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M18_MODE    0x00000003U
+#define TEE_M18_MODE_M  (TEE_M18_MODE_V << TEE_M18_MODE_S)
+#define TEE_M18_MODE_V  0x00000003U
+#define TEE_M18_MODE_S  0
+
+/** TEE_M19_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c)
+/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M19_MODE    0x00000003U
+#define TEE_M19_MODE_M  (TEE_M19_MODE_V << TEE_M19_MODE_S)
+#define TEE_M19_MODE_V  0x00000003U
+#define TEE_M19_MODE_S  0
+
+/** TEE_M20_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50)
+/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M20_MODE    0x00000003U
+#define TEE_M20_MODE_M  (TEE_M20_MODE_V << TEE_M20_MODE_S)
+#define TEE_M20_MODE_V  0x00000003U
+#define TEE_M20_MODE_S  0
+
+/** TEE_M21_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54)
+/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M21_MODE    0x00000003U
+#define TEE_M21_MODE_M  (TEE_M21_MODE_V << TEE_M21_MODE_S)
+#define TEE_M21_MODE_V  0x00000003U
+#define TEE_M21_MODE_S  0
+
+/** TEE_M22_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58)
+/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M22_MODE    0x00000003U
+#define TEE_M22_MODE_M  (TEE_M22_MODE_V << TEE_M22_MODE_S)
+#define TEE_M22_MODE_V  0x00000003U
+#define TEE_M22_MODE_S  0
+
+/** TEE_M23_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c)
+/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M23_MODE    0x00000003U
+#define TEE_M23_MODE_M  (TEE_M23_MODE_V << TEE_M23_MODE_S)
+#define TEE_M23_MODE_V  0x00000003U
+#define TEE_M23_MODE_S  0
+
+/** TEE_M24_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60)
+/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M24_MODE    0x00000003U
+#define TEE_M24_MODE_M  (TEE_M24_MODE_V << TEE_M24_MODE_S)
+#define TEE_M24_MODE_V  0x00000003U
+#define TEE_M24_MODE_S  0
+
+/** TEE_M25_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64)
+/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M25_MODE    0x00000003U
+#define TEE_M25_MODE_M  (TEE_M25_MODE_V << TEE_M25_MODE_S)
+#define TEE_M25_MODE_V  0x00000003U
+#define TEE_M25_MODE_S  0
+
+/** TEE_M26_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68)
+/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M26_MODE    0x00000003U
+#define TEE_M26_MODE_M  (TEE_M26_MODE_V << TEE_M26_MODE_S)
+#define TEE_M26_MODE_V  0x00000003U
+#define TEE_M26_MODE_S  0
+
+/** TEE_M27_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c)
+/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M27_MODE    0x00000003U
+#define TEE_M27_MODE_M  (TEE_M27_MODE_V << TEE_M27_MODE_S)
+#define TEE_M27_MODE_V  0x00000003U
+#define TEE_M27_MODE_S  0
+
+/** TEE_M28_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70)
+/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M28_MODE    0x00000003U
+#define TEE_M28_MODE_M  (TEE_M28_MODE_V << TEE_M28_MODE_S)
+#define TEE_M28_MODE_V  0x00000003U
+#define TEE_M28_MODE_S  0
+
+/** TEE_M29_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74)
+/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M29_MODE    0x00000003U
+#define TEE_M29_MODE_M  (TEE_M29_MODE_V << TEE_M29_MODE_S)
+#define TEE_M29_MODE_V  0x00000003U
+#define TEE_M29_MODE_S  0
+
+/** TEE_M30_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78)
+/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M30_MODE    0x00000003U
+#define TEE_M30_MODE_M  (TEE_M30_MODE_V << TEE_M30_MODE_S)
+#define TEE_M30_MODE_V  0x00000003U
+#define TEE_M30_MODE_S  0
+
+/** TEE_M31_MODE_CTRL_REG register
+ *  Tee mode control register
+ */
+#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c)
+/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+ *  tee_mode
+ */
+#define TEE_M31_MODE    0x00000003U
+#define TEE_M31_MODE_M  (TEE_M31_MODE_V << TEE_M31_MODE_S)
+#define TEE_M31_MODE_V  0x00000003U
+#define TEE_M31_MODE_S  0
+
+/** TEE_CLOCK_GATE_REG register
+ *  Clock gating register
+ */
+#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80)
+/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reg_clk_en
+ */
+#define TEE_CLK_EN    (BIT(0))
+#define TEE_CLK_EN_M  (TEE_CLK_EN_V << TEE_CLK_EN_S)
+#define TEE_CLK_EN_V  0x00000001U
+#define TEE_CLK_EN_S  0
+
+/** TEE_DATE_REG register
+ *  Version register
+ */
+#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc)
+/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706;
+ *  reg_tee_date
+ */
+#define TEE_DATE_REG_M  (TEE_DATE_REG_V << TEE_DATE_REG_S)
+#define TEE_DATE_REG_V  0x0FFFFFFFU
+#define TEE_DATE_REG_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/tee_struct.h b/components/soc/esp32p4/include/soc/tee_struct.h
new file mode 100644
index 0000000000..47f806da1a
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/tee_struct.h
@@ -0,0 +1,573 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Tee mode control register */
+/** Type of m0_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m0_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m0_mode_ctrl_reg_t;
+
+/** Type of m1_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m1_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m1_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m1_mode_ctrl_reg_t;
+
+/** Type of m2_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m2_mode : R/W; bitpos: [1:0]; default: 0;
+         *  M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m2_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m2_mode_ctrl_reg_t;
+
+/** Type of m3_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m3_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m3_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m3_mode_ctrl_reg_t;
+
+/** Type of m4_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m4_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m4_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m4_mode_ctrl_reg_t;
+
+/** Type of m5_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m5_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m5_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m5_mode_ctrl_reg_t;
+
+/** Type of m6_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m6_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m6_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m6_mode_ctrl_reg_t;
+
+/** Type of m7_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m7_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m7_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m7_mode_ctrl_reg_t;
+
+/** Type of m8_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m8_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m8_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m8_mode_ctrl_reg_t;
+
+/** Type of m9_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m9_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m9_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m9_mode_ctrl_reg_t;
+
+/** Type of m10_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m10_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m10_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m10_mode_ctrl_reg_t;
+
+/** Type of m11_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m11_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m11_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m11_mode_ctrl_reg_t;
+
+/** Type of m12_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m12_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m12_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m12_mode_ctrl_reg_t;
+
+/** Type of m13_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m13_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m13_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m13_mode_ctrl_reg_t;
+
+/** Type of m14_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m14_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m14_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m14_mode_ctrl_reg_t;
+
+/** Type of m15_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m15_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m15_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m15_mode_ctrl_reg_t;
+
+/** Type of m16_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m16_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m16_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m16_mode_ctrl_reg_t;
+
+/** Type of m17_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m17_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m17_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m17_mode_ctrl_reg_t;
+
+/** Type of m18_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m18_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m18_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m18_mode_ctrl_reg_t;
+
+/** Type of m19_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m19_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m19_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m19_mode_ctrl_reg_t;
+
+/** Type of m20_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m20_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m20_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m20_mode_ctrl_reg_t;
+
+/** Type of m21_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m21_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m21_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m21_mode_ctrl_reg_t;
+
+/** Type of m22_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m22_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m22_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m22_mode_ctrl_reg_t;
+
+/** Type of m23_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m23_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m23_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m23_mode_ctrl_reg_t;
+
+/** Type of m24_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m24_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m24_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m24_mode_ctrl_reg_t;
+
+/** Type of m25_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m25_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m25_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m25_mode_ctrl_reg_t;
+
+/** Type of m26_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m26_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m26_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m26_mode_ctrl_reg_t;
+
+/** Type of m27_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m27_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m27_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m27_mode_ctrl_reg_t;
+
+/** Type of m28_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m28_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m28_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m28_mode_ctrl_reg_t;
+
+/** Type of m29_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m29_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m29_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m29_mode_ctrl_reg_t;
+
+/** Type of m30_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m30_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m30_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m30_mode_ctrl_reg_t;
+
+/** Type of m31_mode_ctrl register
+ *  Tee mode control register
+ */
+typedef union {
+    struct {
+        /** m31_mode : R/W; bitpos: [1:0]; default: 3;
+         *  M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
+         *  tee_mode
+         */
+        uint32_t m31_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_m31_mode_ctrl_reg_t;
+
+
+/** Group: clock gating register */
+/** Type of clock_gate register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reg_clk_en
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date_reg : R/W; bitpos: [27:0]; default: 35672706;
+         *  reg_tee_date
+         */
+        uint32_t date_reg:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} tee_date_reg_t;
+
+
+typedef struct tee_dev_t {
+    volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
+    volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
+    volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;
+    volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl;
+    volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl;
+    volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl;
+    volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl;
+    volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl;
+    volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl;
+    volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl;
+    volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl;
+    volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl;
+    volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl;
+    volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl;
+    volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl;
+    volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl;
+    volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl;
+    volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl;
+    volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl;
+    volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl;
+    volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl;
+    volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl;
+    volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl;
+    volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl;
+    volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl;
+    volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl;
+    volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl;
+    volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl;
+    volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl;
+    volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl;
+    volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl;
+    volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl;
+    volatile tee_clock_gate_reg_t clock_gate;
+    uint32_t reserved_084[990];
+    volatile tee_date_reg_t date;
+} tee_dev_t;
+
+extern tee_dev_t TEE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/touch_reg.h b/components/soc/esp32p4/include/soc/touch_reg.h
new file mode 100644
index 0000000000..9decb192d8
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/touch_reg.h
@@ -0,0 +1,764 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTC_TOUCH_INT_RAW_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_RAW_REG (DR_REG_RTC_TOUCH_BASE + 0x0)
+/** RTC_TOUCH_SCAN_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_RAW    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_M  (RTC_TOUCH_SCAN_DONE_INT_RAW_V << RTC_TOUCH_SCAN_DONE_INT_RAW_S)
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_S  0
+/** RTC_TOUCH_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_RAW    (BIT(1))
+#define RTC_TOUCH_DONE_INT_RAW_M  (RTC_TOUCH_DONE_INT_RAW_V << RTC_TOUCH_DONE_INT_RAW_S)
+#define RTC_TOUCH_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_RAW_S  1
+/** RTC_TOUCH_ACTIVE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_RAW    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_RAW_M  (RTC_TOUCH_ACTIVE_INT_RAW_V << RTC_TOUCH_ACTIVE_INT_RAW_S)
+#define RTC_TOUCH_ACTIVE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_RAW_S  2
+/** RTC_TOUCH_INACTIVE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_RAW    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_RAW_M  (RTC_TOUCH_INACTIVE_INT_RAW_V << RTC_TOUCH_INACTIVE_INT_RAW_S)
+#define RTC_TOUCH_INACTIVE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_RAW_S  3
+/** RTC_TOUCH_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_RAW    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_RAW_M  (RTC_TOUCH_TIMEOUT_INT_RAW_V << RTC_TOUCH_TIMEOUT_INT_RAW_S)
+#define RTC_TOUCH_TIMEOUT_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_RAW_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S  5
+
+/** RTC_TOUCH_INT_ST_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_ST_REG (DR_REG_RTC_TOUCH_BASE + 0x4)
+/** RTC_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_ST    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_ST_M  (RTC_TOUCH_SCAN_DONE_INT_ST_V << RTC_TOUCH_SCAN_DONE_INT_ST_S)
+#define RTC_TOUCH_SCAN_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_ST_S  0
+/** RTC_TOUCH_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_ST    (BIT(1))
+#define RTC_TOUCH_DONE_INT_ST_M  (RTC_TOUCH_DONE_INT_ST_V << RTC_TOUCH_DONE_INT_ST_S)
+#define RTC_TOUCH_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_ST_S  1
+/** RTC_TOUCH_ACTIVE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_ST    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_ST_M  (RTC_TOUCH_ACTIVE_INT_ST_V << RTC_TOUCH_ACTIVE_INT_ST_S)
+#define RTC_TOUCH_ACTIVE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_ST_S  2
+/** RTC_TOUCH_INACTIVE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_ST    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_ST_M  (RTC_TOUCH_INACTIVE_INT_ST_V << RTC_TOUCH_INACTIVE_INT_ST_S)
+#define RTC_TOUCH_INACTIVE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_ST_S  3
+/** RTC_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_ST    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_ST_M  (RTC_TOUCH_TIMEOUT_INT_ST_V << RTC_TOUCH_TIMEOUT_INT_ST_S)
+#define RTC_TOUCH_TIMEOUT_INT_ST_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_ST_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S  5
+
+/** RTC_TOUCH_INT_ENA_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_ENA_REG (DR_REG_RTC_TOUCH_BASE + 0x8)
+/** RTC_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_ENA    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_M  (RTC_TOUCH_SCAN_DONE_INT_ENA_V << RTC_TOUCH_SCAN_DONE_INT_ENA_S)
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_S  0
+/** RTC_TOUCH_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_ENA    (BIT(1))
+#define RTC_TOUCH_DONE_INT_ENA_M  (RTC_TOUCH_DONE_INT_ENA_V << RTC_TOUCH_DONE_INT_ENA_S)
+#define RTC_TOUCH_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_ENA_S  1
+/** RTC_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_ENA    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_ENA_M  (RTC_TOUCH_ACTIVE_INT_ENA_V << RTC_TOUCH_ACTIVE_INT_ENA_S)
+#define RTC_TOUCH_ACTIVE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_ENA_S  2
+/** RTC_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_ENA    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_ENA_M  (RTC_TOUCH_INACTIVE_INT_ENA_V << RTC_TOUCH_INACTIVE_INT_ENA_S)
+#define RTC_TOUCH_INACTIVE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_ENA_S  3
+/** RTC_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_ENA    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_ENA_M  (RTC_TOUCH_TIMEOUT_INT_ENA_V << RTC_TOUCH_TIMEOUT_INT_ENA_S)
+#define RTC_TOUCH_TIMEOUT_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_ENA_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S  5
+
+/** RTC_TOUCH_INT_CLR_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_CLR_REG (DR_REG_RTC_TOUCH_BASE + 0xc)
+/** RTC_TOUCH_SCAN_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_CLR    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_M  (RTC_TOUCH_SCAN_DONE_INT_CLR_V << RTC_TOUCH_SCAN_DONE_INT_CLR_S)
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_S  0
+/** RTC_TOUCH_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_CLR    (BIT(1))
+#define RTC_TOUCH_DONE_INT_CLR_M  (RTC_TOUCH_DONE_INT_CLR_V << RTC_TOUCH_DONE_INT_CLR_S)
+#define RTC_TOUCH_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_CLR_S  1
+/** RTC_TOUCH_ACTIVE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_CLR    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_CLR_M  (RTC_TOUCH_ACTIVE_INT_CLR_V << RTC_TOUCH_ACTIVE_INT_CLR_S)
+#define RTC_TOUCH_ACTIVE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_CLR_S  2
+/** RTC_TOUCH_INACTIVE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_CLR    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_CLR_M  (RTC_TOUCH_INACTIVE_INT_CLR_V << RTC_TOUCH_INACTIVE_INT_CLR_S)
+#define RTC_TOUCH_INACTIVE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_CLR_S  3
+/** RTC_TOUCH_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_CLR    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_CLR_M  (RTC_TOUCH_TIMEOUT_INT_CLR_V << RTC_TOUCH_TIMEOUT_INT_CLR_S)
+#define RTC_TOUCH_TIMEOUT_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_CLR_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S  5
+
+/** RTC_TOUCH_CHN_STATUS_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_CHN_STATUS_REG (DR_REG_RTC_TOUCH_BASE + 0x10)
+/** RTC_TOUCH_PAD_ACTIVE : RO; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_ACTIVE    0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_M  (RTC_TOUCH_PAD_ACTIVE_V << RTC_TOUCH_PAD_ACTIVE_S)
+#define RTC_TOUCH_PAD_ACTIVE_V  0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_S  0
+/** RTC_TOUCH_MEAS_DONE : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_MEAS_DONE    (BIT(15))
+#define RTC_TOUCH_MEAS_DONE_M  (RTC_TOUCH_MEAS_DONE_V << RTC_TOUCH_MEAS_DONE_S)
+#define RTC_TOUCH_MEAS_DONE_V  0x00000001U
+#define RTC_TOUCH_MEAS_DONE_S  15
+/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_CURR    0x0000000FU
+#define RTC_TOUCH_SCAN_CURR_M  (RTC_TOUCH_SCAN_CURR_V << RTC_TOUCH_SCAN_CURR_S)
+#define RTC_TOUCH_SCAN_CURR_V  0x0000000FU
+#define RTC_TOUCH_SCAN_CURR_S  16
+
+/** RTC_TOUCH_STATUS_0_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_0_REG (DR_REG_RTC_TOUCH_BASE + 0x14)
+/** RTC_TOUCH_PAD0_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD0_DATA_M  (RTC_TOUCH_PAD0_DATA_V << RTC_TOUCH_PAD0_DATA_S)
+#define RTC_TOUCH_PAD0_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD0_DATA_S  0
+/** RTC_TOUCH_PAD0_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD0_DEBOUNCE_CNT_V << RTC_TOUCH_PAD0_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD0_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD0_NEG_NOISE_CNT_V << RTC_TOUCH_PAD0_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_1_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_1_REG (DR_REG_RTC_TOUCH_BASE + 0x18)
+/** RTC_TOUCH_PAD1_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD1_DATA_M  (RTC_TOUCH_PAD1_DATA_V << RTC_TOUCH_PAD1_DATA_S)
+#define RTC_TOUCH_PAD1_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD1_DATA_S  0
+/** RTC_TOUCH_PAD1_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD1_DEBOUNCE_CNT_V << RTC_TOUCH_PAD1_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD1_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD1_NEG_NOISE_CNT_V << RTC_TOUCH_PAD1_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_2_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_2_REG (DR_REG_RTC_TOUCH_BASE + 0x1c)
+/** RTC_TOUCH_PAD2_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD2_DATA_M  (RTC_TOUCH_PAD2_DATA_V << RTC_TOUCH_PAD2_DATA_S)
+#define RTC_TOUCH_PAD2_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD2_DATA_S  0
+/** RTC_TOUCH_PAD2_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD2_DEBOUNCE_CNT_V << RTC_TOUCH_PAD2_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD2_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD2_NEG_NOISE_CNT_V << RTC_TOUCH_PAD2_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_3_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_3_REG (DR_REG_RTC_TOUCH_BASE + 0x20)
+/** RTC_TOUCH_PAD3_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD3_DATA_M  (RTC_TOUCH_PAD3_DATA_V << RTC_TOUCH_PAD3_DATA_S)
+#define RTC_TOUCH_PAD3_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD3_DATA_S  0
+/** RTC_TOUCH_PAD3_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD3_DEBOUNCE_CNT_V << RTC_TOUCH_PAD3_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD3_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD3_NEG_NOISE_CNT_V << RTC_TOUCH_PAD3_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_4_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_4_REG (DR_REG_RTC_TOUCH_BASE + 0x24)
+/** RTC_TOUCH_PAD4_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD4_DATA_M  (RTC_TOUCH_PAD4_DATA_V << RTC_TOUCH_PAD4_DATA_S)
+#define RTC_TOUCH_PAD4_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD4_DATA_S  0
+/** RTC_TOUCH_PAD4_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD4_DEBOUNCE_CNT_V << RTC_TOUCH_PAD4_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD4_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD4_NEG_NOISE_CNT_V << RTC_TOUCH_PAD4_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_5_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_5_REG (DR_REG_RTC_TOUCH_BASE + 0x28)
+/** RTC_TOUCH_PAD5_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD5_DATA_M  (RTC_TOUCH_PAD5_DATA_V << RTC_TOUCH_PAD5_DATA_S)
+#define RTC_TOUCH_PAD5_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD5_DATA_S  0
+/** RTC_TOUCH_PAD5_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD5_DEBOUNCE_CNT_V << RTC_TOUCH_PAD5_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD5_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD5_NEG_NOISE_CNT_V << RTC_TOUCH_PAD5_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_6_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_6_REG (DR_REG_RTC_TOUCH_BASE + 0x2c)
+/** RTC_TOUCH_PAD6_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD6_DATA_M  (RTC_TOUCH_PAD6_DATA_V << RTC_TOUCH_PAD6_DATA_S)
+#define RTC_TOUCH_PAD6_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD6_DATA_S  0
+/** RTC_TOUCH_PAD6_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD6_DEBOUNCE_CNT_V << RTC_TOUCH_PAD6_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD6_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD6_NEG_NOISE_CNT_V << RTC_TOUCH_PAD6_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_7_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_7_REG (DR_REG_RTC_TOUCH_BASE + 0x30)
+/** RTC_TOUCH_PAD7_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD7_DATA_M  (RTC_TOUCH_PAD7_DATA_V << RTC_TOUCH_PAD7_DATA_S)
+#define RTC_TOUCH_PAD7_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD7_DATA_S  0
+/** RTC_TOUCH_PAD7_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD7_DEBOUNCE_CNT_V << RTC_TOUCH_PAD7_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD7_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD7_NEG_NOISE_CNT_V << RTC_TOUCH_PAD7_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_8_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_8_REG (DR_REG_RTC_TOUCH_BASE + 0x34)
+/** RTC_TOUCH_PAD8_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD8_DATA_M  (RTC_TOUCH_PAD8_DATA_V << RTC_TOUCH_PAD8_DATA_S)
+#define RTC_TOUCH_PAD8_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD8_DATA_S  0
+/** RTC_TOUCH_PAD8_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD8_DEBOUNCE_CNT_V << RTC_TOUCH_PAD8_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD8_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD8_NEG_NOISE_CNT_V << RTC_TOUCH_PAD8_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_9_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_9_REG (DR_REG_RTC_TOUCH_BASE + 0x38)
+/** RTC_TOUCH_PAD9_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD9_DATA_M  (RTC_TOUCH_PAD9_DATA_V << RTC_TOUCH_PAD9_DATA_S)
+#define RTC_TOUCH_PAD9_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD9_DATA_S  0
+/** RTC_TOUCH_PAD9_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD9_DEBOUNCE_CNT_V << RTC_TOUCH_PAD9_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD9_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD9_NEG_NOISE_CNT_V << RTC_TOUCH_PAD9_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_10_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_10_REG (DR_REG_RTC_TOUCH_BASE + 0x3c)
+/** RTC_TOUCH_PAD10_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD10_DATA_M  (RTC_TOUCH_PAD10_DATA_V << RTC_TOUCH_PAD10_DATA_S)
+#define RTC_TOUCH_PAD10_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD10_DATA_S  0
+/** RTC_TOUCH_PAD10_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD10_DEBOUNCE_CNT_V << RTC_TOUCH_PAD10_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD10_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD10_NEG_NOISE_CNT_V << RTC_TOUCH_PAD10_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_11_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_11_REG (DR_REG_RTC_TOUCH_BASE + 0x40)
+/** RTC_TOUCH_PAD11_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD11_DATA_M  (RTC_TOUCH_PAD11_DATA_V << RTC_TOUCH_PAD11_DATA_S)
+#define RTC_TOUCH_PAD11_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD11_DATA_S  0
+/** RTC_TOUCH_PAD11_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD11_DEBOUNCE_CNT_V << RTC_TOUCH_PAD11_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD11_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD11_NEG_NOISE_CNT_V << RTC_TOUCH_PAD11_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_12_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_12_REG (DR_REG_RTC_TOUCH_BASE + 0x44)
+/** RTC_TOUCH_PAD12_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD12_DATA_M  (RTC_TOUCH_PAD12_DATA_V << RTC_TOUCH_PAD12_DATA_S)
+#define RTC_TOUCH_PAD12_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD12_DATA_S  0
+/** RTC_TOUCH_PAD12_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD12_DEBOUNCE_CNT_V << RTC_TOUCH_PAD12_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD12_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD12_NEG_NOISE_CNT_V << RTC_TOUCH_PAD12_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_13_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_13_REG (DR_REG_RTC_TOUCH_BASE + 0x48)
+/** RTC_TOUCH_PAD13_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD13_DATA_M  (RTC_TOUCH_PAD13_DATA_V << RTC_TOUCH_PAD13_DATA_S)
+#define RTC_TOUCH_PAD13_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD13_DATA_S  0
+/** RTC_TOUCH_PAD13_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD13_DEBOUNCE_CNT_V << RTC_TOUCH_PAD13_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD13_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD13_NEG_NOISE_CNT_V << RTC_TOUCH_PAD13_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_14_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_14_REG (DR_REG_RTC_TOUCH_BASE + 0x4c)
+/** RTC_TOUCH_PAD14_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD14_DATA_M  (RTC_TOUCH_PAD14_DATA_V << RTC_TOUCH_PAD14_DATA_S)
+#define RTC_TOUCH_PAD14_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD14_DATA_S  0
+/** RTC_TOUCH_PAD14_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD14_DEBOUNCE_CNT_V << RTC_TOUCH_PAD14_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD14_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD14_NEG_NOISE_CNT_V << RTC_TOUCH_PAD14_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_15_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_15_REG (DR_REG_RTC_TOUCH_BASE + 0x50)
+/** RTC_TOUCH_SLP_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_DATA    0x0000FFFFU
+#define RTC_TOUCH_SLP_DATA_M  (RTC_TOUCH_SLP_DATA_V << RTC_TOUCH_SLP_DATA_S)
+#define RTC_TOUCH_SLP_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_SLP_DATA_S  0
+/** RTC_TOUCH_SLP_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_M  (RTC_TOUCH_SLP_DEBOUNCE_CNT_V << RTC_TOUCH_SLP_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_SLP_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_M  (RTC_TOUCH_SLP_NEG_NOISE_CNT_V << RTC_TOUCH_SLP_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_16_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_16_REG (DR_REG_RTC_TOUCH_BASE + 0x54)
+/** RTC_TOUCH_APPROACH_PAD2_CNT : RO; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD2_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD2_CNT_M  (RTC_TOUCH_APPROACH_PAD2_CNT_V << RTC_TOUCH_APPROACH_PAD2_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD2_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD2_CNT_S  0
+/** RTC_TOUCH_APPROACH_PAD1_CNT : RO; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD1_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD1_CNT_M  (RTC_TOUCH_APPROACH_PAD1_CNT_V << RTC_TOUCH_APPROACH_PAD1_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD1_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD1_CNT_S  8
+/** RTC_TOUCH_APPROACH_PAD0_CNT : RO; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD0_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD0_CNT_M  (RTC_TOUCH_APPROACH_PAD0_CNT_V << RTC_TOUCH_APPROACH_PAD0_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD0_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD0_CNT_S  16
+/** RTC_TOUCH_SLP_APPROACH_CNT : RO; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_APPROACH_CNT    0x000000FFU
+#define RTC_TOUCH_SLP_APPROACH_CNT_M  (RTC_TOUCH_SLP_APPROACH_CNT_V << RTC_TOUCH_SLP_APPROACH_CNT_S)
+#define RTC_TOUCH_SLP_APPROACH_CNT_V  0x000000FFU
+#define RTC_TOUCH_SLP_APPROACH_CNT_S  24
+
+/** RTC_TOUCH_STATUS_17_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_17_REG (DR_REG_RTC_TOUCH_BASE + 0x58)
+/** RTC_TOUCH_DCAP_LPF : RO; bitpos: [6:0]; default: 0;
+ *  Reserved
+ */
+#define RTC_TOUCH_DCAP_LPF    0x0000007FU
+#define RTC_TOUCH_DCAP_LPF_M  (RTC_TOUCH_DCAP_LPF_V << RTC_TOUCH_DCAP_LPF_S)
+#define RTC_TOUCH_DCAP_LPF_V  0x0000007FU
+#define RTC_TOUCH_DCAP_LPF_S  0
+/** RTC_TOUCH_DRES_LPF : RO; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRES_LPF    0x00000003U
+#define RTC_TOUCH_DRES_LPF_M  (RTC_TOUCH_DRES_LPF_V << RTC_TOUCH_DRES_LPF_S)
+#define RTC_TOUCH_DRES_LPF_V  0x00000003U
+#define RTC_TOUCH_DRES_LPF_S  7
+/** RTC_TOUCH_DRV_LS : RO; bitpos: [12:9]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRV_LS    0x0000000FU
+#define RTC_TOUCH_DRV_LS_M  (RTC_TOUCH_DRV_LS_V << RTC_TOUCH_DRV_LS_S)
+#define RTC_TOUCH_DRV_LS_V  0x0000000FU
+#define RTC_TOUCH_DRV_LS_S  9
+/** RTC_TOUCH_DRV_HS : RO; bitpos: [17:13]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRV_HS    0x0000001FU
+#define RTC_TOUCH_DRV_HS_M  (RTC_TOUCH_DRV_HS_V << RTC_TOUCH_DRV_HS_S)
+#define RTC_TOUCH_DRV_HS_V  0x0000001FU
+#define RTC_TOUCH_DRV_HS_S  13
+/** RTC_TOUCH_DBIAS : RO; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DBIAS    0x0000001FU
+#define RTC_TOUCH_DBIAS_M  (RTC_TOUCH_DBIAS_V << RTC_TOUCH_DBIAS_S)
+#define RTC_TOUCH_DBIAS_V  0x0000001FU
+#define RTC_TOUCH_DBIAS_S  18
+/** RTC_TOUCH_FREQ_SCAN_CNT : RO; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_FREQ_SCAN_CNT    0x00000003U
+#define RTC_TOUCH_FREQ_SCAN_CNT_M  (RTC_TOUCH_FREQ_SCAN_CNT_V << RTC_TOUCH_FREQ_SCAN_CNT_S)
+#define RTC_TOUCH_FREQ_SCAN_CNT_V  0x00000003U
+#define RTC_TOUCH_FREQ_SCAN_CNT_S  23
+
+/** RTC_TOUCH_CHN_TMP_STATUS_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_CHN_TMP_STATUS_REG (DR_REG_RTC_TOUCH_BASE + 0x5c)
+/** RTC_TOUCH_PAD_INACTIVE_STATUS : RO; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_INACTIVE_STATUS    0x00007FFFU
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_M  (RTC_TOUCH_PAD_INACTIVE_STATUS_V << RTC_TOUCH_PAD_INACTIVE_STATUS_S)
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_V  0x00007FFFU
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_S  0
+/** RTC_TOUCH_PAD_ACTIVE_STATUS : RO; bitpos: [29:15]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_ACTIVE_STATUS    0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_M  (RTC_TOUCH_PAD_ACTIVE_STATUS_V << RTC_TOUCH_PAD_ACTIVE_STATUS_S)
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_V  0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_S  15
+
+/** RTC_TOUCH_DATE_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_DATE_REG (DR_REG_RTC_TOUCH_BASE + 0x100)
+/** RTC_TOUCH_DATE : R/W; bitpos: [27:0]; default: 2294548;
+ *  need_des
+ */
+#define RTC_TOUCH_DATE    0x0FFFFFFFU
+#define RTC_TOUCH_DATE_M  (RTC_TOUCH_DATE_V << RTC_TOUCH_DATE_S)
+#define RTC_TOUCH_DATE_V  0x0FFFFFFFU
+#define RTC_TOUCH_DATE_S  0
+/** RTC_TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_CLK_EN    (BIT(31))
+#define RTC_TOUCH_CLK_EN_M  (RTC_TOUCH_CLK_EN_V << RTC_TOUCH_CLK_EN_S)
+#define RTC_TOUCH_CLK_EN_V  0x00000001U
+#define RTC_TOUCH_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/touch_struct.h b/components/soc/esp32p4/include/soc/touch_struct.h
new file mode 100644
index 0000000000..d94b69cfe6
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/touch_struct.h
@@ -0,0 +1,658 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_raw:1;
+        /** done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_raw:1;
+        /** active_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_raw:1;
+        /** inactive_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_raw:1;
+        /** timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_raw:1;
+        /** approach_loop_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_st : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_st:1;
+        /** done_int_st : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_st:1;
+        /** active_int_st : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_st:1;
+        /** inactive_int_st : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_st:1;
+        /** timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_st:1;
+        /** approach_loop_done_int_st : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_ena:1;
+        /** done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_ena:1;
+        /** active_int_ena : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_ena:1;
+        /** inactive_int_ena : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_ena:1;
+        /** timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_ena:1;
+        /** approach_loop_done_int_ena : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_clr:1;
+        /** done_int_clr : WT; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_clr:1;
+        /** active_int_clr : WT; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_clr:1;
+        /** inactive_int_clr : WT; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_clr:1;
+        /** timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_clr:1;
+        /** approach_loop_done_int_clr : WT; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_clr_reg_t;
+
+/** Type of chn_status register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad_active : RO; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_active:15;
+        /** meas_done : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t meas_done:1;
+        /** scan_curr : RO; bitpos: [19:16]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_curr:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} rtc_touch_chn_status_reg_t;
+
+/** Type of status_0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad0_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad0_data:16;
+        /** pad0_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad0_debounce_cnt:3;
+        /** pad0_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad0_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_0_reg_t;
+
+/** Type of status_1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad1_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad1_data:16;
+        /** pad1_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad1_debounce_cnt:3;
+        /** pad1_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad1_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_1_reg_t;
+
+/** Type of status_2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad2_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad2_data:16;
+        /** pad2_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad2_debounce_cnt:3;
+        /** pad2_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad2_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_2_reg_t;
+
+/** Type of status_3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad3_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad3_data:16;
+        /** pad3_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad3_debounce_cnt:3;
+        /** pad3_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad3_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_3_reg_t;
+
+/** Type of status_4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad4_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad4_data:16;
+        /** pad4_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad4_debounce_cnt:3;
+        /** pad4_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad4_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_4_reg_t;
+
+/** Type of status_5 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad5_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad5_data:16;
+        /** pad5_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad5_debounce_cnt:3;
+        /** pad5_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad5_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_5_reg_t;
+
+/** Type of status_6 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad6_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad6_data:16;
+        /** pad6_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad6_debounce_cnt:3;
+        /** pad6_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad6_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_6_reg_t;
+
+/** Type of status_7 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad7_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad7_data:16;
+        /** pad7_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad7_debounce_cnt:3;
+        /** pad7_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad7_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_7_reg_t;
+
+/** Type of status_8 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad8_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad8_data:16;
+        /** pad8_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad8_debounce_cnt:3;
+        /** pad8_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad8_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_8_reg_t;
+
+/** Type of status_9 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad9_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad9_data:16;
+        /** pad9_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad9_debounce_cnt:3;
+        /** pad9_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad9_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_9_reg_t;
+
+/** Type of status_10 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad10_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad10_data:16;
+        /** pad10_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad10_debounce_cnt:3;
+        /** pad10_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad10_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_10_reg_t;
+
+/** Type of status_11 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad11_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad11_data:16;
+        /** pad11_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad11_debounce_cnt:3;
+        /** pad11_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad11_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_11_reg_t;
+
+/** Type of status_12 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad12_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad12_data:16;
+        /** pad12_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad12_debounce_cnt:3;
+        /** pad12_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad12_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_12_reg_t;
+
+/** Type of status_13 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad13_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad13_data:16;
+        /** pad13_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad13_debounce_cnt:3;
+        /** pad13_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad13_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_13_reg_t;
+
+/** Type of status_14 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad14_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad14_data:16;
+        /** pad14_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad14_debounce_cnt:3;
+        /** pad14_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad14_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_14_reg_t;
+
+/** Type of status_15 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** slp_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_data:16;
+        /** slp_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_debounce_cnt:3;
+        /** slp_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_status_15_reg_t;
+
+/** Type of status_16 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** approach_pad2_cnt : RO; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad2_cnt:8;
+        /** approach_pad1_cnt : RO; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad1_cnt:8;
+        /** approach_pad0_cnt : RO; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad0_cnt:8;
+        /** slp_approach_cnt : RO; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_approach_cnt:8;
+    };
+    uint32_t val;
+} rtc_touch_status_16_reg_t;
+
+/** Type of status_17 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dcap_lpf : RO; bitpos: [6:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t dcap_lpf:7;
+        /** dres_lpf : RO; bitpos: [8:7]; default: 0;
+         *  need_des
+         */
+        uint32_t dres_lpf:2;
+        /** drv_ls : RO; bitpos: [12:9]; default: 0;
+         *  need_des
+         */
+        uint32_t drv_ls:4;
+        /** drv_hs : RO; bitpos: [17:13]; default: 0;
+         *  need_des
+         */
+        uint32_t drv_hs:5;
+        /** dbias : RO; bitpos: [22:18]; default: 0;
+         *  need_des
+         */
+        uint32_t dbias:5;
+        /** freq_scan_cnt : RO; bitpos: [24:23]; default: 0;
+         *  need_des
+         */
+        uint32_t freq_scan_cnt:2;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} rtc_touch_status_17_reg_t;
+
+/** Type of chn_tmp_status register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad_inactive_status : RO; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_inactive_status:15;
+        /** pad_active_status : RO; bitpos: [29:15]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_active_status:15;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rtc_touch_chn_tmp_status_reg_t;
+
+
+/** Group: Version */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2294548;
+         *  need_des
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:3;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rtc_touch_date_reg_t;
+
+
+typedef struct {
+    volatile rtc_touch_int_raw_reg_t int_raw;
+    volatile rtc_touch_int_st_reg_t int_st;
+    volatile rtc_touch_int_ena_reg_t int_ena;
+    volatile rtc_touch_int_clr_reg_t int_clr;
+    volatile rtc_touch_chn_status_reg_t chn_status;
+    volatile rtc_touch_status_0_reg_t status_0;
+    volatile rtc_touch_status_1_reg_t status_1;
+    volatile rtc_touch_status_2_reg_t status_2;
+    volatile rtc_touch_status_3_reg_t status_3;
+    volatile rtc_touch_status_4_reg_t status_4;
+    volatile rtc_touch_status_5_reg_t status_5;
+    volatile rtc_touch_status_6_reg_t status_6;
+    volatile rtc_touch_status_7_reg_t status_7;
+    volatile rtc_touch_status_8_reg_t status_8;
+    volatile rtc_touch_status_9_reg_t status_9;
+    volatile rtc_touch_status_10_reg_t status_10;
+    volatile rtc_touch_status_11_reg_t status_11;
+    volatile rtc_touch_status_12_reg_t status_12;
+    volatile rtc_touch_status_13_reg_t status_13;
+    volatile rtc_touch_status_14_reg_t status_14;
+    volatile rtc_touch_status_15_reg_t status_15;
+    volatile rtc_touch_status_16_reg_t status_16;
+    volatile rtc_touch_status_17_reg_t status_17;
+    volatile rtc_touch_chn_tmp_status_reg_t chn_tmp_status;
+    uint32_t reserved_060[40];
+    volatile rtc_touch_date_reg_t date;
+} rtc_touch_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtc_touch_dev_t) == 0x104, "Invalid size of rtc_touch_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/trace_reg.h b/components/soc/esp32p4/include/soc/trace_reg.h
new file mode 100644
index 0000000000..c0f45143e9
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/trace_reg.h
@@ -0,0 +1,463 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TRACE_MEM_START_ADDR_REG register
+ *  mem start addr
+ */
+#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
+/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of trace memory
+ */
+#define TRACE_MEM_START_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_M  (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
+#define TRACE_MEM_START_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_S  0
+
+/** TRACE_MEM_END_ADDR_REG register
+ *  mem end addr
+ */
+#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
+/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The end address of trace memory
+ */
+#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
+#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_S  0
+
+/** TRACE_MEM_CURRENT_ADDR_REG register
+ *  mem current addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
+/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  current_mem_addr,indicate that next writing addr
+ */
+#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
+#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_S  0
+
+/** TRACE_MEM_ADDR_UPDATE_REG register
+ *  mem addr update
+ */
+#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
+/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  when set, the  will
+ *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
+ *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
+ */
+#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
+
+/** TRACE_FIFO_STATUS_REG register
+ *  fifo status register
+ */
+#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
+/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Represent whether the fifo is empty. \\1: empty \\0: not empty
+ */
+#define TRACE_FIFO_EMPTY    (BIT(0))
+#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
+#define TRACE_FIFO_EMPTY_V  0x00000001U
+#define TRACE_FIFO_EMPTY_S  0
+/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
+ *  Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due
+ *  to hart halted or havereset \\3: lost state
+ */
+#define TRACE_WORK_STATUS    0x00000003U
+#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
+#define TRACE_WORK_STATUS_V  0x00000003U
+#define TRACE_WORK_STATUS_S  1
+
+/** TRACE_INTR_ENA_REG register
+ *  interrupt enable register
+ */
+#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
+/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set 1 enable fifo_overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
+/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 enable mem_full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
+#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
+#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_ENA_S  1
+
+/** TRACE_INTR_RAW_REG register
+ *  interrupt status register
+ */
+#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
+/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
+ *  fifo_overflow interrupt status
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
+/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
+ *  mem_full interrupt status
+ */
+#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
+#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
+#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_RAW_S  1
+
+/** TRACE_INTR_CLR_REG register
+ *  interrupt clear register
+ */
+#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
+/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
+ *  Set 1 clear fifo overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
+/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
+ *  Set 1 clear mem full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
+#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
+#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_CLR_S  1
+
+/** TRACE_TRIGGER_REG register
+ *  trigger register
+ */
+#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
+/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
+ *  Configure whether or not start trace.\\1: start trace \\0: invalid\\
+ */
+#define TRACE_TRIGGER_ON    (BIT(0))
+#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
+#define TRACE_TRIGGER_ON_V  0x00000001U
+#define TRACE_TRIGGER_ON_S  0
+/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
+ *  Configure whether or not stop trace.\\1: stop trace \\0: invalid\\
+ */
+#define TRACE_TRIGGER_OFF    (BIT(1))
+#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
+#define TRACE_TRIGGER_OFF_V  0x00000001U
+#define TRACE_TRIGGER_OFF_S  1
+/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
+ *  Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when
+ *  mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\
+ */
+#define TRACE_MEM_LOOP    (BIT(2))
+#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
+#define TRACE_MEM_LOOP_V  0x00000001U
+#define TRACE_MEM_LOOP_S  2
+/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
+ *  Configure whether or not enable auto-restart.\\1: enable\\0: disable\\
+ */
+#define TRACE_RESTART_ENA    (BIT(3))
+#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
+#define TRACE_RESTART_ENA_V  0x00000001U
+#define TRACE_RESTART_ENA_S  3
+
+/** TRACE_CONFIG_REG register
+ *  trace configuration register
+ */
+#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24)
+/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\
+ */
+#define TRACE_DM_TRIGGER_ENA    (BIT(0))
+#define TRACE_DM_TRIGGER_ENA_M  (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
+#define TRACE_DM_TRIGGER_ENA_V  0x00000001U
+#define TRACE_DM_TRIGGER_ENA_S  0
+/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not enable trace cpu haverest, when enabeld, if cpu have
+ *  reset, the encoder will output a packet to report the address of the last
+ *  instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0:
+ *  disabled\\
+ */
+#define TRACE_RESET_ENA    (BIT(1))
+#define TRACE_RESET_ENA_M  (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
+#define TRACE_RESET_ENA_V  0x00000001U
+#define TRACE_RESET_ENA_S  1
+/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Configure whether or not enable trace cpu is halted, when enabeld, if the cpu
+ *  halted, the encoder will output a packet to report the address of the last
+ *  instruction, and upon halted deassertion, the encoder start again.When disabled,
+ *  encoder will not report the last address before halted and first address after
+ *  halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\
+ */
+#define TRACE_HALT_ENA    (BIT(2))
+#define TRACE_HALT_ENA_M  (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
+#define TRACE_HALT_ENA_V  0x00000001U
+#define TRACE_HALT_ENA_S  2
+/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
+ *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
+ *  the cpu will be stalled until the packets is able to write to fifo.\\1:
+ *  enabled.\\0: disabled\\
+ */
+#define TRACE_STALL_ENA    (BIT(3))
+#define TRACE_STALL_ENA_M  (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
+#define TRACE_STALL_ENA_V  0x00000001U
+#define TRACE_STALL_ENA_S  3
+/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
+ *  Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta
+ *  address mode\\
+ */
+#define TRACE_FULL_ADDRESS    (BIT(4))
+#define TRACE_FULL_ADDRESS_M  (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
+#define TRACE_FULL_ADDRESS_V  0x00000001U
+#define TRACE_FULL_ADDRESS_S  4
+/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
+ *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
+ *  exception address, only exception cause in exception packets.\\1: enabled\\0:
+ *  disabled\\
+ */
+#define TRACE_IMPLICIT_EXCEPT    (BIT(5))
+#define TRACE_IMPLICIT_EXCEPT_M  (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
+#define TRACE_IMPLICIT_EXCEPT_V  0x00000001U
+#define TRACE_IMPLICIT_EXCEPT_S  5
+
+/** TRACE_FILTER_CONTROL_REG register
+ *  filter control register
+ */
+#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28)
+/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match
+ */
+#define TRACE_FILTER_EN    (BIT(0))
+#define TRACE_FILTER_EN_M  (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
+#define TRACE_FILTER_EN_V  0x00000001U
+#define TRACE_FILTER_EN_S  0
+/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
+ *  when set, the comparator must be high in order for the filter to match
+ */
+#define TRACE_MATCH_COMP    (BIT(1))
+#define TRACE_MATCH_COMP_M  (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
+#define TRACE_MATCH_COMP_V  0x00000001U
+#define TRACE_MATCH_COMP_S  1
+/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
+ *  when set, match privilege levels specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+ */
+#define TRACE_MATCH_PRIVILEGE    (BIT(2))
+#define TRACE_MATCH_PRIVILEGE_M  (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
+#define TRACE_MATCH_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_PRIVILEGE_S  2
+/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
+ *  when set, start matching from exception cause codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+ *  matching upon return from the 1st matching exception.
+ */
+#define TRACE_MATCH_ECAUSE    (BIT(3))
+#define TRACE_MATCH_ECAUSE_M  (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
+#define TRACE_MATCH_ECAUSE_V  0x00000001U
+#define TRACE_MATCH_ECAUSE_S  3
+/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
+ *  when set, start matching from a trap with the interrupt level codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+ *  stop matching upon return from the 1st matching trap.
+ */
+#define TRACE_MATCH_INTERRUPT    (BIT(4))
+#define TRACE_MATCH_INTERRUPT_M  (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
+#define TRACE_MATCH_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_INTERRUPT_S  4
+
+/** TRACE_FILTER_MATCH_CONTROL_REG register
+ *  filter match control register
+ */
+#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c)
+/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
+ *  Select match which privilege level when
+ *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1:
+ *  machine mode. \\0: user mode
+ */
+#define TRACE_MATCH_CHOICE_PRIVILEGE    (BIT(0))
+#define TRACE_MATCH_CHOICE_PRIVILEGE_M  (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
+#define TRACE_MATCH_CHOICE_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_CHOICE_PRIVILEGE_S  0
+/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
+ *  Select which match which itype when
+ *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match
+ *  itype of 2. \\0: match itype or 1.
+ */
+#define TRACE_MATCH_VALUE_INTERRUPT    (BIT(1))
+#define TRACE_MATCH_VALUE_INTERRUPT_M  (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
+#define TRACE_MATCH_VALUE_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_VALUE_INTERRUPT_S  1
+/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
+ *  specified which ecause matched.
+ */
+#define TRACE_MATCH_CHOICE_ECAUSE    0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_M  (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
+#define TRACE_MATCH_CHOICE_ECAUSE_V  0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_S  2
+
+/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
+ *  filter comparator match control register
+ */
+#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30)
+/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
+ *  Determines which input to compare against the primary comparator, \\0: iaddr, \\1:
+ *  tval.
+ */
+#define TRACE_P_INPUT    (BIT(0))
+#define TRACE_P_INPUT_M  (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
+#define TRACE_P_INPUT_V  0x00000001U
+#define TRACE_P_INPUT_S  0
+/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
+ *  Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than,
+ *  \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other:
+ *  always match
+ */
+#define TRACE_P_FUNCTION    0x00000007U
+#define TRACE_P_FUNCTION_M  (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
+#define TRACE_P_FUNCTION_V  0x00000007U
+#define TRACE_P_FUNCTION_S  2
+/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
+ *  Generate a trace packet explicitly reporting the address that cause the primary
+ *  match
+ */
+#define TRACE_P_NOTIFY    (BIT(5))
+#define TRACE_P_NOTIFY_M  (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
+#define TRACE_P_NOTIFY_V  0x00000001U
+#define TRACE_P_NOTIFY_S  5
+/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
+ *  Determines which input to compare against the secondary comparator, \\0: iaddr,
+ *  \\1: tval.
+ */
+#define TRACE_S_INPUT    (BIT(8))
+#define TRACE_S_INPUT_M  (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
+#define TRACE_S_INPUT_V  0x00000001U
+#define TRACE_S_INPUT_S  8
+/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
+ *  Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less
+ *  than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal,
+ *  \\other: always match
+ */
+#define TRACE_S_FUNCTION    0x00000007U
+#define TRACE_S_FUNCTION_M  (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
+#define TRACE_S_FUNCTION_V  0x00000007U
+#define TRACE_S_FUNCTION_S  10
+/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
+ *  Generate a trace packet explicitly reporting the address that cause the secondary
+ *  match
+ */
+#define TRACE_S_NOTIFY    (BIT(13))
+#define TRACE_S_NOTIFY_M  (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
+#define TRACE_S_NOTIFY_V  0x00000001U
+#define TRACE_S_NOTIFY_S  13
+/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  0: only primary matches, \\1: primary and secondary comparator both
+ *  matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3:
+ *  set when primary matches and continue to match until after secondary comparator
+ *  matches
+ */
+#define TRACE_MATCH_MODE    0x00000003U
+#define TRACE_MATCH_MODE_M  (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
+#define TRACE_MATCH_MODE_V  0x00000003U
+#define TRACE_MATCH_MODE_S  16
+
+/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
+ *  primary comparator match value
+ */
+#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34)
+/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  primary comparator match value
+ */
+#define TRACE_P_MATCH    0xFFFFFFFFU
+#define TRACE_P_MATCH_M  (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
+#define TRACE_P_MATCH_V  0xFFFFFFFFU
+#define TRACE_P_MATCH_S  0
+
+/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
+ *  secondary comparator match value
+ */
+#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38)
+/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  secondary comparator match value
+ */
+#define TRACE_S_MATCH    0xFFFFFFFFU
+#define TRACE_S_MATCH_M  (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
+#define TRACE_S_MATCH_V  0xFFFFFFFFU
+#define TRACE_S_MATCH_S  0
+
+/** TRACE_RESYNC_PROLONGED_REG register
+ *  resync configuration register
+ */
+#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c)
+/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
+ *  count number, when count to this value, send a sync package
+ */
+#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
+#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_S  0
+/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  resyc mode sel: \\0: off, \\2: cycle count  \\3: package num count
+ */
+#define TRACE_RESYNC_MODE    0x00000003U
+#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
+#define TRACE_RESYNC_MODE_V  0x00000003U
+#define TRACE_RESYNC_MODE_S  24
+
+/** TRACE_AHB_CONFIG_REG register
+ *  AHB config register
+ */
+#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
+/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
+ *  set hburst
+ */
+#define TRACE_HBURST    0x00000007U
+#define TRACE_HBURST_M  (TRACE_HBURST_V << TRACE_HBURST_S)
+#define TRACE_HBURST_V  0x00000007U
+#define TRACE_HBURST_S  0
+/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
+ *  set max continuous access for incr mode
+ */
+#define TRACE_MAX_INCR    0x00000007U
+#define TRACE_MAX_INCR_M  (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
+#define TRACE_MAX_INCR_V  0x00000007U
+#define TRACE_MAX_INCR_S  3
+
+/** TRACE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44)
+/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define TRACE_CLK_EN    (BIT(0))
+#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
+#define TRACE_CLK_EN_V  0x00000001U
+#define TRACE_CLK_EN_S  0
+
+/** TRACE_DATE_REG register
+ *  Version control register
+ */
+#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
+/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define TRACE_DATE    0x0FFFFFFFU
+#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
+#define TRACE_DATE_V  0x0FFFFFFFU
+#define TRACE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/trace_struct.h b/components/soc/esp32p4/include/soc/trace_struct.h
new file mode 100644
index 0000000000..08667b8cbc
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/trace_struct.h
@@ -0,0 +1,461 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Trace memory configuration registers */
+/** Type of mem_start_addr register
+ *  mem start addr
+ */
+typedef union {
+    struct {
+        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of trace memory
+         */
+        uint32_t mem_start_addr:32;
+    };
+    uint32_t val;
+} trace_mem_start_addr_reg_t;
+
+/** Type of mem_end_addr register
+ *  mem end addr
+ */
+typedef union {
+    struct {
+        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of trace memory
+         */
+        uint32_t mem_end_addr:32;
+    };
+    uint32_t val;
+} trace_mem_end_addr_reg_t;
+
+/** Type of mem_current_addr register
+ *  mem current addr
+ */
+typedef union {
+    struct {
+        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  current_mem_addr,indicate that next writing addr
+         */
+        uint32_t mem_current_addr:32;
+    };
+    uint32_t val;
+} trace_mem_current_addr_reg_t;
+
+/** Type of mem_addr_update register
+ *  mem addr update
+ */
+typedef union {
+    struct {
+        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
+         *  when set, the  will
+         *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
+         *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
+         */
+        uint32_t mem_current_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_mem_addr_update_reg_t;
+
+
+/** Group: Trace fifo status register */
+/** Type of fifo_status register
+ *  fifo status register
+ */
+typedef union {
+    struct {
+        /** fifo_empty : RO; bitpos: [0]; default: 1;
+         *  Represent whether the fifo is empty. \\1: empty \\0: not empty
+         */
+        uint32_t fifo_empty:1;
+        /** work_status : RO; bitpos: [2:1]; default: 0;
+         *  Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due
+         *  to hart halted or havereset \\3: lost state
+         */
+        uint32_t work_status:2;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} trace_fifo_status_reg_t;
+
+
+/** Group: Trace interrupt configuration registers */
+/** Type of intr_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Set 1 enable fifo_overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_ena:1;
+        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Set 1 enable mem_full interrupt
+         */
+        uint32_t mem_full_intr_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_ena_reg_t;
+
+/** Type of intr_raw register
+ *  interrupt status register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
+         *  fifo_overflow interrupt status
+         */
+        uint32_t fifo_overflow_intr_raw:1;
+        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
+         *  mem_full interrupt status
+         */
+        uint32_t mem_full_intr_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_raw_reg_t;
+
+/** Type of intr_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
+         *  Set 1 clear fifo overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_clr:1;
+        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
+         *  Set 1 clear mem full interrupt
+         */
+        uint32_t mem_full_intr_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_clr_reg_t;
+
+
+/** Group: Trace configuration register */
+/** Type of trigger register
+ *  trigger register
+ */
+typedef union {
+    struct {
+        /** trigger_on : WT; bitpos: [0]; default: 0;
+         *  Configure whether or not start trace.\\1: start trace \\0: invalid\\
+         */
+        uint32_t trigger_on:1;
+        /** trigger_off : WT; bitpos: [1]; default: 0;
+         *  Configure whether or not stop trace.\\1: stop trace \\0: invalid\\
+         */
+        uint32_t trigger_off:1;
+        /** mem_loop : R/W; bitpos: [2]; default: 1;
+         *  Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when
+         *  mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\
+         */
+        uint32_t mem_loop:1;
+        /** restart_ena : R/W; bitpos: [3]; default: 1;
+         *  Configure whether or not enable auto-restart.\\1: enable\\0: disable\\
+         */
+        uint32_t restart_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} trace_trigger_reg_t;
+
+/** Type of config register
+ *  trace configuration register
+ */
+typedef union {
+    struct {
+        /** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\
+         */
+        uint32_t dm_trigger_ena:1;
+        /** reset_ena : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not enable trace cpu haverest, when enabeld, if cpu have
+         *  reset, the encoder will output a packet to report the address of the last
+         *  instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0:
+         *  disabled\\
+         */
+        uint32_t reset_ena:1;
+        /** halt_ena : R/W; bitpos: [2]; default: 0;
+         *  Configure whether or not enable trace cpu is halted, when enabeld, if the cpu
+         *  halted, the encoder will output a packet to report the address of the last
+         *  instruction, and upon halted deassertion, the encoder start again.When disabled,
+         *  encoder will not report the last address before halted and first address after
+         *  halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\
+         */
+        uint32_t halt_ena:1;
+        /** stall_ena : R/W; bitpos: [3]; default: 0;
+         *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
+         *  the cpu will be stalled until the packets is able to write to fifo.\\1:
+         *  enabled.\\0: disabled\\
+         */
+        uint32_t stall_ena:1;
+        /** full_address : R/W; bitpos: [4]; default: 0;
+         *  Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta
+         *  address mode\\
+         */
+        uint32_t full_address:1;
+        /** implicit_except : R/W; bitpos: [5]; default: 0;
+         *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
+         *  exception address, only exception cause in exception packets.\\1: enabled\\0:
+         *  disabled\\
+         */
+        uint32_t implicit_except:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_config_reg_t;
+
+/** Type of filter_control register
+ *  filter control register
+ */
+typedef union {
+    struct {
+        /** filter_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match
+         */
+        uint32_t filter_en:1;
+        /** match_comp : R/W; bitpos: [1]; default: 0;
+         *  when set, the comparator must be high in order for the filter to match
+         */
+        uint32_t match_comp:1;
+        /** match_privilege : R/W; bitpos: [2]; default: 0;
+         *  when set, match privilege levels specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+         */
+        uint32_t match_privilege:1;
+        /** match_ecause : R/W; bitpos: [3]; default: 0;
+         *  when set, start matching from exception cause codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+         *  matching upon return from the 1st matching exception.
+         */
+        uint32_t match_ecause:1;
+        /** match_interrupt : R/W; bitpos: [4]; default: 0;
+         *  when set, start matching from a trap with the interrupt level codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+         *  stop matching upon return from the 1st matching trap.
+         */
+        uint32_t match_interrupt:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} trace_filter_control_reg_t;
+
+/** Type of filter_match_control register
+ *  filter match control register
+ */
+typedef union {
+    struct {
+        /** match_choice_privilege : R/W; bitpos: [0]; default: 0;
+         *  Select match which privilege level when
+         *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1:
+         *  machine mode. \\0: user mode
+         */
+        uint32_t match_choice_privilege:1;
+        /** match_value_interrupt : R/W; bitpos: [1]; default: 0;
+         *  Select which match which itype when
+         *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match
+         *  itype of 2. \\0: match itype or 1.
+         */
+        uint32_t match_value_interrupt:1;
+        /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
+         *  specified which ecause matched.
+         */
+        uint32_t match_choice_ecause:6;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} trace_filter_match_control_reg_t;
+
+/** Type of filter_comparator_control register
+ *  filter comparator match control register
+ */
+typedef union {
+    struct {
+        /** p_input : R/W; bitpos: [0]; default: 0;
+         *  Determines which input to compare against the primary comparator, \\0: iaddr, \\1:
+         *  tval.
+         */
+        uint32_t p_input:1;
+        uint32_t reserved_1:1;
+        /** p_function : R/W; bitpos: [4:2]; default: 0;
+         *  Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than,
+         *  \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other:
+         *  always match
+         */
+        uint32_t p_function:3;
+        /** p_notify : R/W; bitpos: [5]; default: 0;
+         *  Generate a trace packet explicitly reporting the address that cause the primary
+         *  match
+         */
+        uint32_t p_notify:1;
+        uint32_t reserved_6:2;
+        /** s_input : R/W; bitpos: [8]; default: 0;
+         *  Determines which input to compare against the secondary comparator, \\0: iaddr,
+         *  \\1: tval.
+         */
+        uint32_t s_input:1;
+        uint32_t reserved_9:1;
+        /** s_function : R/W; bitpos: [12:10]; default: 0;
+         *  Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less
+         *  than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal,
+         *  \\other: always match
+         */
+        uint32_t s_function:3;
+        /** s_notify : R/W; bitpos: [13]; default: 0;
+         *  Generate a trace packet explicitly reporting the address that cause the secondary
+         *  match
+         */
+        uint32_t s_notify:1;
+        uint32_t reserved_14:2;
+        /** match_mode : R/W; bitpos: [17:16]; default: 0;
+         *  0: only primary matches, \\1: primary and secondary comparator both
+         *  matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3:
+         *  set when primary matches and continue to match until after secondary comparator
+         *  matches
+         */
+        uint32_t match_mode:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} trace_filter_comparator_control_reg_t;
+
+/** Type of filter_p_comparator_match register
+ *  primary comparator match value
+ */
+typedef union {
+    struct {
+        /** p_match : R/W; bitpos: [31:0]; default: 0;
+         *  primary comparator match value
+         */
+        uint32_t p_match:32;
+    };
+    uint32_t val;
+} trace_filter_p_comparator_match_reg_t;
+
+/** Type of filter_s_comparator_match register
+ *  secondary comparator match value
+ */
+typedef union {
+    struct {
+        /** s_match : R/W; bitpos: [31:0]; default: 0;
+         *  secondary comparator match value
+         */
+        uint32_t s_match:32;
+    };
+    uint32_t val;
+} trace_filter_s_comparator_match_reg_t;
+
+/** Type of resync_prolonged register
+ *  resync configuration register
+ */
+typedef union {
+    struct {
+        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
+         *  count number, when count to this value, send a sync package
+         */
+        uint32_t resync_prolonged:24;
+        /** resync_mode : R/W; bitpos: [25:24]; default: 0;
+         *  resyc mode sel: \\0: off, \\2: cycle count  \\3: package num count
+         */
+        uint32_t resync_mode:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} trace_resync_prolonged_reg_t;
+
+/** Type of ahb_config register
+ *  AHB config register
+ */
+typedef union {
+    struct {
+        /** hburst : R/W; bitpos: [2:0]; default: 0;
+         *  set hburst
+         */
+        uint32_t hburst:3;
+        /** max_incr : R/W; bitpos: [5:3]; default: 0;
+         *  set max continuous access for incr mode
+         */
+        uint32_t max_incr:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_ahb_config_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35721984;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} trace_date_reg_t;
+
+
+typedef struct {
+    volatile trace_mem_start_addr_reg_t mem_start_addr;
+    volatile trace_mem_end_addr_reg_t mem_end_addr;
+    volatile trace_mem_current_addr_reg_t mem_current_addr;
+    volatile trace_mem_addr_update_reg_t mem_addr_update;
+    volatile trace_fifo_status_reg_t fifo_status;
+    volatile trace_intr_ena_reg_t intr_ena;
+    volatile trace_intr_raw_reg_t intr_raw;
+    volatile trace_intr_clr_reg_t intr_clr;
+    volatile trace_trigger_reg_t trigger;
+    volatile trace_config_reg_t config;
+    volatile trace_filter_control_reg_t filter_control;
+    volatile trace_filter_match_control_reg_t filter_match_control;
+    volatile trace_filter_comparator_control_reg_t filter_comparator_control;
+    volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
+    volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
+    volatile trace_resync_prolonged_reg_t resync_prolonged;
+    volatile trace_ahb_config_reg_t ahb_config;
+    volatile trace_clock_gate_reg_t clock_gate;
+    uint32_t reserved_048[237];
+    volatile trace_date_reg_t date;
+} trace_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/tsens_reg.h b/components/soc/esp32p4/include/soc/tsens_reg.h
new file mode 100644
index 0000000000..279688bc82
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/tsens_reg.h
@@ -0,0 +1,220 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TSENS_CTRL_REG register
+ *  Tsens configuration.
+ */
+#define TSENS_CTRL_REG (DR_REG_TSENS_BASE + 0x0)
+/** TSENS_OUT : RO; bitpos: [7:0]; default: 0;
+ *  Temperature sensor data out.
+ */
+#define TSENS_OUT    0x000000FFU
+#define TSENS_OUT_M  (TSENS_OUT_V << TSENS_OUT_S)
+#define TSENS_OUT_V  0x000000FFU
+#define TSENS_OUT_S  0
+/** TSENS_READY : RO; bitpos: [8]; default: 0;
+ *  Indicate temperature sensor out ready.
+ */
+#define TSENS_READY    (BIT(8))
+#define TSENS_READY_M  (TSENS_READY_V << TSENS_READY_S)
+#define TSENS_READY_V  0x00000001U
+#define TSENS_READY_S  8
+/** TSENS_SAMPLE_EN : R/W; bitpos: [9]; default: 0;
+ *  Enable sample signal for wakeup module.
+ */
+#define TSENS_SAMPLE_EN    (BIT(9))
+#define TSENS_SAMPLE_EN_M  (TSENS_SAMPLE_EN_V << TSENS_SAMPLE_EN_S)
+#define TSENS_SAMPLE_EN_V  0x00000001U
+#define TSENS_SAMPLE_EN_S  9
+/** TSENS_WAKEUP_MASK : R/W; bitpos: [10]; default: 1;
+ *  Wake up signal  mask.
+ */
+#define TSENS_WAKEUP_MASK    (BIT(10))
+#define TSENS_WAKEUP_MASK_M  (TSENS_WAKEUP_MASK_V << TSENS_WAKEUP_MASK_S)
+#define TSENS_WAKEUP_MASK_V  0x00000001U
+#define TSENS_WAKEUP_MASK_S  10
+/** TSENS_INT_EN : R/W; bitpos: [12]; default: 1;
+ *  Enable temperature sensor to send out interrupt.
+ */
+#define TSENS_INT_EN    (BIT(12))
+#define TSENS_INT_EN_M  (TSENS_INT_EN_V << TSENS_INT_EN_S)
+#define TSENS_INT_EN_V  0x00000001U
+#define TSENS_INT_EN_S  12
+/** TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
+ *  Invert temperature sensor data.
+ */
+#define TSENS_IN_INV    (BIT(13))
+#define TSENS_IN_INV_M  (TSENS_IN_INV_V << TSENS_IN_INV_S)
+#define TSENS_IN_INV_V  0x00000001U
+#define TSENS_IN_INV_S  13
+/** TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
+ *  Temperature sensor clock divider.
+ */
+#define TSENS_CLK_DIV    0x000000FFU
+#define TSENS_CLK_DIV_M  (TSENS_CLK_DIV_V << TSENS_CLK_DIV_S)
+#define TSENS_CLK_DIV_V  0x000000FFU
+#define TSENS_CLK_DIV_S  14
+/** TSENS_POWER_UP : R/W; bitpos: [22]; default: 0;
+ *  Temperature sensor power up.
+ */
+#define TSENS_POWER_UP    (BIT(22))
+#define TSENS_POWER_UP_M  (TSENS_POWER_UP_V << TSENS_POWER_UP_S)
+#define TSENS_POWER_UP_V  0x00000001U
+#define TSENS_POWER_UP_S  22
+/** TSENS_POWER_UP_FORCE : R/W; bitpos: [23]; default: 0;
+ *  1: dump out & power up controlled by SW,  0: by FSM.
+ */
+#define TSENS_POWER_UP_FORCE    (BIT(23))
+#define TSENS_POWER_UP_FORCE_M  (TSENS_POWER_UP_FORCE_V << TSENS_POWER_UP_FORCE_S)
+#define TSENS_POWER_UP_FORCE_V  0x00000001U
+#define TSENS_POWER_UP_FORCE_S  23
+
+/** TSENS_INT_RAW_REG register
+ *  Tsens interrupt raw registers.
+ */
+#define TSENS_INT_RAW_REG (DR_REG_TSENS_BASE + 0x8)
+/** TSENS_COCPU_TSENS_WAKE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt raw.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_M  (TSENS_COCPU_TSENS_WAKE_INT_RAW_V << TSENS_COCPU_TSENS_WAKE_INT_RAW_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_S  0
+
+/** TSENS_INT_ST_REG register
+ *  Tsens interrupt status registers.
+ */
+#define TSENS_INT_ST_REG (DR_REG_TSENS_BASE + 0xc)
+/** TSENS_COCPU_TSENS_WAKE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt status.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ST    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_M  (TSENS_COCPU_TSENS_WAKE_INT_ST_V << TSENS_COCPU_TSENS_WAKE_INT_ST_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_S  0
+
+/** TSENS_INT_ENA_REG register
+ *  Tsens interrupt enable registers.
+ */
+#define TSENS_INT_ENA_REG (DR_REG_TSENS_BASE + 0x10)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA : R/WTC; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_S  0
+
+/** TSENS_INT_CLR_REG register
+ *  Tsens interrupt clear registers.
+ */
+#define TSENS_INT_CLR_REG (DR_REG_TSENS_BASE + 0x14)
+/** TSENS_COCPU_TSENS_WAKE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt clear.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_M  (TSENS_COCPU_TSENS_WAKE_INT_CLR_V << TSENS_COCPU_TSENS_WAKE_INT_CLR_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_S  0
+
+/** TSENS_CLK_CONF_REG register
+ *  Tsens regbank configuration registers.
+ */
+#define TSENS_CLK_CONF_REG (DR_REG_TSENS_BASE + 0x18)
+/** TSENS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Tsens regbank clock gating enable.
+ */
+#define TSENS_CLK_EN    (BIT(0))
+#define TSENS_CLK_EN_M  (TSENS_CLK_EN_V << TSENS_CLK_EN_S)
+#define TSENS_CLK_EN_V  0x00000001U
+#define TSENS_CLK_EN_S  0
+
+/** TSENS_INT_ENA_W1TS_REG register
+ *  Tsens wakeup interrupt enable assert.
+ */
+#define TSENS_INT_ENA_W1TS_REG (DR_REG_TSENS_BASE + 0x1c)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this field to assert interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S  0
+
+/** TSENS_INT_ENA_W1TC_REG register
+ *  Tsens wakeup interrupt enable deassert.
+ */
+#define TSENS_INT_ENA_W1TC_REG (DR_REG_TSENS_BASE + 0x20)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this field to deassert interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S  0
+
+/** TSENS_WAKEUP_CTRL_REG register
+ *  Tsens wakeup control registers.
+ */
+#define TSENS_WAKEUP_CTRL_REG (DR_REG_TSENS_BASE + 0x24)
+/** TSENS_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
+ *  Lower threshold.
+ */
+#define TSENS_WAKEUP_TH_LOW    0x000000FFU
+#define TSENS_WAKEUP_TH_LOW_M  (TSENS_WAKEUP_TH_LOW_V << TSENS_WAKEUP_TH_LOW_S)
+#define TSENS_WAKEUP_TH_LOW_V  0x000000FFU
+#define TSENS_WAKEUP_TH_LOW_S  0
+/** TSENS_WAKEUP_TH_HIGH : R/W; bitpos: [21:14]; default: 255;
+ *  Upper threshold.
+ */
+#define TSENS_WAKEUP_TH_HIGH    0x000000FFU
+#define TSENS_WAKEUP_TH_HIGH_M  (TSENS_WAKEUP_TH_HIGH_V << TSENS_WAKEUP_TH_HIGH_S)
+#define TSENS_WAKEUP_TH_HIGH_V  0x000000FFU
+#define TSENS_WAKEUP_TH_HIGH_S  14
+/** TSENS_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define TSENS_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define TSENS_WAKEUP_OVER_UPPER_TH_M  (TSENS_WAKEUP_OVER_UPPER_TH_V << TSENS_WAKEUP_OVER_UPPER_TH_S)
+#define TSENS_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define TSENS_WAKEUP_OVER_UPPER_TH_S  29
+/** TSENS_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Tsens wakeup enable.
+ */
+#define TSENS_WAKEUP_EN    (BIT(30))
+#define TSENS_WAKEUP_EN_M  (TSENS_WAKEUP_EN_V << TSENS_WAKEUP_EN_S)
+#define TSENS_WAKEUP_EN_V  0x00000001U
+#define TSENS_WAKEUP_EN_S  30
+/** TSENS_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define TSENS_WAKEUP_MODE    (BIT(31))
+#define TSENS_WAKEUP_MODE_M  (TSENS_WAKEUP_MODE_V << TSENS_WAKEUP_MODE_S)
+#define TSENS_WAKEUP_MODE_V  0x00000001U
+#define TSENS_WAKEUP_MODE_S  31
+
+/** TSENS_SAMPLE_RATE_REG register
+ *  Hardware automatic sampling control registers.
+ */
+#define TSENS_SAMPLE_RATE_REG (DR_REG_TSENS_BASE + 0x28)
+/** TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
+ *  Hardware automatic sampling rate.
+ */
+#define TSENS_SAMPLE_RATE    0x0000FFFFU
+#define TSENS_SAMPLE_RATE_M  (TSENS_SAMPLE_RATE_V << TSENS_SAMPLE_RATE_S)
+#define TSENS_SAMPLE_RATE_V  0x0000FFFFU
+#define TSENS_SAMPLE_RATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/tsens_struct.h b/components/soc/esp32p4/include/soc/tsens_struct.h
new file mode 100644
index 0000000000..671e88faa8
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/tsens_struct.h
@@ -0,0 +1,232 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Tsens control registers. */
+/** Type of ctrl register
+ *  Tsens configuration.
+ */
+typedef union {
+    struct {
+        /** out : RO; bitpos: [7:0]; default: 0;
+         *  Temperature sensor data out.
+         */
+        uint32_t out:8;
+        /** ready : RO; bitpos: [8]; default: 0;
+         *  Indicate temperature sensor out ready.
+         */
+        uint32_t ready:1;
+        /** sample_en : R/W; bitpos: [9]; default: 0;
+         *  Enable sample signal for wakeup module.
+         */
+        uint32_t sample_en:1;
+        /** wakeup_mask : R/W; bitpos: [10]; default: 1;
+         *  Wake up signal  mask.
+         */
+        uint32_t wakeup_mask:1;
+        uint32_t reserved_11:1;
+        /** int_en : R/W; bitpos: [12]; default: 1;
+         *  Enable temperature sensor to send out interrupt.
+         */
+        uint32_t int_en:1;
+        /** in_inv : R/W; bitpos: [13]; default: 0;
+         *  Invert temperature sensor data.
+         */
+        uint32_t in_inv:1;
+        /** clk_div : R/W; bitpos: [21:14]; default: 6;
+         *  Temperature sensor clock divider.
+         */
+        uint32_t clk_div:8;
+        /** power_up : R/W; bitpos: [22]; default: 0;
+         *  Temperature sensor power up.
+         */
+        uint32_t power_up:1;
+        /** power_up_force : R/W; bitpos: [23]; default: 0;
+         *  1: dump out & power up controlled by SW,  0: by FSM.
+         */
+        uint32_t power_up_force:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} tsens_ctrl_reg_t;
+
+
+/** Group: Tsens interrupt registers. */
+/** Type of int_raw register
+ *  Tsens interrupt raw registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt raw.
+         */
+        uint32_t cocpu_tsens_wake_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Tsens interrupt status registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_st : RO; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt status.
+         */
+        uint32_t cocpu_tsens_wake_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Tsens interrupt enable registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena : R/WTC; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Tsens interrupt clear registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_clr : WT; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt clear.
+         */
+        uint32_t cocpu_tsens_wake_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_clr_reg_t;
+
+/** Type of int_ena_w1ts register
+ *  Tsens wakeup interrupt enable assert.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena_w1ts : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this field to assert interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena_w1ts:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_w1ts_reg_t;
+
+/** Type of int_ena_w1tc register
+ *  Tsens wakeup interrupt enable deassert.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena_w1tc : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this field to deassert interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena_w1tc:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_w1tc_reg_t;
+
+
+/** Group: Tsens regbank clock control registers. */
+/** Type of clk_conf register
+ *  Tsens regbank configuration registers.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Tsens regbank clock gating enable.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_clk_conf_reg_t;
+
+
+/** Group: Tsens wakeup control registers. */
+/** Type of wakeup_ctrl register
+ *  Tsens wakeup control registers.
+ */
+typedef union {
+    struct {
+        /** wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
+         *  Lower threshold.
+         */
+        uint32_t wakeup_th_low:8;
+        uint32_t reserved_8:6;
+        /** wakeup_th_high : R/W; bitpos: [21:14]; default: 255;
+         *  Upper threshold.
+         */
+        uint32_t wakeup_th_high:8;
+        uint32_t reserved_22:7;
+        /** wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
+         *  Indicates that this wakeup event arose from exceeding upper threshold.
+         */
+        uint32_t wakeup_over_upper_th:1;
+        /** wakeup_en : R/W; bitpos: [30]; default: 0;
+         *  Tsens wakeup enable.
+         */
+        uint32_t wakeup_en:1;
+        /** wakeup_mode : R/W; bitpos: [31]; default: 0;
+         *  0:absolute value comparison mode. 1: relative value comparison mode.
+         */
+        uint32_t wakeup_mode:1;
+    };
+    uint32_t val;
+} tsens_wakeup_ctrl_reg_t;
+
+/** Type of sample_rate register
+ *  Hardware automatic sampling control registers.
+ */
+typedef union {
+    struct {
+        /** sample_rate : R/W; bitpos: [15:0]; default: 20;
+         *  Hardware automatic sampling rate.
+         */
+        uint32_t sample_rate:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} tsens_sample_rate_reg_t;
+
+
+typedef struct {
+    volatile tsens_ctrl_reg_t ctrl;
+    uint32_t reserved_004;
+    volatile tsens_int_raw_reg_t int_raw;
+    volatile tsens_int_st_reg_t int_st;
+    volatile tsens_int_ena_reg_t int_ena;
+    volatile tsens_int_clr_reg_t int_clr;
+    volatile tsens_clk_conf_reg_t clk_conf;
+    volatile tsens_int_ena_w1ts_reg_t int_ena_w1ts;
+    volatile tsens_int_ena_w1tc_reg_t int_ena_w1tc;
+    volatile tsens_wakeup_ctrl_reg_t wakeup_ctrl;
+    volatile tsens_sample_rate_reg_t sample_rate;
+} tsens_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tsens_dev_t) == 0x2c, "Invalid size of tsens_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/twai_struct.h b/components/soc/esp32p4/include/soc/twai_struct.h
new file mode 100644
index 0000000000..758d6462fc
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/twai_struct.h
@@ -0,0 +1,796 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of mode register
+ *  TWAI mode register.
+ */
+typedef union {
+    struct {
+        /** reset_mode : R/W; bitpos: [0]; default: 1;
+         *  1: reset, detection of a set reset mode bit results in aborting the current
+         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+         *  operating mode.
+         */
+        uint32_t reset_mode:1;
+        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
+         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+         *  TWAI-bus, even if a message is received successfully. The error counters are
+         *  stopped at the current value. 0: normal.
+         */
+        uint32_t listen_only_mode:1;
+        /** self_test_mode : R/W; bitpos: [2]; default: 0;
+         *  1: self test, in this mode a full node test is possible without any other active
+         *  node on the bus using the self reception request command. The TWAI controller will
+         *  perform a successful transmission, even if there is no acknowledge received. 0:
+         *  normal, an acknowledge is required for successful transmission.
+         */
+        uint32_t self_test_mode:1;
+        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
+         *  1:single, the single acceptance filter option is enabled (one filter with the
+         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+         *  (two filters, each with the length of 16 bit are active).
+         */
+        uint32_t acceptance_filter_mode:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} twai_mode_reg_t;
+
+/** Type of cmd register
+ *  TWAI command register.
+ */
+typedef union {
+    struct {
+        /** tx_request : WO; bitpos: [0]; default: 0;
+         *  1: present, a message shall be transmitted. 0: absent
+         */
+        uint32_t tx_request:1;
+        /** abort_tx : WO; bitpos: [1]; default: 0;
+         *  1: present, if not already in progress, a pending transmission request is
+         *  cancelled. 0: absent
+         */
+        uint32_t abort_tx:1;
+        /** release_buffer : WO; bitpos: [2]; default: 0;
+         *  1: released, the receive buffer, representing the message memory space in the
+         *  RXFIFO is released. 0: no action
+         */
+        uint32_t release_buffer:1;
+        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
+         *  1: clear, the data overrun status bit is cleared. 0: no action.
+         */
+        uint32_t clear_data_overrun:1;
+        /** self_rx_request : WO; bitpos: [4]; default: 0;
+         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+         */
+        uint32_t self_rx_request:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_cmd_reg_t;
+
+/** Type of bus_timing_0 register
+ *  Bit timing configuration register 0.
+ */
+typedef union {
+    struct {
+        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
+         *  The period of the TWAI system clock is programmable and determines the individual
+         *  bit timing. Software has R/W permission in reset mode and RO permission in
+         *  operation mode.
+         */
+        uint32_t baud_presc:14;
+        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
+         *  The synchronization jump width defines the maximum number of clock cycles a bit
+         *  period may be shortened or lengthened. Software has R/W permission in reset mode
+         *  and RO in operation mode.
+         */
+        uint32_t sync_jump_width:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_bus_timing_0_reg_t;
+
+/** Type of bus_timing_1 register
+ *  Bit timing configuration register 1.
+ */
+typedef union {
+    struct {
+        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
+         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment1:4;
+        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
+         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment2:3;
+        /** time_sampling : R/W; bitpos: [7]; default: 0;
+         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t time_sampling:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_bus_timing_1_reg_t;
+
+/** Type of err_warning_limit register
+ *  TWAI error threshold configuration register.
+ */
+typedef union {
+    struct {
+        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
+         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t err_warning_limit:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_warning_limit_reg_t;
+
+/** Type of clock_divider register
+ *  Clock divider register.
+ */
+typedef union {
+    struct {
+        /** cd : R/W; bitpos: [7:0]; default: 0;
+         *  These bits are used to define the frequency at the external CLKOUT pin.
+         */
+        uint32_t cd:8;
+        /** clock_off : R/W; bitpos: [8]; default: 0;
+         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+         *  R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t clock_off:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_clock_divider_reg_t;
+
+/** Type of sw_standby_cfg register
+ *  Software configure standby pin directly.
+ */
+typedef union {
+    struct {
+        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable standby pin.
+         */
+        uint32_t sw_standby_en:1;
+        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
+         *  Clear standby pin.
+         */
+        uint32_t sw_standby_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_sw_standby_cfg_reg_t;
+
+/** Type of hw_cfg register
+ *  Hardware configure standby pin.
+ */
+typedef union {
+    struct {
+        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable function that hardware control standby pin.
+         */
+        uint32_t hw_standby_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_hw_cfg_reg_t;
+
+/** Type of hw_standby_cnt register
+ *  Configure standby counter.
+ */
+typedef union {
+    struct {
+        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+         *  is enabled.
+         */
+        uint32_t standby_wait_cnt:32;
+    };
+    uint32_t val;
+} twai_hw_standby_cnt_reg_t;
+
+/** Type of idle_intr_cnt register
+ *  Configure idle interrupt counter.
+ */
+typedef union {
+    struct {
+        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before triggering idle interrupt.
+         */
+        uint32_t idle_intr_cnt:32;
+    };
+    uint32_t val;
+} twai_idle_intr_cnt_reg_t;
+
+/** Type of eco_cfg register
+ *  ECO configuration register.
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable eco module.
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 1;
+         *  Output of eco module.
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_eco_cfg_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of status register
+ *  TWAI status register.
+ */
+typedef union {
+    struct {
+        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
+         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+         *  message is available
+         */
+        uint32_t status_receive_buffer:1;
+        /** status_overrun : RO; bitpos: [1]; default: 0;
+         *  1: overrun, a message was lost because there was not enough space for that message
+         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+         *  overrun command was given
+         */
+        uint32_t status_overrun:1;
+        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
+         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+         *  or is in the process of being transmitted
+         */
+        uint32_t status_transmit_buffer:1;
+        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
+         *  1: complete, last requested transmission has been successfully completed. 0:
+         *  incomplete, previously requested transmission is not yet completed
+         */
+        uint32_t status_transmission_complete:1;
+        /** status_receive : RO; bitpos: [4]; default: 0;
+         *  1: receive, the TWAI controller is receiving a message. 0: idle
+         */
+        uint32_t status_receive:1;
+        /** status_transmit : RO; bitpos: [5]; default: 0;
+         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+         */
+        uint32_t status_transmit:1;
+        /** status_err : RO; bitpos: [6]; default: 0;
+         *  1: error, at least one of the error counters has reached or exceeded the CPU
+         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+         *  counters are below the warning limit
+         */
+        uint32_t status_err:1;
+        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
+         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+         *  TWAI controller is involved in bus activities
+         */
+        uint32_t status_node_bus_off:1;
+        /** status_miss : RO; bitpos: [8]; default: 0;
+         *  1: current message is destroyed because of FIFO overflow.
+         */
+        uint32_t status_miss:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_status_reg_t;
+
+/** Type of arb_lost_cap register
+ *  TWAI arbiter lost capture register.
+ */
+typedef union {
+    struct {
+        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the bit position of losing arbitration.
+         */
+        uint32_t arbitration_lost_capture:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_arb_lost_cap_reg_t;
+
+/** Type of err_code_cap register
+ *  TWAI error info capture register.
+ */
+typedef union {
+    struct {
+        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the location of errors on the bus.
+         */
+        uint32_t err_capture_code_segment:5;
+        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
+         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+         */
+        uint32_t err_capture_code_direction:1;
+        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
+         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+         */
+        uint32_t err_capture_code_type:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_code_cap_reg_t;
+
+/** Type of rx_err_cnt register
+ *  Rx error counter register.
+ */
+typedef union {
+    struct {
+        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The RX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t rx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_rx_err_cnt_reg_t;
+
+/** Type of tx_err_cnt register
+ *  Tx error counter register.
+ */
+typedef union {
+    struct {
+        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The TX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t tx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_tx_err_cnt_reg_t;
+
+/** Type of rx_message_counter register
+ *  Received message counter register.
+ */
+typedef union {
+    struct {
+        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
+         *  Reflects the number of messages available within the RXFIFO. The value is
+         *  incremented with each receive event and decremented by the release receive buffer
+         *  command.
+         */
+        uint32_t rx_message_counter:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} twai_rx_message_counter_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of interrupt register
+ *  Interrupt signals' register.
+ */
+typedef union {
+    struct {
+        /** receive_int_st : RO; bitpos: [0]; default: 0;
+         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+         *  within the interrupt enable register. 0: reset
+         */
+        uint32_t receive_int_st:1;
+        /** transmit_int_st : RO; bitpos: [1]; default: 0;
+         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t transmit_int_st:1;
+        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
+         *  1: this bit is set on every change (set and clear) of either the error status or
+         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+         *  reset
+         */
+        uint32_t err_warning_int_st:1;
+        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+         *  DOIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t data_overrun_int_st:1;
+        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
+         *  1: this bit is set then the timestamp counter reaches the maximum value and
+         *  overflow.
+         */
+        uint32_t ts_counter_ovfl_int_st:1;
+        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
+         *  1: this bit is set whenever the TWAI controller has reached the error passive
+         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+         *  the TWAI controller is in the error passive status and enters the error active
+         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t err_passive_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
+         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
+         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+         *  the BEIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t bus_err_int_st:1;
+        /** idle_int_st : RO; bitpos: [8]; default: 0;
+         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t idle_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_reg_t;
+
+/** Type of interrupt_enable register
+ *  Interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
+         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+         *  the respective interrupt. 0: disable
+         */
+        uint32_t ext_receive_int_ena:1;
+        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+         *  requests the respective interrupt. 0: disable
+         */
+        uint32_t ext_transmit_int_ena:1;
+        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
+         *  1: enabled, if the error or bus status change (see status register. Table 14), the
+         *  TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_err_warning_int_ena:1;
+        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+         *  the TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_data_overrun_int_ena:1;
+        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
+         *  enable the timestamp counter overflow interrupt request.
+         */
+        uint32_t ts_counter_ovfl_int_ena:1;
+        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
+         *  1: enabled, if the error status of the TWAI controller changes from error active to
+         *  error passive or vice versa, the respective interrupt is requested. 0: disable
+         */
+        uint32_t err_passive_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
+         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+         *  is requested. 0: disable
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t bus_err_int_ena:1;
+        /** idle_int_ena : RO; bitpos: [8]; default: 0;
+         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t idle_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_enable_reg_t;
+
+
+/** Group: Data Registers */
+/** Type of data_0 register
+ *  Data register 0.
+ */
+typedef union {
+    struct {
+        /** data_0 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 0 and when
+         *  software initiate read operation, it is rx data register 0.
+         */
+        uint32_t data_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_0_reg_t;
+
+/** Type of data_1 register
+ *  Data register 1.
+ */
+typedef union {
+    struct {
+        /** data_1 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 1 and when
+         *  software initiate read operation, it is rx data register 1.
+         */
+        uint32_t data_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_1_reg_t;
+
+/** Type of data_2 register
+ *  Data register 2.
+ */
+typedef union {
+    struct {
+        /** data_2 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 2 and when
+         *  software initiate read operation, it is rx data register 2.
+         */
+        uint32_t data_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_2_reg_t;
+
+/** Type of data_3 register
+ *  Data register 3.
+ */
+typedef union {
+    struct {
+        /** data_3 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 3 and when
+         *  software initiate read operation, it is rx data register 3.
+         */
+        uint32_t data_3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_3_reg_t;
+
+/** Type of data_4 register
+ *  Data register 4.
+ */
+typedef union {
+    struct {
+        /** data_4 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 4 and when
+         *  software initiate read operation, it is rx data register 4.
+         */
+        uint32_t data_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_4_reg_t;
+
+/** Type of data_5 register
+ *  Data register 5.
+ */
+typedef union {
+    struct {
+        /** data_5 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 5 and when
+         *  software initiate read operation, it is rx data register 5.
+         */
+        uint32_t data_5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_5_reg_t;
+
+/** Type of data_6 register
+ *  Data register 6.
+ */
+typedef union {
+    struct {
+        /** data_6 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 6 and when
+         *  software initiate read operation, it is rx data register 6.
+         */
+        uint32_t data_6:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_6_reg_t;
+
+/** Type of data_7 register
+ *  Data register 7.
+ */
+typedef union {
+    struct {
+        /** data_7 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 7 and when
+         *  software initiate read operation, it is rx data register 7.
+         */
+        uint32_t data_7:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_7_reg_t;
+
+/** Type of data_8 register
+ *  Data register 8.
+ */
+typedef union {
+    struct {
+        /** data_8 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 8 and when software initiate read operation, it
+         *  is rx data register 8.
+         */
+        uint32_t data_8:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_8_reg_t;
+
+/** Type of data_9 register
+ *  Data register 9.
+ */
+typedef union {
+    struct {
+        /** data_9 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 9 and when software initiate read operation, it
+         *  is rx data register 9.
+         */
+        uint32_t data_9:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_9_reg_t;
+
+/** Type of data_10 register
+ *  Data register 10.
+ */
+typedef union {
+    struct {
+        /** data_10 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 10 and when software initiate read operation, it
+         *  is rx data register 10.
+         */
+        uint32_t data_10:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_10_reg_t;
+
+/** Type of data_11 register
+ *  Data register 11.
+ */
+typedef union {
+    struct {
+        /** data_11 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 11 and when software initiate read operation, it
+         *  is rx data register 11.
+         */
+        uint32_t data_11:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_11_reg_t;
+
+/** Type of data_12 register
+ *  Data register 12.
+ */
+typedef union {
+    struct {
+        /** data_12 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 12 and when software initiate read operation, it
+         *  is rx data register 12.
+         */
+        uint32_t data_12:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_12_reg_t;
+
+
+/** Group: Timestamp Register */
+/** Type of timestamp_data register
+ *  Timestamp data register
+ */
+typedef union {
+    struct {
+        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
+         *  Data of timestamp of a CAN frame.
+         */
+        uint32_t timestamp_data:32;
+    };
+    uint32_t val;
+} twai_timestamp_data_reg_t;
+
+/** Type of timestamp_prescaler register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
+         *  Configures the clock division number of timestamp counter.
+         */
+        uint32_t ts_div_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_timestamp_prescaler_reg_t;
+
+/** Type of timestamp_cfg register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_enable : R/W; bitpos: [0]; default: 0;
+         *  enable the timestamp collection function.
+         */
+        uint32_t ts_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_timestamp_cfg_reg_t;
+
+
+typedef struct {
+    volatile twai_mode_reg_t mode;
+    volatile twai_cmd_reg_t cmd;
+    volatile twai_status_reg_t status;
+    volatile twai_interrupt_reg_t interrupt;
+    volatile twai_interrupt_enable_reg_t interrupt_enable;
+    uint32_t reserved_014;
+    volatile twai_bus_timing_0_reg_t bus_timing_0;
+    volatile twai_bus_timing_1_reg_t bus_timing_1;
+    uint32_t reserved_020[3];
+    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
+    volatile twai_err_code_cap_reg_t err_code_cap;
+    volatile twai_err_warning_limit_reg_t err_warning_limit;
+    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
+    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
+    volatile twai_data_0_reg_t data_0;
+    volatile twai_data_1_reg_t data_1;
+    volatile twai_data_2_reg_t data_2;
+    volatile twai_data_3_reg_t data_3;
+    volatile twai_data_4_reg_t data_4;
+    volatile twai_data_5_reg_t data_5;
+    volatile twai_data_6_reg_t data_6;
+    volatile twai_data_7_reg_t data_7;
+    volatile twai_data_8_reg_t data_8;
+    volatile twai_data_9_reg_t data_9;
+    volatile twai_data_10_reg_t data_10;
+    volatile twai_data_11_reg_t data_11;
+    volatile twai_data_12_reg_t data_12;
+    volatile twai_rx_message_counter_reg_t rx_message_counter;
+    uint32_t reserved_078;
+    volatile twai_clock_divider_reg_t clock_divider;
+    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
+    volatile twai_hw_cfg_reg_t hw_cfg;
+    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
+    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
+    volatile twai_eco_cfg_reg_t eco_cfg;
+    volatile twai_timestamp_data_reg_t timestamp_data;
+    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
+    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
+} twai_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/twaifd_reg.h b/components/soc/esp32p4/include/soc/twaifd_reg.h
new file mode 100644
index 0000000000..933e0dc154
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/twaifd_reg.h
@@ -0,0 +1,1795 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TWAIFD_DEVICE_ID_REG register
+ *  TWAI FD device id status register
+ */
+#define TWAIFD_DEVICE_ID_REG (DR_REG_TWAIFD_BASE + 0x0)
+/** TWAIFD_DEVICE_ID : R/W; bitpos: [31:0]; default: 51965;
+ *  Represents whether CAN IP function is mapped correctly on its base address.
+ */
+#define TWAIFD_DEVICE_ID    0xFFFFFFFFU
+#define TWAIFD_DEVICE_ID_M  (TWAIFD_DEVICE_ID_V << TWAIFD_DEVICE_ID_S)
+#define TWAIFD_DEVICE_ID_V  0xFFFFFFFFU
+#define TWAIFD_DEVICE_ID_S  0
+
+/** TWAIFD_MODE_SETTING_REG register
+ *  TWAI FD mode setting register
+ */
+#define TWAIFD_MODE_SETTING_REG (DR_REG_TWAIFD_BASE + 0x4)
+/** TWAIFD_SW_RESET : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to reset the TWAI FD controller.\\
+ *  0: invalid\\
+ *  1: reset.\\
+ */
+#define TWAIFD_SW_RESET    (BIT(0))
+#define TWAIFD_SW_RESET_M  (TWAIFD_SW_RESET_V << TWAIFD_SW_RESET_S)
+#define TWAIFD_SW_RESET_V  0x00000001U
+#define TWAIFD_SW_RESET_S  0
+/** TWAIFD_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
+ *  bus monitor enable
+ */
+#define TWAIFD_LISTEN_ONLY_MODE    (BIT(1))
+#define TWAIFD_LISTEN_ONLY_MODE_M  (TWAIFD_LISTEN_ONLY_MODE_V << TWAIFD_LISTEN_ONLY_MODE_S)
+#define TWAIFD_LISTEN_ONLY_MODE_V  0x00000001U
+#define TWAIFD_LISTEN_ONLY_MODE_S  1
+/** TWAIFD_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable the self test mode.\\
+ *  0: disable\\
+ *  1: enable\\
+ */
+#define TWAIFD_SELF_TEST_MODE    (BIT(2))
+#define TWAIFD_SELF_TEST_MODE_M  (TWAIFD_SELF_TEST_MODE_V << TWAIFD_SELF_TEST_MODE_S)
+#define TWAIFD_SELF_TEST_MODE_V  0x00000001U
+#define TWAIFD_SELF_TEST_MODE_S  2
+/** TWAIFD_ACCEPT_FILTER_MODE : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable the usage of acceptance filters.\\
+ *  0: disable\\
+ *  1: enable\\
+ */
+#define TWAIFD_ACCEPT_FILTER_MODE    (BIT(3))
+#define TWAIFD_ACCEPT_FILTER_MODE_M  (TWAIFD_ACCEPT_FILTER_MODE_V << TWAIFD_ACCEPT_FILTER_MODE_S)
+#define TWAIFD_ACCEPT_FILTER_MODE_V  0x00000001U
+#define TWAIFD_ACCEPT_FILTER_MODE_S  3
+/** TWAIFD_FLEXIBLE_DATA_RATE : R/W; bitpos: [4]; default: 1;
+ *  Configures whether or not to support flexible data rate.\\
+ *  0: not support\\
+ *  1: support\\
+ */
+#define TWAIFD_FLEXIBLE_DATA_RATE    (BIT(4))
+#define TWAIFD_FLEXIBLE_DATA_RATE_M  (TWAIFD_FLEXIBLE_DATA_RATE_V << TWAIFD_FLEXIBLE_DATA_RATE_S)
+#define TWAIFD_FLEXIBLE_DATA_RATE_V  0x00000001U
+#define TWAIFD_FLEXIBLE_DATA_RATE_S  4
+/** TWAIFD_RTR_FRM_BEHAVIOR : R/W; bitpos: [5]; default: 0;
+ *  time_triggered transmission mode
+ */
+#define TWAIFD_RTR_FRM_BEHAVIOR    (BIT(5))
+#define TWAIFD_RTR_FRM_BEHAVIOR_M  (TWAIFD_RTR_FRM_BEHAVIOR_V << TWAIFD_RTR_FRM_BEHAVIOR_S)
+#define TWAIFD_RTR_FRM_BEHAVIOR_V  0x00000001U
+#define TWAIFD_RTR_FRM_BEHAVIOR_S  5
+/** TWAIFD_ROM : R/W; bitpos: [6]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_ROM    (BIT(6))
+#define TWAIFD_ROM_M  (TWAIFD_ROM_V << TWAIFD_ROM_S)
+#define TWAIFD_ROM_V  0x00000001U
+#define TWAIFD_ROM_S  6
+/** TWAIFD_ACK_BEHAVIOR : R/W; bitpos: [7]; default: 0;
+ *  Configures the acknowledge behavior.\\
+ *  0: normal behavior.\\
+ *  1: acknowledge is not sent.\\
+ */
+#define TWAIFD_ACK_BEHAVIOR    (BIT(7))
+#define TWAIFD_ACK_BEHAVIOR_M  (TWAIFD_ACK_BEHAVIOR_V << TWAIFD_ACK_BEHAVIOR_S)
+#define TWAIFD_ACK_BEHAVIOR_V  0x00000001U
+#define TWAIFD_ACK_BEHAVIOR_S  7
+/** TWAIFD_TEST_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable the triple sampling mode.\\
+ *  0: disable\\
+ *  1: enable\\
+ */
+#define TWAIFD_TEST_MODE    (BIT(8))
+#define TWAIFD_TEST_MODE_M  (TWAIFD_TEST_MODE_V << TWAIFD_TEST_MODE_S)
+#define TWAIFD_TEST_MODE_V  0x00000001U
+#define TWAIFD_TEST_MODE_S  8
+/** TWAIFD_RXBAM : R/W; bitpos: [9]; default: 1;
+ *  a\\
+ */
+#define TWAIFD_RXBAM    (BIT(9))
+#define TWAIFD_RXBAM_M  (TWAIFD_RXBAM_V << TWAIFD_RXBAM_S)
+#define TWAIFD_RXBAM_V  0x00000001U
+#define TWAIFD_RXBAM_S  9
+/** TWAIFD_LIMIT_RETX_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable the limit of retransmission.\\
+ *  0: disable\\
+ *  1: enable\\
+ */
+#define TWAIFD_LIMIT_RETX_EN    (BIT(16))
+#define TWAIFD_LIMIT_RETX_EN_M  (TWAIFD_LIMIT_RETX_EN_V << TWAIFD_LIMIT_RETX_EN_S)
+#define TWAIFD_LIMIT_RETX_EN_V  0x00000001U
+#define TWAIFD_LIMIT_RETX_EN_S  16
+/** TWAIFD_RETX_THRES : R/W; bitpos: [20:17]; default: 0;
+ *  Configures the threshold of retransmission attempts. \\
+ */
+#define TWAIFD_RETX_THRES    0x0000000FU
+#define TWAIFD_RETX_THRES_M  (TWAIFD_RETX_THRES_V << TWAIFD_RETX_THRES_S)
+#define TWAIFD_RETX_THRES_V  0x0000000FU
+#define TWAIFD_RETX_THRES_S  17
+/** TWAIFD_ILBP : R/W; bitpos: [21]; default: 0;
+ *  acknowledge forbidden mode
+ */
+#define TWAIFD_ILBP    (BIT(21))
+#define TWAIFD_ILBP_M  (TWAIFD_ILBP_V << TWAIFD_ILBP_S)
+#define TWAIFD_ILBP_V  0x00000001U
+#define TWAIFD_ILBP_S  21
+/** TWAIFD_CTRL_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable the twai FD controller.\\
+ *  0: disable\\
+ *  1: enable\\
+ */
+#define TWAIFD_CTRL_EN    (BIT(22))
+#define TWAIFD_CTRL_EN_M  (TWAIFD_CTRL_EN_V << TWAIFD_CTRL_EN_S)
+#define TWAIFD_CTRL_EN_V  0x00000001U
+#define TWAIFD_CTRL_EN_S  22
+/** TWAIFD_FD_TYPE : R/W; bitpos: [23]; default: 0;
+ *  Configure the twai fd frame type.\\
+ *  0: ISO CAN FD\\
+ *  1: CAN FD 1.0\\
+ */
+#define TWAIFD_FD_TYPE    (BIT(23))
+#define TWAIFD_FD_TYPE_M  (TWAIFD_FD_TYPE_V << TWAIFD_FD_TYPE_S)
+#define TWAIFD_FD_TYPE_V  0x00000001U
+#define TWAIFD_FD_TYPE_S  23
+/** TWAIFD_PEX : R/W; bitpos: [24]; default: 0;
+ *  protocol expection mode\\
+ */
+#define TWAIFD_PEX    (BIT(24))
+#define TWAIFD_PEX_M  (TWAIFD_PEX_V << TWAIFD_PEX_S)
+#define TWAIFD_PEX_V  0x00000001U
+#define TWAIFD_PEX_S  24
+/** TWAIFD_TBFBO : R/W; bitpos: [25]; default: 1;
+ *  a\\
+ */
+#define TWAIFD_TBFBO    (BIT(25))
+#define TWAIFD_TBFBO_M  (TWAIFD_TBFBO_V << TWAIFD_TBFBO_S)
+#define TWAIFD_TBFBO_V  0x00000001U
+#define TWAIFD_TBFBO_S  25
+/** TWAIFD_FDRF : R/W; bitpos: [26]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_FDRF    (BIT(26))
+#define TWAIFD_FDRF_M  (TWAIFD_FDRF_V << TWAIFD_FDRF_S)
+#define TWAIFD_FDRF_V  0x00000001U
+#define TWAIFD_FDRF_S  26
+
+/** TWAIFD_COMMAND_REG register
+ *  TWAI FD command register
+ */
+#define TWAIFD_COMMAND_REG (DR_REG_TWAIFD_BASE + 0x8)
+/** TWAIFD_RXRPMV : WO; bitpos: [1]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_RXRPMV    (BIT(1))
+#define TWAIFD_RXRPMV_M  (TWAIFD_RXRPMV_V << TWAIFD_RXRPMV_S)
+#define TWAIFD_RXRPMV_V  0x00000001U
+#define TWAIFD_RXRPMV_S  1
+/** TWAIFD_RELEASE_RX_BUF : WO; bitpos: [2]; default: 0;
+ *  Configures whether or not to delete all data from the receive buffer.\\
+ *  0: invalid\\
+ *  1: delete\\
+ */
+#define TWAIFD_RELEASE_RX_BUF    (BIT(2))
+#define TWAIFD_RELEASE_RX_BUF_M  (TWAIFD_RELEASE_RX_BUF_V << TWAIFD_RELEASE_RX_BUF_S)
+#define TWAIFD_RELEASE_RX_BUF_V  0x00000001U
+#define TWAIFD_RELEASE_RX_BUF_S  2
+/** TWAIFD_CLR_OVERRUN_FLG : WO; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear the data overrun flag.\\
+ *  0: invalid\\
+ *  1: clear\\
+ */
+#define TWAIFD_CLR_OVERRUN_FLG    (BIT(3))
+#define TWAIFD_CLR_OVERRUN_FLG_M  (TWAIFD_CLR_OVERRUN_FLG_V << TWAIFD_CLR_OVERRUN_FLG_S)
+#define TWAIFD_CLR_OVERRUN_FLG_V  0x00000001U
+#define TWAIFD_CLR_OVERRUN_FLG_S  3
+/** TWAIFD_ERCRST : WO; bitpos: [4]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_ERCRST    (BIT(4))
+#define TWAIFD_ERCRST_M  (TWAIFD_ERCRST_V << TWAIFD_ERCRST_S)
+#define TWAIFD_ERCRST_V  0x00000001U
+#define TWAIFD_ERCRST_S  4
+/** TWAIFD_RXFCRST : WO; bitpos: [5]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_RXFCRST    (BIT(5))
+#define TWAIFD_RXFCRST_M  (TWAIFD_RXFCRST_V << TWAIFD_RXFCRST_S)
+#define TWAIFD_RXFCRST_V  0x00000001U
+#define TWAIFD_RXFCRST_S  5
+/** TWAIFD_TXFCRST : WO; bitpos: [6]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXFCRST    (BIT(6))
+#define TWAIFD_TXFCRST_M  (TWAIFD_TXFCRST_V << TWAIFD_TXFCRST_S)
+#define TWAIFD_TXFCRST_V  0x00000001U
+#define TWAIFD_TXFCRST_S  6
+/** TWAIFD_CPEXS : WO; bitpos: [7]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_CPEXS    (BIT(7))
+#define TWAIFD_CPEXS_M  (TWAIFD_CPEXS_V << TWAIFD_CPEXS_S)
+#define TWAIFD_CPEXS_V  0x00000001U
+#define TWAIFD_CPEXS_S  7
+
+/** TWAIFD_STATUS_REG register
+ *  TWAI FD status register
+ */
+#define TWAIFD_STATUS_REG (DR_REG_TWAIFD_BASE + 0xc)
+/** TWAIFD_RX_BUF_STAT : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the receive buffer is empty.\\
+ *  0: empty\\
+ *  1: not empty\\
+ */
+#define TWAIFD_RX_BUF_STAT    (BIT(0))
+#define TWAIFD_RX_BUF_STAT_M  (TWAIFD_RX_BUF_STAT_V << TWAIFD_RX_BUF_STAT_S)
+#define TWAIFD_RX_BUF_STAT_V  0x00000001U
+#define TWAIFD_RX_BUF_STAT_S  0
+/** TWAIFD_DATA_OVERRUN_FLG : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not the receive buffer is full and the frame is
+ *  overrun(lost).\\
+ *  0: not overrun\\
+ *  1: overrun\\
+ */
+#define TWAIFD_DATA_OVERRUN_FLG    (BIT(1))
+#define TWAIFD_DATA_OVERRUN_FLG_M  (TWAIFD_DATA_OVERRUN_FLG_V << TWAIFD_DATA_OVERRUN_FLG_S)
+#define TWAIFD_DATA_OVERRUN_FLG_V  0x00000001U
+#define TWAIFD_DATA_OVERRUN_FLG_S  1
+/** TWAIFD_TX_BUF_SAT : RO; bitpos: [2]; default: 0;
+ *  Represents whether or not the transmit buffer is full.\\
+ *  0: not full\\
+ *  1: full\\
+ */
+#define TWAIFD_TX_BUF_SAT    (BIT(2))
+#define TWAIFD_TX_BUF_SAT_M  (TWAIFD_TX_BUF_SAT_V << TWAIFD_TX_BUF_SAT_S)
+#define TWAIFD_TX_BUF_SAT_V  0x00000001U
+#define TWAIFD_TX_BUF_SAT_S  2
+/** TWAIFD_ERR_FRM_TX : RO; bitpos: [3]; default: 0;
+ *  Represents whether or not the error frame is being transmitted.\\
+ *  0: not being transmitted\\
+ *  1: being transmitted\\
+ */
+#define TWAIFD_ERR_FRM_TX    (BIT(3))
+#define TWAIFD_ERR_FRM_TX_M  (TWAIFD_ERR_FRM_TX_V << TWAIFD_ERR_FRM_TX_S)
+#define TWAIFD_ERR_FRM_TX_V  0x00000001U
+#define TWAIFD_ERR_FRM_TX_S  3
+/** TWAIFD_RX_FRM_STAT : RO; bitpos: [4]; default: 0;
+ *  Represents whether or not the controller is receiving a frame.\\
+ *  0: not receiving\\
+ *  1: receiving\\
+ */
+#define TWAIFD_RX_FRM_STAT    (BIT(4))
+#define TWAIFD_RX_FRM_STAT_M  (TWAIFD_RX_FRM_STAT_V << TWAIFD_RX_FRM_STAT_S)
+#define TWAIFD_RX_FRM_STAT_V  0x00000001U
+#define TWAIFD_RX_FRM_STAT_S  4
+/** TWAIFD_TX_FRM_STAT : RO; bitpos: [5]; default: 0;
+ *  Represents whether or not the controller is transmitting a frame.\\
+ *  0: not transmitting\\
+ *  1: transmitting\\
+ */
+#define TWAIFD_TX_FRM_STAT    (BIT(5))
+#define TWAIFD_TX_FRM_STAT_M  (TWAIFD_TX_FRM_STAT_V << TWAIFD_TX_FRM_STAT_S)
+#define TWAIFD_TX_FRM_STAT_V  0x00000001U
+#define TWAIFD_TX_FRM_STAT_S  5
+/** TWAIFD_ERR_STAT : RO; bitpos: [6]; default: 0;
+ *  Represents whether or not the error warning limit is reached.\\
+ *  0: not reached\\
+ *  1: reached\\
+ */
+#define TWAIFD_ERR_STAT    (BIT(6))
+#define TWAIFD_ERR_STAT_M  (TWAIFD_ERR_STAT_V << TWAIFD_ERR_STAT_S)
+#define TWAIFD_ERR_STAT_V  0x00000001U
+#define TWAIFD_ERR_STAT_S  6
+/** TWAIFD_BUS_STAT : RO; bitpos: [7]; default: 1;
+ *  Represents whether or not bus is active.\\
+ *  0: active\\
+ *  1: not active\\
+ */
+#define TWAIFD_BUS_STAT    (BIT(7))
+#define TWAIFD_BUS_STAT_M  (TWAIFD_BUS_STAT_V << TWAIFD_BUS_STAT_S)
+#define TWAIFD_BUS_STAT_V  0x00000001U
+#define TWAIFD_BUS_STAT_S  7
+/** TWAIFD_PEXS : RO; bitpos: [8]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_PEXS    (BIT(8))
+#define TWAIFD_PEXS_M  (TWAIFD_PEXS_V << TWAIFD_PEXS_S)
+#define TWAIFD_PEXS_V  0x00000001U
+#define TWAIFD_PEXS_S  8
+/** TWAIFD_REINTEGRATING_WAIT : RO; bitpos: [9]; default: 0;
+ *  fsm is in reintegrating wait status
+ */
+#define TWAIFD_REINTEGRATING_WAIT    (BIT(9))
+#define TWAIFD_REINTEGRATING_WAIT_M  (TWAIFD_REINTEGRATING_WAIT_V << TWAIFD_REINTEGRATING_WAIT_S)
+#define TWAIFD_REINTEGRATING_WAIT_V  0x00000001U
+#define TWAIFD_REINTEGRATING_WAIT_S  9
+/** TWAIFD_STCNT : RO; bitpos: [16]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_STCNT    (BIT(16))
+#define TWAIFD_STCNT_M  (TWAIFD_STCNT_V << TWAIFD_STCNT_S)
+#define TWAIFD_STCNT_V  0x00000001U
+#define TWAIFD_STCNT_S  16
+/** TWAIFD_STRGS : RO; bitpos: [17]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_STRGS    (BIT(17))
+#define TWAIFD_STRGS_M  (TWAIFD_STRGS_V << TWAIFD_STRGS_S)
+#define TWAIFD_STRGS_V  0x00000001U
+#define TWAIFD_STRGS_S  17
+
+/** TWAIFD_INT_RAW_REG register
+ *  TWAI FD interrupt raw register
+ */
+#define TWAIFD_INT_RAW_REG (DR_REG_TWAIFD_BASE + 0x10)
+/** TWAIFD_RX_FRM_SUC_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of TWAIFD_RX_FRM_SUC_INT.
+ */
+#define TWAIFD_RX_FRM_SUC_INT_RAW    (BIT(0))
+#define TWAIFD_RX_FRM_SUC_INT_RAW_M  (TWAIFD_RX_FRM_SUC_INT_RAW_V << TWAIFD_RX_FRM_SUC_INT_RAW_S)
+#define TWAIFD_RX_FRM_SUC_INT_RAW_V  0x00000001U
+#define TWAIFD_RX_FRM_SUC_INT_RAW_S  0
+/** TWAIFD_TX_FRM_SUC_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of TWAIFD_TX_FRM_SUC_INT.
+ */
+#define TWAIFD_TX_FRM_SUC_INT_RAW    (BIT(1))
+#define TWAIFD_TX_FRM_SUC_INT_RAW_M  (TWAIFD_TX_FRM_SUC_INT_RAW_V << TWAIFD_TX_FRM_SUC_INT_RAW_S)
+#define TWAIFD_TX_FRM_SUC_INT_RAW_V  0x00000001U
+#define TWAIFD_TX_FRM_SUC_INT_RAW_S  1
+/** TWAIFD_ERR_WARNING_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of TWAIFD_ERR_WARNING_INT.
+ */
+#define TWAIFD_ERR_WARNING_INT_RAW    (BIT(2))
+#define TWAIFD_ERR_WARNING_INT_RAW_M  (TWAIFD_ERR_WARNING_INT_RAW_V << TWAIFD_ERR_WARNING_INT_RAW_S)
+#define TWAIFD_ERR_WARNING_INT_RAW_V  0x00000001U
+#define TWAIFD_ERR_WARNING_INT_RAW_S  2
+/** TWAIFD_RX_DATA_OVERRUN_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
+ */
+#define TWAIFD_RX_DATA_OVERRUN_INT_RAW    (BIT(3))
+#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_M  (TWAIFD_RX_DATA_OVERRUN_INT_RAW_V << TWAIFD_RX_DATA_OVERRUN_INT_RAW_S)
+#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_V  0x00000001U
+#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_S  3
+/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+ */
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW    (BIT(5))
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_S)
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_V  0x00000001U
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_S  5
+/** TWAIFD_ARB_LOST_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of TWAIFD_ARB_LOST_INT.
+ */
+#define TWAIFD_ARB_LOST_INT_RAW    (BIT(6))
+#define TWAIFD_ARB_LOST_INT_RAW_M  (TWAIFD_ARB_LOST_INT_RAW_V << TWAIFD_ARB_LOST_INT_RAW_S)
+#define TWAIFD_ARB_LOST_INT_RAW_V  0x00000001U
+#define TWAIFD_ARB_LOST_INT_RAW_S  6
+/** TWAIFD_ERR_DETECTED_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of TWAIFD_ERR_DETECTED_INT.
+ */
+#define TWAIFD_ERR_DETECTED_INT_RAW    (BIT(7))
+#define TWAIFD_ERR_DETECTED_INT_RAW_M  (TWAIFD_ERR_DETECTED_INT_RAW_V << TWAIFD_ERR_DETECTED_INT_RAW_S)
+#define TWAIFD_ERR_DETECTED_INT_RAW_V  0x00000001U
+#define TWAIFD_ERR_DETECTED_INT_RAW_S  7
+/** TWAIFD_IS_OVERLOAD_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt status of TWAIFD_IS_OVERLOAD_INT.
+ */
+#define TWAIFD_IS_OVERLOAD_INT_RAW    (BIT(8))
+#define TWAIFD_IS_OVERLOAD_INT_RAW_M  (TWAIFD_IS_OVERLOAD_INT_RAW_V << TWAIFD_IS_OVERLOAD_INT_RAW_S)
+#define TWAIFD_IS_OVERLOAD_INT_RAW_V  0x00000001U
+#define TWAIFD_IS_OVERLOAD_INT_RAW_S  8
+/** TWAIFD_RX_BUF_FULL_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt status of TWAIFD_RX_BUF_FULL_INT.
+ */
+#define TWAIFD_RX_BUF_FULL_INT_RAW    (BIT(9))
+#define TWAIFD_RX_BUF_FULL_INT_RAW_M  (TWAIFD_RX_BUF_FULL_INT_RAW_V << TWAIFD_RX_BUF_FULL_INT_RAW_S)
+#define TWAIFD_RX_BUF_FULL_INT_RAW_V  0x00000001U
+#define TWAIFD_RX_BUF_FULL_INT_RAW_S  9
+/** TWAIFD_BIT_RATE_SHIFT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
+ */
+#define TWAIFD_BIT_RATE_SHIFT_INT_RAW    (BIT(10))
+#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_M  (TWAIFD_BIT_RATE_SHIFT_INT_RAW_V << TWAIFD_BIT_RATE_SHIFT_INT_RAW_S)
+#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_V  0x00000001U
+#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_S  10
+/** TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
+ */
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW    (BIT(11))
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_S)
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_V  0x00000001U
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_S  11
+/** TWAIFD_TX_BUF_STATUS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
+ */
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW    (BIT(12))
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_V << TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_S)
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_V  0x00000001U
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_S  12
+
+/** TWAIFD_INT_ENA_REG register
+ *  TWAI FD interrupt enable register
+ */
+#define TWAIFD_INT_ENA_REG (DR_REG_TWAIFD_BASE + 0x14)
+/** TWAIFD_RX_FRM_SUC_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable TWAIFD_RX_FRM_SUC_INT.
+ */
+#define TWAIFD_RX_FRM_SUC_INT_ENA    (BIT(0))
+#define TWAIFD_RX_FRM_SUC_INT_ENA_M  (TWAIFD_RX_FRM_SUC_INT_ENA_V << TWAIFD_RX_FRM_SUC_INT_ENA_S)
+#define TWAIFD_RX_FRM_SUC_INT_ENA_V  0x00000001U
+#define TWAIFD_RX_FRM_SUC_INT_ENA_S  0
+/** TWAIFD_TX_FRM_SUC_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable TWAIFD_TX_FRM_SUC_INT.
+ */
+#define TWAIFD_TX_FRM_SUC_INT_ENA    (BIT(1))
+#define TWAIFD_TX_FRM_SUC_INT_ENA_M  (TWAIFD_TX_FRM_SUC_INT_ENA_V << TWAIFD_TX_FRM_SUC_INT_ENA_S)
+#define TWAIFD_TX_FRM_SUC_INT_ENA_V  0x00000001U
+#define TWAIFD_TX_FRM_SUC_INT_ENA_S  1
+/** TWAIFD_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable TWAIFD_ERR_WARNING_INT.
+ */
+#define TWAIFD_ERR_WARNING_INT_ENA    (BIT(2))
+#define TWAIFD_ERR_WARNING_INT_ENA_M  (TWAIFD_ERR_WARNING_INT_ENA_V << TWAIFD_ERR_WARNING_INT_ENA_S)
+#define TWAIFD_ERR_WARNING_INT_ENA_V  0x00000001U
+#define TWAIFD_ERR_WARNING_INT_ENA_S  2
+/** TWAIFD_RX_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable TWAIFD_RX_DATA_OVERRUN_INT.
+ */
+#define TWAIFD_RX_DATA_OVERRUN_INT_ENA    (BIT(3))
+#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_M  (TWAIFD_RX_DATA_OVERRUN_INT_ENA_V << TWAIFD_RX_DATA_OVERRUN_INT_ENA_S)
+#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_V  0x00000001U
+#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_S  3
+/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+ */
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA    (BIT(5))
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_S)
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_V  0x00000001U
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_S  5
+/** TWAIFD_ARB_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable TWAIFD_ARB_LOST_INT.
+ */
+#define TWAIFD_ARB_LOST_INT_ENA    (BIT(6))
+#define TWAIFD_ARB_LOST_INT_ENA_M  (TWAIFD_ARB_LOST_INT_ENA_V << TWAIFD_ARB_LOST_INT_ENA_S)
+#define TWAIFD_ARB_LOST_INT_ENA_V  0x00000001U
+#define TWAIFD_ARB_LOST_INT_ENA_S  6
+/** TWAIFD_ERR_DETECTED_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable TWAIFD_ERR_DETECTED_INT.
+ */
+#define TWAIFD_ERR_DETECTED_INT_ENA    (BIT(7))
+#define TWAIFD_ERR_DETECTED_INT_ENA_M  (TWAIFD_ERR_DETECTED_INT_ENA_V << TWAIFD_ERR_DETECTED_INT_ENA_S)
+#define TWAIFD_ERR_DETECTED_INT_ENA_V  0x00000001U
+#define TWAIFD_ERR_DETECTED_INT_ENA_S  7
+/** TWAIFD_IS_OVERLOAD_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to enable TWAIFD_IS_OVERLOAD_INT.
+ */
+#define TWAIFD_IS_OVERLOAD_INT_ENA    (BIT(8))
+#define TWAIFD_IS_OVERLOAD_INT_ENA_M  (TWAIFD_IS_OVERLOAD_INT_ENA_V << TWAIFD_IS_OVERLOAD_INT_ENA_S)
+#define TWAIFD_IS_OVERLOAD_INT_ENA_V  0x00000001U
+#define TWAIFD_IS_OVERLOAD_INT_ENA_S  8
+/** TWAIFD_RX_BUF_FULL_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to enable TWAIFD_RX_BUF_FULL_INT.
+ */
+#define TWAIFD_RX_BUF_FULL_INT_ENA    (BIT(9))
+#define TWAIFD_RX_BUF_FULL_INT_ENA_M  (TWAIFD_RX_BUF_FULL_INT_ENA_V << TWAIFD_RX_BUF_FULL_INT_ENA_S)
+#define TWAIFD_RX_BUF_FULL_INT_ENA_V  0x00000001U
+#define TWAIFD_RX_BUF_FULL_INT_ENA_S  9
+/** TWAIFD_BIT_RATE_SHIFT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Write 1 to enable TWAIFD_BIT_RATE_SHIFT_INT.
+ */
+#define TWAIFD_BIT_RATE_SHIFT_INT_ENA    (BIT(10))
+#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_M  (TWAIFD_BIT_RATE_SHIFT_INT_ENA_V << TWAIFD_BIT_RATE_SHIFT_INT_ENA_S)
+#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_V  0x00000001U
+#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_S  10
+/** TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Write 1 to enable TWAIFD_RX_BUF_NOT_EMPTY_INT.
+ */
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA    (BIT(11))
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_S)
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_V  0x00000001U
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_S  11
+/** TWAIFD_TX_BUF_STATUS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable TWAIFD_TX_BUF_STATUS_CHG_INT.
+ */
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA    (BIT(12))
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_V << TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_S)
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_V  0x00000001U
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_S  12
+
+/** TWAIFD_INT_ST_REG register
+ *  TWAI FD interrupt status register
+ */
+#define TWAIFD_INT_ST_REG (DR_REG_TWAIFD_BASE + 0x18)
+/** TWAIFD_RX_FRM_SUC_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of TWAIFD_RX_FRM_SUC_INT.
+ */
+#define TWAIFD_RX_FRM_SUC_INT_ST    (BIT(0))
+#define TWAIFD_RX_FRM_SUC_INT_ST_M  (TWAIFD_RX_FRM_SUC_INT_ST_V << TWAIFD_RX_FRM_SUC_INT_ST_S)
+#define TWAIFD_RX_FRM_SUC_INT_ST_V  0x00000001U
+#define TWAIFD_RX_FRM_SUC_INT_ST_S  0
+/** TWAIFD_TX_FRM_SUC_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of TWAIFD_TX_FRM_SUC_INT.
+ */
+#define TWAIFD_TX_FRM_SUC_INT_ST    (BIT(1))
+#define TWAIFD_TX_FRM_SUC_INT_ST_M  (TWAIFD_TX_FRM_SUC_INT_ST_V << TWAIFD_TX_FRM_SUC_INT_ST_S)
+#define TWAIFD_TX_FRM_SUC_INT_ST_V  0x00000001U
+#define TWAIFD_TX_FRM_SUC_INT_ST_S  1
+/** TWAIFD_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of TWAIFD_ERR_WARNING_INT.
+ */
+#define TWAIFD_ERR_WARNING_INT_ST    (BIT(2))
+#define TWAIFD_ERR_WARNING_INT_ST_M  (TWAIFD_ERR_WARNING_INT_ST_V << TWAIFD_ERR_WARNING_INT_ST_S)
+#define TWAIFD_ERR_WARNING_INT_ST_V  0x00000001U
+#define TWAIFD_ERR_WARNING_INT_ST_S  2
+/** TWAIFD_RX_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
+ */
+#define TWAIFD_RX_DATA_OVERRUN_INT_ST    (BIT(3))
+#define TWAIFD_RX_DATA_OVERRUN_INT_ST_M  (TWAIFD_RX_DATA_OVERRUN_INT_ST_V << TWAIFD_RX_DATA_OVERRUN_INT_ST_S)
+#define TWAIFD_RX_DATA_OVERRUN_INT_ST_V  0x00000001U
+#define TWAIFD_RX_DATA_OVERRUN_INT_ST_S  3
+/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+ */
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST    (BIT(5))
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_S)
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_V  0x00000001U
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_S  5
+/** TWAIFD_ARB_LOST_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of TWAIFD_ARB_LOST_INT.
+ */
+#define TWAIFD_ARB_LOST_INT_ST    (BIT(6))
+#define TWAIFD_ARB_LOST_INT_ST_M  (TWAIFD_ARB_LOST_INT_ST_V << TWAIFD_ARB_LOST_INT_ST_S)
+#define TWAIFD_ARB_LOST_INT_ST_V  0x00000001U
+#define TWAIFD_ARB_LOST_INT_ST_S  6
+/** TWAIFD_ERR_DETECTED_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of TWAIFD_ERR_DETECTED_INT.
+ */
+#define TWAIFD_ERR_DETECTED_INT_ST    (BIT(7))
+#define TWAIFD_ERR_DETECTED_INT_ST_M  (TWAIFD_ERR_DETECTED_INT_ST_V << TWAIFD_ERR_DETECTED_INT_ST_S)
+#define TWAIFD_ERR_DETECTED_INT_ST_V  0x00000001U
+#define TWAIFD_ERR_DETECTED_INT_ST_S  7
+/** TWAIFD_IS_OVERLOAD_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status of TWAIFD_IS_OVERLOAD_INT.
+ */
+#define TWAIFD_IS_OVERLOAD_INT_ST    (BIT(8))
+#define TWAIFD_IS_OVERLOAD_INT_ST_M  (TWAIFD_IS_OVERLOAD_INT_ST_V << TWAIFD_IS_OVERLOAD_INT_ST_S)
+#define TWAIFD_IS_OVERLOAD_INT_ST_V  0x00000001U
+#define TWAIFD_IS_OVERLOAD_INT_ST_S  8
+/** TWAIFD_RX_BUF_FULL_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status of TWAIFD_RX_BUF_FULL_INT.
+ */
+#define TWAIFD_RX_BUF_FULL_INT_ST    (BIT(9))
+#define TWAIFD_RX_BUF_FULL_INT_ST_M  (TWAIFD_RX_BUF_FULL_INT_ST_V << TWAIFD_RX_BUF_FULL_INT_ST_S)
+#define TWAIFD_RX_BUF_FULL_INT_ST_V  0x00000001U
+#define TWAIFD_RX_BUF_FULL_INT_ST_S  9
+/** TWAIFD_BIT_RATE_SHIFT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
+ */
+#define TWAIFD_BIT_RATE_SHIFT_INT_ST    (BIT(10))
+#define TWAIFD_BIT_RATE_SHIFT_INT_ST_M  (TWAIFD_BIT_RATE_SHIFT_INT_ST_V << TWAIFD_BIT_RATE_SHIFT_INT_ST_S)
+#define TWAIFD_BIT_RATE_SHIFT_INT_ST_V  0x00000001U
+#define TWAIFD_BIT_RATE_SHIFT_INT_ST_S  10
+/** TWAIFD_RX_BUF_NOT_EMPTY_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
+ */
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST    (BIT(11))
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_S)
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_V  0x00000001U
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_S  11
+/** TWAIFD_TX_BUF_STATUS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
+ */
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST    (BIT(12))
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_ST_V << TWAIFD_TX_BUF_STATUS_CHG_INT_ST_S)
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_V  0x00000001U
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_S  12
+
+/** TWAIFD_INT_CLR_REG register
+ *  TWAI FD interrupt clear register
+ */
+#define TWAIFD_INT_CLR_REG (DR_REG_TWAIFD_BASE + 0x1c)
+/** TWAIFD_RX_FRM_SUC_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear TWAIFD_RX_FRM_SUC_INT.
+ */
+#define TWAIFD_RX_FRM_SUC_INT_CLR    (BIT(0))
+#define TWAIFD_RX_FRM_SUC_INT_CLR_M  (TWAIFD_RX_FRM_SUC_INT_CLR_V << TWAIFD_RX_FRM_SUC_INT_CLR_S)
+#define TWAIFD_RX_FRM_SUC_INT_CLR_V  0x00000001U
+#define TWAIFD_RX_FRM_SUC_INT_CLR_S  0
+/** TWAIFD_TX_FRM_SUC_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear TWAIFD_TX_FRM_SUC_INT.
+ */
+#define TWAIFD_TX_FRM_SUC_INT_CLR    (BIT(1))
+#define TWAIFD_TX_FRM_SUC_INT_CLR_M  (TWAIFD_TX_FRM_SUC_INT_CLR_V << TWAIFD_TX_FRM_SUC_INT_CLR_S)
+#define TWAIFD_TX_FRM_SUC_INT_CLR_V  0x00000001U
+#define TWAIFD_TX_FRM_SUC_INT_CLR_S  1
+/** TWAIFD_ERR_WARNING_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear TWAIFD_ERR_WARNING_INT.
+ */
+#define TWAIFD_ERR_WARNING_INT_CLR    (BIT(2))
+#define TWAIFD_ERR_WARNING_INT_CLR_M  (TWAIFD_ERR_WARNING_INT_CLR_V << TWAIFD_ERR_WARNING_INT_CLR_S)
+#define TWAIFD_ERR_WARNING_INT_CLR_V  0x00000001U
+#define TWAIFD_ERR_WARNING_INT_CLR_S  2
+/** TWAIFD_RX_DATA_OVERRUN_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear TWAIFD_RX_DATA_OVERRUN_INT.
+ */
+#define TWAIFD_RX_DATA_OVERRUN_INT_CLR    (BIT(3))
+#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_M  (TWAIFD_RX_DATA_OVERRUN_INT_CLR_V << TWAIFD_RX_DATA_OVERRUN_INT_CLR_S)
+#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_V  0x00000001U
+#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_S  3
+/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+ */
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR    (BIT(5))
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_S)
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_V  0x00000001U
+#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_S  5
+/** TWAIFD_ARB_LOST_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear TWAIFD_ARB_LOST_INT.
+ */
+#define TWAIFD_ARB_LOST_INT_CLR    (BIT(6))
+#define TWAIFD_ARB_LOST_INT_CLR_M  (TWAIFD_ARB_LOST_INT_CLR_V << TWAIFD_ARB_LOST_INT_CLR_S)
+#define TWAIFD_ARB_LOST_INT_CLR_V  0x00000001U
+#define TWAIFD_ARB_LOST_INT_CLR_S  6
+/** TWAIFD_ERR_DETECTED_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear TWAIFD_ERR_DETECTED_INT.
+ */
+#define TWAIFD_ERR_DETECTED_INT_CLR    (BIT(7))
+#define TWAIFD_ERR_DETECTED_INT_CLR_M  (TWAIFD_ERR_DETECTED_INT_CLR_V << TWAIFD_ERR_DETECTED_INT_CLR_S)
+#define TWAIFD_ERR_DETECTED_INT_CLR_V  0x00000001U
+#define TWAIFD_ERR_DETECTED_INT_CLR_S  7
+/** TWAIFD_IS_OVERLOAD_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear TWAIFD_IS_OVERLOAD_INT.
+ */
+#define TWAIFD_IS_OVERLOAD_INT_CLR    (BIT(8))
+#define TWAIFD_IS_OVERLOAD_INT_CLR_M  (TWAIFD_IS_OVERLOAD_INT_CLR_V << TWAIFD_IS_OVERLOAD_INT_CLR_S)
+#define TWAIFD_IS_OVERLOAD_INT_CLR_V  0x00000001U
+#define TWAIFD_IS_OVERLOAD_INT_CLR_S  8
+/** TWAIFD_RX_BUF_FULL_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear TWAIFD_RX_BUF_FULL_INT.
+ */
+#define TWAIFD_RX_BUF_FULL_INT_CLR    (BIT(9))
+#define TWAIFD_RX_BUF_FULL_INT_CLR_M  (TWAIFD_RX_BUF_FULL_INT_CLR_V << TWAIFD_RX_BUF_FULL_INT_CLR_S)
+#define TWAIFD_RX_BUF_FULL_INT_CLR_V  0x00000001U
+#define TWAIFD_RX_BUF_FULL_INT_CLR_S  9
+/** TWAIFD_BIT_RATE_SHIFT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Write 1 to clear TWAIFD_BIT_RATE_SHIFT_INT.
+ */
+#define TWAIFD_BIT_RATE_SHIFT_INT_CLR    (BIT(10))
+#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_M  (TWAIFD_BIT_RATE_SHIFT_INT_CLR_V << TWAIFD_BIT_RATE_SHIFT_INT_CLR_S)
+#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_V  0x00000001U
+#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_S  10
+/** TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Write 1 to clear TWAIFD_RX_BUF_NOT_EMPTY_INT.
+ */
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR    (BIT(11))
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_S)
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_V  0x00000001U
+#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_S  11
+/** TWAIFD_TX_BUF_STATUS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Write 1 to clear TWAIFD_TX_BUF_STATUS_CHG_INT.
+ */
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR    (BIT(12))
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_V << TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_S)
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_V  0x00000001U
+#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_S  12
+
+/** TWAIFD_BIT_TIMING_REG register
+ *  TWAI FD bit-timing  register
+ */
+#define TWAIFD_BIT_TIMING_REG (DR_REG_TWAIFD_BASE + 0x20)
+/** TWAIFD_PROP : R/W; bitpos: [6:0]; default: 5;
+ *  Configures the propagation segment of nominal bit rate.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_PROP    0x0000007FU
+#define TWAIFD_PROP_M  (TWAIFD_PROP_V << TWAIFD_PROP_S)
+#define TWAIFD_PROP_V  0x0000007FU
+#define TWAIFD_PROP_S  0
+/** TWAIFD_PH1 : R/W; bitpos: [12:7]; default: 3;
+ *  Configures the phase 1 segment of nominal bit rate.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_PH1    0x0000003FU
+#define TWAIFD_PH1_M  (TWAIFD_PH1_V << TWAIFD_PH1_S)
+#define TWAIFD_PH1_V  0x0000003FU
+#define TWAIFD_PH1_S  7
+/** TWAIFD_PH2 : R/W; bitpos: [18:13]; default: 5;
+ *  Configures the phase 2 segment of nominal bit rate.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_PH2    0x0000003FU
+#define TWAIFD_PH2_M  (TWAIFD_PH2_V << TWAIFD_PH2_S)
+#define TWAIFD_PH2_V  0x0000003FU
+#define TWAIFD_PH2_S  13
+/** TWAIFD_BRP : R/W; bitpos: [26:19]; default: 16;
+ *  Configures the baud-rate prescaler of nominal bit rate.\\
+ *  Measurement unit: cycle of core clock.
+ */
+#define TWAIFD_BRP    0x000000FFU
+#define TWAIFD_BRP_M  (TWAIFD_BRP_V << TWAIFD_BRP_S)
+#define TWAIFD_BRP_V  0x000000FFU
+#define TWAIFD_BRP_S  19
+/** TWAIFD_SJW : R/W; bitpos: [31:27]; default: 2;
+ *  Represents the synchronization jump width in nominal bit time.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_SJW    0x0000001FU
+#define TWAIFD_SJW_M  (TWAIFD_SJW_V << TWAIFD_SJW_S)
+#define TWAIFD_SJW_V  0x0000001FU
+#define TWAIFD_SJW_S  27
+
+/** TWAIFD_BIT_TIMEING_FD_REG register
+ *  TWAI FD bit-timing of FD register
+ */
+#define TWAIFD_BIT_TIMEING_FD_REG (DR_REG_TWAIFD_BASE + 0x24)
+/** TWAIFD_PROP_FD : R/W; bitpos: [5:0]; default: 3;
+ *  Configures the propagation segment of data bit rate.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_PROP_FD    0x0000003FU
+#define TWAIFD_PROP_FD_M  (TWAIFD_PROP_FD_V << TWAIFD_PROP_FD_S)
+#define TWAIFD_PROP_FD_V  0x0000003FU
+#define TWAIFD_PROP_FD_S  0
+/** TWAIFD_PH1_FD : R/W; bitpos: [11:7]; default: 3;
+ *  Configures the phase 1 segment of data bit rate.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_PH1_FD    0x0000001FU
+#define TWAIFD_PH1_FD_M  (TWAIFD_PH1_FD_V << TWAIFD_PH1_FD_S)
+#define TWAIFD_PH1_FD_V  0x0000001FU
+#define TWAIFD_PH1_FD_S  7
+/** TWAIFD_PH2_FD : R/W; bitpos: [17:13]; default: 3;
+ *  Configures the phase 2 segment of data bit rate.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_PH2_FD    0x0000001FU
+#define TWAIFD_PH2_FD_M  (TWAIFD_PH2_FD_V << TWAIFD_PH2_FD_S)
+#define TWAIFD_PH2_FD_V  0x0000001FU
+#define TWAIFD_PH2_FD_S  13
+/** TWAIFD_BRP_FD : R/W; bitpos: [26:19]; default: 4;
+ *  Configures the baud-rate prescaler of data bit rate.\\
+ *  Measurement unit: cycle of core clock.
+ */
+#define TWAIFD_BRP_FD    0x000000FFU
+#define TWAIFD_BRP_FD_M  (TWAIFD_BRP_FD_V << TWAIFD_BRP_FD_S)
+#define TWAIFD_BRP_FD_V  0x000000FFU
+#define TWAIFD_BRP_FD_S  19
+/** TWAIFD_SJW_FD : R/W; bitpos: [31:27]; default: 2;
+ *  Represents the synchronization jump width in data bit time.\\
+ *  Measurement unit: time quanta\\
+ */
+#define TWAIFD_SJW_FD    0x0000001FU
+#define TWAIFD_SJW_FD_M  (TWAIFD_SJW_FD_V << TWAIFD_SJW_FD_S)
+#define TWAIFD_SJW_FD_V  0x0000001FU
+#define TWAIFD_SJW_FD_S  27
+
+/** TWAIFD_ERR_TH_STAT_REG register
+ *  TWAI FD error threshold and status register
+ */
+#define TWAIFD_ERR_TH_STAT_REG (DR_REG_TWAIFD_BASE + 0x28)
+/** TWAIFD_ERR_WARNING_THRES : R/W; bitpos: [7:0]; default: 96;
+ *  Configures the error warning threshold.\\
+ */
+#define TWAIFD_ERR_WARNING_THRES    0x000000FFU
+#define TWAIFD_ERR_WARNING_THRES_M  (TWAIFD_ERR_WARNING_THRES_V << TWAIFD_ERR_WARNING_THRES_S)
+#define TWAIFD_ERR_WARNING_THRES_V  0x000000FFU
+#define TWAIFD_ERR_WARNING_THRES_S  0
+/** TWAIFD_ERR_PASSIVE_THRES : R/W; bitpos: [15:8]; default: 128;
+ *  Configures the error passive threshold.\\
+ */
+#define TWAIFD_ERR_PASSIVE_THRES    0x000000FFU
+#define TWAIFD_ERR_PASSIVE_THRES_M  (TWAIFD_ERR_PASSIVE_THRES_V << TWAIFD_ERR_PASSIVE_THRES_S)
+#define TWAIFD_ERR_PASSIVE_THRES_V  0x000000FFU
+#define TWAIFD_ERR_PASSIVE_THRES_S  8
+/** TWAIFD_ERR_ACTIVE : RO; bitpos: [16]; default: 1;
+ *  Represents the fault state of error active.\\
+ */
+#define TWAIFD_ERR_ACTIVE    (BIT(16))
+#define TWAIFD_ERR_ACTIVE_M  (TWAIFD_ERR_ACTIVE_V << TWAIFD_ERR_ACTIVE_S)
+#define TWAIFD_ERR_ACTIVE_V  0x00000001U
+#define TWAIFD_ERR_ACTIVE_S  16
+/** TWAIFD_ERR_PASSIVE : RO; bitpos: [17]; default: 0;
+ *  Represents the fault state of error passive.\\
+ */
+#define TWAIFD_ERR_PASSIVE    (BIT(17))
+#define TWAIFD_ERR_PASSIVE_M  (TWAIFD_ERR_PASSIVE_V << TWAIFD_ERR_PASSIVE_S)
+#define TWAIFD_ERR_PASSIVE_V  0x00000001U
+#define TWAIFD_ERR_PASSIVE_S  17
+/** TWAIFD_BUS_OFF : RO; bitpos: [18]; default: 0;
+ *  Represents the fault state of bus off.\\
+ */
+#define TWAIFD_BUS_OFF    (BIT(18))
+#define TWAIFD_BUS_OFF_M  (TWAIFD_BUS_OFF_V << TWAIFD_BUS_OFF_S)
+#define TWAIFD_BUS_OFF_V  0x00000001U
+#define TWAIFD_BUS_OFF_S  18
+
+/** TWAIFD_ERROR_COUNTERS_REG register
+ *  TWAI FD error counters status register
+ */
+#define TWAIFD_ERROR_COUNTERS_REG (DR_REG_TWAIFD_BASE + 0x2c)
+/** TWAIFD_RXC_VAL : RO; bitpos: [15:0]; default: 0;
+ *  Represents the receiver error counter value.\\
+ */
+#define TWAIFD_RXC_VAL    0x0000FFFFU
+#define TWAIFD_RXC_VAL_M  (TWAIFD_RXC_VAL_V << TWAIFD_RXC_VAL_S)
+#define TWAIFD_RXC_VAL_V  0x0000FFFFU
+#define TWAIFD_RXC_VAL_S  0
+/** TWAIFD_TXC_VAL : RO; bitpos: [31:16]; default: 0;
+ *  Represents the transmitter error counter value.\\
+ */
+#define TWAIFD_TXC_VAL    0x0000FFFFU
+#define TWAIFD_TXC_VAL_M  (TWAIFD_TXC_VAL_V << TWAIFD_TXC_VAL_S)
+#define TWAIFD_TXC_VAL_V  0x0000FFFFU
+#define TWAIFD_TXC_VAL_S  16
+
+/** TWAIFD_ERROR_COUNTERS_SP_REG register
+ *  TWAI FD special error counters status register
+ */
+#define TWAIFD_ERROR_COUNTERS_SP_REG (DR_REG_TWAIFD_BASE + 0x30)
+/** TWAIFD_ERR_FD_VAL : RO; bitpos: [15:0]; default: 0;
+ *  Represents the number of error in the data bit time.\\
+ */
+#define TWAIFD_ERR_FD_VAL    0x0000FFFFU
+#define TWAIFD_ERR_FD_VAL_M  (TWAIFD_ERR_FD_VAL_V << TWAIFD_ERR_FD_VAL_S)
+#define TWAIFD_ERR_FD_VAL_V  0x0000FFFFU
+#define TWAIFD_ERR_FD_VAL_S  0
+/** TWAIFD_ERR_NORM_VAL : RO; bitpos: [31:16]; default: 0;
+ *  Represents the number of error in the nominal bit time.\\
+ */
+#define TWAIFD_ERR_NORM_VAL    0x0000FFFFU
+#define TWAIFD_ERR_NORM_VAL_M  (TWAIFD_ERR_NORM_VAL_V << TWAIFD_ERR_NORM_VAL_S)
+#define TWAIFD_ERR_NORM_VAL_V  0x0000FFFFU
+#define TWAIFD_ERR_NORM_VAL_S  16
+
+/** TWAIFD_CTR_PRES_REG register
+ *  TWAI FD error counters pre-define configuration register
+ */
+#define TWAIFD_CTR_PRES_REG (DR_REG_TWAIFD_BASE + 0x34)
+/** TWAIFD_CTR_PRES_VAL : WO; bitpos: [8:0]; default: 0;
+ *  Configures the pre-defined value to set the error counter.\\
+ */
+#define TWAIFD_CTR_PRES_VAL    0x000001FFU
+#define TWAIFD_CTR_PRES_VAL_M  (TWAIFD_CTR_PRES_VAL_V << TWAIFD_CTR_PRES_VAL_S)
+#define TWAIFD_CTR_PRES_VAL_V  0x000001FFU
+#define TWAIFD_CTR_PRES_VAL_S  0
+/** TWAIFD_PTX : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to set the receiver error counter into the value of
+ *  pre-defined value.\\
+ *  0: invalid\\
+ *  1: set\\
+ */
+#define TWAIFD_PTX    (BIT(9))
+#define TWAIFD_PTX_M  (TWAIFD_PTX_V << TWAIFD_PTX_S)
+#define TWAIFD_PTX_V  0x00000001U
+#define TWAIFD_PTX_S  9
+/** TWAIFD_PRX : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to set the transmitter error counter into the value of
+ *  pre-defined value.\\
+ *  0: invalid\\
+ *  1: set\\
+ */
+#define TWAIFD_PRX    (BIT(10))
+#define TWAIFD_PRX_M  (TWAIFD_PRX_V << TWAIFD_PRX_S)
+#define TWAIFD_PRX_V  0x00000001U
+#define TWAIFD_PRX_S  10
+/** TWAIFD_ENORM : WO; bitpos: [11]; default: 0;
+ *  Configures whether or not to erase the error counter of nominal bit time.\\
+ *  0: invalid\\
+ *  1: erase\\
+ */
+#define TWAIFD_ENORM    (BIT(11))
+#define TWAIFD_ENORM_M  (TWAIFD_ENORM_V << TWAIFD_ENORM_S)
+#define TWAIFD_ENORM_V  0x00000001U
+#define TWAIFD_ENORM_S  11
+/** TWAIFD_EFD : WO; bitpos: [12]; default: 0;
+ *  Configures whether or not to erase the error counter of data bit time.\\
+ *  0: invalid\\
+ *  1: erase\\
+ */
+#define TWAIFD_EFD    (BIT(12))
+#define TWAIFD_EFD_M  (TWAIFD_EFD_V << TWAIFD_EFD_S)
+#define TWAIFD_EFD_V  0x00000001U
+#define TWAIFD_EFD_S  12
+
+/** TWAIFD_RX_MEM_INFO_REG register
+ *  TWAI FD rx memory information register
+ */
+#define TWAIFD_RX_MEM_INFO_REG (DR_REG_TWAIFD_BASE + 0x38)
+/** TWAIFD_RX_BUFF_SIZE_VAL : RO; bitpos: [12:0]; default: 0;
+ *  Represents the size of RX buffer.\\
+ */
+#define TWAIFD_RX_BUFF_SIZE_VAL    0x00001FFFU
+#define TWAIFD_RX_BUFF_SIZE_VAL_M  (TWAIFD_RX_BUFF_SIZE_VAL_V << TWAIFD_RX_BUFF_SIZE_VAL_S)
+#define TWAIFD_RX_BUFF_SIZE_VAL_V  0x00001FFFU
+#define TWAIFD_RX_BUFF_SIZE_VAL_S  0
+/** TWAIFD_RX_FREE_CTR : RO; bitpos: [28:16]; default: 0;
+ *  Represents the number of free words in RX buffer.\\
+ */
+#define TWAIFD_RX_FREE_CTR    0x00001FFFU
+#define TWAIFD_RX_FREE_CTR_M  (TWAIFD_RX_FREE_CTR_V << TWAIFD_RX_FREE_CTR_S)
+#define TWAIFD_RX_FREE_CTR_V  0x00001FFFU
+#define TWAIFD_RX_FREE_CTR_S  16
+
+/** TWAIFD_RX_POINTERS_REG register
+ *  TWAI FD rx memory pointer information register
+ */
+#define TWAIFD_RX_POINTERS_REG (DR_REG_TWAIFD_BASE + 0x3c)
+/** TWAIFD_RX_WPT_VAL : RO; bitpos: [11:0]; default: 0;
+ *  Represents the write pointer position in RX buffer.\\
+ */
+#define TWAIFD_RX_WPT_VAL    0x00000FFFU
+#define TWAIFD_RX_WPT_VAL_M  (TWAIFD_RX_WPT_VAL_V << TWAIFD_RX_WPT_VAL_S)
+#define TWAIFD_RX_WPT_VAL_V  0x00000FFFU
+#define TWAIFD_RX_WPT_VAL_S  0
+/** TWAIFD_RX_RPT_VAL : RO; bitpos: [27:16]; default: 0;
+ *  Represents the read pointer position in RX buffer.\\
+ */
+#define TWAIFD_RX_RPT_VAL    0x00000FFFU
+#define TWAIFD_RX_RPT_VAL_M  (TWAIFD_RX_RPT_VAL_V << TWAIFD_RX_RPT_VAL_S)
+#define TWAIFD_RX_RPT_VAL_V  0x00000FFFU
+#define TWAIFD_RX_RPT_VAL_S  16
+
+/** TWAIFD_RX_STATUS_SETTING_REG register
+ *  TWAI FD tx status & setting register
+ */
+#define TWAIFD_RX_STATUS_SETTING_REG (DR_REG_TWAIFD_BASE + 0x40)
+/** TWAIFD_RX_EMPTY : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the RX buffer is empty.\\
+ *  0: not empty\\
+ *  1: empty\\
+ */
+#define TWAIFD_RX_EMPTY    (BIT(0))
+#define TWAIFD_RX_EMPTY_M  (TWAIFD_RX_EMPTY_V << TWAIFD_RX_EMPTY_S)
+#define TWAIFD_RX_EMPTY_V  0x00000001U
+#define TWAIFD_RX_EMPTY_S  0
+/** TWAIFD_RX_FULL : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not the RX buffer is full.\\
+ *  0: not full\\
+ *  1: full\\
+ */
+#define TWAIFD_RX_FULL    (BIT(1))
+#define TWAIFD_RX_FULL_M  (TWAIFD_RX_FULL_V << TWAIFD_RX_FULL_S)
+#define TWAIFD_RX_FULL_V  0x00000001U
+#define TWAIFD_RX_FULL_S  1
+/** TWAIFD_RX_FRM_CTR : RO; bitpos: [14:4]; default: 0;
+ *  Represents the number of received frame in RX buffer.\\
+ */
+#define TWAIFD_RX_FRM_CTR    0x000007FFU
+#define TWAIFD_RX_FRM_CTR_M  (TWAIFD_RX_FRM_CTR_V << TWAIFD_RX_FRM_CTR_S)
+#define TWAIFD_RX_FRM_CTR_V  0x000007FFU
+#define TWAIFD_RX_FRM_CTR_S  4
+/** TWAIFD_RTSOP : R/W; bitpos: [16]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_RTSOP    (BIT(16))
+#define TWAIFD_RTSOP_M  (TWAIFD_RTSOP_V << TWAIFD_RTSOP_S)
+#define TWAIFD_RTSOP_V  0x00000001U
+#define TWAIFD_RTSOP_S  16
+
+/** TWAIFD_RX_DATA_REG register
+ *  TWAI FD received data register
+ */
+#define TWAIFD_RX_DATA_REG (DR_REG_TWAIFD_BASE + 0x44)
+/** TWAIFD_RX_DATA : RO; bitpos: [31:0]; default: 0;
+ *  Data received.
+ */
+#define TWAIFD_RX_DATA    0xFFFFFFFFU
+#define TWAIFD_RX_DATA_M  (TWAIFD_RX_DATA_V << TWAIFD_RX_DATA_S)
+#define TWAIFD_RX_DATA_V  0xFFFFFFFFU
+#define TWAIFD_RX_DATA_S  0
+
+/** TWAIFD_FILTER_A_MASK_REG register
+ *  TWAI FD filter A mask value register
+ */
+#define TWAIFD_FILTER_A_MASK_REG (DR_REG_TWAIFD_BASE + 0x60)
+/** TWAIFD_BIT_MASK_A : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit masked value.
+ */
+#define TWAIFD_BIT_MASK_A    0x1FFFFFFFU
+#define TWAIFD_BIT_MASK_A_M  (TWAIFD_BIT_MASK_A_V << TWAIFD_BIT_MASK_A_S)
+#define TWAIFD_BIT_MASK_A_V  0x1FFFFFFFU
+#define TWAIFD_BIT_MASK_A_S  0
+
+/** TWAIFD_FILTER_A_VAL_REG register
+ *  TWAI FD filter A bit value register
+ */
+#define TWAIFD_FILTER_A_VAL_REG (DR_REG_TWAIFD_BASE + 0x64)
+/** TWAIFD_BIT_VAL_A : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit value.
+ */
+#define TWAIFD_BIT_VAL_A    0x1FFFFFFFU
+#define TWAIFD_BIT_VAL_A_M  (TWAIFD_BIT_VAL_A_V << TWAIFD_BIT_VAL_A_S)
+#define TWAIFD_BIT_VAL_A_V  0x1FFFFFFFU
+#define TWAIFD_BIT_VAL_A_S  0
+
+/** TWAIFD_FILTER_B_MASK_REG register
+ *  TWAI FD filter B mask value register
+ */
+#define TWAIFD_FILTER_B_MASK_REG (DR_REG_TWAIFD_BASE + 0x68)
+/** TWAIFD_BIT_MASK_B : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit masked value.
+ */
+#define TWAIFD_BIT_MASK_B    0x1FFFFFFFU
+#define TWAIFD_BIT_MASK_B_M  (TWAIFD_BIT_MASK_B_V << TWAIFD_BIT_MASK_B_S)
+#define TWAIFD_BIT_MASK_B_V  0x1FFFFFFFU
+#define TWAIFD_BIT_MASK_B_S  0
+
+/** TWAIFD_FILTER_B_VAL_REG register
+ *  TWAI FD filter B bit value register
+ */
+#define TWAIFD_FILTER_B_VAL_REG (DR_REG_TWAIFD_BASE + 0x6c)
+/** TWAIFD_BIT_VAL_B : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit value.
+ */
+#define TWAIFD_BIT_VAL_B    0x1FFFFFFFU
+#define TWAIFD_BIT_VAL_B_M  (TWAIFD_BIT_VAL_B_V << TWAIFD_BIT_VAL_B_S)
+#define TWAIFD_BIT_VAL_B_V  0x1FFFFFFFU
+#define TWAIFD_BIT_VAL_B_S  0
+
+/** TWAIFD_FILTER_C_MASK_REG register
+ *  TWAI FD filter C mask value register
+ */
+#define TWAIFD_FILTER_C_MASK_REG (DR_REG_TWAIFD_BASE + 0x70)
+/** TWAIFD_BIT_MASK_C : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit masked value.
+ */
+#define TWAIFD_BIT_MASK_C    0x1FFFFFFFU
+#define TWAIFD_BIT_MASK_C_M  (TWAIFD_BIT_MASK_C_V << TWAIFD_BIT_MASK_C_S)
+#define TWAIFD_BIT_MASK_C_V  0x1FFFFFFFU
+#define TWAIFD_BIT_MASK_C_S  0
+
+/** TWAIFD_FILTER_C_VAL_REG register
+ *  TWAI FD filter C bit value register
+ */
+#define TWAIFD_FILTER_C_VAL_REG (DR_REG_TWAIFD_BASE + 0x74)
+/** TWAIFD_BIT_VAL_C : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit value.
+ */
+#define TWAIFD_BIT_VAL_C    0x1FFFFFFFU
+#define TWAIFD_BIT_VAL_C_M  (TWAIFD_BIT_VAL_C_V << TWAIFD_BIT_VAL_C_S)
+#define TWAIFD_BIT_VAL_C_V  0x1FFFFFFFU
+#define TWAIFD_BIT_VAL_C_S  0
+
+/** TWAIFD_FILTER_RAN_LOW_REG register
+ *  TWAI FD filter range low value register
+ */
+#define TWAIFD_FILTER_RAN_LOW_REG (DR_REG_TWAIFD_BASE + 0x78)
+/** TWAIFD_BIT_RAN_LOW : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit masked value.
+ */
+#define TWAIFD_BIT_RAN_LOW    0x1FFFFFFFU
+#define TWAIFD_BIT_RAN_LOW_M  (TWAIFD_BIT_RAN_LOW_V << TWAIFD_BIT_RAN_LOW_S)
+#define TWAIFD_BIT_RAN_LOW_V  0x1FFFFFFFU
+#define TWAIFD_BIT_RAN_LOW_S  0
+
+/** TWAIFD_FILTER_RAN_HIGH_REG register
+ *  TWAI FD filter range high value register
+ */
+#define TWAIFD_FILTER_RAN_HIGH_REG (DR_REG_TWAIFD_BASE + 0x7c)
+/** TWAIFD_BIT_RAN_HIGH : R/W; bitpos: [28:0]; default: 0;
+ *  filter A bit value.
+ */
+#define TWAIFD_BIT_RAN_HIGH    0x1FFFFFFFU
+#define TWAIFD_BIT_RAN_HIGH_M  (TWAIFD_BIT_RAN_HIGH_V << TWAIFD_BIT_RAN_HIGH_S)
+#define TWAIFD_BIT_RAN_HIGH_V  0x1FFFFFFFU
+#define TWAIFD_BIT_RAN_HIGH_S  0
+
+/** TWAIFD_FILTER_CONTROL_REG register
+ *  TWAI FD filter control register
+ */
+#define TWAIFD_FILTER_CONTROL_REG (DR_REG_TWAIFD_BASE + 0x80)
+/** TWAIFD_FANB : R/W; bitpos: [0]; default: 1;
+ *  filter A with nominal and base mode.
+ */
+#define TWAIFD_FANB    (BIT(0))
+#define TWAIFD_FANB_M  (TWAIFD_FANB_V << TWAIFD_FANB_S)
+#define TWAIFD_FANB_V  0x00000001U
+#define TWAIFD_FANB_S  0
+/** TWAIFD_FANE : R/W; bitpos: [1]; default: 1;
+ *  filter A with nominal and extended mode.
+ */
+#define TWAIFD_FANE    (BIT(1))
+#define TWAIFD_FANE_M  (TWAIFD_FANE_V << TWAIFD_FANE_S)
+#define TWAIFD_FANE_V  0x00000001U
+#define TWAIFD_FANE_S  1
+/** TWAIFD_FAFB : R/W; bitpos: [2]; default: 1;
+ *  filter A with FD and base mode.
+ */
+#define TWAIFD_FAFB    (BIT(2))
+#define TWAIFD_FAFB_M  (TWAIFD_FAFB_V << TWAIFD_FAFB_S)
+#define TWAIFD_FAFB_V  0x00000001U
+#define TWAIFD_FAFB_S  2
+/** TWAIFD_FAFE : R/W; bitpos: [3]; default: 1;
+ *  filter A with FD and extended mode.
+ */
+#define TWAIFD_FAFE    (BIT(3))
+#define TWAIFD_FAFE_M  (TWAIFD_FAFE_V << TWAIFD_FAFE_S)
+#define TWAIFD_FAFE_V  0x00000001U
+#define TWAIFD_FAFE_S  3
+/** TWAIFD_FBNB : R/W; bitpos: [4]; default: 0;
+ *  filter B with nominal and base mode.
+ */
+#define TWAIFD_FBNB    (BIT(4))
+#define TWAIFD_FBNB_M  (TWAIFD_FBNB_V << TWAIFD_FBNB_S)
+#define TWAIFD_FBNB_V  0x00000001U
+#define TWAIFD_FBNB_S  4
+/** TWAIFD_FBNE : R/W; bitpos: [5]; default: 0;
+ *  filter B with nominal and extended mode.
+ */
+#define TWAIFD_FBNE    (BIT(5))
+#define TWAIFD_FBNE_M  (TWAIFD_FBNE_V << TWAIFD_FBNE_S)
+#define TWAIFD_FBNE_V  0x00000001U
+#define TWAIFD_FBNE_S  5
+/** TWAIFD_FBFB : R/W; bitpos: [6]; default: 0;
+ *  filter B with FD and base mode.
+ */
+#define TWAIFD_FBFB    (BIT(6))
+#define TWAIFD_FBFB_M  (TWAIFD_FBFB_V << TWAIFD_FBFB_S)
+#define TWAIFD_FBFB_V  0x00000001U
+#define TWAIFD_FBFB_S  6
+/** TWAIFD_FBFE : R/W; bitpos: [7]; default: 0;
+ *  filter B with FD and extended mode.
+ */
+#define TWAIFD_FBFE    (BIT(7))
+#define TWAIFD_FBFE_M  (TWAIFD_FBFE_V << TWAIFD_FBFE_S)
+#define TWAIFD_FBFE_V  0x00000001U
+#define TWAIFD_FBFE_S  7
+/** TWAIFD_FCNB : R/W; bitpos: [8]; default: 0;
+ *  filter C with nominal and base mode.
+ */
+#define TWAIFD_FCNB    (BIT(8))
+#define TWAIFD_FCNB_M  (TWAIFD_FCNB_V << TWAIFD_FCNB_S)
+#define TWAIFD_FCNB_V  0x00000001U
+#define TWAIFD_FCNB_S  8
+/** TWAIFD_FCNE : R/W; bitpos: [9]; default: 0;
+ *  filter C with nominal and extended mode.
+ */
+#define TWAIFD_FCNE    (BIT(9))
+#define TWAIFD_FCNE_M  (TWAIFD_FCNE_V << TWAIFD_FCNE_S)
+#define TWAIFD_FCNE_V  0x00000001U
+#define TWAIFD_FCNE_S  9
+/** TWAIFD_FCFB : R/W; bitpos: [10]; default: 0;
+ *  filter C with FD and base mode.
+ */
+#define TWAIFD_FCFB    (BIT(10))
+#define TWAIFD_FCFB_M  (TWAIFD_FCFB_V << TWAIFD_FCFB_S)
+#define TWAIFD_FCFB_V  0x00000001U
+#define TWAIFD_FCFB_S  10
+/** TWAIFD_FCFE : R/W; bitpos: [11]; default: 0;
+ *  filter C with FD and extended mode.
+ */
+#define TWAIFD_FCFE    (BIT(11))
+#define TWAIFD_FCFE_M  (TWAIFD_FCFE_V << TWAIFD_FCFE_S)
+#define TWAIFD_FCFE_V  0x00000001U
+#define TWAIFD_FCFE_S  11
+/** TWAIFD_FRNB : R/W; bitpos: [12]; default: 0;
+ *  filter range with nominal and base mode.
+ */
+#define TWAIFD_FRNB    (BIT(12))
+#define TWAIFD_FRNB_M  (TWAIFD_FRNB_V << TWAIFD_FRNB_S)
+#define TWAIFD_FRNB_V  0x00000001U
+#define TWAIFD_FRNB_S  12
+/** TWAIFD_FRNE : R/W; bitpos: [13]; default: 0;
+ *  filter range with nominal and extended mode.
+ */
+#define TWAIFD_FRNE    (BIT(13))
+#define TWAIFD_FRNE_M  (TWAIFD_FRNE_V << TWAIFD_FRNE_S)
+#define TWAIFD_FRNE_V  0x00000001U
+#define TWAIFD_FRNE_S  13
+/** TWAIFD_FRFB : R/W; bitpos: [14]; default: 0;
+ *  filter range with FD and base mode.
+ */
+#define TWAIFD_FRFB    (BIT(14))
+#define TWAIFD_FRFB_M  (TWAIFD_FRFB_V << TWAIFD_FRFB_S)
+#define TWAIFD_FRFB_V  0x00000001U
+#define TWAIFD_FRFB_S  14
+/** TWAIFD_FRFE : R/W; bitpos: [15]; default: 0;
+ *  filter range with FD and extended mode.
+ */
+#define TWAIFD_FRFE    (BIT(15))
+#define TWAIFD_FRFE_M  (TWAIFD_FRFE_V << TWAIFD_FRFE_S)
+#define TWAIFD_FRFE_V  0x00000001U
+#define TWAIFD_FRFE_S  15
+/** TWAIFD_SFA : RO; bitpos: [16]; default: 0;
+ *  filter A status
+ */
+#define TWAIFD_SFA    (BIT(16))
+#define TWAIFD_SFA_M  (TWAIFD_SFA_V << TWAIFD_SFA_S)
+#define TWAIFD_SFA_V  0x00000001U
+#define TWAIFD_SFA_S  16
+/** TWAIFD_SFB : RO; bitpos: [17]; default: 0;
+ *  filter B status
+ */
+#define TWAIFD_SFB    (BIT(17))
+#define TWAIFD_SFB_M  (TWAIFD_SFB_V << TWAIFD_SFB_S)
+#define TWAIFD_SFB_V  0x00000001U
+#define TWAIFD_SFB_S  17
+/** TWAIFD_SFC : RO; bitpos: [18]; default: 0;
+ *  filter C status
+ */
+#define TWAIFD_SFC    (BIT(18))
+#define TWAIFD_SFC_M  (TWAIFD_SFC_V << TWAIFD_SFC_S)
+#define TWAIFD_SFC_V  0x00000001U
+#define TWAIFD_SFC_S  18
+/** TWAIFD_SFR : RO; bitpos: [19]; default: 0;
+ *  filter range status
+ */
+#define TWAIFD_SFR    (BIT(19))
+#define TWAIFD_SFR_M  (TWAIFD_SFR_V << TWAIFD_SFR_S)
+#define TWAIFD_SFR_V  0x00000001U
+#define TWAIFD_SFR_S  19
+
+/** TWAIFD_TX_STAT_REG register
+ *  TWAI FD TX buffer status register
+ */
+#define TWAIFD_TX_STAT_REG (DR_REG_TWAIFD_BASE + 0x94)
+/** TWAIFD_TXT_1_EMPTY : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the TX buffer1 is empty.\\
+ *  0: not empty\\
+ *  1: empty\\
+ */
+#define TWAIFD_TXT_1_EMPTY    (BIT(0))
+#define TWAIFD_TXT_1_EMPTY_M  (TWAIFD_TXT_1_EMPTY_V << TWAIFD_TXT_1_EMPTY_S)
+#define TWAIFD_TXT_1_EMPTY_V  0x00000001U
+#define TWAIFD_TXT_1_EMPTY_S  0
+/** TWAIFD_TXT_2_EMPTY : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not the TX buffer2 is empty.\\
+ *  0: not empty\\
+ *  1: empty\\
+ */
+#define TWAIFD_TXT_2_EMPTY    (BIT(1))
+#define TWAIFD_TXT_2_EMPTY_M  (TWAIFD_TXT_2_EMPTY_V << TWAIFD_TXT_2_EMPTY_S)
+#define TWAIFD_TXT_2_EMPTY_V  0x00000001U
+#define TWAIFD_TXT_2_EMPTY_S  1
+
+/** TWAIFD_TX_CFG_REG register
+ *  TWAI FD TX buffer configuration register
+ */
+#define TWAIFD_TX_CFG_REG (DR_REG_TWAIFD_BASE + 0x98)
+/** TWAIFD_TXT_1_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether or not allow transmitting frames from TX buffer1.\\
+ *  0: not allow\\
+ *  1: allow\\
+ */
+#define TWAIFD_TXT_1_ALLOW    (BIT(0))
+#define TWAIFD_TXT_1_ALLOW_M  (TWAIFD_TXT_1_ALLOW_V << TWAIFD_TXT_1_ALLOW_S)
+#define TWAIFD_TXT_1_ALLOW_V  0x00000001U
+#define TWAIFD_TXT_1_ALLOW_S  0
+/** TWAIFD_TXT_2_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether or not allow transmitting frames from TX buffer2.\\
+ *  0: not allow\\
+ *  1: allow\\
+ */
+#define TWAIFD_TXT_2_ALLOW    (BIT(1))
+#define TWAIFD_TXT_2_ALLOW_M  (TWAIFD_TXT_2_ALLOW_V << TWAIFD_TXT_2_ALLOW_S)
+#define TWAIFD_TXT_2_ALLOW_V  0x00000001U
+#define TWAIFD_TXT_2_ALLOW_S  1
+/** TWAIFD_TXT_1_COMMIT : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not the frames from TX register are inserted into TX
+ *  buffer1.\\
+ *  0: not inserted\\
+ *  1: inserted\\
+ */
+#define TWAIFD_TXT_1_COMMIT    (BIT(2))
+#define TWAIFD_TXT_1_COMMIT_M  (TWAIFD_TXT_1_COMMIT_V << TWAIFD_TXT_1_COMMIT_S)
+#define TWAIFD_TXT_1_COMMIT_V  0x00000001U
+#define TWAIFD_TXT_1_COMMIT_S  2
+/** TWAIFD_TXT_2_COMMIT : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not the frames from TX register are inserted into TX
+ *  buffer2.\\
+ *  0: not inserted\\
+ *  1: inserted\\
+ */
+#define TWAIFD_TXT_2_COMMIT    (BIT(3))
+#define TWAIFD_TXT_2_COMMIT_M  (TWAIFD_TXT_2_COMMIT_V << TWAIFD_TXT_2_COMMIT_S)
+#define TWAIFD_TXT_2_COMMIT_V  0x00000001U
+#define TWAIFD_TXT_2_COMMIT_S  3
+
+/** TWAIFD_TX_DATA_0_REG register
+ *  TWAI FD transmit data register 0
+ */
+#define TWAIFD_TX_DATA_0_REG (DR_REG_TWAIFD_BASE + 0x9c)
+/** TWAIFD_DLC_TX : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the brs to be transmitted.
+ */
+#define TWAIFD_DLC_TX    0x0000000FU
+#define TWAIFD_DLC_TX_M  (TWAIFD_DLC_TX_V << TWAIFD_DLC_TX_S)
+#define TWAIFD_DLC_TX_V  0x0000000FU
+#define TWAIFD_DLC_TX_S  0
+/** TWAIFD_RTR_TX : R/W; bitpos: [5]; default: 0;
+ *  Configures the rtr bit to be transmitted.
+ */
+#define TWAIFD_RTR_TX    (BIT(5))
+#define TWAIFD_RTR_TX_M  (TWAIFD_RTR_TX_V << TWAIFD_RTR_TX_S)
+#define TWAIFD_RTR_TX_V  0x00000001U
+#define TWAIFD_RTR_TX_S  5
+/** TWAIFD_ID_TYPE_TX : R/W; bitpos: [6]; default: 0;
+ *  Configures the frame type to be transmitted.
+ */
+#define TWAIFD_ID_TYPE_TX    (BIT(6))
+#define TWAIFD_ID_TYPE_TX_M  (TWAIFD_ID_TYPE_TX_V << TWAIFD_ID_TYPE_TX_S)
+#define TWAIFD_ID_TYPE_TX_V  0x00000001U
+#define TWAIFD_ID_TYPE_TX_S  6
+/** TWAIFD_FR_TYPE_TX : R/W; bitpos: [7]; default: 0;
+ *  Configures the fd type to be transmitted.
+ */
+#define TWAIFD_FR_TYPE_TX    (BIT(7))
+#define TWAIFD_FR_TYPE_TX_M  (TWAIFD_FR_TYPE_TX_V << TWAIFD_FR_TYPE_TX_S)
+#define TWAIFD_FR_TYPE_TX_V  0x00000001U
+#define TWAIFD_FR_TYPE_TX_S  7
+/** TWAIFD_TBF_TX : R/W; bitpos: [8]; default: 0;
+ *  Configures the tbf bit to be transmitted.
+ */
+#define TWAIFD_TBF_TX    (BIT(8))
+#define TWAIFD_TBF_TX_M  (TWAIFD_TBF_TX_V << TWAIFD_TBF_TX_S)
+#define TWAIFD_TBF_TX_V  0x00000001U
+#define TWAIFD_TBF_TX_S  8
+/** TWAIFD_BRS_TX : R/W; bitpos: [9]; default: 0;
+ *  Configures the brs bit to be transmitted.
+ */
+#define TWAIFD_BRS_TX    (BIT(9))
+#define TWAIFD_BRS_TX_M  (TWAIFD_BRS_TX_V << TWAIFD_BRS_TX_S)
+#define TWAIFD_BRS_TX_V  0x00000001U
+#define TWAIFD_BRS_TX_S  9
+
+/** TWAIFD_TX_DATA_1_REG register
+ *  TWAI FD transmit data register 1
+ */
+#define TWAIFD_TX_DATA_1_REG (DR_REG_TWAIFD_BASE + 0xa0)
+/** TWAIFD_TS_VAL_U_TX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper timestamp to be transmitted
+ */
+#define TWAIFD_TS_VAL_U_TX    0xFFFFFFFFU
+#define TWAIFD_TS_VAL_U_TX_M  (TWAIFD_TS_VAL_U_TX_V << TWAIFD_TS_VAL_U_TX_S)
+#define TWAIFD_TS_VAL_U_TX_V  0xFFFFFFFFU
+#define TWAIFD_TS_VAL_U_TX_S  0
+
+/** TWAIFD_TX_DATA_2_REG register
+ *  TWAI FD transmit data register 2
+ */
+#define TWAIFD_TX_DATA_2_REG (DR_REG_TWAIFD_BASE + 0xa4)
+/** TWAIFD_TS_VAL_L_TX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the lower timestamp to be transmitted
+ */
+#define TWAIFD_TS_VAL_L_TX    0xFFFFFFFFU
+#define TWAIFD_TS_VAL_L_TX_M  (TWAIFD_TS_VAL_L_TX_V << TWAIFD_TS_VAL_L_TX_S)
+#define TWAIFD_TS_VAL_L_TX_V  0xFFFFFFFFU
+#define TWAIFD_TS_VAL_L_TX_S  0
+
+/** TWAIFD_TX_DATA_3_REG register
+ *  TWAI FD transmit data register 3
+ */
+#define TWAIFD_TX_DATA_3_REG (DR_REG_TWAIFD_BASE + 0xa8)
+/** TWAIFD_ID_EXT_TX : R/W; bitpos: [17:0]; default: 0;
+ *  Configures the base ID to be transmitted
+ */
+#define TWAIFD_ID_EXT_TX    0x0003FFFFU
+#define TWAIFD_ID_EXT_TX_M  (TWAIFD_ID_EXT_TX_V << TWAIFD_ID_EXT_TX_S)
+#define TWAIFD_ID_EXT_TX_V  0x0003FFFFU
+#define TWAIFD_ID_EXT_TX_S  0
+/** TWAIFD_ID_BASE_TX : R/W; bitpos: [28:18]; default: 0;
+ *  Configures the extended ID to be transmitted
+ */
+#define TWAIFD_ID_BASE_TX    0x000007FFU
+#define TWAIFD_ID_BASE_TX_M  (TWAIFD_ID_BASE_TX_V << TWAIFD_ID_BASE_TX_S)
+#define TWAIFD_ID_BASE_TX_V  0x000007FFU
+#define TWAIFD_ID_BASE_TX_S  18
+
+/** TWAIFD_TX_DATA_4_REG register
+ *  TWAI FD transmit data register 4
+ */
+#define TWAIFD_TX_DATA_4_REG (DR_REG_TWAIFD_BASE + 0xac)
+/** TWAIFD_TX_DATA0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th word to be transmitted
+ */
+#define TWAIFD_TX_DATA0    0xFFFFFFFFU
+#define TWAIFD_TX_DATA0_M  (TWAIFD_TX_DATA0_V << TWAIFD_TX_DATA0_S)
+#define TWAIFD_TX_DATA0_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA0_S  0
+
+/** TWAIFD_TX_DATA_5_REG register
+ *  TWAI FD transmit data register 5
+ */
+#define TWAIFD_TX_DATA_5_REG (DR_REG_TWAIFD_BASE + 0xb0)
+/** TWAIFD_TX_DATA1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1th word to be transmitted
+ */
+#define TWAIFD_TX_DATA1    0xFFFFFFFFU
+#define TWAIFD_TX_DATA1_M  (TWAIFD_TX_DATA1_V << TWAIFD_TX_DATA1_S)
+#define TWAIFD_TX_DATA1_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA1_S  0
+
+/** TWAIFD_TX_DATA_6_REG register
+ *  TWAI FD transmit data register 6
+ */
+#define TWAIFD_TX_DATA_6_REG (DR_REG_TWAIFD_BASE + 0xb4)
+/** TWAIFD_TX_DATA2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2th word to be transmitted
+ */
+#define TWAIFD_TX_DATA2    0xFFFFFFFFU
+#define TWAIFD_TX_DATA2_M  (TWAIFD_TX_DATA2_V << TWAIFD_TX_DATA2_S)
+#define TWAIFD_TX_DATA2_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA2_S  0
+
+/** TWAIFD_TX_DATA_7_REG register
+ *  TWAI FD transmit data register 7
+ */
+#define TWAIFD_TX_DATA_7_REG (DR_REG_TWAIFD_BASE + 0xb8)
+/** TWAIFD_TX_DATA3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3th word to be transmitted
+ */
+#define TWAIFD_TX_DATA3    0xFFFFFFFFU
+#define TWAIFD_TX_DATA3_M  (TWAIFD_TX_DATA3_V << TWAIFD_TX_DATA3_S)
+#define TWAIFD_TX_DATA3_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA3_S  0
+
+/** TWAIFD_TX_DATA_8_REG register
+ *  TWAI FD transmit data register 8
+ */
+#define TWAIFD_TX_DATA_8_REG (DR_REG_TWAIFD_BASE + 0xbc)
+/** TWAIFD_TX_DATA4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th word to be transmitted
+ */
+#define TWAIFD_TX_DATA4    0xFFFFFFFFU
+#define TWAIFD_TX_DATA4_M  (TWAIFD_TX_DATA4_V << TWAIFD_TX_DATA4_S)
+#define TWAIFD_TX_DATA4_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA4_S  0
+
+/** TWAIFD_TX_DATA_9_REG register
+ *  TWAI FD transmit data register 9
+ */
+#define TWAIFD_TX_DATA_9_REG (DR_REG_TWAIFD_BASE + 0xc0)
+/** TWAIFD_TX_DATA5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th word to be transmitted
+ */
+#define TWAIFD_TX_DATA5    0xFFFFFFFFU
+#define TWAIFD_TX_DATA5_M  (TWAIFD_TX_DATA5_V << TWAIFD_TX_DATA5_S)
+#define TWAIFD_TX_DATA5_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA5_S  0
+
+/** TWAIFD_TX_DATA_10_REG register
+ *  TWAI FD transmit data register 10
+ */
+#define TWAIFD_TX_DATA_10_REG (DR_REG_TWAIFD_BASE + 0xc4)
+/** TWAIFD_TX_DATA6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th word to be transmitted
+ */
+#define TWAIFD_TX_DATA6    0xFFFFFFFFU
+#define TWAIFD_TX_DATA6_M  (TWAIFD_TX_DATA6_V << TWAIFD_TX_DATA6_S)
+#define TWAIFD_TX_DATA6_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA6_S  0
+
+/** TWAIFD_TX_DATA_11_REG register
+ *  TWAI FD transmit data register 11
+ */
+#define TWAIFD_TX_DATA_11_REG (DR_REG_TWAIFD_BASE + 0xc8)
+/** TWAIFD_TX_DATA7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th word to be transmitted
+ */
+#define TWAIFD_TX_DATA7    0xFFFFFFFFU
+#define TWAIFD_TX_DATA7_M  (TWAIFD_TX_DATA7_V << TWAIFD_TX_DATA7_S)
+#define TWAIFD_TX_DATA7_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA7_S  0
+
+/** TWAIFD_TX_DATA_12_REG register
+ *  TWAI FD transmit data register 12
+ */
+#define TWAIFD_TX_DATA_12_REG (DR_REG_TWAIFD_BASE + 0xcc)
+/** TWAIFD_TX_DATA8 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 8th word to be transmitted
+ */
+#define TWAIFD_TX_DATA8    0xFFFFFFFFU
+#define TWAIFD_TX_DATA8_M  (TWAIFD_TX_DATA8_V << TWAIFD_TX_DATA8_S)
+#define TWAIFD_TX_DATA8_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA8_S  0
+
+/** TWAIFD_TX_DATA_13_REG register
+ *  TWAI FD transmit data register 13
+ */
+#define TWAIFD_TX_DATA_13_REG (DR_REG_TWAIFD_BASE + 0xd0)
+/** TWAIFD_TX_DATA9 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 9th word to be transmitted
+ */
+#define TWAIFD_TX_DATA9    0xFFFFFFFFU
+#define TWAIFD_TX_DATA9_M  (TWAIFD_TX_DATA9_V << TWAIFD_TX_DATA9_S)
+#define TWAIFD_TX_DATA9_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA9_S  0
+
+/** TWAIFD_TX_DATA_14_REG register
+ *  TWAI FD transmit data register 14
+ */
+#define TWAIFD_TX_DATA_14_REG (DR_REG_TWAIFD_BASE + 0xd4)
+/** TWAIFD_TX_DATA10 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 10th word to be transmitted
+ */
+#define TWAIFD_TX_DATA10    0xFFFFFFFFU
+#define TWAIFD_TX_DATA10_M  (TWAIFD_TX_DATA10_V << TWAIFD_TX_DATA10_S)
+#define TWAIFD_TX_DATA10_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA10_S  0
+
+/** TWAIFD_TX_DATA_15_REG register
+ *  TWAI FD transmit data register 15
+ */
+#define TWAIFD_TX_DATA_15_REG (DR_REG_TWAIFD_BASE + 0xd8)
+/** TWAIFD_TX_DATA11 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 11th word to be transmitted
+ */
+#define TWAIFD_TX_DATA11    0xFFFFFFFFU
+#define TWAIFD_TX_DATA11_M  (TWAIFD_TX_DATA11_V << TWAIFD_TX_DATA11_S)
+#define TWAIFD_TX_DATA11_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA11_S  0
+
+/** TWAIFD_TX_DATA_16_REG register
+ *  TWAI FD transmit data register 16
+ */
+#define TWAIFD_TX_DATA_16_REG (DR_REG_TWAIFD_BASE + 0xdc)
+/** TWAIFD_TX_DATA12 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 12th word to be transmitted
+ */
+#define TWAIFD_TX_DATA12    0xFFFFFFFFU
+#define TWAIFD_TX_DATA12_M  (TWAIFD_TX_DATA12_V << TWAIFD_TX_DATA12_S)
+#define TWAIFD_TX_DATA12_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA12_S  0
+
+/** TWAIFD_TX_DATA_17_REG register
+ *  TWAI FD transmit data register 17
+ */
+#define TWAIFD_TX_DATA_17_REG (DR_REG_TWAIFD_BASE + 0xe0)
+/** TWAIFD_TX_DATA13 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 13th word to be transmitted
+ */
+#define TWAIFD_TX_DATA13    0xFFFFFFFFU
+#define TWAIFD_TX_DATA13_M  (TWAIFD_TX_DATA13_V << TWAIFD_TX_DATA13_S)
+#define TWAIFD_TX_DATA13_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA13_S  0
+
+/** TWAIFD_TX_DATA_18_REG register
+ *  TWAI FD transmit data register 18
+ */
+#define TWAIFD_TX_DATA_18_REG (DR_REG_TWAIFD_BASE + 0xe4)
+/** TWAIFD_TX_DATA14 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 14th word to be transmitted
+ */
+#define TWAIFD_TX_DATA14    0xFFFFFFFFU
+#define TWAIFD_TX_DATA14_M  (TWAIFD_TX_DATA14_V << TWAIFD_TX_DATA14_S)
+#define TWAIFD_TX_DATA14_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA14_S  0
+
+/** TWAIFD_TX_DATA_19_REG register
+ *  TWAI FD transmit data register 19
+ */
+#define TWAIFD_TX_DATA_19_REG (DR_REG_TWAIFD_BASE + 0xe8)
+/** TWAIFD_TX_DATA15 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 15th word to be transmitted
+ */
+#define TWAIFD_TX_DATA15    0xFFFFFFFFU
+#define TWAIFD_TX_DATA15_M  (TWAIFD_TX_DATA15_V << TWAIFD_TX_DATA15_S)
+#define TWAIFD_TX_DATA15_V  0xFFFFFFFFU
+#define TWAIFD_TX_DATA15_S  0
+
+/** TWAIFD_TX_CAMMAND_INFO_REG register
+ *  TWAI FD TXT buffer command & information register
+ */
+#define TWAIFD_TX_CAMMAND_INFO_REG (DR_REG_TWAIFD_BASE + 0x14c)
+/** TWAIFD_TXTB_SW_SET_ETY : R/W; bitpos: [0]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXTB_SW_SET_ETY    (BIT(0))
+#define TWAIFD_TXTB_SW_SET_ETY_M  (TWAIFD_TXTB_SW_SET_ETY_V << TWAIFD_TXTB_SW_SET_ETY_S)
+#define TWAIFD_TXTB_SW_SET_ETY_V  0x00000001U
+#define TWAIFD_TXTB_SW_SET_ETY_S  0
+/** TWAIFD_TXTB_SW_SET_RDY : R/W; bitpos: [1]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXTB_SW_SET_RDY    (BIT(1))
+#define TWAIFD_TXTB_SW_SET_RDY_M  (TWAIFD_TXTB_SW_SET_RDY_V << TWAIFD_TXTB_SW_SET_RDY_S)
+#define TWAIFD_TXTB_SW_SET_RDY_V  0x00000001U
+#define TWAIFD_TXTB_SW_SET_RDY_S  1
+/** TWAIFD_TXTB_SW_SET_ABT : R/W; bitpos: [2]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXTB_SW_SET_ABT    (BIT(2))
+#define TWAIFD_TXTB_SW_SET_ABT_M  (TWAIFD_TXTB_SW_SET_ABT_V << TWAIFD_TXTB_SW_SET_ABT_S)
+#define TWAIFD_TXTB_SW_SET_ABT_V  0x00000001U
+#define TWAIFD_TXTB_SW_SET_ABT_S  2
+/** TWAIFD_TXB1 : R/W; bitpos: [8]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB1    (BIT(8))
+#define TWAIFD_TXB1_M  (TWAIFD_TXB1_V << TWAIFD_TXB1_S)
+#define TWAIFD_TXB1_V  0x00000001U
+#define TWAIFD_TXB1_S  8
+/** TWAIFD_TXB2 : R/W; bitpos: [9]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB2    (BIT(9))
+#define TWAIFD_TXB2_M  (TWAIFD_TXB2_V << TWAIFD_TXB2_S)
+#define TWAIFD_TXB2_V  0x00000001U
+#define TWAIFD_TXB2_S  9
+/** TWAIFD_TXB3 : R/W; bitpos: [10]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB3    (BIT(10))
+#define TWAIFD_TXB3_M  (TWAIFD_TXB3_V << TWAIFD_TXB3_S)
+#define TWAIFD_TXB3_V  0x00000001U
+#define TWAIFD_TXB3_S  10
+/** TWAIFD_TXB4 : R/W; bitpos: [11]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB4    (BIT(11))
+#define TWAIFD_TXB4_M  (TWAIFD_TXB4_V << TWAIFD_TXB4_S)
+#define TWAIFD_TXB4_V  0x00000001U
+#define TWAIFD_TXB4_S  11
+/** TWAIFD_TXB5 : R/W; bitpos: [12]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB5    (BIT(12))
+#define TWAIFD_TXB5_M  (TWAIFD_TXB5_V << TWAIFD_TXB5_S)
+#define TWAIFD_TXB5_V  0x00000001U
+#define TWAIFD_TXB5_S  12
+/** TWAIFD_TXB6 : R/W; bitpos: [13]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB6    (BIT(13))
+#define TWAIFD_TXB6_M  (TWAIFD_TXB6_V << TWAIFD_TXB6_S)
+#define TWAIFD_TXB6_V  0x00000001U
+#define TWAIFD_TXB6_S  13
+/** TWAIFD_TXB7 : R/W; bitpos: [14]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB7    (BIT(14))
+#define TWAIFD_TXB7_M  (TWAIFD_TXB7_V << TWAIFD_TXB7_S)
+#define TWAIFD_TXB7_V  0x00000001U
+#define TWAIFD_TXB7_S  14
+/** TWAIFD_TXB8 : R/W; bitpos: [15]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXB8    (BIT(15))
+#define TWAIFD_TXB8_M  (TWAIFD_TXB8_V << TWAIFD_TXB8_S)
+#define TWAIFD_TXB8_V  0x00000001U
+#define TWAIFD_TXB8_S  15
+/** TWAIFD_TXT_BUF_CTR : R/W; bitpos: [19:16]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TXT_BUF_CTR    0x0000000FU
+#define TWAIFD_TXT_BUF_CTR_M  (TWAIFD_TXT_BUF_CTR_V << TWAIFD_TXT_BUF_CTR_S)
+#define TWAIFD_TXT_BUF_CTR_V  0x0000000FU
+#define TWAIFD_TXT_BUF_CTR_S  16
+
+/** TWAIFD_ERR_CAP_RETR_CTR_ALC_REG register
+ *  TWAI FD error capture & retransmit counter & arbitration lost register
+ */
+#define TWAIFD_ERR_CAP_RETR_CTR_ALC_REG (DR_REG_TWAIFD_BASE + 0x160)
+/** TWAIFD_ERR_TYPE : RO; bitpos: [4:0]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_ERR_TYPE    0x0000001FU
+#define TWAIFD_ERR_TYPE_M  (TWAIFD_ERR_TYPE_V << TWAIFD_ERR_TYPE_S)
+#define TWAIFD_ERR_TYPE_V  0x0000001FU
+#define TWAIFD_ERR_TYPE_S  0
+/** TWAIFD_ERR_POS : RO; bitpos: [7:5]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_ERR_POS    0x00000007U
+#define TWAIFD_ERR_POS_M  (TWAIFD_ERR_POS_V << TWAIFD_ERR_POS_S)
+#define TWAIFD_ERR_POS_V  0x00000007U
+#define TWAIFD_ERR_POS_S  5
+/** TWAIFD_RETR_CTR : RO; bitpos: [11:8]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_RETR_CTR    0x0000000FU
+#define TWAIFD_RETR_CTR_M  (TWAIFD_RETR_CTR_V << TWAIFD_RETR_CTR_S)
+#define TWAIFD_RETR_CTR_V  0x0000000FU
+#define TWAIFD_RETR_CTR_S  8
+/** TWAIFD_ALC_BIT : RO; bitpos: [20:16]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_ALC_BIT    0x0000001FU
+#define TWAIFD_ALC_BIT_M  (TWAIFD_ALC_BIT_V << TWAIFD_ALC_BIT_S)
+#define TWAIFD_ALC_BIT_V  0x0000001FU
+#define TWAIFD_ALC_BIT_S  16
+/** TWAIFD_ALC_ID_FIELD : RO; bitpos: [23:21]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_ALC_ID_FIELD    0x00000007U
+#define TWAIFD_ALC_ID_FIELD_M  (TWAIFD_ALC_ID_FIELD_V << TWAIFD_ALC_ID_FIELD_S)
+#define TWAIFD_ALC_ID_FIELD_V  0x00000007U
+#define TWAIFD_ALC_ID_FIELD_S  21
+
+/** TWAIFD_TRV_DELAY_SSP_CFG_REG register
+ *  TWAI FD transmit delay & secondary sample point configuration register
+ */
+#define TWAIFD_TRV_DELAY_SSP_CFG_REG (DR_REG_TWAIFD_BASE + 0x164)
+/** TWAIFD_TRV_DELAY_VALUE : RO; bitpos: [6:0]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_TRV_DELAY_VALUE    0x0000007FU
+#define TWAIFD_TRV_DELAY_VALUE_M  (TWAIFD_TRV_DELAY_VALUE_V << TWAIFD_TRV_DELAY_VALUE_S)
+#define TWAIFD_TRV_DELAY_VALUE_V  0x0000007FU
+#define TWAIFD_TRV_DELAY_VALUE_S  0
+/** TWAIFD_SSP_OFFSET : R/W; bitpos: [23:16]; default: 10;
+ *  a\\
+ */
+#define TWAIFD_SSP_OFFSET    0x000000FFU
+#define TWAIFD_SSP_OFFSET_M  (TWAIFD_SSP_OFFSET_V << TWAIFD_SSP_OFFSET_S)
+#define TWAIFD_SSP_OFFSET_V  0x000000FFU
+#define TWAIFD_SSP_OFFSET_S  16
+/** TWAIFD_SSP_SRC : R/W; bitpos: [25:24]; default: 0;
+ *  a\\
+ */
+#define TWAIFD_SSP_SRC    0x00000003U
+#define TWAIFD_SSP_SRC_M  (TWAIFD_SSP_SRC_V << TWAIFD_SSP_SRC_S)
+#define TWAIFD_SSP_SRC_V  0x00000003U
+#define TWAIFD_SSP_SRC_S  24
+
+/** TWAIFD_RX_FRM_COUNTER_REG register
+ *  TWAI FD received frame counter register
+ */
+#define TWAIFD_RX_FRM_COUNTER_REG (DR_REG_TWAIFD_BASE + 0x180)
+/** TWAIFD_RX_COUNTER_VAL : RO; bitpos: [31:0]; default: 0;
+ *  Configures the received frame counters to enable bus traffic measurement.
+ */
+#define TWAIFD_RX_COUNTER_VAL    0xFFFFFFFFU
+#define TWAIFD_RX_COUNTER_VAL_M  (TWAIFD_RX_COUNTER_VAL_V << TWAIFD_RX_COUNTER_VAL_S)
+#define TWAIFD_RX_COUNTER_VAL_V  0xFFFFFFFFU
+#define TWAIFD_RX_COUNTER_VAL_S  0
+
+/** TWAIFD_TX_FRM_COUNTER_REG register
+ *  TWAI FD transmitted frame counter register
+ */
+#define TWAIFD_TX_FRM_COUNTER_REG (DR_REG_TWAIFD_BASE + 0x184)
+/** TWAIFD_TX_COUNTER_VAL : RO; bitpos: [31:0]; default: 0;
+ *  Configures the transcieved frame counters to enable bus traffic measurement.
+ */
+#define TWAIFD_TX_COUNTER_VAL    0xFFFFFFFFU
+#define TWAIFD_TX_COUNTER_VAL_M  (TWAIFD_TX_COUNTER_VAL_V << TWAIFD_TX_COUNTER_VAL_S)
+#define TWAIFD_TX_COUNTER_VAL_V  0xFFFFFFFFU
+#define TWAIFD_TX_COUNTER_VAL_S  0
+
+/** TWAIFD_CLK_REG register
+ *  TWAI FD clock configuration register
+ */
+#define TWAIFD_CLK_REG (DR_REG_TWAIFD_BASE + 0x18c)
+/** TWAIFD_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+ *  registers.
+ */
+#define TWAIFD_CLK_EN    (BIT(31))
+#define TWAIFD_CLK_EN_M  (TWAIFD_CLK_EN_V << TWAIFD_CLK_EN_S)
+#define TWAIFD_CLK_EN_V  0x00000001U
+#define TWAIFD_CLK_EN_S  31
+
+/** TWAIFD_DATE_REG register
+ *  TWAI FD version register
+ */
+#define TWAIFD_DATE_REG (DR_REG_TWAIFD_BASE + 0x190)
+/** TWAIFD_TWAIFD_DATE : R/W; bitpos: [31:0]; default: 35717712;
+ *  This is the version register.
+ */
+#define TWAIFD_TWAIFD_DATE    0xFFFFFFFFU
+#define TWAIFD_TWAIFD_DATE_M  (TWAIFD_TWAIFD_DATE_V << TWAIFD_TWAIFD_DATE_S)
+#define TWAIFD_TWAIFD_DATE_V  0xFFFFFFFFU
+#define TWAIFD_TWAIFD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/twaifd_struct.h b/components/soc/esp32p4/include/soc/twaifd_struct.h
new file mode 100644
index 0000000000..d0c0a3cd1e
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/twaifd_struct.h
@@ -0,0 +1,1548 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ID register */
+/** Type of device_id register
+ *  TWAI FD device id status register
+ */
+typedef union {
+    struct {
+        /** device_id : R/W; bitpos: [31:0]; default: 51965;
+         *  Represents whether CAN IP function is mapped correctly on its base address.
+         */
+        uint32_t device_id:32;
+    };
+    uint32_t val;
+} twaifd_device_id_reg_t;
+
+
+/** Group: Configuration register */
+/** Type of mode_setting register
+ *  TWAI FD mode setting register
+ */
+typedef union {
+    struct {
+        /** sw_reset : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to reset the TWAI FD controller.\\
+         *  0: invalid\\
+         *  1: reset.\\
+         */
+        uint32_t sw_reset:1;
+        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
+         *  bus monitor enable
+         */
+        uint32_t listen_only_mode:1;
+        /** self_test_mode : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable the self test mode.\\
+         *  0: disable\\
+         *  1: enable\\
+         */
+        uint32_t self_test_mode:1;
+        /** accept_filter_mode : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable the usage of acceptance filters.\\
+         *  0: disable\\
+         *  1: enable\\
+         */
+        uint32_t accept_filter_mode:1;
+        /** flexible_data_rate : R/W; bitpos: [4]; default: 1;
+         *  Configures whether or not to support flexible data rate.\\
+         *  0: not support\\
+         *  1: support\\
+         */
+        uint32_t flexible_data_rate:1;
+        /** rtr_frm_behavior : R/W; bitpos: [5]; default: 0;
+         *  time_triggered transmission mode
+         */
+        uint32_t rtr_frm_behavior:1;
+        /** rom : R/W; bitpos: [6]; default: 0;
+         *  a\\
+         */
+        uint32_t rom:1;
+        /** ack_behavior : R/W; bitpos: [7]; default: 0;
+         *  Configures the acknowledge behavior.\\
+         *  0: normal behavior.\\
+         *  1: acknowledge is not sent.\\
+         */
+        uint32_t ack_behavior:1;
+        /** test_mode : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable the triple sampling mode.\\
+         *  0: disable\\
+         *  1: enable\\
+         */
+        uint32_t test_mode:1;
+        /** rxbam : R/W; bitpos: [9]; default: 1;
+         *  a\\
+         */
+        uint32_t rxbam:1;
+        uint32_t reserved_10:6;
+        /** limit_retx_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable the limit of retransmission.\\
+         *  0: disable\\
+         *  1: enable\\
+         */
+        uint32_t limit_retx_en:1;
+        /** retx_thres : R/W; bitpos: [20:17]; default: 0;
+         *  Configures the threshold of retransmission attempts. \\
+         */
+        uint32_t retx_thres:4;
+        /** ilbp : R/W; bitpos: [21]; default: 0;
+         *  acknowledge forbidden mode
+         */
+        uint32_t ilbp:1;
+        /** ctrl_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable the twai FD controller.\\
+         *  0: disable\\
+         *  1: enable\\
+         */
+        uint32_t ctrl_en:1;
+        /** fd_type : R/W; bitpos: [23]; default: 0;
+         *  Configure the twai fd frame type.\\
+         *  0: ISO CAN FD\\
+         *  1: CAN FD 1.0\\
+         */
+        uint32_t fd_type:1;
+        /** pex : R/W; bitpos: [24]; default: 0;
+         *  protocol expection mode\\
+         */
+        uint32_t pex:1;
+        /** tbfbo : R/W; bitpos: [25]; default: 1;
+         *  a\\
+         */
+        uint32_t tbfbo:1;
+        /** fdrf : R/W; bitpos: [26]; default: 0;
+         *  a\\
+         */
+        uint32_t fdrf:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} twaifd_mode_setting_reg_t;
+
+/** Type of command register
+ *  TWAI FD command register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** rxrpmv : WO; bitpos: [1]; default: 0;
+         *  a\\
+         */
+        uint32_t rxrpmv:1;
+        /** release_rx_buf : WO; bitpos: [2]; default: 0;
+         *  Configures whether or not to delete all data from the receive buffer.\\
+         *  0: invalid\\
+         *  1: delete\\
+         */
+        uint32_t release_rx_buf:1;
+        /** clr_overrun_flg : WO; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear the data overrun flag.\\
+         *  0: invalid\\
+         *  1: clear\\
+         */
+        uint32_t clr_overrun_flg:1;
+        /** ercrst : WO; bitpos: [4]; default: 0;
+         *  a\\
+         */
+        uint32_t ercrst:1;
+        /** rxfcrst : WO; bitpos: [5]; default: 0;
+         *  a\\
+         */
+        uint32_t rxfcrst:1;
+        /** txfcrst : WO; bitpos: [6]; default: 0;
+         *  a\\
+         */
+        uint32_t txfcrst:1;
+        /** cpexs : WO; bitpos: [7]; default: 0;
+         *  a\\
+         */
+        uint32_t cpexs:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twaifd_command_reg_t;
+
+/** Type of bit_timing register
+ *  TWAI FD bit-timing  register
+ */
+typedef union {
+    struct {
+        /** prop : R/W; bitpos: [6:0]; default: 5;
+         *  Configures the propagation segment of nominal bit rate.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t prop:7;
+        /** ph1 : R/W; bitpos: [12:7]; default: 3;
+         *  Configures the phase 1 segment of nominal bit rate.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t ph1:6;
+        /** ph2 : R/W; bitpos: [18:13]; default: 5;
+         *  Configures the phase 2 segment of nominal bit rate.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t ph2:6;
+        /** brp : R/W; bitpos: [26:19]; default: 16;
+         *  Configures the baud-rate prescaler of nominal bit rate.\\
+         *  Measurement unit: cycle of core clock.
+         */
+        uint32_t brp:8;
+        /** sjw : R/W; bitpos: [31:27]; default: 2;
+         *  Represents the synchronization jump width in nominal bit time.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t sjw:5;
+    };
+    uint32_t val;
+} twaifd_bit_timing_reg_t;
+
+/** Type of bit_timeing_fd register
+ *  TWAI FD bit-timing of FD register
+ */
+typedef union {
+    struct {
+        /** prop_fd : R/W; bitpos: [5:0]; default: 3;
+         *  Configures the propagation segment of data bit rate.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t prop_fd:6;
+        uint32_t reserved_6:1;
+        /** ph1_fd : R/W; bitpos: [11:7]; default: 3;
+         *  Configures the phase 1 segment of data bit rate.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t ph1_fd:5;
+        uint32_t reserved_12:1;
+        /** ph2_fd : R/W; bitpos: [17:13]; default: 3;
+         *  Configures the phase 2 segment of data bit rate.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t ph2_fd:5;
+        uint32_t reserved_18:1;
+        /** brp_fd : R/W; bitpos: [26:19]; default: 4;
+         *  Configures the baud-rate prescaler of data bit rate.\\
+         *  Measurement unit: cycle of core clock.
+         */
+        uint32_t brp_fd:8;
+        /** sjw_fd : R/W; bitpos: [31:27]; default: 2;
+         *  Represents the synchronization jump width in data bit time.\\
+         *  Measurement unit: time quanta\\
+         */
+        uint32_t sjw_fd:5;
+    };
+    uint32_t val;
+} twaifd_bit_timeing_fd_reg_t;
+
+/** Type of tx_cfg register
+ *  TWAI FD TX buffer configuration register
+ */
+typedef union {
+    struct {
+        /** txt_1_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not allow transmitting frames from TX buffer1.\\
+         *  0: not allow\\
+         *  1: allow\\
+         */
+        uint32_t txt_1_allow:1;
+        /** txt_2_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether or not allow transmitting frames from TX buffer2.\\
+         *  0: not allow\\
+         *  1: allow\\
+         */
+        uint32_t txt_2_allow:1;
+        /** txt_1_commit : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not the frames from TX register are inserted into TX
+         *  buffer1.\\
+         *  0: not inserted\\
+         *  1: inserted\\
+         */
+        uint32_t txt_1_commit:1;
+        /** txt_2_commit : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not the frames from TX register are inserted into TX
+         *  buffer2.\\
+         *  0: not inserted\\
+         *  1: inserted\\
+         */
+        uint32_t txt_2_commit:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} twaifd_tx_cfg_reg_t;
+
+/** Type of trv_delay_ssp_cfg register
+ *  TWAI FD transmit delay & secondary sample point configuration register
+ */
+typedef union {
+    struct {
+        /** trv_delay_value : RO; bitpos: [6:0]; default: 0;
+         *  a\\
+         */
+        uint32_t trv_delay_value:7;
+        uint32_t reserved_7:9;
+        /** ssp_offset : R/W; bitpos: [23:16]; default: 10;
+         *  a\\
+         */
+        uint32_t ssp_offset:8;
+        /** ssp_src : R/W; bitpos: [25:24]; default: 0;
+         *  a\\
+         */
+        uint32_t ssp_src:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} twaifd_trv_delay_ssp_cfg_reg_t;
+
+
+/** Group: Status register */
+/** Type of status register
+ *  TWAI FD status register
+ */
+typedef union {
+    struct {
+        /** rx_buf_stat : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the receive buffer is empty.\\
+         *  0: empty\\
+         *  1: not empty\\
+         */
+        uint32_t rx_buf_stat:1;
+        /** data_overrun_flg : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not the receive buffer is full and the frame is
+         *  overrun(lost).\\
+         *  0: not overrun\\
+         *  1: overrun\\
+         */
+        uint32_t data_overrun_flg:1;
+        /** tx_buf_sat : RO; bitpos: [2]; default: 0;
+         *  Represents whether or not the transmit buffer is full.\\
+         *  0: not full\\
+         *  1: full\\
+         */
+        uint32_t tx_buf_sat:1;
+        /** err_frm_tx : RO; bitpos: [3]; default: 0;
+         *  Represents whether or not the error frame is being transmitted.\\
+         *  0: not being transmitted\\
+         *  1: being transmitted\\
+         */
+        uint32_t err_frm_tx:1;
+        /** rx_frm_stat : RO; bitpos: [4]; default: 0;
+         *  Represents whether or not the controller is receiving a frame.\\
+         *  0: not receiving\\
+         *  1: receiving\\
+         */
+        uint32_t rx_frm_stat:1;
+        /** tx_frm_stat : RO; bitpos: [5]; default: 0;
+         *  Represents whether or not the controller is transmitting a frame.\\
+         *  0: not transmitting\\
+         *  1: transmitting\\
+         */
+        uint32_t tx_frm_stat:1;
+        /** err_stat : RO; bitpos: [6]; default: 0;
+         *  Represents whether or not the error warning limit is reached.\\
+         *  0: not reached\\
+         *  1: reached\\
+         */
+        uint32_t err_stat:1;
+        /** bus_stat : RO; bitpos: [7]; default: 1;
+         *  Represents whether or not bus is active.\\
+         *  0: active\\
+         *  1: not active\\
+         */
+        uint32_t bus_stat:1;
+        /** pexs : RO; bitpos: [8]; default: 0;
+         *  a\\
+         */
+        uint32_t pexs:1;
+        /** reintegrating_wait : RO; bitpos: [9]; default: 0;
+         *  fsm is in reintegrating wait status
+         */
+        uint32_t reintegrating_wait:1;
+        uint32_t reserved_10:6;
+        /** stcnt : RO; bitpos: [16]; default: 0;
+         *  a\\
+         */
+        uint32_t stcnt:1;
+        /** strgs : RO; bitpos: [17]; default: 0;
+         *  a\\
+         */
+        uint32_t strgs:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} twaifd_status_reg_t;
+
+/** Type of rx_mem_info register
+ *  TWAI FD rx memory information register
+ */
+typedef union {
+    struct {
+        /** rx_buff_size_val : RO; bitpos: [12:0]; default: 0;
+         *  Represents the size of RX buffer.\\
+         */
+        uint32_t rx_buff_size_val:13;
+        uint32_t reserved_13:3;
+        /** rx_free_ctr : RO; bitpos: [28:16]; default: 0;
+         *  Represents the number of free words in RX buffer.\\
+         */
+        uint32_t rx_free_ctr:13;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_rx_mem_info_reg_t;
+
+/** Type of rx_pointers register
+ *  TWAI FD rx memory pointer information register
+ */
+typedef union {
+    struct {
+        /** rx_wpt_val : RO; bitpos: [11:0]; default: 0;
+         *  Represents the write pointer position in RX buffer.\\
+         */
+        uint32_t rx_wpt_val:12;
+        uint32_t reserved_12:4;
+        /** rx_rpt_val : RO; bitpos: [27:16]; default: 0;
+         *  Represents the read pointer position in RX buffer.\\
+         */
+        uint32_t rx_rpt_val:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} twaifd_rx_pointers_reg_t;
+
+/** Type of rx_status_setting register
+ *  TWAI FD tx status & setting register
+ */
+typedef union {
+    struct {
+        /** rx_empty : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the RX buffer is empty.\\
+         *  0: not empty\\
+         *  1: empty\\
+         */
+        uint32_t rx_empty:1;
+        /** rx_full : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not the RX buffer is full.\\
+         *  0: not full\\
+         *  1: full\\
+         */
+        uint32_t rx_full:1;
+        uint32_t reserved_2:2;
+        /** rx_frm_ctr : RO; bitpos: [14:4]; default: 0;
+         *  Represents the number of received frame in RX buffer.\\
+         */
+        uint32_t rx_frm_ctr:11;
+        uint32_t reserved_15:1;
+        /** rtsop : R/W; bitpos: [16]; default: 0;
+         *  a\\
+         */
+        uint32_t rtsop:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} twaifd_rx_status_setting_reg_t;
+
+/** Type of tx_stat register
+ *  TWAI FD TX buffer status register
+ */
+typedef union {
+    struct {
+        /** txt_1_empty : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the TX buffer1 is empty.\\
+         *  0: not empty\\
+         *  1: empty\\
+         */
+        uint32_t txt_1_empty:1;
+        /** txt_2_empty : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not the TX buffer2 is empty.\\
+         *  0: not empty\\
+         *  1: empty\\
+         */
+        uint32_t txt_2_empty:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twaifd_tx_stat_reg_t;
+
+/** Type of err_cap_retr_ctr_alc register
+ *  TWAI FD error capture & retransmit counter & arbitration lost register
+ */
+typedef union {
+    struct {
+        /** err_type : RO; bitpos: [4:0]; default: 0;
+         *  a\\
+         */
+        uint32_t err_type:5;
+        /** err_pos : RO; bitpos: [7:5]; default: 0;
+         *  a\\
+         */
+        uint32_t err_pos:3;
+        /** retr_ctr : RO; bitpos: [11:8]; default: 0;
+         *  a\\
+         */
+        uint32_t retr_ctr:4;
+        uint32_t reserved_12:4;
+        /** alc_bit : RO; bitpos: [20:16]; default: 0;
+         *  a\\
+         */
+        uint32_t alc_bit:5;
+        /** alc_id_field : RO; bitpos: [23:21]; default: 0;
+         *  a\\
+         */
+        uint32_t alc_id_field:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} twaifd_err_cap_retr_ctr_alc_reg_t;
+
+
+/** Group: interrupt register */
+/** Type of int_raw register
+ *  TWAI FD interrupt raw register
+ */
+typedef union {
+    struct {
+        /** rx_frm_suc_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of TWAIFD_RX_FRM_SUC_INT.
+         */
+        uint32_t rx_frm_suc_int_raw:1;
+        /** tx_frm_suc_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of TWAIFD_TX_FRM_SUC_INT.
+         */
+        uint32_t tx_frm_suc_int_raw:1;
+        /** err_warning_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of TWAIFD_ERR_WARNING_INT.
+         */
+        uint32_t err_warning_int_raw:1;
+        /** rx_data_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
+         */
+        uint32_t rx_data_overrun_int_raw:1;
+        uint32_t reserved_4:1;
+        /** fault_confinement_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+         */
+        uint32_t fault_confinement_chg_int_raw:1;
+        /** arb_lost_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of TWAIFD_ARB_LOST_INT.
+         */
+        uint32_t arb_lost_int_raw:1;
+        /** err_detected_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of TWAIFD_ERR_DETECTED_INT.
+         */
+        uint32_t err_detected_int_raw:1;
+        /** is_overload_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt status of TWAIFD_IS_OVERLOAD_INT.
+         */
+        uint32_t is_overload_int_raw:1;
+        /** rx_buf_full_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt status of TWAIFD_RX_BUF_FULL_INT.
+         */
+        uint32_t rx_buf_full_int_raw:1;
+        /** bit_rate_shift_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
+         */
+        uint32_t bit_rate_shift_int_raw:1;
+        /** rx_buf_not_empty_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
+         */
+        uint32_t rx_buf_not_empty_int_raw:1;
+        /** tx_buf_status_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
+         */
+        uint32_t tx_buf_status_chg_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} twaifd_int_raw_reg_t;
+
+/** Type of int_ena register
+ *  TWAI FD interrupt enable register
+ */
+typedef union {
+    struct {
+        /** rx_frm_suc_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable TWAIFD_RX_FRM_SUC_INT.
+         */
+        uint32_t rx_frm_suc_int_ena:1;
+        /** tx_frm_suc_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable TWAIFD_TX_FRM_SUC_INT.
+         */
+        uint32_t tx_frm_suc_int_ena:1;
+        /** err_warning_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable TWAIFD_ERR_WARNING_INT.
+         */
+        uint32_t err_warning_int_ena:1;
+        /** rx_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable TWAIFD_RX_DATA_OVERRUN_INT.
+         */
+        uint32_t rx_data_overrun_int_ena:1;
+        uint32_t reserved_4:1;
+        /** fault_confinement_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+         */
+        uint32_t fault_confinement_chg_int_ena:1;
+        /** arb_lost_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable TWAIFD_ARB_LOST_INT.
+         */
+        uint32_t arb_lost_int_ena:1;
+        /** err_detected_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable TWAIFD_ERR_DETECTED_INT.
+         */
+        uint32_t err_detected_int_ena:1;
+        /** is_overload_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable TWAIFD_IS_OVERLOAD_INT.
+         */
+        uint32_t is_overload_int_ena:1;
+        /** rx_buf_full_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable TWAIFD_RX_BUF_FULL_INT.
+         */
+        uint32_t rx_buf_full_int_ena:1;
+        /** bit_rate_shift_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable TWAIFD_BIT_RATE_SHIFT_INT.
+         */
+        uint32_t bit_rate_shift_int_ena:1;
+        /** rx_buf_not_empty_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable TWAIFD_RX_BUF_NOT_EMPTY_INT.
+         */
+        uint32_t rx_buf_not_empty_int_ena:1;
+        /** tx_buf_status_chg_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable TWAIFD_TX_BUF_STATUS_CHG_INT.
+         */
+        uint32_t tx_buf_status_chg_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} twaifd_int_ena_reg_t;
+
+/** Type of int_st register
+ *  TWAI FD interrupt status register
+ */
+typedef union {
+    struct {
+        /** rx_frm_suc_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of TWAIFD_RX_FRM_SUC_INT.
+         */
+        uint32_t rx_frm_suc_int_st:1;
+        /** tx_frm_suc_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of TWAIFD_TX_FRM_SUC_INT.
+         */
+        uint32_t tx_frm_suc_int_st:1;
+        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of TWAIFD_ERR_WARNING_INT.
+         */
+        uint32_t err_warning_int_st:1;
+        /** rx_data_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
+         */
+        uint32_t rx_data_overrun_int_st:1;
+        uint32_t reserved_4:1;
+        /** fault_confinement_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+         */
+        uint32_t fault_confinement_chg_int_st:1;
+        /** arb_lost_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of TWAIFD_ARB_LOST_INT.
+         */
+        uint32_t arb_lost_int_st:1;
+        /** err_detected_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of TWAIFD_ERR_DETECTED_INT.
+         */
+        uint32_t err_detected_int_st:1;
+        /** is_overload_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status of TWAIFD_IS_OVERLOAD_INT.
+         */
+        uint32_t is_overload_int_st:1;
+        /** rx_buf_full_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status of TWAIFD_RX_BUF_FULL_INT.
+         */
+        uint32_t rx_buf_full_int_st:1;
+        /** bit_rate_shift_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
+         */
+        uint32_t bit_rate_shift_int_st:1;
+        /** rx_buf_not_empty_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
+         */
+        uint32_t rx_buf_not_empty_int_st:1;
+        /** tx_buf_status_chg_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
+         */
+        uint32_t tx_buf_status_chg_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} twaifd_int_st_reg_t;
+
+/** Type of int_clr register
+ *  TWAI FD interrupt clear register
+ */
+typedef union {
+    struct {
+        /** rx_frm_suc_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear TWAIFD_RX_FRM_SUC_INT.
+         */
+        uint32_t rx_frm_suc_int_clr:1;
+        /** tx_frm_suc_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear TWAIFD_TX_FRM_SUC_INT.
+         */
+        uint32_t tx_frm_suc_int_clr:1;
+        /** err_warning_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear TWAIFD_ERR_WARNING_INT.
+         */
+        uint32_t err_warning_int_clr:1;
+        /** rx_data_overrun_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear TWAIFD_RX_DATA_OVERRUN_INT.
+         */
+        uint32_t rx_data_overrun_int_clr:1;
+        uint32_t reserved_4:1;
+        /** fault_confinement_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear TWAIFD_FAULT_CONFINEMENT_CHG_INT.
+         */
+        uint32_t fault_confinement_chg_int_clr:1;
+        /** arb_lost_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear TWAIFD_ARB_LOST_INT.
+         */
+        uint32_t arb_lost_int_clr:1;
+        /** err_detected_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear TWAIFD_ERR_DETECTED_INT.
+         */
+        uint32_t err_detected_int_clr:1;
+        /** is_overload_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear TWAIFD_IS_OVERLOAD_INT.
+         */
+        uint32_t is_overload_int_clr:1;
+        /** rx_buf_full_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear TWAIFD_RX_BUF_FULL_INT.
+         */
+        uint32_t rx_buf_full_int_clr:1;
+        /** bit_rate_shift_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear TWAIFD_BIT_RATE_SHIFT_INT.
+         */
+        uint32_t bit_rate_shift_int_clr:1;
+        /** rx_buf_not_empty_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear TWAIFD_RX_BUF_NOT_EMPTY_INT.
+         */
+        uint32_t rx_buf_not_empty_int_clr:1;
+        /** tx_buf_status_chg_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear TWAIFD_TX_BUF_STATUS_CHG_INT.
+         */
+        uint32_t tx_buf_status_chg_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} twaifd_int_clr_reg_t;
+
+
+/** Group: error confinement register */
+/** Type of err_th_stat register
+ *  TWAI FD error threshold and status register
+ */
+typedef union {
+    struct {
+        /** err_warning_thres : R/W; bitpos: [7:0]; default: 96;
+         *  Configures the error warning threshold.\\
+         */
+        uint32_t err_warning_thres:8;
+        /** err_passive_thres : R/W; bitpos: [15:8]; default: 128;
+         *  Configures the error passive threshold.\\
+         */
+        uint32_t err_passive_thres:8;
+        /** err_active : RO; bitpos: [16]; default: 1;
+         *  Represents the fault state of error active.\\
+         */
+        uint32_t err_active:1;
+        /** err_passive : RO; bitpos: [17]; default: 0;
+         *  Represents the fault state of error passive.\\
+         */
+        uint32_t err_passive:1;
+        /** bus_off : RO; bitpos: [18]; default: 0;
+         *  Represents the fault state of bus off.\\
+         */
+        uint32_t bus_off:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} twaifd_err_th_stat_reg_t;
+
+/** Type of error_counters register
+ *  TWAI FD error counters status register
+ */
+typedef union {
+    struct {
+        /** rxc_val : RO; bitpos: [15:0]; default: 0;
+         *  Represents the receiver error counter value.\\
+         */
+        uint32_t rxc_val:16;
+        /** txc_val : RO; bitpos: [31:16]; default: 0;
+         *  Represents the transmitter error counter value.\\
+         */
+        uint32_t txc_val:16;
+    };
+    uint32_t val;
+} twaifd_error_counters_reg_t;
+
+/** Type of error_counters_sp register
+ *  TWAI FD special error counters status register
+ */
+typedef union {
+    struct {
+        /** err_fd_val : RO; bitpos: [15:0]; default: 0;
+         *  Represents the number of error in the data bit time.\\
+         */
+        uint32_t err_fd_val:16;
+        /** err_norm_val : RO; bitpos: [31:16]; default: 0;
+         *  Represents the number of error in the nominal bit time.\\
+         */
+        uint32_t err_norm_val:16;
+    };
+    uint32_t val;
+} twaifd_error_counters_sp_reg_t;
+
+/** Type of ctr_pres register
+ *  TWAI FD error counters pre-define configuration register
+ */
+typedef union {
+    struct {
+        /** ctr_pres_val : WO; bitpos: [8:0]; default: 0;
+         *  Configures the pre-defined value to set the error counter.\\
+         */
+        uint32_t ctr_pres_val:9;
+        /** ptx : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to set the receiver error counter into the value of
+         *  pre-defined value.\\
+         *  0: invalid\\
+         *  1: set\\
+         */
+        uint32_t ptx:1;
+        /** prx : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to set the transmitter error counter into the value of
+         *  pre-defined value.\\
+         *  0: invalid\\
+         *  1: set\\
+         */
+        uint32_t prx:1;
+        /** enorm : WO; bitpos: [11]; default: 0;
+         *  Configures whether or not to erase the error counter of nominal bit time.\\
+         *  0: invalid\\
+         *  1: erase\\
+         */
+        uint32_t enorm:1;
+        /** efd : WO; bitpos: [12]; default: 0;
+         *  Configures whether or not to erase the error counter of data bit time.\\
+         *  0: invalid\\
+         *  1: erase\\
+         */
+        uint32_t efd:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} twaifd_ctr_pres_reg_t;
+
+
+/** Group: receiver register */
+/** Type of rx_data register
+ *  TWAI FD received data register
+ */
+typedef union {
+    struct {
+        /** rx_data : RO; bitpos: [31:0]; default: 0;
+         *  Data received.
+         */
+        uint32_t rx_data:32;
+    };
+    uint32_t val;
+} twaifd_rx_data_reg_t;
+
+
+/** Group: filter register */
+/** Type of filter_a_mask register
+ *  TWAI FD filter A mask value register
+ */
+typedef union {
+    struct {
+        /** bit_mask_a : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit masked value.
+         */
+        uint32_t bit_mask_a:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_a_mask_reg_t;
+
+/** Type of filter_a_val register
+ *  TWAI FD filter A bit value register
+ */
+typedef union {
+    struct {
+        /** bit_val_a : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit value.
+         */
+        uint32_t bit_val_a:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_a_val_reg_t;
+
+/** Type of filter_b_mask register
+ *  TWAI FD filter B mask value register
+ */
+typedef union {
+    struct {
+        /** bit_mask_b : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit masked value.
+         */
+        uint32_t bit_mask_b:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_b_mask_reg_t;
+
+/** Type of filter_b_val register
+ *  TWAI FD filter B bit value register
+ */
+typedef union {
+    struct {
+        /** bit_val_b : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit value.
+         */
+        uint32_t bit_val_b:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_b_val_reg_t;
+
+/** Type of filter_c_mask register
+ *  TWAI FD filter C mask value register
+ */
+typedef union {
+    struct {
+        /** bit_mask_c : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit masked value.
+         */
+        uint32_t bit_mask_c:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_c_mask_reg_t;
+
+/** Type of filter_c_val register
+ *  TWAI FD filter C bit value register
+ */
+typedef union {
+    struct {
+        /** bit_val_c : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit value.
+         */
+        uint32_t bit_val_c:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_c_val_reg_t;
+
+/** Type of filter_ran_low register
+ *  TWAI FD filter range low value register
+ */
+typedef union {
+    struct {
+        /** bit_ran_low : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit masked value.
+         */
+        uint32_t bit_ran_low:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_ran_low_reg_t;
+
+/** Type of filter_ran_high register
+ *  TWAI FD filter range high value register
+ */
+typedef union {
+    struct {
+        /** bit_ran_high : R/W; bitpos: [28:0]; default: 0;
+         *  filter A bit value.
+         */
+        uint32_t bit_ran_high:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_filter_ran_high_reg_t;
+
+/** Type of filter_control register
+ *  TWAI FD filter control register
+ */
+typedef union {
+    struct {
+        /** fanb : R/W; bitpos: [0]; default: 1;
+         *  filter A with nominal and base mode.
+         */
+        uint32_t fanb:1;
+        /** fane : R/W; bitpos: [1]; default: 1;
+         *  filter A with nominal and extended mode.
+         */
+        uint32_t fane:1;
+        /** fafb : R/W; bitpos: [2]; default: 1;
+         *  filter A with FD and base mode.
+         */
+        uint32_t fafb:1;
+        /** fafe : R/W; bitpos: [3]; default: 1;
+         *  filter A with FD and extended mode.
+         */
+        uint32_t fafe:1;
+        /** fbnb : R/W; bitpos: [4]; default: 0;
+         *  filter B with nominal and base mode.
+         */
+        uint32_t fbnb:1;
+        /** fbne : R/W; bitpos: [5]; default: 0;
+         *  filter B with nominal and extended mode.
+         */
+        uint32_t fbne:1;
+        /** fbfb : R/W; bitpos: [6]; default: 0;
+         *  filter B with FD and base mode.
+         */
+        uint32_t fbfb:1;
+        /** fbfe : R/W; bitpos: [7]; default: 0;
+         *  filter B with FD and extended mode.
+         */
+        uint32_t fbfe:1;
+        /** fcnb : R/W; bitpos: [8]; default: 0;
+         *  filter C with nominal and base mode.
+         */
+        uint32_t fcnb:1;
+        /** fcne : R/W; bitpos: [9]; default: 0;
+         *  filter C with nominal and extended mode.
+         */
+        uint32_t fcne:1;
+        /** fcfb : R/W; bitpos: [10]; default: 0;
+         *  filter C with FD and base mode.
+         */
+        uint32_t fcfb:1;
+        /** fcfe : R/W; bitpos: [11]; default: 0;
+         *  filter C with FD and extended mode.
+         */
+        uint32_t fcfe:1;
+        /** frnb : R/W; bitpos: [12]; default: 0;
+         *  filter range with nominal and base mode.
+         */
+        uint32_t frnb:1;
+        /** frne : R/W; bitpos: [13]; default: 0;
+         *  filter range with nominal and extended mode.
+         */
+        uint32_t frne:1;
+        /** frfb : R/W; bitpos: [14]; default: 0;
+         *  filter range with FD and base mode.
+         */
+        uint32_t frfb:1;
+        /** frfe : R/W; bitpos: [15]; default: 0;
+         *  filter range with FD and extended mode.
+         */
+        uint32_t frfe:1;
+        /** sfa : RO; bitpos: [16]; default: 0;
+         *  filter A status
+         */
+        uint32_t sfa:1;
+        /** sfb : RO; bitpos: [17]; default: 0;
+         *  filter B status
+         */
+        uint32_t sfb:1;
+        /** sfc : RO; bitpos: [18]; default: 0;
+         *  filter C status
+         */
+        uint32_t sfc:1;
+        /** sfr : RO; bitpos: [19]; default: 0;
+         *  filter range status
+         */
+        uint32_t sfr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} twaifd_filter_control_reg_t;
+
+
+/** Group: transmitter register */
+/** Type of tx_data_0 register
+ *  TWAI FD transmit data register 0
+ */
+typedef union {
+    struct {
+        /** dlc_tx : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the brs to be transmitted.
+         */
+        uint32_t dlc_tx:4;
+        uint32_t reserved_4:1;
+        /** rtr_tx : R/W; bitpos: [5]; default: 0;
+         *  Configures the rtr bit to be transmitted.
+         */
+        uint32_t rtr_tx:1;
+        /** id_type_tx : R/W; bitpos: [6]; default: 0;
+         *  Configures the frame type to be transmitted.
+         */
+        uint32_t id_type_tx:1;
+        /** fr_type_tx : R/W; bitpos: [7]; default: 0;
+         *  Configures the fd type to be transmitted.
+         */
+        uint32_t fr_type_tx:1;
+        /** tbf_tx : R/W; bitpos: [8]; default: 0;
+         *  Configures the tbf bit to be transmitted.
+         */
+        uint32_t tbf_tx:1;
+        /** brs_tx : R/W; bitpos: [9]; default: 0;
+         *  Configures the brs bit to be transmitted.
+         */
+        uint32_t brs_tx:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} twaifd_tx_data_0_reg_t;
+
+/** Type of tx_data_1 register
+ *  TWAI FD transmit data register 1
+ */
+typedef union {
+    struct {
+        /** ts_val_u_tx : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper timestamp to be transmitted
+         */
+        uint32_t ts_val_u_tx:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_1_reg_t;
+
+/** Type of tx_data_2 register
+ *  TWAI FD transmit data register 2
+ */
+typedef union {
+    struct {
+        /** ts_val_l_tx : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the lower timestamp to be transmitted
+         */
+        uint32_t ts_val_l_tx:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_2_reg_t;
+
+/** Type of tx_data_3 register
+ *  TWAI FD transmit data register 3
+ */
+typedef union {
+    struct {
+        /** id_ext_tx : R/W; bitpos: [17:0]; default: 0;
+         *  Configures the base ID to be transmitted
+         */
+        uint32_t id_ext_tx:18;
+        /** id_base_tx : R/W; bitpos: [28:18]; default: 0;
+         *  Configures the extended ID to be transmitted
+         */
+        uint32_t id_base_tx:11;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} twaifd_tx_data_3_reg_t;
+
+/** Type of tx_data_4 register
+ *  TWAI FD transmit data register 4
+ */
+typedef union {
+    struct {
+        /** tx_data0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th word to be transmitted
+         */
+        uint32_t tx_data0:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_4_reg_t;
+
+/** Type of tx_data_5 register
+ *  TWAI FD transmit data register 5
+ */
+typedef union {
+    struct {
+        /** tx_data1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1th word to be transmitted
+         */
+        uint32_t tx_data1:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_5_reg_t;
+
+/** Type of tx_data_6 register
+ *  TWAI FD transmit data register 6
+ */
+typedef union {
+    struct {
+        /** tx_data2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2th word to be transmitted
+         */
+        uint32_t tx_data2:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_6_reg_t;
+
+/** Type of tx_data_7 register
+ *  TWAI FD transmit data register 7
+ */
+typedef union {
+    struct {
+        /** tx_data3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 3th word to be transmitted
+         */
+        uint32_t tx_data3:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_7_reg_t;
+
+/** Type of tx_data_8 register
+ *  TWAI FD transmit data register 8
+ */
+typedef union {
+    struct {
+        /** tx_data4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 4th word to be transmitted
+         */
+        uint32_t tx_data4:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_8_reg_t;
+
+/** Type of tx_data_9 register
+ *  TWAI FD transmit data register 9
+ */
+typedef union {
+    struct {
+        /** tx_data5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 5th word to be transmitted
+         */
+        uint32_t tx_data5:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_9_reg_t;
+
+/** Type of tx_data_10 register
+ *  TWAI FD transmit data register 10
+ */
+typedef union {
+    struct {
+        /** tx_data6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 6th word to be transmitted
+         */
+        uint32_t tx_data6:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_10_reg_t;
+
+/** Type of tx_data_11 register
+ *  TWAI FD transmit data register 11
+ */
+typedef union {
+    struct {
+        /** tx_data7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 7th word to be transmitted
+         */
+        uint32_t tx_data7:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_11_reg_t;
+
+/** Type of tx_data_12 register
+ *  TWAI FD transmit data register 12
+ */
+typedef union {
+    struct {
+        /** tx_data8 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 8th word to be transmitted
+         */
+        uint32_t tx_data8:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_12_reg_t;
+
+/** Type of tx_data_13 register
+ *  TWAI FD transmit data register 13
+ */
+typedef union {
+    struct {
+        /** tx_data9 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 9th word to be transmitted
+         */
+        uint32_t tx_data9:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_13_reg_t;
+
+/** Type of tx_data_14 register
+ *  TWAI FD transmit data register 14
+ */
+typedef union {
+    struct {
+        /** tx_data10 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 10th word to be transmitted
+         */
+        uint32_t tx_data10:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_14_reg_t;
+
+/** Type of tx_data_15 register
+ *  TWAI FD transmit data register 15
+ */
+typedef union {
+    struct {
+        /** tx_data11 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 11th word to be transmitted
+         */
+        uint32_t tx_data11:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_15_reg_t;
+
+/** Type of tx_data_16 register
+ *  TWAI FD transmit data register 16
+ */
+typedef union {
+    struct {
+        /** tx_data12 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 12th word to be transmitted
+         */
+        uint32_t tx_data12:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_16_reg_t;
+
+/** Type of tx_data_17 register
+ *  TWAI FD transmit data register 17
+ */
+typedef union {
+    struct {
+        /** tx_data13 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 13th word to be transmitted
+         */
+        uint32_t tx_data13:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_17_reg_t;
+
+/** Type of tx_data_18 register
+ *  TWAI FD transmit data register 18
+ */
+typedef union {
+    struct {
+        /** tx_data14 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 14th word to be transmitted
+         */
+        uint32_t tx_data14:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_18_reg_t;
+
+/** Type of tx_data_19 register
+ *  TWAI FD transmit data register 19
+ */
+typedef union {
+    struct {
+        /** tx_data15 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 15th word to be transmitted
+         */
+        uint32_t tx_data15:32;
+    };
+    uint32_t val;
+} twaifd_tx_data_19_reg_t;
+
+/** Type of tx_cammand_info register
+ *  TWAI FD TXT buffer command & information register
+ */
+typedef union {
+    struct {
+        /** txtb_sw_set_ety : R/W; bitpos: [0]; default: 0;
+         *  a\\
+         */
+        uint32_t txtb_sw_set_ety:1;
+        /** txtb_sw_set_rdy : R/W; bitpos: [1]; default: 0;
+         *  a\\
+         */
+        uint32_t txtb_sw_set_rdy:1;
+        /** txtb_sw_set_abt : R/W; bitpos: [2]; default: 0;
+         *  a\\
+         */
+        uint32_t txtb_sw_set_abt:1;
+        uint32_t reserved_3:5;
+        /** txb1 : R/W; bitpos: [8]; default: 0;
+         *  a\\
+         */
+        uint32_t txb1:1;
+        /** txb2 : R/W; bitpos: [9]; default: 0;
+         *  a\\
+         */
+        uint32_t txb2:1;
+        /** txb3 : R/W; bitpos: [10]; default: 0;
+         *  a\\
+         */
+        uint32_t txb3:1;
+        /** txb4 : R/W; bitpos: [11]; default: 0;
+         *  a\\
+         */
+        uint32_t txb4:1;
+        /** txb5 : R/W; bitpos: [12]; default: 0;
+         *  a\\
+         */
+        uint32_t txb5:1;
+        /** txb6 : R/W; bitpos: [13]; default: 0;
+         *  a\\
+         */
+        uint32_t txb6:1;
+        /** txb7 : R/W; bitpos: [14]; default: 0;
+         *  a\\
+         */
+        uint32_t txb7:1;
+        /** txb8 : R/W; bitpos: [15]; default: 0;
+         *  a\\
+         */
+        uint32_t txb8:1;
+        /** txt_buf_ctr : R/W; bitpos: [19:16]; default: 0;
+         *  a\\
+         */
+        uint32_t txt_buf_ctr:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} twaifd_tx_cammand_info_reg_t;
+
+
+/** Group: controller register */
+/** Type of rx_frm_counter register
+ *  TWAI FD received frame counter register
+ */
+typedef union {
+    struct {
+        /** rx_counter_val : RO; bitpos: [31:0]; default: 0;
+         *  Configures the received frame counters to enable bus traffic measurement.
+         */
+        uint32_t rx_counter_val:32;
+    };
+    uint32_t val;
+} twaifd_rx_frm_counter_reg_t;
+
+/** Type of tx_frm_counter register
+ *  TWAI FD transmitted frame counter register
+ */
+typedef union {
+    struct {
+        /** tx_counter_val : RO; bitpos: [31:0]; default: 0;
+         *  Configures the transcieved frame counters to enable bus traffic measurement.
+         */
+        uint32_t tx_counter_val:32;
+    };
+    uint32_t val;
+} twaifd_tx_frm_counter_reg_t;
+
+
+/** Group: clock register */
+/** Type of clk register
+ *  TWAI FD clock configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} twaifd_clk_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  TWAI FD version register
+ */
+typedef union {
+    struct {
+        /** twaifd_date : R/W; bitpos: [31:0]; default: 35717712;
+         *  This is the version register.
+         */
+        uint32_t twaifd_date:32;
+    };
+    uint32_t val;
+} twaifd_date_reg_t;
+
+
+typedef struct {
+    volatile twaifd_device_id_reg_t device_id;
+    volatile twaifd_mode_setting_reg_t mode_setting;
+    volatile twaifd_command_reg_t command;
+    volatile twaifd_status_reg_t status;
+    volatile twaifd_int_raw_reg_t int_raw;
+    volatile twaifd_int_ena_reg_t int_ena;
+    volatile twaifd_int_st_reg_t int_st;
+    volatile twaifd_int_clr_reg_t int_clr;
+    volatile twaifd_bit_timing_reg_t bit_timing;
+    volatile twaifd_bit_timeing_fd_reg_t bit_timeing_fd;
+    volatile twaifd_err_th_stat_reg_t err_th_stat;
+    volatile twaifd_error_counters_reg_t error_counters;
+    volatile twaifd_error_counters_sp_reg_t error_counters_sp;
+    volatile twaifd_ctr_pres_reg_t ctr_pres;
+    volatile twaifd_rx_mem_info_reg_t rx_mem_info;
+    volatile twaifd_rx_pointers_reg_t rx_pointers;
+    volatile twaifd_rx_status_setting_reg_t rx_status_setting;
+    volatile twaifd_rx_data_reg_t rx_data;
+    uint32_t reserved_048[6];
+    volatile twaifd_filter_a_mask_reg_t filter_a_mask;
+    volatile twaifd_filter_a_val_reg_t filter_a_val;
+    volatile twaifd_filter_b_mask_reg_t filter_b_mask;
+    volatile twaifd_filter_b_val_reg_t filter_b_val;
+    volatile twaifd_filter_c_mask_reg_t filter_c_mask;
+    volatile twaifd_filter_c_val_reg_t filter_c_val;
+    volatile twaifd_filter_ran_low_reg_t filter_ran_low;
+    volatile twaifd_filter_ran_high_reg_t filter_ran_high;
+    volatile twaifd_filter_control_reg_t filter_control;
+    uint32_t reserved_084[4];
+    volatile twaifd_tx_stat_reg_t tx_stat;
+    volatile twaifd_tx_cfg_reg_t tx_cfg;
+    volatile twaifd_tx_data_0_reg_t tx_data_0;
+    volatile twaifd_tx_data_1_reg_t tx_data_1;
+    volatile twaifd_tx_data_2_reg_t tx_data_2;
+    volatile twaifd_tx_data_3_reg_t tx_data_3;
+    volatile twaifd_tx_data_4_reg_t tx_data_4;
+    volatile twaifd_tx_data_5_reg_t tx_data_5;
+    volatile twaifd_tx_data_6_reg_t tx_data_6;
+    volatile twaifd_tx_data_7_reg_t tx_data_7;
+    volatile twaifd_tx_data_8_reg_t tx_data_8;
+    volatile twaifd_tx_data_9_reg_t tx_data_9;
+    volatile twaifd_tx_data_10_reg_t tx_data_10;
+    volatile twaifd_tx_data_11_reg_t tx_data_11;
+    volatile twaifd_tx_data_12_reg_t tx_data_12;
+    volatile twaifd_tx_data_13_reg_t tx_data_13;
+    volatile twaifd_tx_data_14_reg_t tx_data_14;
+    volatile twaifd_tx_data_15_reg_t tx_data_15;
+    volatile twaifd_tx_data_16_reg_t tx_data_16;
+    volatile twaifd_tx_data_17_reg_t tx_data_17;
+    volatile twaifd_tx_data_18_reg_t tx_data_18;
+    volatile twaifd_tx_data_19_reg_t tx_data_19;
+    uint32_t reserved_0ec[24];
+    volatile twaifd_tx_cammand_info_reg_t tx_cammand_info;
+    uint32_t reserved_150[4];
+    volatile twaifd_err_cap_retr_ctr_alc_reg_t err_cap_retr_ctr_alc;
+    volatile twaifd_trv_delay_ssp_cfg_reg_t trv_delay_ssp_cfg;
+    uint32_t reserved_168[6];
+    volatile twaifd_rx_frm_counter_reg_t rx_frm_counter;
+    volatile twaifd_tx_frm_counter_reg_t tx_frm_counter;
+    uint32_t reserved_188;
+    volatile twaifd_clk_reg_t clk;
+    volatile twaifd_date_reg_t date;
+} twaifd_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(twaifd_dev_t) == 0x194, "Invalid size of twaifd_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/uart_channel.h b/components/soc/esp32p4/include/soc/uart_channel.h
new file mode 100644
index 0000000000..9d9fb454fd
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/uart_channel.h
@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6.
+
+#pragma once
+
+//UART channels
+#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  16
+#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  17
+
+#define UART_TXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
+#define UART_RXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
diff --git a/components/soc/esp32p4/include/soc/uart_pins.h b/components/soc/esp32p4/include/soc/uart_pins.h
new file mode 100644
index 0000000000..7164eeae56
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/uart_pins.h
@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/io_mux_reg.h"
+
+/* Specify the number of pins for UART */
+#define SOC_UART_PINS_COUNT  (4)
+
+/* Specify the GPIO pin number for each UART signal in the IOMUX */
+#define U0RXD_GPIO_NUM 17
+#define U0TXD_GPIO_NUM 16
+#define U0RTS_GPIO_NUM (-1)
+#define U0CTS_GPIO_NUM (-1)
+
+#define U1RXD_GPIO_NUM (-1)
+#define U1TXD_GPIO_NUM (-1)
+#define U1RTS_GPIO_NUM (-1)
+#define U1CTS_GPIO_NUM (-1)
+
+/* The following defines are necessary for reconfiguring the UART
+ * to use IOMUX, at runtime. */
+#define U0TXD_MUX_FUNC  (FUNC_GPIO37_UART0_TXD_PAD)
+#define U0RXD_MUX_FUNC  (FUNC_GPIO38_UART0_RXD_PAD)
+/* No func for the following pins, they shall not be used */
+#define U0RTS_MUX_FUNC  (-1)
+#define U0CTS_MUX_FUNC  (-1)
+/* Same goes for UART1 */
+#define U1TXD_MUX_FUNC  (-1)
+#define U1RXD_MUX_FUNC  (-1)
+#define U1RTS_MUX_FUNC  (-1)
+#define U1CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32p4/include/soc/uart_struct.h b/components/soc/esp32p4/include/soc/uart_struct.h
new file mode 100644
index 0000000000..735f4ad96a
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/uart_struct.h
@@ -0,0 +1,1271 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enble bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_char : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_char:8;
+        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_char:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t at_cmd_char:8;
+        /** char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maxinum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36720720;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;
+    volatile uart_negpulse_reg_t negpulse;
+    volatile uart_lowpulse_reg_t lowpulse;
+    volatile uart_highpulse_reg_t highpulse;
+    volatile uart_rxd_cnt_reg_t rxd_cnt;
+    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/uhci_reg.h b/components/soc/esp32p4/include/soc/uhci_reg.h
new file mode 100644
index 0000000000..84a244c530
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/uhci_reg.h
@@ -0,0 +1,966 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UHCI_CONF0_REG register
+ *  UHCI Configuration Register0
+ */
+#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0)
+/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0 to this bit to reset decode state machine.
+ */
+#define UHCI_TX_RST    (BIT(0))
+#define UHCI_TX_RST_M  (UHCI_TX_RST_V << UHCI_TX_RST_S)
+#define UHCI_TX_RST_V  0x00000001U
+#define UHCI_TX_RST_S  0
+/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0 to this bit to reset encode state machine.
+ */
+#define UHCI_RX_RST    (BIT(1))
+#define UHCI_RX_RST_M  (UHCI_RX_RST_V << UHCI_RX_RST_S)
+#define UHCI_RX_RST_V  0x00000001U
+#define UHCI_RX_RST_S  1
+/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  Select which uart to connect with GDMA.
+ */
+#define UHCI_UART_SEL    0x00000007U
+#define UHCI_UART_SEL_M  (UHCI_UART_SEL_V << UHCI_UART_SEL_S)
+#define UHCI_UART_SEL_V  0x00000007U
+#define UHCI_UART_SEL_S  2
+/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to separate the data frame using a special char.
+ */
+#define UHCI_SEPER_EN    (BIT(5))
+#define UHCI_SEPER_EN_M  (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S)
+#define UHCI_SEPER_EN_V  0x00000001U
+#define UHCI_SEPER_EN_S  5
+/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1;
+ *  Set this bit to encode the data packet with a formatting header.
+ */
+#define UHCI_HEAD_EN    (BIT(6))
+#define UHCI_HEAD_EN_M  (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S)
+#define UHCI_HEAD_EN_V  0x00000001U
+#define UHCI_HEAD_EN_S  6
+/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1;
+ *  Set this bit to enable UHCI to receive the 16 bit CRC.
+ */
+#define UHCI_CRC_REC_EN    (BIT(7))
+#define UHCI_CRC_REC_EN_M  (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S)
+#define UHCI_CRC_REC_EN_V  0x00000001U
+#define UHCI_CRC_REC_EN_S  7
+/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0;
+ *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
+ *  been in idle state.
+ */
+#define UHCI_UART_IDLE_EOF_EN    (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_M  (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S)
+#define UHCI_UART_IDLE_EOF_EN_V  0x00000001U
+#define UHCI_UART_IDLE_EOF_EN_S  8
+/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1;
+ *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
+ *  receiving byte count has reached the specified value. The value is payload length
+ *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+ *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
+ *  receiving payload data is end when 0xc0 is received.
+ */
+#define UHCI_LEN_EOF_EN    (BIT(9))
+#define UHCI_LEN_EOF_EN_M  (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S)
+#define UHCI_LEN_EOF_EN_V  0x00000001U
+#define UHCI_LEN_EOF_EN_S  9
+/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1;
+ *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
+ *  end of the payload.
+ */
+#define UHCI_ENCODE_CRC_EN    (BIT(10))
+#define UHCI_ENCODE_CRC_EN_M  (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S)
+#define UHCI_ENCODE_CRC_EN_V  0x00000001U
+#define UHCI_ENCODE_CRC_EN_S  10
+/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+ *  registers.
+ */
+#define UHCI_CLK_EN    (BIT(11))
+#define UHCI_CLK_EN_M  (UHCI_CLK_EN_V << UHCI_CLK_EN_S)
+#define UHCI_CLK_EN_V  0x00000001U
+#define UHCI_CLK_EN_S  11
+/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0;
+ *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
+ *  received by UART.
+ */
+#define UHCI_UART_RX_BRK_EOF_EN    (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_M  (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S)
+#define UHCI_UART_RX_BRK_EOF_EN_V  0x00000001U
+#define UHCI_UART_RX_BRK_EOF_EN_S  12
+
+/** UHCI_INT_RAW_REG register
+ *  UHCI Interrupt Raw Register
+ */
+#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4)
+/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
+ *  delimiter is sent successfully.
+ */
+#define UHCI_RX_START_INT_RAW    (BIT(0))
+#define UHCI_RX_START_INT_RAW_M  (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S)
+#define UHCI_RX_START_INT_RAW_V  0x00000001U
+#define UHCI_RX_START_INT_RAW_S  0
+/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
+ *  DMA detects delimiter.
+ */
+#define UHCI_TX_START_INT_RAW    (BIT(1))
+#define UHCI_TX_START_INT_RAW_M  (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S)
+#define UHCI_TX_START_INT_RAW_V  0x00000001U
+#define UHCI_TX_START_INT_RAW_S  1
+/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
+ *  the required time of DMA receiving data  exceeds the configuration value.
+ */
+#define UHCI_RX_HUNG_INT_RAW    (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M  (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S)
+#define UHCI_RX_HUNG_INT_RAW_V  0x00000001U
+#define UHCI_RX_HUNG_INT_RAW_S  2
+/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
+ *  the required time of DMA reading RAM data  exceeds the configuration value.
+ */
+#define UHCI_TX_HUNG_INT_RAW    (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M  (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S)
+#define UHCI_TX_HUNG_INT_RAW_V  0x00000001U
+#define UHCI_TX_HUNG_INT_RAW_S  3
+/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
+ *  when UHCI sends short packet successfully with single_send mode.
+ */
+#define UHCI_SEND_S_REG_Q_INT_RAW    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_RAW_M  (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S)
+#define UHCI_SEND_S_REG_Q_INT_RAW_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_RAW_S  4
+/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
+ *  when UHCI sends short packet successfully with always_send mode.
+ */
+#define UHCI_SEND_A_REG_Q_INT_RAW    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_RAW_M  (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S)
+#define UHCI_SEND_A_REG_Q_INT_RAW_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_RAW_S  5
+/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
+ *  there are errors in EOF.
+ */
+#define UHCI_OUT_EOF_INT_RAW    (BIT(6))
+#define UHCI_OUT_EOF_INT_RAW_M  (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S)
+#define UHCI_OUT_EOF_INT_RAW_V  0x00000001U
+#define UHCI_OUT_EOF_INT_RAW_S  6
+/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0;
+ *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
+ *  UHCI_APP_CTRL0_IN_SET is set to 1.
+ */
+#define UHCI_APP_CTRL0_INT_RAW    (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_M  (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S)
+#define UHCI_APP_CTRL0_INT_RAW_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_RAW_S  7
+/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0;
+ *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
+ *  UHCI_APP_CTRL1_IN_SET is set to 1.
+ */
+#define UHCI_APP_CTRL1_INT_RAW    (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_M  (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S)
+#define UHCI_APP_CTRL1_INT_RAW_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_RAW_S  8
+
+/** UHCI_INT_ST_REG register
+ *  UHCI Interrupt Status Register
+ */
+#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8)
+/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Indicates the interrupt status of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_ST    (BIT(0))
+#define UHCI_RX_START_INT_ST_M  (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S)
+#define UHCI_RX_START_INT_ST_V  0x00000001U
+#define UHCI_RX_START_INT_ST_S  0
+/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Indicates the interrupt status of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_ST    (BIT(1))
+#define UHCI_TX_START_INT_ST_M  (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S)
+#define UHCI_TX_START_INT_ST_V  0x00000001U
+#define UHCI_TX_START_INT_ST_S  1
+/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_ST    (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M  (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S)
+#define UHCI_RX_HUNG_INT_ST_V  0x00000001U
+#define UHCI_RX_HUNG_INT_ST_S  2
+/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_ST    (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M  (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S)
+#define UHCI_TX_HUNG_INT_ST_V  0x00000001U
+#define UHCI_TX_HUNG_INT_ST_S  3
+/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_ST    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_ST_M  (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S)
+#define UHCI_SEND_S_REG_Q_INT_ST_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_ST_S  4
+/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_ST    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_ST_M  (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S)
+#define UHCI_SEND_A_REG_Q_INT_ST_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_ST_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_ST    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
+/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_ST    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_M  (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S)
+#define UHCI_APP_CTRL0_INT_ST_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_ST_S  7
+/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_ST    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_M  (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S)
+#define UHCI_APP_CTRL1_INT_ST_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_ST_S  8
+
+/** UHCI_INT_ENA_REG register
+ *  UHCI Interrupt Enable Register
+ */
+#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc)
+/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_ENA    (BIT(0))
+#define UHCI_RX_START_INT_ENA_M  (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S)
+#define UHCI_RX_START_INT_ENA_V  0x00000001U
+#define UHCI_RX_START_INT_ENA_S  0
+/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_ENA    (BIT(1))
+#define UHCI_TX_START_INT_ENA_M  (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S)
+#define UHCI_TX_START_INT_ENA_V  0x00000001U
+#define UHCI_TX_START_INT_ENA_S  1
+/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_ENA    (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M  (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S)
+#define UHCI_RX_HUNG_INT_ENA_V  0x00000001U
+#define UHCI_RX_HUNG_INT_ENA_S  2
+/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_ENA    (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M  (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S)
+#define UHCI_TX_HUNG_INT_ENA_V  0x00000001U
+#define UHCI_TX_HUNG_INT_ENA_S  3
+/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_ENA    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_ENA_M  (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S)
+#define UHCI_SEND_S_REG_Q_INT_ENA_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_ENA_S  4
+/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_ENA    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_ENA_M  (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S)
+#define UHCI_SEND_A_REG_Q_INT_ENA_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_ENA_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
+/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_ENA    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_M  (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S)
+#define UHCI_APP_CTRL0_INT_ENA_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_ENA_S  7
+/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_ENA    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_M  (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S)
+#define UHCI_APP_CTRL1_INT_ENA_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_ENA_S  8
+
+/** UHCI_INT_CLR_REG register
+ *  UHCI Interrupt Clear Register
+ */
+#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10)
+/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_CLR    (BIT(0))
+#define UHCI_RX_START_INT_CLR_M  (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S)
+#define UHCI_RX_START_INT_CLR_V  0x00000001U
+#define UHCI_RX_START_INT_CLR_S  0
+/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_CLR    (BIT(1))
+#define UHCI_TX_START_INT_CLR_M  (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S)
+#define UHCI_TX_START_INT_CLR_V  0x00000001U
+#define UHCI_TX_START_INT_CLR_S  1
+/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_CLR    (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M  (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S)
+#define UHCI_RX_HUNG_INT_CLR_V  0x00000001U
+#define UHCI_RX_HUNG_INT_CLR_S  2
+/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_CLR    (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M  (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S)
+#define UHCI_TX_HUNG_INT_CLR_V  0x00000001U
+#define UHCI_TX_HUNG_INT_CLR_S  3
+/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_CLR    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_CLR_M  (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S)
+#define UHCI_SEND_S_REG_Q_INT_CLR_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_CLR_S  4
+/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_CLR    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_CLR_M  (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S)
+#define UHCI_SEND_A_REG_Q_INT_CLR_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_CLR_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
+/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_CLR    (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_M  (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S)
+#define UHCI_APP_CTRL0_INT_CLR_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_CLR_S  7
+/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_CLR    (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_M  (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S)
+#define UHCI_APP_CTRL1_INT_CLR_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_CLR_S  8
+
+/** UHCI_CONF1_REG register
+ *  UHCI Configuration Register1
+ */
+#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14)
+/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to enable head checksum check when receiving.
+ */
+#define UHCI_CHECK_SUM_EN    (BIT(0))
+#define UHCI_CHECK_SUM_EN_M  (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S)
+#define UHCI_CHECK_SUM_EN_V  0x00000001U
+#define UHCI_CHECK_SUM_EN_S  0
+/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to  enable sequence number check when receiving.
+ */
+#define UHCI_CHECK_SEQ_EN    (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M  (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S)
+#define UHCI_CHECK_SEQ_EN_V  0x00000001U
+#define UHCI_CHECK_SEQ_EN_S  1
+/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to support CRC calculation, and data integrity check bit should 1.
+ */
+#define UHCI_CRC_DISABLE    (BIT(2))
+#define UHCI_CRC_DISABLE_M  (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S)
+#define UHCI_CRC_DISABLE_V  0x00000001U
+#define UHCI_CRC_DISABLE_S  2
+/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to save data packet head when UHCI receive data.
+ */
+#define UHCI_SAVE_HEAD    (BIT(3))
+#define UHCI_SAVE_HEAD_M  (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S)
+#define UHCI_SAVE_HEAD_V  0x00000001U
+#define UHCI_SAVE_HEAD_S  3
+/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to encode data packet with checksum.
+ */
+#define UHCI_TX_CHECK_SUM_RE    (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M  (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S)
+#define UHCI_TX_CHECK_SUM_RE_V  0x00000001U
+#define UHCI_TX_CHECK_SUM_RE_S  4
+/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to encode data packet with ACK when reliable data packet is ready.
+ */
+#define UHCI_TX_ACK_NUM_RE    (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M  (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S)
+#define UHCI_TX_ACK_NUM_RE_V  0x00000001U
+#define UHCI_TX_ACK_NUM_RE_S  5
+/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
+ */
+#define UHCI_WAIT_SW_START    (BIT(7))
+#define UHCI_WAIT_SW_START_M  (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S)
+#define UHCI_WAIT_SW_START_V  0x00000001U
+#define UHCI_WAIT_SW_START_S  7
+/** UHCI_SW_START : WT; bitpos: [8]; default: 0;
+ *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
+ */
+#define UHCI_SW_START    (BIT(8))
+#define UHCI_SW_START_M  (UHCI_SW_START_V << UHCI_SW_START_S)
+#define UHCI_SW_START_V  0x00000001U
+#define UHCI_SW_START_S  8
+
+/** UHCI_STATE0_REG register
+ *  UHCI Receive Status Register
+ */
+#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18)
+/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0;
+ *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
+ *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
+ *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
+ *  not found, but received packet is completed. 3'b110: CRC check error.
+ */
+#define UHCI_RX_ERR_CAUSE    0x00000007U
+#define UHCI_RX_ERR_CAUSE_M  (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S)
+#define UHCI_RX_ERR_CAUSE_V  0x00000007U
+#define UHCI_RX_ERR_CAUSE_S  0
+/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0;
+ *  Indicates UHCI decoder status.
+ */
+#define UHCI_DECODE_STATE    0x00000007U
+#define UHCI_DECODE_STATE_M  (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S)
+#define UHCI_DECODE_STATE_V  0x00000007U
+#define UHCI_DECODE_STATE_S  3
+
+/** UHCI_STATE1_REG register
+ *  UHCI Transmit Status Register
+ */
+#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c)
+/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0;
+ *  Indicates UHCI encoder status.
+ */
+#define UHCI_ENCODE_STATE    0x00000007U
+#define UHCI_ENCODE_STATE_M  (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S)
+#define UHCI_ENCODE_STATE_V  0x00000007U
+#define UHCI_ENCODE_STATE_S  0
+
+/** UHCI_ESCAPE_CONF_REG register
+ *  UHCI Escapes Configuration Register0
+ */
+#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20)
+/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
+ */
+#define UHCI_TX_C0_ESC_EN    (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M  (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S)
+#define UHCI_TX_C0_ESC_EN_V  0x00000001U
+#define UHCI_TX_C0_ESC_EN_S  0
+/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to enable resolve char 0xDB when DMA receiving data.
+ */
+#define UHCI_TX_DB_ESC_EN    (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M  (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S)
+#define UHCI_TX_DB_ESC_EN_V  0x00000001U
+#define UHCI_TX_DB_ESC_EN_S  1
+/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
+ */
+#define UHCI_TX_11_ESC_EN    (BIT(2))
+#define UHCI_TX_11_ESC_EN_M  (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S)
+#define UHCI_TX_11_ESC_EN_V  0x00000001U
+#define UHCI_TX_11_ESC_EN_S  2
+/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
+ */
+#define UHCI_TX_13_ESC_EN    (BIT(3))
+#define UHCI_TX_13_ESC_EN_M  (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S)
+#define UHCI_TX_13_ESC_EN_V  0x00000001U
+#define UHCI_TX_13_ESC_EN_S  3
+/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
+ */
+#define UHCI_RX_C0_ESC_EN    (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M  (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S)
+#define UHCI_RX_C0_ESC_EN_V  0x00000001U
+#define UHCI_RX_C0_ESC_EN_S  4
+/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
+ */
+#define UHCI_RX_DB_ESC_EN    (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M  (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S)
+#define UHCI_RX_DB_ESC_EN_V  0x00000001U
+#define UHCI_RX_DB_ESC_EN_S  5
+/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
+ */
+#define UHCI_RX_11_ESC_EN    (BIT(6))
+#define UHCI_RX_11_ESC_EN_M  (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S)
+#define UHCI_RX_11_ESC_EN_V  0x00000001U
+#define UHCI_RX_11_ESC_EN_S  6
+/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
+ */
+#define UHCI_RX_13_ESC_EN    (BIT(7))
+#define UHCI_RX_13_ESC_EN_M  (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S)
+#define UHCI_RX_13_ESC_EN_V  0x00000001U
+#define UHCI_RX_13_ESC_EN_S  7
+
+/** UHCI_HUNG_CONF_REG register
+ *  UHCI Hung Configuration Register0
+ */
+#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24)
+/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
+ *  data.
+ */
+#define UHCI_TXFIFO_TIMEOUT    0x000000FFU
+#define UHCI_TXFIFO_TIMEOUT_M  (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S)
+#define UHCI_TXFIFO_TIMEOUT_V  0x000000FFU
+#define UHCI_TXFIFO_TIMEOUT_S  0
+/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  Configures the maximum counter value.
+ */
+#define UHCI_TXFIFO_TIMEOUT_SHIFT    0x00000007U
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S)
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
+/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  Set this bit to enable TX FIFO timeout when receiving.
+ */
+#define UHCI_TXFIFO_TIMEOUT_ENA    (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M  (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S)
+#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x00000001U
+#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
+/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16;
+ *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
+ *  RAM data.
+ */
+#define UHCI_RXFIFO_TIMEOUT    0x000000FFU
+#define UHCI_RXFIFO_TIMEOUT_M  (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S)
+#define UHCI_RXFIFO_TIMEOUT_V  0x000000FFU
+#define UHCI_RXFIFO_TIMEOUT_S  12
+/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0;
+ *  Configures the maximum counter value.
+ */
+#define UHCI_RXFIFO_TIMEOUT_SHIFT    0x00000007U
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S)
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
+/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1;
+ *  Set this bit to enable TX FIFO timeout when DMA sending data.
+ */
+#define UHCI_RXFIFO_TIMEOUT_ENA    (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M  (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S)
+#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x00000001U
+#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
+
+/** UHCI_ACK_NUM_REG register
+ *  UHCI Ack Value Configuration Register0
+ */
+#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28)
+/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0;
+ *  Indicates the ACK number during software flow control.
+ */
+#define UHCI_ACK_NUM    0x00000007U
+#define UHCI_ACK_NUM_M  (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S)
+#define UHCI_ACK_NUM_V  0x00000007U
+#define UHCI_ACK_NUM_S  0
+/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0;
+ *  Set this bit to load the ACK value of UHCI_ACK_NUM.
+ */
+#define UHCI_ACK_NUM_LOAD    (BIT(3))
+#define UHCI_ACK_NUM_LOAD_M  (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S)
+#define UHCI_ACK_NUM_LOAD_V  0x00000001U
+#define UHCI_ACK_NUM_LOAD_S  3
+
+/** UHCI_RX_HEAD_REG register
+ *  UHCI Head Register
+ */
+#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c)
+/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0;
+ *  Stores the head of received packet.
+ */
+#define UHCI_RX_HEAD    0xFFFFFFFFU
+#define UHCI_RX_HEAD_M  (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S)
+#define UHCI_RX_HEAD_V  0xFFFFFFFFU
+#define UHCI_RX_HEAD_S  0
+
+/** UHCI_QUICK_SENT_REG register
+ *  UCHI Quick send Register
+ */
+#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30)
+/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0;
+ *  Configures single_send mode.
+ */
+#define UHCI_SINGLE_SEND_NUM    0x00000007U
+#define UHCI_SINGLE_SEND_NUM_M  (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S)
+#define UHCI_SINGLE_SEND_NUM_V  0x00000007U
+#define UHCI_SINGLE_SEND_NUM_S  0
+/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0;
+ *  Set this bit to enable sending short packet with single_send mode.
+ */
+#define UHCI_SINGLE_SEND_EN    (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M  (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S)
+#define UHCI_SINGLE_SEND_EN_V  0x00000001U
+#define UHCI_SINGLE_SEND_EN_S  3
+/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0;
+ *  Configures always_send mode.
+ */
+#define UHCI_ALWAYS_SEND_NUM    0x00000007U
+#define UHCI_ALWAYS_SEND_NUM_M  (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S)
+#define UHCI_ALWAYS_SEND_NUM_V  0x00000007U
+#define UHCI_ALWAYS_SEND_NUM_S  4
+/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable sending short packet with always_send mode.
+ */
+#define UHCI_ALWAYS_SEND_EN    (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M  (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S)
+#define UHCI_ALWAYS_SEND_EN_V  0x00000001U
+#define UHCI_ALWAYS_SEND_EN_S  7
+
+/** UHCI_REG_Q0_WORD0_REG register
+ *  UHCI Q0_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34)
+/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q0_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD0_M  (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S)
+#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD0_S  0
+
+/** UHCI_REG_Q0_WORD1_REG register
+ *  UHCI Q0_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38)
+/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q0_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD1_M  (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S)
+#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD1_S  0
+
+/** UHCI_REG_Q1_WORD0_REG register
+ *  UHCI Q1_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c)
+/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q1_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD0_M  (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S)
+#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD0_S  0
+
+/** UHCI_REG_Q1_WORD1_REG register
+ *  UHCI Q1_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40)
+/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q1_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD1_M  (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S)
+#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD1_S  0
+
+/** UHCI_REG_Q2_WORD0_REG register
+ *  UHCI Q2_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44)
+/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q2_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD0_M  (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S)
+#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD0_S  0
+
+/** UHCI_REG_Q2_WORD1_REG register
+ *  UHCI Q2_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48)
+/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q2_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD1_M  (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S)
+#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD1_S  0
+
+/** UHCI_REG_Q3_WORD0_REG register
+ *  UHCI Q3_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c)
+/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q3_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD0_M  (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S)
+#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD0_S  0
+
+/** UHCI_REG_Q3_WORD1_REG register
+ *  UHCI Q3_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50)
+/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q3_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD1_M  (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S)
+#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD1_S  0
+
+/** UHCI_REG_Q4_WORD0_REG register
+ *  UHCI Q4_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54)
+/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q4_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD0_M  (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S)
+#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD0_S  0
+
+/** UHCI_REG_Q4_WORD1_REG register
+ *  UHCI Q4_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58)
+/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q4_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD1_M  (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S)
+#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD1_S  0
+
+/** UHCI_REG_Q5_WORD0_REG register
+ *  UHCI Q5_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c)
+/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q5_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD0_M  (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S)
+#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD0_S  0
+
+/** UHCI_REG_Q5_WORD1_REG register
+ *  UHCI Q5_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60)
+/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q5_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD1_M  (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S)
+#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD1_S  0
+
+/** UHCI_REG_Q6_WORD0_REG register
+ *  UHCI Q6_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64)
+/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q6_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD0_M  (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S)
+#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD0_S  0
+
+/** UHCI_REG_Q6_WORD1_REG register
+ *  UHCI Q6_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68)
+/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q6_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD1_M  (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S)
+#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD1_S  0
+
+/** UHCI_ESC_CONF0_REG register
+ *  UHCI Escapes Sequence Configuration Register0
+ */
+#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c)
+/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192;
+ *  Configures the delimiter for encoding, default value is 0xC0.
+ */
+#define UHCI_SEPER_CHAR    0x000000FFU
+#define UHCI_SEPER_CHAR_M  (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S)
+#define UHCI_SEPER_CHAR_V  0x000000FFU
+#define UHCI_SEPER_CHAR_S  0
+/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_SEPER_ESC_CHAR0    0x000000FFU
+#define UHCI_SEPER_ESC_CHAR0_M  (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S)
+#define UHCI_SEPER_ESC_CHAR0_V  0x000000FFU
+#define UHCI_SEPER_ESC_CHAR0_S  8
+/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220;
+ *  Configures the second char of SLIP escape character, default value is 0xDC.
+ */
+#define UHCI_SEPER_ESC_CHAR1    0x000000FFU
+#define UHCI_SEPER_ESC_CHAR1_M  (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S)
+#define UHCI_SEPER_ESC_CHAR1_V  0x000000FFU
+#define UHCI_SEPER_ESC_CHAR1_S  16
+
+/** UHCI_ESC_CONF1_REG register
+ *  UHCI Escapes Sequence Configuration Register1
+ */
+#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70)
+/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219;
+ *  Configures the char needing encoding, which is 0xDB as flow control char by default.
+ */
+#define UHCI_ESC_SEQ0    0x000000FFU
+#define UHCI_ESC_SEQ0_M  (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S)
+#define UHCI_ESC_SEQ0_V  0x000000FFU
+#define UHCI_ESC_SEQ0_S  0
+/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ0_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR0_M  (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S)
+#define UHCI_ESC_SEQ0_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR0_S  8
+/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221;
+ *  Configures the second char of SLIP escape character, default value is 0xDD.
+ */
+#define UHCI_ESC_SEQ0_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR1_M  (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S)
+#define UHCI_ESC_SEQ0_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR1_S  16
+
+/** UHCI_ESC_CONF2_REG register
+ *  UHCI Escapes Sequence Configuration Register2
+ */
+#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74)
+/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17;
+ *  Configures the char needing encoding, which is 0x11 as flow control char by default.
+ */
+#define UHCI_ESC_SEQ1    0x000000FFU
+#define UHCI_ESC_SEQ1_M  (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S)
+#define UHCI_ESC_SEQ1_V  0x000000FFU
+#define UHCI_ESC_SEQ1_S  0
+/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ1_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR0_M  (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S)
+#define UHCI_ESC_SEQ1_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR0_S  8
+/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222;
+ *  Configures the second char of SLIP escape character, default value is 0xDE.
+ */
+#define UHCI_ESC_SEQ1_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR1_M  (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S)
+#define UHCI_ESC_SEQ1_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR1_S  16
+
+/** UHCI_ESC_CONF3_REG register
+ *  UHCI Escapes Sequence Configuration Register3
+ */
+#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78)
+/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19;
+ *  Configures the char needing encoding, which is 0x13 as flow control char by default.
+ */
+#define UHCI_ESC_SEQ2    0x000000FFU
+#define UHCI_ESC_SEQ2_M  (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S)
+#define UHCI_ESC_SEQ2_V  0x000000FFU
+#define UHCI_ESC_SEQ2_S  0
+/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ2_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR0_M  (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S)
+#define UHCI_ESC_SEQ2_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR0_S  8
+/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223;
+ *  Configures the second char of SLIP escape character, default value is 0xDF.
+ */
+#define UHCI_ESC_SEQ2_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR1_M  (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S)
+#define UHCI_ESC_SEQ2_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR1_S  16
+
+/** UHCI_PKT_THRES_REG register
+ *  UCHI Packet Length Configuration Register
+ */
+#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c)
+/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128;
+ *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
+ */
+#define UHCI_PKT_THRS    0x00001FFFU
+#define UHCI_PKT_THRS_M  (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S)
+#define UHCI_PKT_THRS_V  0x00001FFFU
+#define UHCI_PKT_THRS_S  0
+
+/** UHCI_DATE_REG register
+ *  UHCI Version Register
+ */
+#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80)
+/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936;
+ *  Configures version.
+ */
+#define UHCI_DATE    0xFFFFFFFFU
+#define UHCI_DATE_M  (UHCI_DATE_V << UHCI_DATE_S)
+#define UHCI_DATE_V  0xFFFFFFFFU
+#define UHCI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/uhci_struct.h b/components/soc/esp32p4/include/soc/uhci_struct.h
new file mode 100644
index 0000000000..850747a199
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/uhci_struct.h
@@ -0,0 +1,843 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of conf0 register
+ *  UHCI Configuration Register0
+ */
+typedef union {
+    struct {
+        /** tx_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0 to this bit to reset decode state machine.
+         */
+        uint32_t tx_rst:1;
+        /** rx_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset encode state machine.
+         */
+        uint32_t rx_rst:1;
+        /** uart_sel : R/W; bitpos: [4:2]; default: 0;
+         *  Select which uart to connect with GDMA.
+         */
+        uint32_t uart_sel:3;
+        /** seper_en : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to separate the data frame using a special char.
+         */
+        uint32_t seper_en:1;
+        /** head_en : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to encode the data packet with a formatting header.
+         */
+        uint32_t head_en:1;
+        /** crc_rec_en : R/W; bitpos: [7]; default: 1;
+         *  Set this bit to enable UHCI to receive the 16 bit CRC.
+         */
+        uint32_t crc_rec_en:1;
+        /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
+         *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
+         *  been in idle state.
+         */
+        uint32_t uart_idle_eof_en:1;
+        /** len_eof_en : R/W; bitpos: [9]; default: 1;
+         *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
+         *  receiving byte count has reached the specified value. The value is payload length
+         *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+         *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
+         *  receiving payload data is end when 0xc0 is received.
+         */
+        uint32_t len_eof_en:1;
+        /** encode_crc_en : R/W; bitpos: [10]; default: 1;
+         *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
+         *  end of the payload.
+         */
+        uint32_t encode_crc_en:1;
+        /** clk_en : R/W; bitpos: [11]; default: 0;
+         *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
+         *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
+         *  received by UART.
+         */
+        uint32_t uart_rx_brk_eof_en:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} uhci_conf0_reg_t;
+
+/** Type of conf1 register
+ *  UHCI Configuration Register1
+ */
+typedef union {
+    struct {
+        /** check_sum_en : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to enable head checksum check when receiving.
+         */
+        uint32_t check_sum_en:1;
+        /** check_seq_en : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to  enable sequence number check when receiving.
+         */
+        uint32_t check_seq_en:1;
+        /** crc_disable : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to support CRC calculation, and data integrity check bit should 1.
+         */
+        uint32_t crc_disable:1;
+        /** save_head : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to save data packet head when UHCI receive data.
+         */
+        uint32_t save_head:1;
+        /** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to encode data packet with checksum.
+         */
+        uint32_t tx_check_sum_re:1;
+        /** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to encode data packet with ACK when reliable data packet is ready.
+         */
+        uint32_t tx_ack_num_re:1;
+        uint32_t reserved_6:1;
+        /** wait_sw_start : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
+         */
+        uint32_t wait_sw_start:1;
+        /** sw_start : WT; bitpos: [8]; default: 0;
+         *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
+         */
+        uint32_t sw_start:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_conf1_reg_t;
+
+/** Type of escape_conf register
+ *  UHCI Escapes Configuration Register0
+ */
+typedef union {
+    struct {
+        /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
+         */
+        uint32_t tx_c0_esc_en:1;
+        /** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to enable resolve char 0xDB when DMA receiving data.
+         */
+        uint32_t tx_db_esc_en:1;
+        /** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
+         */
+        uint32_t tx_11_esc_en:1;
+        /** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
+         */
+        uint32_t tx_13_esc_en:1;
+        /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
+         */
+        uint32_t rx_c0_esc_en:1;
+        /** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
+         */
+        uint32_t rx_db_esc_en:1;
+        /** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
+         */
+        uint32_t rx_11_esc_en:1;
+        /** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
+         */
+        uint32_t rx_13_esc_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uhci_escape_conf_reg_t;
+
+/** Type of hung_conf register
+ *  UHCI Hung Configuration Register0
+ */
+typedef union {
+    struct {
+        /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
+         *  data.
+         */
+        uint32_t txfifo_timeout:8;
+        /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  Configures the maximum counter value.
+         */
+        uint32_t txfifo_timeout_shift:3;
+        /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  Set this bit to enable TX FIFO timeout when receiving.
+         */
+        uint32_t txfifo_timeout_ena:1;
+        /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
+         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
+         *  RAM data.
+         */
+        uint32_t rxfifo_timeout:8;
+        /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
+         *  Configures the maximum counter value.
+         */
+        uint32_t rxfifo_timeout_shift:3;
+        /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
+         *  Set this bit to enable TX FIFO timeout when DMA sending data.
+         */
+        uint32_t rxfifo_timeout_ena:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_hung_conf_reg_t;
+
+/** Type of ack_num register
+ *  UHCI Ack Value Configuration Register0
+ */
+typedef union {
+    struct {
+        /** ack_num : R/W; bitpos: [2:0]; default: 0;
+         *  Indicates the ACK number during software flow control.
+         */
+        uint32_t ack_num:3;
+        /** ack_num_load : WT; bitpos: [3]; default: 0;
+         *  Set this bit to load the ACK value of UHCI_ACK_NUM.
+         */
+        uint32_t ack_num_load:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uhci_ack_num_reg_t;
+
+/** Type of quick_sent register
+ *  UCHI Quick send Register
+ */
+typedef union {
+    struct {
+        /** single_send_num : R/W; bitpos: [2:0]; default: 0;
+         *  Configures single_send mode.
+         */
+        uint32_t single_send_num:3;
+        /** single_send_en : WT; bitpos: [3]; default: 0;
+         *  Set this bit to enable sending short packet with single_send mode.
+         */
+        uint32_t single_send_en:1;
+        /** always_send_num : R/W; bitpos: [6:4]; default: 0;
+         *  Configures always_send mode.
+         */
+        uint32_t always_send_num:3;
+        /** always_send_en : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable sending short packet with always_send mode.
+         */
+        uint32_t always_send_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uhci_quick_sent_reg_t;
+
+/** Type of reg_q0_word0 register
+ *  UHCI Q0_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q0_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q0_word0_reg_t;
+
+/** Type of reg_q0_word1 register
+ *  UHCI Q0_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q0_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q0_word1_reg_t;
+
+/** Type of reg_q1_word0 register
+ *  UHCI Q1_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q1_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q1_word0_reg_t;
+
+/** Type of reg_q1_word1 register
+ *  UHCI Q1_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q1_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q1_word1_reg_t;
+
+/** Type of reg_q2_word0 register
+ *  UHCI Q2_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q2_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q2_word0_reg_t;
+
+/** Type of reg_q2_word1 register
+ *  UHCI Q2_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q2_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q2_word1_reg_t;
+
+/** Type of reg_q3_word0 register
+ *  UHCI Q3_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q3_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q3_word0_reg_t;
+
+/** Type of reg_q3_word1 register
+ *  UHCI Q3_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q3_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q3_word1_reg_t;
+
+/** Type of reg_q4_word0 register
+ *  UHCI Q4_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q4_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q4_word0_reg_t;
+
+/** Type of reg_q4_word1 register
+ *  UHCI Q4_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q4_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q4_word1_reg_t;
+
+/** Type of reg_q5_word0 register
+ *  UHCI Q5_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q5_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q5_word0_reg_t;
+
+/** Type of reg_q5_word1 register
+ *  UHCI Q5_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q5_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q5_word1_reg_t;
+
+/** Type of reg_q6_word0 register
+ *  UHCI Q6_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q6_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q6_word0_reg_t;
+
+/** Type of reg_q6_word1 register
+ *  UHCI Q6_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q6_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q6_word1_reg_t;
+
+/** Type of esc_conf0 register
+ *  UHCI Escapes Sequence Configuration Register0
+ */
+typedef union {
+    struct {
+        /** seper_char : R/W; bitpos: [7:0]; default: 192;
+         *  Configures the delimiter for encoding, default value is 0xC0.
+         */
+        uint32_t seper_char:8;
+        /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t seper_esc_char0:8;
+        /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
+         *  Configures the second char of SLIP escape character, default value is 0xDC.
+         */
+        uint32_t seper_esc_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf0_reg_t;
+
+/** Type of esc_conf1 register
+ *  UHCI Escapes Sequence Configuration Register1
+ */
+typedef union {
+    struct {
+        /** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
+         *  Configures the char needing encoding, which is 0xDB as flow control char by default.
+         */
+        uint32_t esc_seq0:8;
+        /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq0_char0:8;
+        /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
+         *  Configures the second char of SLIP escape character, default value is 0xDD.
+         */
+        uint32_t esc_seq0_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf1_reg_t;
+
+/** Type of esc_conf2 register
+ *  UHCI Escapes Sequence Configuration Register2
+ */
+typedef union {
+    struct {
+        /** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
+         *  Configures the char needing encoding, which is 0x11 as flow control char by default.
+         */
+        uint32_t esc_seq1:8;
+        /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq1_char0:8;
+        /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
+         *  Configures the second char of SLIP escape character, default value is 0xDE.
+         */
+        uint32_t esc_seq1_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf2_reg_t;
+
+/** Type of esc_conf3 register
+ *  UHCI Escapes Sequence Configuration Register3
+ */
+typedef union {
+    struct {
+        /** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
+         *  Configures the char needing encoding, which is 0x13 as flow control char by default.
+         */
+        uint32_t esc_seq2:8;
+        /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq2_char0:8;
+        /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
+         *  Configures the second char of SLIP escape character, default value is 0xDF.
+         */
+        uint32_t esc_seq2_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf3_reg_t;
+
+/** Type of pkt_thres register
+ *  UCHI Packet Length Configuration Register
+ */
+typedef union {
+    struct {
+        /** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
+         *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
+         */
+        uint32_t pkt_thrs:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} uhci_pkt_thres_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  UHCI Interrupt Raw Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
+         *  delimiter is sent successfully.
+         */
+        uint32_t rx_start_int_raw:1;
+        /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
+         *  DMA detects delimiter.
+         */
+        uint32_t tx_start_int_raw:1;
+        /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
+         *  the required time of DMA receiving data  exceeds the configuration value.
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
+         *  the required time of DMA reading RAM data  exceeds the configuration value.
+         */
+        uint32_t tx_hung_int_raw:1;
+        /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
+         *  when UHCI sends short packet successfully with single_send mode.
+         */
+        uint32_t send_s_reg_q_int_raw:1;
+        /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
+         *  when UHCI sends short packet successfully with always_send mode.
+         */
+        uint32_t send_a_reg_q_int_raw:1;
+        /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
+         *  there are errors in EOF.
+         */
+        uint32_t out_eof_int_raw:1;
+        /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
+         *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
+         *  UHCI_APP_CTRL0_IN_SET is set to 1.
+         */
+        uint32_t app_ctrl0_int_raw:1;
+        /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
+         *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
+         *  UHCI_APP_CTRL1_IN_SET is set to 1.
+         */
+        uint32_t app_ctrl1_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_raw_reg_t;
+
+/** Type of int_st register
+ *  UHCI Interrupt Status Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_st : RO; bitpos: [0]; default: 0;
+         *  Indicates the interrupt status of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_st:1;
+        /** tx_start_int_st : RO; bitpos: [1]; default: 0;
+         *  Indicates the interrupt status of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_st:1;
+        /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
+         *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_st:1;
+        /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
+         *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_st:1;
+        /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
+         *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_st:1;
+        /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
+         *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_st:1;
+        /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
+         *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_st_reg_t;
+
+/** Type of int_ena register
+ *  UHCI Interrupt Enable Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_ena:1;
+        /** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_ena:1;
+        /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_ena:1;
+        /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_ena:1;
+        /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_ena:1;
+        /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_ena:1;
+        /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  UHCI Interrupt Clear Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_clr:1;
+        /** tx_start_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_clr:1;
+        /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_clr:1;
+        /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_clr:1;
+        /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_clr:1;
+        /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_clr:1;
+        /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_clr_reg_t;
+
+
+/** Group: UHCI Status Register */
+/** Type of state0 register
+ *  UHCI Receive Status Register
+ */
+typedef union {
+    struct {
+        /** rx_err_cause : RO; bitpos: [2:0]; default: 0;
+         *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
+         *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
+         *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
+         *  not found, but received packet is completed. 3'b110: CRC check error.
+         */
+        uint32_t rx_err_cause:3;
+        /** decode_state : RO; bitpos: [5:3]; default: 0;
+         *  Indicates UHCI decoder status.
+         */
+        uint32_t decode_state:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} uhci_state0_reg_t;
+
+/** Type of state1 register
+ *  UHCI Transmit Status Register
+ */
+typedef union {
+    struct {
+        /** encode_state : RO; bitpos: [2:0]; default: 0;
+         *  Indicates UHCI encoder status.
+         */
+        uint32_t encode_state:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} uhci_state1_reg_t;
+
+/** Type of rx_head register
+ *  UHCI Head Register
+ */
+typedef union {
+    struct {
+        /** rx_head : RO; bitpos: [31:0]; default: 0;
+         *  Stores the head of received packet.
+         */
+        uint32_t rx_head:32;
+    };
+    uint32_t val;
+} uhci_rx_head_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UHCI Version Register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35655936;
+         *  Configures version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uhci_date_reg_t;
+
+
+typedef struct {
+    volatile uhci_conf0_reg_t conf0;
+    volatile uhci_int_raw_reg_t int_raw;
+    volatile uhci_int_st_reg_t int_st;
+    volatile uhci_int_ena_reg_t int_ena;
+    volatile uhci_int_clr_reg_t int_clr;
+    volatile uhci_conf1_reg_t conf1;
+    volatile uhci_state0_reg_t state0;
+    volatile uhci_state1_reg_t state1;
+    volatile uhci_escape_conf_reg_t escape_conf;
+    volatile uhci_hung_conf_reg_t hung_conf;
+    volatile uhci_ack_num_reg_t ack_num;
+    volatile uhci_rx_head_reg_t rx_head;
+    volatile uhci_quick_sent_reg_t quick_sent;
+    volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
+    volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
+    volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
+    volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
+    volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
+    volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
+    volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
+    volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
+    volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
+    volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
+    volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
+    volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
+    volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
+    volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
+    volatile uhci_esc_conf0_reg_t esc_conf0;
+    volatile uhci_esc_conf1_reg_t esc_conf1;
+    volatile uhci_esc_conf2_reg_t esc_conf2;
+    volatile uhci_esc_conf3_reg_t esc_conf3;
+    volatile uhci_pkt_thres_reg_t pkt_thres;
+    volatile uhci_date_reg_t date;
+} uhci_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/usb_device_reg.h b/components/soc/esp32p4/include/soc/usb_device_reg.h
new file mode 100644
index 0000000000..478c734ea8
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/usb_device_reg.h
@@ -0,0 +1,1282 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+ *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
+ *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
+ *  received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
+ *  Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
+/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
+#define USB_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_S  0
+/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
+#define USB_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_S  1
+/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
+/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
+/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
+/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
+/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
+/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
+/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_SERIAL_JTAG_ECO_LOW_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
+/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M  (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S)
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S  0
+
+/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
+/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S)
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S  0
+
+/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74)
+/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_RESULT_48    (BIT(0))
+#define USB_SERIAL_JTAG_RDN_RESULT_48_M  (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S)
+#define USB_SERIAL_JTAG_RDN_RESULT_48_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_RESULT_48_S  0
+/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_ENA_48    (BIT(1))
+#define USB_SERIAL_JTAG_RDN_ENA_48_M  (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S)
+#define USB_SERIAL_JTAG_RDN_ENA_48_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_ENA_48_S  1
+
+/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78)
+/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M  (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S)
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S  0
+
+/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c)
+/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S)
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S  0
+
+/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_RESULT_APB    (BIT(0))
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_M  (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S)
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_S  0
+/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_ENA_APB    (BIT(1))
+#define USB_SERIAL_JTAG_RDN_ENA_APB_M  (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S)
+#define USB_SERIAL_JTAG_RDN_ENA_APB_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_ENA_APB_S  1
+
+/** USB_SERIAL_JTAG_SRAM_CTRL_REG register
+ *  PPA SRAM Control Register
+ */
+#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84)
+/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  Control signals
+ */
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL    0x00003FFFU
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M  (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S)
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V  0x00003FFFU
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S  0
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/usb_device_struct.h b/components/soc/esp32p4/include/soc/usb_device_struct.h
new file mode 100644
index 0000000000..ed400ae548
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/usb_device_struct.h
@@ -0,0 +1,1044 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of ep1 register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+typedef union {
+    struct {
+        /** rdwr_byte : RO; bitpos: [7:0]; default: 0;
+         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+         *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+         *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
+         *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
+         *  received, then read data from UART Rx FIFO.
+         */
+        uint32_t rdwr_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_reg_t;
+
+/** Type of ep1_conf register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+typedef union {
+    struct {
+        /** wr_done : WT; bitpos: [0]; default: 0;
+         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+         */
+        uint32_t wr_done:1;
+        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
+         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+         *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
+         *  Host.
+         */
+        uint32_t serial_in_ep_data_free:1;
+        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
+         *  1'b1: Indicate there is data in UART Rx FIFO.
+         */
+        uint32_t serial_out_ep_data_avail:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_conf_reg_t;
+
+/** Type of conf0 register
+ *  PHY hardware configuration.
+ */
+typedef union {
+    struct {
+        /** phy_sel : R/W; bitpos: [0]; default: 0;
+         *  Select internal/external PHY
+         */
+        uint32_t phy_sel:1;
+        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
+         *  Enable software control USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [2]; default: 0;
+         *  USB D+ D- exchange
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [4:3]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [6:5]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [7]; default: 0;
+         *  Enable software control input  threshold
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
+         *  Enable software control USB D+ D- pullup pulldown
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [9]; default: 1;
+         *  Control USB D+ pull up.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
+         *  Control USB D+ pull down.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [11]; default: 0;
+         *  Control USB D- pull up.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
+         *  Control USB D- pull down.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [13]; default: 0;
+         *  Control pull up value.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
+         *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+         *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+         *  through GPIO Matrix.
+         */
+        uint32_t usb_jtag_bridge_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_conf0_reg_t;
+
+/** Type of test register
+ *  Registers used for debugging the PHY.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable test of the USB pad
+         */
+        uint32_t test_enable:1;
+        /** test_usb_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test
+         */
+        uint32_t test_usb_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 1;
+         *  USB RCV value in test
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 1;
+         *  USB D+ rx value in test
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_serial_jtag_test_reg_t;
+
+/** Type of misc_conf register
+ *  Clock enable control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_misc_conf_reg_t;
+
+/** Type of mem_conf register
+ *  Memory power control
+ */
+typedef union {
+    struct {
+        /** usb_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  1: power down usb memory.
+         */
+        uint32_t usb_mem_pd:1;
+        /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
+         *  1: Force clock on for usb memory.
+         */
+        uint32_t usb_mem_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_mem_conf_reg_t;
+
+/** Type of chip_rst register
+ *  CDC-ACM chip reset control.
+ */
+typedef union {
+    struct {
+        /** rts : RO; bitpos: [0]; default: 0;
+         *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+         */
+        uint32_t rts:1;
+        /** dtr : RO; bitpos: [1]; default: 0;
+         *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+         */
+        uint32_t dtr:1;
+        /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to disable chip reset from usb serial channel to reset chip.
+         */
+        uint32_t usb_uart_chip_rst_dis:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_chip_rst_reg_t;
+
+/** Type of get_line_code_w0 register
+ *  W0 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w0_reg_t;
+
+/** Type of get_line_code_w1 register
+ *  W1 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bdata_bits:8;
+        /** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bparity_type:8;
+        /** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bchar_format:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w1_reg_t;
+
+/** Type of config_update register
+ *  Configuration registers' value update
+ */
+typedef union {
+    struct {
+        /** config_update : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this register would update the value of configure registers from APB
+         *  clock domain to 48MHz clock domain.
+         */
+        uint32_t config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_config_update_reg_t;
+
+/** Type of ser_afifo_config register
+ *  Serial AFIFO configure register
+ */
+typedef union {
+    struct {
+        /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+         */
+        uint32_t serial_in_afifo_reset_wr:1;
+        /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+         */
+        uint32_t serial_in_afifo_reset_rd:1;
+        /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+         */
+        uint32_t serial_out_afifo_reset_wr:1;
+        /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+         */
+        uint32_t serial_out_afifo_reset_rd:1;
+        /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
+         *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+         */
+        uint32_t serial_out_afifo_rempty:1;
+        /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
+         *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+         */
+        uint32_t serial_in_afifo_wfull:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} usb_serial_jtag_ser_afifo_config_reg_t;
+
+/** Type of eco_low_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low_48 : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_low_48:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_low_48_reg_t;
+
+/** Type of eco_high_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high_48 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_high_48:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_high_48_reg_t;
+
+/** Type of eco_low_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low_apb : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_low_apb:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_low_apb_reg_t;
+
+/** Type of eco_high_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high_apb : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_high_apb:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_high_apb_reg_t;
+
+/** Type of sram_ctrl register
+ *  PPA SRAM Control Register
+ */
+typedef union {
+    struct {
+        /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  Control signals
+         */
+        uint32_t mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} usb_serial_jtag_sram_ctrl_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Interrupt raw status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when flush cmd is received for IN
+         *  endpoint 2 of JTAG.
+         */
+        uint32_t jtag_in_flush_int_raw:1;
+        /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when SOF frame is received.
+         */
+        uint32_t sof_int_raw:1;
+        /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+         *  one packet.
+         */
+        uint32_t serial_out_recv_pkt_int_raw:1;
+        /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
+         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+         */
+        uint32_t serial_in_empty_int_raw:1;
+        /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when pid error is detected.
+         */
+        uint32_t pid_err_int_raw:1;
+        /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC5 error is detected.
+         */
+        uint32_t crc5_err_int_raw:1;
+        /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC16 error is detected.
+         */
+        uint32_t crc16_err_int_raw:1;
+        /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when stuff error is detected.
+         */
+        uint32_t stuff_err_int_raw:1;
+        /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+         *  received.
+         */
+        uint32_t in_token_rec_in_ep1_int_raw:1;
+        /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when usb bus reset is detected.
+         */
+        uint32_t usb_bus_reset_int_raw:1;
+        /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep1_zero_payload_int_raw:1;
+        /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep2_zero_payload_int_raw:1;
+        /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+         *  is changed.
+         */
+        uint32_t rts_chg_int_raw:1;
+        /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+         *  is changed.
+         */
+        uint32_t dtr_chg_int_raw:1;
+        /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+         *  received.
+         */
+        uint32_t get_line_code_int_raw:1;
+        /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+         *  received.
+         */
+        uint32_t set_line_code_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_st:1;
+        /** sof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+         */
+        uint32_t sof_int_st:1;
+        /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_st:1;
+        /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_st:1;
+        /** pid_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_st:1;
+        /** crc5_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_st:1;
+        /** crc16_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_st:1;
+        /** stuff_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_st:1;
+        /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_st:1;
+        /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_st:1;
+        /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_st:1;
+        /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_st:1;
+        /** rts_chg_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_st:1;
+        /** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_st:1;
+        /** get_line_code_int_st : RO; bitpos: [14]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_st:1;
+        /** set_line_code_int_st : RO; bitpos: [15]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_ena:1;
+        /** sof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+         */
+        uint32_t sof_int_ena:1;
+        /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_ena:1;
+        /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_ena:1;
+        /** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_ena:1;
+        /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_ena:1;
+        /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_ena:1;
+        /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_ena:1;
+        /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_ena:1;
+        /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_ena:1;
+        /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_ena:1;
+        /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_ena:1;
+        /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_ena:1;
+        /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_ena:1;
+        /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_ena:1;
+        /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_clr:1;
+        /** sof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_clr:1;
+        /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_clr:1;
+        /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_clr:1;
+        /** pid_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_clr:1;
+        /** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_clr:1;
+        /** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_clr:1;
+        /** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_clr:1;
+        /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_clr:1;
+        /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_clr:1;
+        /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_clr:1;
+        /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_clr:1;
+        /** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_clr:1;
+        /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_clr:1;
+        /** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_clr:1;
+        /** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of jfifo_st register
+ *  JTAG FIFO status and control registers.
+ */
+typedef union {
+    struct {
+        /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
+         *  JTAT in fifo counter.
+         */
+        uint32_t in_fifo_cnt:2;
+        /** in_fifo_empty : RO; bitpos: [2]; default: 1;
+         *  1: JTAG in fifo is empty.
+         */
+        uint32_t in_fifo_empty:1;
+        /** in_fifo_full : RO; bitpos: [3]; default: 0;
+         *  1: JTAG in fifo is full.
+         */
+        uint32_t in_fifo_full:1;
+        /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
+         *  JTAT out fifo counter.
+         */
+        uint32_t out_fifo_cnt:2;
+        /** out_fifo_empty : RO; bitpos: [6]; default: 1;
+         *  1: JTAG out fifo is empty.
+         */
+        uint32_t out_fifo_empty:1;
+        /** out_fifo_full : RO; bitpos: [7]; default: 0;
+         *  1: JTAG out fifo is full.
+         */
+        uint32_t out_fifo_full:1;
+        /** in_fifo_reset : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to reset JTAG in fifo.
+         */
+        uint32_t in_fifo_reset:1;
+        /** out_fifo_reset : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to reset JTAG out fifo.
+         */
+        uint32_t out_fifo_reset:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} usb_serial_jtag_jfifo_st_reg_t;
+
+/** Type of fram_num register
+ *  Last received SOF frame index register.
+ */
+typedef union {
+    struct {
+        /** sof_frame_index : RO; bitpos: [10:0]; default: 0;
+         *  Frame index of received SOF frame.
+         */
+        uint32_t sof_frame_index:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} usb_serial_jtag_fram_num_reg_t;
+
+/** Type of in_ep0_st register
+ *  Control IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep0_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 0.
+         */
+        uint32_t in_ep0_state:2;
+        /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_wr_addr:7;
+        /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep0_st_reg_t;
+
+/** Type of in_ep1_st register
+ *  CDC-ACM IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep1_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 1.
+         */
+        uint32_t in_ep1_state:2;
+        /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_wr_addr:7;
+        /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep1_st_reg_t;
+
+/** Type of in_ep2_st register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep2_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 2.
+         */
+        uint32_t in_ep2_state:2;
+        /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_wr_addr:7;
+        /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep2_st_reg_t;
+
+/** Type of in_ep3_st register
+ *  JTAG IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep3_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 3.
+         */
+        uint32_t in_ep3_state:2;
+        /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_wr_addr:7;
+        /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep3_st_reg_t;
+
+/** Type of out_ep0_st register
+ *  Control OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep0_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 0.
+         */
+        uint32_t out_ep0_state:2;
+        /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+         */
+        uint32_t out_ep0_wr_addr:7;
+        /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 0.
+         */
+        uint32_t out_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep0_st_reg_t;
+
+/** Type of out_ep1_st register
+ *  CDC-ACM OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep1_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 1.
+         */
+        uint32_t out_ep1_state:2;
+        /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+         */
+        uint32_t out_ep1_wr_addr:7;
+        /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 1.
+         */
+        uint32_t out_ep1_rd_addr:7;
+        /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
+         *  Data count in OUT endpoint 1 when one packet is received.
+         */
+        uint32_t out_ep1_rec_data_cnt:7;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep1_st_reg_t;
+
+/** Type of out_ep2_st register
+ *  JTAG OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep2_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 2.
+         */
+        uint32_t out_ep2_state:2;
+        /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+         */
+        uint32_t out_ep2_wr_addr:7;
+        /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 2.
+         */
+        uint32_t out_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep2_st_reg_t;
+
+/** Type of set_line_code_w0 register
+ *  W0 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by host through SET_LINE_CODING command.
+         */
+        uint32_t dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w0_reg_t;
+
+/** Type of set_line_code_w1 register
+ *  W1 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** bchar_format : RO; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by host through SET_LINE_CODING command.
+         */
+        uint32_t bchar_format:8;
+        /** bparity_type : RO; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by host through SET_LINE_CODING command.
+         */
+        uint32_t bparity_type:8;
+        /** bdata_bits : RO; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by host through SET_LINE_CODING command.
+         */
+        uint32_t bdata_bits:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w1_reg_t;
+
+/** Type of bus_reset_st register
+ *  USB Bus reset status register
+ */
+typedef union {
+    struct {
+        /** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
+         *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+         *  reset is released.
+         */
+        uint32_t usb_bus_reset_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_bus_reset_st_reg_t;
+
+/** Type of eco_cell_ctrl_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rdn_result_48 : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_result_48:1;
+        /** rdn_ena_48 : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_ena_48:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_cell_ctrl_48_reg_t;
+
+/** Type of eco_cell_ctrl_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rdn_result_apb : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_result_apb:1;
+        /** rdn_ena_apb : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_ena_apb:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_cell_ctrl_apb_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Date register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 34676752;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_date_reg_t;
+
+
+typedef struct {
+    volatile usb_serial_jtag_ep1_reg_t ep1;
+    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
+    volatile usb_serial_jtag_int_raw_reg_t int_raw;
+    volatile usb_serial_jtag_int_st_reg_t int_st;
+    volatile usb_serial_jtag_int_ena_reg_t int_ena;
+    volatile usb_serial_jtag_int_clr_reg_t int_clr;
+    volatile usb_serial_jtag_conf0_reg_t conf0;
+    volatile usb_serial_jtag_test_reg_t test;
+    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
+    volatile usb_serial_jtag_fram_num_reg_t fram_num;
+    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
+    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
+    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
+    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
+    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
+    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
+    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
+    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
+    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
+    volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
+    volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
+    volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
+    volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
+    volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
+    volatile usb_serial_jtag_config_update_reg_t config_update;
+    volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
+    volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
+    volatile usb_serial_jtag_eco_low_48_reg_t eco_low_48;
+    volatile usb_serial_jtag_eco_high_48_reg_t eco_high_48;
+    volatile usb_serial_jtag_eco_cell_ctrl_48_reg_t eco_cell_ctrl_48;
+    volatile usb_serial_jtag_eco_low_apb_reg_t eco_low_apb;
+    volatile usb_serial_jtag_eco_high_apb_reg_t eco_high_apb;
+    volatile usb_serial_jtag_eco_cell_ctrl_apb_reg_t eco_cell_ctrl_apb;
+    volatile usb_serial_jtag_sram_ctrl_reg_t sram_ctrl;
+    volatile usb_serial_jtag_date_reg_t date;
+} usb_serial_jtag_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h
new file mode 100644
index 0000000000..478c734ea8
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,1282 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+ *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
+ *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
+ *  received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
+ *  Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
+/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
+#define USB_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_S  0
+/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
+#define USB_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_S  1
+/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
+/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
+/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
+/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
+/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
+/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
+/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_SERIAL_JTAG_ECO_LOW_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
+/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M  (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S)
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S  0
+
+/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
+/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S)
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S  0
+
+/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74)
+/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_RESULT_48    (BIT(0))
+#define USB_SERIAL_JTAG_RDN_RESULT_48_M  (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S)
+#define USB_SERIAL_JTAG_RDN_RESULT_48_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_RESULT_48_S  0
+/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_ENA_48    (BIT(1))
+#define USB_SERIAL_JTAG_RDN_ENA_48_M  (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S)
+#define USB_SERIAL_JTAG_RDN_ENA_48_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_ENA_48_S  1
+
+/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78)
+/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M  (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S)
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S  0
+
+/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c)
+/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S)
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S  0
+
+/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_RESULT_APB    (BIT(0))
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_M  (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S)
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_S  0
+/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_ENA_APB    (BIT(1))
+#define USB_SERIAL_JTAG_RDN_ENA_APB_M  (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S)
+#define USB_SERIAL_JTAG_RDN_ENA_APB_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_ENA_APB_S  1
+
+/** USB_SERIAL_JTAG_SRAM_CTRL_REG register
+ *  PPA SRAM Control Register
+ */
+#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84)
+/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  Control signals
+ */
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL    0x00003FFFU
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M  (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S)
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V  0x00003FFFU
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S  0
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h
new file mode 100644
index 0000000000..ed400ae548
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h
@@ -0,0 +1,1044 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of ep1 register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+typedef union {
+    struct {
+        /** rdwr_byte : RO; bitpos: [7:0]; default: 0;
+         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+         *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+         *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
+         *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
+         *  received, then read data from UART Rx FIFO.
+         */
+        uint32_t rdwr_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_reg_t;
+
+/** Type of ep1_conf register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+typedef union {
+    struct {
+        /** wr_done : WT; bitpos: [0]; default: 0;
+         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+         */
+        uint32_t wr_done:1;
+        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
+         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+         *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
+         *  Host.
+         */
+        uint32_t serial_in_ep_data_free:1;
+        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
+         *  1'b1: Indicate there is data in UART Rx FIFO.
+         */
+        uint32_t serial_out_ep_data_avail:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_conf_reg_t;
+
+/** Type of conf0 register
+ *  PHY hardware configuration.
+ */
+typedef union {
+    struct {
+        /** phy_sel : R/W; bitpos: [0]; default: 0;
+         *  Select internal/external PHY
+         */
+        uint32_t phy_sel:1;
+        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
+         *  Enable software control USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [2]; default: 0;
+         *  USB D+ D- exchange
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [4:3]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [6:5]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [7]; default: 0;
+         *  Enable software control input  threshold
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
+         *  Enable software control USB D+ D- pullup pulldown
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [9]; default: 1;
+         *  Control USB D+ pull up.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
+         *  Control USB D+ pull down.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [11]; default: 0;
+         *  Control USB D- pull up.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
+         *  Control USB D- pull down.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [13]; default: 0;
+         *  Control pull up value.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
+         *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+         *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+         *  through GPIO Matrix.
+         */
+        uint32_t usb_jtag_bridge_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_conf0_reg_t;
+
+/** Type of test register
+ *  Registers used for debugging the PHY.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable test of the USB pad
+         */
+        uint32_t test_enable:1;
+        /** test_usb_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test
+         */
+        uint32_t test_usb_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 1;
+         *  USB RCV value in test
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 1;
+         *  USB D+ rx value in test
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_serial_jtag_test_reg_t;
+
+/** Type of misc_conf register
+ *  Clock enable control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_misc_conf_reg_t;
+
+/** Type of mem_conf register
+ *  Memory power control
+ */
+typedef union {
+    struct {
+        /** usb_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  1: power down usb memory.
+         */
+        uint32_t usb_mem_pd:1;
+        /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
+         *  1: Force clock on for usb memory.
+         */
+        uint32_t usb_mem_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_mem_conf_reg_t;
+
+/** Type of chip_rst register
+ *  CDC-ACM chip reset control.
+ */
+typedef union {
+    struct {
+        /** rts : RO; bitpos: [0]; default: 0;
+         *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+         */
+        uint32_t rts:1;
+        /** dtr : RO; bitpos: [1]; default: 0;
+         *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+         */
+        uint32_t dtr:1;
+        /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to disable chip reset from usb serial channel to reset chip.
+         */
+        uint32_t usb_uart_chip_rst_dis:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_chip_rst_reg_t;
+
+/** Type of get_line_code_w0 register
+ *  W0 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w0_reg_t;
+
+/** Type of get_line_code_w1 register
+ *  W1 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bdata_bits:8;
+        /** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bparity_type:8;
+        /** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bchar_format:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w1_reg_t;
+
+/** Type of config_update register
+ *  Configuration registers' value update
+ */
+typedef union {
+    struct {
+        /** config_update : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this register would update the value of configure registers from APB
+         *  clock domain to 48MHz clock domain.
+         */
+        uint32_t config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_config_update_reg_t;
+
+/** Type of ser_afifo_config register
+ *  Serial AFIFO configure register
+ */
+typedef union {
+    struct {
+        /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+         */
+        uint32_t serial_in_afifo_reset_wr:1;
+        /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+         */
+        uint32_t serial_in_afifo_reset_rd:1;
+        /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+         */
+        uint32_t serial_out_afifo_reset_wr:1;
+        /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+         */
+        uint32_t serial_out_afifo_reset_rd:1;
+        /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
+         *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+         */
+        uint32_t serial_out_afifo_rempty:1;
+        /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
+         *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+         */
+        uint32_t serial_in_afifo_wfull:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} usb_serial_jtag_ser_afifo_config_reg_t;
+
+/** Type of eco_low_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low_48 : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_low_48:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_low_48_reg_t;
+
+/** Type of eco_high_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high_48 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_high_48:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_high_48_reg_t;
+
+/** Type of eco_low_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low_apb : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_low_apb:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_low_apb_reg_t;
+
+/** Type of eco_high_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high_apb : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_high_apb:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_high_apb_reg_t;
+
+/** Type of sram_ctrl register
+ *  PPA SRAM Control Register
+ */
+typedef union {
+    struct {
+        /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  Control signals
+         */
+        uint32_t mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} usb_serial_jtag_sram_ctrl_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Interrupt raw status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when flush cmd is received for IN
+         *  endpoint 2 of JTAG.
+         */
+        uint32_t jtag_in_flush_int_raw:1;
+        /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when SOF frame is received.
+         */
+        uint32_t sof_int_raw:1;
+        /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+         *  one packet.
+         */
+        uint32_t serial_out_recv_pkt_int_raw:1;
+        /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
+         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+         */
+        uint32_t serial_in_empty_int_raw:1;
+        /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when pid error is detected.
+         */
+        uint32_t pid_err_int_raw:1;
+        /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC5 error is detected.
+         */
+        uint32_t crc5_err_int_raw:1;
+        /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC16 error is detected.
+         */
+        uint32_t crc16_err_int_raw:1;
+        /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when stuff error is detected.
+         */
+        uint32_t stuff_err_int_raw:1;
+        /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+         *  received.
+         */
+        uint32_t in_token_rec_in_ep1_int_raw:1;
+        /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when usb bus reset is detected.
+         */
+        uint32_t usb_bus_reset_int_raw:1;
+        /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep1_zero_payload_int_raw:1;
+        /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep2_zero_payload_int_raw:1;
+        /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+         *  is changed.
+         */
+        uint32_t rts_chg_int_raw:1;
+        /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+         *  is changed.
+         */
+        uint32_t dtr_chg_int_raw:1;
+        /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+         *  received.
+         */
+        uint32_t get_line_code_int_raw:1;
+        /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+         *  received.
+         */
+        uint32_t set_line_code_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_st:1;
+        /** sof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+         */
+        uint32_t sof_int_st:1;
+        /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_st:1;
+        /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_st:1;
+        /** pid_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_st:1;
+        /** crc5_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_st:1;
+        /** crc16_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_st:1;
+        /** stuff_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_st:1;
+        /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_st:1;
+        /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_st:1;
+        /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_st:1;
+        /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_st:1;
+        /** rts_chg_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_st:1;
+        /** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_st:1;
+        /** get_line_code_int_st : RO; bitpos: [14]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_st:1;
+        /** set_line_code_int_st : RO; bitpos: [15]; default: 0;
+         *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_ena:1;
+        /** sof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+         */
+        uint32_t sof_int_ena:1;
+        /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_ena:1;
+        /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_ena:1;
+        /** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_ena:1;
+        /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_ena:1;
+        /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_ena:1;
+        /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_ena:1;
+        /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_ena:1;
+        /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_ena:1;
+        /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_ena:1;
+        /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_ena:1;
+        /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_ena:1;
+        /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_ena:1;
+        /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_ena:1;
+        /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_clr:1;
+        /** sof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_clr:1;
+        /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_clr:1;
+        /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_clr:1;
+        /** pid_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_clr:1;
+        /** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_clr:1;
+        /** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_clr:1;
+        /** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_clr:1;
+        /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_clr:1;
+        /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_clr:1;
+        /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_clr:1;
+        /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_clr:1;
+        /** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_clr:1;
+        /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_clr:1;
+        /** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_clr:1;
+        /** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of jfifo_st register
+ *  JTAG FIFO status and control registers.
+ */
+typedef union {
+    struct {
+        /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
+         *  JTAT in fifo counter.
+         */
+        uint32_t in_fifo_cnt:2;
+        /** in_fifo_empty : RO; bitpos: [2]; default: 1;
+         *  1: JTAG in fifo is empty.
+         */
+        uint32_t in_fifo_empty:1;
+        /** in_fifo_full : RO; bitpos: [3]; default: 0;
+         *  1: JTAG in fifo is full.
+         */
+        uint32_t in_fifo_full:1;
+        /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
+         *  JTAT out fifo counter.
+         */
+        uint32_t out_fifo_cnt:2;
+        /** out_fifo_empty : RO; bitpos: [6]; default: 1;
+         *  1: JTAG out fifo is empty.
+         */
+        uint32_t out_fifo_empty:1;
+        /** out_fifo_full : RO; bitpos: [7]; default: 0;
+         *  1: JTAG out fifo is full.
+         */
+        uint32_t out_fifo_full:1;
+        /** in_fifo_reset : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to reset JTAG in fifo.
+         */
+        uint32_t in_fifo_reset:1;
+        /** out_fifo_reset : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to reset JTAG out fifo.
+         */
+        uint32_t out_fifo_reset:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} usb_serial_jtag_jfifo_st_reg_t;
+
+/** Type of fram_num register
+ *  Last received SOF frame index register.
+ */
+typedef union {
+    struct {
+        /** sof_frame_index : RO; bitpos: [10:0]; default: 0;
+         *  Frame index of received SOF frame.
+         */
+        uint32_t sof_frame_index:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} usb_serial_jtag_fram_num_reg_t;
+
+/** Type of in_ep0_st register
+ *  Control IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep0_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 0.
+         */
+        uint32_t in_ep0_state:2;
+        /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_wr_addr:7;
+        /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep0_st_reg_t;
+
+/** Type of in_ep1_st register
+ *  CDC-ACM IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep1_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 1.
+         */
+        uint32_t in_ep1_state:2;
+        /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_wr_addr:7;
+        /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep1_st_reg_t;
+
+/** Type of in_ep2_st register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep2_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 2.
+         */
+        uint32_t in_ep2_state:2;
+        /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_wr_addr:7;
+        /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep2_st_reg_t;
+
+/** Type of in_ep3_st register
+ *  JTAG IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep3_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 3.
+         */
+        uint32_t in_ep3_state:2;
+        /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_wr_addr:7;
+        /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep3_st_reg_t;
+
+/** Type of out_ep0_st register
+ *  Control OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep0_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 0.
+         */
+        uint32_t out_ep0_state:2;
+        /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+         */
+        uint32_t out_ep0_wr_addr:7;
+        /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 0.
+         */
+        uint32_t out_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep0_st_reg_t;
+
+/** Type of out_ep1_st register
+ *  CDC-ACM OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep1_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 1.
+         */
+        uint32_t out_ep1_state:2;
+        /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+         */
+        uint32_t out_ep1_wr_addr:7;
+        /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 1.
+         */
+        uint32_t out_ep1_rd_addr:7;
+        /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
+         *  Data count in OUT endpoint 1 when one packet is received.
+         */
+        uint32_t out_ep1_rec_data_cnt:7;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep1_st_reg_t;
+
+/** Type of out_ep2_st register
+ *  JTAG OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep2_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 2.
+         */
+        uint32_t out_ep2_state:2;
+        /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+         */
+        uint32_t out_ep2_wr_addr:7;
+        /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 2.
+         */
+        uint32_t out_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep2_st_reg_t;
+
+/** Type of set_line_code_w0 register
+ *  W0 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by host through SET_LINE_CODING command.
+         */
+        uint32_t dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w0_reg_t;
+
+/** Type of set_line_code_w1 register
+ *  W1 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** bchar_format : RO; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by host through SET_LINE_CODING command.
+         */
+        uint32_t bchar_format:8;
+        /** bparity_type : RO; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by host through SET_LINE_CODING command.
+         */
+        uint32_t bparity_type:8;
+        /** bdata_bits : RO; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by host through SET_LINE_CODING command.
+         */
+        uint32_t bdata_bits:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w1_reg_t;
+
+/** Type of bus_reset_st register
+ *  USB Bus reset status register
+ */
+typedef union {
+    struct {
+        /** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
+         *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+         *  reset is released.
+         */
+        uint32_t usb_bus_reset_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_bus_reset_st_reg_t;
+
+/** Type of eco_cell_ctrl_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rdn_result_48 : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_result_48:1;
+        /** rdn_ena_48 : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_ena_48:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_cell_ctrl_48_reg_t;
+
+/** Type of eco_cell_ctrl_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rdn_result_apb : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_result_apb:1;
+        /** rdn_ena_apb : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_ena_apb:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_cell_ctrl_apb_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Date register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 34676752;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_date_reg_t;
+
+
+typedef struct {
+    volatile usb_serial_jtag_ep1_reg_t ep1;
+    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
+    volatile usb_serial_jtag_int_raw_reg_t int_raw;
+    volatile usb_serial_jtag_int_st_reg_t int_st;
+    volatile usb_serial_jtag_int_ena_reg_t int_ena;
+    volatile usb_serial_jtag_int_clr_reg_t int_clr;
+    volatile usb_serial_jtag_conf0_reg_t conf0;
+    volatile usb_serial_jtag_test_reg_t test;
+    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
+    volatile usb_serial_jtag_fram_num_reg_t fram_num;
+    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
+    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
+    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
+    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
+    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
+    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
+    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
+    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
+    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
+    volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
+    volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
+    volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
+    volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
+    volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
+    volatile usb_serial_jtag_config_update_reg_t config_update;
+    volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
+    volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
+    volatile usb_serial_jtag_eco_low_48_reg_t eco_low_48;
+    volatile usb_serial_jtag_eco_high_48_reg_t eco_high_48;
+    volatile usb_serial_jtag_eco_cell_ctrl_48_reg_t eco_cell_ctrl_48;
+    volatile usb_serial_jtag_eco_low_apb_reg_t eco_low_apb;
+    volatile usb_serial_jtag_eco_high_apb_reg_t eco_high_apb;
+    volatile usb_serial_jtag_eco_cell_ctrl_apb_reg_t eco_cell_ctrl_apb;
+    volatile usb_serial_jtag_sram_ctrl_reg_t sram_ctrl;
+    volatile usb_serial_jtag_date_reg_t date;
+} usb_serial_jtag_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/usbwrap_reg.h b/components/soc/esp32p4/include/soc/usbwrap_reg.h
new file mode 100644
index 0000000000..68e7c5852b
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/usbwrap_reg.h
@@ -0,0 +1,182 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_WRAP_OTG_CONF_REG register
+ *  USB wrapper configuration registers.
+ */
+#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
+/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+ *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+ *  software.
+ */
+#define USB_WRAP_SRP_SESSEND_OVERRIDE    (BIT(0))
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_M  (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_V  0x00000001U
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_S  0
+/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
+ *  Software over-ride value of srp session end signal.
+ */
+#define USB_WRAP_SRP_SESSEND_VALUE    (BIT(1))
+#define USB_WRAP_SRP_SESSEND_VALUE_M  (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
+#define USB_WRAP_SRP_SESSEND_VALUE_V  0x00000001U
+#define USB_WRAP_SRP_SESSEND_VALUE_S  1
+/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
+ *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+ */
+#define USB_WRAP_PHY_SEL    (BIT(2))
+#define USB_WRAP_PHY_SEL_M  (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
+#define USB_WRAP_PHY_SEL_V  0x00000001U
+#define USB_WRAP_PHY_SEL_S  2
+/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0;
+ *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+ */
+#define USB_WRAP_DFIFO_FORCE_PD    (BIT(3))
+#define USB_WRAP_DFIFO_FORCE_PD_M  (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S)
+#define USB_WRAP_DFIFO_FORCE_PD_V  0x00000001U
+#define USB_WRAP_DFIFO_FORCE_PD_S  3
+/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
+ *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+ */
+#define USB_WRAP_DBNCE_FLTR_BYPASS    (BIT(4))
+#define USB_WRAP_DBNCE_FLTR_BYPASS_M  (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
+#define USB_WRAP_DBNCE_FLTR_BYPASS_V  0x00000001U
+#define USB_WRAP_DBNCE_FLTR_BYPASS_S  4
+/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
+ *  Enable software controlle USB D+ D- exchange
+ */
+#define USB_WRAP_EXCHG_PINS_OVERRIDE    (BIT(5))
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_M  (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_S  5
+/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
+ *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+ */
+#define USB_WRAP_EXCHG_PINS    (BIT(6))
+#define USB_WRAP_EXCHG_PINS_M  (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
+#define USB_WRAP_EXCHG_PINS_V  0x00000001U
+#define USB_WRAP_EXCHG_PINS_S  6
+/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+ */
+#define USB_WRAP_VREFH    0x00000003U
+#define USB_WRAP_VREFH_M  (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
+#define USB_WRAP_VREFH_V  0x00000003U
+#define USB_WRAP_VREFH_S  7
+/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+ */
+#define USB_WRAP_VREFL    0x00000003U
+#define USB_WRAP_VREFL_M  (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
+#define USB_WRAP_VREFL_V  0x00000003U
+#define USB_WRAP_VREFL_S  9
+/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
+ *  Enable software controlle input  threshold.
+ */
+#define USB_WRAP_VREF_OVERRIDE    (BIT(11))
+#define USB_WRAP_VREF_OVERRIDE_M  (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
+#define USB_WRAP_VREF_OVERRIDE_V  0x00000001U
+#define USB_WRAP_VREF_OVERRIDE_S  11
+/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
+ *  Enable software controlle USB D+ D- pullup pulldown.
+ */
+#define USB_WRAP_PAD_PULL_OVERRIDE    (BIT(12))
+#define USB_WRAP_PAD_PULL_OVERRIDE_M  (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
+#define USB_WRAP_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_WRAP_PAD_PULL_OVERRIDE_S  12
+/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
+ *  Controlle USB D+ pullup.
+ */
+#define USB_WRAP_DP_PULLUP    (BIT(13))
+#define USB_WRAP_DP_PULLUP_M  (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
+#define USB_WRAP_DP_PULLUP_V  0x00000001U
+#define USB_WRAP_DP_PULLUP_S  13
+/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
+ *  Controlle USB D+ pulldown.
+ */
+#define USB_WRAP_DP_PULLDOWN    (BIT(14))
+#define USB_WRAP_DP_PULLDOWN_M  (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
+#define USB_WRAP_DP_PULLDOWN_V  0x00000001U
+#define USB_WRAP_DP_PULLDOWN_S  14
+/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
+ *  Controlle USB D+ pullup.
+ */
+#define USB_WRAP_DM_PULLUP    (BIT(15))
+#define USB_WRAP_DM_PULLUP_M  (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
+#define USB_WRAP_DM_PULLUP_V  0x00000001U
+#define USB_WRAP_DM_PULLUP_S  15
+/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
+ *  Controlle USB D+ pulldown.
+ */
+#define USB_WRAP_DM_PULLDOWN    (BIT(16))
+#define USB_WRAP_DM_PULLDOWN_M  (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
+#define USB_WRAP_DM_PULLDOWN_V  0x00000001U
+#define USB_WRAP_DM_PULLDOWN_S  16
+/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
+ *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+ */
+#define USB_WRAP_PULLUP_VALUE    (BIT(17))
+#define USB_WRAP_PULLUP_VALUE_M  (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
+#define USB_WRAP_PULLUP_VALUE_V  0x00000001U
+#define USB_WRAP_PULLUP_VALUE_S  17
+/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
+ *  Enable USB pad function.
+ */
+#define USB_WRAP_USB_PAD_ENABLE    (BIT(18))
+#define USB_WRAP_USB_PAD_ENABLE_M  (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S)
+#define USB_WRAP_USB_PAD_ENABLE_V  0x00000001U
+#define USB_WRAP_USB_PAD_ENABLE_S  18
+/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0;
+ *  Force ahb clock always on.
+ */
+#define USB_WRAP_AHB_CLK_FORCE_ON    (BIT(19))
+#define USB_WRAP_AHB_CLK_FORCE_ON_M  (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
+#define USB_WRAP_AHB_CLK_FORCE_ON_V  0x00000001U
+#define USB_WRAP_AHB_CLK_FORCE_ON_S  19
+/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  Force phy clock always on.
+ */
+#define USB_WRAP_PHY_CLK_FORCE_ON    (BIT(20))
+#define USB_WRAP_PHY_CLK_FORCE_ON_M  (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
+#define USB_WRAP_PHY_CLK_FORCE_ON_V  0x00000001U
+#define USB_WRAP_PHY_CLK_FORCE_ON_S  20
+/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0;
+ *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+ */
+#define USB_WRAP_DFIFO_FORCE_PU    (BIT(22))
+#define USB_WRAP_DFIFO_FORCE_PU_M  (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S)
+#define USB_WRAP_DFIFO_FORCE_PU_V  0x00000001U
+#define USB_WRAP_DFIFO_FORCE_PU_S  22
+/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Disable auto clock gating of CSR registers.
+ */
+#define USB_WRAP_CLK_EN    (BIT(31))
+#define USB_WRAP_CLK_EN_M  (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
+#define USB_WRAP_CLK_EN_V  0x00000001U
+#define USB_WRAP_CLK_EN_S  31
+
+/** USB_WRAP_DATE_REG register
+ *  Date register.
+ */
+#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc)
+/** USB_WRAP_USB_WRAP_DATE : HRO; bitpos: [31:0]; default: 587400452;
+ *  Date register.
+ */
+#define USB_WRAP_USB_WRAP_DATE    0xFFFFFFFFU
+#define USB_WRAP_USB_WRAP_DATE_M  (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S)
+#define USB_WRAP_USB_WRAP_DATE_V  0xFFFFFFFFU
+#define USB_WRAP_USB_WRAP_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/usbwrap_struct.h b/components/soc/esp32p4/include/soc/usbwrap_struct.h
new file mode 100644
index 0000000000..d99347df55
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/usbwrap_struct.h
@@ -0,0 +1,138 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: USB wrapper registers. */
+/** Type of otg_conf register
+ *  USB wrapper configuration registers.
+ */
+typedef union {
+    struct {
+        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+         *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+         *  software.
+         */
+        uint32_t srp_sessend_override:1;
+        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
+         *  Software over-ride value of srp session end signal.
+         */
+        uint32_t srp_sessend_value:1;
+        /** phy_sel : R/W; bitpos: [2]; default: 0;
+         *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+         */
+        uint32_t phy_sel:1;
+        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pd:1;
+        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
+         *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+         */
+        uint32_t dbnce_fltr_bypass:1;
+        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
+         *  Enable software controlle USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [6]; default: 0;
+         *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [8:7]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [10:9]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [11]; default: 0;
+         *  Enable software controlle input  threshold.
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
+         *  Enable software controlle USB D+ D- pullup pulldown.
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [13]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [15]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [17]; default: 0;
+         *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [18]; default: 0;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
+         *  Force ahb clock always on.
+         */
+        uint32_t ahb_clk_force_on:1;
+        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
+         *  Force phy clock always on.
+         */
+        uint32_t phy_clk_force_on:1;
+        uint32_t reserved_21:1;
+        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
+         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pu:1;
+        uint32_t reserved_23:8;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Disable auto clock gating of CSR registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} usb_wrap_otg_conf_reg_t;
+
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
+         *  Date register.
+         */
+        uint32_t usb_wrap_date:32;
+    };
+    uint32_t val;
+} usb_wrap_date_reg_t;
+
+
+typedef struct {
+    volatile usb_wrap_otg_conf_reg_t otg_conf;
+    uint32_t reserved_004[254];
+    volatile usb_wrap_date_reg_t date;
+} usb_wrap_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/interrupts.c b/components/soc/esp32p4/interrupts.c
index e69de29bb2..48f79a467c 100644
--- a/components/soc/esp32p4/interrupts.c
+++ b/components/soc/esp32p4/interrupts.c
@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/interrupts.h"
+
+const char *const esp_isr_names[] = {
+    [0] = "WIFI_MAC",
+    [1] = "WIFI_MAC_NMI",
+    [2] = "WIFI_PWR",
+    [3] = "WIFI_BB",
+    [4] = "BT_MAC",
+    [5] = "BT_BB",
+    [6] = "BT_BB_NMI",
+    [7] = "LP_TIMER",
+    [8] = "COEX",
+    [9] = "BLE_TIMER",
+    [10] = "BLE_SEC",
+    [11] = "I2C_MASTER",
+    [12] = "ZB_MAC",
+    [13] = "PMU",
+    [14] = "EFUSE",
+    [15] = "LP_RTC_TIMER",
+    [16] = "LP_UART",
+    [17] = "LP_I2C",
+    [18] = "LP_WDT",
+    [19] = "LP_PERI_TIMEOUT",
+    [20] = "LP_APM_M0",
+    [21] = "LP_APM_M1",
+    [22] = "CPU_FROM_CPU_0",
+    [23] = "CPU_FROM_CPU_1",
+    [24] = "CPU_FROM_CPU_2",
+    [25] = "CPU_FROM_CPU_3",
+    [26] = "ASSIST_DEBUG",
+    [27] = "TRACE",
+    [28] = "CACHE",
+    [29] = "CPU_PERI_TIMEOUT",
+    [30] = "GPIO_INTERRUPT_PRO",
+    [31] = "GPIO_INTERRUPT_PRO_NMI",
+    [32] = "PAU",
+    [33] = "HP_PERI_TIMEOUT",
+    [34] = "MODEM_PERI_TIMEOUT",
+    [35] = "HP_APM_M0",
+    [36] = "HP_APM_M1",
+    [37] = "HP_APM_M2",
+    [38] = "HP_APM_M3",
+    [39] = "LP_APM0",
+    [40] = "MSPI",
+    [41] = "I2S1",
+    [42] = "UHCI0",
+    [43] = "UART0",
+    [44] = "UART1",
+    [45] = "LEDC",
+    [46] = "CAN0",
+    [47] = "CAN1",
+    [48] = "USB",
+    [49] = "RMT",
+    [50] = "I2C_EXT0",
+    [51] = "TG0_T0",
+    [52] = "TG0_T1",
+    [53] = "TG0_WDT",
+    [54] = "TG1_T0",
+    [55] = "TG1_T1",
+    [56] = "TG1_WDT",
+    [57] = "SYSTIMER_TARGET0",
+    [58] = "SYSTIMER_TARGET1",
+    [59] = "SYSTIMER_TARGET2",
+    [60] = "APB_ADC",
+    [61] = "PWM",
+    [62] = "PCNT",
+    [63] = "PARL_IO",
+    [64] = "SLC0",
+    [65] = "SLC1",
+    [66] = "DMA_IN_CH0",
+    [67] = "DMA_IN_CH1",
+    [68] = "DMA_IN_CH2",
+    [69] = "DMA_OUT_CH0",
+    [70] = "DMA_OUT_CH1",
+    [71] = "DMA_OUT_CH2",
+    [72] = "GPSPI2",
+    [73] = "AES",
+    [74] = "SHA",
+    [75] = "RSA",
+    [76] = "ECC",
+};
diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
new file mode 100644
index 0000000000..64aaa0c3e6
--- /dev/null
+++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
@@ -0,0 +1,94 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+PROVIDE ( UART0             = 0x500CA000 );
+PROVIDE ( UART1             = 0x500CB000 );
+PROVIDE ( UART2             = 0x500CC000 );
+PROVIDE ( UART3             = 0x500CD000 );
+PROVIDE ( UART4             = 0x500CE000 );
+PROVIDE ( SPIMEM0           = 0x5008C000 );
+PROVIDE ( SPIMEM1           = 0x5008D000 );
+PROVIDE ( I2C0              = 0x500C4000 );
+PROVIDE ( I2C1              = 0x500C5000 );
+PROVIDE ( UHCI0             = 0x500DF000 );
+PROVIDE ( RMT               = 0x500D4000 );
+PROVIDE ( RMTMEM            = 0x500D4800 );
+PROVIDE ( LEDC              = 0x500D3000 );
+PROVIDE ( TIMERG0           = 0x500C2000 );
+PROVIDE ( TIMERG1           = 0x500C3000 );
+PROVIDE ( SYSTIMER          = 0x500E2000 );
+PROVIDE ( TWAI0             = 0x500D7000 );
+PROVIDE ( I2S0              = 0x500C6000 );
+PROVIDE ( I2S1              = 0x500C7000 );
+PROVIDE ( I2S2              = 0x500C8000 );
+PROVIDE ( TWAI1             = 0x500D8000 );
+PROVIDE ( TWAI2             = 0x500D9000 );
+PROVIDE ( APB_SARADC        = 0x6000E000 ); /* need remove */
+PROVIDE ( USB_SERIAL_JTAG   = 0x500D2000 );
+PROVIDE ( SDMMC             = 0x50083000 );
+
+PROVIDE ( INTMTX        = 0x500D6000 );
+PROVIDE ( ATOMIC_LOCKER = 0x60011000 ); /* need remove */
+PROVIDE ( PCNT          = 0x500C9000 );
+PROVIDE ( SOC_ETM       = 0x500D5000 );
+PROVIDE ( MCPWM0        = 0x500C0000 );
+PROVIDE ( MCPWM1        = 0x500C1000 );
+PROVIDE ( PARL_IO       = 0x500CF000 );
+PROVIDE ( PVT_MONITOR   = 0x5009E000 );
+
+PROVIDE ( GDMA      = 0x50081000 );
+PROVIDE ( GPSPI2    = 0x500D0000 );
+
+PROVIDE ( AES       = 0x50090000 );
+PROVIDE ( SHA       = 0x50091000 );
+PROVIDE ( RSA       = 0x50092000 );
+PROVIDE ( ECC       = 0x50093000 );
+PROVIDE ( DS        = 0x50094000 );
+PROVIDE ( HMAC      = 0x50095000 );
+PROVIDE ( ECDSA     = 0x50096000 );
+
+PROVIDE ( IO_MUX         = 0x500e1000 );
+PROVIDE ( IOMUX          = 0x500e1000 );
+PROVIDE ( GPIO           = 0x500E0000 );
+PROVIDE ( SIGMADELTA     = 0x500E0F00 );
+
+PROVIDE ( HP_SYSTEM         = 0x500E5000 );
+PROVIDE ( TEE               = 0x60098000 ); /* need update */
+PROVIDE ( HP_APM            = 0x60099000 ); /* need update */
+
+PROVIDE ( PMU           = 0x50115000 );
+PROVIDE ( LP_AON_CLKRST = 0x50111000 );
+PROVIDE ( EFUSE         = 0x5012D000 );
+PROVIDE ( LP_TIMER      = 0x50112000 );
+PROVIDE ( LP_UART       = 0x50121000 );
+PROVIDE ( LP_I2C        = 0x50122000 );
+PROVIDE ( LP_WDT        = 0x50116000 );
+PROVIDE ( LP_I2S        = 0x50125000 );
+PROVIDE ( LP_GPIO         = 0x5012A000 );
+PROVIDE ( LP_I2C_ANA_MST = 0x50124000 );
+PROVIDE ( LP_ANA_PERI   = 0x50113000 );
+PROVIDE ( LP_APM        = 0x600B3800 ); /* need update */
+PROVIDE ( AHB_DMA      =  0x50085000 );
+PROVIDE ( AXI_DMA      =  0x5008a000 );
+PROVIDE ( LCD_CAM      = 0x500dc000 );
+PROVIDE ( LP_IOMUX      = 0x5012B000 );
+
+PROVIDE ( MIPI_CSI_BRIDGE    = 0x5009F800 );
+PROVIDE ( MIPI_CSI_HOST      = 0x5009F000 );
+PROVIDE ( MIPI_DSI_BRIDGE    = 0x500A0800 );
+PROVIDE ( MIPI_DSI_HOST      = 0x500A0000 );
+PROVIDE ( MIPI_CSI_MEM       = 0x50104000 );
+PROVIDE ( MIPI_DSI_MEM       = 0x50105000 );
+PROVIDE ( ISP                = 0x500A1000 );
+PROVIDE ( GDMA               = 0x50081000 );
+PROVIDE ( I3C_MST            = 0x500DA000 );
+PROVIDE ( I3C_MST_MEM        = 0x500DA000 );
+PROVIDE ( I3C_SLV            = 0x500DB000 );
+
+PROVIDE ( PPA                = 0x50087000 );
+PROVIDE ( DMA2D              = 0x50088000 );
+PROVIDE ( JPEG               = 0x50086000 );
diff --git a/components/soc/esp32p4/ledc_periph.c b/components/soc/esp32p4/ledc_periph.c
new file mode 100644
index 0000000000..18e9d9a68d
--- /dev/null
+++ b/components/soc/esp32p4/ledc_periph.c
@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/ledc_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every LEDC peripheral: GPIO signals
+*/
+const ledc_signal_conn_t ledc_periph_signal[1] = {
+	{
+        .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
+	}
+};
diff --git a/components/soc/esp32p4/mcpwm_periph.c b/components/soc/esp32p4/mcpwm_periph.c
new file mode 100644
index 0000000000..6de1cfa631
--- /dev/null
+++ b/components/soc/esp32p4/mcpwm_periph.c
@@ -0,0 +1,83 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/soc.h"
+#include "soc/mcpwm_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const mcpwm_signal_conn_t mcpwm_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_MCPWM0_MODULE,
+            .irq_id = ETS_PWM0_INTR_SOURCE,
+            .operators = {
+                [0] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = 0
+                        },
+                        [1] = {
+                            .pwm_sig = 0
+                        }
+                    }
+                },
+                [1] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = 0
+                        },
+                        [1] = {
+                            .pwm_sig = 0
+                        }
+                    }
+                },
+                [2] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = 0
+                        },
+                        [1] = {
+                            .pwm_sig = 0
+                        }
+                    }
+                }
+            },
+            .gpio_faults = {
+                [0] = {
+                    .fault_sig = 0
+                },
+                [1] = {
+                    .fault_sig = 0
+                },
+                [2] = {
+                    .fault_sig = 0
+                }
+            },
+            .captures = {
+                [0] = {
+                    .cap_sig = 0
+                },
+                [1] = {
+                    .cap_sig = 0
+                },
+                [2] = {
+                    .cap_sig = 0
+                }
+            },
+            .gpio_synchros = {
+                [0] = {
+                    .sync_sig = 0
+                },
+                [1] = {
+                    .sync_sig = 0
+                },
+                [2] = {
+                    .sync_sig = 0
+                }
+            }
+        },
+    }
+};
diff --git a/components/soc/esp32p4/parlio_periph.c b/components/soc/esp32p4/parlio_periph.c
new file mode 100644
index 0000000000..40ac06320c
--- /dev/null
+++ b/components/soc/esp32p4/parlio_periph.c
@@ -0,0 +1,66 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/parlio_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const parlio_signal_conn_t parlio_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_PARLIO_MODULE,
+            .tx_irq_id = ETS_PARL_IO_INTR_SOURCE,
+            .rx_irq_id = ETS_PARL_IO_INTR_SOURCE,
+            .tx_units = {
+                [0] = {
+                    .data_sigs = {
+                        PARL_TX_DATA0_IDX,
+                        PARL_TX_DATA1_IDX,
+                        PARL_TX_DATA2_IDX,
+                        PARL_TX_DATA3_IDX,
+                        PARL_TX_DATA4_IDX,
+                        PARL_TX_DATA5_IDX,
+                        PARL_TX_DATA6_IDX,
+                        PARL_TX_DATA7_IDX,
+                        PARL_TX_DATA8_IDX,
+                        PARL_TX_DATA9_IDX,
+                        PARL_TX_DATA10_IDX,
+                        PARL_TX_DATA11_IDX,
+                        PARL_TX_DATA12_IDX,
+                        PARL_TX_DATA13_IDX,
+                        PARL_TX_DATA14_IDX,
+                        PARL_TX_DATA15_IDX,
+                    },
+                    .clk_out_sig = PARL_TX_CLK_OUT_IDX,
+                    .clk_in_sig = PARL_TX_CLK_IN_IDX,
+                }
+            },
+            .rx_units = {
+                [0] = {
+                    .data_sigs = {
+                        PARL_RX_DATA0_IDX,
+                        PARL_RX_DATA1_IDX,
+                        PARL_RX_DATA2_IDX,
+                        PARL_RX_DATA3_IDX,
+                        PARL_RX_DATA4_IDX,
+                        PARL_RX_DATA5_IDX,
+                        PARL_RX_DATA6_IDX,
+                        PARL_RX_DATA7_IDX,
+                        PARL_RX_DATA8_IDX,
+                        PARL_RX_DATA9_IDX,
+                        PARL_RX_DATA10_IDX,
+                        PARL_RX_DATA11_IDX,
+                        PARL_RX_DATA12_IDX,
+                        PARL_RX_DATA13_IDX,
+                        PARL_RX_DATA14_IDX,
+                        PARL_RX_DATA15_IDX,
+                    },
+                    .clk_out_sig = -1,
+                    .clk_in_sig = PARL_RX_CLK_IN_IDX,
+                }
+            }
+        },
+    },
+};
diff --git a/components/soc/esp32p4/pcnt_periph.c b/components/soc/esp32p4/pcnt_periph.c
new file mode 100644
index 0000000000..a3b2adaee2
--- /dev/null
+++ b/components/soc/esp32p4/pcnt_periph.c
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/pcnt_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const pcnt_signal_conn_t pcnt_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_PCNT_MODULE,
+            .irq = ETS_PCNT_INTR_SOURCE,
+            .units = {
+                [0] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        },
+                        [1] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        }
+                    }
+                },
+                [1] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        },
+                        [1] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        }
+                    }
+                },
+                [2] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        },
+                        [1] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        }
+                    }
+                },
+                [3] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        },
+                        [1] = {
+                            .control_sig = 0,
+                            .pulse_sig = 0
+                        }
+                    }
+                }
+            }
+        }
+    }
+};
diff --git a/components/soc/esp32p4/rmt_periph.c b/components/soc/esp32p4/rmt_periph.c
new file mode 100644
index 0000000000..06ed9e3b74
--- /dev/null
+++ b/components/soc/esp32p4/rmt_periph.c
@@ -0,0 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/rmt_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const rmt_signal_conn_t rmt_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_RMT_MODULE,
+            .irq = ETS_RMT_INTR_SOURCE,
+            .channels = {
+                [0] = {
+                    .tx_sig = RMT_SIG_PAD_OUT0_IDX,
+                    .rx_sig = -1
+                },
+                [1] = {
+                    .tx_sig = RMT_SIG_PAD_OUT1_IDX,
+                    .rx_sig = -1
+                },
+                [2] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_PAD_IN0_IDX
+                },
+                [3] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_PAD_IN1_IDX
+                },
+            }
+        }
+    }
+};
diff --git a/components/soc/esp32p4/rtc_io_periph.c b/components/soc/esp32p4/rtc_io_periph.c
new file mode 100644
index 0000000000..51befd2bae
--- /dev/null
+++ b/components/soc/esp32p4/rtc_io_periph.c
@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/rtc_periph.h"
+
+const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
+    RTCIO_GPIO0_CHANNEL,    //GPIO0
+    RTCIO_GPIO1_CHANNEL,    //GPIO1
+    RTCIO_GPIO2_CHANNEL,    //GPIO2
+    RTCIO_GPIO3_CHANNEL,    //GPIO3
+    RTCIO_GPIO4_CHANNEL,    //GPIO4
+    RTCIO_GPIO5_CHANNEL,    //GPIO5
+    RTCIO_GPIO6_CHANNEL,    //GPIO6
+    RTCIO_GPIO7_CHANNEL,    //GPIO7
+    -1,//GPIO8
+    -1,//GPIO9
+    -1,//GPIO10
+    -1,//GPIO11
+    -1,//GPIO12
+    -1,//GPIO13
+    -1,//GPIO14
+    -1,//GPIO15
+    -1,//GPIO16
+    -1,//GPIO17
+    -1,//GPIO18
+    -1,//GPIO19
+    -1,//GPIO20
+    -1,//GPIO21
+    -1,//GPIO22
+    -1,//GPIO23
+    -1,//GPIO24
+    -1,//GPIO25
+    -1,//GPIO26
+    -1,//GPIO27
+    -1,//GPIO28
+    -1,//GPIO29
+    -1,//GPIO30
+};
diff --git a/components/soc/esp32p4/sdio_slave_periph.c b/components/soc/esp32p4/sdio_slave_periph.c
new file mode 100644
index 0000000000..21d9501108
--- /dev/null
+++ b/components/soc/esp32p4/sdio_slave_periph.c
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "soc/sdio_slave_periph.h"
+#include "soc/sdio_slave_pins.h"
+
+const sdio_slave_slot_info_t sdio_slave_slot_info[1]  = {
+    {
+        .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK,
+        .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD,
+        .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0,
+        .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1,
+        .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2,
+        .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3,
+        .func = SDIO_SLAVE_SLOT0_FUNC,
+    },
+};
diff --git a/components/soc/esp32p4/sdm_periph.c b/components/soc/esp32p4/sdm_periph.c
new file mode 100644
index 0000000000..2c47c3bee1
--- /dev/null
+++ b/components/soc/esp32p4/sdm_periph.c
@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/sdm_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
+    .channels = {
+        [0] = {
+            GPIO_SD0_OUT_IDX
+        },
+        [1] = {
+            GPIO_SD1_OUT_IDX
+        },
+        [2] = {
+            GPIO_SD2_OUT_IDX
+        },
+        [3] = {
+            GPIO_SD3_OUT_IDX
+        }
+    }
+};
diff --git a/components/soc/esp32p4/sdmmc_periph.c b/components/soc/esp32p4/sdmmc_periph.c
new file mode 100644
index 0000000000..8b12f54d34
--- /dev/null
+++ b/components/soc/esp32p4/sdmmc_periph.c
@@ -0,0 +1,63 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/sdmmc_periph.h"
+// ESP32P4-TODO: need new iomux and sig map
+const sdmmc_slot_info_t sdmmc_slot_info[SOC_SDMMC_NUM_SLOTS] = {
+    {
+        .width = 8,
+        .card_detect = 0,
+        .write_protect = 0,
+        .card_int = 0,
+    },
+    {
+        .width = 4,
+        .card_detect = 0,
+        .write_protect = 0,
+        .card_int = 0,
+    }
+};
+
+const sdmmc_slot_io_info_t sdmmc_slot_gpio_num[SOC_SDMMC_NUM_SLOTS] = {
+    {
+        .clk = SDMMC_SLOT0_IOMUX_PIN_NUM_CLK,
+        .cmd = SDMMC_SLOT0_IOMUX_PIN_NUM_CMD,
+        .d0 = SDMMC_SLOT0_IOMUX_PIN_NUM_D0,
+        .d1 = SDMMC_SLOT0_IOMUX_PIN_NUM_D1,
+        .d2 = SDMMC_SLOT0_IOMUX_PIN_NUM_D2,
+        .d3 = SDMMC_SLOT0_IOMUX_PIN_NUM_D3,
+        .d4 = SDMMC_SLOT0_IOMUX_PIN_NUM_D4,
+        .d5 = SDMMC_SLOT0_IOMUX_PIN_NUM_D5,
+        .d6 = SDMMC_SLOT0_IOMUX_PIN_NUM_D6,
+        .d7 = SDMMC_SLOT0_IOMUX_PIN_NUM_D7,
+    },
+    {
+        .clk = SDMMC_SLOT1_IOMUX_PIN_NUM_CLK,
+        .cmd = SDMMC_SLOT1_IOMUX_PIN_NUM_CMD,
+        .d0 = SDMMC_SLOT1_IOMUX_PIN_NUM_D0,
+        .d1 = SDMMC_SLOT1_IOMUX_PIN_NUM_D1,
+        .d2 = SDMMC_SLOT1_IOMUX_PIN_NUM_D2,
+        .d3 = SDMMC_SLOT1_IOMUX_PIN_NUM_D3,
+    }
+};
+
+const sdmmc_slot_io_info_t sdmmc_slot_gpio_sig[SOC_SDMMC_NUM_SLOTS] = {
+    {
+
+    },
+    {
+        .clk = SD_CARD_CCLK_2_PAD_OUT_IDX,
+        .cmd = SD_CARD_CCMD_2_PAD_OUT_IDX,
+        .d0 = SD_CARD_CDATA0_2_PAD_OUT_IDX,
+        .d1 = SD_CARD_CDATA1_2_PAD_OUT_IDX,
+        .d2 = SD_CARD_CDATA2_2_PAD_OUT_IDX,
+        .d3 = SD_CARD_CDATA3_2_PAD_OUT_IDX,
+        .d4 = SD_CARD_CDATA4_2_PAD_OUT_IDX,
+        .d5 = SD_CARD_CDATA5_2_PAD_OUT_IDX,
+        .d6 = SD_CARD_CDATA6_2_PAD_OUT_IDX,
+        .d7 = SD_CARD_CDATA7_2_PAD_OUT_IDX,
+    },
+};
diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c
new file mode 100644
index 0000000000..86c2e7bbfe
--- /dev/null
+++ b/components/soc/esp32p4/spi_periph.c
@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/spi_periph.h"
+#include "stddef.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
+    {
+        .spiclk_in = 0,/* SPI clock is not an input signal*/
+        .spics_in = 0,/* SPI cs is not an input signal*/
+        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
+        .irq = ETS_MSPI_INTR_SOURCE,
+        .irq_dma = -1,
+        .module = PERIPH_SPI_MODULE,
+        .hw = (spi_dev_t *) &SPIMEM1,
+        .func = SPI_FUNC_NUM,
+    }, { // TODO: IDF-5334 Need check
+        .spiclk_out = FSPICLK_OUT_IDX,
+        .spiclk_in = FSPICLK_IN_IDX,
+        .spid_out = FSPID_OUT_IDX,
+        .spiq_out = FSPIQ_OUT_IDX,
+        .spiwp_out = FSPIWP_OUT_IDX,
+        .spihd_out = FSPIHD_OUT_IDX,
+        .spid_in = FSPID_IN_IDX,
+        .spiq_in = FSPIQ_IN_IDX,
+        .spiwp_in = FSPIWP_IN_IDX,
+        .spihd_in = FSPIHD_IN_IDX,
+        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
+        .spics_in = FSPICS0_IN_IDX,
+        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
+        .irq = ETS_GSPI2_INTR_SOURCE,
+        .irq_dma = -1,
+        .module = PERIPH_SPI2_MODULE,
+        .hw = &GPSPI2,
+        .func = SPI2_FUNC_NUM,
+    }
+};
diff --git a/components/soc/esp32p4/temperature_sensor_periph.c b/components/soc/esp32p4/temperature_sensor_periph.c
new file mode 100644
index 0000000000..a681a41e3b
--- /dev/null
+++ b/components/soc/esp32p4/temperature_sensor_periph.c
@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/temperature_sensor_periph.h"
+
+const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
+    /*Offset   reg_val  min  max  error */
+    {-2,     5,    50,  125,   3},
+    {-1,     7,    20,  100,   2},
+    { 0,    15,   -10,   80,   1},
+    { 1,    11,   -30,   50,   2},
+    { 2,    10,   -40,   20,   3},
+};
diff --git a/components/soc/esp32p4/timer_periph.c b/components/soc/esp32p4/timer_periph.c
new file mode 100644
index 0000000000..d0d4ca2e81
--- /dev/null
+++ b/components/soc/esp32p4/timer_periph.c
@@ -0,0 +1,24 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/timer_periph.h"
+
+const timer_group_signal_conn_t timer_group_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_TIMG0_MODULE,
+            .timer_irq_id = {
+                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
+            }
+        },
+        [1] = {
+            .module = PERIPH_TIMG1_MODULE,
+            .timer_irq_id = {
+                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
+            }
+        }
+    }
+};
diff --git a/components/soc/esp32p4/twai_periph.c b/components/soc/esp32p4/twai_periph.c
new file mode 100644
index 0000000000..3f7d17c41d
--- /dev/null
+++ b/components/soc/esp32p4/twai_periph.c
@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/twai_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const twai_controller_signal_conn_t twai_controller_periph_signals = {
+    .controllers = {
+        [0] = {
+            .module = PERIPH_TWAI0_MODULE,
+            .irq_id = ETS_TWAI0_INTR_SOURCE,
+            .tx_sig = TWAI0_TX_IDX,
+            .rx_sig = TWAI0_RX_IDX,
+            .bus_off_sig = TWAI0_BUS_OFF_ON_IDX,
+            .clk_out_sig = TWAI0_CLKOUT_IDX,
+            .stand_by_sig = TWAI0_STANDBY_IDX,
+        },
+        [1] = {
+            .module = PERIPH_TWAI1_MODULE,
+            .irq_id = ETS_TWAI1_INTR_SOURCE,
+            .tx_sig = TWAI1_TX_IDX,
+            .rx_sig = TWAI1_RX_IDX,
+            .bus_off_sig = TWAI1_BUS_OFF_ON_IDX,
+            .clk_out_sig = TWAI1_CLKOUT_IDX,
+            .stand_by_sig = TWAI1_STANDBY_IDX,
+        }
+    }
+};
diff --git a/components/soc/esp32p4/uart_periph.c b/components/soc/esp32p4/uart_periph.c
index e69de29bb2..506d808273 100644
--- a/components/soc/esp32p4/uart_periph.c
+++ b/components/soc/esp32p4/uart_periph.c
@@ -0,0 +1,80 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/uart_periph.h"
+
+/*
+ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
+   {
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U0TXD_GPIO_NUM,
+                .iomux_func = U0TXD_MUX_FUNC,
+                .input = 0,
+                .signal = 0,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U0RXD_GPIO_NUM,
+                .iomux_func = U0RXD_MUX_FUNC,
+                .input = 1,
+                .signal = 0,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U0RTS_GPIO_NUM,
+                .iomux_func = U0RTS_MUX_FUNC,
+                .input = 0,
+                .signal = 0,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U0CTS_GPIO_NUM,
+                .iomux_func = U0CTS_MUX_FUNC,
+                .input = 1,
+                .signal = 0,
+            }
+        },
+        .irq = ETS_UART0_INTR_SOURCE,
+        .module = PERIPH_UART0_MODULE,
+    },
+
+    {
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U1TXD_GPIO_NUM,
+                .iomux_func = U1TXD_MUX_FUNC,
+                .input = 0,
+                .signal = 0,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U1RXD_GPIO_NUM,
+                .iomux_func = U1RXD_MUX_FUNC,
+                .input = 1,
+                .signal = 0,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U1RTS_GPIO_NUM,
+                .iomux_func = U1RTS_MUX_FUNC,
+                .input = 0,
+                .signal = 0,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U1CTS_GPIO_NUM,
+                .iomux_func = U1CTS_MUX_FUNC,
+                .input = 1,
+                .signal = 0,
+            },
+        },
+        .irq = ETS_UART1_INTR_SOURCE,
+        .module = PERIPH_UART1_MODULE,
+    },
+};
diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h
index cb4de430f1..725486d50f 100644
--- a/components/soc/include/soc/rtc_cntl_periph.h
+++ b/components/soc/include/soc/rtc_cntl_periph.h
@@ -9,7 +9,7 @@
 #include "sdkconfig.h"
 
 // TODO: IDF-5645
-#if CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4
 #include "soc/lp_aon_reg.h"
 #include "soc/lp_analog_peri_reg.h"
 #include "soc/lp_clkrst_reg.h"

From d9e25c305a3c46316062e9f6e5dbd6aebe29cafa Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Fri, 30 Jun 2023 11:30:03 +0800
Subject: [PATCH 02/13] feat(adc): use soc_caps to decide which files to be
 included

---
 components/esp_adc/CMakeLists.txt | 6 ++++--
 components/hal/CMakeLists.txt     | 6 ++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/components/esp_adc/CMakeLists.txt b/components/esp_adc/CMakeLists.txt
index 6d3d4fbaba..0c602f92c1 100644
--- a/components/esp_adc/CMakeLists.txt
+++ b/components/esp_adc/CMakeLists.txt
@@ -4,10 +4,12 @@ set(includes "include" "interface" "${target}/include" "deprecated/include")
 
 set(srcs "adc_cali.c"
          "adc_cali_curve_fitting.c"
-         "adc_oneshot.c"
-         "adc_common.c"
          "deprecated/esp_adc_cal_common_legacy.c")
 
+if(CONFIG_SOC_ADC_SUPPORTED)
+    list(APPEND srcs "adc_oneshot.c" "adc_common.c")
+endif()
+
 if(CONFIG_SOC_ADC_DMA_SUPPORTED)
     list(APPEND srcs "adc_continuous.c")
     if(CONFIG_SOC_ADC_MONITOR_SUPPORTED)
diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt
index 892a368377..f88e8bc0be 100644
--- a/components/hal/CMakeLists.txt
+++ b/components/hal/CMakeLists.txt
@@ -40,8 +40,6 @@ if(NOT BOOTLOADER_BUILD)
         "gpio_hal.c"
         "uart_hal.c"
         "uart_hal_iram.c"
-        "adc_hal_common.c"
-        "adc_oneshot_hal.c"
         "${target}/clk_tree_hal.c")
 
     if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
@@ -110,6 +108,10 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "parlio_hal.c")
     endif()
 
+    if(CONFIG_SOC_ADC_SUPPORTED)
+        list(APPEND srcs "adc_hal_common.c" "adc_oneshot_hal.c")
+    endif()
+
     if(CONFIG_SOC_ADC_DMA_SUPPORTED)
         list(APPEND srcs "adc_hal.c")
     endif()

From 611c1037a2454fc9d72d11d06bfa4aab960e23ec Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Fri, 30 Jun 2023 11:37:21 +0800
Subject: [PATCH 03/13] feat(soc): added soc_caps.h on esp32p4

---
 .../esp32p4/include/soc/Kconfig.soc_caps.in   | 956 ++++++++++++++++++
 components/soc/esp32p4/include/soc/soc_caps.h | 479 +++++++++
 tools/test_apps/.build-test-rules.yml         |   4 +
 3 files changed, 1439 insertions(+)
 create mode 100644 components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
 create mode 100644 components/soc/esp32p4/include/soc/soc_caps.h

diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
new file mode 100644
index 0000000000..cf0f176453
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -0,0 +1,956 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config SOC_UART_SUPPORTED
+    bool
+    default y
+
+config SOC_ASYNC_MEMCPY_SUPPORTED
+    bool
+    default y
+
+config SOC_SUPPORTS_SECURE_DL_MODE
+    bool
+    default y
+
+config SOC_EFUSE_KEY_PURPOSE_FIELD
+    bool
+    default y
+
+config SOC_RTC_FAST_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_RTC_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_SUPPORTED
+    bool
+    default y
+
+config SOC_FLASH_ENC_SUPPORTED
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_40M
+    bool
+    default y
+
+config SOC_AES_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_AES_GDMA
+    bool
+    default y
+
+config SOC_AES_SUPPORT_AES_128
+    bool
+    default y
+
+config SOC_AES_SUPPORT_AES_256
+    bool
+    default y
+
+config SOC_ADC_PERIPH_NUM
+    int
+    default 1
+
+config SOC_ADC_MAX_CHANNEL_NUM
+    int
+    default 7
+
+config SOC_ADC_ATTEN_NUM
+    int
+    default 4
+
+config SOC_ADC_DIGI_CONTROLLER_NUM
+    int
+    default 1
+
+config SOC_ADC_PATT_LEN_MAX
+    int
+    default 8
+
+config SOC_ADC_DIGI_MAX_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_DIGI_MIN_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_DIGI_IIR_FILTER_NUM
+    int
+    default 2
+
+config SOC_ADC_DIGI_MONITOR_NUM
+    int
+    default 2
+
+config SOC_ADC_DIGI_RESULT_BYTES
+    int
+    default 4
+
+config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
+    int
+    default 4
+
+config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
+    int
+    default 83333
+
+config SOC_ADC_SAMPLE_FREQ_THRES_LOW
+    int
+    default 611
+
+config SOC_ADC_RTC_MIN_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_RTC_MAX_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_CALIBRATION_V1_SUPPORTED
+    bool
+    default n
+
+config SOC_APB_BACKUP_DMA
+    bool
+    default n
+
+config SOC_BROWNOUT_RESET_SUPPORTED
+    bool
+    default y
+
+config SOC_SHARED_IDCACHE_SUPPORTED
+    bool
+    default y
+
+config SOC_CACHE_FREEZE_SUPPORTED
+    bool
+    default y
+
+config SOC_CACHE_L2_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_CORES_NUM
+    int
+    default 2
+
+config SOC_CPU_INTR_NUM
+    int
+    default 32
+
+config SOC_CPU_HAS_FLEXIBLE_INTC
+    bool
+    default y
+
+config SOC_INT_PLIC_SUPPORTED
+    bool
+    default n
+
+config SOC_INT_CLIC_SUPPORTED
+    bool
+    default y
+
+config SOC_BRANCH_PREDICTOR_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_BREAKPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINT_SIZE
+    hex
+    default 0x80000000
+
+config SOC_CPU_HAS_PMA
+    bool
+    default y
+
+config SOC_CPU_IDRAM_SPLIT_USING_PMP
+    bool
+    default y
+
+config SOC_DS_SIGNATURE_MAX_BIT_LEN
+    int
+    default 3072
+
+config SOC_DS_KEY_PARAM_MD_IV_LENGTH
+    int
+    default 16
+
+config SOC_DS_KEY_CHECK_MAX_WAIT_US
+    int
+    default 1100
+
+config SOC_GDMA_GROUPS
+    int
+    default 1
+
+config SOC_GDMA_PAIRS_PER_GROUP
+    int
+    default 3
+
+config SOC_GDMA_SUPPORT_ETM
+    bool
+    default n
+
+config SOC_ETM_GROUPS
+    int
+    default 1
+
+config SOC_ETM_CHANNELS_PER_GROUP
+    int
+    default 50
+
+config SOC_GPIO_PORT
+    int
+    default 1
+
+config SOC_GPIO_PIN_COUNT
+    int
+    default 64
+
+config SOC_GPIO_ETM_EVENTS_PER_GROUP
+    int
+    default 8
+
+config SOC_GPIO_ETM_TASKS_PER_GROUP
+    int
+    default 8
+
+config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
+    bool
+    default y
+
+config SOC_GPIO_VALID_GPIO_MASK
+    hex
+    default 0xFFFFFFFFFFFFFFFF
+
+config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
+    int
+    default 0
+
+config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
+    hex
+    default 0x000000007FFFFF00
+
+config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
+    int
+    default 8
+
+config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
+    int
+    default 8
+
+config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
+    bool
+    default y
+
+config SOC_I2C_NUM
+    int
+    default 1
+
+config SOC_I2C_FIFO_LEN
+    int
+    default 32
+
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_HW_CLR_BUS
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_RTC
+    bool
+    default y
+
+config SOC_I2S_NUM
+    int
+    default 1
+
+config SOC_I2S_HW_VERSION_2
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_XTAL
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PCM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM_TX
+    bool
+    default y
+
+config SOC_I2S_PDM_MAX_TX_LINES
+    int
+    default 2
+
+config SOC_I2S_SUPPORTS_TDM
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_XTAL_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_CHANNEL_NUM
+    int
+    default 6
+
+config SOC_LEDC_TIMER_BIT_WIDTH
+    int
+    default 20
+
+config SOC_LEDC_SUPPORT_FADE_STOP
+    bool
+    default y
+
+config SOC_LEDC_GAMMA_FADE_RANGE_MAX
+    int
+    default 16
+
+config SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    bool
+    default n
+
+config SOC_MMU_PERIPH_NUM
+    int
+    default 2
+
+config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
+    int
+    default 2
+
+config SOC_MMU_DI_VADDR_SHARED
+    bool
+    default y
+
+config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
+    bool
+    default n
+
+config SOC_MPU_MIN_REGION_SIZE
+    hex
+    default 0x20000000
+
+config SOC_MPU_REGIONS_MAX_NUM
+    int
+    default 8
+
+config SOC_MPU_REGION_RO_SUPPORTED
+    bool
+    default n
+
+config SOC_MPU_REGION_WO_SUPPORTED
+    bool
+    default n
+
+config SOC_PCNT_GROUPS
+    int
+    default 1
+
+config SOC_PCNT_UNITS_PER_GROUP
+    int
+    default 4
+
+config SOC_PCNT_CHANNELS_PER_UNIT
+    int
+    default 2
+
+config SOC_PCNT_THRES_POINT_PER_UNIT
+    int
+    default 2
+
+config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
+    bool
+    default y
+
+config SOC_RMT_GROUPS
+    int
+    default 1
+
+config SOC_RMT_TX_CANDIDATES_PER_GROUP
+    int
+    default 2
+
+config SOC_RMT_RX_CANDIDATES_PER_GROUP
+    int
+    default 2
+
+config SOC_RMT_CHANNELS_PER_GROUP
+    int
+    default 4
+
+config SOC_RMT_MEM_WORDS_PER_CHANNEL
+    int
+    default 48
+
+config SOC_RMT_SUPPORT_RX_PINGPONG
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_RX_DEMODULATION
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_ASYNC_STOP
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_LOOP_COUNT
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_SYNCHRO
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_RC_FAST
+    bool
+    default y
+
+config SOC_MCPWM_GROUPS
+    int
+    default 1
+
+config SOC_MCPWM_TIMERS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_OPERATORS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_COMPARATORS_PER_OPERATOR
+    int
+    default 2
+
+config SOC_MCPWM_GENERATORS_PER_OPERATOR
+    int
+    default 2
+
+config SOC_MCPWM_TRIGGERS_PER_OPERATOR
+    int
+    default 2
+
+config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
+    bool
+    default y
+
+config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
+    int
+    default 3
+
+config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
+    bool
+    default y
+
+config SOC_MCPWM_SUPPORT_ETM
+    bool
+    default y
+
+config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
+    bool
+    default y
+
+config SOC_PARLIO_GROUPS
+    int
+    default 1
+
+config SOC_PARLIO_TX_UNITS_PER_GROUP
+    int
+    default 1
+
+config SOC_PARLIO_RX_UNITS_PER_GROUP
+    int
+    default 1
+
+config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
+    int
+    default 16
+
+config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
+    int
+    default 16
+
+config SOC_PARLIO_TX_RX_SHARE_INTERRUPT
+    bool
+    default y
+
+config SOC_RSA_MAX_BIT_LEN
+    int
+    default 3072
+
+config SOC_SHA_DMA_MAX_BUFFER_SIZE
+    int
+    default 3968
+
+config SOC_SHA_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_RESUME
+    bool
+    default y
+
+config SOC_SHA_GDMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA1
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA224
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA256
+    bool
+    default y
+
+config SOC_SDMMC_USE_IOMUX
+    bool
+    default y
+
+config SOC_SDMMC_USE_GPIO_MATRIX
+    bool
+    default y
+
+config SOC_SDMMC_NUM_SLOTS
+    int
+    default 2
+
+config SOC_SDMMC_IOMUX_FUNC
+    bool
+    default n
+
+config SOC_SDMMC_DMA_NEED_CACHE_WB
+    bool
+    default y
+
+config SOC_SDM_GROUPS
+    int
+    default 1
+
+config SOC_SDM_CHANNELS_PER_GROUP
+    int
+    default 4
+
+config SOC_SDM_CLK_SUPPORT_PLL_F80M
+    bool
+    default y
+
+config SOC_SDM_CLK_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_SPI_PERIPH_NUM
+    int
+    default 2
+
+config SOC_SPI_MAX_CS_NUM
+    int
+    default 6
+
+config SOC_MEMSPI_IS_INDEPENDENT
+    bool
+    default y
+
+config SOC_SPI_MAXIMUM_BUFFER_SIZE
+    int
+    default 64
+
+config SOC_SPI_SUPPORT_DDRCLK
+    bool
+    default y
+
+config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CD_SIG
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_SLAVE_HD_VER2
+    bool
+    default n
+
+config SOC_SPI_SUPPORT_CLK_XTAL
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CLK_PLL_F80M
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CLK_RC_FAST
+    bool
+    default y
+
+config SOC_SPI_MAX_PRE_DIVIDER
+    int
+    default 16
+
+config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_IDLE_INTR
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_CHECK_SUS
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_WRAP
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_COUNTER_NUM
+    int
+    default 2
+
+config SOC_SYSTIMER_ALARM_NUM
+    int
+    default 3
+
+config SOC_SYSTIMER_BIT_WIDTH_LO
+    int
+    default 32
+
+config SOC_SYSTIMER_BIT_WIDTH_HI
+    int
+    default 20
+
+config SOC_SYSTIMER_FIXED_DIVIDER
+    bool
+    default y
+
+config SOC_SYSTIMER_SUPPORT_RC_FAST
+    bool
+    default y
+
+config SOC_SYSTIMER_INT_LEVEL
+    bool
+    default y
+
+config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
+    bool
+    default y
+
+config SOC_LP_TIMER_BIT_WIDTH_LO
+    int
+    default 32
+
+config SOC_LP_TIMER_BIT_WIDTH_HI
+    int
+    default 16
+
+config SOC_TIMER_GROUPS
+    int
+    default 2
+
+config SOC_TIMER_GROUP_TIMERS_PER_GROUP
+    int
+    default 1
+
+config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
+    int
+    default 54
+
+config SOC_TIMER_GROUP_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_TIMER_GROUP_SUPPORT_RC_FAST
+    bool
+    default y
+
+config SOC_TIMER_GROUP_TOTAL_TIMERS
+    int
+    default 2
+
+config SOC_TIMER_SUPPORT_ETM
+    bool
+    default n
+
+config SOC_TWAI_CONTROLLER_NUM
+    int
+    default 2
+
+config SOC_TWAI_CLK_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_TWAI_BRP_MIN
+    int
+    default 2
+
+config SOC_TWAI_BRP_MAX
+    int
+    default 32768
+
+config SOC_TWAI_SUPPORTS_RX_STATUS
+    bool
+    default y
+
+config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
+    bool
+    default y
+
+config SOC_EFUSE_DIS_PAD_JTAG
+    bool
+    default y
+
+config SOC_EFUSE_DIS_USB_JTAG
+    bool
+    default y
+
+config SOC_EFUSE_DIS_DIRECT_BOOT
+    bool
+    default y
+
+config SOC_EFUSE_SOFT_DIS_JTAG
+    bool
+    default y
+
+config SOC_SECURE_BOOT_V2_RSA
+    bool
+    default y
+
+config SOC_SECURE_BOOT_V2_ECC
+    bool
+    default y
+
+config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
+    int
+    default 3
+
+config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
+    bool
+    default y
+
+config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
+    bool
+    default y
+
+config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
+    int
+    default 32
+
+config SOC_FLASH_ENCRYPTION_XTS_AES
+    bool
+    default y
+
+config SOC_FLASH_ENCRYPTION_XTS_AES_128
+    bool
+    default y
+
+config SOC_UART_NUM
+    int
+    default 2
+
+config SOC_UART_HP_NUM
+    int
+    default 2
+
+config SOC_UART_FIFO_LEN
+    int
+    default 128
+
+config SOC_UART_BITRATE_MAX
+    int
+    default 5000000
+
+config SOC_UART_SUPPORT_PLL_F80M_CLK
+    bool
+    default y
+
+config SOC_UART_SUPPORT_RTC_CLK
+    bool
+    default y
+
+config SOC_UART_SUPPORT_XTAL_CLK
+    bool
+    default y
+
+config SOC_UART_SUPPORT_WAKEUP_INT
+    bool
+    default y
+
+config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
+    bool
+    default y
+
+config SOC_COEX_HW_PTI
+    bool
+    default y
+
+config SOC_PHY_DIG_REGS_MEM_SIZE
+    int
+    default 21
+
+config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
+    int
+    default 12
+
+config SOC_PM_SUPPORT_WIFI_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_BT_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_CPU_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_MODEM_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_XTAL32K_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RC32K_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RC_FAST_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_VDDSDIO_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_TOP_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
+    bool
+    default y
+
+config SOC_PM_CPU_RETENTION_BY_SW
+    bool
+    default n
+
+config SOC_PM_PAU_LINK_NUM
+    int
+    default 4
+
+config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
+    bool
+    default y
+
+config SOC_MODEM_CLOCK_IS_INDEPENDENT
+    bool
+    default n
+
+config SOC_CLK_XTAL32K_SUPPORTED
+    bool
+    default y
+
+config SOC_CLK_OSC_SLOW_SUPPORTED
+    bool
+    default y
+
+config SOC_CLK_RC32K_SUPPORTED
+    bool
+    default y
+
+config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
+    bool
+    default y
+
+config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL
+    bool
+    default y
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
new file mode 100644
index 0000000000..21a3346f60
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -0,0 +1,479 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The long term plan is to have a single soc_caps.h for each peripheral.
+// During the refactoring and multichip support development process, we
+// seperate these information into periph_caps.h for each peripheral and
+// include them here.
+
+/*
+ * These defines are parsed and imported as kconfig variables via the script
+ * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
+ *
+ * If this file is changed the script will automatically run the script
+ * and generate the kconfig variables as part of the pre-commit hooks.
+ *
+ * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32p4/include/soc/'`
+ *
+ * For more information see `tools/gen_soc_caps_kconfig/README.md`
+ *
+*/
+
+#pragma once
+
+/*-------------------------- COMMON CAPS ---------------------------------------*/
+// #define SOC_ADC_SUPPORTED               1  //TODO: IDF-6496
+// #define SOC_ANA_CMPR_SUPPORTED          1  //TODO: IDF-7479
+// #define SOC_DEDICATED_GPIO_SUPPORTED    1  //TODO: IDF-7552
+#define SOC_UART_SUPPORTED              1
+// #define SOC_GDMA_SUPPORTED              1  //TODO: IDF-6504
+// #define SOC_GPTIMER_SUPPORTED           1  //TODO: IDF-6515
+// #define SOC_PCNT_SUPPORTED              1  //TODO: IDF-7475
+// #define SOC_MCPWM_SUPPORTED             1  //TODO: IDF-7493
+// #define SOC_TWAI_SUPPORTED              1  //TODO: IDF-7470
+// #define SOC_ETM_SUPPORTED               1  //TODO: IDF-7478
+// #define SOC_PARLIO_SUPPORTED            1  //TODO: IDF-7471, TODO: IDF-7472
+#define SOC_ASYNC_MEMCPY_SUPPORTED      1
+// disable usb serial jtag for esp32p4, current image does not support
+// #define SOC_USB_SERIAL_JTAG_SUPPORTED   1  //TODO: IDF-7496
+// #define SOC_TEMP_SENSOR_SUPPORTED       1  //TODO: IDF-7482
+#define SOC_SUPPORTS_SECURE_DL_MODE     1
+// #define SOC_RISCV_COPROC_SUPPORTED      1
+#define SOC_EFUSE_KEY_PURPOSE_FIELD     1
+#define SOC_RTC_FAST_MEM_SUPPORTED      1
+#define SOC_RTC_MEM_SUPPORTED           1
+// #define SOC_I2S_SUPPORTED               1  //TODO: IDF-6508
+// #define SOC_RMT_SUPPORTED               1  //TODO: IDF-7476
+// #define SOC_SDM_SUPPORTED               1  //TODO: IDF-7551
+// #define SOC_GPSPI_SUPPORTED             1  //TODO: IDF-7502, TODO: IDF-7503
+// #define SOC_LEDC_SUPPORTED              1  //TODO: IDF-6510
+// #define SOC_I2C_SUPPORTED               1  //TODO: IDF-6507, TODO: IDF-7491
+#define SOC_SYSTIMER_SUPPORTED          1
+// #define SOC_AES_SUPPORTED               1  //TODO: IDF-6519
+// #define SOC_MPI_SUPPORTED               1
+// #define SOC_SHA_SUPPORTED               1  //TODO: IDF-7541
+// #define SOC_HMAC_SUPPORTED              1  //TODO: IDF-7543
+// #define SOC_DIG_SIGN_SUPPORTED          1  //TODO: IDF-6518
+// #define SOC_ECC_SUPPORTED               1  //TODO: IDF-7549
+#define SOC_FLASH_ENC_SUPPORTED         1
+// #define SOC_SECURE_BOOT_SUPPORTED       1  //TODO: IDF-7544
+// #define SOC_BOD_SUPPORTED               1  //TODO: IDF-7519
+// #define SOC_APM_SUPPORTED               1  //TODO: IDF-7542
+// #define SOC_PMU_SUPPORTED               1  //TODO: IDF-7531
+// #define SOC_PAU_SUPPORTED               1  //TODO: IDF-7531
+// #define SOC_LP_TIMER_SUPPORTED          1  //TODO: IDF-7532
+// #define SOC_SPIRAM_SUPPORTED            1  //TODO: IDF-7495
+// #define SOC_ULP_SUPPORTED               1  //TODO: IDF-7534
+// #define SOC_SDMMC_HOST_SUPPORTED        1  //TODO: IDF-6502
+// #define SOC_CLK_TREE_SUPPORTED          1  //TODO: IDF-7526
+
+/*-------------------------- XTAL CAPS ---------------------------------------*/
+#define SOC_XTAL_SUPPORT_40M            1
+
+/*-------------------------- AES CAPS -----------------------------------------*/
+#define SOC_AES_SUPPORT_DMA     (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_AES_GDMA            (1)
+
+#define SOC_AES_SUPPORT_AES_128 (1)
+#define SOC_AES_SUPPORT_AES_256 (1)
+
+/*-------------------------- ADC CAPS -------------------------------*/
+/*!< SAR ADC Module*/
+// #define SOC_ADC_DIG_CTRL_SUPPORTED              1  //TODO: IDF-6496, TODO: IDF-6497
+// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
+// #define SOC_ADC_MONITOR_SUPPORTED               1
+#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
+// #define SOC_ADC_DMA_SUPPORTED                   1
+#define SOC_ADC_PERIPH_NUM                      (1U)
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (7)
+#define SOC_ADC_MAX_CHANNEL_NUM                 (7)
+#define SOC_ADC_ATTEN_NUM                       (4)
+
+/*!< Digital */
+#define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
+#define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
+#define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
+#define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
+#define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
+#define SOC_ADC_DIGI_MONITOR_NUM                (2)
+#define SOC_ADC_DIGI_RESULT_BYTES               (4)
+#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
+/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
+#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
+#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+
+/*!< RTC */
+#define SOC_ADC_RTC_MIN_BITWIDTH                (12)
+#define SOC_ADC_RTC_MAX_BITWIDTH                (12)
+
+/*!< Calibration */
+#define SOC_ADC_CALIBRATION_V1_SUPPORTED        (0) /*!< support HW offset calibration version 1*/
+
+// ESP32P4-TODO: Copy from esp32c6, need check
+/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
+#define SOC_APB_BACKUP_DMA              (0)
+
+/*-------------------------- BROWNOUT CAPS -----------------------------------*/
+#define SOC_BROWNOUT_RESET_SUPPORTED 1
+
+/*-------------------------- CACHE CAPS --------------------------------------*/
+#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_CACHE_FREEZE_SUPPORTED              1
+#define SOC_CACHE_L2_SUPPORTED                  1
+
+/*-------------------------- CPU CAPS ----------------------------------------*/
+#define SOC_CPU_CORES_NUM               (2U)
+#define SOC_CPU_INTR_NUM                32
+#define SOC_CPU_HAS_FLEXIBLE_INTC       1
+#define SOC_INT_PLIC_SUPPORTED          0       //riscv platform-level interrupt controller
+#define SOC_INT_CLIC_SUPPORTED          1
+#define SOC_BRANCH_PREDICTOR_SUPPORTED  1
+
+#define SOC_CPU_BREAKPOINTS_NUM         4
+#define SOC_CPU_WATCHPOINTS_NUM         4
+#define SOC_CPU_WATCHPOINT_SIZE         0x80000000 // bytes
+
+#define SOC_CPU_HAS_PMA                 1
+#define SOC_CPU_IDRAM_SPLIT_USING_PMP   1
+
+// TODO: IDF-5360 (Copy from esp32c3, need check)
+/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
+/** The maximum length of a Digital Signature in bits. */
+#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
+
+/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
+#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
+
+/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
+    See TRM DS chapter for more details */
+#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
+
+/*-------------------------- GDMA CAPS -------------------------------------*/
+#define SOC_GDMA_GROUPS                 (1U) // Number of GDMA groups
+#define SOC_GDMA_PAIRS_PER_GROUP        (3)  // Number of GDMA pairs in each group
+#define SOC_GDMA_SUPPORT_ETM            (0)  // Support ETM submodule
+
+/*-------------------------- ETM CAPS --------------------------------------*/
+#define SOC_ETM_GROUPS                  1U  // Number of ETM groups
+#define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
+
+/*-------------------------- GPIO CAPS ---------------------------------------*/
+// ESP32-P4 has 1 GPIO peripheral
+#define SOC_GPIO_PORT                      1U
+#define SOC_GPIO_PIN_COUNT                 64
+// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1  //TODO: IDF-7481
+// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8  //TODO: IDF-7481
+
+// GPIO peripheral has the ETM extension
+// #define SOC_GPIO_SUPPORT_ETM          1
+#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
+#define SOC_GPIO_ETM_TASKS_PER_GROUP  8
+
+// Target has the full LP IO subsystem
+// On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
+// GPIO0~7 on ESP32P4 can support chip deep sleep wakeup
+// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
+
+#define SOC_GPIO_VALID_GPIO_MASK        (0xFFFFFFFFFFFFFFFF)
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
+
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
+
+/*-------------------------- RTCIO CAPS --------------------------------------*/
+// #define SOC_RTCIO_PIN_COUNT                 8  //TODO: IDF-7480
+// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED    1  //TODO: IDF-7480
+// #define SOC_RTCIO_HOLD_SUPPORTED            1  //TODO: IDF-7480
+// #define SOC_RTCIO_WAKE_SUPPORTED            1  //TODO: IDF-7480
+
+/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
+#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
+#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
+
+/*-------------------------- I2C CAPS ----------------------------------------*/
+// ESP32-P4 has 1 I2C
+#define SOC_I2C_NUM                 (1U)
+
+#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
+#define SOC_I2C_SUPPORT_SLAVE       (1)
+
+// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
+#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+
+#define SOC_I2C_SUPPORT_XTAL        (1)
+#define SOC_I2C_SUPPORT_RTC         (1)
+
+/*-------------------------- I2S CAPS ----------------------------------------*/
+#define SOC_I2S_NUM                 (1U)
+#define SOC_I2S_HW_VERSION_2        (1)
+#define SOC_I2S_SUPPORTS_XTAL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
+#define SOC_I2S_SUPPORTS_PCM        (1)
+#define SOC_I2S_SUPPORTS_PDM        (1)
+#define SOC_I2S_SUPPORTS_PDM_TX     (1)
+#define SOC_I2S_PDM_MAX_TX_LINES    (2)
+#define SOC_I2S_SUPPORTS_TDM        (1)
+
+/*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_CHANNEL_NUM                (6)
+#define SOC_LEDC_TIMER_BIT_WIDTH            (20)
+#define SOC_LEDC_SUPPORT_FADE_STOP          (1)
+#define SOC_LEDC_GAMMA_FADE_RANGE_MAX       (16)
+
+/*-------------------------- MMU CAPS ----------------------------------------*/
+#define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (0)
+#define SOC_MMU_PERIPH_NUM                    (2U)
+#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM     (2U)
+#define SOC_MMU_DI_VADDR_SHARED               (1) /*!< D/I vaddr are shared */
+
+/*-------------------------- MPU CAPS ----------------------------------------*/
+#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
+#define SOC_MPU_MIN_REGION_SIZE                   0x20000000U
+#define SOC_MPU_REGIONS_MAX_NUM                   8
+#define SOC_MPU_REGION_RO_SUPPORTED               0
+#define SOC_MPU_REGION_WO_SUPPORTED               0
+
+/*-------------------------- PCNT CAPS ---------------------------------------*/
+#define SOC_PCNT_GROUPS                       1U
+#define SOC_PCNT_UNITS_PER_GROUP              4
+#define SOC_PCNT_CHANNELS_PER_UNIT            2
+#define SOC_PCNT_THRES_POINT_PER_UNIT         2
+#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
+
+/*--------------------------- RMT CAPS ---------------------------------------*/
+#define SOC_RMT_GROUPS                        1U /*!< One RMT group */
+#define SOC_RMT_TX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Transmit */
+#define SOC_RMT_RX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Receive */
+#define SOC_RMT_CHANNELS_PER_GROUP            4  /*!< Total 4 channels */
+#define SOC_RMT_MEM_WORDS_PER_CHANNEL         48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
+#define SOC_RMT_SUPPORT_RX_PINGPONG           1  /*!< Support Ping-Pong mode on RX path */
+#define SOC_RMT_SUPPORT_RX_DEMODULATION       1  /*!< Support signal demodulation on RX path (i.e. remove carrier) */
+#define SOC_RMT_SUPPORT_TX_ASYNC_STOP         1  /*!< Support stop transmission asynchronously */
+#define SOC_RMT_SUPPORT_TX_LOOP_COUNT         1  /*!< Support transmit specified number of cycles in loop mode */
+#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP     1  /*!< Hardware support of auto-stop in loop mode */
+#define SOC_RMT_SUPPORT_TX_SYNCHRO            1  /*!< Support coordinate a group of TX channels to start simultaneously */
+#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY  1  /*!< TX carrier can be modulated to data phase only */
+#define SOC_RMT_SUPPORT_XTAL                  1  /*!< Support set XTAL clock as the RMT clock source */
+#define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST as the RMT clock source */
+
+/*-------------------------- MCPWM CAPS --------------------------------------*/
+#define SOC_MCPWM_GROUPS                     (1U)   ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
+#define SOC_MCPWM_TIMERS_PER_GROUP           (3)    ///< The number of timers that each group has
+#define SOC_MCPWM_OPERATORS_PER_GROUP        (3)    ///< The number of operators that each group has
+#define SOC_MCPWM_COMPARATORS_PER_OPERATOR   (2)    ///< The number of comparators that each operator has
+#define SOC_MCPWM_GENERATORS_PER_OPERATOR    (2)    ///< The number of generators that each operator has
+#define SOC_MCPWM_TRIGGERS_PER_OPERATOR      (2)    ///< The number of triggers that each operator has
+#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP      (3)    ///< The number of fault signal detectors that each group has
+#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP   (1)    ///< The number of capture timers that each group has
+#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3)    ///< The number of capture channels that each capture timer has
+#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP    (3)    ///< The number of GPIO synchros that each group has
+#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE       (1)    ///< Software sync event can be routed to its output
+#define SOC_MCPWM_SUPPORT_ETM                (1)    ///< Support ETM (Event Task Matrix)
+#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP     (1)    ///< Capture timer shares clock with other PWM timers
+
+/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
+// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
+
+/*-------------------------- PARLIO CAPS --------------------------------------*/
+#define SOC_PARLIO_GROUPS                    1U  /*!< Number of parallel IO peripherals */
+#define SOC_PARLIO_TX_UNITS_PER_GROUP        1U  /*!< number of TX units in each group */
+#define SOC_PARLIO_RX_UNITS_PER_GROUP        1U  /*!< number of RX units in each group */
+#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
+#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
+#define SOC_PARLIO_TX_RX_SHARE_INTERRUPT     1   /*!< TX and RX unit share the same interrupt source number */
+
+/*--------------------------- RSA CAPS ---------------------------------------*/
+#define SOC_RSA_MAX_BIT_LEN    (3072)
+
+// TODO: IDF-5353 (Copy from esp32c3, need check)
+/*--------------------------- SHA CAPS ---------------------------------------*/
+
+/* Max amount of bytes in a single DMA operation is 4095,
+   for SHA this means that the biggest safe amount of bytes is
+   31 blocks of 128 bytes = 3968
+*/
+#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
+#define SOC_SHA_SUPPORT_DMA             (1)
+
+/* The SHA engine is able to resume hashing from a user */
+#define SOC_SHA_SUPPORT_RESUME          (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_SHA_GDMA             (1)
+
+/* Supported HW algorithms */
+#define SOC_SHA_SUPPORT_SHA1            (1)
+#define SOC_SHA_SUPPORT_SHA224          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
+
+#ifdef SDMMC_DEFAULT_IOMUX
+#define SOC_SDMMC_USE_IOMUX 1
+#else
+#define SOC_SDMMC_USE_GPIO_MATRIX 1
+#endif
+#define SOC_SDMMC_NUM_SLOTS 2
+#define SOC_SDMMC_IOMUX_FUNC 0
+#define SOC_SDMMC_DMA_NEED_CACHE_WB 1
+
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
+#define SOC_SDM_GROUPS               1U
+#define SOC_SDM_CHANNELS_PER_GROUP   4
+#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
+#define SOC_SDM_CLK_SUPPORT_XTAL     1
+
+// TODO: IDF-5334 (Copy from esp32c3, need check)
+/*-------------------------- SPI CAPS ----------------------------------------*/
+#define SOC_SPI_PERIPH_NUM          2
+#define SOC_SPI_PERIPH_CS_NUM(i)    6
+#define SOC_SPI_MAX_CS_NUM          6
+
+#define SOC_MEMSPI_IS_INDEPENDENT 1
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
+
+#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
+#define SOC_SPI_SUPPORT_CD_SIG              1
+#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       0
+#define SOC_SPI_SUPPORT_CLK_XTAL            1
+#define SOC_SPI_SUPPORT_CLK_PLL_F80M        1
+#define SOC_SPI_SUPPORT_CLK_RC_FAST         1
+
+// Peripheral supports DIO, DOUT, QIO, or QOUT
+// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
+#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)  ({(void)host_id; 1;})
+
+#define SOC_MEMSPI_IS_INDEPENDENT 1
+#define SOC_SPI_MAX_PRE_DIVIDER 16
+
+/*-------------------------- SPI MEM CAPS ---------------------------------------*/
+#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
+#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
+#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
+#define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
+#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
+#define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
+#define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
+
+#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED         1
+#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
+#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
+
+/*-------------------------- SYSTIMER CAPS ----------------------------------*/
+#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
+#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
+#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
+#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
+#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
+#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
+#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
+#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+// #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event  //TODO: IDF-7486
+
+/*-------------------------- LP_TIMER CAPS ----------------------------------*/
+#define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
+#define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
+
+/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
+#define SOC_TIMER_GROUPS                  (2)
+#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
+#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
+#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
+#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
+#define SOC_TIMER_SUPPORT_ETM             (0)
+
+/*-------------------------- TWAI CAPS ---------------------------------------*/
+#define SOC_TWAI_CONTROLLER_NUM         2
+#define SOC_TWAI_CLK_SUPPORT_XTAL       1
+#define SOC_TWAI_BRP_MIN                2
+#define SOC_TWAI_BRP_MAX                32768
+#define SOC_TWAI_SUPPORTS_RX_STATUS     1
+
+/*-------------------------- eFuse CAPS----------------------------*/
+#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
+#define SOC_EFUSE_DIS_PAD_JTAG 1
+#define SOC_EFUSE_DIS_USB_JTAG 1
+#define SOC_EFUSE_DIS_DIRECT_BOOT 1
+#define SOC_EFUSE_SOFT_DIS_JTAG 1
+
+/*-------------------------- Secure Boot CAPS----------------------------*/
+#define SOC_SECURE_BOOT_V2_RSA              1
+#define SOC_SECURE_BOOT_V2_ECC              1
+#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
+#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS   1
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY  1
+
+/*-------------------------- Flash Encryption CAPS----------------------------*/
+#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (32)
+#define SOC_FLASH_ENCRYPTION_XTS_AES        1
+#define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
+
+/*-------------------------- MEMPROT CAPS ------------------------------------*/
+
+
+/*-------------------------- UART CAPS ---------------------------------------*/
+// ESP32-P4 has 2 UARTs
+#define SOC_UART_NUM                    (2)
+#define SOC_UART_HP_NUM                 (2)
+// #define SOC_UART_LP_NUM                 (1U)
+#define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
+#define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
+#define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */
+#define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
+#define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
+
+// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
+#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
+
+// TODO: IDF-5679 (Copy from esp32c3, need check)
+/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
+#define SOC_COEX_HW_PTI                 (1)
+
+/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
+#define SOC_PHY_DIG_REGS_MEM_SIZE       (21*4)
+
+// TODO: IDF-5679 (Copy from esp32c3, need check)
+/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
+#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
+
+// TODO: IDF-5351 (Copy from esp32c3, need check)
+/*-------------------------- Power Management CAPS ----------------------------*/
+#define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
+#define SOC_PM_SUPPORT_BT_WAKEUP        (1)
+#define SOC_PM_SUPPORT_CPU_PD           (1)
+#define SOC_PM_SUPPORT_MODEM_PD         (1)
+#define SOC_PM_SUPPORT_XTAL32K_PD       (1)
+#define SOC_PM_SUPPORT_RC32K_PD         (1)
+#define SOC_PM_SUPPORT_RC_FAST_PD       (1)
+#define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
+#define SOC_PM_SUPPORT_TOP_PD           (1)
+
+#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
+
+#define SOC_PM_CPU_RETENTION_BY_SW      (0)
+
+#define SOC_PM_PAU_LINK_NUM             (4)
+
+/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
+#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
+#define SOC_MODEM_CLOCK_IS_INDEPENDENT            (0)
+
+#define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
+#define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
+#define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
+
+/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                (1)
diff --git a/tools/test_apps/.build-test-rules.yml b/tools/test_apps/.build-test-rules.yml
index ab8b54c347..5752cbd62f 100644
--- a/tools/test_apps/.build-test-rules.yml
+++ b/tools/test_apps/.build-test-rules.yml
@@ -186,3 +186,7 @@ tools/test_apps/system/unicore_bootloader:
   enable:
     - if: SOC_CPU_CORES_NUM > 1
       reason: the test should be run on multicore chips
+  disable:
+    - if: IDF_TARGET in ["esp32p4"] # TODO: IDF-7692
+      temporary: true
+      reason: not supported on esp32p4 yet

From 0959c0cb96f8bc2c75585608e05e3aa1fa4e824a Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Thu, 29 Jun 2023 16:03:57 +0800
Subject: [PATCH 04/13] feat(soc): rename mspi registers

---
 .../soc/esp32p4/include/soc/dspi_mem_reg.h    | 2832 ------------
 components/soc/esp32p4/include/soc/reg_base.h |    4 +-
 components/soc/esp32p4/include/soc/soc.h      |    2 +-
 .../soc/esp32p4/include/soc/spi1_mem_c_reg.h  | 1958 ++++-----
 .../esp32p4/include/soc/spi1_mem_c_struct.h   |  312 +-
 .../soc/esp32p4/include/soc/spi1_mem_s_reg.h  | 1958 ++++-----
 .../esp32p4/include/soc/spi1_mem_s_struct.h   |  312 +-
 .../soc/esp32p4/include/soc/spi_mem_c_reg.h   | 3442 +++++++--------
 .../esp32p4/include/soc/spi_mem_c_struct.h    |  380 +-
 .../soc/esp32p4/include/soc/spi_mem_reg.h     |   12 +-
 .../soc/esp32p4/include/soc/spi_mem_s_reg.h   | 3910 ++++++++---------
 .../esp32p4/include/soc/spi_mem_s_struct.h    |  424 +-
 12 files changed, 6355 insertions(+), 9191 deletions(-)
 delete mode 100644 components/soc/esp32p4/include/soc/dspi_mem_reg.h

diff --git a/components/soc/esp32p4/include/soc/dspi_mem_reg.h b/components/soc/esp32p4/include/soc/dspi_mem_reg.h
deleted file mode 100644
index 229004612d..0000000000
--- a/components/soc/esp32p4/include/soc/dspi_mem_reg.h
+++ /dev/null
@@ -1,2832 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_DSPI_MEM_REG_H_
-#define _SOC_DSPI_MEM_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define DSPI_MEM_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x0)
-/* DSPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
-ion will be triggered when the bit is set. The bit will be cleared once the oper
-ation done.1: enable 0: disable..*/
-#define DSPI_MEM_USR    (BIT(18))
-#define DSPI_MEM_USR_M  (BIT(18))
-#define DSPI_MEM_USR_V  0x1
-#define DSPI_MEM_USR_S  18
-/* DSPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
-#define DSPI_MEM_SLV_ST    0x0000000F
-#define DSPI_MEM_SLV_ST_M  ((DSPI_MEM_SLV_ST_V)<<(DSPI_MEM_SLV_ST_S))
-#define DSPI_MEM_SLV_ST_V  0xF
-#define DSPI_MEM_SLV_ST_S  4
-/* DSPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
-, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
-nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
-#define DSPI_MEM_MST_ST    0x0000000F
-#define DSPI_MEM_MST_ST_M  ((DSPI_MEM_MST_ST_V)<<(DSPI_MEM_MST_ST_S))
-#define DSPI_MEM_MST_ST_V  0xF
-#define DSPI_MEM_MST_ST_S  0
-
-#define DSPI_MEM_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x8)
-/* DSPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
-lways 1. 0: Others..*/
-#define DSPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define DSPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define DSPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
-#define DSPI_MEM_DATA_IE_ALWAYS_ON_S  31
-/* DSPI_MEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
-s 1. 0: Others..*/
-#define DSPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define DSPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define DSPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
-#define DSPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/* DSPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
-ble 0: disable..*/
-#define DSPI_MEM_FREAD_QIO    (BIT(24))
-#define DSPI_MEM_FREAD_QIO_M  (BIT(24))
-#define DSPI_MEM_FREAD_QIO_V  0x1
-#define DSPI_MEM_FREAD_QIO_S  24
-/* DSPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
-ble 0: disable..*/
-#define DSPI_MEM_FREAD_DIO    (BIT(23))
-#define DSPI_MEM_FREAD_DIO_M  (BIT(23))
-#define DSPI_MEM_FREAD_DIO_V  0x1
-#define DSPI_MEM_FREAD_DIO_S  23
-/* DSPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
-#define DSPI_MEM_WP_REG    (BIT(21))
-#define DSPI_MEM_WP_REG_M  (BIT(21))
-#define DSPI_MEM_WP_REG_V  0x1
-#define DSPI_MEM_WP_REG_S  21
-/* DSPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_FREAD_QUAD    (BIT(20))
-#define DSPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define DSPI_MEM_FREAD_QUAD_V  0x1
-#define DSPI_MEM_FREAD_QUAD_S  20
-/* DSPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
-#define DSPI_MEM_D_POL    (BIT(19))
-#define DSPI_MEM_D_POL_M  (BIT(19))
-#define DSPI_MEM_D_POL_V  0x1
-#define DSPI_MEM_D_POL_S  19
-/* DSPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
-#define DSPI_MEM_Q_POL    (BIT(18))
-#define DSPI_MEM_Q_POL_M  (BIT(18))
-#define DSPI_MEM_Q_POL_V  0x1
-#define DSPI_MEM_Q_POL_S  18
-/* DSPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_FREAD_DUAL    (BIT(14))
-#define DSPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define DSPI_MEM_FREAD_DUAL_V  0x1
-#define DSPI_MEM_FREAD_DUAL_S  14
-/* DSPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
-UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
-#define DSPI_MEM_FASTRD_MODE    (BIT(13))
-#define DSPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define DSPI_MEM_FASTRD_MODE_V  0x1
-#define DSPI_MEM_FASTRD_MODE_S  13
-/* DSPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
-#define DSPI_MEM_FCMD_OCT    (BIT(9))
-#define DSPI_MEM_FCMD_OCT_M  (BIT(9))
-#define DSPI_MEM_FCMD_OCT_V  0x1
-#define DSPI_MEM_FCMD_OCT_S  9
-/* DSPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
-#define DSPI_MEM_FCMD_QUAD    (BIT(8))
-#define DSPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define DSPI_MEM_FCMD_QUAD_V  0x1
-#define DSPI_MEM_FCMD_QUAD_S  8
-/* DSPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
-#define DSPI_MEM_FADDR_OCT    (BIT(6))
-#define DSPI_MEM_FADDR_OCT_M  (BIT(6))
-#define DSPI_MEM_FADDR_OCT_V  0x1
-#define DSPI_MEM_FADDR_OCT_S  6
-/* DSPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
-#define DSPI_MEM_FDIN_OCT    (BIT(5))
-#define DSPI_MEM_FDIN_OCT_M  (BIT(5))
-#define DSPI_MEM_FDIN_OCT_V  0x1
-#define DSPI_MEM_FDIN_OCT_S  5
-/* DSPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
-#define DSPI_MEM_FDOUT_OCT    (BIT(4))
-#define DSPI_MEM_FDOUT_OCT_M  (BIT(4))
-#define DSPI_MEM_FDOUT_OCT_V  0x1
-#define DSPI_MEM_FDOUT_OCT_S  4
-/* DSPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
-is output by the MSPI controller in the second half part of dummy phase. It is u
-sed to pre-drive flash..*/
-#define DSPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define DSPI_MEM_FDUMMY_WOUT_M  (BIT(3))
-#define DSPI_MEM_FDUMMY_WOUT_V  0x1
-#define DSPI_MEM_FDUMMY_WOUT_S  3
-/* DSPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
-s output by the MSPI controller in the first half part of dummy phase. It is use
-d to mask invalid SPI_DQS in the half part of dummy phase..*/
-#define DSPI_MEM_FDUMMY_RIN    (BIT(2))
-#define DSPI_MEM_FDUMMY_RIN_M  (BIT(2))
-#define DSPI_MEM_FDUMMY_RIN_V  0x1
-#define DSPI_MEM_FDUMMY_RIN_S  2
-/* DSPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_IO[7:0] is output by the MSPI controller..*/
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/* DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_DQS is output by the MSPI controller..*/
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-
-#define DSPI_MEM_CTRL1_REG          (DR_REG_DSPI_MEM_BASE + 0xC)
-/* DSPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
- send signals to AXI. Set this bit to reset these FIFO..*/
-#define DSPI_MEM_TXFIFO_RST    (BIT(31))
-#define DSPI_MEM_TXFIFO_RST_M  (BIT(31))
-#define DSPI_MEM_TXFIFO_RST_V  0x1
-#define DSPI_MEM_TXFIFO_RST_S  31
-/* DSPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
- receive signals from AXI.  Set this bit to reset these FIFO..*/
-#define DSPI_MEM_RXFIFO_RST    (BIT(30))
-#define DSPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define DSPI_MEM_RXFIFO_RST_V  0x1
-#define DSPI_MEM_RXFIFO_RST_S  30
-/* DSPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
-bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
-in  tx_bus_fifo_l2..*/
-#define DSPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define DSPI_MEM_FAST_WRITE_EN_M  (BIT(29))
-#define DSPI_MEM_FAST_WRITE_EN_V  0x1
-#define DSPI_MEM_FAST_WRITE_EN_S  29
-/* DSPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
-the same time..*/
-#define DSPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define DSPI_MEM_DUAL_RAM_EN_M  (BIT(28))
-#define DSPI_MEM_DUAL_RAM_EN_V  0x1
-#define DSPI_MEM_DUAL_RAM_EN_S  28
-/* DSPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
-cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
-ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
-cessed at the same time..*/
-#define DSPI_MEM_RAM0_EN    (BIT(27))
-#define DSPI_MEM_RAM0_EN_M  (BIT(27))
-#define DSPI_MEM_RAM0_EN_V  0x1
-#define DSPI_MEM_RAM0_EN_S  27
-/* DSPI_MEM_AW_SPLICE_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Write Splice-transfer..*/
-#define DSPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define DSPI_MEM_AW_SPLICE_EN_M  (BIT(26))
-#define DSPI_MEM_AW_SPLICE_EN_V  0x1
-#define DSPI_MEM_AW_SPLICE_EN_S  26
-/* DSPI_MEM_AR_SPLICE_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Read Splice-transfer..*/
-#define DSPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define DSPI_MEM_AR_SPLICE_EN_M  (BIT(25))
-#define DSPI_MEM_AR_SPLICE_EN_V  0x1
-#define DSPI_MEM_AR_SPLICE_EN_S  25
-/* DSPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
- when there is a ECC error in AXI read data. The ECC error information is record
-ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
-#define DSPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define DSPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
-#define DSPI_MEM_RRESP_ECC_ERR_EN_V  0x1
-#define DSPI_MEM_RRESP_ECC_ERR_EN_S  24
-/* DSPI_MEM_SPI_AXI_RDATA_BACK_FAST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
-eply AXI read data to AXI bus when all the read data is available..*/
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST    (BIT(23))
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_M  (BIT(23))
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_V  0x1
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_S  23
-/* DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V  0x1
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S  22
-/* DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
-y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V  0x1
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S  21
-/* DSPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
-#define DSPI_MEM_CLK_MODE    0x00000003
-#define DSPI_MEM_CLK_MODE_M  ((DSPI_MEM_CLK_MODE_V)<<(DSPI_MEM_CLK_MODE_S))
-#define DSPI_MEM_CLK_MODE_V  0x3
-#define DSPI_MEM_CLK_MODE_S  0
-
-#define DSPI_MEM_CTRL2_REG          (DR_REG_DSPI_MEM_BASE + 0x10)
-/* DSPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
-#define DSPI_MEM_SYNC_RESET    (BIT(31))
-#define DSPI_MEM_SYNC_RESET_M  (BIT(31))
-#define DSPI_MEM_SYNC_RESET_V  0x1
-#define DSPI_MEM_SYNC_RESET_S  31
-/* DSPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
- clock cycles..*/
-#define DSPI_MEM_CS_HOLD_DELAY    0x0000003F
-#define DSPI_MEM_CS_HOLD_DELAY_M  ((DSPI_MEM_CS_HOLD_DELAY_V)<<(DSPI_MEM_CS_HOLD_DELAY_S))
-#define DSPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define DSPI_MEM_CS_HOLD_DELAY_S  25
-/* DSPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
-fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
-whether there is an ECC region or not..*/
-#define DSPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define DSPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
-#define DSPI_MEM_SPLIT_TRANS_EN_V  0x1
-#define DSPI_MEM_SPLIT_TRANS_EN_S  24
-/* DSPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses flash..*/
-#define DSPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define DSPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
-#define DSPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
-#define DSPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/* DSPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
-hen accesses flash..*/
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/* DSPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
- mode when accessed flash..*/
-#define DSPI_MEM_ECC_CS_HOLD_TIME    0x00000007
-#define DSPI_MEM_ECC_CS_HOLD_TIME_M  ((DSPI_MEM_ECC_CS_HOLD_TIME_V)<<(DSPI_MEM_ECC_CS_HOLD_TIME_S))
-#define DSPI_MEM_ECC_CS_HOLD_TIME_V  0x7
-#define DSPI_MEM_ECC_CS_HOLD_TIME_S  10
-/* DSPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
-th SPI_MEM_CS_HOLD bit..*/
-#define DSPI_MEM_CS_HOLD_TIME    0x0000001F
-#define DSPI_MEM_CS_HOLD_TIME_M  ((DSPI_MEM_CS_HOLD_TIME_V)<<(DSPI_MEM_CS_HOLD_TIME_S))
-#define DSPI_MEM_CS_HOLD_TIME_V  0x1F
-#define DSPI_MEM_CS_HOLD_TIME_S  5
-/* DSPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
-M_CS_SETUP bit..*/
-#define DSPI_MEM_CS_SETUP_TIME    0x0000001F
-#define DSPI_MEM_CS_SETUP_TIME_M  ((DSPI_MEM_CS_SETUP_TIME_V)<<(DSPI_MEM_CS_SETUP_TIME_S))
-#define DSPI_MEM_CS_SETUP_TIME_V  0x1F
-#define DSPI_MEM_CS_SETUP_TIME_S  0
-
-#define DSPI_MEM_CLOCK_REG          (DR_REG_DSPI_MEM_BASE + 0x14)
-/* DSPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
- clock..*/
-#define DSPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define DSPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define DSPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define DSPI_MEM_CLK_EQU_SYSCLK_S  31
-/* DSPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- system/(spi_mem_clkcnt_N+1).*/
-#define DSPI_MEM_CLKCNT_N    0x000000FF
-#define DSPI_MEM_CLKCNT_N_M  ((DSPI_MEM_CLKCNT_N_V)<<(DSPI_MEM_CLKCNT_N_S))
-#define DSPI_MEM_CLKCNT_N_V  0xFF
-#define DSPI_MEM_CLKCNT_N_S  16
-/* DSPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define DSPI_MEM_CLKCNT_H    0x000000FF
-#define DSPI_MEM_CLKCNT_H_M  ((DSPI_MEM_CLKCNT_H_V)<<(DSPI_MEM_CLKCNT_H_S))
-#define DSPI_MEM_CLKCNT_H_V  0xFF
-#define DSPI_MEM_CLKCNT_H_S  8
-/* DSPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
-#define DSPI_MEM_CLKCNT_L    0x000000FF
-#define DSPI_MEM_CLKCNT_L_M  ((DSPI_MEM_CLKCNT_L_V)<<(DSPI_MEM_CLKCNT_L_S))
-#define DSPI_MEM_CLKCNT_L_V  0xFF
-#define DSPI_MEM_CLKCNT_L_S  0
-
-#define DSPI_MEM_USER_REG          (DR_REG_DSPI_MEM_BASE + 0x18)
-/* DSPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation..*/
-#define DSPI_MEM_USR_DUMMY    (BIT(29))
-#define DSPI_MEM_USR_DUMMY_M  (BIT(29))
-#define DSPI_MEM_USR_DUMMY_V  0x1
-#define DSPI_MEM_USR_DUMMY_S  29
-/* DSPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable..*/
-#define DSPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define DSPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define DSPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define DSPI_MEM_USR_DUMMY_IDLE_S  26
-/* DSPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
-#define DSPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define DSPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define DSPI_MEM_CK_OUT_EDGE_V  0x1
-#define DSPI_MEM_CK_OUT_EDGE_S  9
-/* DSPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
-#define DSPI_MEM_CS_SETUP    (BIT(7))
-#define DSPI_MEM_CS_SETUP_M  (BIT(7))
-#define DSPI_MEM_CS_SETUP_V  0x1
-#define DSPI_MEM_CS_SETUP_S  7
-/* DSPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
-#define DSPI_MEM_CS_HOLD    (BIT(6))
-#define DSPI_MEM_CS_HOLD_M  (BIT(6))
-#define DSPI_MEM_CS_HOLD_V  0x1
-#define DSPI_MEM_CS_HOLD_S  6
-
-#define DSPI_MEM_USER1_REG          (DR_REG_DSPI_MEM_BASE + 0x1C)
-/* DSPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_USR_ADDR_BITLEN    0x0000003F
-#define DSPI_MEM_USR_ADDR_BITLEN_M  ((DSPI_MEM_USR_ADDR_BITLEN_V)<<(DSPI_MEM_USR_ADDR_BITLEN_S))
-#define DSPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define DSPI_MEM_USR_ADDR_BITLEN_S  26
-/* DSPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
-/*description: SPI0 USR_CMD read or write data byte length -1.*/
-#define DSPI_MEM_USR_DBYTELEN    0x00000007
-#define DSPI_MEM_USR_DBYTELEN_M  ((DSPI_MEM_USR_DBYTELEN_V)<<(DSPI_MEM_USR_DBYTELEN_S))
-#define DSPI_MEM_USR_DBYTELEN_V  0x7
-#define DSPI_MEM_USR_DBYTELEN_S  6
-/* DSPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
-cle_num-1)..*/
-#define DSPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
-#define DSPI_MEM_USR_DUMMY_CYCLELEN_M  ((DSPI_MEM_USR_DUMMY_CYCLELEN_V)<<(DSPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define DSPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define DSPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define DSPI_MEM_USER2_REG          (DR_REG_DSPI_MEM_BASE + 0x20)
-/* DSPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
-#define DSPI_MEM_USR_COMMAND_BITLEN    0x0000000F
-#define DSPI_MEM_USR_COMMAND_BITLEN_M  ((DSPI_MEM_USR_COMMAND_BITLEN_V)<<(DSPI_MEM_USR_COMMAND_BITLEN_S))
-#define DSPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define DSPI_MEM_USR_COMMAND_BITLEN_S  28
-/* DSPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command..*/
-#define DSPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
-#define DSPI_MEM_USR_COMMAND_VALUE_M  ((DSPI_MEM_USR_COMMAND_VALUE_V)<<(DSPI_MEM_USR_COMMAND_VALUE_S))
-#define DSPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define DSPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define DSPI_MEM_RD_STATUS_REG          (DR_REG_DSPI_MEM_BASE + 0x2C)
-/* DSPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
-it..*/
-#define DSPI_MEM_WB_MODE    0x000000FF
-#define DSPI_MEM_WB_MODE_M  ((DSPI_MEM_WB_MODE_V)<<(DSPI_MEM_WB_MODE_S))
-#define DSPI_MEM_WB_MODE_V  0xFF
-#define DSPI_MEM_WB_MODE_S  16
-
-#define DSPI_MEM_MISC_REG          (DR_REG_DSPI_MEM_BASE + 0x34)
-/* DSPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: SPI_CS line keep low when the bit is set..*/
-#define DSPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define DSPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define DSPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define DSPI_MEM_CS_KEEP_ACTIVE_S  10
-/* DSPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
-#define DSPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define DSPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define DSPI_MEM_CK_IDLE_EDGE_V  0x1
-#define DSPI_MEM_CK_IDLE_EDGE_S  9
-/* DSPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0,  sram is connected to SUBPINs..*/
-#define DSPI_MEM_SSUB_PIN    (BIT(8))
-#define DSPI_MEM_SSUB_PIN_M  (BIT(8))
-#define DSPI_MEM_SSUB_PIN_V  0x1
-#define DSPI_MEM_SSUB_PIN_S  8
-/* DSPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0,  flash is connected to SUBPINs..*/
-#define DSPI_MEM_FSUB_PIN    (BIT(7))
-#define DSPI_MEM_FSUB_PIN_M  (BIT(7))
-#define DSPI_MEM_FSUB_PIN_V  0x1
-#define DSPI_MEM_FSUB_PIN_S  7
-
-#define DSPI_MEM_CACHE_FCTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x3C)
-/* DSPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
-_ERR will be replied to BRESP/RRESP..*/
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN    (BIT(31))
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_M  (BIT(31))
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_V  0x1
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_S  31
-/* DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: Set this bit to check AXI read/write the same address region..*/
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x1
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
-/* DSPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_qio..*/
-#define DSPI_MEM_FADDR_QUAD    (BIT(8))
-#define DSPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define DSPI_MEM_FADDR_QUAD_V  0x1
-#define DSPI_MEM_FADDR_QUAD_S  8
-/* DSPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
-e same with spi_mem_fread_qio..*/
-#define DSPI_MEM_FDOUT_QUAD    (BIT(7))
-#define DSPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define DSPI_MEM_FDOUT_QUAD_V  0x1
-#define DSPI_MEM_FDOUT_QUAD_S  7
-/* DSPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
- same with spi_mem_fread_qio..*/
-#define DSPI_MEM_FDIN_QUAD    (BIT(6))
-#define DSPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define DSPI_MEM_FDIN_QUAD_V  0x1
-#define DSPI_MEM_FDIN_QUAD_S  6
-/* DSPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_dio..*/
-#define DSPI_MEM_FADDR_DUAL    (BIT(5))
-#define DSPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define DSPI_MEM_FADDR_DUAL_V  0x1
-#define DSPI_MEM_FADDR_DUAL_S  5
-/* DSPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
- same with spi_mem_fread_dio..*/
-#define DSPI_MEM_FDOUT_DUAL    (BIT(4))
-#define DSPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define DSPI_MEM_FDOUT_DUAL_V  0x1
-#define DSPI_MEM_FDOUT_DUAL_S  4
-/* DSPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-same with spi_mem_fread_dio..*/
-#define DSPI_MEM_FDIN_DUAL    (BIT(3))
-#define DSPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define DSPI_MEM_FDIN_DUAL_V  0x1
-#define DSPI_MEM_FDIN_DUAL_S  3
-/* DSPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
-#define DSPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
-#define DSPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define DSPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define DSPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* DSPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/* DSPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
-#define DSPI_MEM_AXI_REQ_EN    (BIT(0))
-#define DSPI_MEM_AXI_REQ_EN_M  (BIT(0))
-#define DSPI_MEM_AXI_REQ_EN_V  0x1
-#define DSPI_MEM_AXI_REQ_EN_S  0
-
-#define DSPI_MEM_CACHE_SCTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x40)
-/* DSPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
-e. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
-/* DSPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: reserved.*/
-#define DSPI_MEM_SRAM_OCT    (BIT(21))
-#define DSPI_MEM_SRAM_OCT_M  (BIT(21))
-#define DSPI_MEM_SRAM_OCT_V  0x1
-#define DSPI_MEM_SRAM_OCT_S  21
-/* DSPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_S  20
-/* DSPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
-he register value shall be (bit_num-1)..*/
-#define DSPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
-#define DSPI_MEM_SRAM_ADDR_BITLEN_M  ((DSPI_MEM_SRAM_ADDR_BITLEN_V)<<(DSPI_MEM_SRAM_ADDR_BITLEN_S))
-#define DSPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
-#define DSPI_MEM_SRAM_ADDR_BITLEN_S  14
-/* DSPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
-. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
-/* DSPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
-nd..*/
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_S  5
-/* DSPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
- operations..*/
-#define DSPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
-#define DSPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
-#define DSPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
-#define DSPI_MEM_USR_RD_SRAM_DUMMY_S  4
-/* DSPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
-e operations..*/
-#define DSPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
-#define DSPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
-#define DSPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
-#define DSPI_MEM_USR_WR_SRAM_DUMMY_S  3
-/* DSPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
-le.*/
-#define DSPI_MEM_USR_SRAM_QIO    (BIT(2))
-#define DSPI_MEM_USR_SRAM_QIO_M  (BIT(2))
-#define DSPI_MEM_USR_SRAM_QIO_V  0x1
-#define DSPI_MEM_USR_SRAM_QIO_S  2
-/* DSPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
-le.*/
-#define DSPI_MEM_USR_SRAM_DIO    (BIT(1))
-#define DSPI_MEM_USR_SRAM_DIO_M  (BIT(1))
-#define DSPI_MEM_USR_SRAM_DIO_V  0x1
-#define DSPI_MEM_USR_SRAM_DIO_S  1
-/* DSPI_MEM_CACHE_USR_SADDR_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
-able, 0:disable..*/
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
-
-#define DSPI_MEM_SRAM_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x44)
-/* DSPI_SMEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
-] are always 1. 0: Others..*/
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_V  0x1
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_S  31
-/* DSPI_SMEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
-e always 1. 0: Others..*/
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_V  0x1
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_S  30
-/* DSPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDOUT_HEX    (BIT(27))
-#define DSPI_MEM_SDOUT_HEX_M  (BIT(27))
-#define DSPI_MEM_SDOUT_HEX_V  0x1
-#define DSPI_MEM_SDOUT_HEX_S  27
-/* DSPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDIN_HEX    (BIT(26))
-#define DSPI_MEM_SDIN_HEX_M  (BIT(26))
-#define DSPI_MEM_SDIN_HEX_V  0x1
-#define DSPI_MEM_SDIN_HEX_S  26
-/* DSPI_SMEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_IO[7:0] is output by the MSPI controller..*/
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/* DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_DQS is output by the MSPI controller..*/
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/* DSPI_MEM_SDUMMY_WOUT : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
-the signal level of SPI bus is output by the MSPI controller..*/
-#define DSPI_MEM_SDUMMY_WOUT    (BIT(23))
-#define DSPI_MEM_SDUMMY_WOUT_M  (BIT(23))
-#define DSPI_MEM_SDUMMY_WOUT_V  0x1
-#define DSPI_MEM_SDUMMY_WOUT_S  23
-/* DSPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
-he signal level of SPI bus is output by the MSPI controller..*/
-#define DSPI_MEM_SDUMMY_RIN    (BIT(22))
-#define DSPI_MEM_SDUMMY_RIN_M  (BIT(22))
-#define DSPI_MEM_SDUMMY_RIN_V  0x1
-#define DSPI_MEM_SDUMMY_RIN_S  22
-/* DSPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SCMD_OCT    (BIT(21))
-#define DSPI_MEM_SCMD_OCT_M  (BIT(21))
-#define DSPI_MEM_SCMD_OCT_V  0x1
-#define DSPI_MEM_SCMD_OCT_S  21
-/* DSPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SADDR_OCT    (BIT(20))
-#define DSPI_MEM_SADDR_OCT_M  (BIT(20))
-#define DSPI_MEM_SADDR_OCT_V  0x1
-#define DSPI_MEM_SADDR_OCT_S  20
-/* DSPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDOUT_OCT    (BIT(19))
-#define DSPI_MEM_SDOUT_OCT_M  (BIT(19))
-#define DSPI_MEM_SDOUT_OCT_V  0x1
-#define DSPI_MEM_SDOUT_OCT_S  19
-/* DSPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDIN_OCT    (BIT(18))
-#define DSPI_MEM_SDIN_OCT_M  (BIT(18))
-#define DSPI_MEM_SDIN_OCT_V  0x1
-#define DSPI_MEM_SDIN_OCT_S  18
-/* DSPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SCMD_QUAD    (BIT(17))
-#define DSPI_MEM_SCMD_QUAD_M  (BIT(17))
-#define DSPI_MEM_SCMD_QUAD_V  0x1
-#define DSPI_MEM_SCMD_QUAD_S  17
-/* DSPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SADDR_QUAD    (BIT(16))
-#define DSPI_MEM_SADDR_QUAD_M  (BIT(16))
-#define DSPI_MEM_SADDR_QUAD_V  0x1
-#define DSPI_MEM_SADDR_QUAD_S  16
-/* DSPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SDOUT_QUAD    (BIT(15))
-#define DSPI_MEM_SDOUT_QUAD_M  (BIT(15))
-#define DSPI_MEM_SDOUT_QUAD_V  0x1
-#define DSPI_MEM_SDOUT_QUAD_S  15
-/* DSPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SDIN_QUAD    (BIT(14))
-#define DSPI_MEM_SDIN_QUAD_M  (BIT(14))
-#define DSPI_MEM_SDIN_QUAD_V  0x1
-#define DSPI_MEM_SDIN_QUAD_S  14
-/* DSPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_dio..*/
-#define DSPI_MEM_SADDR_DUAL    (BIT(12))
-#define DSPI_MEM_SADDR_DUAL_M  (BIT(12))
-#define DSPI_MEM_SADDR_DUAL_V  0x1
-#define DSPI_MEM_SADDR_DUAL_S  12
-/* DSPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_dio..*/
-#define DSPI_MEM_SDOUT_DUAL    (BIT(11))
-#define DSPI_MEM_SDOUT_DUAL_M  (BIT(11))
-#define DSPI_MEM_SDOUT_DUAL_V  0x1
-#define DSPI_MEM_SDOUT_DUAL_S  11
-/* DSPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_dio..*/
-#define DSPI_MEM_SDIN_DUAL    (BIT(10))
-#define DSPI_MEM_SDIN_DUAL_M  (BIT(10))
-#define DSPI_MEM_SDIN_DUAL_V  0x1
-#define DSPI_MEM_SDIN_DUAL_S  10
-/* DSPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
-/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
-_mode bit..*/
-#define DSPI_MEM_SWB_MODE    0x000000FF
-#define DSPI_MEM_SWB_MODE_M  ((DSPI_MEM_SWB_MODE_V)<<(DSPI_MEM_SWB_MODE_S))
-#define DSPI_MEM_SWB_MODE_V  0xFF
-#define DSPI_MEM_SWB_MODE_S  2
-/* DSPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is always on..*/
-#define DSPI_MEM_SCLK_MODE    0x00000003
-#define DSPI_MEM_SCLK_MODE_M  ((DSPI_MEM_SCLK_MODE_V)<<(DSPI_MEM_SCLK_MODE_S))
-#define DSPI_MEM_SCLK_MODE_V  0x3
-#define DSPI_MEM_SCLK_MODE_S  0
-
-#define DSPI_MEM_SRAM_DRD_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x48)
-/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
- sram. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
-/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the read command value of command phase
- for sram..*/
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
-
-#define DSPI_MEM_SRAM_DWR_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x4C)
-/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
- The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
-/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the write command value of command phas
-e for sram..*/
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
-
-#define DSPI_MEM_SRAM_CLK_REG          (DR_REG_DSPI_MEM_BASE + 0x50)
-/* DSPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
-lk is divided from system clock..*/
-#define DSPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
-#define DSPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
-#define DSPI_MEM_SCLK_EQU_SYSCLK_V  0x1
-#define DSPI_MEM_SCLK_EQU_SYSCLK_S  31
-/* DSPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
-lk frequency is system/(spi_mem_clkcnt_N+1).*/
-#define DSPI_MEM_SCLKCNT_N    0x000000FF
-#define DSPI_MEM_SCLKCNT_N_M  ((DSPI_MEM_SCLKCNT_N_V)<<(DSPI_MEM_SCLKCNT_N_S))
-#define DSPI_MEM_SCLKCNT_N_V  0xFF
-#define DSPI_MEM_SCLKCNT_N_S  16
-/* DSPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define DSPI_MEM_SCLKCNT_H    0x000000FF
-#define DSPI_MEM_SCLKCNT_H_M  ((DSPI_MEM_SCLKCNT_H_V)<<(DSPI_MEM_SCLKCNT_H_S))
-#define DSPI_MEM_SCLKCNT_H_V  0xFF
-#define DSPI_MEM_SCLKCNT_H_S  8
-/* DSPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
-#define DSPI_MEM_SCLKCNT_L    0x000000FF
-#define DSPI_MEM_SCLKCNT_L_M  ((DSPI_MEM_SCLKCNT_L_V)<<(DSPI_MEM_SCLKCNT_L_S))
-#define DSPI_MEM_SCLKCNT_L_V  0xFF
-#define DSPI_MEM_SCLKCNT_L_S  0
-
-#define DSPI_MEM_FSM_REG          (DR_REG_DSPI_MEM_BASE + 0x54)
-/* DSPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
-/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
-#define DSPI_MEM_LOCK_DELAY_TIME    0x0000001F
-#define DSPI_MEM_LOCK_DELAY_TIME_M  ((DSPI_MEM_LOCK_DELAY_TIME_V)<<(DSPI_MEM_LOCK_DELAY_TIME_S))
-#define DSPI_MEM_LOCK_DELAY_TIME_V  0x1F
-#define DSPI_MEM_LOCK_DELAY_TIME_S  7
-
-#define DSPI_MEM_INT_ENA_REG          (DR_REG_DSPI_MEM_BASE + 0xC0)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/* DSPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define DSPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ENA_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_ENA_S  6
-/* DSPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define DSPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_ENA_S  5
-/* DSPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define DSPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ENA_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_ENA_S  4
-/* DSPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define DSPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ENA_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_ENA_S  3
-
-#define DSPI_MEM_INT_CLR_REG          (DR_REG_DSPI_MEM_BASE + 0xC4)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/* DSPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define DSPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_CLR_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_CLR_S  6
-/* DSPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define DSPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_CLR_S  5
-/* DSPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define DSPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_CLR_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_CLR_S  4
-/* DSPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define DSPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_CLR_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_CLR_S  3
-
-#define DSPI_MEM_INT_RAW_REG          (DR_REG_DSPI_MEM_BASE + 0xC8)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO
- is underflow..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO
- is underflow..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
-O connected to SPI_DQS is overflow..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
-O connected to SPI_DQS1 is overflow..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
- address is invalid by compared to MMU configuration. 0: Others..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
-ite flash request is received. 0: Others..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
-address is invalid by compared to MMU configuration. 0: Others..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/* DSPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
-is rejected. 0: Others..*/
-#define DSPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_RAW_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_RAW_S  6
-/* DSPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
-et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
- times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
-. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
-his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
-ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
-I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
-of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
-d, this bit will not be triggered..*/
-#define DSPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_RAW_S  5
-/* DSPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
-is changed from non idle state to idle state. 0: Others..*/
-#define DSPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_RAW_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_RAW_S  4
-/* DSPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
-is changed from non idle state to idle state. It means that SPI_CS raises high.
-0: Others.*/
-#define DSPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_RAW_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_RAW_S  3
-
-#define DSPI_MEM_INT_ST_REG          (DR_REG_DSPI_MEM_BASE + 0xCC)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/* DSPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define DSPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ST_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_ST_S  6
-/* DSPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define DSPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ST_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_ST_S  5
-/* DSPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define DSPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ST_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_ST_S  4
-/* DSPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define DSPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ST_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_ST_S  3
-
-#define DSPI_MEM_DDR_REG          (DR_REG_DSPI_MEM_BASE + 0xD4)
-/* DSPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
-#define DSPI_FMEM_HYPERBUS_CA    (BIT(30))
-#define DSPI_FMEM_HYPERBUS_CA_M  (BIT(30))
-#define DSPI_FMEM_HYPERBUS_CA_V  0x1
-#define DSPI_FMEM_HYPERBUS_CA_S  30
-/* DSPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
-..*/
-#define DSPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define DSPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define DSPI_FMEM_OCTA_RAM_ADDR_V  0x1
-#define DSPI_FMEM_OCTA_RAM_ADDR_S  29
-/* DSPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
-#define DSPI_FMEM_CLK_DIFF_INV    (BIT(28))
-#define DSPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
-#define DSPI_FMEM_CLK_DIFF_INV_V  0x1
-#define DSPI_FMEM_CLK_DIFF_INV_S  28
-/* DSPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_S  27
-/* DSPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define DSPI_FMEM_DQS_CA_IN    (BIT(26))
-#define DSPI_FMEM_DQS_CA_IN_M  (BIT(26))
-#define DSPI_FMEM_DQS_CA_IN_V  0x1
-#define DSPI_FMEM_DQS_CA_IN_S  26
-/* DSPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define DSPI_FMEM_CLK_DIFF_EN    (BIT(24))
-#define DSPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
-#define DSPI_FMEM_CLK_DIFF_EN_V  0x1
-#define DSPI_FMEM_CLK_DIFF_EN_S  24
-/* DSPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define DSPI_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define DSPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define DSPI_FMEM_DDR_DQS_LOOP_V  0x1
-#define DSPI_FMEM_DDR_DQS_LOOP_S  21
-/* DSPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define DSPI_FMEM_USR_DDR_DQS_THD    0x0000007F
-#define DSPI_FMEM_USR_DDR_DQS_THD_M  ((DSPI_FMEM_USR_DDR_DQS_THD_V)<<(DSPI_FMEM_USR_DDR_DQS_THD_S))
-#define DSPI_FMEM_USR_DDR_DQS_THD_V  0x7F
-#define DSPI_FMEM_USR_DDR_DQS_THD_S  14
-/* DSPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to flash..*/
-#define DSPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define DSPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define DSPI_FMEM_RX_DDR_MSK_EN_V  0x1
-#define DSPI_FMEM_RX_DDR_MSK_EN_S  13
-/* DSPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to flash..*/
-#define DSPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define DSPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define DSPI_FMEM_TX_DDR_MSK_EN_V  0x1
-#define DSPI_FMEM_TX_DDR_MSK_EN_S  12
-/* DSPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the panda device..*/
-#define DSPI_FMEM_OUTMINBYTELEN    0x0000007F
-#define DSPI_FMEM_OUTMINBYTELEN_M  ((DSPI_FMEM_OUTMINBYTELEN_V)<<(DSPI_FMEM_OUTMINBYTELEN_S))
-#define DSPI_FMEM_OUTMINBYTELEN_V  0x7F
-#define DSPI_FMEM_OUTMINBYTELEN_S  5
-/* DSPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define DSPI_FMEM_DDR_CMD_DIS    (BIT(4))
-#define DSPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
-#define DSPI_FMEM_DDR_CMD_DIS_V  0x1
-#define DSPI_FMEM_DDR_CMD_DIS_S  4
-/* DSPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define DSPI_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define DSPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define DSPI_FMEM_DDR_WDAT_SWP_V  0x1
-#define DSPI_FMEM_DDR_WDAT_SWP_S  3
-/* DSPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define DSPI_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define DSPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define DSPI_FMEM_DDR_RDAT_SWP_V  0x1
-#define DSPI_FMEM_DDR_RDAT_SWP_S  2
-/* DSPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define DSPI_FMEM_VAR_DUMMY    (BIT(1))
-#define DSPI_FMEM_VAR_DUMMY_M  (BIT(1))
-#define DSPI_FMEM_VAR_DUMMY_V  0x1
-#define DSPI_FMEM_VAR_DUMMY_S  1
-/* DSPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define DSPI_FMEM_DDR_EN    (BIT(0))
-#define DSPI_FMEM_DDR_EN_M  (BIT(0))
-#define DSPI_FMEM_DDR_EN_V  0x1
-#define DSPI_FMEM_DDR_EN_S  0
-
-#define DSPI_SMEM_DDR_REG          (DR_REG_DSPI_MEM_BASE + 0xD8)
-/* DSPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
-]}..*/
-#define DSPI_SMEM_HYPERBUS_CA    (BIT(30))
-#define DSPI_SMEM_HYPERBUS_CA_M  (BIT(30))
-#define DSPI_SMEM_HYPERBUS_CA_V  0x1
-#define DSPI_SMEM_HYPERBUS_CA_S  30
-/* DSPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
-, 1'b0}..*/
-#define DSPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define DSPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define DSPI_SMEM_OCTA_RAM_ADDR_V  0x1
-#define DSPI_SMEM_OCTA_RAM_ADDR_S  29
-/* DSPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
-#define DSPI_SMEM_CLK_DIFF_INV    (BIT(28))
-#define DSPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
-#define DSPI_SMEM_CLK_DIFF_INV_V  0x1
-#define DSPI_SMEM_CLK_DIFF_INV_S  28
-/* DSPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_S  27
-/* DSPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define DSPI_SMEM_DQS_CA_IN    (BIT(26))
-#define DSPI_SMEM_DQS_CA_IN_M  (BIT(26))
-#define DSPI_SMEM_DQS_CA_IN_V  0x1
-#define DSPI_SMEM_DQS_CA_IN_S  26
-/* DSPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define DSPI_SMEM_CLK_DIFF_EN    (BIT(24))
-#define DSPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
-#define DSPI_SMEM_CLK_DIFF_EN_V  0x1
-#define DSPI_SMEM_CLK_DIFF_EN_S  24
-/* DSPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define DSPI_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define DSPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define DSPI_SMEM_DDR_DQS_LOOP_V  0x1
-#define DSPI_SMEM_DDR_DQS_LOOP_S  21
-/* DSPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define DSPI_SMEM_USR_DDR_DQS_THD    0x0000007F
-#define DSPI_SMEM_USR_DDR_DQS_THD_M  ((DSPI_SMEM_USR_DDR_DQS_THD_V)<<(DSPI_SMEM_USR_DDR_DQS_THD_S))
-#define DSPI_SMEM_USR_DDR_DQS_THD_V  0x7F
-#define DSPI_SMEM_USR_DDR_DQS_THD_S  14
-/* DSPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to external RAM..*/
-#define DSPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define DSPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define DSPI_SMEM_RX_DDR_MSK_EN_V  0x1
-#define DSPI_SMEM_RX_DDR_MSK_EN_S  13
-/* DSPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to external RAM..*/
-#define DSPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define DSPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define DSPI_SMEM_TX_DDR_MSK_EN_V  0x1
-#define DSPI_SMEM_TX_DDR_MSK_EN_S  12
-/* DSPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the DDR psram..*/
-#define DSPI_SMEM_OUTMINBYTELEN    0x0000007F
-#define DSPI_SMEM_OUTMINBYTELEN_M  ((DSPI_SMEM_OUTMINBYTELEN_V)<<(DSPI_SMEM_OUTMINBYTELEN_S))
-#define DSPI_SMEM_OUTMINBYTELEN_V  0x7F
-#define DSPI_SMEM_OUTMINBYTELEN_S  5
-/* DSPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define DSPI_SMEM_DDR_CMD_DIS    (BIT(4))
-#define DSPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
-#define DSPI_SMEM_DDR_CMD_DIS_V  0x1
-#define DSPI_SMEM_DDR_CMD_DIS_S  4
-/* DSPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define DSPI_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define DSPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define DSPI_SMEM_DDR_WDAT_SWP_V  0x1
-#define DSPI_SMEM_DDR_WDAT_SWP_S  3
-/* DSPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define DSPI_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define DSPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define DSPI_SMEM_DDR_RDAT_SWP_V  0x1
-#define DSPI_SMEM_DDR_RDAT_SWP_S  2
-/* DSPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define DSPI_SMEM_VAR_DUMMY    (BIT(1))
-#define DSPI_SMEM_VAR_DUMMY_M  (BIT(1))
-#define DSPI_SMEM_VAR_DUMMY_V  0x1
-#define DSPI_SMEM_VAR_DUMMY_S  1
-/* DSPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define DSPI_SMEM_DDR_EN    (BIT(0))
-#define DSPI_SMEM_DDR_EN_M  (BIT(0))
-#define DSPI_SMEM_DDR_EN_V  0x1
-#define DSPI_SMEM_DDR_EN_S  0
-
-#define DSPI_FMEM_PMS0_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x100)
-/* DSPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS0_ECC    (BIT(2))
-#define DSPI_FMEM_PMS0_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS0_ECC_V  0x1
-#define DSPI_FMEM_PMS0_ECC_S  2
-/* DSPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS0_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS0_WR_ATTR_S  1
-/* DSPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS0_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS0_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS1_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x104)
-/* DSPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS1_ECC    (BIT(2))
-#define DSPI_FMEM_PMS1_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS1_ECC_V  0x1
-#define DSPI_FMEM_PMS1_ECC_S  2
-/* DSPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS1_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS1_WR_ATTR_S  1
-/* DSPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS1_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS1_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS2_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x108)
-/* DSPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS2_ECC    (BIT(2))
-#define DSPI_FMEM_PMS2_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS2_ECC_V  0x1
-#define DSPI_FMEM_PMS2_ECC_S  2
-/* DSPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS2_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS2_WR_ATTR_S  1
-/* DSPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS2_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS2_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS3_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x10C)
-/* DSPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS3_ECC    (BIT(2))
-#define DSPI_FMEM_PMS3_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS3_ECC_V  0x1
-#define DSPI_FMEM_PMS3_ECC_S  2
-/* DSPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS3_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS3_WR_ATTR_S  1
-/* DSPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS3_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS3_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS0_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x110)
-/* DSPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS0_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS0_ADDR_S_M  ((DSPI_FMEM_PMS0_ADDR_S_V)<<(DSPI_FMEM_PMS0_ADDR_S_S))
-#define DSPI_FMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS0_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS1_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x114)
-/* DSPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS1_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS1_ADDR_S_M  ((DSPI_FMEM_PMS1_ADDR_S_V)<<(DSPI_FMEM_PMS1_ADDR_S_S))
-#define DSPI_FMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS1_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS2_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x118)
-/* DSPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS2_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS2_ADDR_S_M  ((DSPI_FMEM_PMS2_ADDR_S_V)<<(DSPI_FMEM_PMS2_ADDR_S_S))
-#define DSPI_FMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS2_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS3_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x11C)
-/* DSPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS3_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS3_ADDR_S_M  ((DSPI_FMEM_PMS3_ADDR_S_V)<<(DSPI_FMEM_PMS3_ADDR_S_S))
-#define DSPI_FMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS3_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS0_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x120)
-/* DSPI_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS0_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS0_SIZE_M  ((DSPI_FMEM_PMS0_SIZE_V)<<(DSPI_FMEM_PMS0_SIZE_S))
-#define DSPI_FMEM_PMS0_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS0_SIZE_S  0
-
-#define DSPI_FMEM_PMS1_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x124)
-/* DSPI_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS1_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS1_SIZE_M  ((DSPI_FMEM_PMS1_SIZE_V)<<(DSPI_FMEM_PMS1_SIZE_S))
-#define DSPI_FMEM_PMS1_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS1_SIZE_S  0
-
-#define DSPI_FMEM_PMS2_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x128)
-/* DSPI_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS2_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS2_SIZE_M  ((DSPI_FMEM_PMS2_SIZE_V)<<(DSPI_FMEM_PMS2_SIZE_S))
-#define DSPI_FMEM_PMS2_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS2_SIZE_S  0
-
-#define DSPI_FMEM_PMS3_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x12C)
-/* DSPI_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS3_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS3_SIZE_M  ((DSPI_FMEM_PMS3_SIZE_V)<<(DSPI_FMEM_PMS3_SIZE_S))
-#define DSPI_FMEM_PMS3_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS3_SIZE_S  0
-
-#define DSPI_SMEM_PMS0_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x130)
-/* DSPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS0_ECC    (BIT(2))
-#define DSPI_SMEM_PMS0_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS0_ECC_V  0x1
-#define DSPI_SMEM_PMS0_ECC_S  2
-/* DSPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS0_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS0_WR_ATTR_S  1
-/* DSPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS0_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS0_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS1_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x134)
-/* DSPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS1_ECC    (BIT(2))
-#define DSPI_SMEM_PMS1_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS1_ECC_V  0x1
-#define DSPI_SMEM_PMS1_ECC_S  2
-/* DSPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS1_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS1_WR_ATTR_S  1
-/* DSPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS1_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS1_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS2_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x138)
-/* DSPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS2_ECC    (BIT(2))
-#define DSPI_SMEM_PMS2_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS2_ECC_V  0x1
-#define DSPI_SMEM_PMS2_ECC_S  2
-/* DSPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS2_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS2_WR_ATTR_S  1
-/* DSPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS2_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS2_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS3_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x13C)
-/* DSPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS3_ECC    (BIT(2))
-#define DSPI_SMEM_PMS3_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS3_ECC_V  0x1
-#define DSPI_SMEM_PMS3_ECC_S  2
-/* DSPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS3_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS3_WR_ATTR_S  1
-/* DSPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS3_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS3_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS0_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x140)
-/* DSPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS0_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS0_ADDR_S_M  ((DSPI_SMEM_PMS0_ADDR_S_V)<<(DSPI_SMEM_PMS0_ADDR_S_S))
-#define DSPI_SMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS0_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS1_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x144)
-/* DSPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS1_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS1_ADDR_S_M  ((DSPI_SMEM_PMS1_ADDR_S_V)<<(DSPI_SMEM_PMS1_ADDR_S_S))
-#define DSPI_SMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS1_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS2_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x148)
-/* DSPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS2_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS2_ADDR_S_M  ((DSPI_SMEM_PMS2_ADDR_S_V)<<(DSPI_SMEM_PMS2_ADDR_S_S))
-#define DSPI_SMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS2_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS3_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x14C)
-/* DSPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS3_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS3_ADDR_S_M  ((DSPI_SMEM_PMS3_ADDR_S_V)<<(DSPI_SMEM_PMS3_ADDR_S_S))
-#define DSPI_SMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS3_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS0_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x150)
-/* DSPI_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS0_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS0_SIZE_M  ((DSPI_SMEM_PMS0_SIZE_V)<<(DSPI_SMEM_PMS0_SIZE_S))
-#define DSPI_SMEM_PMS0_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS0_SIZE_S  0
-
-#define DSPI_SMEM_PMS1_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x154)
-/* DSPI_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS1_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS1_SIZE_M  ((DSPI_SMEM_PMS1_SIZE_V)<<(DSPI_SMEM_PMS1_SIZE_S))
-#define DSPI_SMEM_PMS1_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS1_SIZE_S  0
-
-#define DSPI_SMEM_PMS2_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x158)
-/* DSPI_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS2_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS2_SIZE_M  ((DSPI_SMEM_PMS2_SIZE_V)<<(DSPI_SMEM_PMS2_SIZE_S))
-#define DSPI_SMEM_PMS2_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS2_SIZE_S  0
-
-#define DSPI_SMEM_PMS3_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x15C)
-/* DSPI_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS3_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS3_SIZE_M  ((DSPI_SMEM_PMS3_SIZE_V)<<(DSPI_SMEM_PMS3_SIZE_S))
-#define DSPI_SMEM_PMS3_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS3_SIZE_S  0
-
-#define DSPI_MEM_PMS_REJECT_REG          (DR_REG_DSPI_MEM_BASE + 0x164)
-/* DSPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
-/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_IVD    (BIT(31))
-#define DSPI_MEM_PMS_IVD_M  (BIT(31))
-#define DSPI_MEM_PMS_IVD_V  0x1
-#define DSPI_MEM_PMS_IVD_S  31
-/* DSPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
- is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define DSPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
-#define DSPI_MEM_PMS_MULTI_HIT_V  0x1
-#define DSPI_MEM_PMS_MULTI_HIT_S  30
-/* DSPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_ST    (BIT(29))
-#define DSPI_MEM_PMS_ST_M  (BIT(29))
-#define DSPI_MEM_PMS_ST_V  0x1
-#define DSPI_MEM_PMS_ST_S  29
-/* DSPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
-_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_LD    (BIT(28))
-#define DSPI_MEM_PMS_LD_M  (BIT(28))
-#define DSPI_MEM_PMS_LD_V  0x1
-#define DSPI_MEM_PMS_LD_S  28
-/* DSPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
-#define DSPI_MEM_PM_EN    (BIT(26))
-#define DSPI_MEM_PM_EN_M  (BIT(26))
-#define DSPI_MEM_PM_EN_V  0x1
-#define DSPI_MEM_PM_EN_S  26
-/* DSPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_REJECT_ADDR    0x03FFFFFF
-#define DSPI_MEM_REJECT_ADDR_M  ((DSPI_MEM_REJECT_ADDR_V)<<(DSPI_MEM_REJECT_ADDR_S))
-#define DSPI_MEM_REJECT_ADDR_V  0x3FFFFFF
-#define DSPI_MEM_REJECT_ADDR_S  0
-
-#define DSPI_MEM_ECC_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x168)
-/* DSPI_MEM_ECC_ERR_BITS : R/SS/WTC ;bitpos:[31:25] ;default: 7'd0 ; */
-/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
- to byte 0 bit 0 to byte 15 bit 7).*/
-#define DSPI_MEM_ECC_ERR_BITS    0x0000007F
-#define DSPI_MEM_ECC_ERR_BITS_M  ((DSPI_MEM_ECC_ERR_BITS_V)<<(DSPI_MEM_ECC_ERR_BITS_S))
-#define DSPI_MEM_ECC_ERR_BITS_V  0x7F
-#define DSPI_MEM_ECC_ERR_BITS_S  25
-/* DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
-ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
-R record the first ECC error information..*/
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/* DSPI_MEM_USR_ECC_ADDR_EN : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
-#define DSPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define DSPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
-#define DSPI_MEM_USR_ECC_ADDR_EN_V  0x1
-#define DSPI_MEM_USR_ECC_ADDR_EN_S  21
-/* DSPI_FMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
-is bit should be 0. Otherwise, this bit should be 1..*/
-#define DSPI_FMEM_ECC_ADDR_EN    (BIT(20))
-#define DSPI_FMEM_ECC_ADDR_EN_M  (BIT(20))
-#define DSPI_FMEM_ECC_ADDR_EN_V  0x1
-#define DSPI_FMEM_ECC_ADDR_EN_S  20
-/* DSPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
-1024 bytes. 3: 2048 bytes..*/
-#define DSPI_FMEM_PAGE_SIZE    0x00000003
-#define DSPI_FMEM_PAGE_SIZE_M  ((DSPI_FMEM_PAGE_SIZE_V)<<(DSPI_FMEM_PAGE_SIZE_S))
-#define DSPI_FMEM_PAGE_SIZE_V  0x3
-#define DSPI_FMEM_PAGE_SIZE_S  18
-/* DSPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
-h..*/
-#define DSPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define DSPI_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define DSPI_FMEM_ECC_ERR_INT_EN_V  0x1
-#define DSPI_FMEM_ECC_ERR_INT_EN_S  17
-/* DSPI_FMEM_ECC_ERR_INT_NUM : R/W ;bitpos:[16:11] ;default: 6'd10 ; */
-/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
-upt..*/
-#define DSPI_FMEM_ECC_ERR_INT_NUM    0x0000003F
-#define DSPI_FMEM_ECC_ERR_INT_NUM_M  ((DSPI_FMEM_ECC_ERR_INT_NUM_V)<<(DSPI_FMEM_ECC_ERR_INT_NUM_S))
-#define DSPI_FMEM_ECC_ERR_INT_NUM_V  0x3F
-#define DSPI_FMEM_ECC_ERR_INT_NUM_S  11
-
-#define DSPI_MEM_ECC_ERR_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x16C)
-/* DSPI_MEM_ECC_ERR_CNT : R/SS/WTC ;bitpos:[31:26] ;default: 6'd0 ; */
-/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define DSPI_MEM_ECC_ERR_CNT    0x0000003F
-#define DSPI_MEM_ECC_ERR_CNT_M  ((DSPI_MEM_ECC_ERR_CNT_V)<<(DSPI_MEM_ECC_ERR_CNT_S))
-#define DSPI_MEM_ECC_ERR_CNT_V  0x3F
-#define DSPI_MEM_ECC_ERR_CNT_S  26
-/* DSPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define DSPI_MEM_ECC_ERR_ADDR    0x03FFFFFF
-#define DSPI_MEM_ECC_ERR_ADDR_M  ((DSPI_MEM_ECC_ERR_ADDR_V)<<(DSPI_MEM_ECC_ERR_ADDR_S))
-#define DSPI_MEM_ECC_ERR_ADDR_V  0x3FFFFFF
-#define DSPI_MEM_ECC_ERR_ADDR_S  0
-
-#define DSPI_MEM_AXI_ERR_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x170)
-/* DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
-and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
-/* DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M  (BIT(30))
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S  30
-/* DSPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY    (BIT(29))
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_M  (BIT(29))
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_S  29
-/* DSPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
-/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY    (BIT(28))
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_M  (BIT(28))
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_S  28
-/* DSPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY    (BIT(27))
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_M  (BIT(27))
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_S  27
-/* DSPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
-/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
- and SPI0 transfers are done. 0: Others..*/
-#define DSPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define DSPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
-#define DSPI_MEM_ALL_FIFO_EMPTY_V  0x1
-#define DSPI_MEM_ALL_FIFO_EMPTY_S  26
-/* DSPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
-H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
-#define DSPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
-#define DSPI_MEM_AXI_ERR_ADDR_M  ((DSPI_MEM_AXI_ERR_ADDR_V)<<(DSPI_MEM_AXI_ERR_ADDR_S))
-#define DSPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
-#define DSPI_MEM_AXI_ERR_ADDR_S  0
-
-#define DSPI_SMEM_ECC_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x174)
-/* DSPI_SMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
-ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
-#define DSPI_SMEM_ECC_ADDR_EN    (BIT(20))
-#define DSPI_SMEM_ECC_ADDR_EN_M  (BIT(20))
-#define DSPI_SMEM_ECC_ADDR_EN_V  0x1
-#define DSPI_SMEM_ECC_ADDR_EN_S  20
-/* DSPI_SMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd2 ; */
-/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
-es. 2: 1024 bytes. 3: 2048 bytes..*/
-#define DSPI_SMEM_PAGE_SIZE    0x00000003
-#define DSPI_SMEM_PAGE_SIZE_M  ((DSPI_SMEM_PAGE_SIZE_V)<<(DSPI_SMEM_PAGE_SIZE_S))
-#define DSPI_SMEM_PAGE_SIZE_V  0x3
-#define DSPI_SMEM_PAGE_SIZE_S  18
-/* DSPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
-rnal RAM..*/
-#define DSPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define DSPI_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define DSPI_SMEM_ECC_ERR_INT_EN_V  0x1
-#define DSPI_SMEM_ECC_ERR_INT_EN_S  17
-
-#define DSPI_MEM_TIMING_CALI_REG          (DR_REG_DSPI_MEM_BASE + 0x180)
-/* DSPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
-#define DSPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define DSPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
-#define DSPI_MEM_TIMING_CALI_UPDATE_V  0x1
-#define DSPI_MEM_TIMING_CALI_UPDATE_S  6
-/* DSPI_MEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
-lash..*/
-#define DSPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define DSPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
-#define DSPI_MEM_DLL_TIMING_CALI_V  0x1
-#define DSPI_MEM_DLL_TIMING_CALI_S  5
-/* DSPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* DSPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
-#define DSPI_MEM_TIMING_CALI    (BIT(1))
-#define DSPI_MEM_TIMING_CALI_M  (BIT(1))
-#define DSPI_MEM_TIMING_CALI_V  0x1
-#define DSPI_MEM_TIMING_CALI_S  1
-/* DSPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable timing adjust clock for all reading operations..*/
-#define DSPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define DSPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define DSPI_MEM_TIMING_CLK_ENA_V  0x1
-#define DSPI_MEM_TIMING_CLK_ENA_S  0
-
-#define DSPI_MEM_DIN_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x184)
-/* DSPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DINS_MODE    0x00000007
-#define DSPI_MEM_DINS_MODE_M  ((DSPI_MEM_DINS_MODE_V)<<(DSPI_MEM_DINS_MODE_S))
-#define DSPI_MEM_DINS_MODE_V  0x7
-#define DSPI_MEM_DINS_MODE_S  24
-/* DSPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN7_MODE    0x00000007
-#define DSPI_MEM_DIN7_MODE_M  ((DSPI_MEM_DIN7_MODE_V)<<(DSPI_MEM_DIN7_MODE_S))
-#define DSPI_MEM_DIN7_MODE_V  0x7
-#define DSPI_MEM_DIN7_MODE_S  21
-/* DSPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN6_MODE    0x00000007
-#define DSPI_MEM_DIN6_MODE_M  ((DSPI_MEM_DIN6_MODE_V)<<(DSPI_MEM_DIN6_MODE_S))
-#define DSPI_MEM_DIN6_MODE_V  0x7
-#define DSPI_MEM_DIN6_MODE_S  18
-/* DSPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN5_MODE    0x00000007
-#define DSPI_MEM_DIN5_MODE_M  ((DSPI_MEM_DIN5_MODE_V)<<(DSPI_MEM_DIN5_MODE_S))
-#define DSPI_MEM_DIN5_MODE_V  0x7
-#define DSPI_MEM_DIN5_MODE_S  15
-/* DSPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN4_MODE    0x00000007
-#define DSPI_MEM_DIN4_MODE_M  ((DSPI_MEM_DIN4_MODE_V)<<(DSPI_MEM_DIN4_MODE_S))
-#define DSPI_MEM_DIN4_MODE_V  0x7
-#define DSPI_MEM_DIN4_MODE_S  12
-/* DSPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN3_MODE    0x00000007
-#define DSPI_MEM_DIN3_MODE_M  ((DSPI_MEM_DIN3_MODE_V)<<(DSPI_MEM_DIN3_MODE_S))
-#define DSPI_MEM_DIN3_MODE_V  0x7
-#define DSPI_MEM_DIN3_MODE_S  9
-/* DSPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN2_MODE    0x00000007
-#define DSPI_MEM_DIN2_MODE_M  ((DSPI_MEM_DIN2_MODE_V)<<(DSPI_MEM_DIN2_MODE_S))
-#define DSPI_MEM_DIN2_MODE_V  0x7
-#define DSPI_MEM_DIN2_MODE_S  6
-/* DSPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN1_MODE    0x00000007
-#define DSPI_MEM_DIN1_MODE_M  ((DSPI_MEM_DIN1_MODE_V)<<(DSPI_MEM_DIN1_MODE_S))
-#define DSPI_MEM_DIN1_MODE_V  0x7
-#define DSPI_MEM_DIN1_MODE_S  3
-/* DSPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN0_MODE    0x00000007
-#define DSPI_MEM_DIN0_MODE_M  ((DSPI_MEM_DIN0_MODE_V)<<(DSPI_MEM_DIN0_MODE_S))
-#define DSPI_MEM_DIN0_MODE_V  0x7
-#define DSPI_MEM_DIN0_MODE_S  0
-
-#define DSPI_MEM_DIN_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x188)
-/* DSPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DINS_NUM    0x00000003
-#define DSPI_MEM_DINS_NUM_M  ((DSPI_MEM_DINS_NUM_V)<<(DSPI_MEM_DINS_NUM_S))
-#define DSPI_MEM_DINS_NUM_V  0x3
-#define DSPI_MEM_DINS_NUM_S  16
-/* DSPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN7_NUM    0x00000003
-#define DSPI_MEM_DIN7_NUM_M  ((DSPI_MEM_DIN7_NUM_V)<<(DSPI_MEM_DIN7_NUM_S))
-#define DSPI_MEM_DIN7_NUM_V  0x3
-#define DSPI_MEM_DIN7_NUM_S  14
-/* DSPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN6_NUM    0x00000003
-#define DSPI_MEM_DIN6_NUM_M  ((DSPI_MEM_DIN6_NUM_V)<<(DSPI_MEM_DIN6_NUM_S))
-#define DSPI_MEM_DIN6_NUM_V  0x3
-#define DSPI_MEM_DIN6_NUM_S  12
-/* DSPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN5_NUM    0x00000003
-#define DSPI_MEM_DIN5_NUM_M  ((DSPI_MEM_DIN5_NUM_V)<<(DSPI_MEM_DIN5_NUM_S))
-#define DSPI_MEM_DIN5_NUM_V  0x3
-#define DSPI_MEM_DIN5_NUM_S  10
-/* DSPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN4_NUM    0x00000003
-#define DSPI_MEM_DIN4_NUM_M  ((DSPI_MEM_DIN4_NUM_V)<<(DSPI_MEM_DIN4_NUM_S))
-#define DSPI_MEM_DIN4_NUM_V  0x3
-#define DSPI_MEM_DIN4_NUM_S  8
-/* DSPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN3_NUM    0x00000003
-#define DSPI_MEM_DIN3_NUM_M  ((DSPI_MEM_DIN3_NUM_V)<<(DSPI_MEM_DIN3_NUM_S))
-#define DSPI_MEM_DIN3_NUM_V  0x3
-#define DSPI_MEM_DIN3_NUM_S  6
-/* DSPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN2_NUM    0x00000003
-#define DSPI_MEM_DIN2_NUM_M  ((DSPI_MEM_DIN2_NUM_V)<<(DSPI_MEM_DIN2_NUM_S))
-#define DSPI_MEM_DIN2_NUM_V  0x3
-#define DSPI_MEM_DIN2_NUM_S  4
-/* DSPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN1_NUM    0x00000003
-#define DSPI_MEM_DIN1_NUM_M  ((DSPI_MEM_DIN1_NUM_V)<<(DSPI_MEM_DIN1_NUM_S))
-#define DSPI_MEM_DIN1_NUM_V  0x3
-#define DSPI_MEM_DIN1_NUM_S  2
-/* DSPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN0_NUM    0x00000003
-#define DSPI_MEM_DIN0_NUM_M  ((DSPI_MEM_DIN0_NUM_V)<<(DSPI_MEM_DIN0_NUM_S))
-#define DSPI_MEM_DIN0_NUM_V  0x3
-#define DSPI_MEM_DIN0_NUM_S  0
-
-#define DSPI_MEM_DOUT_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x18C)
-/* DSPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUTS_MODE    (BIT(8))
-#define DSPI_MEM_DOUTS_MODE_M  (BIT(8))
-#define DSPI_MEM_DOUTS_MODE_V  0x1
-#define DSPI_MEM_DOUTS_MODE_S  8
-/* DSPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT7_MODE    (BIT(7))
-#define DSPI_MEM_DOUT7_MODE_M  (BIT(7))
-#define DSPI_MEM_DOUT7_MODE_V  0x1
-#define DSPI_MEM_DOUT7_MODE_S  7
-/* DSPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT6_MODE    (BIT(6))
-#define DSPI_MEM_DOUT6_MODE_M  (BIT(6))
-#define DSPI_MEM_DOUT6_MODE_V  0x1
-#define DSPI_MEM_DOUT6_MODE_S  6
-/* DSPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT5_MODE    (BIT(5))
-#define DSPI_MEM_DOUT5_MODE_M  (BIT(5))
-#define DSPI_MEM_DOUT5_MODE_V  0x1
-#define DSPI_MEM_DOUT5_MODE_S  5
-/* DSPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT4_MODE    (BIT(4))
-#define DSPI_MEM_DOUT4_MODE_M  (BIT(4))
-#define DSPI_MEM_DOUT4_MODE_V  0x1
-#define DSPI_MEM_DOUT4_MODE_S  4
-/* DSPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT3_MODE    (BIT(3))
-#define DSPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define DSPI_MEM_DOUT3_MODE_V  0x1
-#define DSPI_MEM_DOUT3_MODE_S  3
-/* DSPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT2_MODE    (BIT(2))
-#define DSPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define DSPI_MEM_DOUT2_MODE_V  0x1
-#define DSPI_MEM_DOUT2_MODE_S  2
-/* DSPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT1_MODE    (BIT(1))
-#define DSPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define DSPI_MEM_DOUT1_MODE_V  0x1
-#define DSPI_MEM_DOUT1_MODE_S  1
-/* DSPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT0_MODE    (BIT(0))
-#define DSPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define DSPI_MEM_DOUT0_MODE_V  0x1
-#define DSPI_MEM_DOUT0_MODE_S  0
-
-#define DSPI_SMEM_TIMING_CALI_REG          (DR_REG_DSPI_MEM_BASE + 0x190)
-/* DSPI_SMEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
-XT_RAM..*/
-#define DSPI_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define DSPI_SMEM_DLL_TIMING_CALI_M  (BIT(5))
-#define DSPI_SMEM_DLL_TIMING_CALI_V  0x1
-#define DSPI_SMEM_DLL_TIMING_CALI_S  5
-/* DSPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* DSPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
-ations..*/
-#define DSPI_SMEM_TIMING_CALI    (BIT(1))
-#define DSPI_SMEM_TIMING_CALI_M  (BIT(1))
-#define DSPI_SMEM_TIMING_CALI_V  0x1
-#define DSPI_SMEM_TIMING_CALI_S  1
-/* DSPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
-ns..*/
-#define DSPI_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define DSPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
-#define DSPI_SMEM_TIMING_CLK_ENA_V  0x1
-#define DSPI_SMEM_TIMING_CLK_ENA_S  0
-
-#define DSPI_SMEM_DIN_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x194)
-/* DSPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DINS_MODE    0x00000007
-#define DSPI_SMEM_DINS_MODE_M  ((DSPI_SMEM_DINS_MODE_V)<<(DSPI_SMEM_DINS_MODE_S))
-#define DSPI_SMEM_DINS_MODE_V  0x7
-#define DSPI_SMEM_DINS_MODE_S  24
-/* DSPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN7_MODE    0x00000007
-#define DSPI_SMEM_DIN7_MODE_M  ((DSPI_SMEM_DIN7_MODE_V)<<(DSPI_SMEM_DIN7_MODE_S))
-#define DSPI_SMEM_DIN7_MODE_V  0x7
-#define DSPI_SMEM_DIN7_MODE_S  21
-/* DSPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN6_MODE    0x00000007
-#define DSPI_SMEM_DIN6_MODE_M  ((DSPI_SMEM_DIN6_MODE_V)<<(DSPI_SMEM_DIN6_MODE_S))
-#define DSPI_SMEM_DIN6_MODE_V  0x7
-#define DSPI_SMEM_DIN6_MODE_S  18
-/* DSPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN5_MODE    0x00000007
-#define DSPI_SMEM_DIN5_MODE_M  ((DSPI_SMEM_DIN5_MODE_V)<<(DSPI_SMEM_DIN5_MODE_S))
-#define DSPI_SMEM_DIN5_MODE_V  0x7
-#define DSPI_SMEM_DIN5_MODE_S  15
-/* DSPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN4_MODE    0x00000007
-#define DSPI_SMEM_DIN4_MODE_M  ((DSPI_SMEM_DIN4_MODE_V)<<(DSPI_SMEM_DIN4_MODE_S))
-#define DSPI_SMEM_DIN4_MODE_V  0x7
-#define DSPI_SMEM_DIN4_MODE_S  12
-/* DSPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN3_MODE    0x00000007
-#define DSPI_SMEM_DIN3_MODE_M  ((DSPI_SMEM_DIN3_MODE_V)<<(DSPI_SMEM_DIN3_MODE_S))
-#define DSPI_SMEM_DIN3_MODE_V  0x7
-#define DSPI_SMEM_DIN3_MODE_S  9
-/* DSPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN2_MODE    0x00000007
-#define DSPI_SMEM_DIN2_MODE_M  ((DSPI_SMEM_DIN2_MODE_V)<<(DSPI_SMEM_DIN2_MODE_S))
-#define DSPI_SMEM_DIN2_MODE_V  0x7
-#define DSPI_SMEM_DIN2_MODE_S  6
-/* DSPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN1_MODE    0x00000007
-#define DSPI_SMEM_DIN1_MODE_M  ((DSPI_SMEM_DIN1_MODE_V)<<(DSPI_SMEM_DIN1_MODE_S))
-#define DSPI_SMEM_DIN1_MODE_V  0x7
-#define DSPI_SMEM_DIN1_MODE_S  3
-/* DSPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN0_MODE    0x00000007
-#define DSPI_SMEM_DIN0_MODE_M  ((DSPI_SMEM_DIN0_MODE_V)<<(DSPI_SMEM_DIN0_MODE_S))
-#define DSPI_SMEM_DIN0_MODE_V  0x7
-#define DSPI_SMEM_DIN0_MODE_S  0
-
-#define DSPI_SMEM_DIN_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x198)
-/* DSPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DINS_NUM    0x00000003
-#define DSPI_SMEM_DINS_NUM_M  ((DSPI_SMEM_DINS_NUM_V)<<(DSPI_SMEM_DINS_NUM_S))
-#define DSPI_SMEM_DINS_NUM_V  0x3
-#define DSPI_SMEM_DINS_NUM_S  16
-/* DSPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN7_NUM    0x00000003
-#define DSPI_SMEM_DIN7_NUM_M  ((DSPI_SMEM_DIN7_NUM_V)<<(DSPI_SMEM_DIN7_NUM_S))
-#define DSPI_SMEM_DIN7_NUM_V  0x3
-#define DSPI_SMEM_DIN7_NUM_S  14
-/* DSPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN6_NUM    0x00000003
-#define DSPI_SMEM_DIN6_NUM_M  ((DSPI_SMEM_DIN6_NUM_V)<<(DSPI_SMEM_DIN6_NUM_S))
-#define DSPI_SMEM_DIN6_NUM_V  0x3
-#define DSPI_SMEM_DIN6_NUM_S  12
-/* DSPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN5_NUM    0x00000003
-#define DSPI_SMEM_DIN5_NUM_M  ((DSPI_SMEM_DIN5_NUM_V)<<(DSPI_SMEM_DIN5_NUM_S))
-#define DSPI_SMEM_DIN5_NUM_V  0x3
-#define DSPI_SMEM_DIN5_NUM_S  10
-/* DSPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN4_NUM    0x00000003
-#define DSPI_SMEM_DIN4_NUM_M  ((DSPI_SMEM_DIN4_NUM_V)<<(DSPI_SMEM_DIN4_NUM_S))
-#define DSPI_SMEM_DIN4_NUM_V  0x3
-#define DSPI_SMEM_DIN4_NUM_S  8
-/* DSPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN3_NUM    0x00000003
-#define DSPI_SMEM_DIN3_NUM_M  ((DSPI_SMEM_DIN3_NUM_V)<<(DSPI_SMEM_DIN3_NUM_S))
-#define DSPI_SMEM_DIN3_NUM_V  0x3
-#define DSPI_SMEM_DIN3_NUM_S  6
-/* DSPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN2_NUM    0x00000003
-#define DSPI_SMEM_DIN2_NUM_M  ((DSPI_SMEM_DIN2_NUM_V)<<(DSPI_SMEM_DIN2_NUM_S))
-#define DSPI_SMEM_DIN2_NUM_V  0x3
-#define DSPI_SMEM_DIN2_NUM_S  4
-/* DSPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN1_NUM    0x00000003
-#define DSPI_SMEM_DIN1_NUM_M  ((DSPI_SMEM_DIN1_NUM_V)<<(DSPI_SMEM_DIN1_NUM_S))
-#define DSPI_SMEM_DIN1_NUM_V  0x3
-#define DSPI_SMEM_DIN1_NUM_S  2
-/* DSPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN0_NUM    0x00000003
-#define DSPI_SMEM_DIN0_NUM_M  ((DSPI_SMEM_DIN0_NUM_V)<<(DSPI_SMEM_DIN0_NUM_S))
-#define DSPI_SMEM_DIN0_NUM_V  0x3
-#define DSPI_SMEM_DIN0_NUM_S  0
-
-#define DSPI_SMEM_DOUT_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x19C)
-/* DSPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUTS_MODE    (BIT(8))
-#define DSPI_SMEM_DOUTS_MODE_M  (BIT(8))
-#define DSPI_SMEM_DOUTS_MODE_V  0x1
-#define DSPI_SMEM_DOUTS_MODE_S  8
-/* DSPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT7_MODE    (BIT(7))
-#define DSPI_SMEM_DOUT7_MODE_M  (BIT(7))
-#define DSPI_SMEM_DOUT7_MODE_V  0x1
-#define DSPI_SMEM_DOUT7_MODE_S  7
-/* DSPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT6_MODE    (BIT(6))
-#define DSPI_SMEM_DOUT6_MODE_M  (BIT(6))
-#define DSPI_SMEM_DOUT6_MODE_V  0x1
-#define DSPI_SMEM_DOUT6_MODE_S  6
-/* DSPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT5_MODE    (BIT(5))
-#define DSPI_SMEM_DOUT5_MODE_M  (BIT(5))
-#define DSPI_SMEM_DOUT5_MODE_V  0x1
-#define DSPI_SMEM_DOUT5_MODE_S  5
-/* DSPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT4_MODE    (BIT(4))
-#define DSPI_SMEM_DOUT4_MODE_M  (BIT(4))
-#define DSPI_SMEM_DOUT4_MODE_V  0x1
-#define DSPI_SMEM_DOUT4_MODE_S  4
-/* DSPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT3_MODE    (BIT(3))
-#define DSPI_SMEM_DOUT3_MODE_M  (BIT(3))
-#define DSPI_SMEM_DOUT3_MODE_V  0x1
-#define DSPI_SMEM_DOUT3_MODE_S  3
-/* DSPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT2_MODE    (BIT(2))
-#define DSPI_SMEM_DOUT2_MODE_M  (BIT(2))
-#define DSPI_SMEM_DOUT2_MODE_V  0x1
-#define DSPI_SMEM_DOUT2_MODE_S  2
-/* DSPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT1_MODE    (BIT(1))
-#define DSPI_SMEM_DOUT1_MODE_M  (BIT(1))
-#define DSPI_SMEM_DOUT1_MODE_V  0x1
-#define DSPI_SMEM_DOUT1_MODE_S  1
-/* DSPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT0_MODE    (BIT(0))
-#define DSPI_SMEM_DOUT0_MODE_M  (BIT(0))
-#define DSPI_SMEM_DOUT0_MODE_V  0x1
-#define DSPI_SMEM_DOUT0_MODE_S  0
-
-#define DSPI_SMEM_AC_REG          (DR_REG_DSPI_MEM_BASE + 0x1A0)
-/* DSPI_SMEM_SPLIT_TRANS_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
- transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
-er whether there is an ECC region or not..*/
-#define DSPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define DSPI_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
-#define DSPI_SMEM_SPLIT_TRANS_EN_V  0x1
-#define DSPI_SMEM_SPLIT_TRANS_EN_S  31
-/* DSPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
-SPI core clock cycles..*/
-#define DSPI_SMEM_CS_HOLD_DELAY    0x0000003F
-#define DSPI_SMEM_CS_HOLD_DELAY_M  ((DSPI_SMEM_CS_HOLD_DELAY_V)<<(DSPI_SMEM_CS_HOLD_DELAY_S))
-#define DSPI_SMEM_CS_HOLD_DELAY_V  0x3F
-#define DSPI_SMEM_CS_HOLD_DELAY_S  25
-/* DSPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses external RAM..*/
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_S  16
-/* DSPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
-en accesses external RAM..*/
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/* DSPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
-ycles in ECC mode when accessed external RAM..*/
-#define DSPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_M  ((DSPI_SMEM_ECC_CS_HOLD_TIME_V)<<(DSPI_SMEM_ECC_CS_HOLD_TIME_S))
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_S  12
-/* DSPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */
-/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
-re combined with spi_mem_cs_hold bit..*/
-#define DSPI_SMEM_CS_HOLD_TIME    0x0000001F
-#define DSPI_SMEM_CS_HOLD_TIME_M  ((DSPI_SMEM_CS_HOLD_TIME_V)<<(DSPI_SMEM_CS_HOLD_TIME_S))
-#define DSPI_SMEM_CS_HOLD_TIME_V  0x1F
-#define DSPI_SMEM_CS_HOLD_TIME_S  7
-/* DSPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */
-/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
-pi_mem_cs_setup bit..*/
-#define DSPI_SMEM_CS_SETUP_TIME    0x0000001F
-#define DSPI_SMEM_CS_SETUP_TIME_M  ((DSPI_SMEM_CS_SETUP_TIME_V)<<(DSPI_SMEM_CS_SETUP_TIME_S))
-#define DSPI_SMEM_CS_SETUP_TIME_V  0x1F
-#define DSPI_SMEM_CS_SETUP_TIME_S  2
-/* DSPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
-le..*/
-#define DSPI_SMEM_CS_HOLD    (BIT(1))
-#define DSPI_SMEM_CS_HOLD_M  (BIT(1))
-#define DSPI_SMEM_CS_HOLD_V  0x1
-#define DSPI_SMEM_CS_HOLD_S  1
-/* DSPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
-isable..*/
-#define DSPI_SMEM_CS_SETUP    (BIT(0))
-#define DSPI_SMEM_CS_SETUP_M  (BIT(0))
-#define DSPI_SMEM_CS_SETUP_V  0x1
-#define DSPI_SMEM_CS_SETUP_S  0
-
-#define DSPI_SMEM_DIN_HEX_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x1A4)
-/* DSPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DINS_HEX_MODE    0x00000007
-#define DSPI_SMEM_DINS_HEX_MODE_M  ((DSPI_SMEM_DINS_HEX_MODE_V)<<(DSPI_SMEM_DINS_HEX_MODE_S))
-#define DSPI_SMEM_DINS_HEX_MODE_V  0x7
-#define DSPI_SMEM_DINS_HEX_MODE_S  24
-/* DSPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN15_MODE    0x00000007
-#define DSPI_SMEM_DIN15_MODE_M  ((DSPI_SMEM_DIN15_MODE_V)<<(DSPI_SMEM_DIN15_MODE_S))
-#define DSPI_SMEM_DIN15_MODE_V  0x7
-#define DSPI_SMEM_DIN15_MODE_S  21
-/* DSPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN14_MODE    0x00000007
-#define DSPI_SMEM_DIN14_MODE_M  ((DSPI_SMEM_DIN14_MODE_V)<<(DSPI_SMEM_DIN14_MODE_S))
-#define DSPI_SMEM_DIN14_MODE_V  0x7
-#define DSPI_SMEM_DIN14_MODE_S  18
-/* DSPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN13_MODE    0x00000007
-#define DSPI_SMEM_DIN13_MODE_M  ((DSPI_SMEM_DIN13_MODE_V)<<(DSPI_SMEM_DIN13_MODE_S))
-#define DSPI_SMEM_DIN13_MODE_V  0x7
-#define DSPI_SMEM_DIN13_MODE_S  15
-/* DSPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN12_MODE    0x00000007
-#define DSPI_SMEM_DIN12_MODE_M  ((DSPI_SMEM_DIN12_MODE_V)<<(DSPI_SMEM_DIN12_MODE_S))
-#define DSPI_SMEM_DIN12_MODE_V  0x7
-#define DSPI_SMEM_DIN12_MODE_S  12
-/* DSPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN11_MODE    0x00000007
-#define DSPI_SMEM_DIN11_MODE_M  ((DSPI_SMEM_DIN11_MODE_V)<<(DSPI_SMEM_DIN11_MODE_S))
-#define DSPI_SMEM_DIN11_MODE_V  0x7
-#define DSPI_SMEM_DIN11_MODE_S  9
-/* DSPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN10_MODE    0x00000007
-#define DSPI_SMEM_DIN10_MODE_M  ((DSPI_SMEM_DIN10_MODE_V)<<(DSPI_SMEM_DIN10_MODE_S))
-#define DSPI_SMEM_DIN10_MODE_V  0x7
-#define DSPI_SMEM_DIN10_MODE_S  6
-/* DSPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN09_MODE    0x00000007
-#define DSPI_SMEM_DIN09_MODE_M  ((DSPI_SMEM_DIN09_MODE_V)<<(DSPI_SMEM_DIN09_MODE_S))
-#define DSPI_SMEM_DIN09_MODE_V  0x7
-#define DSPI_SMEM_DIN09_MODE_S  3
-/* DSPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN08_MODE    0x00000007
-#define DSPI_SMEM_DIN08_MODE_M  ((DSPI_SMEM_DIN08_MODE_V)<<(DSPI_SMEM_DIN08_MODE_S))
-#define DSPI_SMEM_DIN08_MODE_V  0x7
-#define DSPI_SMEM_DIN08_MODE_S  0
-
-#define DSPI_SMEM_DIN_HEX_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x1A8)
-/* DSPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DINS_HEX_NUM    0x00000003
-#define DSPI_SMEM_DINS_HEX_NUM_M  ((DSPI_SMEM_DINS_HEX_NUM_V)<<(DSPI_SMEM_DINS_HEX_NUM_S))
-#define DSPI_SMEM_DINS_HEX_NUM_V  0x3
-#define DSPI_SMEM_DINS_HEX_NUM_S  16
-/* DSPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN15_NUM    0x00000003
-#define DSPI_SMEM_DIN15_NUM_M  ((DSPI_SMEM_DIN15_NUM_V)<<(DSPI_SMEM_DIN15_NUM_S))
-#define DSPI_SMEM_DIN15_NUM_V  0x3
-#define DSPI_SMEM_DIN15_NUM_S  14
-/* DSPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN14_NUM    0x00000003
-#define DSPI_SMEM_DIN14_NUM_M  ((DSPI_SMEM_DIN14_NUM_V)<<(DSPI_SMEM_DIN14_NUM_S))
-#define DSPI_SMEM_DIN14_NUM_V  0x3
-#define DSPI_SMEM_DIN14_NUM_S  12
-/* DSPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN13_NUM    0x00000003
-#define DSPI_SMEM_DIN13_NUM_M  ((DSPI_SMEM_DIN13_NUM_V)<<(DSPI_SMEM_DIN13_NUM_S))
-#define DSPI_SMEM_DIN13_NUM_V  0x3
-#define DSPI_SMEM_DIN13_NUM_S  10
-/* DSPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN12_NUM    0x00000003
-#define DSPI_SMEM_DIN12_NUM_M  ((DSPI_SMEM_DIN12_NUM_V)<<(DSPI_SMEM_DIN12_NUM_S))
-#define DSPI_SMEM_DIN12_NUM_V  0x3
-#define DSPI_SMEM_DIN12_NUM_S  8
-/* DSPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN11_NUM    0x00000003
-#define DSPI_SMEM_DIN11_NUM_M  ((DSPI_SMEM_DIN11_NUM_V)<<(DSPI_SMEM_DIN11_NUM_S))
-#define DSPI_SMEM_DIN11_NUM_V  0x3
-#define DSPI_SMEM_DIN11_NUM_S  6
-/* DSPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN10_NUM    0x00000003
-#define DSPI_SMEM_DIN10_NUM_M  ((DSPI_SMEM_DIN10_NUM_V)<<(DSPI_SMEM_DIN10_NUM_S))
-#define DSPI_SMEM_DIN10_NUM_V  0x3
-#define DSPI_SMEM_DIN10_NUM_S  4
-/* DSPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN09_NUM    0x00000003
-#define DSPI_SMEM_DIN09_NUM_M  ((DSPI_SMEM_DIN09_NUM_V)<<(DSPI_SMEM_DIN09_NUM_S))
-#define DSPI_SMEM_DIN09_NUM_V  0x3
-#define DSPI_SMEM_DIN09_NUM_S  2
-/* DSPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN08_NUM    0x00000003
-#define DSPI_SMEM_DIN08_NUM_M  ((DSPI_SMEM_DIN08_NUM_V)<<(DSPI_SMEM_DIN08_NUM_S))
-#define DSPI_SMEM_DIN08_NUM_V  0x3
-#define DSPI_SMEM_DIN08_NUM_S  0
-
-#define DSPI_SMEM_DOUT_HEX_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x1AC)
-/* DSPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUTS_HEX_MODE    (BIT(8))
-#define DSPI_SMEM_DOUTS_HEX_MODE_M  (BIT(8))
-#define DSPI_SMEM_DOUTS_HEX_MODE_V  0x1
-#define DSPI_SMEM_DOUTS_HEX_MODE_S  8
-/* DSPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT15_MODE    (BIT(7))
-#define DSPI_SMEM_DOUT15_MODE_M  (BIT(7))
-#define DSPI_SMEM_DOUT15_MODE_V  0x1
-#define DSPI_SMEM_DOUT15_MODE_S  7
-/* DSPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT14_MODE    (BIT(6))
-#define DSPI_SMEM_DOUT14_MODE_M  (BIT(6))
-#define DSPI_SMEM_DOUT14_MODE_V  0x1
-#define DSPI_SMEM_DOUT14_MODE_S  6
-/* DSPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT13_MODE    (BIT(5))
-#define DSPI_SMEM_DOUT13_MODE_M  (BIT(5))
-#define DSPI_SMEM_DOUT13_MODE_V  0x1
-#define DSPI_SMEM_DOUT13_MODE_S  5
-/* DSPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT12_MODE    (BIT(4))
-#define DSPI_SMEM_DOUT12_MODE_M  (BIT(4))
-#define DSPI_SMEM_DOUT12_MODE_V  0x1
-#define DSPI_SMEM_DOUT12_MODE_S  4
-/* DSPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT11_MODE    (BIT(3))
-#define DSPI_SMEM_DOUT11_MODE_M  (BIT(3))
-#define DSPI_SMEM_DOUT11_MODE_V  0x1
-#define DSPI_SMEM_DOUT11_MODE_S  3
-/* DSPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT10_MODE    (BIT(2))
-#define DSPI_SMEM_DOUT10_MODE_M  (BIT(2))
-#define DSPI_SMEM_DOUT10_MODE_V  0x1
-#define DSPI_SMEM_DOUT10_MODE_S  2
-/* DSPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT09_MODE    (BIT(1))
-#define DSPI_SMEM_DOUT09_MODE_M  (BIT(1))
-#define DSPI_SMEM_DOUT09_MODE_V  0x1
-#define DSPI_SMEM_DOUT09_MODE_S  1
-/* DSPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT08_MODE    (BIT(0))
-#define DSPI_SMEM_DOUT08_MODE_M  (BIT(0))
-#define DSPI_SMEM_DOUT08_MODE_V  0x1
-#define DSPI_SMEM_DOUT08_MODE_S  0
-
-#define DSPI_MEM_CLOCK_GATE_REG          (DR_REG_DSPI_MEM_BASE + 0x200)
-/* DSPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
-#define DSPI_MEM_SPI_CLK_EN    (BIT(0))
-#define DSPI_MEM_SPI_CLK_EN_M  (BIT(0))
-#define DSPI_MEM_SPI_CLK_EN_V  0x1
-#define DSPI_MEM_SPI_CLK_EN_S  0
-
-#define DSPI_MEM_XTS_PLAIN_BASE_REG          (DR_REG_DSPI_MEM_BASE + 0x300)
-/* DSPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field is only used to generate include file in c case. This field is useles
-s. Please do not use this field..*/
-#define DSPI_MEM_SPI_XTS_PLAIN    0xFFFFFFFF
-#define DSPI_MEM_SPI_XTS_PLAIN_M  ((DSPI_MEM_SPI_XTS_PLAIN_V)<<(DSPI_MEM_SPI_XTS_PLAIN_S))
-#define DSPI_MEM_SPI_XTS_PLAIN_V  0xFFFFFFFF
-#define DSPI_MEM_SPI_XTS_PLAIN_S  0
-
-#define DSPI_MEM_XTS_LINESIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x340)
-/* DSPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the line-size parameter which will be used in manual encryption
- calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
- 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
-#define DSPI_MEM_SPI_XTS_LINESIZE    0x00000003
-#define DSPI_MEM_SPI_XTS_LINESIZE_M  ((DSPI_MEM_SPI_XTS_LINESIZE_V)<<(DSPI_MEM_SPI_XTS_LINESIZE_S))
-#define DSPI_MEM_SPI_XTS_LINESIZE_V  0x3
-#define DSPI_MEM_SPI_XTS_LINESIZE_S  0
-
-#define DSPI_MEM_XTS_DESTINATION_REG          (DR_REG_DSPI_MEM_BASE + 0x344)
-/* DSPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
-n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
-used..*/
-#define DSPI_MEM_SPI_XTS_DESTINATION    (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTINATION_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTINATION_V  0x1
-#define DSPI_MEM_SPI_XTS_DESTINATION_S  0
-
-#define DSPI_MEM_XTS_PHYSICAL_ADDRESS_REG          (DR_REG_DSPI_MEM_BASE + 0x348)
-/* DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits stores the physical-address parameter which will be used in manual enc
-ryption calculation. This value should aligned with byte number decided by line-
-size parameter..*/
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFF
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M  ((DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S))
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V  0x3FFFFFF
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S  0
-
-#define DSPI_MEM_XTS_TRIGGER_REG          (DR_REG_DSPI_MEM_BASE + 0x34C)
-/* DSPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to trigger the process of manual encryption calculation. This actio
-n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
-n status becomes 2..*/
-#define DSPI_MEM_SPI_XTS_TRIGGER    (BIT(0))
-#define DSPI_MEM_SPI_XTS_TRIGGER_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_TRIGGER_V  0x1
-#define DSPI_MEM_SPI_XTS_TRIGGER_S  0
-
-#define DSPI_MEM_XTS_RELEASE_REG          (DR_REG_DSPI_MEM_BASE + 0x350)
-/* DSPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to release encrypted result to mspi. This action should only be ass
-erted when manual encryption status is 2. After this action, manual encryption s
-tatus will become 3..*/
-#define DSPI_MEM_SPI_XTS_RELEASE    (BIT(0))
-#define DSPI_MEM_SPI_XTS_RELEASE_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_RELEASE_V  0x1
-#define DSPI_MEM_SPI_XTS_RELEASE_S  0
-
-#define DSPI_MEM_XTS_DESTROY_REG          (DR_REG_DSPI_MEM_BASE + 0x354)
-/* DSPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
-en manual encryption status is 3. After this action, manual encryption status wi
-ll become 0..*/
-#define DSPI_MEM_SPI_XTS_DESTROY    (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTROY_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTROY_V  0x1
-#define DSPI_MEM_SPI_XTS_DESTROY_S  0
-
-#define DSPI_MEM_XTS_STATE_REG          (DR_REG_DSPI_MEM_BASE + 0x358)
-/* DSPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
- calculation, 2: encryption calculation is done but the encrypted result is invi
-sible to mspi, 3: the encrypted result is visible to mspi..*/
-#define DSPI_MEM_SPI_XTS_STATE    0x00000003
-#define DSPI_MEM_SPI_XTS_STATE_M  ((DSPI_MEM_SPI_XTS_STATE_V)<<(DSPI_MEM_SPI_XTS_STATE_S))
-#define DSPI_MEM_SPI_XTS_STATE_V  0x3
-#define DSPI_MEM_SPI_XTS_STATE_S  0
-
-#define DSPI_MEM_XTS_DATE_REG          (DR_REG_DSPI_MEM_BASE + 0x35C)
-/* DSPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
-/*description: This bits stores the last modified-time of manual encryption feature..*/
-#define DSPI_MEM_SPI_XTS_DATE    0x3FFFFFFF
-#define DSPI_MEM_SPI_XTS_DATE_M  ((DSPI_MEM_SPI_XTS_DATE_V)<<(DSPI_MEM_SPI_XTS_DATE_S))
-#define DSPI_MEM_SPI_XTS_DATE_V  0x3FFFFFFF
-#define DSPI_MEM_SPI_XTS_DATE_S  0
-
-#define DSPI_MEM_MMU_ITEM_CONTENT_REG          (DR_REG_DSPI_MEM_BASE + 0x37C)
-/* DSPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: MSPI-MMU item content.*/
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT    0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_M  ((DSPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(DSPI_MEM_SPI_MMU_ITEM_CONTENT_S))
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_S  0
-
-#define DSPI_MEM_MMU_ITEM_INDEX_REG          (DR_REG_DSPI_MEM_BASE + 0x380)
-/* DSPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: MSPI-MMU item index.*/
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX    0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_M  ((DSPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(DSPI_MEM_SPI_MMU_ITEM_INDEX_S))
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_V  0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_S  0
-
-#define DSPI_MEM_MMU_POWER_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x384)
-/* DSPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
-#define DSPI_MEM_RDN_RESULT    (BIT(31))
-#define DSPI_MEM_RDN_RESULT_M  (BIT(31))
-#define DSPI_MEM_RDN_RESULT_V  0x1
-#define DSPI_MEM_RDN_RESULT_S  31
-/* DSPI_MEM_RDN_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: ECO register enable bit.*/
-#define DSPI_MEM_RDN_ENA    (BIT(30))
-#define DSPI_MEM_RDN_ENA_M  (BIT(30))
-#define DSPI_MEM_RDN_ENA_V  0x1
-#define DSPI_MEM_RDN_ENA_S  30
-/* DSPI_MEM_AUX_CTRL : R/W ;bitpos:[29:16] ;default: 14'h1320 ; */
-/*description: MMU PSRAM aux control register.*/
-#define DSPI_MEM_AUX_CTRL    0x00003FFF
-#define DSPI_MEM_AUX_CTRL_M  ((DSPI_MEM_AUX_CTRL_V)<<(DSPI_MEM_AUX_CTRL_S))
-#define DSPI_MEM_AUX_CTRL_V  0x3FFF
-#define DSPI_MEM_AUX_CTRL_S  16
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
- controlled by rtc..*/
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU    (BIT(2))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_M  (BIT(2))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_V  0x1
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_S  2
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to force mmu-memory powerdown.*/
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD    (BIT(1))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_M  (BIT(1))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_V  0x1
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_S  1
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable mmu-memory clock force on.*/
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON    (BIT(0))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_M  (BIT(0))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_V  0x1
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_S  0
-
-#define DSPI_MEM_DPA_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x388)
-/* DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
-T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V  0x1
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S  4
-/* DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
-ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
-ing key 1..*/
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V  0x1
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S  3
-/* DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
-7: The bigger the number is, the more secure the cryption is. (Note that the per
-formance of cryption will decrease together with this number increasing).*/
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL    0x00000007
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M  ((DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S))
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V  0x7
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S  0
-
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_REG          (DR_REG_DSPI_MEM_BASE + 0x3F0)
-/* DSPI_MEM_REGISTERRND_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO high register.*/
-#define DSPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_M  ((DSPI_MEM_REGISTERRND_ECO_HIGH_V)<<(DSPI_MEM_REGISTERRND_ECO_HIGH_S))
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_S  0
-
-#define DSPI_MEM_REGISTERRND_ECO_LOW_REG          (DR_REG_DSPI_MEM_BASE + 0x3F4)
-/* DSPI_MEM_REGISTERRND_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO low register.*/
-#define DSPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_LOW_M  ((DSPI_MEM_REGISTERRND_ECO_LOW_V)<<(DSPI_MEM_REGISTERRND_ECO_LOW_S))
-#define DSPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_LOW_S  0
-
-#define DSPI_MEM_DATE_REG          (DR_REG_DSPI_MEM_BASE + 0x3FC)
-/* DSPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2211210 ; */
-/*description: SPI0 register version..*/
-#define DSPI_MEM_DATE    0x0FFFFFFF
-#define DSPI_MEM_DATE_M  ((DSPI_MEM_DATE_V)<<(DSPI_MEM_DATE_S))
-#define DSPI_MEM_DATE_V  0xFFFFFFF
-#define DSPI_MEM_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_DSPI_MEM_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h
index cfe4730526..bdb3e63aae 100644
--- a/components/soc/esp32p4/include/soc/reg_base.h
+++ b/components/soc/esp32p4/include/soc/reg_base.h
@@ -54,8 +54,8 @@
 #define DR_REG_DMA2D_BASE             (DR_REG_HPPERIPH0_BASE + 0x88000)
 #define DR_REG_KEY_MANAGER_BASE       (DR_REG_HPPERIPH0_BASE + 0x89000)
 #define DR_REG_AXI_DMA_BASE           (DR_REG_HPPERIPH0_BASE + 0x8A000)
-#define DR_REG_SPI0_BASE              (DR_REG_HPPERIPH0_BASE + 0x8C000)
-#define DR_REG_SPI1_BASE              (DR_REG_HPPERIPH0_BASE + 0x8D000)
+#define DR_REG_FLASH_SPI0_BASE        (DR_REG_HPPERIPH0_BASE + 0x8C000)
+#define DR_REG_FLASH_SPI1_BASE        (DR_REG_HPPERIPH0_BASE + 0x8D000)
 #define DR_REG_PSRAM_MSPI0_BASE       (DR_REG_HPPERIPH0_BASE + 0x8E000)
 #define DR_REG_PSRAM_MSPI1_BASE       (DR_REG_HPPERIPH0_BASE + 0x8F000)
 #define DR_REG_CRYPTO_BASE            (DR_REG_HPPERIPH0_BASE + 0x90000)
diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
index 26f56a0d21..a0e2870af6 100644
--- a/components/soc/esp32p4/include/soc/soc.h
+++ b/components/soc/esp32p4/include/soc/soc.h
@@ -21,7 +21,7 @@
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_BASE(i) + 0x0)
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1000)         // only one I2S on C6
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
-#define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
+#define REG_SPI_MEM_BASE(i)                     (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000)  // SPIMEM0 and SPIMEM1
 #define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE + (i) * 0x1000)        // GPSPI2 and GPSPI3
 #define REG_I2C_BASE(i)                         (DR_REG_I2C0_BASE + (i) * 0x1000)
 #define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE + (i) * 0x1000)
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
index 17ad59822c..09829c5cdc 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
+++ b/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
@@ -11,1470 +11,1470 @@
 extern "C" {
 #endif
 
-/** SPI_MEM_CMD_REG register
+/** SPI1_MEM_C_CMD_REG register
  *  SPI1 memory command register
  */
-#define SPI_MEM_CMD_REG (DR_REG_SPI1_BASE + 0x0)
-/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
+#define SPI1_MEM_C_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0x0)
+/** SPI1_MEM_C_MST_ST : RO; bitpos: [3:0]; default: 0;
  *  The current status of SPI1 master FSM.
  */
-#define SPI_MEM_MST_ST    0x0000000FU
-#define SPI_MEM_MST_ST_M  (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S)
-#define SPI_MEM_MST_ST_V  0x0000000FU
-#define SPI_MEM_MST_ST_S  0
-/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
+#define SPI1_MEM_C_MST_ST    0x0000000FU
+#define SPI1_MEM_C_MST_ST_M  (SPI1_MEM_C_MST_ST_V << SPI1_MEM_C_MST_ST_S)
+#define SPI1_MEM_C_MST_ST_V  0x0000000FU
+#define SPI1_MEM_C_MST_ST_S  0
+/** SPI1_MEM_C_SLV_ST : RO; bitpos: [7:4]; default: 0;
  *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
  *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
  *  6:write data state, 7: done state, 8: read data end state.
  */
-#define SPI_MEM_SLV_ST    0x0000000FU
-#define SPI_MEM_SLV_ST_M  (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S)
-#define SPI_MEM_SLV_ST_V  0x0000000FU
-#define SPI_MEM_SLV_ST_S  4
-/** SPI_MEM_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
+#define SPI1_MEM_C_SLV_ST    0x0000000FU
+#define SPI1_MEM_C_SLV_ST_M  (SPI1_MEM_C_SLV_ST_V << SPI1_MEM_C_SLV_ST_S)
+#define SPI1_MEM_C_SLV_ST_V  0x0000000FU
+#define SPI1_MEM_C_SLV_ST_S  4
+/** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
  *  In user mode, it is set to indicate that program/erase operation will be triggered.
- *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+ *  The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the
  *  operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S)
-#define SPI_MEM_FLASH_PE_V  0x00000001U
-#define SPI_MEM_FLASH_PE_S  17
-/** SPI_MEM_USR : R/W/SC; bitpos: [18]; default: 0;
+#define SPI1_MEM_C_FLASH_PE    (BIT(17))
+#define SPI1_MEM_C_FLASH_PE_M  (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S)
+#define SPI1_MEM_C_FLASH_PE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PE_S  17
+/** SPI1_MEM_C_USR : R/W/SC; bitpos: [18]; default: 0;
  *  User define command enable.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (SPI_MEM_USR_V << SPI_MEM_USR_S)
-#define SPI_MEM_USR_V  0x00000001U
-#define SPI_MEM_USR_S  18
-/** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
+#define SPI1_MEM_C_USR    (BIT(18))
+#define SPI1_MEM_C_USR_M  (SPI1_MEM_C_USR_V << SPI1_MEM_C_USR_S)
+#define SPI1_MEM_C_USR_V  0x00000001U
+#define SPI1_MEM_C_USR_S  18
+/** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
  *  Drive Flash into high performance mode.  The bit will be cleared once the operation
  *  done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S)
-#define SPI_MEM_FLASH_HPM_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_S  19
-/** SPI_MEM_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
+#define SPI1_MEM_C_FLASH_HPM    (BIT(19))
+#define SPI1_MEM_C_FLASH_HPM_M  (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S)
+#define SPI1_MEM_C_FLASH_HPM_V  0x00000001U
+#define SPI1_MEM_C_FLASH_HPM_S  19
+/** SPI1_MEM_C_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
  *  This bit combined with reg_resandres bit releases Flash from the power-down state
  *  or high performance mode and obtains the devices ID. The bit will be cleared once
  *  the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S)
-#define SPI_MEM_FLASH_RES_V  0x00000001U
-#define SPI_MEM_FLASH_RES_S  20
-/** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
+#define SPI1_MEM_C_FLASH_RES    (BIT(20))
+#define SPI1_MEM_C_FLASH_RES_M  (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S)
+#define SPI1_MEM_C_FLASH_RES_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RES_S  20
+/** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
  *  Drive Flash into power down.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S)
-#define SPI_MEM_FLASH_DP_V  0x00000001U
-#define SPI_MEM_FLASH_DP_S  21
-/** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
+#define SPI1_MEM_C_FLASH_DP    (BIT(21))
+#define SPI1_MEM_C_FLASH_DP_M  (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S)
+#define SPI1_MEM_C_FLASH_DP_V  0x00000001U
+#define SPI1_MEM_C_FLASH_DP_S  21
+/** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
  *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S)
-#define SPI_MEM_FLASH_CE_V  0x00000001U
-#define SPI_MEM_FLASH_CE_S  22
-/** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
+#define SPI1_MEM_C_FLASH_CE    (BIT(22))
+#define SPI1_MEM_C_FLASH_CE_M  (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S)
+#define SPI1_MEM_C_FLASH_CE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_CE_S  22
+/** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
  *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S)
-#define SPI_MEM_FLASH_BE_V  0x00000001U
-#define SPI_MEM_FLASH_BE_S  23
-/** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_FLASH_BE    (BIT(23))
+#define SPI1_MEM_C_FLASH_BE_M  (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S)
+#define SPI1_MEM_C_FLASH_BE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_BE_S  23
+/** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
  *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S)
-#define SPI_MEM_FLASH_SE_V  0x00000001U
-#define SPI_MEM_FLASH_SE_S  24
-/** SPI_MEM_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
+#define SPI1_MEM_C_FLASH_SE    (BIT(24))
+#define SPI1_MEM_C_FLASH_SE_M  (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S)
+#define SPI1_MEM_C_FLASH_SE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_SE_S  24
+/** SPI1_MEM_C_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
  *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
  *  operation  will be triggered when the bit is set. The bit will be cleared once the
  *  operation done .1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S)
-#define SPI_MEM_FLASH_PP_V  0x00000001U
-#define SPI_MEM_FLASH_PP_S  25
-/** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
+#define SPI1_MEM_C_FLASH_PP    (BIT(25))
+#define SPI1_MEM_C_FLASH_PP_M  (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S)
+#define SPI1_MEM_C_FLASH_PP_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PP_S  25
+/** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
  *  Write status register enable.   Write status operation  will be triggered when the
  *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S)
-#define SPI_MEM_FLASH_WRSR_V  0x00000001U
-#define SPI_MEM_FLASH_WRSR_S  26
-/** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
+#define SPI1_MEM_C_FLASH_WRSR    (BIT(26))
+#define SPI1_MEM_C_FLASH_WRSR_M  (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S)
+#define SPI1_MEM_C_FLASH_WRSR_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WRSR_S  26
+/** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
  *  Read status register-1.  Read status operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S)
-#define SPI_MEM_FLASH_RDSR_V  0x00000001U
-#define SPI_MEM_FLASH_RDSR_S  27
-/** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
+#define SPI1_MEM_C_FLASH_RDSR    (BIT(27))
+#define SPI1_MEM_C_FLASH_RDSR_M  (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S)
+#define SPI1_MEM_C_FLASH_RDSR_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RDSR_S  27
+/** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
  *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
  *  cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S)
-#define SPI_MEM_FLASH_RDID_V  0x00000001U
-#define SPI_MEM_FLASH_RDID_S  28
-/** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
+#define SPI1_MEM_C_FLASH_RDID    (BIT(28))
+#define SPI1_MEM_C_FLASH_RDID_M  (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S)
+#define SPI1_MEM_C_FLASH_RDID_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RDID_S  28
+/** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
  *  Write flash disable. Write disable command will be sent when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S)
-#define SPI_MEM_FLASH_WRDI_V  0x00000001U
-#define SPI_MEM_FLASH_WRDI_S  29
-/** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
+#define SPI1_MEM_C_FLASH_WRDI    (BIT(29))
+#define SPI1_MEM_C_FLASH_WRDI_M  (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S)
+#define SPI1_MEM_C_FLASH_WRDI_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WRDI_S  29
+/** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
  *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
  *  will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S)
-#define SPI_MEM_FLASH_WREN_V  0x00000001U
-#define SPI_MEM_FLASH_WREN_S  30
-/** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
+#define SPI1_MEM_C_FLASH_WREN    (BIT(30))
+#define SPI1_MEM_C_FLASH_WREN_M  (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S)
+#define SPI1_MEM_C_FLASH_WREN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WREN_S  30
+/** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
  *  Read flash enable. Read flash operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S)
-#define SPI_MEM_FLASH_READ_V  0x00000001U
-#define SPI_MEM_FLASH_READ_S  31
+#define SPI1_MEM_C_FLASH_READ    (BIT(31))
+#define SPI1_MEM_C_FLASH_READ_M  (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S)
+#define SPI1_MEM_C_FLASH_READ_V  0x00000001U
+#define SPI1_MEM_C_FLASH_READ_S  31
 
-/** SPI_MEM_ADDR_REG register
+/** SPI1_MEM_C_ADDR_REG register
  *  SPI1 address register
  */
-#define SPI_MEM_ADDR_REG (DR_REG_SPI1_BASE + 0x4)
-/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_ADDR_REG (DR_REG_FLASH_SPI1_BASE + 0x4)
+/** SPI1_MEM_C_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
  *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
  *  address, the bit24-bit31 are the byte length of a transfer.
  */
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_M  (SPI_MEM_USR_ADDR_VALUE_V << SPI_MEM_USR_ADDR_VALUE_S)
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_S  0
+#define SPI1_MEM_C_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI1_MEM_C_USR_ADDR_VALUE_M  (SPI1_MEM_C_USR_ADDR_VALUE_V << SPI1_MEM_C_USR_ADDR_VALUE_S)
+#define SPI1_MEM_C_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI1_MEM_C_USR_ADDR_VALUE_S  0
 
-/** SPI_MEM_CTRL_REG register
+/** SPI1_MEM_C_CTRL_REG register
  *  SPI1 control register.
  */
-#define SPI_MEM_CTRL_REG (DR_REG_SPI1_BASE + 0x8)
-/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+#define SPI1_MEM_C_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x8)
+/** SPI1_MEM_C_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
  *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S)
-#define SPI_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI_MEM_FDUMMY_RIN_S  2
-/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+#define SPI1_MEM_C_FDUMMY_RIN    (BIT(2))
+#define SPI1_MEM_C_FDUMMY_RIN_M  (SPI1_MEM_C_FDUMMY_RIN_V << SPI1_MEM_C_FDUMMY_RIN_S)
+#define SPI1_MEM_C_FDUMMY_RIN_V  0x00000001U
+#define SPI1_MEM_C_FDUMMY_RIN_S  2
+/** SPI1_MEM_C_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
  *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S)
-#define SPI_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FDUMMY_WOUT    (BIT(3))
+#define SPI1_MEM_C_FDUMMY_WOUT_M  (SPI1_MEM_C_FDUMMY_WOUT_V << SPI1_MEM_C_FDUMMY_WOUT_S)
+#define SPI1_MEM_C_FDUMMY_WOUT_V  0x00000001U
+#define SPI1_MEM_C_FDUMMY_WOUT_S  3
+/** SPI1_MEM_C_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
  *  Apply 8 signals during write-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S)
-#define SPI_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI_MEM_FDOUT_OCT_S  4
-/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0;
+#define SPI1_MEM_C_FDOUT_OCT    (BIT(4))
+#define SPI1_MEM_C_FDOUT_OCT_M  (SPI1_MEM_C_FDOUT_OCT_V << SPI1_MEM_C_FDOUT_OCT_S)
+#define SPI1_MEM_C_FDOUT_OCT_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_OCT_S  4
+/** SPI1_MEM_C_FDIN_OCT : HRO; bitpos: [5]; default: 0;
  *  Apply 8 signals during read-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S)
-#define SPI_MEM_FDIN_OCT_V  0x00000001U
-#define SPI_MEM_FDIN_OCT_S  5
-/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0;
+#define SPI1_MEM_C_FDIN_OCT    (BIT(5))
+#define SPI1_MEM_C_FDIN_OCT_M  (SPI1_MEM_C_FDIN_OCT_V << SPI1_MEM_C_FDIN_OCT_S)
+#define SPI1_MEM_C_FDIN_OCT_V  0x00000001U
+#define SPI1_MEM_C_FDIN_OCT_S  5
+/** SPI1_MEM_C_FADDR_OCT : HRO; bitpos: [6]; default: 0;
  *  Apply 8 signals during address phase 1:enable 0: disable
  */
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S)
-#define SPI_MEM_FADDR_OCT_V  0x00000001U
-#define SPI_MEM_FADDR_OCT_S  6
-/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_C_FADDR_OCT    (BIT(6))
+#define SPI1_MEM_C_FADDR_OCT_M  (SPI1_MEM_C_FADDR_OCT_V << SPI1_MEM_C_FADDR_OCT_S)
+#define SPI1_MEM_C_FADDR_OCT_V  0x00000001U
+#define SPI1_MEM_C_FADDR_OCT_S  6
+/** SPI1_MEM_C_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
  *  Apply 4 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S)
-#define SPI_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI_MEM_FCMD_QUAD_S  8
-/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0;
+#define SPI1_MEM_C_FCMD_QUAD    (BIT(8))
+#define SPI1_MEM_C_FCMD_QUAD_M  (SPI1_MEM_C_FCMD_QUAD_V << SPI1_MEM_C_FCMD_QUAD_S)
+#define SPI1_MEM_C_FCMD_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FCMD_QUAD_S  8
+/** SPI1_MEM_C_FCMD_OCT : HRO; bitpos: [9]; default: 0;
  *  Apply 8 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S)
-#define SPI_MEM_FCMD_OCT_V  0x00000001U
-#define SPI_MEM_FCMD_OCT_S  9
-/** SPI_MEM_FCS_CRC_EN : HRO; bitpos: [10]; default: 0;
+#define SPI1_MEM_C_FCMD_OCT    (BIT(9))
+#define SPI1_MEM_C_FCMD_OCT_M  (SPI1_MEM_C_FCMD_OCT_V << SPI1_MEM_C_FCMD_OCT_S)
+#define SPI1_MEM_C_FCMD_OCT_V  0x00000001U
+#define SPI1_MEM_C_FCMD_OCT_S  9
+/** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0;
  *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
  *  low.
  */
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S)
-#define SPI_MEM_FCS_CRC_EN_V  0x00000001U
-#define SPI_MEM_FCS_CRC_EN_S  10
-/** SPI_MEM_TX_CRC_EN : HRO; bitpos: [11]; default: 0;
+#define SPI1_MEM_C_FCS_CRC_EN    (BIT(10))
+#define SPI1_MEM_C_FCS_CRC_EN_M  (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S)
+#define SPI1_MEM_C_FCS_CRC_EN_V  0x00000001U
+#define SPI1_MEM_C_FCS_CRC_EN_S  10
+/** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0;
  *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
  */
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S)
-#define SPI_MEM_TX_CRC_EN_V  0x00000001U
-#define SPI_MEM_TX_CRC_EN_S  11
-/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
- *  and spi_mem_fread_dout. 1: enable 0: disable.
+#define SPI1_MEM_C_TX_CRC_EN    (BIT(11))
+#define SPI1_MEM_C_TX_CRC_EN_M  (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S)
+#define SPI1_MEM_C_TX_CRC_EN_V  0x00000001U
+#define SPI1_MEM_C_TX_CRC_EN_S  11
+/** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout
+ *  and spi1_mem_c_fread_dout. 1: enable 0: disable.
  */
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S)
-#define SPI_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI_MEM_FASTRD_MODE_S  13
-/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_C_FASTRD_MODE    (BIT(13))
+#define SPI1_MEM_C_FASTRD_MODE_M  (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S)
+#define SPI1_MEM_C_FASTRD_MODE_V  0x00000001U
+#define SPI1_MEM_C_FASTRD_MODE_S  13
+/** SPI1_MEM_C_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
  *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S)
-#define SPI_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI_MEM_FREAD_DUAL_S  14
-/** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1;
- *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
- *  spi_mem_flash_res bit. 1: enable 0: disable.
+#define SPI1_MEM_C_FREAD_DUAL    (BIT(14))
+#define SPI1_MEM_C_FREAD_DUAL_M  (SPI1_MEM_C_FREAD_DUAL_V << SPI1_MEM_C_FREAD_DUAL_S)
+#define SPI1_MEM_C_FREAD_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FREAD_DUAL_S  14
+/** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1;
+ *  The Device ID is read out to SPI1_MEM_C_RD_STATUS register,  this bit combine with
+ *  spi1_mem_c_flash_res bit. 1: enable 0: disable.
  */
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S)
-#define SPI_MEM_RESANDRES_V  0x00000001U
-#define SPI_MEM_RESANDRES_S  15
-/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
+#define SPI1_MEM_C_RESANDRES    (BIT(15))
+#define SPI1_MEM_C_RESANDRES_M  (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S)
+#define SPI1_MEM_C_RESANDRES_V  0x00000001U
+#define SPI1_MEM_C_RESANDRES_S  15
+/** SPI1_MEM_C_Q_POL : R/W; bitpos: [18]; default: 1;
  *  The bit is used to set MISO line polarity, 1: high 0, low
  */
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S)
-#define SPI_MEM_Q_POL_V  0x00000001U
-#define SPI_MEM_Q_POL_S  18
-/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1;
+#define SPI1_MEM_C_Q_POL    (BIT(18))
+#define SPI1_MEM_C_Q_POL_M  (SPI1_MEM_C_Q_POL_V << SPI1_MEM_C_Q_POL_S)
+#define SPI1_MEM_C_Q_POL_V  0x00000001U
+#define SPI1_MEM_C_Q_POL_S  18
+/** SPI1_MEM_C_D_POL : R/W; bitpos: [19]; default: 1;
  *  The bit is used to set MOSI line polarity, 1: high 0, low
  */
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S)
-#define SPI_MEM_D_POL_V  0x00000001U
-#define SPI_MEM_D_POL_S  19
-/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+#define SPI1_MEM_C_D_POL    (BIT(19))
+#define SPI1_MEM_C_D_POL_M  (SPI1_MEM_C_D_POL_V << SPI1_MEM_C_D_POL_S)
+#define SPI1_MEM_C_D_POL_V  0x00000001U
+#define SPI1_MEM_C_D_POL_S  19
+/** SPI1_MEM_C_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
  *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S)
-#define SPI_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI_MEM_FREAD_QUAD_S  20
-/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
+#define SPI1_MEM_C_FREAD_QUAD    (BIT(20))
+#define SPI1_MEM_C_FREAD_QUAD_M  (SPI1_MEM_C_FREAD_QUAD_V << SPI1_MEM_C_FREAD_QUAD_S)
+#define SPI1_MEM_C_FREAD_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FREAD_QUAD_S  20
+/** SPI1_MEM_C_WP_REG : R/W; bitpos: [21]; default: 1;
  *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
  */
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S)
-#define SPI_MEM_WP_REG_V  0x00000001U
-#define SPI_MEM_WP_REG_S  21
-/** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_C_WP_REG    (BIT(21))
+#define SPI1_MEM_C_WP_REG_M  (SPI1_MEM_C_WP_REG_V << SPI1_MEM_C_WP_REG_S)
+#define SPI1_MEM_C_WP_REG_V  0x00000001U
+#define SPI1_MEM_C_WP_REG_S  21
+/** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0;
  *  two bytes data will be written to status register when it is set. 1: enable 0:
  *  disable.
  */
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S)
-#define SPI_MEM_WRSR_2B_V  0x00000001U
-#define SPI_MEM_WRSR_2B_S  22
-/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_C_WRSR_2B    (BIT(22))
+#define SPI1_MEM_C_WRSR_2B_M  (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S)
+#define SPI1_MEM_C_WRSR_2B_V  0x00000001U
+#define SPI1_MEM_C_WRSR_2B_S  22
+/** SPI1_MEM_C_FREAD_DIO : R/W; bitpos: [23]; default: 0;
  *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S)
-#define SPI_MEM_FREAD_DIO_V  0x00000001U
-#define SPI_MEM_FREAD_DIO_S  23
-/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_FREAD_DIO    (BIT(23))
+#define SPI1_MEM_C_FREAD_DIO_M  (SPI1_MEM_C_FREAD_DIO_V << SPI1_MEM_C_FREAD_DIO_S)
+#define SPI1_MEM_C_FREAD_DIO_V  0x00000001U
+#define SPI1_MEM_C_FREAD_DIO_S  23
+/** SPI1_MEM_C_FREAD_QIO : R/W; bitpos: [24]; default: 0;
  *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S)
-#define SPI_MEM_FREAD_QIO_V  0x00000001U
-#define SPI_MEM_FREAD_QIO_S  24
+#define SPI1_MEM_C_FREAD_QIO    (BIT(24))
+#define SPI1_MEM_C_FREAD_QIO_M  (SPI1_MEM_C_FREAD_QIO_V << SPI1_MEM_C_FREAD_QIO_S)
+#define SPI1_MEM_C_FREAD_QIO_V  0x00000001U
+#define SPI1_MEM_C_FREAD_QIO_S  24
 
-/** SPI_MEM_CTRL1_REG register
+/** SPI1_MEM_C_CTRL1_REG register
  *  SPI1 control1 register.
  */
-#define SPI_MEM_CTRL1_REG (DR_REG_SPI1_BASE + 0xc)
-/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+#define SPI1_MEM_C_CTRL1_REG (DR_REG_FLASH_SPI1_BASE + 0xc)
+/** SPI1_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
  *  SPI clock is alwasy on.
  */
-#define SPI_MEM_CLK_MODE    0x00000003U
-#define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
-#define SPI_MEM_CLK_MODE_V  0x00000003U
-#define SPI_MEM_CLK_MODE_S  0
-/** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
- *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+#define SPI1_MEM_C_CLK_MODE    0x00000003U
+#define SPI1_MEM_C_CLK_MODE_M  (SPI1_MEM_C_CLK_MODE_V << SPI1_MEM_C_CLK_MODE_S)
+#define SPI1_MEM_C_CLK_MODE_V  0x00000003U
+#define SPI1_MEM_C_CLK_MODE_S  0
+/** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
+ *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512)
  *  SPI_CLK cycles.
  */
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_M  (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S)
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+#define SPI1_MEM_C_CS_HOLD_DLY_RES    0x000003FFU
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_M  (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S)
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_V  0x000003FFU
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_S  2
 
-/** SPI_MEM_CTRL2_REG register
+/** SPI1_MEM_C_CTRL2_REG register
  *  SPI1 control2 register.
  */
-#define SPI_MEM_CTRL2_REG (DR_REG_SPI1_BASE + 0x10)
-/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
+#define SPI1_MEM_C_CTRL2_REG (DR_REG_FLASH_SPI1_BASE + 0x10)
+/** SPI1_MEM_C_SYNC_RESET : WT; bitpos: [31]; default: 0;
  *  The FSM will be reset.
  */
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S)
-#define SPI_MEM_SYNC_RESET_V  0x00000001U
-#define SPI_MEM_SYNC_RESET_S  31
+#define SPI1_MEM_C_SYNC_RESET    (BIT(31))
+#define SPI1_MEM_C_SYNC_RESET_M  (SPI1_MEM_C_SYNC_RESET_V << SPI1_MEM_C_SYNC_RESET_S)
+#define SPI1_MEM_C_SYNC_RESET_V  0x00000001U
+#define SPI1_MEM_C_SYNC_RESET_S  31
 
-/** SPI_MEM_CLOCK_REG register
+/** SPI1_MEM_C_CLOCK_REG register
  *  SPI1 clock division control register.
  */
-#define SPI_MEM_CLOCK_REG (DR_REG_SPI1_BASE + 0x14)
-/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
- *  In the master mode it must be equal to spi_mem_clkcnt_N.
+#define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14)
+/** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi1_mem_c_clkcnt_N.
  */
-#define SPI_MEM_CLKCNT_L    0x000000FFU
-#define SPI_MEM_CLKCNT_L_M  (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
-#define SPI_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI_MEM_CLKCNT_L_S  0
-/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
- *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+#define SPI1_MEM_C_CLKCNT_L    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_L_M  (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S)
+#define SPI1_MEM_C_CLKCNT_L_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_L_S  0
+/** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1).
  */
-#define SPI_MEM_CLKCNT_H    0x000000FFU
-#define SPI_MEM_CLKCNT_H_M  (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
-#define SPI_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI_MEM_CLKCNT_H_S  8
-/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
- *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- *  system/(spi_mem_clkcnt_N+1)
+#define SPI1_MEM_C_CLKCNT_H    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_H_M  (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S)
+#define SPI1_MEM_C_CLKCNT_H_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_H_S  8
+/** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is
+ *  system/(spi1_mem_c_clkcnt_N+1)
  */
-#define SPI_MEM_CLKCNT_N    0x000000FFU
-#define SPI_MEM_CLKCNT_N_M  (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
-#define SPI_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI_MEM_CLKCNT_N_S  16
-/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+#define SPI1_MEM_C_CLKCNT_N    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_N_M  (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S)
+#define SPI1_MEM_C_CLKCNT_N_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_N_S  16
+/** SPI1_MEM_C_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
  *  reserved
  */
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S)
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+#define SPI1_MEM_C_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_M  (SPI1_MEM_C_CLK_EQU_SYSCLK_V << SPI1_MEM_C_CLK_EQU_SYSCLK_S)
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_S  31
 
-/** SPI_MEM_USER_REG register
+/** SPI1_MEM_C_USER_REG register
  *  SPI1 user register.
  */
-#define SPI_MEM_USER_REG (DR_REG_SPI1_BASE + 0x18)
-/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+#define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18)
+/** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode.
  */
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S)
-#define SPI_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/** SPI_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+#define SPI1_MEM_C_CK_OUT_EDGE    (BIT(9))
+#define SPI1_MEM_C_CK_OUT_EDGE_M  (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S)
+#define SPI1_MEM_C_CK_OUT_EDGE_V  0x00000001U
+#define SPI1_MEM_C_CK_OUT_EDGE_S  9
+/** SPI1_MEM_C_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
  *  In the write operations read-data phase apply 2 signals
  */
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (SPI_MEM_FWRITE_DUAL_V << SPI_MEM_FWRITE_DUAL_S)
-#define SPI_MEM_FWRITE_DUAL_V  0x00000001U
-#define SPI_MEM_FWRITE_DUAL_S  12
-/** SPI_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+#define SPI1_MEM_C_FWRITE_DUAL    (BIT(12))
+#define SPI1_MEM_C_FWRITE_DUAL_M  (SPI1_MEM_C_FWRITE_DUAL_V << SPI1_MEM_C_FWRITE_DUAL_S)
+#define SPI1_MEM_C_FWRITE_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_DUAL_S  12
+/** SPI1_MEM_C_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
  *  In the write operations read-data phase apply 4 signals
  */
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (SPI_MEM_FWRITE_QUAD_V << SPI_MEM_FWRITE_QUAD_S)
-#define SPI_MEM_FWRITE_QUAD_V  0x00000001U
-#define SPI_MEM_FWRITE_QUAD_S  13
-/** SPI_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_C_FWRITE_QUAD    (BIT(13))
+#define SPI1_MEM_C_FWRITE_QUAD_M  (SPI1_MEM_C_FWRITE_QUAD_V << SPI1_MEM_C_FWRITE_QUAD_S)
+#define SPI1_MEM_C_FWRITE_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_QUAD_S  13
+/** SPI1_MEM_C_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
  *  In the write operations address phase and read-data phase apply 2 signals.
  */
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (SPI_MEM_FWRITE_DIO_V << SPI_MEM_FWRITE_DIO_S)
-#define SPI_MEM_FWRITE_DIO_V  0x00000001U
-#define SPI_MEM_FWRITE_DIO_S  14
-/** SPI_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_C_FWRITE_DIO    (BIT(14))
+#define SPI1_MEM_C_FWRITE_DIO_M  (SPI1_MEM_C_FWRITE_DIO_V << SPI1_MEM_C_FWRITE_DIO_S)
+#define SPI1_MEM_C_FWRITE_DIO_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_DIO_S  14
+/** SPI1_MEM_C_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
  *  In the write operations address phase and read-data phase apply 4 signals.
  */
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (SPI_MEM_FWRITE_QIO_V << SPI_MEM_FWRITE_QIO_S)
-#define SPI_MEM_FWRITE_QIO_V  0x00000001U
-#define SPI_MEM_FWRITE_QIO_S  15
-/** SPI_MEM_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_C_FWRITE_QIO    (BIT(15))
+#define SPI1_MEM_C_FWRITE_QIO_M  (SPI1_MEM_C_FWRITE_QIO_V << SPI1_MEM_C_FWRITE_QIO_S)
+#define SPI1_MEM_C_FWRITE_QIO_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_QIO_S  15
+/** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (SPI_MEM_USR_MISO_HIGHPART_V << SPI_MEM_USR_MISO_HIGHPART_S)
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/** SPI_MEM_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_C_USR_MISO_HIGHPART    (BIT(24))
+#define SPI1_MEM_C_USR_MISO_HIGHPART_M  (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S)
+#define SPI1_MEM_C_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI1_MEM_C_USR_MISO_HIGHPART_S  24
+/** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (SPI_MEM_USR_MOSI_HIGHPART_V << SPI_MEM_USR_MOSI_HIGHPART_S)
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+#define SPI1_MEM_C_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_M  (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S)
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_S  25
+/** SPI1_MEM_C_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
  *  SPI clock is disable in dummy phase when the bit is enable.
  */
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S)
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/** SPI_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0;
+#define SPI1_MEM_C_USR_DUMMY_IDLE    (BIT(26))
+#define SPI1_MEM_C_USR_DUMMY_IDLE_M  (SPI1_MEM_C_USR_DUMMY_IDLE_V << SPI1_MEM_C_USR_DUMMY_IDLE_S)
+#define SPI1_MEM_C_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI1_MEM_C_USR_DUMMY_IDLE_S  26
+/** SPI1_MEM_C_USR_MOSI : R/W; bitpos: [27]; default: 0;
  *  This bit enable the write-data phase of an operation.
  */
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (SPI_MEM_USR_MOSI_V << SPI_MEM_USR_MOSI_S)
-#define SPI_MEM_USR_MOSI_V  0x00000001U
-#define SPI_MEM_USR_MOSI_S  27
-/** SPI_MEM_USR_MISO : R/W; bitpos: [28]; default: 0;
+#define SPI1_MEM_C_USR_MOSI    (BIT(27))
+#define SPI1_MEM_C_USR_MOSI_M  (SPI1_MEM_C_USR_MOSI_V << SPI1_MEM_C_USR_MOSI_S)
+#define SPI1_MEM_C_USR_MOSI_V  0x00000001U
+#define SPI1_MEM_C_USR_MOSI_S  27
+/** SPI1_MEM_C_USR_MISO : R/W; bitpos: [28]; default: 0;
  *  This bit enable the read-data phase of an operation.
  */
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (SPI_MEM_USR_MISO_V << SPI_MEM_USR_MISO_S)
-#define SPI_MEM_USR_MISO_V  0x00000001U
-#define SPI_MEM_USR_MISO_S  28
-/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+#define SPI1_MEM_C_USR_MISO    (BIT(28))
+#define SPI1_MEM_C_USR_MISO_M  (SPI1_MEM_C_USR_MISO_V << SPI1_MEM_C_USR_MISO_S)
+#define SPI1_MEM_C_USR_MISO_V  0x00000001U
+#define SPI1_MEM_C_USR_MISO_S  28
+/** SPI1_MEM_C_USR_DUMMY : R/W; bitpos: [29]; default: 0;
  *  This bit enable the dummy phase of an operation.
  */
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S)
-#define SPI_MEM_USR_DUMMY_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_S  29
-/** SPI_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0;
+#define SPI1_MEM_C_USR_DUMMY    (BIT(29))
+#define SPI1_MEM_C_USR_DUMMY_M  (SPI1_MEM_C_USR_DUMMY_V << SPI1_MEM_C_USR_DUMMY_S)
+#define SPI1_MEM_C_USR_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_USR_DUMMY_S  29
+/** SPI1_MEM_C_USR_ADDR : R/W; bitpos: [30]; default: 0;
  *  This bit enable the address phase of an operation.
  */
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (SPI_MEM_USR_ADDR_V << SPI_MEM_USR_ADDR_S)
-#define SPI_MEM_USR_ADDR_V  0x00000001U
-#define SPI_MEM_USR_ADDR_S  30
-/** SPI_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+#define SPI1_MEM_C_USR_ADDR    (BIT(30))
+#define SPI1_MEM_C_USR_ADDR_M  (SPI1_MEM_C_USR_ADDR_V << SPI1_MEM_C_USR_ADDR_S)
+#define SPI1_MEM_C_USR_ADDR_V  0x00000001U
+#define SPI1_MEM_C_USR_ADDR_S  30
+/** SPI1_MEM_C_USR_COMMAND : R/W; bitpos: [31]; default: 1;
  *  This bit enable the command phase of an operation.
  */
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (SPI_MEM_USR_COMMAND_V << SPI_MEM_USR_COMMAND_S)
-#define SPI_MEM_USR_COMMAND_V  0x00000001U
-#define SPI_MEM_USR_COMMAND_S  31
+#define SPI1_MEM_C_USR_COMMAND    (BIT(31))
+#define SPI1_MEM_C_USR_COMMAND_M  (SPI1_MEM_C_USR_COMMAND_V << SPI1_MEM_C_USR_COMMAND_S)
+#define SPI1_MEM_C_USR_COMMAND_V  0x00000001U
+#define SPI1_MEM_C_USR_COMMAND_S  31
 
-/** SPI_MEM_USER1_REG register
+/** SPI1_MEM_C_USER1_REG register
  *  SPI1 user1 register.
  */
-#define SPI_MEM_USER1_REG (DR_REG_SPI1_BASE + 0x1c)
-/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
- *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+#define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c)
+/** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1).
  */
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_M  (SPI1_MEM_C_USR_DUMMY_CYCLELEN_V << SPI1_MEM_C_USR_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_S  0
+/** SPI1_MEM_C_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
  *  The length in bits of address phase. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_M  (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S)
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
+#define SPI1_MEM_C_USR_ADDR_BITLEN    0x0000003FU
+#define SPI1_MEM_C_USR_ADDR_BITLEN_M  (SPI1_MEM_C_USR_ADDR_BITLEN_V << SPI1_MEM_C_USR_ADDR_BITLEN_S)
+#define SPI1_MEM_C_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI1_MEM_C_USR_ADDR_BITLEN_S  26
 
-/** SPI_MEM_USER2_REG register
+/** SPI1_MEM_C_USER2_REG register
  *  SPI1 user2 register.
  */
-#define SPI_MEM_USER2_REG (DR_REG_SPI1_BASE + 0x20)
-/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+#define SPI1_MEM_C_USER2_REG (DR_REG_FLASH_SPI1_BASE + 0x20)
+/** SPI1_MEM_C_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command.
  */
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_M  (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S)
-#define SPI_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+#define SPI1_MEM_C_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI1_MEM_C_USR_COMMAND_VALUE_M  (SPI1_MEM_C_USR_COMMAND_VALUE_V << SPI1_MEM_C_USR_COMMAND_VALUE_S)
+#define SPI1_MEM_C_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI1_MEM_C_USR_COMMAND_VALUE_S  0
+/** SPI1_MEM_C_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
  *  The length in bits of command phase. The register value shall be (bit_num-1)
  */
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_M  (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S)
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+#define SPI1_MEM_C_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_M  (SPI1_MEM_C_USR_COMMAND_BITLEN_V << SPI1_MEM_C_USR_COMMAND_BITLEN_S)
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_S  28
 
-/** SPI_MEM_MOSI_DLEN_REG register
+/** SPI1_MEM_C_MOSI_DLEN_REG register
  *  SPI1 send data bit length control register.
  */
-#define SPI_MEM_MOSI_DLEN_REG (DR_REG_SPI1_BASE + 0x24)
-/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_C_MOSI_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x24)
+/** SPI1_MEM_C_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of write-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_M  (SPI_MEM_USR_MOSI_DBITLEN_V << SPI_MEM_USR_MOSI_DBITLEN_S)
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+#define SPI1_MEM_C_USR_MOSI_DBITLEN    0x000003FFU
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_M  (SPI1_MEM_C_USR_MOSI_DBITLEN_V << SPI1_MEM_C_USR_MOSI_DBITLEN_S)
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_S  0
 
-/** SPI_MEM_MISO_DLEN_REG register
+/** SPI1_MEM_C_MISO_DLEN_REG register
  *  SPI1 receive data bit length control register.
  */
-#define SPI_MEM_MISO_DLEN_REG (DR_REG_SPI1_BASE + 0x28)
-/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_C_MISO_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x28)
+/** SPI1_MEM_C_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of  read-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_M  (SPI_MEM_USR_MISO_DBITLEN_V << SPI_MEM_USR_MISO_DBITLEN_S)
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
+#define SPI1_MEM_C_USR_MISO_DBITLEN    0x000003FFU
+#define SPI1_MEM_C_USR_MISO_DBITLEN_M  (SPI1_MEM_C_USR_MISO_DBITLEN_V << SPI1_MEM_C_USR_MISO_DBITLEN_S)
+#define SPI1_MEM_C_USR_MISO_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_C_USR_MISO_DBITLEN_S  0
 
-/** SPI_MEM_RD_STATUS_REG register
+/** SPI1_MEM_C_RD_STATUS_REG register
  *  SPI1 status register.
  */
-#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI1_BASE + 0x2c)
-/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
- *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+#define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c)
+/** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
+ *  The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit.
  */
-#define SPI_MEM_STATUS    0x0000FFFFU
-#define SPI_MEM_STATUS_M  (SPI_MEM_STATUS_V << SPI_MEM_STATUS_S)
-#define SPI_MEM_STATUS_V  0x0000FFFFU
-#define SPI_MEM_STATUS_S  0
-/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
- *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+#define SPI1_MEM_C_STATUS    0x0000FFFFU
+#define SPI1_MEM_C_STATUS_M  (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S)
+#define SPI1_MEM_C_STATUS_V  0x0000FFFFU
+#define SPI1_MEM_C_STATUS_S  0
+/** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi1_mem_c_fastrd_mode bit.
  */
-#define SPI_MEM_WB_MODE    0x000000FFU
-#define SPI_MEM_WB_MODE_M  (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
-#define SPI_MEM_WB_MODE_V  0x000000FFU
-#define SPI_MEM_WB_MODE_S  16
+#define SPI1_MEM_C_WB_MODE    0x000000FFU
+#define SPI1_MEM_C_WB_MODE_M  (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S)
+#define SPI1_MEM_C_WB_MODE_V  0x000000FFU
+#define SPI1_MEM_C_WB_MODE_S  16
 
-/** SPI_MEM_MISC_REG register
+/** SPI1_MEM_C_MISC_REG register
  *  SPI1 misc register
  */
-#define SPI_MEM_MISC_REG (DR_REG_SPI1_BASE + 0x34)
-/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_MISC_REG (DR_REG_FLASH_SPI1_BASE + 0x34)
+/** SPI1_MEM_C_CS0_DIS : R/W; bitpos: [0]; default: 0;
  *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (SPI_MEM_CS0_DIS_V << SPI_MEM_CS0_DIS_S)
-#define SPI_MEM_CS0_DIS_V  0x00000001U
-#define SPI_MEM_CS0_DIS_S  0
-/** SPI_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1;
+#define SPI1_MEM_C_CS0_DIS    (BIT(0))
+#define SPI1_MEM_C_CS0_DIS_M  (SPI1_MEM_C_CS0_DIS_V << SPI1_MEM_C_CS0_DIS_S)
+#define SPI1_MEM_C_CS0_DIS_V  0x00000001U
+#define SPI1_MEM_C_CS0_DIS_S  0
+/** SPI1_MEM_C_CS1_DIS : R/W; bitpos: [1]; default: 1;
  *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (SPI_MEM_CS1_DIS_V << SPI_MEM_CS1_DIS_S)
-#define SPI_MEM_CS1_DIS_V  0x00000001U
-#define SPI_MEM_CS1_DIS_S  1
-/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_C_CS1_DIS    (BIT(1))
+#define SPI1_MEM_C_CS1_DIS_M  (SPI1_MEM_C_CS1_DIS_V << SPI1_MEM_C_CS1_DIS_S)
+#define SPI1_MEM_C_CS1_DIS_V  0x00000001U
+#define SPI1_MEM_C_CS1_DIS_S  1
+/** SPI1_MEM_C_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
  *  1: spi clk line is high when idle     0: spi clk line is low when idle
  */
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S)
-#define SPI_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+#define SPI1_MEM_C_CK_IDLE_EDGE    (BIT(9))
+#define SPI1_MEM_C_CK_IDLE_EDGE_M  (SPI1_MEM_C_CK_IDLE_EDGE_V << SPI1_MEM_C_CK_IDLE_EDGE_S)
+#define SPI1_MEM_C_CK_IDLE_EDGE_V  0x00000001U
+#define SPI1_MEM_C_CK_IDLE_EDGE_S  9
+/** SPI1_MEM_C_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
  *  spi cs line keep low when the bit is set.
  */
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S)
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+#define SPI1_MEM_C_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_M  (SPI1_MEM_C_CS_KEEP_ACTIVE_V << SPI1_MEM_C_CS_KEEP_ACTIVE_S)
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_S  10
 
-/** SPI_MEM_TX_CRC_REG register
+/** SPI1_MEM_C_TX_CRC_REG register
  *  SPI1 TX CRC data register.
  */
-#define SPI_MEM_TX_CRC_REG (DR_REG_SPI1_BASE + 0x38)
-/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
+#define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38)
+/** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
  *  For SPI1, the value of crc32.
  */
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_M  (SPI_MEM_TX_CRC_DATA_V << SPI_MEM_TX_CRC_DATA_S)
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_S  0
+#define SPI1_MEM_C_TX_CRC_DATA    0xFFFFFFFFU
+#define SPI1_MEM_C_TX_CRC_DATA_M  (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S)
+#define SPI1_MEM_C_TX_CRC_DATA_V  0xFFFFFFFFU
+#define SPI1_MEM_C_TX_CRC_DATA_S  0
 
-/** SPI_MEM_CACHE_FCTRL_REG register
+/** SPI1_MEM_C_CACHE_FCTRL_REG register
  *  SPI1 bit mode control register.
  */
-#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI1_BASE + 0x3c)
-/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c)
+/** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
  *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
  */
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S)
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x00000001U
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M  (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S)
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V  0x00000001U
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S  1
+/** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
  *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
- *  spi_mem_fread_dio.
+ *  spi1_mem_c_fread_dio.
  */
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S)
-#define SPI_MEM_FDIN_DUAL_V  0x00000001U
-#define SPI_MEM_FDIN_DUAL_S  3
-/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FDIN_DUAL    (BIT(3))
+#define SPI1_MEM_C_FDIN_DUAL_M  (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S)
+#define SPI1_MEM_C_FDIN_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FDIN_DUAL_S  3
+/** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
  *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_c_fread_dio.
  */
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S)
-#define SPI_MEM_FDOUT_DUAL_V  0x00000001U
-#define SPI_MEM_FDOUT_DUAL_S  4
-/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_C_FDOUT_DUAL    (BIT(4))
+#define SPI1_MEM_C_FDOUT_DUAL_M  (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S)
+#define SPI1_MEM_C_FDOUT_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_DUAL_S  4
+/** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
  *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_c_fread_dio.
  */
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S)
-#define SPI_MEM_FADDR_DUAL_V  0x00000001U
-#define SPI_MEM_FADDR_DUAL_S  5
-/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
+#define SPI1_MEM_C_FADDR_DUAL    (BIT(5))
+#define SPI1_MEM_C_FADDR_DUAL_M  (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S)
+#define SPI1_MEM_C_FADDR_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FADDR_DUAL_S  5
+/** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
  *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_c_fread_qio.
  */
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S)
-#define SPI_MEM_FDIN_QUAD_V  0x00000001U
-#define SPI_MEM_FDIN_QUAD_S  6
-/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_C_FDIN_QUAD    (BIT(6))
+#define SPI1_MEM_C_FDIN_QUAD_M  (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S)
+#define SPI1_MEM_C_FDIN_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FDIN_QUAD_S  6
+/** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
  *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_c_fread_qio.
  */
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S)
-#define SPI_MEM_FDOUT_QUAD_V  0x00000001U
-#define SPI_MEM_FDOUT_QUAD_S  7
-/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_C_FDOUT_QUAD    (BIT(7))
+#define SPI1_MEM_C_FDOUT_QUAD_M  (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S)
+#define SPI1_MEM_C_FDOUT_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_QUAD_S  7
+/** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
  *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_c_fread_qio.
  */
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S)
-#define SPI_MEM_FADDR_QUAD_V  0x00000001U
-#define SPI_MEM_FADDR_QUAD_S  8
+#define SPI1_MEM_C_FADDR_QUAD    (BIT(8))
+#define SPI1_MEM_C_FADDR_QUAD_M  (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S)
+#define SPI1_MEM_C_FADDR_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FADDR_QUAD_S  8
 
-/** SPI_MEM_W0_REG register
+/** SPI1_MEM_C_W0_REG register
  *  SPI1 memory data buffer0
  */
-#define SPI_MEM_W0_REG (DR_REG_SPI1_BASE + 0x58)
-/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W0_REG (DR_REG_FLASH_SPI1_BASE + 0x58)
+/** SPI1_MEM_C_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF0    0xFFFFFFFFU
-#define SPI_MEM_BUF0_M  (SPI_MEM_BUF0_V << SPI_MEM_BUF0_S)
-#define SPI_MEM_BUF0_V  0xFFFFFFFFU
-#define SPI_MEM_BUF0_S  0
+#define SPI1_MEM_C_BUF0    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF0_M  (SPI1_MEM_C_BUF0_V << SPI1_MEM_C_BUF0_S)
+#define SPI1_MEM_C_BUF0_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF0_S  0
 
-/** SPI_MEM_W1_REG register
+/** SPI1_MEM_C_W1_REG register
  *  SPI1 memory data buffer1
  */
-#define SPI_MEM_W1_REG (DR_REG_SPI1_BASE + 0x5c)
-/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W1_REG (DR_REG_FLASH_SPI1_BASE + 0x5c)
+/** SPI1_MEM_C_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF1    0xFFFFFFFFU
-#define SPI_MEM_BUF1_M  (SPI_MEM_BUF1_V << SPI_MEM_BUF1_S)
-#define SPI_MEM_BUF1_V  0xFFFFFFFFU
-#define SPI_MEM_BUF1_S  0
+#define SPI1_MEM_C_BUF1    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF1_M  (SPI1_MEM_C_BUF1_V << SPI1_MEM_C_BUF1_S)
+#define SPI1_MEM_C_BUF1_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF1_S  0
 
-/** SPI_MEM_W2_REG register
+/** SPI1_MEM_C_W2_REG register
  *  SPI1 memory data buffer2
  */
-#define SPI_MEM_W2_REG (DR_REG_SPI1_BASE + 0x60)
-/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W2_REG (DR_REG_FLASH_SPI1_BASE + 0x60)
+/** SPI1_MEM_C_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF2    0xFFFFFFFFU
-#define SPI_MEM_BUF2_M  (SPI_MEM_BUF2_V << SPI_MEM_BUF2_S)
-#define SPI_MEM_BUF2_V  0xFFFFFFFFU
-#define SPI_MEM_BUF2_S  0
+#define SPI1_MEM_C_BUF2    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF2_M  (SPI1_MEM_C_BUF2_V << SPI1_MEM_C_BUF2_S)
+#define SPI1_MEM_C_BUF2_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF2_S  0
 
-/** SPI_MEM_W3_REG register
+/** SPI1_MEM_C_W3_REG register
  *  SPI1 memory data buffer3
  */
-#define SPI_MEM_W3_REG (DR_REG_SPI1_BASE + 0x64)
-/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W3_REG (DR_REG_FLASH_SPI1_BASE + 0x64)
+/** SPI1_MEM_C_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF3    0xFFFFFFFFU
-#define SPI_MEM_BUF3_M  (SPI_MEM_BUF3_V << SPI_MEM_BUF3_S)
-#define SPI_MEM_BUF3_V  0xFFFFFFFFU
-#define SPI_MEM_BUF3_S  0
+#define SPI1_MEM_C_BUF3    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF3_M  (SPI1_MEM_C_BUF3_V << SPI1_MEM_C_BUF3_S)
+#define SPI1_MEM_C_BUF3_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF3_S  0
 
-/** SPI_MEM_W4_REG register
+/** SPI1_MEM_C_W4_REG register
  *  SPI1 memory data buffer4
  */
-#define SPI_MEM_W4_REG (DR_REG_SPI1_BASE + 0x68)
-/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W4_REG (DR_REG_FLASH_SPI1_BASE + 0x68)
+/** SPI1_MEM_C_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF4    0xFFFFFFFFU
-#define SPI_MEM_BUF4_M  (SPI_MEM_BUF4_V << SPI_MEM_BUF4_S)
-#define SPI_MEM_BUF4_V  0xFFFFFFFFU
-#define SPI_MEM_BUF4_S  0
+#define SPI1_MEM_C_BUF4    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF4_M  (SPI1_MEM_C_BUF4_V << SPI1_MEM_C_BUF4_S)
+#define SPI1_MEM_C_BUF4_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF4_S  0
 
-/** SPI_MEM_W5_REG register
+/** SPI1_MEM_C_W5_REG register
  *  SPI1 memory data buffer5
  */
-#define SPI_MEM_W5_REG (DR_REG_SPI1_BASE + 0x6c)
-/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W5_REG (DR_REG_FLASH_SPI1_BASE + 0x6c)
+/** SPI1_MEM_C_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF5    0xFFFFFFFFU
-#define SPI_MEM_BUF5_M  (SPI_MEM_BUF5_V << SPI_MEM_BUF5_S)
-#define SPI_MEM_BUF5_V  0xFFFFFFFFU
-#define SPI_MEM_BUF5_S  0
+#define SPI1_MEM_C_BUF5    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF5_M  (SPI1_MEM_C_BUF5_V << SPI1_MEM_C_BUF5_S)
+#define SPI1_MEM_C_BUF5_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF5_S  0
 
-/** SPI_MEM_W6_REG register
+/** SPI1_MEM_C_W6_REG register
  *  SPI1 memory data buffer6
  */
-#define SPI_MEM_W6_REG (DR_REG_SPI1_BASE + 0x70)
-/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W6_REG (DR_REG_FLASH_SPI1_BASE + 0x70)
+/** SPI1_MEM_C_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF6    0xFFFFFFFFU
-#define SPI_MEM_BUF6_M  (SPI_MEM_BUF6_V << SPI_MEM_BUF6_S)
-#define SPI_MEM_BUF6_V  0xFFFFFFFFU
-#define SPI_MEM_BUF6_S  0
+#define SPI1_MEM_C_BUF6    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF6_M  (SPI1_MEM_C_BUF6_V << SPI1_MEM_C_BUF6_S)
+#define SPI1_MEM_C_BUF6_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF6_S  0
 
-/** SPI_MEM_W7_REG register
+/** SPI1_MEM_C_W7_REG register
  *  SPI1 memory data buffer7
  */
-#define SPI_MEM_W7_REG (DR_REG_SPI1_BASE + 0x74)
-/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W7_REG (DR_REG_FLASH_SPI1_BASE + 0x74)
+/** SPI1_MEM_C_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF7    0xFFFFFFFFU
-#define SPI_MEM_BUF7_M  (SPI_MEM_BUF7_V << SPI_MEM_BUF7_S)
-#define SPI_MEM_BUF7_V  0xFFFFFFFFU
-#define SPI_MEM_BUF7_S  0
+#define SPI1_MEM_C_BUF7    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF7_M  (SPI1_MEM_C_BUF7_V << SPI1_MEM_C_BUF7_S)
+#define SPI1_MEM_C_BUF7_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF7_S  0
 
-/** SPI_MEM_W8_REG register
+/** SPI1_MEM_C_W8_REG register
  *  SPI1 memory data buffer8
  */
-#define SPI_MEM_W8_REG (DR_REG_SPI1_BASE + 0x78)
-/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W8_REG (DR_REG_FLASH_SPI1_BASE + 0x78)
+/** SPI1_MEM_C_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF8    0xFFFFFFFFU
-#define SPI_MEM_BUF8_M  (SPI_MEM_BUF8_V << SPI_MEM_BUF8_S)
-#define SPI_MEM_BUF8_V  0xFFFFFFFFU
-#define SPI_MEM_BUF8_S  0
+#define SPI1_MEM_C_BUF8    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF8_M  (SPI1_MEM_C_BUF8_V << SPI1_MEM_C_BUF8_S)
+#define SPI1_MEM_C_BUF8_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF8_S  0
 
-/** SPI_MEM_W9_REG register
+/** SPI1_MEM_C_W9_REG register
  *  SPI1 memory data buffer9
  */
-#define SPI_MEM_W9_REG (DR_REG_SPI1_BASE + 0x7c)
-/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W9_REG (DR_REG_FLASH_SPI1_BASE + 0x7c)
+/** SPI1_MEM_C_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF9    0xFFFFFFFFU
-#define SPI_MEM_BUF9_M  (SPI_MEM_BUF9_V << SPI_MEM_BUF9_S)
-#define SPI_MEM_BUF9_V  0xFFFFFFFFU
-#define SPI_MEM_BUF9_S  0
+#define SPI1_MEM_C_BUF9    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF9_M  (SPI1_MEM_C_BUF9_V << SPI1_MEM_C_BUF9_S)
+#define SPI1_MEM_C_BUF9_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF9_S  0
 
-/** SPI_MEM_W10_REG register
+/** SPI1_MEM_C_W10_REG register
  *  SPI1 memory data buffer10
  */
-#define SPI_MEM_W10_REG (DR_REG_SPI1_BASE + 0x80)
-/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W10_REG (DR_REG_FLASH_SPI1_BASE + 0x80)
+/** SPI1_MEM_C_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF10    0xFFFFFFFFU
-#define SPI_MEM_BUF10_M  (SPI_MEM_BUF10_V << SPI_MEM_BUF10_S)
-#define SPI_MEM_BUF10_V  0xFFFFFFFFU
-#define SPI_MEM_BUF10_S  0
+#define SPI1_MEM_C_BUF10    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF10_M  (SPI1_MEM_C_BUF10_V << SPI1_MEM_C_BUF10_S)
+#define SPI1_MEM_C_BUF10_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF10_S  0
 
-/** SPI_MEM_W11_REG register
+/** SPI1_MEM_C_W11_REG register
  *  SPI1 memory data buffer11
  */
-#define SPI_MEM_W11_REG (DR_REG_SPI1_BASE + 0x84)
-/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W11_REG (DR_REG_FLASH_SPI1_BASE + 0x84)
+/** SPI1_MEM_C_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF11    0xFFFFFFFFU
-#define SPI_MEM_BUF11_M  (SPI_MEM_BUF11_V << SPI_MEM_BUF11_S)
-#define SPI_MEM_BUF11_V  0xFFFFFFFFU
-#define SPI_MEM_BUF11_S  0
+#define SPI1_MEM_C_BUF11    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF11_M  (SPI1_MEM_C_BUF11_V << SPI1_MEM_C_BUF11_S)
+#define SPI1_MEM_C_BUF11_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF11_S  0
 
-/** SPI_MEM_W12_REG register
+/** SPI1_MEM_C_W12_REG register
  *  SPI1 memory data buffer12
  */
-#define SPI_MEM_W12_REG (DR_REG_SPI1_BASE + 0x88)
-/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W12_REG (DR_REG_FLASH_SPI1_BASE + 0x88)
+/** SPI1_MEM_C_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF12    0xFFFFFFFFU
-#define SPI_MEM_BUF12_M  (SPI_MEM_BUF12_V << SPI_MEM_BUF12_S)
-#define SPI_MEM_BUF12_V  0xFFFFFFFFU
-#define SPI_MEM_BUF12_S  0
+#define SPI1_MEM_C_BUF12    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF12_M  (SPI1_MEM_C_BUF12_V << SPI1_MEM_C_BUF12_S)
+#define SPI1_MEM_C_BUF12_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF12_S  0
 
-/** SPI_MEM_W13_REG register
+/** SPI1_MEM_C_W13_REG register
  *  SPI1 memory data buffer13
  */
-#define SPI_MEM_W13_REG (DR_REG_SPI1_BASE + 0x8c)
-/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W13_REG (DR_REG_FLASH_SPI1_BASE + 0x8c)
+/** SPI1_MEM_C_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF13    0xFFFFFFFFU
-#define SPI_MEM_BUF13_M  (SPI_MEM_BUF13_V << SPI_MEM_BUF13_S)
-#define SPI_MEM_BUF13_V  0xFFFFFFFFU
-#define SPI_MEM_BUF13_S  0
+#define SPI1_MEM_C_BUF13    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF13_M  (SPI1_MEM_C_BUF13_V << SPI1_MEM_C_BUF13_S)
+#define SPI1_MEM_C_BUF13_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF13_S  0
 
-/** SPI_MEM_W14_REG register
+/** SPI1_MEM_C_W14_REG register
  *  SPI1 memory data buffer14
  */
-#define SPI_MEM_W14_REG (DR_REG_SPI1_BASE + 0x90)
-/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W14_REG (DR_REG_FLASH_SPI1_BASE + 0x90)
+/** SPI1_MEM_C_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF14    0xFFFFFFFFU
-#define SPI_MEM_BUF14_M  (SPI_MEM_BUF14_V << SPI_MEM_BUF14_S)
-#define SPI_MEM_BUF14_V  0xFFFFFFFFU
-#define SPI_MEM_BUF14_S  0
+#define SPI1_MEM_C_BUF14    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF14_M  (SPI1_MEM_C_BUF14_V << SPI1_MEM_C_BUF14_S)
+#define SPI1_MEM_C_BUF14_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF14_S  0
 
-/** SPI_MEM_W15_REG register
+/** SPI1_MEM_C_W15_REG register
  *  SPI1 memory data buffer15
  */
-#define SPI_MEM_W15_REG (DR_REG_SPI1_BASE + 0x94)
-/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W15_REG (DR_REG_FLASH_SPI1_BASE + 0x94)
+/** SPI1_MEM_C_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF15    0xFFFFFFFFU
-#define SPI_MEM_BUF15_M  (SPI_MEM_BUF15_V << SPI_MEM_BUF15_S)
-#define SPI_MEM_BUF15_V  0xFFFFFFFFU
-#define SPI_MEM_BUF15_S  0
+#define SPI1_MEM_C_BUF15    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF15_M  (SPI1_MEM_C_BUF15_V << SPI1_MEM_C_BUF15_S)
+#define SPI1_MEM_C_BUF15_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF15_S  0
 
-/** SPI_MEM_FLASH_WAITI_CTRL_REG register
+/** SPI1_MEM_C_FLASH_WAITI_CTRL_REG register
  *  SPI1 wait idle control register
  */
-#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI1_BASE + 0x98)
-/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_C_FLASH_WAITI_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x98)
+/** SPI1_MEM_C_WAITI_EN : R/W; bitpos: [0]; default: 1;
  *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
  *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
  *  Suspend/Resume are not supported.
  */
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (SPI_MEM_WAITI_EN_V << SPI_MEM_WAITI_EN_S)
-#define SPI_MEM_WAITI_EN_V  0x00000001U
-#define SPI_MEM_WAITI_EN_S  0
-/** SPI_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_WAITI_EN    (BIT(0))
+#define SPI1_MEM_C_WAITI_EN_M  (SPI1_MEM_C_WAITI_EN_V << SPI1_MEM_C_WAITI_EN_S)
+#define SPI1_MEM_C_WAITI_EN_V  0x00000001U
+#define SPI1_MEM_C_WAITI_EN_S  0
+/** SPI1_MEM_C_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
  *  The dummy phase enable when wait flash idle (RDSR)
  */
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (SPI_MEM_WAITI_DUMMY_V << SPI_MEM_WAITI_DUMMY_S)
-#define SPI_MEM_WAITI_DUMMY_V  0x00000001U
-#define SPI_MEM_WAITI_DUMMY_S  1
-/** SPI_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
+#define SPI1_MEM_C_WAITI_DUMMY    (BIT(1))
+#define SPI1_MEM_C_WAITI_DUMMY_M  (SPI1_MEM_C_WAITI_DUMMY_V << SPI1_MEM_C_WAITI_DUMMY_S)
+#define SPI1_MEM_C_WAITI_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_WAITI_DUMMY_S  1
+/** SPI1_MEM_C_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
  *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
  *  address in RDSR or read SUS command transfer.
  */
-#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_M  (SPI_MEM_WAITI_ADDR_EN_V << SPI_MEM_WAITI_ADDR_EN_S)
-#define SPI_MEM_WAITI_ADDR_EN_V  0x00000001U
-#define SPI_MEM_WAITI_ADDR_EN_S  2
-/** SPI_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
- *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
- *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
- *  SPI_MEM_WAITI_ADDR_EN is cleared.
+#define SPI1_MEM_C_WAITI_ADDR_EN    (BIT(2))
+#define SPI1_MEM_C_WAITI_ADDR_EN_M  (SPI1_MEM_C_WAITI_ADDR_EN_V << SPI1_MEM_C_WAITI_ADDR_EN_S)
+#define SPI1_MEM_C_WAITI_ADDR_EN_V  0x00000001U
+#define SPI1_MEM_C_WAITI_ADDR_EN_S  2
+/** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
+ *  When SPI1_MEM_C_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+ *  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+ *  SPI1_MEM_C_WAITI_ADDR_EN is cleared.
  */
-#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  (SPI_MEM_WAITI_ADDR_CYCLELEN_V << SPI_MEM_WAITI_ADDR_CYCLELEN_S)
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
-/** SPI_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN    0x00000003U
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S)
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V  0x00000003U
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S  3
+/** SPI1_MEM_C_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
  *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
  */
-#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_M  (SPI_MEM_WAITI_CMD_2B_V << SPI_MEM_WAITI_CMD_2B_S)
-#define SPI_MEM_WAITI_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAITI_CMD_2B_S  9
-/** SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
+#define SPI1_MEM_C_WAITI_CMD_2B    (BIT(9))
+#define SPI1_MEM_C_WAITI_CMD_2B_M  (SPI1_MEM_C_WAITI_CMD_2B_V << SPI1_MEM_C_WAITI_CMD_2B_S)
+#define SPI1_MEM_C_WAITI_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_WAITI_CMD_2B_S  9
+/** SPI1_MEM_C_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
  *  The dummy cycle length when wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  (SPI_MEM_WAITI_DUMMY_CYCLELEN_V << SPI_MEM_WAITI_DUMMY_CYCLELEN_S)
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/** SPI_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_M  (SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S  10
+/** SPI1_MEM_C_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
  *  The command value to wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_CMD    0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_M  (SPI_MEM_WAITI_CMD_V << SPI_MEM_WAITI_CMD_S)
-#define SPI_MEM_WAITI_CMD_V  0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_S  16
+#define SPI1_MEM_C_WAITI_CMD    0x0000FFFFU
+#define SPI1_MEM_C_WAITI_CMD_M  (SPI1_MEM_C_WAITI_CMD_V << SPI1_MEM_C_WAITI_CMD_S)
+#define SPI1_MEM_C_WAITI_CMD_V  0x0000FFFFU
+#define SPI1_MEM_C_WAITI_CMD_S  16
 
-/** SPI_MEM_FLASH_SUS_CTRL_REG register
+/** SPI1_MEM_C_FLASH_SUS_CTRL_REG register
  *  SPI1 flash suspend control register
  */
-#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI1_BASE + 0x9c)
-/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_FLASH_SUS_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x9c)
+/** SPI1_MEM_C_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
  *  program erase resume bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (SPI_MEM_FLASH_PER_V << SPI_MEM_FLASH_PER_S)
-#define SPI_MEM_FLASH_PER_V  0x00000001U
-#define SPI_MEM_FLASH_PER_S  0
-/** SPI_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_FLASH_PER    (BIT(0))
+#define SPI1_MEM_C_FLASH_PER_M  (SPI1_MEM_C_FLASH_PER_V << SPI1_MEM_C_FLASH_PER_S)
+#define SPI1_MEM_C_FLASH_PER_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_S  0
+/** SPI1_MEM_C_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
  *  program erase suspend bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (SPI_MEM_FLASH_PES_V << SPI_MEM_FLASH_PES_S)
-#define SPI_MEM_FLASH_PES_V  0x00000001U
-#define SPI_MEM_FLASH_PES_S  1
-/** SPI_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_C_FLASH_PES    (BIT(1))
+#define SPI1_MEM_C_FLASH_PES_M  (SPI1_MEM_C_FLASH_PES_V << SPI1_MEM_C_FLASH_PES_S)
+#define SPI1_MEM_C_FLASH_PES_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_S  1
+/** SPI1_MEM_C_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase resume command is sent. 0: SPI1 does not wait after program erase
  *  resume command is sent.
  */
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (SPI_MEM_FLASH_PER_WAIT_EN_V << SPI_MEM_FLASH_PER_WAIT_EN_S)
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/** SPI_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_M  (SPI1_MEM_C_FLASH_PER_WAIT_EN_V << SPI1_MEM_C_FLASH_PER_WAIT_EN_S)
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_S  2
+/** SPI1_MEM_C_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
  *  suspend command is sent.
  */
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (SPI_MEM_FLASH_PES_WAIT_EN_V << SPI_MEM_FLASH_PES_WAIT_EN_S)
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/** SPI_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_M  (SPI1_MEM_C_FLASH_PES_WAIT_EN_V << SPI1_MEM_C_FLASH_PES_WAIT_EN_S)
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_S  3
+/** SPI1_MEM_C_PES_PER_EN : R/W; bitpos: [4]; default: 0;
  *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
  *  application should send PER after PES is done.
  */
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (SPI_MEM_PES_PER_EN_V << SPI_MEM_PES_PER_EN_S)
-#define SPI_MEM_PES_PER_EN_V  0x00000001U
-#define SPI_MEM_PES_PER_EN_S  4
-/** SPI_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_C_PES_PER_EN    (BIT(4))
+#define SPI1_MEM_C_PES_PER_EN_M  (SPI1_MEM_C_PES_PER_EN_V << SPI1_MEM_C_PES_PER_EN_S)
+#define SPI1_MEM_C_PES_PER_EN_V  0x00000001U
+#define SPI1_MEM_C_PES_PER_EN_S  4
+/** SPI1_MEM_C_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
  *  Set this bit to enable Auto-suspending function.
  */
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (SPI_MEM_FLASH_PES_EN_V << SPI_MEM_FLASH_PES_EN_S)
-#define SPI_MEM_FLASH_PES_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_EN_S  5
-/** SPI_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
+#define SPI1_MEM_C_FLASH_PES_EN    (BIT(5))
+#define SPI1_MEM_C_FLASH_PES_EN_M  (SPI1_MEM_C_FLASH_PES_EN_V << SPI1_MEM_C_FLASH_PES_EN_S)
+#define SPI1_MEM_C_FLASH_PES_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_EN_S  5
+/** SPI1_MEM_C_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
  *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
  *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
  *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
- *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+ *  status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0].
  */
-#define SPI_MEM_PESR_END_MSK    0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_M  (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S)
-#define SPI_MEM_PESR_END_MSK_V  0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_S  6
-/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_C_PESR_END_MSK    0x0000FFFFU
+#define SPI1_MEM_C_PESR_END_MSK_M  (SPI1_MEM_C_PESR_END_MSK_V << SPI1_MEM_C_PESR_END_MSK_S)
+#define SPI1_MEM_C_PESR_END_MSK_V  0x0000FFFFU
+#define SPI1_MEM_C_PESR_END_MSK_S  6
+/** SPI1_MEM_C_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
  *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
  *  check flash SUS/SUS1/SUS2 status bit
  */
-#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S)
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x00000001U
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_C_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_M  (SPI1_MEM_C_FMEM_RD_SUS_2B_V << SPI1_MEM_C_FMEM_RD_SUS_2B_S)
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_V  0x00000001U
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_S  22
+/** SPI1_MEM_C_PER_END_EN : R/W; bitpos: [23]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
  *  flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (SPI_MEM_PER_END_EN_V << SPI_MEM_PER_END_EN_S)
-#define SPI_MEM_PER_END_EN_V  0x00000001U
-#define SPI_MEM_PER_END_EN_S  23
-/** SPI_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_PER_END_EN    (BIT(23))
+#define SPI1_MEM_C_PER_END_EN_M  (SPI1_MEM_C_PER_END_EN_V << SPI1_MEM_C_PER_END_EN_S)
+#define SPI1_MEM_C_PER_END_EN_V  0x00000001U
+#define SPI1_MEM_C_PER_END_EN_S  23
+/** SPI1_MEM_C_PES_END_EN : R/W; bitpos: [24]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
  *  of flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (SPI_MEM_PES_END_EN_V << SPI_MEM_PES_END_EN_S)
-#define SPI_MEM_PES_END_EN_V  0x00000001U
-#define SPI_MEM_PES_END_EN_S  24
-/** SPI_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
- *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+#define SPI1_MEM_C_PES_END_EN    (BIT(24))
+#define SPI1_MEM_C_PES_END_EN_M  (SPI1_MEM_C_PES_END_EN_V << SPI1_MEM_C_PES_END_EN_S)
+#define SPI1_MEM_C_PES_END_EN_V  0x00000001U
+#define SPI1_MEM_C_PES_END_EN_S  24
+/** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
+ *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it
  *  will be treated as check pass.
  */
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  (SPI_MEM_SUS_TIMEOUT_CNT_V << SPI_MEM_SUS_TIMEOUT_CNT_S)
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT    0x0000007FU
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_M  (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S)
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_V  0x0000007FU
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_S  25
 
-/** SPI_MEM_FLASH_SUS_CMD_REG register
+/** SPI1_MEM_C_FLASH_SUS_CMD_REG register
  *  SPI1 flash suspend command register
  */
-#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI1_BASE + 0xa0)
-/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
+#define SPI1_MEM_C_FLASH_SUS_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0xa0)
+/** SPI1_MEM_C_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
  *  Program/Erase suspend command.
  */
-#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_M  (SPI_MEM_FLASH_PES_COMMAND_V << SPI_MEM_FLASH_PES_COMMAND_S)
-#define SPI_MEM_FLASH_PES_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_S  0
-/** SPI_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_C_FLASH_PES_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PES_COMMAND_M  (SPI1_MEM_C_FLASH_PES_COMMAND_V << SPI1_MEM_C_FLASH_PES_COMMAND_S)
+#define SPI1_MEM_C_FLASH_PES_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PES_COMMAND_S  0
+/** SPI1_MEM_C_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
  *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
  *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
  */
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_M  (SPI_MEM_WAIT_PESR_COMMAND_V << SPI_MEM_WAIT_PESR_COMMAND_S)
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+#define SPI1_MEM_C_WAIT_PESR_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_M  (SPI1_MEM_C_WAIT_PESR_COMMAND_V << SPI1_MEM_C_WAIT_PESR_COMMAND_S)
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_S  16
 
-/** SPI_MEM_SUS_STATUS_REG register
+/** SPI1_MEM_C_SUS_STATUS_REG register
  *  SPI1 flash suspend status register
  */
-#define SPI_MEM_SUS_STATUS_REG (DR_REG_SPI1_BASE + 0xa4)
-/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_SUS_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0xa4)
+/** SPI1_MEM_C_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
  *  The status of flash suspend, only used in SPI1.
  */
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (SPI_MEM_FLASH_SUS_V << SPI_MEM_FLASH_SUS_S)
-#define SPI_MEM_FLASH_SUS_V  0x00000001U
-#define SPI_MEM_FLASH_SUS_S  0
-/** SPI_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
- *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+#define SPI1_MEM_C_FLASH_SUS    (BIT(0))
+#define SPI1_MEM_C_FLASH_SUS_M  (SPI1_MEM_C_FLASH_SUS_V << SPI1_MEM_C_FLASH_SUS_S)
+#define SPI1_MEM_C_FLASH_SUS_V  0x00000001U
+#define SPI1_MEM_C_FLASH_SUS_S  0
+/** SPI1_MEM_C_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
+ *  1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ *  SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
  */
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (SPI_MEM_WAIT_PESR_CMD_2B_V << SPI_MEM_WAIT_PESR_CMD_2B_S)
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/** SPI_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_M  (SPI1_MEM_C_WAIT_PESR_CMD_2B_V << SPI1_MEM_C_WAIT_PESR_CMD_2B_S)
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_S  1
+/** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after HPM command is sent.
  */
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (SPI_MEM_FLASH_HPM_DLY_128_V << SPI_MEM_FLASH_HPM_DLY_128_S)
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/** SPI_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_C_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_M  (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S)
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_S  2
+/** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after RES command is sent.
  */
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (SPI_MEM_FLASH_RES_DLY_128_V << SPI_MEM_FLASH_RES_DLY_128_S)
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/** SPI_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_C_FLASH_RES_DLY_128    (BIT(3))
+#define SPI1_MEM_C_FLASH_RES_DLY_128_M  (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S)
+#define SPI1_MEM_C_FLASH_RES_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RES_DLY_128_S  3
+/** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after DP command is sent.
  */
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (SPI_MEM_FLASH_DP_DLY_128_V << SPI_MEM_FLASH_DP_DLY_128_S)
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/** SPI_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
- *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+#define SPI1_MEM_C_FLASH_DP_DLY_128    (BIT(4))
+#define SPI1_MEM_C_FLASH_DP_DLY_128_M  (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S)
+#define SPI1_MEM_C_FLASH_DP_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_DP_DLY_128_S  4
+/** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
+ *  Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (SPI_MEM_FLASH_PER_DLY_128_V << SPI_MEM_FLASH_PER_DLY_128_S)
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/** SPI_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
- *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+#define SPI1_MEM_C_FLASH_PER_DLY_128    (BIT(5))
+#define SPI1_MEM_C_FLASH_PER_DLY_128_M  (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S)
+#define SPI1_MEM_C_FLASH_PER_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_DLY_128_S  5
+/** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
+ *  Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (SPI_MEM_FLASH_PES_DLY_128_V << SPI_MEM_FLASH_PES_DLY_128_S)
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/** SPI_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_C_FLASH_PES_DLY_128    (BIT(6))
+#define SPI1_MEM_C_FLASH_PES_DLY_128_M  (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S)
+#define SPI1_MEM_C_FLASH_PES_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_DLY_128_S  6
+/** SPI1_MEM_C_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
  *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
  */
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (SPI_MEM_SPI0_LOCK_EN_V << SPI_MEM_SPI0_LOCK_EN_S)
-#define SPI_MEM_SPI0_LOCK_EN_V  0x00000001U
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/** SPI_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_C_SPI0_LOCK_EN    (BIT(7))
+#define SPI1_MEM_C_SPI0_LOCK_EN_M  (SPI1_MEM_C_SPI0_LOCK_EN_V << SPI1_MEM_C_SPI0_LOCK_EN_S)
+#define SPI1_MEM_C_SPI0_LOCK_EN_V  0x00000001U
+#define SPI1_MEM_C_SPI0_LOCK_EN_S  7
+/** SPI1_MEM_C_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
  *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
  *  of Program/Erase Suspend/Resume command is 8.
  */
-#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_M  (SPI_MEM_FLASH_PESR_CMD_2B_V << SPI_MEM_FLASH_PESR_CMD_2B_S)
-#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
-/** SPI_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_M  (SPI1_MEM_C_FLASH_PESR_CMD_2B_V << SPI1_MEM_C_FLASH_PESR_CMD_2B_S)
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_S  15
+/** SPI1_MEM_C_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
  *  Program/Erase resume command.
  */
-#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_M  (SPI_MEM_FLASH_PER_COMMAND_V << SPI_MEM_FLASH_PER_COMMAND_S)
-#define SPI_MEM_FLASH_PER_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_S  16
+#define SPI1_MEM_C_FLASH_PER_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PER_COMMAND_M  (SPI1_MEM_C_FLASH_PER_COMMAND_V << SPI1_MEM_C_FLASH_PER_COMMAND_S)
+#define SPI1_MEM_C_FLASH_PER_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PER_COMMAND_S  16
 
-/** SPI_MEM_INT_ENA_REG register
+/** SPI1_MEM_C_INT_ENA_REG register
  *  SPI1 interrupt enable register
  */
-#define SPI_MEM_INT_ENA_REG (DR_REG_SPI1_BASE + 0xc0)
-/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_MEM_PER_END_INT interrupt.
+#define SPI1_MEM_C_INT_ENA_REG (DR_REG_FLASH_SPI1_BASE + 0xc0)
+/** SPI1_MEM_C_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI1_MEM_C_PER_END_INT interrupt.
  */
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (SPI_MEM_PER_END_INT_ENA_V << SPI_MEM_PER_END_INT_ENA_S)
-#define SPI_MEM_PER_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ENA_S  0
-/** SPI_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_MEM_PES_END_INT interrupt.
+#define SPI1_MEM_C_PER_END_INT_ENA    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_ENA_M  (SPI1_MEM_C_PER_END_INT_ENA_V << SPI1_MEM_C_PER_END_INT_ENA_S)
+#define SPI1_MEM_C_PER_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_ENA_S  0
+/** SPI1_MEM_C_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI1_MEM_C_PES_END_INT interrupt.
  */
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (SPI_MEM_PES_END_INT_ENA_V << SPI_MEM_PES_END_INT_ENA_S)
-#define SPI_MEM_PES_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/** SPI_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+#define SPI1_MEM_C_PES_END_INT_ENA    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_ENA_M  (SPI1_MEM_C_PES_END_INT_ENA_V << SPI1_MEM_C_PES_END_INT_ENA_S)
+#define SPI1_MEM_C_PES_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_ENA_S  1
+/** SPI1_MEM_C_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI1_MEM_C_WPE_END_INT interrupt.
  */
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (SPI_MEM_WPE_END_INT_ENA_V << SPI_MEM_WPE_END_INT_ENA_S)
-#define SPI_MEM_WPE_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI1_MEM_C_WPE_END_INT_ENA    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_ENA_M  (SPI1_MEM_C_WPE_END_INT_ENA_V << SPI1_MEM_C_WPE_END_INT_ENA_S)
+#define SPI1_MEM_C_WPE_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_ENA_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_M  (SPI1_MEM_C_SLV_ST_END_INT_ENA_V << SPI1_MEM_C_SLV_ST_END_INT_ENA_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S)
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
+#define SPI1_MEM_C_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_M  (SPI1_MEM_C_MST_ST_END_INT_ENA_V << SPI1_MEM_C_MST_ST_END_INT_ENA_S)
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
  */
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (SPI_MEM_BROWN_OUT_INT_ENA_V << SPI_MEM_BROWN_OUT_INT_ENA_S)
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_M  (SPI1_MEM_C_BROWN_OUT_INT_ENA_V << SPI1_MEM_C_BROWN_OUT_INT_ENA_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_S  10
 
-/** SPI_MEM_INT_CLR_REG register
+/** SPI1_MEM_C_INT_CLR_REG register
  *  SPI1 interrupt clear register
  */
-#define SPI_MEM_INT_CLR_REG (DR_REG_SPI1_BASE + 0xc4)
-/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_MEM_PER_END_INT interrupt.
+#define SPI1_MEM_C_INT_CLR_REG (DR_REG_FLASH_SPI1_BASE + 0xc4)
+/** SPI1_MEM_C_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI1_MEM_C_PER_END_INT interrupt.
  */
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (SPI_MEM_PER_END_INT_CLR_V << SPI_MEM_PER_END_INT_CLR_S)
-#define SPI_MEM_PER_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PER_END_INT_CLR_S  0
-/** SPI_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_MEM_PES_END_INT interrupt.
+#define SPI1_MEM_C_PER_END_INT_CLR    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_CLR_M  (SPI1_MEM_C_PER_END_INT_CLR_V << SPI1_MEM_C_PER_END_INT_CLR_S)
+#define SPI1_MEM_C_PER_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_CLR_S  0
+/** SPI1_MEM_C_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI1_MEM_C_PES_END_INT interrupt.
  */
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (SPI_MEM_PES_END_INT_CLR_V << SPI_MEM_PES_END_INT_CLR_S)
-#define SPI_MEM_PES_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/** SPI_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+#define SPI1_MEM_C_PES_END_INT_CLR    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_CLR_M  (SPI1_MEM_C_PES_END_INT_CLR_V << SPI1_MEM_C_PES_END_INT_CLR_S)
+#define SPI1_MEM_C_PES_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_CLR_S  1
+/** SPI1_MEM_C_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI1_MEM_C_WPE_END_INT interrupt.
  */
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (SPI_MEM_WPE_END_INT_CLR_V << SPI_MEM_WPE_END_INT_CLR_S)
-#define SPI_MEM_WPE_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI1_MEM_C_WPE_END_INT_CLR    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_CLR_M  (SPI1_MEM_C_WPE_END_INT_CLR_V << SPI1_MEM_C_WPE_END_INT_CLR_S)
+#define SPI1_MEM_C_WPE_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_CLR_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_M  (SPI1_MEM_C_SLV_ST_END_INT_CLR_V << SPI1_MEM_C_SLV_ST_END_INT_CLR_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S)
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+#define SPI1_MEM_C_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_M  (SPI1_MEM_C_MST_ST_END_INT_CLR_V << SPI1_MEM_C_MST_ST_END_INT_CLR_S)
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
  */
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (SPI_MEM_BROWN_OUT_INT_CLR_V << SPI_MEM_BROWN_OUT_INT_CLR_S)
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_M  (SPI1_MEM_C_BROWN_OUT_INT_CLR_V << SPI1_MEM_C_BROWN_OUT_INT_CLR_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_S  10
 
-/** SPI_MEM_INT_RAW_REG register
+/** SPI1_MEM_C_INT_RAW_REG register
  *  SPI1 interrupt raw register
  */
-#define SPI_MEM_INT_RAW_REG (DR_REG_SPI1_BASE + 0xc8)
-/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+#define SPI1_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI1_BASE + 0xc8)
+/** SPI1_MEM_C_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume
  *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
  */
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (SPI_MEM_PER_END_INT_RAW_V << SPI_MEM_PER_END_INT_RAW_S)
-#define SPI_MEM_PER_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PER_END_INT_RAW_S  0
-/** SPI_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+#define SPI1_MEM_C_PER_END_INT_RAW    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_RAW_M  (SPI1_MEM_C_PER_END_INT_RAW_V << SPI1_MEM_C_PER_END_INT_RAW_S)
+#define SPI1_MEM_C_PER_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_RAW_S  0
+/** SPI1_MEM_C_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend
  *  command (0x75) is sent and flash is suspended successfully. 0: Others.
  */
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (SPI_MEM_PES_END_INT_RAW_V << SPI_MEM_PES_END_INT_RAW_S)
-#define SPI_MEM_PES_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/** SPI_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+#define SPI1_MEM_C_PES_END_INT_RAW    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_RAW_M  (SPI1_MEM_C_PES_END_INT_RAW_V << SPI1_MEM_C_PES_END_INT_RAW_S)
+#define SPI1_MEM_C_PES_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_RAW_S  1
+/** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
  *  is sent and flash is already idle. 0: Others.
  */
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (SPI_MEM_WPE_END_INT_RAW_V << SPI_MEM_WPE_END_INT_RAW_S)
-#define SPI_MEM_WPE_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+#define SPI1_MEM_C_WPE_END_INT_RAW    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_RAW_M  (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S)
+#define SPI1_MEM_C_WPE_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_RAW_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
  *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
  *  Others
  */
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_M  (SPI1_MEM_C_SLV_ST_END_INT_RAW_V << SPI1_MEM_C_SLV_ST_END_INT_RAW_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
  *  changed from non idle state to idle state. 0: Others.
  */
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S)
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+#define SPI1_MEM_C_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_M  (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S)
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
  *  chip is loosing power and RTC module sends out brown out close flash request to
  *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  *  and MSPI returns to idle state. 0: Others.
  */
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (SPI_MEM_BROWN_OUT_INT_RAW_V << SPI_MEM_BROWN_OUT_INT_RAW_S)
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_M  (SPI1_MEM_C_BROWN_OUT_INT_RAW_V << SPI1_MEM_C_BROWN_OUT_INT_RAW_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_S  10
 
-/** SPI_MEM_INT_ST_REG register
+/** SPI1_MEM_C_INT_ST_REG register
  *  SPI1 interrupt status register
  */
-#define SPI_MEM_INT_ST_REG (DR_REG_SPI1_BASE + 0xcc)
-/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_MEM_PER_END_INT interrupt.
+#define SPI1_MEM_C_INT_ST_REG (DR_REG_FLASH_SPI1_BASE + 0xcc)
+/** SPI1_MEM_C_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI1_MEM_C_PER_END_INT interrupt.
  */
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (SPI_MEM_PER_END_INT_ST_V << SPI_MEM_PER_END_INT_ST_S)
-#define SPI_MEM_PER_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ST_S  0
-/** SPI_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_MEM_PES_END_INT interrupt.
+#define SPI1_MEM_C_PER_END_INT_ST    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_ST_M  (SPI1_MEM_C_PER_END_INT_ST_V << SPI1_MEM_C_PER_END_INT_ST_S)
+#define SPI1_MEM_C_PER_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_ST_S  0
+/** SPI1_MEM_C_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI1_MEM_C_PES_END_INT interrupt.
  */
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (SPI_MEM_PES_END_INT_ST_V << SPI_MEM_PES_END_INT_ST_S)
-#define SPI_MEM_PES_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ST_S  1
-/** SPI_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI_MEM_WPE_END_INT interrupt.
+#define SPI1_MEM_C_PES_END_INT_ST    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_ST_M  (SPI1_MEM_C_PES_END_INT_ST_V << SPI1_MEM_C_PES_END_INT_ST_S)
+#define SPI1_MEM_C_PES_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_ST_S  1
+/** SPI1_MEM_C_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI1_MEM_C_WPE_END_INT interrupt.
  */
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (SPI_MEM_WPE_END_INT_ST_V << SPI_MEM_WPE_END_INT_ST_S)
-#define SPI_MEM_WPE_END_INT_ST_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI1_MEM_C_WPE_END_INT_ST    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_ST_M  (SPI1_MEM_C_WPE_END_INT_ST_V << SPI1_MEM_C_WPE_END_INT_ST_S)
+#define SPI1_MEM_C_WPE_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_ST_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S)
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI1_MEM_C_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_M  (SPI1_MEM_C_SLV_ST_END_INT_ST_V << SPI1_MEM_C_SLV_ST_END_INT_ST_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S)
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/** SPI_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+#define SPI1_MEM_C_MST_ST_END_INT_ST    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_ST_M  (SPI1_MEM_C_MST_ST_END_INT_ST_V << SPI1_MEM_C_MST_ST_END_INT_ST_S)
+#define SPI1_MEM_C_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_ST_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
  */
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (SPI_MEM_BROWN_OUT_INT_ST_V << SPI_MEM_BROWN_OUT_INT_ST_S)
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ST_S  10
+#define SPI1_MEM_C_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_M  (SPI1_MEM_C_BROWN_OUT_INT_ST_V << SPI1_MEM_C_BROWN_OUT_INT_ST_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_S  10
 
-/** SPI_MEM_DDR_REG register
+/** SPI1_MEM_C_DDR_REG register
  *  SPI1 DDR control register
  */
-#define SPI_MEM_DDR_REG (DR_REG_SPI1_BASE + 0xd4)
-/** SPI_MEM_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_DDR_REG (DR_REG_FLASH_SPI1_BASE + 0xd4)
+/** SPI1_MEM_C_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
  *  1: in ddr mode,  0 in sdr mode
  */
-#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_M  (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S)
-#define SPI_MEM_FMEM_DDR_EN_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_EN_S  0
-/** SPI_MEM_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_EN    (BIT(0))
+#define SPI1_MEM_C_FMEM_DDR_EN_M  (SPI1_MEM_C_FMEM_DDR_EN_V << SPI1_MEM_C_FMEM_DDR_EN_S)
+#define SPI1_MEM_C_FMEM_DDR_EN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_EN_S  0
+/** SPI1_MEM_C_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi ddr mode.
  */
-#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_M  (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S)
-#define SPI_MEM_FMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_MEM_FMEM_VAR_DUMMY_S  1
-/** SPI_MEM_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
+#define SPI1_MEM_C_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_M  (SPI1_MEM_C_FMEM_VAR_DUMMY_V << SPI1_MEM_C_FMEM_VAR_DUMMY_S)
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_S  1
+/** SPI1_MEM_C_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
-/** SPI_MEM_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_M  (SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S)
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S  2
+/** SPI1_MEM_C_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
-/** SPI_MEM_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_M  (SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S)
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S  3
+/** SPI1_MEM_C_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S)
-#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
-/** SPI_MEM_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_M  (SPI1_MEM_C_FMEM_DDR_CMD_DIS_V << SPI1_MEM_C_FMEM_DDR_CMD_DIS_S)
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_S  4
+/** SPI1_MEM_C_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the panda device.
  */
-#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_M  (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S)
-#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
-/** SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_M  (SPI1_MEM_C_FMEM_OUTMINBYTELEN_V << SPI1_MEM_C_FMEM_OUTMINBYTELEN_S)
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_S  5
+/** SPI1_MEM_C_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S)
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
-/** SPI_MEM_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_M  (SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S)
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S)
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
-/** SPI_MEM_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_M  (SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S)
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S  21
+/** SPI1_MEM_C_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S)
-#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
-/** SPI_MEM_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_M  (SPI1_MEM_C_FMEM_CLK_DIFF_EN_V << SPI1_MEM_C_FMEM_CLK_DIFF_EN_S)
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_S  24
+/** SPI1_MEM_C_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_M  (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S)
-#define SPI_MEM_FMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_MEM_FMEM_DQS_CA_IN_S  26
-/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
+#define SPI1_MEM_C_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_M  (SPI1_MEM_C_FMEM_DQS_CA_IN_V << SPI1_MEM_C_FMEM_DQS_CA_IN_S)
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_S  26
+/** SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_MEM_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_M  (SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI1_MEM_C_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to flash. .
  */
-#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S)
-#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
-/** SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_M  (SPI1_MEM_C_FMEM_CLK_DIFF_INV_V << SPI1_MEM_C_FMEM_CLK_DIFF_INV_S)
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_S  28
+/** SPI1_MEM_C_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
  */
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S)
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
-/** SPI_MEM_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_M  (SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S)
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI1_MEM_C_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_M  (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S)
-#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_M  (SPI1_MEM_C_FMEM_HYPERBUS_CA_V << SPI1_MEM_C_FMEM_HYPERBUS_CA_S)
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_S  30
 
-/** SPI_MEM_TIMING_CALI_REG register
+/** SPI1_MEM_C_TIMING_CALI_REG register
  *  SPI1 timing control register
  */
-#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI1_BASE + 0x180)
-/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_TIMING_CALI_REG (DR_REG_FLASH_SPI1_BASE + 0x180)
+/** SPI1_MEM_C_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  The bit is used to enable timing auto-calibration for all reading operations.
  */
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S)
-#define SPI_MEM_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_S  1
-/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+#define SPI1_MEM_C_TIMING_CALI    (BIT(1))
+#define SPI1_MEM_C_TIMING_CALI_M  (SPI1_MEM_C_TIMING_CALI_V << SPI1_MEM_C_TIMING_CALI_S)
+#define SPI1_MEM_C_TIMING_CALI_V  0x00000001U
+#define SPI1_MEM_C_TIMING_CALI_S  1
+/** SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
  *  add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_M  (SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S  2
 
-/** SPI_MEM_CLOCK_GATE_REG register
+/** SPI1_MEM_C_CLOCK_GATE_REG register
  *  SPI1 clk_gate register
  */
-#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI1_BASE + 0x200)
-/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI1_BASE + 0x200)
+/** SPI1_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Register clock gate enable signal. 1: Enable. 0: Disable.
  */
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (SPI_MEM_CLK_EN_V << SPI_MEM_CLK_EN_S)
-#define SPI_MEM_CLK_EN_V  0x00000001U
-#define SPI_MEM_CLK_EN_S  0
+#define SPI1_MEM_C_CLK_EN    (BIT(0))
+#define SPI1_MEM_C_CLK_EN_M  (SPI1_MEM_C_CLK_EN_V << SPI1_MEM_C_CLK_EN_S)
+#define SPI1_MEM_C_CLK_EN_V  0x00000001U
+#define SPI1_MEM_C_CLK_EN_S  0
 
-/** SPI_MEM_DATE_REG register
+/** SPI1_MEM_C_DATE_REG register
  *  Version control register
  */
-#define SPI_MEM_DATE_REG (DR_REG_SPI1_BASE + 0x3fc)
-/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128;
+#define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc)
+/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 35660128;
  *  Version control register
  */
-#define SPI_MEM_DATE    0x0FFFFFFFU
-#define SPI_MEM_DATE_M  (SPI_MEM_DATE_V << SPI_MEM_DATE_S)
-#define SPI_MEM_DATE_V  0x0FFFFFFFU
-#define SPI_MEM_DATE_S  0
+#define SPI1_MEM_C_DATE    0x0FFFFFFFU
+#define SPI1_MEM_C_DATE_M  (SPI1_MEM_C_DATE_V << SPI1_MEM_C_DATE_S)
+#define SPI1_MEM_C_DATE_V  0x0FFFFFFFU
+#define SPI1_MEM_C_DATE_S  0
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
index 96e193351d..3d00246003 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
+++ b/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
@@ -29,7 +29,7 @@ typedef union {
         uint32_t reserved_8:9;
         /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
          *  In user mode, it is set to indicate that program/erase operation will be triggered.
-         *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+         *  The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the
          *  operation done.1: enable 0: disable.
          */
         uint32_t flash_pe:1;
@@ -107,7 +107,7 @@ typedef union {
         uint32_t flash_read:1;
     };
     uint32_t val;
-} spi_mem_cmd_reg_t;
+} spi1_mem_c_cmd_reg_t;
 
 /** Type of addr register
  *  SPI1 address register
@@ -121,7 +121,7 @@ typedef union {
         uint32_t usr_addr_value:32;
     };
     uint32_t val;
-} spi_mem_addr_reg_t;
+} spi1_mem_c_addr_reg_t;
 
 /** Type of user register
  *  SPI1 user register.
@@ -130,7 +130,7 @@ typedef union {
     struct {
         uint32_t reserved_0:9;
         /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+         *  the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode.
          */
         uint32_t ck_out_edge:1;
         uint32_t reserved_10:2;
@@ -152,12 +152,12 @@ typedef union {
         uint32_t fwrite_qio:1;
         uint32_t reserved_16:8;
         /** usr_miso_highpart : HRO; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_miso_highpart:1;
         /** usr_mosi_highpart : HRO; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_mosi_highpart:1;
@@ -187,7 +187,7 @@ typedef union {
         uint32_t usr_command:1;
     };
     uint32_t val;
-} spi_mem_user_reg_t;
+} spi1_mem_c_user_reg_t;
 
 /** Type of user1 register
  *  SPI1 user1 register.
@@ -195,7 +195,7 @@ typedef union {
 typedef union {
     struct {
         /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+         *  The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
         uint32_t usr_dummy_cyclelen:6;
@@ -206,7 +206,7 @@ typedef union {
         uint32_t usr_addr_bitlen:6;
     };
     uint32_t val;
-} spi_mem_user1_reg_t;
+} spi1_mem_c_user1_reg_t;
 
 /** Type of user2 register
  *  SPI1 user2 register.
@@ -224,7 +224,7 @@ typedef union {
         uint32_t usr_command_bitlen:4;
     };
     uint32_t val;
-} spi_mem_user2_reg_t;
+} spi1_mem_c_user2_reg_t;
 
 
 /** Group: Control and configuration registers */
@@ -276,8 +276,8 @@ typedef union {
         uint32_t tx_crc_en:1;
         uint32_t reserved_12:1;
         /** fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
-         *  and spi_mem_fread_dout. 1: enable 0: disable.
+         *  This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout
+         *  and spi1_mem_c_fread_dout. 1: enable 0: disable.
          */
         uint32_t fastrd_mode:1;
         /** fread_dual : R/W; bitpos: [14]; default: 0;
@@ -285,8 +285,8 @@ typedef union {
          */
         uint32_t fread_dual:1;
         /** resandres : R/W; bitpos: [15]; default: 1;
-         *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-         *  spi_mem_flash_res bit. 1: enable 0: disable.
+         *  The Device ID is read out to SPI1_MEM_C_RD_STATUS register,  this bit combine with
+         *  spi1_mem_c_flash_res bit. 1: enable 0: disable.
          */
         uint32_t resandres:1;
         uint32_t reserved_16:2;
@@ -324,7 +324,7 @@ typedef union {
         uint32_t reserved_25:7;
     };
     uint32_t val;
-} spi_mem_ctrl_reg_t;
+} spi1_mem_c_ctrl_reg_t;
 
 /** Type of ctrl1 register
  *  SPI1 control1 register.
@@ -338,14 +338,14 @@ typedef union {
          */
         uint32_t clk_mode:2;
         /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
-         *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+         *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512)
          *  SPI_CLK cycles.
          */
         uint32_t cs_hold_dly_res:10;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_ctrl1_reg_t;
+} spi1_mem_c_ctrl1_reg_t;
 
 /** Type of ctrl2 register
  *  SPI1 control2 register.
@@ -359,7 +359,7 @@ typedef union {
         uint32_t sync_reset:1;
     };
     uint32_t val;
-} spi_mem_ctrl2_reg_t;
+} spi1_mem_c_ctrl2_reg_t;
 
 /** Type of clock register
  *  SPI1 clock division control register.
@@ -367,16 +367,16 @@ typedef union {
 typedef union {
     struct {
         /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
+         *  In the master mode it must be equal to spi1_mem_c_clkcnt_N.
          */
         uint32_t clkcnt_l:8;
         /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+         *  In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1).
          */
         uint32_t clkcnt_h:8;
         /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
+         *  In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is
+         *  system/(spi1_mem_c_clkcnt_N+1)
          */
         uint32_t clkcnt_n:8;
         uint32_t reserved_24:7;
@@ -386,7 +386,7 @@ typedef union {
         uint32_t clk_equ_sysclk:1;
     };
     uint32_t val;
-} spi_mem_clock_reg_t;
+} spi1_mem_c_clock_reg_t;
 
 /** Type of mosi_dlen register
  *  SPI1 send data bit length control register.
@@ -400,7 +400,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_mosi_dlen_reg_t;
+} spi1_mem_c_mosi_dlen_reg_t;
 
 /** Type of miso_dlen register
  *  SPI1 receive data bit length control register.
@@ -414,7 +414,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_miso_dlen_reg_t;
+} spi1_mem_c_miso_dlen_reg_t;
 
 /** Type of rd_status register
  *  SPI1 status register.
@@ -422,17 +422,17 @@ typedef union {
 typedef union {
     struct {
         /** status : R/W/SS; bitpos: [15:0]; default: 0;
-         *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+         *  The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit.
          */
         uint32_t status:16;
         /** wb_mode : R/W; bitpos: [23:16]; default: 0;
-         *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+         *  Mode bits in the flash fast read mode  it is combined with spi1_mem_c_fastrd_mode bit.
          */
         uint32_t wb_mode:8;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} spi_mem_rd_status_reg_t;
+} spi1_mem_c_rd_status_reg_t;
 
 /** Type of misc register
  *  SPI1 misc register
@@ -461,7 +461,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_misc_reg_t;
+} spi1_mem_c_misc_reg_t;
 
 /** Type of cache_fctrl register
  *  SPI1 bit mode control register.
@@ -476,38 +476,38 @@ typedef union {
         uint32_t reserved_2:1;
         /** fdin_dual : R/W; bitpos: [3]; default: 0;
          *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
-         *  spi_mem_fread_dio.
+         *  spi1_mem_c_fread_dio.
          */
         uint32_t fdin_dual:1;
         /** fdout_dual : R/W; bitpos: [4]; default: 0;
          *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_c_fread_dio.
          */
         uint32_t fdout_dual:1;
         /** faddr_dual : R/W; bitpos: [5]; default: 0;
          *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_c_fread_dio.
          */
         uint32_t faddr_dual:1;
         /** fdin_quad : R/W; bitpos: [6]; default: 0;
          *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_c_fread_qio.
          */
         uint32_t fdin_quad:1;
         /** fdout_quad : R/W; bitpos: [7]; default: 0;
          *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_c_fread_qio.
          */
         uint32_t fdout_quad:1;
         /** faddr_quad : R/W; bitpos: [8]; default: 0;
          *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_c_fread_qio.
          */
         uint32_t faddr_quad:1;
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_mem_cache_fctrl_reg_t;
+} spi1_mem_c_cache_fctrl_reg_t;
 
 /** Type of flash_waiti_ctrl register
  *  SPI1 wait idle control register
@@ -530,9 +530,9 @@ typedef union {
          */
         uint32_t waiti_addr_en:1;
         /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
-         *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
-         *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
-         *  SPI_MEM_WAITI_ADDR_EN is cleared.
+         *  When SPI1_MEM_C_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+         *  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+         *  SPI1_MEM_C_WAITI_ADDR_EN is cleared.
          */
         uint32_t waiti_addr_cyclelen:2;
         uint32_t reserved_5:4;
@@ -550,7 +550,7 @@ typedef union {
         uint32_t waiti_cmd:16;
     };
     uint32_t val;
-} spi_mem_flash_waiti_ctrl_reg_t;
+} spi1_mem_c_flash_waiti_ctrl_reg_t;
 
 /** Type of flash_sus_ctrl register
  *  SPI1 flash suspend control register
@@ -570,13 +570,13 @@ typedef union {
          */
         uint32_t flash_pes:1;
         /** flash_per_wait_en : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase resume command is sent. 0: SPI1 does not wait after program erase
          *  resume command is sent.
          */
         uint32_t flash_per_wait_en:1;
         /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
          *  suspend command is sent.
          */
@@ -594,7 +594,7 @@ typedef union {
          *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
          *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
          *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
-         *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+         *  status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0].
          */
         uint32_t pesr_end_msk:16;
         /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0;
@@ -613,13 +613,13 @@ typedef union {
          */
         uint32_t pes_end_en:1;
         /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
-         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it
          *  will be treated as check pass.
          */
         uint32_t sus_timeout_cnt:7;
     };
     uint32_t val;
-} spi_mem_flash_sus_ctrl_reg_t;
+} spi1_mem_c_flash_sus_ctrl_reg_t;
 
 /** Type of flash_sus_cmd register
  *  SPI1 flash suspend command register
@@ -637,7 +637,7 @@ typedef union {
         uint32_t wait_pesr_command:16;
     };
     uint32_t val;
-} spi_mem_flash_sus_cmd_reg_t;
+} spi1_mem_c_flash_sus_cmd_reg_t;
 
 /** Type of sus_status register
  *  SPI1 flash suspend status register
@@ -649,39 +649,39 @@ typedef union {
          */
         uint32_t flash_sus:1;
         /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0;
-         *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
-         *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+         *  1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+         *  SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
          */
         uint32_t wait_pesr_cmd_2b:1;
         /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after HPM command is sent.
          */
         uint32_t flash_hpm_dly_128:1;
         /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after RES command is sent.
          */
         uint32_t flash_res_dly_128:1;
         /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after DP command is sent.
          */
         uint32_t flash_dp_dly_128:1;
         /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+         *  Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
          *  sent.
          */
         uint32_t flash_per_dly_128:1;
         /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+         *  Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
          *  sent.
          */
         uint32_t flash_pes_dly_128:1;
@@ -701,7 +701,7 @@ typedef union {
         uint32_t flash_per_command:16;
     };
     uint32_t val;
-} spi_mem_sus_status_reg_t;
+} spi1_mem_c_sus_status_reg_t;
 
 /** Type of ddr register
  *  SPI1 DDR control register
@@ -739,7 +739,7 @@ typedef union {
         uint32_t fmem_usr_ddr_dqs_thd:7;
         /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -776,7 +776,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_mem_ddr_reg_t;
+} spi1_mem_c_ddr_reg_t;
 
 /** Type of clock_gate register
  *  SPI1 clk_gate register
@@ -790,7 +790,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_clock_gate_reg_t;
+} spi1_mem_c_clock_gate_reg_t;
 
 
 /** Group: Status register */
@@ -805,7 +805,7 @@ typedef union {
         uint32_t tx_crc_data:32;
     };
     uint32_t val;
-} spi_mem_tx_crc_reg_t;
+} spi1_mem_c_tx_crc_reg_t;
 
 
 /** Group: Memory data buffer register */
@@ -820,7 +820,7 @@ typedef union {
         uint32_t buf0:32;
     };
     uint32_t val;
-} spi_mem_w0_reg_t;
+} spi1_mem_c_w0_reg_t;
 
 /** Type of w1 register
  *  SPI1 memory data buffer1
@@ -833,7 +833,7 @@ typedef union {
         uint32_t buf1:32;
     };
     uint32_t val;
-} spi_mem_w1_reg_t;
+} spi1_mem_c_w1_reg_t;
 
 /** Type of w2 register
  *  SPI1 memory data buffer2
@@ -846,7 +846,7 @@ typedef union {
         uint32_t buf2:32;
     };
     uint32_t val;
-} spi_mem_w2_reg_t;
+} spi1_mem_c_w2_reg_t;
 
 /** Type of w3 register
  *  SPI1 memory data buffer3
@@ -859,7 +859,7 @@ typedef union {
         uint32_t buf3:32;
     };
     uint32_t val;
-} spi_mem_w3_reg_t;
+} spi1_mem_c_w3_reg_t;
 
 /** Type of w4 register
  *  SPI1 memory data buffer4
@@ -872,7 +872,7 @@ typedef union {
         uint32_t buf4:32;
     };
     uint32_t val;
-} spi_mem_w4_reg_t;
+} spi1_mem_c_w4_reg_t;
 
 /** Type of w5 register
  *  SPI1 memory data buffer5
@@ -885,7 +885,7 @@ typedef union {
         uint32_t buf5:32;
     };
     uint32_t val;
-} spi_mem_w5_reg_t;
+} spi1_mem_c_w5_reg_t;
 
 /** Type of w6 register
  *  SPI1 memory data buffer6
@@ -898,7 +898,7 @@ typedef union {
         uint32_t buf6:32;
     };
     uint32_t val;
-} spi_mem_w6_reg_t;
+} spi1_mem_c_w6_reg_t;
 
 /** Type of w7 register
  *  SPI1 memory data buffer7
@@ -911,7 +911,7 @@ typedef union {
         uint32_t buf7:32;
     };
     uint32_t val;
-} spi_mem_w7_reg_t;
+} spi1_mem_c_w7_reg_t;
 
 /** Type of w8 register
  *  SPI1 memory data buffer8
@@ -924,7 +924,7 @@ typedef union {
         uint32_t buf8:32;
     };
     uint32_t val;
-} spi_mem_w8_reg_t;
+} spi1_mem_c_w8_reg_t;
 
 /** Type of w9 register
  *  SPI1 memory data buffer9
@@ -937,7 +937,7 @@ typedef union {
         uint32_t buf9:32;
     };
     uint32_t val;
-} spi_mem_w9_reg_t;
+} spi1_mem_c_w9_reg_t;
 
 /** Type of w10 register
  *  SPI1 memory data buffer10
@@ -950,7 +950,7 @@ typedef union {
         uint32_t buf10:32;
     };
     uint32_t val;
-} spi_mem_w10_reg_t;
+} spi1_mem_c_w10_reg_t;
 
 /** Type of w11 register
  *  SPI1 memory data buffer11
@@ -963,7 +963,7 @@ typedef union {
         uint32_t buf11:32;
     };
     uint32_t val;
-} spi_mem_w11_reg_t;
+} spi1_mem_c_w11_reg_t;
 
 /** Type of w12 register
  *  SPI1 memory data buffer12
@@ -976,7 +976,7 @@ typedef union {
         uint32_t buf12:32;
     };
     uint32_t val;
-} spi_mem_w12_reg_t;
+} spi1_mem_c_w12_reg_t;
 
 /** Type of w13 register
  *  SPI1 memory data buffer13
@@ -989,7 +989,7 @@ typedef union {
         uint32_t buf13:32;
     };
     uint32_t val;
-} spi_mem_w13_reg_t;
+} spi1_mem_c_w13_reg_t;
 
 /** Type of w14 register
  *  SPI1 memory data buffer14
@@ -1002,7 +1002,7 @@ typedef union {
         uint32_t buf14:32;
     };
     uint32_t val;
-} spi_mem_w14_reg_t;
+} spi1_mem_c_w14_reg_t;
 
 /** Type of w15 register
  *  SPI1 memory data buffer15
@@ -1015,7 +1015,7 @@ typedef union {
         uint32_t buf15:32;
     };
     uint32_t val;
-} spi_mem_w15_reg_t;
+} spi1_mem_c_w15_reg_t;
 
 
 /** Group: Interrupt registers */
@@ -1025,34 +1025,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_MEM_PER_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_PER_END_INT interrupt.
          */
         uint32_t per_end_int_ena:1;
         /** pes_end_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_MEM_PES_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_ena:1;
         /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_ena:1;
         /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_ena:1;
         /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_ena:1;
         uint32_t reserved_5:5;
         /** brown_out_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_ena:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_ena_reg_t;
+} spi1_mem_c_int_ena_reg_t;
 
 /** Type of int_clr register
  *  SPI1 interrupt clear register
@@ -1060,34 +1060,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_MEM_PER_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_PER_END_INT interrupt.
          */
         uint32_t per_end_int_clr:1;
         /** pes_end_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_MEM_PES_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_clr:1;
         /** wpe_end_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_clr:1;
         /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_clr:1;
         /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_clr:1;
         uint32_t reserved_5:5;
         /** brown_out_int_clr : WT; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_clr:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_clr_reg_t;
+} spi1_mem_c_int_clr_reg_t;
 
 /** Type of int_raw register
  *  SPI1 interrupt raw register
@@ -1095,34 +1095,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+         *  The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume
          *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
          */
         uint32_t per_end_int_raw:1;
         /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+         *  The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend
          *  command (0x75) is sent and flash is suspended successfully. 0: Others.
          */
         uint32_t pes_end_int_raw:1;
         /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+         *  The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
          *  is sent and flash is already idle. 0: Others.
          */
         uint32_t wpe_end_int_raw:1;
         /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+         *  The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
         uint32_t slv_st_end_int_raw:1;
         /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+         *  The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
         uint32_t mst_st_end_int_raw:1;
         uint32_t reserved_5:5;
         /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+         *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
          *  chip is loosing power and RTC module sends out brown out close flash request to
          *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
          *  and MSPI returns to idle state. 0: Others.
@@ -1131,7 +1131,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_raw_reg_t;
+} spi1_mem_c_int_raw_reg_t;
 
 /** Type of int_st register
  *  SPI1 interrupt status register
@@ -1139,34 +1139,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_MEM_PER_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_PER_END_INT interrupt.
          */
         uint32_t per_end_int_st:1;
         /** pes_end_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_MEM_PES_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_st:1;
         /** wpe_end_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_st:1;
         /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_st:1;
         /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_st:1;
         uint32_t reserved_5:5;
         /** brown_out_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_st:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_st_reg_t;
+} spi1_mem_c_int_st_reg_t;
 
 
 /** Group: Timing registers */
@@ -1187,7 +1187,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} spi_mem_timing_cali_reg_t;
+} spi1_mem_c_timing_cali_reg_t;
 
 
 /** Group: Version register */
@@ -1203,65 +1203,65 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} spi_mem_date_reg_t;
+} spi1_mem_c_date_reg_t;
 
 
-typedef struct {
-    volatile spi_mem_cmd_reg_t cmd;
-    volatile spi_mem_addr_reg_t addr;
-    volatile spi_mem_ctrl_reg_t ctrl;
-    volatile spi_mem_ctrl1_reg_t ctrl1;
-    volatile spi_mem_ctrl2_reg_t ctrl2;
-    volatile spi_mem_clock_reg_t clock;
-    volatile spi_mem_user_reg_t user;
-    volatile spi_mem_user1_reg_t user1;
-    volatile spi_mem_user2_reg_t user2;
-    volatile spi_mem_mosi_dlen_reg_t mosi_dlen;
-    volatile spi_mem_miso_dlen_reg_t miso_dlen;
-    volatile spi_mem_rd_status_reg_t rd_status;
+typedef struct spi1_mem_c_dev_s {
+    volatile spi1_mem_c_cmd_reg_t cmd;
+    volatile spi1_mem_c_addr_reg_t addr;
+    volatile spi1_mem_c_ctrl_reg_t ctrl;
+    volatile spi1_mem_c_ctrl1_reg_t ctrl1;
+    volatile spi1_mem_c_ctrl2_reg_t ctrl2;
+    volatile spi1_mem_c_clock_reg_t clock;
+    volatile spi1_mem_c_user_reg_t user;
+    volatile spi1_mem_c_user1_reg_t user1;
+    volatile spi1_mem_c_user2_reg_t user2;
+    volatile spi1_mem_c_mosi_dlen_reg_t mosi_dlen;
+    volatile spi1_mem_c_miso_dlen_reg_t miso_dlen;
+    volatile spi1_mem_c_rd_status_reg_t rd_status;
     uint32_t reserved_030;
-    volatile spi_mem_misc_reg_t misc;
-    volatile spi_mem_tx_crc_reg_t tx_crc;
-    volatile spi_mem_cache_fctrl_reg_t cache_fctrl;
+    volatile spi1_mem_c_misc_reg_t misc;
+    volatile spi1_mem_c_tx_crc_reg_t tx_crc;
+    volatile spi1_mem_c_cache_fctrl_reg_t cache_fctrl;
     uint32_t reserved_040[6];
-    volatile spi_mem_w0_reg_t w0;
-    volatile spi_mem_w1_reg_t w1;
-    volatile spi_mem_w2_reg_t w2;
-    volatile spi_mem_w3_reg_t w3;
-    volatile spi_mem_w4_reg_t w4;
-    volatile spi_mem_w5_reg_t w5;
-    volatile spi_mem_w6_reg_t w6;
-    volatile spi_mem_w7_reg_t w7;
-    volatile spi_mem_w8_reg_t w8;
-    volatile spi_mem_w9_reg_t w9;
-    volatile spi_mem_w10_reg_t w10;
-    volatile spi_mem_w11_reg_t w11;
-    volatile spi_mem_w12_reg_t w12;
-    volatile spi_mem_w13_reg_t w13;
-    volatile spi_mem_w14_reg_t w14;
-    volatile spi_mem_w15_reg_t w15;
-    volatile spi_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
-    volatile spi_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
-    volatile spi_mem_flash_sus_cmd_reg_t flash_sus_cmd;
-    volatile spi_mem_sus_status_reg_t sus_status;
+    volatile spi1_mem_c_w0_reg_t w0;
+    volatile spi1_mem_c_w1_reg_t w1;
+    volatile spi1_mem_c_w2_reg_t w2;
+    volatile spi1_mem_c_w3_reg_t w3;
+    volatile spi1_mem_c_w4_reg_t w4;
+    volatile spi1_mem_c_w5_reg_t w5;
+    volatile spi1_mem_c_w6_reg_t w6;
+    volatile spi1_mem_c_w7_reg_t w7;
+    volatile spi1_mem_c_w8_reg_t w8;
+    volatile spi1_mem_c_w9_reg_t w9;
+    volatile spi1_mem_c_w10_reg_t w10;
+    volatile spi1_mem_c_w11_reg_t w11;
+    volatile spi1_mem_c_w12_reg_t w12;
+    volatile spi1_mem_c_w13_reg_t w13;
+    volatile spi1_mem_c_w14_reg_t w14;
+    volatile spi1_mem_c_w15_reg_t w15;
+    volatile spi1_mem_c_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
+    volatile spi1_mem_c_flash_sus_ctrl_reg_t flash_sus_ctrl;
+    volatile spi1_mem_c_flash_sus_cmd_reg_t flash_sus_cmd;
+    volatile spi1_mem_c_sus_status_reg_t sus_status;
     uint32_t reserved_0a8[6];
-    volatile spi_mem_int_ena_reg_t int_ena;
-    volatile spi_mem_int_clr_reg_t int_clr;
-    volatile spi_mem_int_raw_reg_t int_raw;
-    volatile spi_mem_int_st_reg_t int_st;
+    volatile spi1_mem_c_int_ena_reg_t int_ena;
+    volatile spi1_mem_c_int_clr_reg_t int_clr;
+    volatile spi1_mem_c_int_raw_reg_t int_raw;
+    volatile spi1_mem_c_int_st_reg_t int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_ddr_reg_t ddr;
+    volatile spi1_mem_c_ddr_reg_t ddr;
     uint32_t reserved_0d8[42];
-    volatile spi_mem_timing_cali_reg_t timing_cali;
+    volatile spi1_mem_c_timing_cali_reg_t timing_cali;
     uint32_t reserved_184[31];
-    volatile spi_mem_clock_gate_reg_t clock_gate;
+    volatile spi1_mem_c_clock_gate_reg_t clock_gate;
     uint32_t reserved_204[126];
-    volatile spi_mem_date_reg_t date;
+    volatile spi1_mem_c_date_reg_t date;
 } spi1_mem_c_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
+_Static_assert(sizeof(spi1_mem_c_dev_t) == 0x400, "Invalid size of spi1_mem_c_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h
index 7ea59c8413..8aa91923ec 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h
+++ b/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h
@@ -11,1470 +11,1470 @@
 extern "C" {
 #endif
 
-/** SPI_MEM_CMD_REG register
+/** SPI1_MEM_S_CMD_REG register
  *  SPI1 memory command register
  */
-#define SPI_MEM_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0x0)
-/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
+#define SPI1_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0x0)
+/** SPI1_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0;
  *  The current status of SPI1 master FSM.
  */
-#define SPI_MEM_MST_ST    0x0000000FU
-#define SPI_MEM_MST_ST_M  (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S)
-#define SPI_MEM_MST_ST_V  0x0000000FU
-#define SPI_MEM_MST_ST_S  0
-/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
+#define SPI1_MEM_S_MST_ST    0x0000000FU
+#define SPI1_MEM_S_MST_ST_M  (SPI1_MEM_S_MST_ST_V << SPI1_MEM_S_MST_ST_S)
+#define SPI1_MEM_S_MST_ST_V  0x0000000FU
+#define SPI1_MEM_S_MST_ST_S  0
+/** SPI1_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0;
  *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
  *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
  *  6:write data state, 7: done state, 8: read data end state.
  */
-#define SPI_MEM_SLV_ST    0x0000000FU
-#define SPI_MEM_SLV_ST_M  (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S)
-#define SPI_MEM_SLV_ST_V  0x0000000FU
-#define SPI_MEM_SLV_ST_S  4
-/** SPI_MEM_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
+#define SPI1_MEM_S_SLV_ST    0x0000000FU
+#define SPI1_MEM_S_SLV_ST_M  (SPI1_MEM_S_SLV_ST_V << SPI1_MEM_S_SLV_ST_S)
+#define SPI1_MEM_S_SLV_ST_V  0x0000000FU
+#define SPI1_MEM_S_SLV_ST_S  4
+/** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
  *  In user mode, it is set to indicate that program/erase operation will be triggered.
- *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+ *  The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the
  *  operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S)
-#define SPI_MEM_FLASH_PE_V  0x00000001U
-#define SPI_MEM_FLASH_PE_S  17
-/** SPI_MEM_USR : R/W/SC; bitpos: [18]; default: 0;
+#define SPI1_MEM_S_FLASH_PE    (BIT(17))
+#define SPI1_MEM_S_FLASH_PE_M  (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S)
+#define SPI1_MEM_S_FLASH_PE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PE_S  17
+/** SPI1_MEM_S_USR : R/W/SC; bitpos: [18]; default: 0;
  *  User define command enable.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (SPI_MEM_USR_V << SPI_MEM_USR_S)
-#define SPI_MEM_USR_V  0x00000001U
-#define SPI_MEM_USR_S  18
-/** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
+#define SPI1_MEM_S_USR    (BIT(18))
+#define SPI1_MEM_S_USR_M  (SPI1_MEM_S_USR_V << SPI1_MEM_S_USR_S)
+#define SPI1_MEM_S_USR_V  0x00000001U
+#define SPI1_MEM_S_USR_S  18
+/** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
  *  Drive Flash into high performance mode.  The bit will be cleared once the operation
  *  done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S)
-#define SPI_MEM_FLASH_HPM_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_S  19
-/** SPI_MEM_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
+#define SPI1_MEM_S_FLASH_HPM    (BIT(19))
+#define SPI1_MEM_S_FLASH_HPM_M  (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S)
+#define SPI1_MEM_S_FLASH_HPM_V  0x00000001U
+#define SPI1_MEM_S_FLASH_HPM_S  19
+/** SPI1_MEM_S_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
  *  This bit combined with reg_resandres bit releases Flash from the power-down state
  *  or high performance mode and obtains the devices ID. The bit will be cleared once
  *  the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S)
-#define SPI_MEM_FLASH_RES_V  0x00000001U
-#define SPI_MEM_FLASH_RES_S  20
-/** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
+#define SPI1_MEM_S_FLASH_RES    (BIT(20))
+#define SPI1_MEM_S_FLASH_RES_M  (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S)
+#define SPI1_MEM_S_FLASH_RES_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RES_S  20
+/** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
  *  Drive Flash into power down.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S)
-#define SPI_MEM_FLASH_DP_V  0x00000001U
-#define SPI_MEM_FLASH_DP_S  21
-/** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
+#define SPI1_MEM_S_FLASH_DP    (BIT(21))
+#define SPI1_MEM_S_FLASH_DP_M  (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S)
+#define SPI1_MEM_S_FLASH_DP_V  0x00000001U
+#define SPI1_MEM_S_FLASH_DP_S  21
+/** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
  *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S)
-#define SPI_MEM_FLASH_CE_V  0x00000001U
-#define SPI_MEM_FLASH_CE_S  22
-/** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
+#define SPI1_MEM_S_FLASH_CE    (BIT(22))
+#define SPI1_MEM_S_FLASH_CE_M  (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S)
+#define SPI1_MEM_S_FLASH_CE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_CE_S  22
+/** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
  *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S)
-#define SPI_MEM_FLASH_BE_V  0x00000001U
-#define SPI_MEM_FLASH_BE_S  23
-/** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_FLASH_BE    (BIT(23))
+#define SPI1_MEM_S_FLASH_BE_M  (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S)
+#define SPI1_MEM_S_FLASH_BE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_BE_S  23
+/** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
  *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S)
-#define SPI_MEM_FLASH_SE_V  0x00000001U
-#define SPI_MEM_FLASH_SE_S  24
-/** SPI_MEM_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
+#define SPI1_MEM_S_FLASH_SE    (BIT(24))
+#define SPI1_MEM_S_FLASH_SE_M  (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S)
+#define SPI1_MEM_S_FLASH_SE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_SE_S  24
+/** SPI1_MEM_S_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
  *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
  *  operation  will be triggered when the bit is set. The bit will be cleared once the
  *  operation done .1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S)
-#define SPI_MEM_FLASH_PP_V  0x00000001U
-#define SPI_MEM_FLASH_PP_S  25
-/** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
+#define SPI1_MEM_S_FLASH_PP    (BIT(25))
+#define SPI1_MEM_S_FLASH_PP_M  (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S)
+#define SPI1_MEM_S_FLASH_PP_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PP_S  25
+/** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
  *  Write status register enable.   Write status operation  will be triggered when the
  *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S)
-#define SPI_MEM_FLASH_WRSR_V  0x00000001U
-#define SPI_MEM_FLASH_WRSR_S  26
-/** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
+#define SPI1_MEM_S_FLASH_WRSR    (BIT(26))
+#define SPI1_MEM_S_FLASH_WRSR_M  (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S)
+#define SPI1_MEM_S_FLASH_WRSR_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WRSR_S  26
+/** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
  *  Read status register-1.  Read status operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S)
-#define SPI_MEM_FLASH_RDSR_V  0x00000001U
-#define SPI_MEM_FLASH_RDSR_S  27
-/** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
+#define SPI1_MEM_S_FLASH_RDSR    (BIT(27))
+#define SPI1_MEM_S_FLASH_RDSR_M  (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S)
+#define SPI1_MEM_S_FLASH_RDSR_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RDSR_S  27
+/** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
  *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
  *  cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S)
-#define SPI_MEM_FLASH_RDID_V  0x00000001U
-#define SPI_MEM_FLASH_RDID_S  28
-/** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
+#define SPI1_MEM_S_FLASH_RDID    (BIT(28))
+#define SPI1_MEM_S_FLASH_RDID_M  (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S)
+#define SPI1_MEM_S_FLASH_RDID_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RDID_S  28
+/** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
  *  Write flash disable. Write disable command will be sent when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S)
-#define SPI_MEM_FLASH_WRDI_V  0x00000001U
-#define SPI_MEM_FLASH_WRDI_S  29
-/** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
+#define SPI1_MEM_S_FLASH_WRDI    (BIT(29))
+#define SPI1_MEM_S_FLASH_WRDI_M  (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S)
+#define SPI1_MEM_S_FLASH_WRDI_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WRDI_S  29
+/** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
  *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
  *  will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S)
-#define SPI_MEM_FLASH_WREN_V  0x00000001U
-#define SPI_MEM_FLASH_WREN_S  30
-/** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
+#define SPI1_MEM_S_FLASH_WREN    (BIT(30))
+#define SPI1_MEM_S_FLASH_WREN_M  (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S)
+#define SPI1_MEM_S_FLASH_WREN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WREN_S  30
+/** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
  *  Read flash enable. Read flash operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S)
-#define SPI_MEM_FLASH_READ_V  0x00000001U
-#define SPI_MEM_FLASH_READ_S  31
+#define SPI1_MEM_S_FLASH_READ    (BIT(31))
+#define SPI1_MEM_S_FLASH_READ_M  (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S)
+#define SPI1_MEM_S_FLASH_READ_V  0x00000001U
+#define SPI1_MEM_S_FLASH_READ_S  31
 
-/** SPI_MEM_ADDR_REG register
+/** SPI1_MEM_S_ADDR_REG register
  *  SPI1 address register
  */
-#define SPI_MEM_ADDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0x4)
-/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_ADDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0x4)
+/** SPI1_MEM_S_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
  *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
  *  address, the bit24-bit31 are the byte length of a transfer.
  */
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_M  (SPI_MEM_USR_ADDR_VALUE_V << SPI_MEM_USR_ADDR_VALUE_S)
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_S  0
+#define SPI1_MEM_S_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI1_MEM_S_USR_ADDR_VALUE_M  (SPI1_MEM_S_USR_ADDR_VALUE_V << SPI1_MEM_S_USR_ADDR_VALUE_S)
+#define SPI1_MEM_S_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI1_MEM_S_USR_ADDR_VALUE_S  0
 
-/** SPI_MEM_CTRL_REG register
+/** SPI1_MEM_S_CTRL_REG register
  *  SPI1 control register.
  */
-#define SPI_MEM_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8)
-/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+#define SPI1_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8)
+/** SPI1_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
  *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S)
-#define SPI_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI_MEM_FDUMMY_RIN_S  2
-/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+#define SPI1_MEM_S_FDUMMY_RIN    (BIT(2))
+#define SPI1_MEM_S_FDUMMY_RIN_M  (SPI1_MEM_S_FDUMMY_RIN_V << SPI1_MEM_S_FDUMMY_RIN_S)
+#define SPI1_MEM_S_FDUMMY_RIN_V  0x00000001U
+#define SPI1_MEM_S_FDUMMY_RIN_S  2
+/** SPI1_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
  *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S)
-#define SPI_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FDUMMY_WOUT    (BIT(3))
+#define SPI1_MEM_S_FDUMMY_WOUT_M  (SPI1_MEM_S_FDUMMY_WOUT_V << SPI1_MEM_S_FDUMMY_WOUT_S)
+#define SPI1_MEM_S_FDUMMY_WOUT_V  0x00000001U
+#define SPI1_MEM_S_FDUMMY_WOUT_S  3
+/** SPI1_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
  *  Apply 8 signals during write-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S)
-#define SPI_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI_MEM_FDOUT_OCT_S  4
-/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_S_FDOUT_OCT    (BIT(4))
+#define SPI1_MEM_S_FDOUT_OCT_M  (SPI1_MEM_S_FDOUT_OCT_V << SPI1_MEM_S_FDOUT_OCT_S)
+#define SPI1_MEM_S_FDOUT_OCT_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_OCT_S  4
+/** SPI1_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0;
  *  Apply 8 signals during read-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S)
-#define SPI_MEM_FDIN_OCT_V  0x00000001U
-#define SPI_MEM_FDIN_OCT_S  5
-/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0;
+#define SPI1_MEM_S_FDIN_OCT    (BIT(5))
+#define SPI1_MEM_S_FDIN_OCT_M  (SPI1_MEM_S_FDIN_OCT_V << SPI1_MEM_S_FDIN_OCT_S)
+#define SPI1_MEM_S_FDIN_OCT_V  0x00000001U
+#define SPI1_MEM_S_FDIN_OCT_S  5
+/** SPI1_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0;
  *  Apply 8 signals during address phase 1:enable 0: disable
  */
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S)
-#define SPI_MEM_FADDR_OCT_V  0x00000001U
-#define SPI_MEM_FADDR_OCT_S  6
-/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_S_FADDR_OCT    (BIT(6))
+#define SPI1_MEM_S_FADDR_OCT_M  (SPI1_MEM_S_FADDR_OCT_V << SPI1_MEM_S_FADDR_OCT_S)
+#define SPI1_MEM_S_FADDR_OCT_V  0x00000001U
+#define SPI1_MEM_S_FADDR_OCT_S  6
+/** SPI1_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
  *  Apply 4 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S)
-#define SPI_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI_MEM_FCMD_QUAD_S  8
-/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_S_FCMD_QUAD    (BIT(8))
+#define SPI1_MEM_S_FCMD_QUAD_M  (SPI1_MEM_S_FCMD_QUAD_V << SPI1_MEM_S_FCMD_QUAD_S)
+#define SPI1_MEM_S_FCMD_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FCMD_QUAD_S  8
+/** SPI1_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0;
  *  Apply 8 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S)
-#define SPI_MEM_FCMD_OCT_V  0x00000001U
-#define SPI_MEM_FCMD_OCT_S  9
-/** SPI_MEM_FCS_CRC_EN : R/W; bitpos: [10]; default: 0;
+#define SPI1_MEM_S_FCMD_OCT    (BIT(9))
+#define SPI1_MEM_S_FCMD_OCT_M  (SPI1_MEM_S_FCMD_OCT_V << SPI1_MEM_S_FCMD_OCT_S)
+#define SPI1_MEM_S_FCMD_OCT_V  0x00000001U
+#define SPI1_MEM_S_FCMD_OCT_S  9
+/** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0;
  *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
  *  low.
  */
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S)
-#define SPI_MEM_FCS_CRC_EN_V  0x00000001U
-#define SPI_MEM_FCS_CRC_EN_S  10
-/** SPI_MEM_TX_CRC_EN : R/W; bitpos: [11]; default: 0;
+#define SPI1_MEM_S_FCS_CRC_EN    (BIT(10))
+#define SPI1_MEM_S_FCS_CRC_EN_M  (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S)
+#define SPI1_MEM_S_FCS_CRC_EN_V  0x00000001U
+#define SPI1_MEM_S_FCS_CRC_EN_S  10
+/** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0;
  *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
  */
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S)
-#define SPI_MEM_TX_CRC_EN_V  0x00000001U
-#define SPI_MEM_TX_CRC_EN_S  11
-/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
- *  and spi_mem_fread_dout. 1: enable 0: disable.
+#define SPI1_MEM_S_TX_CRC_EN    (BIT(11))
+#define SPI1_MEM_S_TX_CRC_EN_M  (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S)
+#define SPI1_MEM_S_TX_CRC_EN_V  0x00000001U
+#define SPI1_MEM_S_TX_CRC_EN_S  11
+/** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout
+ *  and spi1_mem_s_fread_dout. 1: enable 0: disable.
  */
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S)
-#define SPI_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI_MEM_FASTRD_MODE_S  13
-/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_S_FASTRD_MODE    (BIT(13))
+#define SPI1_MEM_S_FASTRD_MODE_M  (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S)
+#define SPI1_MEM_S_FASTRD_MODE_V  0x00000001U
+#define SPI1_MEM_S_FASTRD_MODE_S  13
+/** SPI1_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
  *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S)
-#define SPI_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI_MEM_FREAD_DUAL_S  14
-/** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1;
- *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
- *  spi_mem_flash_res bit. 1: enable 0: disable.
+#define SPI1_MEM_S_FREAD_DUAL    (BIT(14))
+#define SPI1_MEM_S_FREAD_DUAL_M  (SPI1_MEM_S_FREAD_DUAL_V << SPI1_MEM_S_FREAD_DUAL_S)
+#define SPI1_MEM_S_FREAD_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FREAD_DUAL_S  14
+/** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1;
+ *  The Device ID is read out to SPI1_MEM_S_RD_STATUS register,  this bit combine with
+ *  spi1_mem_s_flash_res bit. 1: enable 0: disable.
  */
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S)
-#define SPI_MEM_RESANDRES_V  0x00000001U
-#define SPI_MEM_RESANDRES_S  15
-/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
+#define SPI1_MEM_S_RESANDRES    (BIT(15))
+#define SPI1_MEM_S_RESANDRES_M  (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S)
+#define SPI1_MEM_S_RESANDRES_V  0x00000001U
+#define SPI1_MEM_S_RESANDRES_S  15
+/** SPI1_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1;
  *  The bit is used to set MISO line polarity, 1: high 0, low
  */
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S)
-#define SPI_MEM_Q_POL_V  0x00000001U
-#define SPI_MEM_Q_POL_S  18
-/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1;
+#define SPI1_MEM_S_Q_POL    (BIT(18))
+#define SPI1_MEM_S_Q_POL_M  (SPI1_MEM_S_Q_POL_V << SPI1_MEM_S_Q_POL_S)
+#define SPI1_MEM_S_Q_POL_V  0x00000001U
+#define SPI1_MEM_S_Q_POL_S  18
+/** SPI1_MEM_S_D_POL : R/W; bitpos: [19]; default: 1;
  *  The bit is used to set MOSI line polarity, 1: high 0, low
  */
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S)
-#define SPI_MEM_D_POL_V  0x00000001U
-#define SPI_MEM_D_POL_S  19
-/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+#define SPI1_MEM_S_D_POL    (BIT(19))
+#define SPI1_MEM_S_D_POL_M  (SPI1_MEM_S_D_POL_V << SPI1_MEM_S_D_POL_S)
+#define SPI1_MEM_S_D_POL_V  0x00000001U
+#define SPI1_MEM_S_D_POL_S  19
+/** SPI1_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
  *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S)
-#define SPI_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI_MEM_FREAD_QUAD_S  20
-/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
+#define SPI1_MEM_S_FREAD_QUAD    (BIT(20))
+#define SPI1_MEM_S_FREAD_QUAD_M  (SPI1_MEM_S_FREAD_QUAD_V << SPI1_MEM_S_FREAD_QUAD_S)
+#define SPI1_MEM_S_FREAD_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FREAD_QUAD_S  20
+/** SPI1_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1;
  *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
  */
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S)
-#define SPI_MEM_WP_REG_V  0x00000001U
-#define SPI_MEM_WP_REG_S  21
-/** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_S_WP_REG    (BIT(21))
+#define SPI1_MEM_S_WP_REG_M  (SPI1_MEM_S_WP_REG_V << SPI1_MEM_S_WP_REG_S)
+#define SPI1_MEM_S_WP_REG_V  0x00000001U
+#define SPI1_MEM_S_WP_REG_S  21
+/** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0;
  *  two bytes data will be written to status register when it is set. 1: enable 0:
  *  disable.
  */
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S)
-#define SPI_MEM_WRSR_2B_V  0x00000001U
-#define SPI_MEM_WRSR_2B_S  22
-/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_S_WRSR_2B    (BIT(22))
+#define SPI1_MEM_S_WRSR_2B_M  (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S)
+#define SPI1_MEM_S_WRSR_2B_V  0x00000001U
+#define SPI1_MEM_S_WRSR_2B_S  22
+/** SPI1_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0;
  *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S)
-#define SPI_MEM_FREAD_DIO_V  0x00000001U
-#define SPI_MEM_FREAD_DIO_S  23
-/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_FREAD_DIO    (BIT(23))
+#define SPI1_MEM_S_FREAD_DIO_M  (SPI1_MEM_S_FREAD_DIO_V << SPI1_MEM_S_FREAD_DIO_S)
+#define SPI1_MEM_S_FREAD_DIO_V  0x00000001U
+#define SPI1_MEM_S_FREAD_DIO_S  23
+/** SPI1_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0;
  *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S)
-#define SPI_MEM_FREAD_QIO_V  0x00000001U
-#define SPI_MEM_FREAD_QIO_S  24
+#define SPI1_MEM_S_FREAD_QIO    (BIT(24))
+#define SPI1_MEM_S_FREAD_QIO_M  (SPI1_MEM_S_FREAD_QIO_V << SPI1_MEM_S_FREAD_QIO_S)
+#define SPI1_MEM_S_FREAD_QIO_V  0x00000001U
+#define SPI1_MEM_S_FREAD_QIO_S  24
 
-/** SPI_MEM_CTRL1_REG register
+/** SPI1_MEM_S_CTRL1_REG register
  *  SPI1 control1 register.
  */
-#define SPI_MEM_CTRL1_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc)
-/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+#define SPI1_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc)
+/** SPI1_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
  *  SPI clock is alwasy on.
  */
-#define SPI_MEM_CLK_MODE    0x00000003U
-#define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
-#define SPI_MEM_CLK_MODE_V  0x00000003U
-#define SPI_MEM_CLK_MODE_S  0
-/** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
- *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+#define SPI1_MEM_S_CLK_MODE    0x00000003U
+#define SPI1_MEM_S_CLK_MODE_M  (SPI1_MEM_S_CLK_MODE_V << SPI1_MEM_S_CLK_MODE_S)
+#define SPI1_MEM_S_CLK_MODE_V  0x00000003U
+#define SPI1_MEM_S_CLK_MODE_S  0
+/** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
+ *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512)
  *  SPI_CLK cycles.
  */
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_M  (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S)
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+#define SPI1_MEM_S_CS_HOLD_DLY_RES    0x000003FFU
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_M  (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S)
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_V  0x000003FFU
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_S  2
 
-/** SPI_MEM_CTRL2_REG register
+/** SPI1_MEM_S_CTRL2_REG register
  *  SPI1 control2 register.
  */
-#define SPI_MEM_CTRL2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x10)
-/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
+#define SPI1_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x10)
+/** SPI1_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0;
  *  The FSM will be reset.
  */
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S)
-#define SPI_MEM_SYNC_RESET_V  0x00000001U
-#define SPI_MEM_SYNC_RESET_S  31
+#define SPI1_MEM_S_SYNC_RESET    (BIT(31))
+#define SPI1_MEM_S_SYNC_RESET_M  (SPI1_MEM_S_SYNC_RESET_V << SPI1_MEM_S_SYNC_RESET_S)
+#define SPI1_MEM_S_SYNC_RESET_V  0x00000001U
+#define SPI1_MEM_S_SYNC_RESET_S  31
 
-/** SPI_MEM_CLOCK_REG register
+/** SPI1_MEM_S_CLOCK_REG register
  *  SPI1 clock division control register.
  */
-#define SPI_MEM_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14)
-/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
- *  In the master mode it must be equal to spi_mem_clkcnt_N.
+#define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14)
+/** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi1_mem_s_clkcnt_N.
  */
-#define SPI_MEM_CLKCNT_L    0x000000FFU
-#define SPI_MEM_CLKCNT_L_M  (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
-#define SPI_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI_MEM_CLKCNT_L_S  0
-/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
- *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+#define SPI1_MEM_S_CLKCNT_L    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_L_M  (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S)
+#define SPI1_MEM_S_CLKCNT_L_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_L_S  0
+/** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1).
  */
-#define SPI_MEM_CLKCNT_H    0x000000FFU
-#define SPI_MEM_CLKCNT_H_M  (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
-#define SPI_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI_MEM_CLKCNT_H_S  8
-/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
- *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- *  system/(spi_mem_clkcnt_N+1)
+#define SPI1_MEM_S_CLKCNT_H    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_H_M  (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S)
+#define SPI1_MEM_S_CLKCNT_H_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_H_S  8
+/** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is
+ *  system/(spi1_mem_s_clkcnt_N+1)
  */
-#define SPI_MEM_CLKCNT_N    0x000000FFU
-#define SPI_MEM_CLKCNT_N_M  (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
-#define SPI_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI_MEM_CLKCNT_N_S  16
-/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+#define SPI1_MEM_S_CLKCNT_N    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_N_M  (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S)
+#define SPI1_MEM_S_CLKCNT_N_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_N_S  16
+/** SPI1_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
  *  reserved
  */
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S)
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+#define SPI1_MEM_S_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_M  (SPI1_MEM_S_CLK_EQU_SYSCLK_V << SPI1_MEM_S_CLK_EQU_SYSCLK_S)
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_S  31
 
-/** SPI_MEM_USER_REG register
+/** SPI1_MEM_S_USER_REG register
  *  SPI1 user register.
  */
-#define SPI_MEM_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18)
-/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+#define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18)
+/** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode.
  */
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S)
-#define SPI_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/** SPI_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+#define SPI1_MEM_S_CK_OUT_EDGE    (BIT(9))
+#define SPI1_MEM_S_CK_OUT_EDGE_M  (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S)
+#define SPI1_MEM_S_CK_OUT_EDGE_V  0x00000001U
+#define SPI1_MEM_S_CK_OUT_EDGE_S  9
+/** SPI1_MEM_S_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
  *  In the write operations read-data phase apply 2 signals
  */
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (SPI_MEM_FWRITE_DUAL_V << SPI_MEM_FWRITE_DUAL_S)
-#define SPI_MEM_FWRITE_DUAL_V  0x00000001U
-#define SPI_MEM_FWRITE_DUAL_S  12
-/** SPI_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+#define SPI1_MEM_S_FWRITE_DUAL    (BIT(12))
+#define SPI1_MEM_S_FWRITE_DUAL_M  (SPI1_MEM_S_FWRITE_DUAL_V << SPI1_MEM_S_FWRITE_DUAL_S)
+#define SPI1_MEM_S_FWRITE_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_DUAL_S  12
+/** SPI1_MEM_S_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
  *  In the write operations read-data phase apply 4 signals
  */
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (SPI_MEM_FWRITE_QUAD_V << SPI_MEM_FWRITE_QUAD_S)
-#define SPI_MEM_FWRITE_QUAD_V  0x00000001U
-#define SPI_MEM_FWRITE_QUAD_S  13
-/** SPI_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_S_FWRITE_QUAD    (BIT(13))
+#define SPI1_MEM_S_FWRITE_QUAD_M  (SPI1_MEM_S_FWRITE_QUAD_V << SPI1_MEM_S_FWRITE_QUAD_S)
+#define SPI1_MEM_S_FWRITE_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_QUAD_S  13
+/** SPI1_MEM_S_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
  *  In the write operations address phase and read-data phase apply 2 signals.
  */
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (SPI_MEM_FWRITE_DIO_V << SPI_MEM_FWRITE_DIO_S)
-#define SPI_MEM_FWRITE_DIO_V  0x00000001U
-#define SPI_MEM_FWRITE_DIO_S  14
-/** SPI_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_S_FWRITE_DIO    (BIT(14))
+#define SPI1_MEM_S_FWRITE_DIO_M  (SPI1_MEM_S_FWRITE_DIO_V << SPI1_MEM_S_FWRITE_DIO_S)
+#define SPI1_MEM_S_FWRITE_DIO_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_DIO_S  14
+/** SPI1_MEM_S_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
  *  In the write operations address phase and read-data phase apply 4 signals.
  */
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (SPI_MEM_FWRITE_QIO_V << SPI_MEM_FWRITE_QIO_S)
-#define SPI_MEM_FWRITE_QIO_V  0x00000001U
-#define SPI_MEM_FWRITE_QIO_S  15
-/** SPI_MEM_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_S_FWRITE_QIO    (BIT(15))
+#define SPI1_MEM_S_FWRITE_QIO_M  (SPI1_MEM_S_FWRITE_QIO_V << SPI1_MEM_S_FWRITE_QIO_S)
+#define SPI1_MEM_S_FWRITE_QIO_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_QIO_S  15
+/** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (SPI_MEM_USR_MISO_HIGHPART_V << SPI_MEM_USR_MISO_HIGHPART_S)
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/** SPI_MEM_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_S_USR_MISO_HIGHPART    (BIT(24))
+#define SPI1_MEM_S_USR_MISO_HIGHPART_M  (SPI1_MEM_S_USR_MISO_HIGHPART_V << SPI1_MEM_S_USR_MISO_HIGHPART_S)
+#define SPI1_MEM_S_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI1_MEM_S_USR_MISO_HIGHPART_S  24
+/** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (SPI_MEM_USR_MOSI_HIGHPART_V << SPI_MEM_USR_MOSI_HIGHPART_S)
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+#define SPI1_MEM_S_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_M  (SPI1_MEM_S_USR_MOSI_HIGHPART_V << SPI1_MEM_S_USR_MOSI_HIGHPART_S)
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_S  25
+/** SPI1_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
  *  SPI clock is disable in dummy phase when the bit is enable.
  */
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S)
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/** SPI_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0;
+#define SPI1_MEM_S_USR_DUMMY_IDLE    (BIT(26))
+#define SPI1_MEM_S_USR_DUMMY_IDLE_M  (SPI1_MEM_S_USR_DUMMY_IDLE_V << SPI1_MEM_S_USR_DUMMY_IDLE_S)
+#define SPI1_MEM_S_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI1_MEM_S_USR_DUMMY_IDLE_S  26
+/** SPI1_MEM_S_USR_MOSI : R/W; bitpos: [27]; default: 0;
  *  This bit enable the write-data phase of an operation.
  */
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (SPI_MEM_USR_MOSI_V << SPI_MEM_USR_MOSI_S)
-#define SPI_MEM_USR_MOSI_V  0x00000001U
-#define SPI_MEM_USR_MOSI_S  27
-/** SPI_MEM_USR_MISO : R/W; bitpos: [28]; default: 0;
+#define SPI1_MEM_S_USR_MOSI    (BIT(27))
+#define SPI1_MEM_S_USR_MOSI_M  (SPI1_MEM_S_USR_MOSI_V << SPI1_MEM_S_USR_MOSI_S)
+#define SPI1_MEM_S_USR_MOSI_V  0x00000001U
+#define SPI1_MEM_S_USR_MOSI_S  27
+/** SPI1_MEM_S_USR_MISO : R/W; bitpos: [28]; default: 0;
  *  This bit enable the read-data phase of an operation.
  */
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (SPI_MEM_USR_MISO_V << SPI_MEM_USR_MISO_S)
-#define SPI_MEM_USR_MISO_V  0x00000001U
-#define SPI_MEM_USR_MISO_S  28
-/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+#define SPI1_MEM_S_USR_MISO    (BIT(28))
+#define SPI1_MEM_S_USR_MISO_M  (SPI1_MEM_S_USR_MISO_V << SPI1_MEM_S_USR_MISO_S)
+#define SPI1_MEM_S_USR_MISO_V  0x00000001U
+#define SPI1_MEM_S_USR_MISO_S  28
+/** SPI1_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0;
  *  This bit enable the dummy phase of an operation.
  */
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S)
-#define SPI_MEM_USR_DUMMY_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_S  29
-/** SPI_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0;
+#define SPI1_MEM_S_USR_DUMMY    (BIT(29))
+#define SPI1_MEM_S_USR_DUMMY_M  (SPI1_MEM_S_USR_DUMMY_V << SPI1_MEM_S_USR_DUMMY_S)
+#define SPI1_MEM_S_USR_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_USR_DUMMY_S  29
+/** SPI1_MEM_S_USR_ADDR : R/W; bitpos: [30]; default: 0;
  *  This bit enable the address phase of an operation.
  */
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (SPI_MEM_USR_ADDR_V << SPI_MEM_USR_ADDR_S)
-#define SPI_MEM_USR_ADDR_V  0x00000001U
-#define SPI_MEM_USR_ADDR_S  30
-/** SPI_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+#define SPI1_MEM_S_USR_ADDR    (BIT(30))
+#define SPI1_MEM_S_USR_ADDR_M  (SPI1_MEM_S_USR_ADDR_V << SPI1_MEM_S_USR_ADDR_S)
+#define SPI1_MEM_S_USR_ADDR_V  0x00000001U
+#define SPI1_MEM_S_USR_ADDR_S  30
+/** SPI1_MEM_S_USR_COMMAND : R/W; bitpos: [31]; default: 1;
  *  This bit enable the command phase of an operation.
  */
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (SPI_MEM_USR_COMMAND_V << SPI_MEM_USR_COMMAND_S)
-#define SPI_MEM_USR_COMMAND_V  0x00000001U
-#define SPI_MEM_USR_COMMAND_S  31
+#define SPI1_MEM_S_USR_COMMAND    (BIT(31))
+#define SPI1_MEM_S_USR_COMMAND_M  (SPI1_MEM_S_USR_COMMAND_V << SPI1_MEM_S_USR_COMMAND_S)
+#define SPI1_MEM_S_USR_COMMAND_V  0x00000001U
+#define SPI1_MEM_S_USR_COMMAND_S  31
 
-/** SPI_MEM_USER1_REG register
+/** SPI1_MEM_S_USER1_REG register
  *  SPI1 user1 register.
  */
-#define SPI_MEM_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c)
-/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
- *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+#define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c)
+/** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1).
  */
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_M  (SPI1_MEM_S_USR_DUMMY_CYCLELEN_V << SPI1_MEM_S_USR_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_S  0
+/** SPI1_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
  *  The length in bits of address phase. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_M  (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S)
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
+#define SPI1_MEM_S_USR_ADDR_BITLEN    0x0000003FU
+#define SPI1_MEM_S_USR_ADDR_BITLEN_M  (SPI1_MEM_S_USR_ADDR_BITLEN_V << SPI1_MEM_S_USR_ADDR_BITLEN_S)
+#define SPI1_MEM_S_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI1_MEM_S_USR_ADDR_BITLEN_S  26
 
-/** SPI_MEM_USER2_REG register
+/** SPI1_MEM_S_USER2_REG register
  *  SPI1 user2 register.
  */
-#define SPI_MEM_USER2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x20)
-/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+#define SPI1_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x20)
+/** SPI1_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command.
  */
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_M  (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S)
-#define SPI_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+#define SPI1_MEM_S_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI1_MEM_S_USR_COMMAND_VALUE_M  (SPI1_MEM_S_USR_COMMAND_VALUE_V << SPI1_MEM_S_USR_COMMAND_VALUE_S)
+#define SPI1_MEM_S_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI1_MEM_S_USR_COMMAND_VALUE_S  0
+/** SPI1_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
  *  The length in bits of command phase. The register value shall be (bit_num-1)
  */
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_M  (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S)
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+#define SPI1_MEM_S_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_M  (SPI1_MEM_S_USR_COMMAND_BITLEN_V << SPI1_MEM_S_USR_COMMAND_BITLEN_S)
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_S  28
 
-/** SPI_MEM_MOSI_DLEN_REG register
+/** SPI1_MEM_S_MOSI_DLEN_REG register
  *  SPI1 send data bit length control register.
  */
-#define SPI_MEM_MOSI_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x24)
-/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_S_MOSI_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x24)
+/** SPI1_MEM_S_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of write-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_M  (SPI_MEM_USR_MOSI_DBITLEN_V << SPI_MEM_USR_MOSI_DBITLEN_S)
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+#define SPI1_MEM_S_USR_MOSI_DBITLEN    0x000003FFU
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_M  (SPI1_MEM_S_USR_MOSI_DBITLEN_V << SPI1_MEM_S_USR_MOSI_DBITLEN_S)
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_S  0
 
-/** SPI_MEM_MISO_DLEN_REG register
+/** SPI1_MEM_S_MISO_DLEN_REG register
  *  SPI1 receive data bit length control register.
  */
-#define SPI_MEM_MISO_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x28)
-/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_S_MISO_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x28)
+/** SPI1_MEM_S_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of  read-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_M  (SPI_MEM_USR_MISO_DBITLEN_V << SPI_MEM_USR_MISO_DBITLEN_S)
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
+#define SPI1_MEM_S_USR_MISO_DBITLEN    0x000003FFU
+#define SPI1_MEM_S_USR_MISO_DBITLEN_M  (SPI1_MEM_S_USR_MISO_DBITLEN_V << SPI1_MEM_S_USR_MISO_DBITLEN_S)
+#define SPI1_MEM_S_USR_MISO_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_S_USR_MISO_DBITLEN_S  0
 
-/** SPI_MEM_RD_STATUS_REG register
+/** SPI1_MEM_S_RD_STATUS_REG register
  *  SPI1 status register.
  */
-#define SPI_MEM_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c)
-/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
- *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+#define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c)
+/** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
+ *  The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit.
  */
-#define SPI_MEM_STATUS    0x0000FFFFU
-#define SPI_MEM_STATUS_M  (SPI_MEM_STATUS_V << SPI_MEM_STATUS_S)
-#define SPI_MEM_STATUS_V  0x0000FFFFU
-#define SPI_MEM_STATUS_S  0
-/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
- *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+#define SPI1_MEM_S_STATUS    0x0000FFFFU
+#define SPI1_MEM_S_STATUS_M  (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S)
+#define SPI1_MEM_S_STATUS_V  0x0000FFFFU
+#define SPI1_MEM_S_STATUS_S  0
+/** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi1_mem_s_fastrd_mode bit.
  */
-#define SPI_MEM_WB_MODE    0x000000FFU
-#define SPI_MEM_WB_MODE_M  (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
-#define SPI_MEM_WB_MODE_V  0x000000FFU
-#define SPI_MEM_WB_MODE_S  16
+#define SPI1_MEM_S_WB_MODE    0x000000FFU
+#define SPI1_MEM_S_WB_MODE_M  (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S)
+#define SPI1_MEM_S_WB_MODE_V  0x000000FFU
+#define SPI1_MEM_S_WB_MODE_S  16
 
-/** SPI_MEM_MISC_REG register
+/** SPI1_MEM_S_MISC_REG register
  *  SPI1 misc register
  */
-#define SPI_MEM_MISC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x34)
-/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x34)
+/** SPI1_MEM_S_CS0_DIS : R/W; bitpos: [0]; default: 0;
  *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (SPI_MEM_CS0_DIS_V << SPI_MEM_CS0_DIS_S)
-#define SPI_MEM_CS0_DIS_V  0x00000001U
-#define SPI_MEM_CS0_DIS_S  0
-/** SPI_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1;
+#define SPI1_MEM_S_CS0_DIS    (BIT(0))
+#define SPI1_MEM_S_CS0_DIS_M  (SPI1_MEM_S_CS0_DIS_V << SPI1_MEM_S_CS0_DIS_S)
+#define SPI1_MEM_S_CS0_DIS_V  0x00000001U
+#define SPI1_MEM_S_CS0_DIS_S  0
+/** SPI1_MEM_S_CS1_DIS : R/W; bitpos: [1]; default: 1;
  *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (SPI_MEM_CS1_DIS_V << SPI_MEM_CS1_DIS_S)
-#define SPI_MEM_CS1_DIS_V  0x00000001U
-#define SPI_MEM_CS1_DIS_S  1
-/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_S_CS1_DIS    (BIT(1))
+#define SPI1_MEM_S_CS1_DIS_M  (SPI1_MEM_S_CS1_DIS_V << SPI1_MEM_S_CS1_DIS_S)
+#define SPI1_MEM_S_CS1_DIS_V  0x00000001U
+#define SPI1_MEM_S_CS1_DIS_S  1
+/** SPI1_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
  *  1: spi clk line is high when idle     0: spi clk line is low when idle
  */
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S)
-#define SPI_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+#define SPI1_MEM_S_CK_IDLE_EDGE    (BIT(9))
+#define SPI1_MEM_S_CK_IDLE_EDGE_M  (SPI1_MEM_S_CK_IDLE_EDGE_V << SPI1_MEM_S_CK_IDLE_EDGE_S)
+#define SPI1_MEM_S_CK_IDLE_EDGE_V  0x00000001U
+#define SPI1_MEM_S_CK_IDLE_EDGE_S  9
+/** SPI1_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
  *  spi cs line keep low when the bit is set.
  */
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S)
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+#define SPI1_MEM_S_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_M  (SPI1_MEM_S_CS_KEEP_ACTIVE_V << SPI1_MEM_S_CS_KEEP_ACTIVE_S)
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_S  10
 
-/** SPI_MEM_TX_CRC_REG register
+/** SPI1_MEM_S_TX_CRC_REG register
  *  SPI1 TX CRC data register.
  */
-#define SPI_MEM_TX_CRC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x38)
-/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
+#define SPI1_MEM_S_TX_CRC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x38)
+/** SPI1_MEM_S_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
  *  For SPI1, the value of crc32.
  */
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_M  (SPI_MEM_TX_CRC_DATA_V << SPI_MEM_TX_CRC_DATA_S)
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_S  0
+#define SPI1_MEM_S_TX_CRC_DATA    0xFFFFFFFFU
+#define SPI1_MEM_S_TX_CRC_DATA_M  (SPI1_MEM_S_TX_CRC_DATA_V << SPI1_MEM_S_TX_CRC_DATA_S)
+#define SPI1_MEM_S_TX_CRC_DATA_V  0xFFFFFFFFU
+#define SPI1_MEM_S_TX_CRC_DATA_S  0
 
-/** SPI_MEM_CACHE_FCTRL_REG register
+/** SPI1_MEM_S_CACHE_FCTRL_REG register
  *  SPI1 bit mode control register.
  */
-#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c)
-/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c)
+/** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
  *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
  */
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S)
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x00000001U
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M  (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S)
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V  0x00000001U
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S  1
+/** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
  *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
- *  spi_mem_fread_dio.
+ *  spi1_mem_s_fread_dio.
  */
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S)
-#define SPI_MEM_FDIN_DUAL_V  0x00000001U
-#define SPI_MEM_FDIN_DUAL_S  3
-/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FDIN_DUAL    (BIT(3))
+#define SPI1_MEM_S_FDIN_DUAL_M  (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S)
+#define SPI1_MEM_S_FDIN_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FDIN_DUAL_S  3
+/** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
  *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_s_fread_dio.
  */
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S)
-#define SPI_MEM_FDOUT_DUAL_V  0x00000001U
-#define SPI_MEM_FDOUT_DUAL_S  4
-/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_S_FDOUT_DUAL    (BIT(4))
+#define SPI1_MEM_S_FDOUT_DUAL_M  (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S)
+#define SPI1_MEM_S_FDOUT_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_DUAL_S  4
+/** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
  *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_s_fread_dio.
  */
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S)
-#define SPI_MEM_FADDR_DUAL_V  0x00000001U
-#define SPI_MEM_FADDR_DUAL_S  5
-/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
+#define SPI1_MEM_S_FADDR_DUAL    (BIT(5))
+#define SPI1_MEM_S_FADDR_DUAL_M  (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S)
+#define SPI1_MEM_S_FADDR_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FADDR_DUAL_S  5
+/** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
  *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_s_fread_qio.
  */
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S)
-#define SPI_MEM_FDIN_QUAD_V  0x00000001U
-#define SPI_MEM_FDIN_QUAD_S  6
-/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_S_FDIN_QUAD    (BIT(6))
+#define SPI1_MEM_S_FDIN_QUAD_M  (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S)
+#define SPI1_MEM_S_FDIN_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FDIN_QUAD_S  6
+/** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
  *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_s_fread_qio.
  */
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S)
-#define SPI_MEM_FDOUT_QUAD_V  0x00000001U
-#define SPI_MEM_FDOUT_QUAD_S  7
-/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_S_FDOUT_QUAD    (BIT(7))
+#define SPI1_MEM_S_FDOUT_QUAD_M  (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S)
+#define SPI1_MEM_S_FDOUT_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_QUAD_S  7
+/** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
  *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_s_fread_qio.
  */
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S)
-#define SPI_MEM_FADDR_QUAD_V  0x00000001U
-#define SPI_MEM_FADDR_QUAD_S  8
+#define SPI1_MEM_S_FADDR_QUAD    (BIT(8))
+#define SPI1_MEM_S_FADDR_QUAD_M  (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S)
+#define SPI1_MEM_S_FADDR_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FADDR_QUAD_S  8
 
-/** SPI_MEM_W0_REG register
+/** SPI1_MEM_S_W0_REG register
  *  SPI1 memory data buffer0
  */
-#define SPI_MEM_W0_REG (DR_REG_PSRAM_MSPI1_BASE + 0x58)
-/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W0_REG (DR_REG_PSRAM_MSPI1_BASE + 0x58)
+/** SPI1_MEM_S_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF0    0xFFFFFFFFU
-#define SPI_MEM_BUF0_M  (SPI_MEM_BUF0_V << SPI_MEM_BUF0_S)
-#define SPI_MEM_BUF0_V  0xFFFFFFFFU
-#define SPI_MEM_BUF0_S  0
+#define SPI1_MEM_S_BUF0    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF0_M  (SPI1_MEM_S_BUF0_V << SPI1_MEM_S_BUF0_S)
+#define SPI1_MEM_S_BUF0_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF0_S  0
 
-/** SPI_MEM_W1_REG register
+/** SPI1_MEM_S_W1_REG register
  *  SPI1 memory data buffer1
  */
-#define SPI_MEM_W1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x5c)
-/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x5c)
+/** SPI1_MEM_S_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF1    0xFFFFFFFFU
-#define SPI_MEM_BUF1_M  (SPI_MEM_BUF1_V << SPI_MEM_BUF1_S)
-#define SPI_MEM_BUF1_V  0xFFFFFFFFU
-#define SPI_MEM_BUF1_S  0
+#define SPI1_MEM_S_BUF1    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF1_M  (SPI1_MEM_S_BUF1_V << SPI1_MEM_S_BUF1_S)
+#define SPI1_MEM_S_BUF1_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF1_S  0
 
-/** SPI_MEM_W2_REG register
+/** SPI1_MEM_S_W2_REG register
  *  SPI1 memory data buffer2
  */
-#define SPI_MEM_W2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x60)
-/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x60)
+/** SPI1_MEM_S_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF2    0xFFFFFFFFU
-#define SPI_MEM_BUF2_M  (SPI_MEM_BUF2_V << SPI_MEM_BUF2_S)
-#define SPI_MEM_BUF2_V  0xFFFFFFFFU
-#define SPI_MEM_BUF2_S  0
+#define SPI1_MEM_S_BUF2    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF2_M  (SPI1_MEM_S_BUF2_V << SPI1_MEM_S_BUF2_S)
+#define SPI1_MEM_S_BUF2_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF2_S  0
 
-/** SPI_MEM_W3_REG register
+/** SPI1_MEM_S_W3_REG register
  *  SPI1 memory data buffer3
  */
-#define SPI_MEM_W3_REG (DR_REG_PSRAM_MSPI1_BASE + 0x64)
-/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W3_REG (DR_REG_PSRAM_MSPI1_BASE + 0x64)
+/** SPI1_MEM_S_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF3    0xFFFFFFFFU
-#define SPI_MEM_BUF3_M  (SPI_MEM_BUF3_V << SPI_MEM_BUF3_S)
-#define SPI_MEM_BUF3_V  0xFFFFFFFFU
-#define SPI_MEM_BUF3_S  0
+#define SPI1_MEM_S_BUF3    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF3_M  (SPI1_MEM_S_BUF3_V << SPI1_MEM_S_BUF3_S)
+#define SPI1_MEM_S_BUF3_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF3_S  0
 
-/** SPI_MEM_W4_REG register
+/** SPI1_MEM_S_W4_REG register
  *  SPI1 memory data buffer4
  */
-#define SPI_MEM_W4_REG (DR_REG_PSRAM_MSPI1_BASE + 0x68)
-/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W4_REG (DR_REG_PSRAM_MSPI1_BASE + 0x68)
+/** SPI1_MEM_S_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF4    0xFFFFFFFFU
-#define SPI_MEM_BUF4_M  (SPI_MEM_BUF4_V << SPI_MEM_BUF4_S)
-#define SPI_MEM_BUF4_V  0xFFFFFFFFU
-#define SPI_MEM_BUF4_S  0
+#define SPI1_MEM_S_BUF4    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF4_M  (SPI1_MEM_S_BUF4_V << SPI1_MEM_S_BUF4_S)
+#define SPI1_MEM_S_BUF4_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF4_S  0
 
-/** SPI_MEM_W5_REG register
+/** SPI1_MEM_S_W5_REG register
  *  SPI1 memory data buffer5
  */
-#define SPI_MEM_W5_REG (DR_REG_PSRAM_MSPI1_BASE + 0x6c)
-/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W5_REG (DR_REG_PSRAM_MSPI1_BASE + 0x6c)
+/** SPI1_MEM_S_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF5    0xFFFFFFFFU
-#define SPI_MEM_BUF5_M  (SPI_MEM_BUF5_V << SPI_MEM_BUF5_S)
-#define SPI_MEM_BUF5_V  0xFFFFFFFFU
-#define SPI_MEM_BUF5_S  0
+#define SPI1_MEM_S_BUF5    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF5_M  (SPI1_MEM_S_BUF5_V << SPI1_MEM_S_BUF5_S)
+#define SPI1_MEM_S_BUF5_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF5_S  0
 
-/** SPI_MEM_W6_REG register
+/** SPI1_MEM_S_W6_REG register
  *  SPI1 memory data buffer6
  */
-#define SPI_MEM_W6_REG (DR_REG_PSRAM_MSPI1_BASE + 0x70)
-/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W6_REG (DR_REG_PSRAM_MSPI1_BASE + 0x70)
+/** SPI1_MEM_S_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF6    0xFFFFFFFFU
-#define SPI_MEM_BUF6_M  (SPI_MEM_BUF6_V << SPI_MEM_BUF6_S)
-#define SPI_MEM_BUF6_V  0xFFFFFFFFU
-#define SPI_MEM_BUF6_S  0
+#define SPI1_MEM_S_BUF6    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF6_M  (SPI1_MEM_S_BUF6_V << SPI1_MEM_S_BUF6_S)
+#define SPI1_MEM_S_BUF6_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF6_S  0
 
-/** SPI_MEM_W7_REG register
+/** SPI1_MEM_S_W7_REG register
  *  SPI1 memory data buffer7
  */
-#define SPI_MEM_W7_REG (DR_REG_PSRAM_MSPI1_BASE + 0x74)
-/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W7_REG (DR_REG_PSRAM_MSPI1_BASE + 0x74)
+/** SPI1_MEM_S_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF7    0xFFFFFFFFU
-#define SPI_MEM_BUF7_M  (SPI_MEM_BUF7_V << SPI_MEM_BUF7_S)
-#define SPI_MEM_BUF7_V  0xFFFFFFFFU
-#define SPI_MEM_BUF7_S  0
+#define SPI1_MEM_S_BUF7    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF7_M  (SPI1_MEM_S_BUF7_V << SPI1_MEM_S_BUF7_S)
+#define SPI1_MEM_S_BUF7_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF7_S  0
 
-/** SPI_MEM_W8_REG register
+/** SPI1_MEM_S_W8_REG register
  *  SPI1 memory data buffer8
  */
-#define SPI_MEM_W8_REG (DR_REG_PSRAM_MSPI1_BASE + 0x78)
-/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W8_REG (DR_REG_PSRAM_MSPI1_BASE + 0x78)
+/** SPI1_MEM_S_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF8    0xFFFFFFFFU
-#define SPI_MEM_BUF8_M  (SPI_MEM_BUF8_V << SPI_MEM_BUF8_S)
-#define SPI_MEM_BUF8_V  0xFFFFFFFFU
-#define SPI_MEM_BUF8_S  0
+#define SPI1_MEM_S_BUF8    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF8_M  (SPI1_MEM_S_BUF8_V << SPI1_MEM_S_BUF8_S)
+#define SPI1_MEM_S_BUF8_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF8_S  0
 
-/** SPI_MEM_W9_REG register
+/** SPI1_MEM_S_W9_REG register
  *  SPI1 memory data buffer9
  */
-#define SPI_MEM_W9_REG (DR_REG_PSRAM_MSPI1_BASE + 0x7c)
-/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W9_REG (DR_REG_PSRAM_MSPI1_BASE + 0x7c)
+/** SPI1_MEM_S_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF9    0xFFFFFFFFU
-#define SPI_MEM_BUF9_M  (SPI_MEM_BUF9_V << SPI_MEM_BUF9_S)
-#define SPI_MEM_BUF9_V  0xFFFFFFFFU
-#define SPI_MEM_BUF9_S  0
+#define SPI1_MEM_S_BUF9    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF9_M  (SPI1_MEM_S_BUF9_V << SPI1_MEM_S_BUF9_S)
+#define SPI1_MEM_S_BUF9_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF9_S  0
 
-/** SPI_MEM_W10_REG register
+/** SPI1_MEM_S_W10_REG register
  *  SPI1 memory data buffer10
  */
-#define SPI_MEM_W10_REG (DR_REG_PSRAM_MSPI1_BASE + 0x80)
-/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W10_REG (DR_REG_PSRAM_MSPI1_BASE + 0x80)
+/** SPI1_MEM_S_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF10    0xFFFFFFFFU
-#define SPI_MEM_BUF10_M  (SPI_MEM_BUF10_V << SPI_MEM_BUF10_S)
-#define SPI_MEM_BUF10_V  0xFFFFFFFFU
-#define SPI_MEM_BUF10_S  0
+#define SPI1_MEM_S_BUF10    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF10_M  (SPI1_MEM_S_BUF10_V << SPI1_MEM_S_BUF10_S)
+#define SPI1_MEM_S_BUF10_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF10_S  0
 
-/** SPI_MEM_W11_REG register
+/** SPI1_MEM_S_W11_REG register
  *  SPI1 memory data buffer11
  */
-#define SPI_MEM_W11_REG (DR_REG_PSRAM_MSPI1_BASE + 0x84)
-/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W11_REG (DR_REG_PSRAM_MSPI1_BASE + 0x84)
+/** SPI1_MEM_S_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF11    0xFFFFFFFFU
-#define SPI_MEM_BUF11_M  (SPI_MEM_BUF11_V << SPI_MEM_BUF11_S)
-#define SPI_MEM_BUF11_V  0xFFFFFFFFU
-#define SPI_MEM_BUF11_S  0
+#define SPI1_MEM_S_BUF11    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF11_M  (SPI1_MEM_S_BUF11_V << SPI1_MEM_S_BUF11_S)
+#define SPI1_MEM_S_BUF11_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF11_S  0
 
-/** SPI_MEM_W12_REG register
+/** SPI1_MEM_S_W12_REG register
  *  SPI1 memory data buffer12
  */
-#define SPI_MEM_W12_REG (DR_REG_PSRAM_MSPI1_BASE + 0x88)
-/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W12_REG (DR_REG_PSRAM_MSPI1_BASE + 0x88)
+/** SPI1_MEM_S_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF12    0xFFFFFFFFU
-#define SPI_MEM_BUF12_M  (SPI_MEM_BUF12_V << SPI_MEM_BUF12_S)
-#define SPI_MEM_BUF12_V  0xFFFFFFFFU
-#define SPI_MEM_BUF12_S  0
+#define SPI1_MEM_S_BUF12    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF12_M  (SPI1_MEM_S_BUF12_V << SPI1_MEM_S_BUF12_S)
+#define SPI1_MEM_S_BUF12_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF12_S  0
 
-/** SPI_MEM_W13_REG register
+/** SPI1_MEM_S_W13_REG register
  *  SPI1 memory data buffer13
  */
-#define SPI_MEM_W13_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8c)
-/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W13_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8c)
+/** SPI1_MEM_S_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF13    0xFFFFFFFFU
-#define SPI_MEM_BUF13_M  (SPI_MEM_BUF13_V << SPI_MEM_BUF13_S)
-#define SPI_MEM_BUF13_V  0xFFFFFFFFU
-#define SPI_MEM_BUF13_S  0
+#define SPI1_MEM_S_BUF13    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF13_M  (SPI1_MEM_S_BUF13_V << SPI1_MEM_S_BUF13_S)
+#define SPI1_MEM_S_BUF13_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF13_S  0
 
-/** SPI_MEM_W14_REG register
+/** SPI1_MEM_S_W14_REG register
  *  SPI1 memory data buffer14
  */
-#define SPI_MEM_W14_REG (DR_REG_PSRAM_MSPI1_BASE + 0x90)
-/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W14_REG (DR_REG_PSRAM_MSPI1_BASE + 0x90)
+/** SPI1_MEM_S_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF14    0xFFFFFFFFU
-#define SPI_MEM_BUF14_M  (SPI_MEM_BUF14_V << SPI_MEM_BUF14_S)
-#define SPI_MEM_BUF14_V  0xFFFFFFFFU
-#define SPI_MEM_BUF14_S  0
+#define SPI1_MEM_S_BUF14    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF14_M  (SPI1_MEM_S_BUF14_V << SPI1_MEM_S_BUF14_S)
+#define SPI1_MEM_S_BUF14_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF14_S  0
 
-/** SPI_MEM_W15_REG register
+/** SPI1_MEM_S_W15_REG register
  *  SPI1 memory data buffer15
  */
-#define SPI_MEM_W15_REG (DR_REG_PSRAM_MSPI1_BASE + 0x94)
-/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W15_REG (DR_REG_PSRAM_MSPI1_BASE + 0x94)
+/** SPI1_MEM_S_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF15    0xFFFFFFFFU
-#define SPI_MEM_BUF15_M  (SPI_MEM_BUF15_V << SPI_MEM_BUF15_S)
-#define SPI_MEM_BUF15_V  0xFFFFFFFFU
-#define SPI_MEM_BUF15_S  0
+#define SPI1_MEM_S_BUF15    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF15_M  (SPI1_MEM_S_BUF15_V << SPI1_MEM_S_BUF15_S)
+#define SPI1_MEM_S_BUF15_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF15_S  0
 
-/** SPI_MEM_FLASH_WAITI_CTRL_REG register
+/** SPI1_MEM_S_FLASH_WAITI_CTRL_REG register
  *  SPI1 wait idle control register
  */
-#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x98)
-/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_S_FLASH_WAITI_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x98)
+/** SPI1_MEM_S_WAITI_EN : R/W; bitpos: [0]; default: 1;
  *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
  *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
  *  Suspend/Resume are not supported.
  */
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (SPI_MEM_WAITI_EN_V << SPI_MEM_WAITI_EN_S)
-#define SPI_MEM_WAITI_EN_V  0x00000001U
-#define SPI_MEM_WAITI_EN_S  0
-/** SPI_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_WAITI_EN    (BIT(0))
+#define SPI1_MEM_S_WAITI_EN_M  (SPI1_MEM_S_WAITI_EN_V << SPI1_MEM_S_WAITI_EN_S)
+#define SPI1_MEM_S_WAITI_EN_V  0x00000001U
+#define SPI1_MEM_S_WAITI_EN_S  0
+/** SPI1_MEM_S_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
  *  The dummy phase enable when wait flash idle (RDSR)
  */
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (SPI_MEM_WAITI_DUMMY_V << SPI_MEM_WAITI_DUMMY_S)
-#define SPI_MEM_WAITI_DUMMY_V  0x00000001U
-#define SPI_MEM_WAITI_DUMMY_S  1
-/** SPI_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
+#define SPI1_MEM_S_WAITI_DUMMY    (BIT(1))
+#define SPI1_MEM_S_WAITI_DUMMY_M  (SPI1_MEM_S_WAITI_DUMMY_V << SPI1_MEM_S_WAITI_DUMMY_S)
+#define SPI1_MEM_S_WAITI_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_WAITI_DUMMY_S  1
+/** SPI1_MEM_S_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
  *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
  *  address in RDSR or read SUS command transfer.
  */
-#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_M  (SPI_MEM_WAITI_ADDR_EN_V << SPI_MEM_WAITI_ADDR_EN_S)
-#define SPI_MEM_WAITI_ADDR_EN_V  0x00000001U
-#define SPI_MEM_WAITI_ADDR_EN_S  2
-/** SPI_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
- *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
- *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
- *  SPI_MEM_WAITI_ADDR_EN is cleared.
+#define SPI1_MEM_S_WAITI_ADDR_EN    (BIT(2))
+#define SPI1_MEM_S_WAITI_ADDR_EN_M  (SPI1_MEM_S_WAITI_ADDR_EN_V << SPI1_MEM_S_WAITI_ADDR_EN_S)
+#define SPI1_MEM_S_WAITI_ADDR_EN_V  0x00000001U
+#define SPI1_MEM_S_WAITI_ADDR_EN_S  2
+/** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
+ *  When SPI1_MEM_S_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+ *  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+ *  SPI1_MEM_S_WAITI_ADDR_EN is cleared.
  */
-#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  (SPI_MEM_WAITI_ADDR_CYCLELEN_V << SPI_MEM_WAITI_ADDR_CYCLELEN_S)
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
-/** SPI_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN    0x00000003U
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S)
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V  0x00000003U
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S  3
+/** SPI1_MEM_S_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
  *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
  */
-#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_M  (SPI_MEM_WAITI_CMD_2B_V << SPI_MEM_WAITI_CMD_2B_S)
-#define SPI_MEM_WAITI_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAITI_CMD_2B_S  9
-/** SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
+#define SPI1_MEM_S_WAITI_CMD_2B    (BIT(9))
+#define SPI1_MEM_S_WAITI_CMD_2B_M  (SPI1_MEM_S_WAITI_CMD_2B_V << SPI1_MEM_S_WAITI_CMD_2B_S)
+#define SPI1_MEM_S_WAITI_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_WAITI_CMD_2B_S  9
+/** SPI1_MEM_S_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
  *  The dummy cycle length when wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  (SPI_MEM_WAITI_DUMMY_CYCLELEN_V << SPI_MEM_WAITI_DUMMY_CYCLELEN_S)
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/** SPI_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_M  (SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S  10
+/** SPI1_MEM_S_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
  *  The command value to wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_CMD    0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_M  (SPI_MEM_WAITI_CMD_V << SPI_MEM_WAITI_CMD_S)
-#define SPI_MEM_WAITI_CMD_V  0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_S  16
+#define SPI1_MEM_S_WAITI_CMD    0x0000FFFFU
+#define SPI1_MEM_S_WAITI_CMD_M  (SPI1_MEM_S_WAITI_CMD_V << SPI1_MEM_S_WAITI_CMD_S)
+#define SPI1_MEM_S_WAITI_CMD_V  0x0000FFFFU
+#define SPI1_MEM_S_WAITI_CMD_S  16
 
-/** SPI_MEM_FLASH_SUS_CTRL_REG register
+/** SPI1_MEM_S_FLASH_SUS_CTRL_REG register
  *  SPI1 flash suspend control register
  */
-#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x9c)
-/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_FLASH_SUS_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x9c)
+/** SPI1_MEM_S_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
  *  program erase resume bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (SPI_MEM_FLASH_PER_V << SPI_MEM_FLASH_PER_S)
-#define SPI_MEM_FLASH_PER_V  0x00000001U
-#define SPI_MEM_FLASH_PER_S  0
-/** SPI_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_FLASH_PER    (BIT(0))
+#define SPI1_MEM_S_FLASH_PER_M  (SPI1_MEM_S_FLASH_PER_V << SPI1_MEM_S_FLASH_PER_S)
+#define SPI1_MEM_S_FLASH_PER_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_S  0
+/** SPI1_MEM_S_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
  *  program erase suspend bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (SPI_MEM_FLASH_PES_V << SPI_MEM_FLASH_PES_S)
-#define SPI_MEM_FLASH_PES_V  0x00000001U
-#define SPI_MEM_FLASH_PES_S  1
-/** SPI_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_S_FLASH_PES    (BIT(1))
+#define SPI1_MEM_S_FLASH_PES_M  (SPI1_MEM_S_FLASH_PES_V << SPI1_MEM_S_FLASH_PES_S)
+#define SPI1_MEM_S_FLASH_PES_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_S  1
+/** SPI1_MEM_S_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase resume command is sent. 0: SPI1 does not wait after program erase
  *  resume command is sent.
  */
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (SPI_MEM_FLASH_PER_WAIT_EN_V << SPI_MEM_FLASH_PER_WAIT_EN_S)
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/** SPI_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_M  (SPI1_MEM_S_FLASH_PER_WAIT_EN_V << SPI1_MEM_S_FLASH_PER_WAIT_EN_S)
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_S  2
+/** SPI1_MEM_S_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
  *  suspend command is sent.
  */
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (SPI_MEM_FLASH_PES_WAIT_EN_V << SPI_MEM_FLASH_PES_WAIT_EN_S)
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/** SPI_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_M  (SPI1_MEM_S_FLASH_PES_WAIT_EN_V << SPI1_MEM_S_FLASH_PES_WAIT_EN_S)
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_S  3
+/** SPI1_MEM_S_PES_PER_EN : R/W; bitpos: [4]; default: 0;
  *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
  *  application should send PER after PES is done.
  */
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (SPI_MEM_PES_PER_EN_V << SPI_MEM_PES_PER_EN_S)
-#define SPI_MEM_PES_PER_EN_V  0x00000001U
-#define SPI_MEM_PES_PER_EN_S  4
-/** SPI_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_S_PES_PER_EN    (BIT(4))
+#define SPI1_MEM_S_PES_PER_EN_M  (SPI1_MEM_S_PES_PER_EN_V << SPI1_MEM_S_PES_PER_EN_S)
+#define SPI1_MEM_S_PES_PER_EN_V  0x00000001U
+#define SPI1_MEM_S_PES_PER_EN_S  4
+/** SPI1_MEM_S_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
  *  Set this bit to enable Auto-suspending function.
  */
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (SPI_MEM_FLASH_PES_EN_V << SPI_MEM_FLASH_PES_EN_S)
-#define SPI_MEM_FLASH_PES_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_EN_S  5
-/** SPI_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
+#define SPI1_MEM_S_FLASH_PES_EN    (BIT(5))
+#define SPI1_MEM_S_FLASH_PES_EN_M  (SPI1_MEM_S_FLASH_PES_EN_V << SPI1_MEM_S_FLASH_PES_EN_S)
+#define SPI1_MEM_S_FLASH_PES_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_EN_S  5
+/** SPI1_MEM_S_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
  *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
  *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
  *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
- *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+ *  status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0].
  */
-#define SPI_MEM_PESR_END_MSK    0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_M  (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S)
-#define SPI_MEM_PESR_END_MSK_V  0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_S  6
-/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_S_PESR_END_MSK    0x0000FFFFU
+#define SPI1_MEM_S_PESR_END_MSK_M  (SPI1_MEM_S_PESR_END_MSK_V << SPI1_MEM_S_PESR_END_MSK_S)
+#define SPI1_MEM_S_PESR_END_MSK_V  0x0000FFFFU
+#define SPI1_MEM_S_PESR_END_MSK_S  6
+/** SPI1_MEM_S_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
  *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
  *  check flash SUS/SUS1/SUS2 status bit
  */
-#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S)
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x00000001U
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_S_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_M  (SPI1_MEM_S_FMEM_RD_SUS_2B_V << SPI1_MEM_S_FMEM_RD_SUS_2B_S)
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_V  0x00000001U
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_S  22
+/** SPI1_MEM_S_PER_END_EN : R/W; bitpos: [23]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
  *  flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (SPI_MEM_PER_END_EN_V << SPI_MEM_PER_END_EN_S)
-#define SPI_MEM_PER_END_EN_V  0x00000001U
-#define SPI_MEM_PER_END_EN_S  23
-/** SPI_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_PER_END_EN    (BIT(23))
+#define SPI1_MEM_S_PER_END_EN_M  (SPI1_MEM_S_PER_END_EN_V << SPI1_MEM_S_PER_END_EN_S)
+#define SPI1_MEM_S_PER_END_EN_V  0x00000001U
+#define SPI1_MEM_S_PER_END_EN_S  23
+/** SPI1_MEM_S_PES_END_EN : R/W; bitpos: [24]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
  *  of flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (SPI_MEM_PES_END_EN_V << SPI_MEM_PES_END_EN_S)
-#define SPI_MEM_PES_END_EN_V  0x00000001U
-#define SPI_MEM_PES_END_EN_S  24
-/** SPI_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
- *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+#define SPI1_MEM_S_PES_END_EN    (BIT(24))
+#define SPI1_MEM_S_PES_END_EN_M  (SPI1_MEM_S_PES_END_EN_V << SPI1_MEM_S_PES_END_EN_S)
+#define SPI1_MEM_S_PES_END_EN_V  0x00000001U
+#define SPI1_MEM_S_PES_END_EN_S  24
+/** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
+ *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it
  *  will be treated as check pass.
  */
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  (SPI_MEM_SUS_TIMEOUT_CNT_V << SPI_MEM_SUS_TIMEOUT_CNT_S)
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT    0x0000007FU
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_M  (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S)
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_V  0x0000007FU
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_S  25
 
-/** SPI_MEM_FLASH_SUS_CMD_REG register
+/** SPI1_MEM_S_FLASH_SUS_CMD_REG register
  *  SPI1 flash suspend command register
  */
-#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa0)
-/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
+#define SPI1_MEM_S_FLASH_SUS_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa0)
+/** SPI1_MEM_S_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
  *  Program/Erase suspend command.
  */
-#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_M  (SPI_MEM_FLASH_PES_COMMAND_V << SPI_MEM_FLASH_PES_COMMAND_S)
-#define SPI_MEM_FLASH_PES_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_S  0
-/** SPI_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_S_FLASH_PES_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PES_COMMAND_M  (SPI1_MEM_S_FLASH_PES_COMMAND_V << SPI1_MEM_S_FLASH_PES_COMMAND_S)
+#define SPI1_MEM_S_FLASH_PES_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PES_COMMAND_S  0
+/** SPI1_MEM_S_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
  *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
  *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
  */
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_M  (SPI_MEM_WAIT_PESR_COMMAND_V << SPI_MEM_WAIT_PESR_COMMAND_S)
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+#define SPI1_MEM_S_WAIT_PESR_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_M  (SPI1_MEM_S_WAIT_PESR_COMMAND_V << SPI1_MEM_S_WAIT_PESR_COMMAND_S)
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_S  16
 
-/** SPI_MEM_SUS_STATUS_REG register
+/** SPI1_MEM_S_SUS_STATUS_REG register
  *  SPI1 flash suspend status register
  */
-#define SPI_MEM_SUS_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa4)
-/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_SUS_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa4)
+/** SPI1_MEM_S_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
  *  The status of flash suspend, only used in SPI1.
  */
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (SPI_MEM_FLASH_SUS_V << SPI_MEM_FLASH_SUS_S)
-#define SPI_MEM_FLASH_SUS_V  0x00000001U
-#define SPI_MEM_FLASH_SUS_S  0
-/** SPI_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
- *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+#define SPI1_MEM_S_FLASH_SUS    (BIT(0))
+#define SPI1_MEM_S_FLASH_SUS_M  (SPI1_MEM_S_FLASH_SUS_V << SPI1_MEM_S_FLASH_SUS_S)
+#define SPI1_MEM_S_FLASH_SUS_V  0x00000001U
+#define SPI1_MEM_S_FLASH_SUS_S  0
+/** SPI1_MEM_S_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
+ *  1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ *  SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
  */
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (SPI_MEM_WAIT_PESR_CMD_2B_V << SPI_MEM_WAIT_PESR_CMD_2B_S)
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/** SPI_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_M  (SPI1_MEM_S_WAIT_PESR_CMD_2B_V << SPI1_MEM_S_WAIT_PESR_CMD_2B_S)
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_S  1
+/** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after HPM command is sent.
  */
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (SPI_MEM_FLASH_HPM_DLY_128_V << SPI_MEM_FLASH_HPM_DLY_128_S)
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/** SPI_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_S_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_M  (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S)
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_S  2
+/** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after RES command is sent.
  */
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (SPI_MEM_FLASH_RES_DLY_128_V << SPI_MEM_FLASH_RES_DLY_128_S)
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/** SPI_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_S_FLASH_RES_DLY_128    (BIT(3))
+#define SPI1_MEM_S_FLASH_RES_DLY_128_M  (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S)
+#define SPI1_MEM_S_FLASH_RES_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RES_DLY_128_S  3
+/** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after DP command is sent.
  */
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (SPI_MEM_FLASH_DP_DLY_128_V << SPI_MEM_FLASH_DP_DLY_128_S)
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/** SPI_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
- *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+#define SPI1_MEM_S_FLASH_DP_DLY_128    (BIT(4))
+#define SPI1_MEM_S_FLASH_DP_DLY_128_M  (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S)
+#define SPI1_MEM_S_FLASH_DP_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_DP_DLY_128_S  4
+/** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
+ *  Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (SPI_MEM_FLASH_PER_DLY_128_V << SPI_MEM_FLASH_PER_DLY_128_S)
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/** SPI_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
- *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+#define SPI1_MEM_S_FLASH_PER_DLY_128    (BIT(5))
+#define SPI1_MEM_S_FLASH_PER_DLY_128_M  (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S)
+#define SPI1_MEM_S_FLASH_PER_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_DLY_128_S  5
+/** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
+ *  Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (SPI_MEM_FLASH_PES_DLY_128_V << SPI_MEM_FLASH_PES_DLY_128_S)
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/** SPI_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_S_FLASH_PES_DLY_128    (BIT(6))
+#define SPI1_MEM_S_FLASH_PES_DLY_128_M  (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S)
+#define SPI1_MEM_S_FLASH_PES_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_DLY_128_S  6
+/** SPI1_MEM_S_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
  *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
  */
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (SPI_MEM_SPI0_LOCK_EN_V << SPI_MEM_SPI0_LOCK_EN_S)
-#define SPI_MEM_SPI0_LOCK_EN_V  0x00000001U
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/** SPI_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_S_SPI0_LOCK_EN    (BIT(7))
+#define SPI1_MEM_S_SPI0_LOCK_EN_M  (SPI1_MEM_S_SPI0_LOCK_EN_V << SPI1_MEM_S_SPI0_LOCK_EN_S)
+#define SPI1_MEM_S_SPI0_LOCK_EN_V  0x00000001U
+#define SPI1_MEM_S_SPI0_LOCK_EN_S  7
+/** SPI1_MEM_S_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
  *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
  *  of Program/Erase Suspend/Resume command is 8.
  */
-#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_M  (SPI_MEM_FLASH_PESR_CMD_2B_V << SPI_MEM_FLASH_PESR_CMD_2B_S)
-#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
-/** SPI_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_M  (SPI1_MEM_S_FLASH_PESR_CMD_2B_V << SPI1_MEM_S_FLASH_PESR_CMD_2B_S)
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_S  15
+/** SPI1_MEM_S_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
  *  Program/Erase resume command.
  */
-#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_M  (SPI_MEM_FLASH_PER_COMMAND_V << SPI_MEM_FLASH_PER_COMMAND_S)
-#define SPI_MEM_FLASH_PER_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_S  16
+#define SPI1_MEM_S_FLASH_PER_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PER_COMMAND_M  (SPI1_MEM_S_FLASH_PER_COMMAND_V << SPI1_MEM_S_FLASH_PER_COMMAND_S)
+#define SPI1_MEM_S_FLASH_PER_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PER_COMMAND_S  16
 
-/** SPI_MEM_INT_ENA_REG register
+/** SPI1_MEM_S_INT_ENA_REG register
  *  SPI1 interrupt enable register
  */
-#define SPI_MEM_INT_ENA_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc0)
-/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_MEM_PER_END_INT interrupt.
+#define SPI1_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc0)
+/** SPI1_MEM_S_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI1_MEM_S_PER_END_INT interrupt.
  */
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (SPI_MEM_PER_END_INT_ENA_V << SPI_MEM_PER_END_INT_ENA_S)
-#define SPI_MEM_PER_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ENA_S  0
-/** SPI_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_MEM_PES_END_INT interrupt.
+#define SPI1_MEM_S_PER_END_INT_ENA    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_ENA_M  (SPI1_MEM_S_PER_END_INT_ENA_V << SPI1_MEM_S_PER_END_INT_ENA_S)
+#define SPI1_MEM_S_PER_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_ENA_S  0
+/** SPI1_MEM_S_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI1_MEM_S_PES_END_INT interrupt.
  */
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (SPI_MEM_PES_END_INT_ENA_V << SPI_MEM_PES_END_INT_ENA_S)
-#define SPI_MEM_PES_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/** SPI_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+#define SPI1_MEM_S_PES_END_INT_ENA    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_ENA_M  (SPI1_MEM_S_PES_END_INT_ENA_V << SPI1_MEM_S_PES_END_INT_ENA_S)
+#define SPI1_MEM_S_PES_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_ENA_S  1
+/** SPI1_MEM_S_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI1_MEM_S_WPE_END_INT interrupt.
  */
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (SPI_MEM_WPE_END_INT_ENA_V << SPI_MEM_WPE_END_INT_ENA_S)
-#define SPI_MEM_WPE_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI1_MEM_S_WPE_END_INT_ENA    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_ENA_M  (SPI1_MEM_S_WPE_END_INT_ENA_V << SPI1_MEM_S_WPE_END_INT_ENA_S)
+#define SPI1_MEM_S_WPE_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_ENA_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_M  (SPI1_MEM_S_SLV_ST_END_INT_ENA_V << SPI1_MEM_S_SLV_ST_END_INT_ENA_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S)
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
+#define SPI1_MEM_S_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_M  (SPI1_MEM_S_MST_ST_END_INT_ENA_V << SPI1_MEM_S_MST_ST_END_INT_ENA_S)
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
  */
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (SPI_MEM_BROWN_OUT_INT_ENA_V << SPI_MEM_BROWN_OUT_INT_ENA_S)
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_M  (SPI1_MEM_S_BROWN_OUT_INT_ENA_V << SPI1_MEM_S_BROWN_OUT_INT_ENA_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_S  10
 
-/** SPI_MEM_INT_CLR_REG register
+/** SPI1_MEM_S_INT_CLR_REG register
  *  SPI1 interrupt clear register
  */
-#define SPI_MEM_INT_CLR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc4)
-/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_MEM_PER_END_INT interrupt.
+#define SPI1_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc4)
+/** SPI1_MEM_S_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI1_MEM_S_PER_END_INT interrupt.
  */
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (SPI_MEM_PER_END_INT_CLR_V << SPI_MEM_PER_END_INT_CLR_S)
-#define SPI_MEM_PER_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PER_END_INT_CLR_S  0
-/** SPI_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_MEM_PES_END_INT interrupt.
+#define SPI1_MEM_S_PER_END_INT_CLR    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_CLR_M  (SPI1_MEM_S_PER_END_INT_CLR_V << SPI1_MEM_S_PER_END_INT_CLR_S)
+#define SPI1_MEM_S_PER_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_CLR_S  0
+/** SPI1_MEM_S_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI1_MEM_S_PES_END_INT interrupt.
  */
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (SPI_MEM_PES_END_INT_CLR_V << SPI_MEM_PES_END_INT_CLR_S)
-#define SPI_MEM_PES_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/** SPI_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+#define SPI1_MEM_S_PES_END_INT_CLR    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_CLR_M  (SPI1_MEM_S_PES_END_INT_CLR_V << SPI1_MEM_S_PES_END_INT_CLR_S)
+#define SPI1_MEM_S_PES_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_CLR_S  1
+/** SPI1_MEM_S_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI1_MEM_S_WPE_END_INT interrupt.
  */
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (SPI_MEM_WPE_END_INT_CLR_V << SPI_MEM_WPE_END_INT_CLR_S)
-#define SPI_MEM_WPE_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI1_MEM_S_WPE_END_INT_CLR    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_CLR_M  (SPI1_MEM_S_WPE_END_INT_CLR_V << SPI1_MEM_S_WPE_END_INT_CLR_S)
+#define SPI1_MEM_S_WPE_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_CLR_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_M  (SPI1_MEM_S_SLV_ST_END_INT_CLR_V << SPI1_MEM_S_SLV_ST_END_INT_CLR_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S)
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+#define SPI1_MEM_S_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_M  (SPI1_MEM_S_MST_ST_END_INT_CLR_V << SPI1_MEM_S_MST_ST_END_INT_CLR_S)
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
  */
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (SPI_MEM_BROWN_OUT_INT_CLR_V << SPI_MEM_BROWN_OUT_INT_CLR_S)
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_M  (SPI1_MEM_S_BROWN_OUT_INT_CLR_V << SPI1_MEM_S_BROWN_OUT_INT_CLR_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_S  10
 
-/** SPI_MEM_INT_RAW_REG register
+/** SPI1_MEM_S_INT_RAW_REG register
  *  SPI1 interrupt raw register
  */
-#define SPI_MEM_INT_RAW_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc8)
-/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+#define SPI1_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc8)
+/** SPI1_MEM_S_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume
  *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
  */
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (SPI_MEM_PER_END_INT_RAW_V << SPI_MEM_PER_END_INT_RAW_S)
-#define SPI_MEM_PER_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PER_END_INT_RAW_S  0
-/** SPI_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+#define SPI1_MEM_S_PER_END_INT_RAW    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_RAW_M  (SPI1_MEM_S_PER_END_INT_RAW_V << SPI1_MEM_S_PER_END_INT_RAW_S)
+#define SPI1_MEM_S_PER_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_RAW_S  0
+/** SPI1_MEM_S_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend
  *  command (0x75) is sent and flash is suspended successfully. 0: Others.
  */
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (SPI_MEM_PES_END_INT_RAW_V << SPI_MEM_PES_END_INT_RAW_S)
-#define SPI_MEM_PES_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/** SPI_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+#define SPI1_MEM_S_PES_END_INT_RAW    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_RAW_M  (SPI1_MEM_S_PES_END_INT_RAW_V << SPI1_MEM_S_PES_END_INT_RAW_S)
+#define SPI1_MEM_S_PES_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_RAW_S  1
+/** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
  *  is sent and flash is already idle. 0: Others.
  */
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (SPI_MEM_WPE_END_INT_RAW_V << SPI_MEM_WPE_END_INT_RAW_S)
-#define SPI_MEM_WPE_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+#define SPI1_MEM_S_WPE_END_INT_RAW    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_RAW_M  (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S)
+#define SPI1_MEM_S_WPE_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_RAW_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
  *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
  *  Others
  */
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_M  (SPI1_MEM_S_SLV_ST_END_INT_RAW_V << SPI1_MEM_S_SLV_ST_END_INT_RAW_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
  *  changed from non idle state to idle state. 0: Others.
  */
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S)
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+#define SPI1_MEM_S_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_M  (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S)
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
  *  chip is loosing power and RTC module sends out brown out close flash request to
  *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  *  and MSPI returns to idle state. 0: Others.
  */
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (SPI_MEM_BROWN_OUT_INT_RAW_V << SPI_MEM_BROWN_OUT_INT_RAW_S)
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_M  (SPI1_MEM_S_BROWN_OUT_INT_RAW_V << SPI1_MEM_S_BROWN_OUT_INT_RAW_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_S  10
 
-/** SPI_MEM_INT_ST_REG register
+/** SPI1_MEM_S_INT_ST_REG register
  *  SPI1 interrupt status register
  */
-#define SPI_MEM_INT_ST_REG (DR_REG_PSRAM_MSPI1_BASE + 0xcc)
-/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_MEM_PER_END_INT interrupt.
+#define SPI1_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI1_BASE + 0xcc)
+/** SPI1_MEM_S_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI1_MEM_S_PER_END_INT interrupt.
  */
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (SPI_MEM_PER_END_INT_ST_V << SPI_MEM_PER_END_INT_ST_S)
-#define SPI_MEM_PER_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ST_S  0
-/** SPI_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_MEM_PES_END_INT interrupt.
+#define SPI1_MEM_S_PER_END_INT_ST    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_ST_M  (SPI1_MEM_S_PER_END_INT_ST_V << SPI1_MEM_S_PER_END_INT_ST_S)
+#define SPI1_MEM_S_PER_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_ST_S  0
+/** SPI1_MEM_S_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI1_MEM_S_PES_END_INT interrupt.
  */
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (SPI_MEM_PES_END_INT_ST_V << SPI_MEM_PES_END_INT_ST_S)
-#define SPI_MEM_PES_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ST_S  1
-/** SPI_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI_MEM_WPE_END_INT interrupt.
+#define SPI1_MEM_S_PES_END_INT_ST    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_ST_M  (SPI1_MEM_S_PES_END_INT_ST_V << SPI1_MEM_S_PES_END_INT_ST_S)
+#define SPI1_MEM_S_PES_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_ST_S  1
+/** SPI1_MEM_S_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI1_MEM_S_WPE_END_INT interrupt.
  */
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (SPI_MEM_WPE_END_INT_ST_V << SPI_MEM_WPE_END_INT_ST_S)
-#define SPI_MEM_WPE_END_INT_ST_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI1_MEM_S_WPE_END_INT_ST    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_ST_M  (SPI1_MEM_S_WPE_END_INT_ST_V << SPI1_MEM_S_WPE_END_INT_ST_S)
+#define SPI1_MEM_S_WPE_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_ST_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S)
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI1_MEM_S_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_M  (SPI1_MEM_S_SLV_ST_END_INT_ST_V << SPI1_MEM_S_SLV_ST_END_INT_ST_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S)
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/** SPI_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+#define SPI1_MEM_S_MST_ST_END_INT_ST    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_ST_M  (SPI1_MEM_S_MST_ST_END_INT_ST_V << SPI1_MEM_S_MST_ST_END_INT_ST_S)
+#define SPI1_MEM_S_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_ST_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
  */
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (SPI_MEM_BROWN_OUT_INT_ST_V << SPI_MEM_BROWN_OUT_INT_ST_S)
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ST_S  10
+#define SPI1_MEM_S_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_M  (SPI1_MEM_S_BROWN_OUT_INT_ST_V << SPI1_MEM_S_BROWN_OUT_INT_ST_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_S  10
 
-/** SPI_MEM_DDR_REG register
+/** SPI1_MEM_S_DDR_REG register
  *  SPI1 DDR control register
  */
-#define SPI_MEM_DDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xd4)
-/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xd4)
+/** SPI1_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
  *  1: in ddr mode,  0 in sdr mode
  */
-#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_M  (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S)
-#define SPI_MEM_FMEM_DDR_EN_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_EN_S  0
-/** SPI_MEM_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_EN    (BIT(0))
+#define SPI1_MEM_S_FMEM_DDR_EN_M  (SPI1_MEM_S_FMEM_DDR_EN_V << SPI1_MEM_S_FMEM_DDR_EN_S)
+#define SPI1_MEM_S_FMEM_DDR_EN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_EN_S  0
+/** SPI1_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi ddr mode.
  */
-#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_M  (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S)
-#define SPI_MEM_FMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_MEM_FMEM_VAR_DUMMY_S  1
-/** SPI_MEM_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
+#define SPI1_MEM_S_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_M  (SPI1_MEM_S_FMEM_VAR_DUMMY_V << SPI1_MEM_S_FMEM_VAR_DUMMY_S)
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_S  1
+/** SPI1_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
-/** SPI_MEM_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_M  (SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S)
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S  2
+/** SPI1_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
-/** SPI_MEM_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_M  (SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S)
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S  3
+/** SPI1_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S)
-#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
-/** SPI_MEM_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_M  (SPI1_MEM_S_FMEM_DDR_CMD_DIS_V << SPI1_MEM_S_FMEM_DDR_CMD_DIS_S)
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_S  4
+/** SPI1_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the panda device.
  */
-#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_M  (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S)
-#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
-/** SPI_MEM_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_M  (SPI1_MEM_S_FMEM_OUTMINBYTELEN_V << SPI1_MEM_S_FMEM_OUTMINBYTELEN_S)
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_S  5
+/** SPI1_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S)
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
-/** SPI_MEM_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_M  (SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S)
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S)
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
-/** SPI_MEM_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_M  (SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S)
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S  21
+/** SPI1_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S)
-#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
-/** SPI_MEM_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_M  (SPI1_MEM_S_FMEM_CLK_DIFF_EN_V << SPI1_MEM_S_FMEM_CLK_DIFF_EN_S)
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_S  24
+/** SPI1_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_M  (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S)
-#define SPI_MEM_FMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_MEM_FMEM_DQS_CA_IN_S  26
-/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
+#define SPI1_MEM_S_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_M  (SPI1_MEM_S_FMEM_DQS_CA_IN_V << SPI1_MEM_S_FMEM_DQS_CA_IN_S)
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_S  26
+/** SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_MEM_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M  (SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI1_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to flash. .
  */
-#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S)
-#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
-/** SPI_MEM_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_M  (SPI1_MEM_S_FMEM_CLK_DIFF_INV_V << SPI1_MEM_S_FMEM_CLK_DIFF_INV_S)
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_S  28
+/** SPI1_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
  */
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S)
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
-/** SPI_MEM_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_M  (SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S)
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI1_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_M  (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S)
-#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_M  (SPI1_MEM_S_FMEM_HYPERBUS_CA_V << SPI1_MEM_S_FMEM_HYPERBUS_CA_S)
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_S  30
 
-/** SPI_MEM_TIMING_CALI_REG register
+/** SPI1_MEM_S_TIMING_CALI_REG register
  *  SPI1 timing control register
  */
-#define SPI_MEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI1_BASE + 0x180)
-/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI1_BASE + 0x180)
+/** SPI1_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  The bit is used to enable timing auto-calibration for all reading operations.
  */
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S)
-#define SPI_MEM_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_S  1
-/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+#define SPI1_MEM_S_TIMING_CALI    (BIT(1))
+#define SPI1_MEM_S_TIMING_CALI_M  (SPI1_MEM_S_TIMING_CALI_V << SPI1_MEM_S_TIMING_CALI_S)
+#define SPI1_MEM_S_TIMING_CALI_V  0x00000001U
+#define SPI1_MEM_S_TIMING_CALI_S  1
+/** SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
  *  add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_M  (SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S  2
 
-/** SPI_MEM_CLOCK_GATE_REG register
+/** SPI1_MEM_S_CLOCK_GATE_REG register
  *  SPI1 clk_gate register
  */
-#define SPI_MEM_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x200)
-/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x200)
+/** SPI1_MEM_S_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Register clock gate enable signal. 1: Enable. 0: Disable.
  */
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (SPI_MEM_CLK_EN_V << SPI_MEM_CLK_EN_S)
-#define SPI_MEM_CLK_EN_V  0x00000001U
-#define SPI_MEM_CLK_EN_S  0
+#define SPI1_MEM_S_CLK_EN    (BIT(0))
+#define SPI1_MEM_S_CLK_EN_M  (SPI1_MEM_S_CLK_EN_V << SPI1_MEM_S_CLK_EN_S)
+#define SPI1_MEM_S_CLK_EN_V  0x00000001U
+#define SPI1_MEM_S_CLK_EN_S  0
 
-/** SPI_MEM_DATE_REG register
+/** SPI1_MEM_S_DATE_REG register
  *  Version control register
  */
-#define SPI_MEM_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc)
-/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 34673216;
+#define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc)
+/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 34673216;
  *  Version control register
  */
-#define SPI_MEM_DATE    0x0FFFFFFFU
-#define SPI_MEM_DATE_M  (SPI_MEM_DATE_V << SPI_MEM_DATE_S)
-#define SPI_MEM_DATE_V  0x0FFFFFFFU
-#define SPI_MEM_DATE_S  0
+#define SPI1_MEM_S_DATE    0x0FFFFFFFU
+#define SPI1_MEM_S_DATE_M  (SPI1_MEM_S_DATE_V << SPI1_MEM_S_DATE_S)
+#define SPI1_MEM_S_DATE_V  0x0FFFFFFFU
+#define SPI1_MEM_S_DATE_S  0
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h
index 3fee8e8707..80ba6092c4 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h
+++ b/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h
@@ -29,7 +29,7 @@ typedef union {
         uint32_t reserved_8:9;
         /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
          *  In user mode, it is set to indicate that program/erase operation will be triggered.
-         *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+         *  The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the
          *  operation done.1: enable 0: disable.
          */
         uint32_t flash_pe:1;
@@ -107,7 +107,7 @@ typedef union {
         uint32_t flash_read:1;
     };
     uint32_t val;
-} spi_mem_cmd_reg_t;
+} spi1_mem_s_cmd_reg_t;
 
 /** Type of addr register
  *  SPI1 address register
@@ -121,7 +121,7 @@ typedef union {
         uint32_t usr_addr_value:32;
     };
     uint32_t val;
-} spi_mem_addr_reg_t;
+} spi1_mem_s_addr_reg_t;
 
 /** Type of user register
  *  SPI1 user register.
@@ -130,7 +130,7 @@ typedef union {
     struct {
         uint32_t reserved_0:9;
         /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+         *  the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode.
          */
         uint32_t ck_out_edge:1;
         uint32_t reserved_10:2;
@@ -152,12 +152,12 @@ typedef union {
         uint32_t fwrite_qio:1;
         uint32_t reserved_16:8;
         /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_miso_highpart:1;
         /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_mosi_highpart:1;
@@ -187,7 +187,7 @@ typedef union {
         uint32_t usr_command:1;
     };
     uint32_t val;
-} spi_mem_user_reg_t;
+} spi1_mem_s_user_reg_t;
 
 /** Type of user1 register
  *  SPI1 user1 register.
@@ -195,7 +195,7 @@ typedef union {
 typedef union {
     struct {
         /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+         *  The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
         uint32_t usr_dummy_cyclelen:6;
@@ -206,7 +206,7 @@ typedef union {
         uint32_t usr_addr_bitlen:6;
     };
     uint32_t val;
-} spi_mem_user1_reg_t;
+} spi1_mem_s_user1_reg_t;
 
 /** Type of user2 register
  *  SPI1 user2 register.
@@ -224,7 +224,7 @@ typedef union {
         uint32_t usr_command_bitlen:4;
     };
     uint32_t val;
-} spi_mem_user2_reg_t;
+} spi1_mem_s_user2_reg_t;
 
 
 /** Group: Control and configuration registers */
@@ -276,8 +276,8 @@ typedef union {
         uint32_t tx_crc_en:1;
         uint32_t reserved_12:1;
         /** fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
-         *  and spi_mem_fread_dout. 1: enable 0: disable.
+         *  This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout
+         *  and spi1_mem_s_fread_dout. 1: enable 0: disable.
          */
         uint32_t fastrd_mode:1;
         /** fread_dual : R/W; bitpos: [14]; default: 0;
@@ -285,8 +285,8 @@ typedef union {
          */
         uint32_t fread_dual:1;
         /** resandres : R/W; bitpos: [15]; default: 1;
-         *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-         *  spi_mem_flash_res bit. 1: enable 0: disable.
+         *  The Device ID is read out to SPI1_MEM_S_RD_STATUS register,  this bit combine with
+         *  spi1_mem_s_flash_res bit. 1: enable 0: disable.
          */
         uint32_t resandres:1;
         uint32_t reserved_16:2;
@@ -324,7 +324,7 @@ typedef union {
         uint32_t reserved_25:7;
     };
     uint32_t val;
-} spi_mem_ctrl_reg_t;
+} spi1_mem_s_ctrl_reg_t;
 
 /** Type of ctrl1 register
  *  SPI1 control1 register.
@@ -338,14 +338,14 @@ typedef union {
          */
         uint32_t clk_mode:2;
         /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
-         *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+         *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512)
          *  SPI_CLK cycles.
          */
         uint32_t cs_hold_dly_res:10;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_ctrl1_reg_t;
+} spi1_mem_s_ctrl1_reg_t;
 
 /** Type of ctrl2 register
  *  SPI1 control2 register.
@@ -359,7 +359,7 @@ typedef union {
         uint32_t sync_reset:1;
     };
     uint32_t val;
-} spi_mem_ctrl2_reg_t;
+} spi1_mem_s_ctrl2_reg_t;
 
 /** Type of clock register
  *  SPI1 clock division control register.
@@ -367,16 +367,16 @@ typedef union {
 typedef union {
     struct {
         /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
+         *  In the master mode it must be equal to spi1_mem_s_clkcnt_N.
          */
         uint32_t clkcnt_l:8;
         /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+         *  In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1).
          */
         uint32_t clkcnt_h:8;
         /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
+         *  In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is
+         *  system/(spi1_mem_s_clkcnt_N+1)
          */
         uint32_t clkcnt_n:8;
         uint32_t reserved_24:7;
@@ -386,7 +386,7 @@ typedef union {
         uint32_t clk_equ_sysclk:1;
     };
     uint32_t val;
-} spi_mem_clock_reg_t;
+} spi1_mem_s_clock_reg_t;
 
 /** Type of mosi_dlen register
  *  SPI1 send data bit length control register.
@@ -400,7 +400,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_mosi_dlen_reg_t;
+} spi1_mem_s_mosi_dlen_reg_t;
 
 /** Type of miso_dlen register
  *  SPI1 receive data bit length control register.
@@ -414,7 +414,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_miso_dlen_reg_t;
+} spi1_mem_s_miso_dlen_reg_t;
 
 /** Type of rd_status register
  *  SPI1 status register.
@@ -422,17 +422,17 @@ typedef union {
 typedef union {
     struct {
         /** status : R/W/SS; bitpos: [15:0]; default: 0;
-         *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+         *  The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit.
          */
         uint32_t status:16;
         /** wb_mode : R/W; bitpos: [23:16]; default: 0;
-         *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+         *  Mode bits in the flash fast read mode  it is combined with spi1_mem_s_fastrd_mode bit.
          */
         uint32_t wb_mode:8;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} spi_mem_rd_status_reg_t;
+} spi1_mem_s_rd_status_reg_t;
 
 /** Type of misc register
  *  SPI1 misc register
@@ -461,7 +461,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_misc_reg_t;
+} spi1_mem_s_misc_reg_t;
 
 /** Type of cache_fctrl register
  *  SPI1 bit mode control register.
@@ -476,38 +476,38 @@ typedef union {
         uint32_t reserved_2:1;
         /** fdin_dual : R/W; bitpos: [3]; default: 0;
          *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
-         *  spi_mem_fread_dio.
+         *  spi1_mem_s_fread_dio.
          */
         uint32_t fdin_dual:1;
         /** fdout_dual : R/W; bitpos: [4]; default: 0;
          *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_s_fread_dio.
          */
         uint32_t fdout_dual:1;
         /** faddr_dual : R/W; bitpos: [5]; default: 0;
          *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_s_fread_dio.
          */
         uint32_t faddr_dual:1;
         /** fdin_quad : R/W; bitpos: [6]; default: 0;
          *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_s_fread_qio.
          */
         uint32_t fdin_quad:1;
         /** fdout_quad : R/W; bitpos: [7]; default: 0;
          *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_s_fread_qio.
          */
         uint32_t fdout_quad:1;
         /** faddr_quad : R/W; bitpos: [8]; default: 0;
          *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_s_fread_qio.
          */
         uint32_t faddr_quad:1;
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_mem_cache_fctrl_reg_t;
+} spi1_mem_s_cache_fctrl_reg_t;
 
 /** Type of flash_waiti_ctrl register
  *  SPI1 wait idle control register
@@ -530,9 +530,9 @@ typedef union {
          */
         uint32_t waiti_addr_en:1;
         /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
-         *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
-         *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
-         *  SPI_MEM_WAITI_ADDR_EN is cleared.
+         *  When SPI1_MEM_S_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+         *  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+         *  SPI1_MEM_S_WAITI_ADDR_EN is cleared.
          */
         uint32_t waiti_addr_cyclelen:2;
         uint32_t reserved_5:4;
@@ -550,7 +550,7 @@ typedef union {
         uint32_t waiti_cmd:16;
     };
     uint32_t val;
-} spi_mem_flash_waiti_ctrl_reg_t;
+} spi1_mem_s_flash_waiti_ctrl_reg_t;
 
 /** Type of flash_sus_ctrl register
  *  SPI1 flash suspend control register
@@ -570,13 +570,13 @@ typedef union {
          */
         uint32_t flash_pes:1;
         /** flash_per_wait_en : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase resume command is sent. 0: SPI1 does not wait after program erase
          *  resume command is sent.
          */
         uint32_t flash_per_wait_en:1;
         /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
          *  suspend command is sent.
          */
@@ -594,7 +594,7 @@ typedef union {
          *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
          *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
          *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
-         *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+         *  status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0].
          */
         uint32_t pesr_end_msk:16;
         /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0;
@@ -613,13 +613,13 @@ typedef union {
          */
         uint32_t pes_end_en:1;
         /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
-         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it
          *  will be treated as check pass.
          */
         uint32_t sus_timeout_cnt:7;
     };
     uint32_t val;
-} spi_mem_flash_sus_ctrl_reg_t;
+} spi1_mem_s_flash_sus_ctrl_reg_t;
 
 /** Type of flash_sus_cmd register
  *  SPI1 flash suspend command register
@@ -637,7 +637,7 @@ typedef union {
         uint32_t wait_pesr_command:16;
     };
     uint32_t val;
-} spi_mem_flash_sus_cmd_reg_t;
+} spi1_mem_s_flash_sus_cmd_reg_t;
 
 /** Type of sus_status register
  *  SPI1 flash suspend status register
@@ -649,39 +649,39 @@ typedef union {
          */
         uint32_t flash_sus:1;
         /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0;
-         *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
-         *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+         *  1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+         *  SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
          */
         uint32_t wait_pesr_cmd_2b:1;
         /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after HPM command is sent.
          */
         uint32_t flash_hpm_dly_128:1;
         /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after RES command is sent.
          */
         uint32_t flash_res_dly_128:1;
         /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after DP command is sent.
          */
         uint32_t flash_dp_dly_128:1;
         /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+         *  Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
          *  sent.
          */
         uint32_t flash_per_dly_128:1;
         /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+         *  Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
          *  sent.
          */
         uint32_t flash_pes_dly_128:1;
@@ -701,7 +701,7 @@ typedef union {
         uint32_t flash_per_command:16;
     };
     uint32_t val;
-} spi_mem_sus_status_reg_t;
+} spi1_mem_s_sus_status_reg_t;
 
 /** Type of ddr register
  *  SPI1 DDR control register
@@ -739,7 +739,7 @@ typedef union {
         uint32_t fmem_usr_ddr_dqs_thd:7;
         /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -776,7 +776,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_mem_ddr_reg_t;
+} spi1_mem_s_ddr_reg_t;
 
 /** Type of clock_gate register
  *  SPI1 clk_gate register
@@ -790,7 +790,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_clock_gate_reg_t;
+} spi1_mem_s_clock_gate_reg_t;
 
 
 /** Group: Status register */
@@ -805,7 +805,7 @@ typedef union {
         uint32_t tx_crc_data:32;
     };
     uint32_t val;
-} spi_mem_tx_crc_reg_t;
+} spi1_mem_s_tx_crc_reg_t;
 
 
 /** Group: Memory data buffer register */
@@ -820,7 +820,7 @@ typedef union {
         uint32_t buf0:32;
     };
     uint32_t val;
-} spi_mem_w0_reg_t;
+} spi1_mem_s_w0_reg_t;
 
 /** Type of w1 register
  *  SPI1 memory data buffer1
@@ -833,7 +833,7 @@ typedef union {
         uint32_t buf1:32;
     };
     uint32_t val;
-} spi_mem_w1_reg_t;
+} spi1_mem_s_w1_reg_t;
 
 /** Type of w2 register
  *  SPI1 memory data buffer2
@@ -846,7 +846,7 @@ typedef union {
         uint32_t buf2:32;
     };
     uint32_t val;
-} spi_mem_w2_reg_t;
+} spi1_mem_s_w2_reg_t;
 
 /** Type of w3 register
  *  SPI1 memory data buffer3
@@ -859,7 +859,7 @@ typedef union {
         uint32_t buf3:32;
     };
     uint32_t val;
-} spi_mem_w3_reg_t;
+} spi1_mem_s_w3_reg_t;
 
 /** Type of w4 register
  *  SPI1 memory data buffer4
@@ -872,7 +872,7 @@ typedef union {
         uint32_t buf4:32;
     };
     uint32_t val;
-} spi_mem_w4_reg_t;
+} spi1_mem_s_w4_reg_t;
 
 /** Type of w5 register
  *  SPI1 memory data buffer5
@@ -885,7 +885,7 @@ typedef union {
         uint32_t buf5:32;
     };
     uint32_t val;
-} spi_mem_w5_reg_t;
+} spi1_mem_s_w5_reg_t;
 
 /** Type of w6 register
  *  SPI1 memory data buffer6
@@ -898,7 +898,7 @@ typedef union {
         uint32_t buf6:32;
     };
     uint32_t val;
-} spi_mem_w6_reg_t;
+} spi1_mem_s_w6_reg_t;
 
 /** Type of w7 register
  *  SPI1 memory data buffer7
@@ -911,7 +911,7 @@ typedef union {
         uint32_t buf7:32;
     };
     uint32_t val;
-} spi_mem_w7_reg_t;
+} spi1_mem_s_w7_reg_t;
 
 /** Type of w8 register
  *  SPI1 memory data buffer8
@@ -924,7 +924,7 @@ typedef union {
         uint32_t buf8:32;
     };
     uint32_t val;
-} spi_mem_w8_reg_t;
+} spi1_mem_s_w8_reg_t;
 
 /** Type of w9 register
  *  SPI1 memory data buffer9
@@ -937,7 +937,7 @@ typedef union {
         uint32_t buf9:32;
     };
     uint32_t val;
-} spi_mem_w9_reg_t;
+} spi1_mem_s_w9_reg_t;
 
 /** Type of w10 register
  *  SPI1 memory data buffer10
@@ -950,7 +950,7 @@ typedef union {
         uint32_t buf10:32;
     };
     uint32_t val;
-} spi_mem_w10_reg_t;
+} spi1_mem_s_w10_reg_t;
 
 /** Type of w11 register
  *  SPI1 memory data buffer11
@@ -963,7 +963,7 @@ typedef union {
         uint32_t buf11:32;
     };
     uint32_t val;
-} spi_mem_w11_reg_t;
+} spi1_mem_s_w11_reg_t;
 
 /** Type of w12 register
  *  SPI1 memory data buffer12
@@ -976,7 +976,7 @@ typedef union {
         uint32_t buf12:32;
     };
     uint32_t val;
-} spi_mem_w12_reg_t;
+} spi1_mem_s_w12_reg_t;
 
 /** Type of w13 register
  *  SPI1 memory data buffer13
@@ -989,7 +989,7 @@ typedef union {
         uint32_t buf13:32;
     };
     uint32_t val;
-} spi_mem_w13_reg_t;
+} spi1_mem_s_w13_reg_t;
 
 /** Type of w14 register
  *  SPI1 memory data buffer14
@@ -1002,7 +1002,7 @@ typedef union {
         uint32_t buf14:32;
     };
     uint32_t val;
-} spi_mem_w14_reg_t;
+} spi1_mem_s_w14_reg_t;
 
 /** Type of w15 register
  *  SPI1 memory data buffer15
@@ -1015,7 +1015,7 @@ typedef union {
         uint32_t buf15:32;
     };
     uint32_t val;
-} spi_mem_w15_reg_t;
+} spi1_mem_s_w15_reg_t;
 
 
 /** Group: Interrupt registers */
@@ -1025,34 +1025,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_MEM_PER_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_PER_END_INT interrupt.
          */
         uint32_t per_end_int_ena:1;
         /** pes_end_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_MEM_PES_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_ena:1;
         /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_ena:1;
         /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_ena:1;
         /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_ena:1;
         uint32_t reserved_5:5;
         /** brown_out_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_ena:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_ena_reg_t;
+} spi1_mem_s_int_ena_reg_t;
 
 /** Type of int_clr register
  *  SPI1 interrupt clear register
@@ -1060,34 +1060,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_MEM_PER_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_PER_END_INT interrupt.
          */
         uint32_t per_end_int_clr:1;
         /** pes_end_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_MEM_PES_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_clr:1;
         /** wpe_end_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_clr:1;
         /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_clr:1;
         /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_clr:1;
         uint32_t reserved_5:5;
         /** brown_out_int_clr : WT; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_clr:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_clr_reg_t;
+} spi1_mem_s_int_clr_reg_t;
 
 /** Type of int_raw register
  *  SPI1 interrupt raw register
@@ -1095,34 +1095,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+         *  The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume
          *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
          */
         uint32_t per_end_int_raw:1;
         /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+         *  The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend
          *  command (0x75) is sent and flash is suspended successfully. 0: Others.
          */
         uint32_t pes_end_int_raw:1;
         /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+         *  The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
          *  is sent and flash is already idle. 0: Others.
          */
         uint32_t wpe_end_int_raw:1;
         /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+         *  The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
         uint32_t slv_st_end_int_raw:1;
         /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+         *  The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
         uint32_t mst_st_end_int_raw:1;
         uint32_t reserved_5:5;
         /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+         *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
          *  chip is loosing power and RTC module sends out brown out close flash request to
          *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
          *  and MSPI returns to idle state. 0: Others.
@@ -1131,7 +1131,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_raw_reg_t;
+} spi1_mem_s_int_raw_reg_t;
 
 /** Type of int_st register
  *  SPI1 interrupt status register
@@ -1139,34 +1139,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_MEM_PER_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_PER_END_INT interrupt.
          */
         uint32_t per_end_int_st:1;
         /** pes_end_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_MEM_PES_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_st:1;
         /** wpe_end_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_st:1;
         /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_st:1;
         /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_st:1;
         uint32_t reserved_5:5;
         /** brown_out_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_st:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_st_reg_t;
+} spi1_mem_s_int_st_reg_t;
 
 
 /** Group: Timing registers */
@@ -1187,7 +1187,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} spi_mem_timing_cali_reg_t;
+} spi1_mem_s_timing_cali_reg_t;
 
 
 /** Group: Version register */
@@ -1203,65 +1203,65 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} spi_mem_date_reg_t;
+} spi1_mem_s_date_reg_t;
 
 
-typedef struct {
-    volatile spi_mem_cmd_reg_t cmd;
-    volatile spi_mem_addr_reg_t addr;
-    volatile spi_mem_ctrl_reg_t ctrl;
-    volatile spi_mem_ctrl1_reg_t ctrl1;
-    volatile spi_mem_ctrl2_reg_t ctrl2;
-    volatile spi_mem_clock_reg_t clock;
-    volatile spi_mem_user_reg_t user;
-    volatile spi_mem_user1_reg_t user1;
-    volatile spi_mem_user2_reg_t user2;
-    volatile spi_mem_mosi_dlen_reg_t mosi_dlen;
-    volatile spi_mem_miso_dlen_reg_t miso_dlen;
-    volatile spi_mem_rd_status_reg_t rd_status;
+typedef struct spi1_mem_s_dev_s {
+    volatile spi1_mem_s_cmd_reg_t cmd;
+    volatile spi1_mem_s_addr_reg_t addr;
+    volatile spi1_mem_s_ctrl_reg_t ctrl;
+    volatile spi1_mem_s_ctrl1_reg_t ctrl1;
+    volatile spi1_mem_s_ctrl2_reg_t ctrl2;
+    volatile spi1_mem_s_clock_reg_t clock;
+    volatile spi1_mem_s_user_reg_t user;
+    volatile spi1_mem_s_user1_reg_t user1;
+    volatile spi1_mem_s_user2_reg_t user2;
+    volatile spi1_mem_s_mosi_dlen_reg_t mosi_dlen;
+    volatile spi1_mem_s_miso_dlen_reg_t miso_dlen;
+    volatile spi1_mem_s_rd_status_reg_t rd_status;
     uint32_t reserved_030;
-    volatile spi_mem_misc_reg_t misc;
-    volatile spi_mem_tx_crc_reg_t tx_crc;
-    volatile spi_mem_cache_fctrl_reg_t cache_fctrl;
+    volatile spi1_mem_s_misc_reg_t misc;
+    volatile spi1_mem_s_tx_crc_reg_t tx_crc;
+    volatile spi1_mem_s_cache_fctrl_reg_t cache_fctrl;
     uint32_t reserved_040[6];
-    volatile spi_mem_w0_reg_t w0;
-    volatile spi_mem_w1_reg_t w1;
-    volatile spi_mem_w2_reg_t w2;
-    volatile spi_mem_w3_reg_t w3;
-    volatile spi_mem_w4_reg_t w4;
-    volatile spi_mem_w5_reg_t w5;
-    volatile spi_mem_w6_reg_t w6;
-    volatile spi_mem_w7_reg_t w7;
-    volatile spi_mem_w8_reg_t w8;
-    volatile spi_mem_w9_reg_t w9;
-    volatile spi_mem_w10_reg_t w10;
-    volatile spi_mem_w11_reg_t w11;
-    volatile spi_mem_w12_reg_t w12;
-    volatile spi_mem_w13_reg_t w13;
-    volatile spi_mem_w14_reg_t w14;
-    volatile spi_mem_w15_reg_t w15;
-    volatile spi_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
-    volatile spi_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
-    volatile spi_mem_flash_sus_cmd_reg_t flash_sus_cmd;
-    volatile spi_mem_sus_status_reg_t sus_status;
+    volatile spi1_mem_s_w0_reg_t w0;
+    volatile spi1_mem_s_w1_reg_t w1;
+    volatile spi1_mem_s_w2_reg_t w2;
+    volatile spi1_mem_s_w3_reg_t w3;
+    volatile spi1_mem_s_w4_reg_t w4;
+    volatile spi1_mem_s_w5_reg_t w5;
+    volatile spi1_mem_s_w6_reg_t w6;
+    volatile spi1_mem_s_w7_reg_t w7;
+    volatile spi1_mem_s_w8_reg_t w8;
+    volatile spi1_mem_s_w9_reg_t w9;
+    volatile spi1_mem_s_w10_reg_t w10;
+    volatile spi1_mem_s_w11_reg_t w11;
+    volatile spi1_mem_s_w12_reg_t w12;
+    volatile spi1_mem_s_w13_reg_t w13;
+    volatile spi1_mem_s_w14_reg_t w14;
+    volatile spi1_mem_s_w15_reg_t w15;
+    volatile spi1_mem_s_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
+    volatile spi1_mem_s_flash_sus_ctrl_reg_t flash_sus_ctrl;
+    volatile spi1_mem_s_flash_sus_cmd_reg_t flash_sus_cmd;
+    volatile spi1_mem_s_sus_status_reg_t sus_status;
     uint32_t reserved_0a8[6];
-    volatile spi_mem_int_ena_reg_t int_ena;
-    volatile spi_mem_int_clr_reg_t int_clr;
-    volatile spi_mem_int_raw_reg_t int_raw;
-    volatile spi_mem_int_st_reg_t int_st;
+    volatile spi1_mem_s_int_ena_reg_t int_ena;
+    volatile spi1_mem_s_int_clr_reg_t int_clr;
+    volatile spi1_mem_s_int_raw_reg_t int_raw;
+    volatile spi1_mem_s_int_st_reg_t int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_ddr_reg_t ddr;
+    volatile spi1_mem_s_ddr_reg_t ddr;
     uint32_t reserved_0d8[42];
-    volatile spi_mem_timing_cali_reg_t timing_cali;
+    volatile spi1_mem_s_timing_cali_reg_t timing_cali;
     uint32_t reserved_184[31];
-    volatile spi_mem_clock_gate_reg_t clock_gate;
+    volatile spi1_mem_s_clock_gate_reg_t clock_gate;
     uint32_t reserved_204[126];
-    volatile spi_mem_date_reg_t date;
+    volatile spi1_mem_s_date_reg_t date;
 } spi1_mem_s_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
+_Static_assert(sizeof(spi1_mem_s_dev_t) == 0x400, "Invalid size of spi1_mem_s_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_reg.h b/components/soc/esp32p4/include/soc/spi_mem_c_reg.h
index 59abb24351..89ff7ae948 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_c_reg.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_c_reg.h
@@ -11,2554 +11,2554 @@
 extern "C" {
 #endif
 
-/** SPI_MEM_CMD_REG register
+/** SPI_MEM_C_CMD_REG register
  *  SPI0 FSM status register
  */
-#define SPI_MEM_CMD_REG (DR_REG_SPI0_BASE + 0x0)
-/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
+#define SPI_MEM_C_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x0)
+/** SPI_MEM_C_MST_ST : RO; bitpos: [3:0]; default: 0;
  *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
  *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
  *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
  */
-#define SPI_MEM_MST_ST    0x0000000FU
-#define SPI_MEM_MST_ST_M  (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S)
-#define SPI_MEM_MST_ST_V  0x0000000FU
-#define SPI_MEM_MST_ST_S  0
-/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
+#define SPI_MEM_C_MST_ST    0x0000000FU
+#define SPI_MEM_C_MST_ST_M  (SPI_MEM_C_MST_ST_V << SPI_MEM_C_MST_ST_S)
+#define SPI_MEM_C_MST_ST_V  0x0000000FU
+#define SPI_MEM_C_MST_ST_S  0
+/** SPI_MEM_C_SLV_ST : RO; bitpos: [7:4]; default: 0;
  *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
  *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
  *  6:write data state, 7: done state, 8: read data end state.
  */
-#define SPI_MEM_SLV_ST    0x0000000FU
-#define SPI_MEM_SLV_ST_M  (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S)
-#define SPI_MEM_SLV_ST_V  0x0000000FU
-#define SPI_MEM_SLV_ST_S  4
-/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0;
- *  SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
+#define SPI_MEM_C_SLV_ST    0x0000000FU
+#define SPI_MEM_C_SLV_ST_M  (SPI_MEM_C_SLV_ST_V << SPI_MEM_C_SLV_ST_S)
+#define SPI_MEM_C_SLV_ST_V  0x0000000FU
+#define SPI_MEM_C_SLV_ST_S  4
+/** SPI_MEM_C_USR : HRO; bitpos: [18]; default: 0;
+ *  SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared.  An operation
  *  will be triggered when the bit is set. The bit will be cleared once the operation
  *  done.1: enable 0: disable.
  */
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (SPI_MEM_USR_V << SPI_MEM_USR_S)
-#define SPI_MEM_USR_V  0x00000001U
-#define SPI_MEM_USR_S  18
+#define SPI_MEM_C_USR    (BIT(18))
+#define SPI_MEM_C_USR_M  (SPI_MEM_C_USR_V << SPI_MEM_C_USR_S)
+#define SPI_MEM_C_USR_V  0x00000001U
+#define SPI_MEM_C_USR_S  18
 
-/** SPI_MEM_CTRL_REG register
+/** SPI_MEM_C_CTRL_REG register
  *  SPI0 control register.
  */
-#define SPI_MEM_CTRL_REG (DR_REG_SPI0_BASE + 0x8)
-/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0;
+#define SPI_MEM_C_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x8)
+/** SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
  *  of SPI_DQS is output by the MSPI controller.
  */
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S)
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_S  0
+/** SPI_MEM_C_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
  *  of SPI_IO[7:0] is output by the MSPI controller.
  */
-#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S)
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_C_WDUMMY_ALWAYS_OUT_V << SPI_MEM_C_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_S  1
+/** SPI_MEM_C_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
  *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
  *  output by the MSPI controller in the first half part of dummy phase. It is used to
  *  mask invalid SPI_DQS in the half part of dummy phase.
  */
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S)
-#define SPI_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI_MEM_FDUMMY_RIN_S  2
-/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+#define SPI_MEM_C_FDUMMY_RIN    (BIT(2))
+#define SPI_MEM_C_FDUMMY_RIN_M  (SPI_MEM_C_FDUMMY_RIN_V << SPI_MEM_C_FDUMMY_RIN_S)
+#define SPI_MEM_C_FDUMMY_RIN_V  0x00000001U
+#define SPI_MEM_C_FDUMMY_RIN_S  2
+/** SPI_MEM_C_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
  *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
  *  output by the MSPI controller in the second half part of dummy phase. It is used to
  *  pre-drive flash.
  */
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S)
-#define SPI_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
+#define SPI_MEM_C_FDUMMY_WOUT    (BIT(3))
+#define SPI_MEM_C_FDUMMY_WOUT_M  (SPI_MEM_C_FDUMMY_WOUT_V << SPI_MEM_C_FDUMMY_WOUT_S)
+#define SPI_MEM_C_FDUMMY_WOUT_V  0x00000001U
+#define SPI_MEM_C_FDUMMY_WOUT_S  3
+/** SPI_MEM_C_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
  *  Apply 8 signals during write-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S)
-#define SPI_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI_MEM_FDOUT_OCT_S  4
-/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0;
+#define SPI_MEM_C_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_C_FDOUT_OCT_M  (SPI_MEM_C_FDOUT_OCT_V << SPI_MEM_C_FDOUT_OCT_S)
+#define SPI_MEM_C_FDOUT_OCT_V  0x00000001U
+#define SPI_MEM_C_FDOUT_OCT_S  4
+/** SPI_MEM_C_FDIN_OCT : HRO; bitpos: [5]; default: 0;
  *  Apply 8 signals during read-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S)
-#define SPI_MEM_FDIN_OCT_V  0x00000001U
-#define SPI_MEM_FDIN_OCT_S  5
-/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0;
+#define SPI_MEM_C_FDIN_OCT    (BIT(5))
+#define SPI_MEM_C_FDIN_OCT_M  (SPI_MEM_C_FDIN_OCT_V << SPI_MEM_C_FDIN_OCT_S)
+#define SPI_MEM_C_FDIN_OCT_V  0x00000001U
+#define SPI_MEM_C_FDIN_OCT_S  5
+/** SPI_MEM_C_FADDR_OCT : HRO; bitpos: [6]; default: 0;
  *  Apply 8 signals during address phase 1:enable 0: disable
  */
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S)
-#define SPI_MEM_FADDR_OCT_V  0x00000001U
-#define SPI_MEM_FADDR_OCT_S  6
-/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_C_FADDR_OCT    (BIT(6))
+#define SPI_MEM_C_FADDR_OCT_M  (SPI_MEM_C_FADDR_OCT_V << SPI_MEM_C_FADDR_OCT_S)
+#define SPI_MEM_C_FADDR_OCT_V  0x00000001U
+#define SPI_MEM_C_FADDR_OCT_S  6
+/** SPI_MEM_C_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
  *  Apply 4 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S)
-#define SPI_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI_MEM_FCMD_QUAD_S  8
-/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0;
+#define SPI_MEM_C_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_C_FCMD_QUAD_M  (SPI_MEM_C_FCMD_QUAD_V << SPI_MEM_C_FCMD_QUAD_S)
+#define SPI_MEM_C_FCMD_QUAD_V  0x00000001U
+#define SPI_MEM_C_FCMD_QUAD_S  8
+/** SPI_MEM_C_FCMD_OCT : HRO; bitpos: [9]; default: 0;
  *  Apply 8 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S)
-#define SPI_MEM_FCMD_OCT_V  0x00000001U
-#define SPI_MEM_FCMD_OCT_S  9
-/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT
- *  and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.
+#define SPI_MEM_C_FCMD_OCT    (BIT(9))
+#define SPI_MEM_C_FCMD_OCT_M  (SPI_MEM_C_FCMD_OCT_V << SPI_MEM_C_FCMD_OCT_S)
+#define SPI_MEM_C_FCMD_OCT_V  0x00000001U
+#define SPI_MEM_C_FCMD_OCT_S  9
+/** SPI_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, SPI_MEM_C_FREAD_QOUT
+ *  and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable.
  */
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S)
-#define SPI_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI_MEM_FASTRD_MODE_S  13
-/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+#define SPI_MEM_C_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_C_FASTRD_MODE_M  (SPI_MEM_C_FASTRD_MODE_V << SPI_MEM_C_FASTRD_MODE_S)
+#define SPI_MEM_C_FASTRD_MODE_V  0x00000001U
+#define SPI_MEM_C_FASTRD_MODE_S  13
+/** SPI_MEM_C_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
  *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S)
-#define SPI_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI_MEM_FREAD_DUAL_S  14
-/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
+#define SPI_MEM_C_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_C_FREAD_DUAL_M  (SPI_MEM_C_FREAD_DUAL_V << SPI_MEM_C_FREAD_DUAL_S)
+#define SPI_MEM_C_FREAD_DUAL_V  0x00000001U
+#define SPI_MEM_C_FREAD_DUAL_S  14
+/** SPI_MEM_C_Q_POL : R/W; bitpos: [18]; default: 1;
  *  The bit is used to set MISO line polarity, 1: high 0, low
  */
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S)
-#define SPI_MEM_Q_POL_V  0x00000001U
-#define SPI_MEM_Q_POL_S  18
-/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1;
+#define SPI_MEM_C_Q_POL    (BIT(18))
+#define SPI_MEM_C_Q_POL_M  (SPI_MEM_C_Q_POL_V << SPI_MEM_C_Q_POL_S)
+#define SPI_MEM_C_Q_POL_V  0x00000001U
+#define SPI_MEM_C_Q_POL_S  18
+/** SPI_MEM_C_D_POL : R/W; bitpos: [19]; default: 1;
  *  The bit is used to set MOSI line polarity, 1: high 0, low
  */
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S)
-#define SPI_MEM_D_POL_V  0x00000001U
-#define SPI_MEM_D_POL_S  19
-/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+#define SPI_MEM_C_D_POL    (BIT(19))
+#define SPI_MEM_C_D_POL_M  (SPI_MEM_C_D_POL_V << SPI_MEM_C_D_POL_S)
+#define SPI_MEM_C_D_POL_V  0x00000001U
+#define SPI_MEM_C_D_POL_S  19
+/** SPI_MEM_C_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
  *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S)
-#define SPI_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI_MEM_FREAD_QUAD_S  20
-/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
+#define SPI_MEM_C_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_C_FREAD_QUAD_M  (SPI_MEM_C_FREAD_QUAD_V << SPI_MEM_C_FREAD_QUAD_S)
+#define SPI_MEM_C_FREAD_QUAD_V  0x00000001U
+#define SPI_MEM_C_FREAD_QUAD_S  20
+/** SPI_MEM_C_WP_REG : R/W; bitpos: [21]; default: 1;
  *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
  */
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S)
-#define SPI_MEM_WP_REG_V  0x00000001U
-#define SPI_MEM_WP_REG_S  21
-/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+#define SPI_MEM_C_WP_REG    (BIT(21))
+#define SPI_MEM_C_WP_REG_M  (SPI_MEM_C_WP_REG_V << SPI_MEM_C_WP_REG_S)
+#define SPI_MEM_C_WP_REG_V  0x00000001U
+#define SPI_MEM_C_WP_REG_S  21
+/** SPI_MEM_C_FREAD_DIO : R/W; bitpos: [23]; default: 0;
  *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S)
-#define SPI_MEM_FREAD_DIO_V  0x00000001U
-#define SPI_MEM_FREAD_DIO_S  23
-/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+#define SPI_MEM_C_FREAD_DIO    (BIT(23))
+#define SPI_MEM_C_FREAD_DIO_M  (SPI_MEM_C_FREAD_DIO_V << SPI_MEM_C_FREAD_DIO_S)
+#define SPI_MEM_C_FREAD_DIO_V  0x00000001U
+#define SPI_MEM_C_FREAD_DIO_S  23
+/** SPI_MEM_C_FREAD_QIO : R/W; bitpos: [24]; default: 0;
  *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S)
-#define SPI_MEM_FREAD_QIO_V  0x00000001U
-#define SPI_MEM_FREAD_QIO_S  24
-/** SPI_MEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0;
+#define SPI_MEM_C_FREAD_QIO    (BIT(24))
+#define SPI_MEM_C_FREAD_QIO_M  (SPI_MEM_C_FREAD_QIO_V << SPI_MEM_C_FREAD_QIO_S)
+#define SPI_MEM_C_FREAD_QIO_V  0x00000001U
+#define SPI_MEM_C_FREAD_QIO_S  24
+/** SPI_MEM_C_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0;
  *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
  *  1. 0: Others.
  */
-#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S)
-#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON_M  (SPI_MEM_C_DQS_IE_ALWAYS_ON_V << SPI_MEM_C_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_C_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
  *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
  *  always 1. 0: Others.
  */
-#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S)
-#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON_M  (SPI_MEM_C_DATA_IE_ALWAYS_ON_V << SPI_MEM_C_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON_S  31
 
-/** SPI_MEM_CTRL1_REG register
+/** SPI_MEM_C_CTRL1_REG register
  *  SPI0 control1 register.
  */
-#define SPI_MEM_CTRL1_REG (DR_REG_SPI0_BASE + 0xc)
-/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_C_CTRL1_REG (DR_REG_FLASH_SPI0_BASE + 0xc)
+/** SPI_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
  *  SPI clock is alwasy on.
  */
-#define SPI_MEM_CLK_MODE    0x00000003U
-#define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
-#define SPI_MEM_CLK_MODE_V  0x00000003U
-#define SPI_MEM_CLK_MODE_S  0
-/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
+#define SPI_MEM_C_CLK_MODE    0x00000003U
+#define SPI_MEM_C_CLK_MODE_M  (SPI_MEM_C_CLK_MODE_V << SPI_MEM_C_CLK_MODE_S)
+#define SPI_MEM_C_CLK_MODE_V  0x00000003U
+#define SPI_MEM_C_CLK_MODE_S  0
+/** SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
  *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
  *  the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
  */
-#define SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define SPI_AR_SIZE0_1_SUPPORT_EN_M  (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S)
-#define SPI_AR_SIZE0_1_SUPPORT_EN_V  0x00000001U
-#define SPI_AR_SIZE0_1_SUPPORT_EN_S  21
-/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_S  21
+/** SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
  *  1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
  */
-#define SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define SPI_AW_SIZE0_1_SUPPORT_EN_M  (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S)
-#define SPI_AW_SIZE0_1_SUPPORT_EN_V  0x00000001U
-#define SPI_AW_SIZE0_1_SUPPORT_EN_S  22
-/** SPI_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1;
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S  22
+/** SPI_MEM_C_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1;
  *  1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
  *  Reply AXI read data to AXI bus when all the read data is available.
  */
-#define SPI_AXI_RDATA_BACK_FAST    (BIT(23))
-#define SPI_AXI_RDATA_BACK_FAST_M  (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S)
-#define SPI_AXI_RDATA_BACK_FAST_V  0x00000001U
-#define SPI_AXI_RDATA_BACK_FAST_S  23
-/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST    (BIT(23))
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST_M  (SPI_MEM_C_AXI_RDATA_BACK_FAST_V << SPI_MEM_C_AXI_RDATA_BACK_FAST_S)
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST_V  0x00000001U
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST_S  23
+/** SPI_MEM_C_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
  *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
  *  when there is a ECC error in AXI read data. The ECC error information is recorded
- *  in SPI_MEM_ECC_ERR_ADDR_REG.
+ *  in SPI_MEM_C_ECC_ERR_ADDR_REG.
  */
-#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_M  (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S)
-#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x00000001U
-#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
-/** SPI_MEM_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0;
+#define SPI_MEM_C_RRESP_ECC_ERR_EN    (BIT(24))
+#define SPI_MEM_C_RRESP_ECC_ERR_EN_M  (SPI_MEM_C_RRESP_ECC_ERR_EN_V << SPI_MEM_C_RRESP_ECC_ERR_EN_S)
+#define SPI_MEM_C_RRESP_ECC_ERR_EN_V  0x00000001U
+#define SPI_MEM_C_RRESP_ECC_ERR_EN_S  24
+/** SPI_MEM_C_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0;
  *  Set this bit to enable AXI Read Splice-transfer.
  */
-#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_M  (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S)
-#define SPI_MEM_AR_SPLICE_EN_V  0x00000001U
-#define SPI_MEM_AR_SPLICE_EN_S  25
-/** SPI_MEM_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0;
+#define SPI_MEM_C_AR_SPLICE_EN    (BIT(25))
+#define SPI_MEM_C_AR_SPLICE_EN_M  (SPI_MEM_C_AR_SPLICE_EN_V << SPI_MEM_C_AR_SPLICE_EN_S)
+#define SPI_MEM_C_AR_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_C_AR_SPLICE_EN_S  25
+/** SPI_MEM_C_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0;
  *  Set this bit to enable AXI Write Splice-transfer.
  */
-#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_M  (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S)
-#define SPI_MEM_AW_SPLICE_EN_V  0x00000001U
-#define SPI_MEM_AW_SPLICE_EN_S  26
-/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1;
- *  When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be
- *  accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1
- *  will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+#define SPI_MEM_C_AW_SPLICE_EN    (BIT(26))
+#define SPI_MEM_C_AW_SPLICE_EN_M  (SPI_MEM_C_AW_SPLICE_EN_V << SPI_MEM_C_AW_SPLICE_EN_S)
+#define SPI_MEM_C_AW_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_C_AW_SPLICE_EN_S  26
+/** SPI_MEM_C_RAM0_EN : HRO; bitpos: [27]; default: 1;
+ *  When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 1, only EXT_RAM0 will be
+ *  accessed. When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 0, only EXT_RAM1
+ *  will be accessed. When SPI_MEM_C_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
  *  accessed at the same time.
  */
-#define SPI_MEM_RAM0_EN    (BIT(27))
-#define SPI_MEM_RAM0_EN_M  (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S)
-#define SPI_MEM_RAM0_EN_V  0x00000001U
-#define SPI_MEM_RAM0_EN_S  27
-/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0;
+#define SPI_MEM_C_RAM0_EN    (BIT(27))
+#define SPI_MEM_C_RAM0_EN_M  (SPI_MEM_C_RAM0_EN_V << SPI_MEM_C_RAM0_EN_S)
+#define SPI_MEM_C_RAM0_EN_V  0x00000001U
+#define SPI_MEM_C_RAM0_EN_S  27
+/** SPI_MEM_C_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0;
  *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
  *  same time.
  */
-#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_M  (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S)
-#define SPI_MEM_DUAL_RAM_EN_V  0x00000001U
-#define SPI_MEM_DUAL_RAM_EN_S  28
-/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1;
+#define SPI_MEM_C_DUAL_RAM_EN    (BIT(28))
+#define SPI_MEM_C_DUAL_RAM_EN_M  (SPI_MEM_C_DUAL_RAM_EN_V << SPI_MEM_C_DUAL_RAM_EN_S)
+#define SPI_MEM_C_DUAL_RAM_EN_V  0x00000001U
+#define SPI_MEM_C_DUAL_RAM_EN_S  28
+/** SPI_MEM_C_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1;
  *  Set this bit to write data faster, do not wait write data has been stored in
  *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
  *  in  tx_bus_fifo_l2.
  */
-#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_M  (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S)
-#define SPI_MEM_FAST_WRITE_EN_V  0x00000001U
-#define SPI_MEM_FAST_WRITE_EN_S  29
-/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0;
+#define SPI_MEM_C_FAST_WRITE_EN    (BIT(29))
+#define SPI_MEM_C_FAST_WRITE_EN_M  (SPI_MEM_C_FAST_WRITE_EN_V << SPI_MEM_C_FAST_WRITE_EN_S)
+#define SPI_MEM_C_FAST_WRITE_EN_V  0x00000001U
+#define SPI_MEM_C_FAST_WRITE_EN_S  29
+/** SPI_MEM_C_RXFIFO_RST : WT; bitpos: [30]; default: 0;
  *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
  *  receive signals from AXI.  Set this bit to reset these FIFO.
  */
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S)
-#define SPI_MEM_RXFIFO_RST_V  0x00000001U
-#define SPI_MEM_RXFIFO_RST_S  30
-/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0;
+#define SPI_MEM_C_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_C_RXFIFO_RST_M  (SPI_MEM_C_RXFIFO_RST_V << SPI_MEM_C_RXFIFO_RST_S)
+#define SPI_MEM_C_RXFIFO_RST_V  0x00000001U
+#define SPI_MEM_C_RXFIFO_RST_S  30
+/** SPI_MEM_C_TXFIFO_RST : WT; bitpos: [31]; default: 0;
  *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
  *  send signals to AXI. Set this bit to reset these FIFO.
  */
-#define SPI_MEM_TXFIFO_RST    (BIT(31))
-#define SPI_MEM_TXFIFO_RST_M  (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S)
-#define SPI_MEM_TXFIFO_RST_V  0x00000001U
-#define SPI_MEM_TXFIFO_RST_S  31
+#define SPI_MEM_C_TXFIFO_RST    (BIT(31))
+#define SPI_MEM_C_TXFIFO_RST_M  (SPI_MEM_C_TXFIFO_RST_V << SPI_MEM_C_TXFIFO_RST_S)
+#define SPI_MEM_C_TXFIFO_RST_V  0x00000001U
+#define SPI_MEM_C_TXFIFO_RST_S  31
 
-/** SPI_MEM_CTRL2_REG register
+/** SPI_MEM_C_CTRL2_REG register
  *  SPI0 control2 register.
  */
-#define SPI_MEM_CTRL2_REG (DR_REG_SPI0_BASE + 0x10)
-/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
+#define SPI_MEM_C_CTRL2_REG (DR_REG_FLASH_SPI0_BASE + 0x10)
+/** SPI_MEM_C_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
  *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
- *  SPI_MEM_CS_SETUP bit.
+ *  SPI_MEM_C_CS_SETUP bit.
  */
-#define SPI_MEM_CS_SETUP_TIME    0x0000001FU
-#define SPI_MEM_CS_SETUP_TIME_M  (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S)
-#define SPI_MEM_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_MEM_CS_SETUP_TIME_S  0
-/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1;
+#define SPI_MEM_C_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_C_CS_SETUP_TIME_M  (SPI_MEM_C_CS_SETUP_TIME_V << SPI_MEM_C_CS_SETUP_TIME_S)
+#define SPI_MEM_C_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_C_CS_SETUP_TIME_S  0
+/** SPI_MEM_C_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1;
  *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
- *  SPI_MEM_CS_HOLD bit.
+ *  SPI_MEM_C_CS_HOLD bit.
  */
-#define SPI_MEM_CS_HOLD_TIME    0x0000001FU
-#define SPI_MEM_CS_HOLD_TIME_M  (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S)
-#define SPI_MEM_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/** SPI_MEM_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3;
- *  SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+#define SPI_MEM_C_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_C_CS_HOLD_TIME_M  (SPI_MEM_C_CS_HOLD_TIME_V << SPI_MEM_C_CS_HOLD_TIME_S)
+#define SPI_MEM_C_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_C_CS_HOLD_TIME_S  5
+/** SPI_MEM_C_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3;
+ *  SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
  *  mode when accessed flash.
  */
-#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007U
-#define SPI_MEM_ECC_CS_HOLD_TIME_M  (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S)
-#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x00000007U
-#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
-/** SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1;
+#define SPI_MEM_C_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_C_ECC_CS_HOLD_TIME_M  (SPI_MEM_C_ECC_CS_HOLD_TIME_V << SPI_MEM_C_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_C_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_C_ECC_CS_HOLD_TIME_S  10
+/** SPI_MEM_C_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1;
  *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
  *  accesses flash.
  */
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S)
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/** SPI_MEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0;
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_C_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_C_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_S  13
+/** SPI_MEM_C_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0;
  *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
  *  accesses flash.
  */
-#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S)
-#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x00000001U
-#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1;
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN_M  (SPI_MEM_C_ECC_16TO18_BYTE_EN_V << SPI_MEM_C_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN_S  14
+/** SPI_MEM_C_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1;
  *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
  *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
  *  matter whether there is an ECC region or not.
  */
-#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_M  (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S)
-#define SPI_MEM_SPLIT_TRANS_EN_V  0x00000001U
-#define SPI_MEM_SPLIT_TRANS_EN_S  24
-/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
+#define SPI_MEM_C_SPLIT_TRANS_EN    (BIT(24))
+#define SPI_MEM_C_SPLIT_TRANS_EN_M  (SPI_MEM_C_SPLIT_TRANS_EN_V << SPI_MEM_C_SPLIT_TRANS_EN_S)
+#define SPI_MEM_C_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_C_SPLIT_TRANS_EN_S  24
+/** SPI_MEM_C_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
  *  These bits are used to set the minimum CS high time tSHSL between SPI burst
- *  transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
+ *  transfer when accesses to flash. tSHSL is (SPI_MEM_C_CS_HOLD_DELAY[5:0] + 1) MSPI
  *  core clock cycles.
  */
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003FU
-#define SPI_MEM_CS_HOLD_DELAY_M  (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S)
-#define SPI_MEM_CS_HOLD_DELAY_V  0x0000003FU
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
+#define SPI_MEM_C_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_C_CS_HOLD_DELAY_M  (SPI_MEM_C_CS_HOLD_DELAY_V << SPI_MEM_C_CS_HOLD_DELAY_S)
+#define SPI_MEM_C_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_C_CS_HOLD_DELAY_S  25
+/** SPI_MEM_C_SYNC_RESET : WT; bitpos: [31]; default: 0;
  *  The spi0_mst_st and spi0_slv_st will be reset.
  */
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S)
-#define SPI_MEM_SYNC_RESET_V  0x00000001U
-#define SPI_MEM_SYNC_RESET_S  31
+#define SPI_MEM_C_SYNC_RESET    (BIT(31))
+#define SPI_MEM_C_SYNC_RESET_M  (SPI_MEM_C_SYNC_RESET_V << SPI_MEM_C_SYNC_RESET_S)
+#define SPI_MEM_C_SYNC_RESET_V  0x00000001U
+#define SPI_MEM_C_SYNC_RESET_S  31
 
-/** SPI_MEM_CLOCK_REG register
+/** SPI_MEM_C_CLOCK_REG register
  *  SPI clock division control register.
  */
-#define SPI_MEM_CLOCK_REG (DR_REG_SPI0_BASE + 0x14)
-/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+#define SPI_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI0_BASE + 0x14)
+/** SPI_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
  *  In the master mode it must be equal to spi_mem_clkcnt_N.
  */
-#define SPI_MEM_CLKCNT_L    0x000000FFU
-#define SPI_MEM_CLKCNT_L_M  (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
-#define SPI_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI_MEM_CLKCNT_L_S  0
-/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+#define SPI_MEM_C_CLKCNT_L    0x000000FFU
+#define SPI_MEM_C_CLKCNT_L_M  (SPI_MEM_C_CLKCNT_L_V << SPI_MEM_C_CLKCNT_L_S)
+#define SPI_MEM_C_CLKCNT_L_V  0x000000FFU
+#define SPI_MEM_C_CLKCNT_L_S  0
+/** SPI_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
  *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
  */
-#define SPI_MEM_CLKCNT_H    0x000000FFU
-#define SPI_MEM_CLKCNT_H_M  (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
-#define SPI_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI_MEM_CLKCNT_H_S  8
-/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+#define SPI_MEM_C_CLKCNT_H    0x000000FFU
+#define SPI_MEM_C_CLKCNT_H_M  (SPI_MEM_C_CLKCNT_H_V << SPI_MEM_C_CLKCNT_H_S)
+#define SPI_MEM_C_CLKCNT_H_V  0x000000FFU
+#define SPI_MEM_C_CLKCNT_H_S  8
+/** SPI_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
  *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
  *  system/(spi_mem_clkcnt_N+1)
  */
-#define SPI_MEM_CLKCNT_N    0x000000FFU
-#define SPI_MEM_CLKCNT_N_M  (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
-#define SPI_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI_MEM_CLKCNT_N_S  16
-/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+#define SPI_MEM_C_CLKCNT_N    0x000000FFU
+#define SPI_MEM_C_CLKCNT_N_M  (SPI_MEM_C_CLKCNT_N_V << SPI_MEM_C_CLKCNT_N_S)
+#define SPI_MEM_C_CLKCNT_N_V  0x000000FFU
+#define SPI_MEM_C_CLKCNT_N_S  16
+/** SPI_MEM_C_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
  *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
  *  clock.
  */
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S)
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+#define SPI_MEM_C_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_C_CLK_EQU_SYSCLK_M  (SPI_MEM_C_CLK_EQU_SYSCLK_V << SPI_MEM_C_CLK_EQU_SYSCLK_S)
+#define SPI_MEM_C_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_MEM_C_CLK_EQU_SYSCLK_S  31
 
-/** SPI_MEM_USER_REG register
+/** SPI_MEM_C_USER_REG register
  *  SPI0 user register.
  */
-#define SPI_MEM_USER_REG (DR_REG_SPI0_BASE + 0x18)
-/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_C_USER_REG (DR_REG_FLASH_SPI0_BASE + 0x18)
+/** SPI_MEM_C_CS_HOLD : R/W; bitpos: [6]; default: 0;
  *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
  */
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S)
-#define SPI_MEM_CS_HOLD_V  0x00000001U
-#define SPI_MEM_CS_HOLD_S  6
-/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_C_CS_HOLD    (BIT(6))
+#define SPI_MEM_C_CS_HOLD_M  (SPI_MEM_C_CS_HOLD_V << SPI_MEM_C_CS_HOLD_S)
+#define SPI_MEM_C_CS_HOLD_V  0x00000001U
+#define SPI_MEM_C_CS_HOLD_S  6
+/** SPI_MEM_C_CS_SETUP : R/W; bitpos: [7]; default: 0;
  *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
  */
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S)
-#define SPI_MEM_CS_SETUP_V  0x00000001U
-#define SPI_MEM_CS_SETUP_S  7
-/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+#define SPI_MEM_C_CS_SETUP    (BIT(7))
+#define SPI_MEM_C_CS_SETUP_M  (SPI_MEM_C_CS_SETUP_V << SPI_MEM_C_CS_SETUP_S)
+#define SPI_MEM_C_CS_SETUP_V  0x00000001U
+#define SPI_MEM_C_CS_SETUP_S  7
+/** SPI_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  The bit combined with SPI_MEM_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
  */
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S)
-#define SPI_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+#define SPI_MEM_C_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_C_CK_OUT_EDGE_M  (SPI_MEM_C_CK_OUT_EDGE_V << SPI_MEM_C_CK_OUT_EDGE_S)
+#define SPI_MEM_C_CK_OUT_EDGE_V  0x00000001U
+#define SPI_MEM_C_CK_OUT_EDGE_S  9
+/** SPI_MEM_C_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
  *  spi clock is disable in dummy phase when the bit is enable.
  */
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S)
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+#define SPI_MEM_C_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_C_USR_DUMMY_IDLE_M  (SPI_MEM_C_USR_DUMMY_IDLE_V << SPI_MEM_C_USR_DUMMY_IDLE_S)
+#define SPI_MEM_C_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_MEM_C_USR_DUMMY_IDLE_S  26
+/** SPI_MEM_C_USR_DUMMY : R/W; bitpos: [29]; default: 0;
  *  This bit enable the dummy phase of an operation.
  */
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S)
-#define SPI_MEM_USR_DUMMY_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_S  29
+#define SPI_MEM_C_USR_DUMMY    (BIT(29))
+#define SPI_MEM_C_USR_DUMMY_M  (SPI_MEM_C_USR_DUMMY_V << SPI_MEM_C_USR_DUMMY_S)
+#define SPI_MEM_C_USR_DUMMY_V  0x00000001U
+#define SPI_MEM_C_USR_DUMMY_S  29
 
-/** SPI_MEM_USER1_REG register
+/** SPI_MEM_C_USER1_REG register
  *  SPI0 user1 register.
  */
-#define SPI_MEM_USER1_REG (DR_REG_SPI0_BASE + 0x1c)
-/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+#define SPI_MEM_C_USER1_REG (DR_REG_FLASH_SPI0_BASE + 0x1c)
+/** SPI_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
  *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1).
  */
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1;
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN_M  (SPI_MEM_C_USR_DUMMY_CYCLELEN_V << SPI_MEM_C_USR_DUMMY_CYCLELEN_S)
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MEM_C_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1;
  *  SPI0 USR_CMD read or write data byte length -1
  */
-#define SPI_MEM_USR_DBYTELEN    0x00000007U
-#define SPI_MEM_USR_DBYTELEN_M  (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S)
-#define SPI_MEM_USR_DBYTELEN_V  0x00000007U
-#define SPI_MEM_USR_DBYTELEN_S  6
-/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+#define SPI_MEM_C_USR_DBYTELEN    0x00000007U
+#define SPI_MEM_C_USR_DBYTELEN_M  (SPI_MEM_C_USR_DBYTELEN_V << SPI_MEM_C_USR_DBYTELEN_S)
+#define SPI_MEM_C_USR_DBYTELEN_V  0x00000007U
+#define SPI_MEM_C_USR_DBYTELEN_S  6
+/** SPI_MEM_C_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
  *  The length in bits of address phase. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_M  (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S)
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
+#define SPI_MEM_C_USR_ADDR_BITLEN    0x0000003FU
+#define SPI_MEM_C_USR_ADDR_BITLEN_M  (SPI_MEM_C_USR_ADDR_BITLEN_V << SPI_MEM_C_USR_ADDR_BITLEN_S)
+#define SPI_MEM_C_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI_MEM_C_USR_ADDR_BITLEN_S  26
 
-/** SPI_MEM_USER2_REG register
+/** SPI_MEM_C_USER2_REG register
  *  SPI0 user2 register.
  */
-#define SPI_MEM_USER2_REG (DR_REG_SPI0_BASE + 0x20)
-/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+#define SPI_MEM_C_USER2_REG (DR_REG_FLASH_SPI0_BASE + 0x20)
+/** SPI_MEM_C_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command.
  */
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_M  (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S)
-#define SPI_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+#define SPI_MEM_C_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_MEM_C_USR_COMMAND_VALUE_M  (SPI_MEM_C_USR_COMMAND_VALUE_V << SPI_MEM_C_USR_COMMAND_VALUE_S)
+#define SPI_MEM_C_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_MEM_C_USR_COMMAND_VALUE_S  0
+/** SPI_MEM_C_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
  *  The length in bits of command phase. The register value shall be (bit_num-1)
  */
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_M  (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S)
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+#define SPI_MEM_C_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_MEM_C_USR_COMMAND_BITLEN_M  (SPI_MEM_C_USR_COMMAND_BITLEN_V << SPI_MEM_C_USR_COMMAND_BITLEN_S)
+#define SPI_MEM_C_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_MEM_C_USR_COMMAND_BITLEN_S  28
 
-/** SPI_MEM_MISC_REG register
+/** SPI_MEM_C_MISC_REG register
  *  SPI0 misc register
  */
-#define SPI_MEM_MISC_REG (DR_REG_SPI0_BASE + 0x34)
-/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0;
+#define SPI_MEM_C_MISC_REG (DR_REG_FLASH_SPI0_BASE + 0x34)
+/** SPI_MEM_C_FSUB_PIN : HRO; bitpos: [7]; default: 0;
  *  For SPI0,  flash is connected to SUBPINs.
  */
-#define SPI_MEM_FSUB_PIN    (BIT(7))
-#define SPI_MEM_FSUB_PIN_M  (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S)
-#define SPI_MEM_FSUB_PIN_V  0x00000001U
-#define SPI_MEM_FSUB_PIN_S  7
-/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0;
+#define SPI_MEM_C_FSUB_PIN    (BIT(7))
+#define SPI_MEM_C_FSUB_PIN_M  (SPI_MEM_C_FSUB_PIN_V << SPI_MEM_C_FSUB_PIN_S)
+#define SPI_MEM_C_FSUB_PIN_V  0x00000001U
+#define SPI_MEM_C_FSUB_PIN_S  7
+/** SPI_MEM_C_SSUB_PIN : HRO; bitpos: [8]; default: 0;
  *  For SPI0,  sram is connected to SUBPINs.
  */
-#define SPI_MEM_SSUB_PIN    (BIT(8))
-#define SPI_MEM_SSUB_PIN_M  (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S)
-#define SPI_MEM_SSUB_PIN_V  0x00000001U
-#define SPI_MEM_SSUB_PIN_S  8
-/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+#define SPI_MEM_C_SSUB_PIN    (BIT(8))
+#define SPI_MEM_C_SSUB_PIN_M  (SPI_MEM_C_SSUB_PIN_V << SPI_MEM_C_SSUB_PIN_S)
+#define SPI_MEM_C_SSUB_PIN_V  0x00000001U
+#define SPI_MEM_C_SSUB_PIN_S  8
+/** SPI_MEM_C_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
  *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
  */
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S)
-#define SPI_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+#define SPI_MEM_C_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_C_CK_IDLE_EDGE_M  (SPI_MEM_C_CK_IDLE_EDGE_V << SPI_MEM_C_CK_IDLE_EDGE_S)
+#define SPI_MEM_C_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_MEM_C_CK_IDLE_EDGE_S  9
+/** SPI_MEM_C_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
  *  SPI_CS line keep low when the bit is set.
  */
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S)
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+#define SPI_MEM_C_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_C_CS_KEEP_ACTIVE_M  (SPI_MEM_C_CS_KEEP_ACTIVE_V << SPI_MEM_C_CS_KEEP_ACTIVE_S)
+#define SPI_MEM_C_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_MEM_C_CS_KEEP_ACTIVE_S  10
 
-/** SPI_MEM_CACHE_FCTRL_REG register
+/** SPI_MEM_C_CACHE_FCTRL_REG register
  *  SPI0 bit mode control register.
  */
-#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI0_BASE + 0x3c)
-/** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1;
+#define SPI_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x3c)
+/** SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1;
  *  Set this bit to check AXI read/write the same address region.
  */
-#define SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_M  (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S)
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x00000001U
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
-/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1;
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_M  (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S)
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_V  0x00000001U
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_S  30
+/** SPI_MEM_C_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1;
  *  Set this bit to close AXI read/write transfer to MSPI, which means that only
  *  SLV_ERR will be replied to BRESP/RRESP.
  */
-#define SPI_CLOSE_AXI_INF_EN    (BIT(31))
-#define SPI_CLOSE_AXI_INF_EN_M  (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S)
-#define SPI_CLOSE_AXI_INF_EN_V  0x00000001U
-#define SPI_CLOSE_AXI_INF_EN_S  31
+#define SPI_MEM_C_CLOSE_AXI_INF_EN    (BIT(31))
+#define SPI_MEM_C_CLOSE_AXI_INF_EN_M  (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S)
+#define SPI_MEM_C_CLOSE_AXI_INF_EN_V  0x00000001U
+#define SPI_MEM_C_CLOSE_AXI_INF_EN_S  31
 
-/** SPI_MEM_SRAM_CMD_REG register
+/** SPI_MEM_C_SRAM_CMD_REG register
  *  SPI0 external RAM mode control register
  */
-#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI0_BASE + 0x44)
-/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0;
+#define SPI_MEM_C_SRAM_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x44)
+/** SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
  *  the level of SPI_DQS is output by the MSPI controller.
  */
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S)
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/** SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0;
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/** SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
  *  the level of SPI_IO[7:0] is output by the MSPI controller.
  */
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M  (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S)
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/** SPI_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1;
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/** SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1;
  *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are
  *  always 1. 0: Others.
  */
-#define SPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_M  (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S)
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_S  30
-/** SPI_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1;
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_M  (SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1;
  *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0]
  *  are always 1. 0: Others.
  */
-#define SPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_M  (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S)
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_S  31
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_M  (SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S  31
 
-/** SPI_MEM_FSM_REG register
+/** SPI_MEM_C_FSM_REG register
  *  SPI0 FSM status register
  */
-#define SPI_MEM_FSM_REG (DR_REG_SPI0_BASE + 0x54)
-/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
+#define SPI_MEM_C_FSM_REG (DR_REG_FLASH_SPI0_BASE + 0x54)
+/** SPI_MEM_C_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
  *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
  */
-#define SPI_MEM_LOCK_DELAY_TIME    0x0000001FU
-#define SPI_MEM_LOCK_DELAY_TIME_M  (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S)
-#define SPI_MEM_LOCK_DELAY_TIME_V  0x0000001FU
-#define SPI_MEM_LOCK_DELAY_TIME_S  7
+#define SPI_MEM_C_LOCK_DELAY_TIME    0x0000001FU
+#define SPI_MEM_C_LOCK_DELAY_TIME_M  (SPI_MEM_C_LOCK_DELAY_TIME_V << SPI_MEM_C_LOCK_DELAY_TIME_S)
+#define SPI_MEM_C_LOCK_DELAY_TIME_V  0x0000001FU
+#define SPI_MEM_C_LOCK_DELAY_TIME_S  7
 
-/** SPI_MEM_INT_ENA_REG register
+/** SPI_MEM_C_INT_ENA_REG register
  *  SPI0 interrupt enable register
  */
-#define SPI_MEM_INT_ENA_REG (DR_REG_SPI0_BASE + 0xc0)
-/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI_MEM_C_INT_ENA_REG (DR_REG_FLASH_SPI0_BASE + 0xc0)
+/** SPI_MEM_C_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI_MEM_C_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI_MEM_C_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_ENA_M  (SPI_MEM_C_SLV_ST_END_INT_ENA_V << SPI_MEM_C_SLV_ST_END_INT_ENA_S)
+#define SPI_MEM_C_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_ENA_S  3
+/** SPI_MEM_C_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI_MEM_C_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S)
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI_MEM_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0;
- *  The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_C_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_ENA_M  (SPI_MEM_C_MST_ST_END_INT_ENA_V << SPI_MEM_C_MST_ST_END_INT_ENA_S)
+#define SPI_MEM_C_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_ENA_S  4
+/** SPI_MEM_C_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  The enable bit for SPI_MEM_C_ECC_ERR_INT interrupt.
  */
-#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_M  (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S)
-#define SPI_MEM_ECC_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_ENA_S  5
-/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
+#define SPI_MEM_C_ECC_ERR_INT_ENA    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_ENA_M  (SPI_MEM_C_ECC_ERR_INT_ENA_V << SPI_MEM_C_ECC_ERR_INT_ENA_S)
+#define SPI_MEM_C_ECC_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_ENA_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI_MEM_C_PMS_REJECT_INT interrupt.
  */
-#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_M  (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S)
-#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+#define SPI_MEM_C_PMS_REJECT_INT_ENA    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_ENA_M  (SPI_MEM_C_PMS_REJECT_INT_ENA_V << SPI_MEM_C_PMS_REJECT_INT_ENA_S)
+#define SPI_MEM_C_PMS_REJECT_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_ENA_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M  (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S  9
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_M  (SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S  9
 
-/** SPI_MEM_INT_CLR_REG register
+/** SPI_MEM_C_INT_CLR_REG register
  *  SPI0 interrupt clear register
  */
-#define SPI_MEM_INT_CLR_REG (DR_REG_SPI0_BASE + 0xc4)
-/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI_MEM_C_INT_CLR_REG (DR_REG_FLASH_SPI0_BASE + 0xc4)
+/** SPI_MEM_C_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI_MEM_C_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI_MEM_C_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_CLR_M  (SPI_MEM_C_SLV_ST_END_INT_CLR_V << SPI_MEM_C_SLV_ST_END_INT_CLR_S)
+#define SPI_MEM_C_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_CLR_S  3
+/** SPI_MEM_C_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI_MEM_C_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S)
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI_MEM_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0;
- *  The clear bit for SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_C_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_CLR_M  (SPI_MEM_C_MST_ST_END_INT_CLR_V << SPI_MEM_C_MST_ST_END_INT_CLR_S)
+#define SPI_MEM_C_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_CLR_S  4
+/** SPI_MEM_C_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0;
+ *  The clear bit for SPI_MEM_C_ECC_ERR_INT interrupt.
  */
-#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_M  (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S)
-#define SPI_MEM_ECC_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_CLR_S  5
-/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.
+#define SPI_MEM_C_ECC_ERR_INT_CLR    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_CLR_M  (SPI_MEM_C_ECC_ERR_INT_CLR_V << SPI_MEM_C_ECC_ERR_INT_CLR_S)
+#define SPI_MEM_C_ECC_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_CLR_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI_MEM_C_PMS_REJECT_INT interrupt.
  */
-#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_M  (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S)
-#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+#define SPI_MEM_C_PMS_REJECT_INT_CLR    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_CLR_M  (SPI_MEM_C_PMS_REJECT_INT_CLR_V << SPI_MEM_C_PMS_REJECT_INT_CLR_S)
+#define SPI_MEM_C_PMS_REJECT_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_CLR_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
- *  The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
- *  The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_M  (SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S  9
 
-/** SPI_MEM_INT_RAW_REG register
+/** SPI_MEM_C_INT_RAW_REG register
  *  SPI0 interrupt raw register
  */
-#define SPI_MEM_INT_RAW_REG (DR_REG_SPI0_BASE + 0xc8)
-/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+#define SPI_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI0_BASE + 0xc8)
+/** SPI_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
  *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
  *  Others
  */
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+#define SPI_MEM_C_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_RAW_M  (SPI_MEM_C_SLV_ST_END_INT_RAW_V << SPI_MEM_C_SLV_ST_END_INT_RAW_S)
+#define SPI_MEM_C_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_RAW_S  3
+/** SPI_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
  *  changed from non idle state to idle state. 0: Others.
  */
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S)
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI_MEM_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0;
- *  The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set
- *  and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
- *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When
- *  SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is
+#define SPI_MEM_C_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_RAW_M  (SPI_MEM_C_MST_ST_END_INT_RAW_V << SPI_MEM_C_MST_ST_END_INT_RAW_S)
+#define SPI_MEM_C_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_RAW_S  4
+/** SPI_MEM_C_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0;
+ *  The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set
+ *  and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+ *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When
+ *  SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is
  *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
- *  than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and
- *  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+ *  than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and
+ *  SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
  *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
- *  SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN
+ *  SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN
  *  are cleared, this bit will not be triggered.
  */
-#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_M  (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S)
-#define SPI_MEM_ECC_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_RAW_S  5
-/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+#define SPI_MEM_C_ECC_ERR_INT_RAW    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_RAW_M  (SPI_MEM_C_ECC_ERR_INT_RAW_V << SPI_MEM_C_ECC_ERR_INT_RAW_S)
+#define SPI_MEM_C_ECC_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_RAW_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
  *  rejected. 0: Others.
  */
-#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_M  (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S)
-#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+#define SPI_MEM_C_PMS_REJECT_INT_RAW    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_RAW_M  (SPI_MEM_C_PMS_REJECT_INT_RAW_V << SPI_MEM_C_PMS_REJECT_INT_RAW_S)
+#define SPI_MEM_C_PMS_REJECT_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_RAW_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
  *  address is invalid by compared to MMU configuration. 0: Others.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0;
- *  The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
  *  flash request is received. 0: Others.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0;
- *  The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
  *  address is invalid by compared to MMU configuration. 0: Others.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_M  (SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S  9
 
-/** SPI_MEM_INT_ST_REG register
+/** SPI_MEM_C_INT_ST_REG register
  *  SPI0 interrupt status register
  */
-#define SPI_MEM_INT_ST_REG (DR_REG_SPI0_BASE + 0xcc)
-/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI_MEM_C_INT_ST_REG (DR_REG_FLASH_SPI0_BASE + 0xcc)
+/** SPI_MEM_C_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI_MEM_C_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S)
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI_MEM_C_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_ST_M  (SPI_MEM_C_SLV_ST_END_INT_ST_V << SPI_MEM_C_SLV_ST_END_INT_ST_S)
+#define SPI_MEM_C_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_ST_S  3
+/** SPI_MEM_C_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI_MEM_C_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S)
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/** SPI_MEM_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0;
- *  The status bit for SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_C_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_ST_M  (SPI_MEM_C_MST_ST_END_INT_ST_V << SPI_MEM_C_MST_ST_END_INT_ST_S)
+#define SPI_MEM_C_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_ST_S  4
+/** SPI_MEM_C_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0;
+ *  The status bit for SPI_MEM_C_ECC_ERR_INT interrupt.
  */
-#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_M  (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S)
-#define SPI_MEM_ECC_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_ST_S  5
-/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0;
- *  The status bit for SPI_MEM_PMS_REJECT_INT interrupt.
+#define SPI_MEM_C_ECC_ERR_INT_ST    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_ST_M  (SPI_MEM_C_ECC_ERR_INT_ST_V << SPI_MEM_C_ECC_ERR_INT_ST_S)
+#define SPI_MEM_C_ECC_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_ST_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI_MEM_C_PMS_REJECT_INT interrupt.
  */
-#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_M  (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S)
-#define SPI_MEM_PMS_REJECT_INT_ST_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_ST_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+#define SPI_MEM_C_PMS_REJECT_INT_ST    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_ST_M  (SPI_MEM_C_PMS_REJECT_INT_ST_V << SPI_MEM_C_PMS_REJECT_INT_ST_S)
+#define SPI_MEM_C_PMS_REJECT_INT_ST_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_ST_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_RADDR_ERR_INT_ST_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_M  (SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S  9
 
-/** SPI_MEM_DDR_REG register
+/** SPI_MEM_C_DDR_REG register
  *  SPI0 flash DDR mode control register
  */
-#define SPI_MEM_DDR_REG (DR_REG_SPI0_BASE + 0xd4)
-/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
+#define SPI_MEM_C_DDR_REG (DR_REG_FLASH_SPI0_BASE + 0xd4)
+/** SPI_MEM_C_FMEM__DDR_EN : HRO; bitpos: [0]; default: 0;
  *  1: in DDR mode,  0 in SDR mode
  */
-#define SPI_FMEM_DDR_EN    (BIT(0))
-#define SPI_FMEM_DDR_EN_M  (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S)
-#define SPI_FMEM_DDR_EN_V  0x00000001U
-#define SPI_FMEM_DDR_EN_S  0
-/** SPI_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
+#define SPI_MEM_C_FMEM__DDR_EN    (BIT(0))
+#define SPI_MEM_C_FMEM__DDR_EN_M  (SPI_MEM_C_FMEM__DDR_EN_V << SPI_MEM_C_FMEM__DDR_EN_S)
+#define SPI_MEM_C_FMEM__DDR_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_EN_S  0
+/** SPI_MEM_C_FMEM__VAR_DUMMY : HRO; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi DDR mode.
  */
-#define SPI_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_FMEM_VAR_DUMMY_M  (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S)
-#define SPI_FMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_FMEM_VAR_DUMMY_S  1
-/** SPI_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
+#define SPI_MEM_C_FMEM__VAR_DUMMY    (BIT(1))
+#define SPI_MEM_C_FMEM__VAR_DUMMY_M  (SPI_MEM_C_FMEM__VAR_DUMMY_V << SPI_MEM_C_FMEM__VAR_DUMMY_S)
+#define SPI_MEM_C_FMEM__VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_C_FMEM__VAR_DUMMY_S  1
+/** SPI_MEM_C_FMEM__DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi DDR mode.
  */
-#define SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_FMEM_DDR_RDAT_SWP_M  (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S)
-#define SPI_FMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_FMEM_DDR_RDAT_SWP_S  2
-/** SPI_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_M  (SPI_MEM_C_FMEM__DDR_RDAT_SWP_V << SPI_MEM_C_FMEM__DDR_RDAT_SWP_S)
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_S  2
+/** SPI_MEM_C_FMEM__DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi DDR mode.
  */
-#define SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_FMEM_DDR_WDAT_SWP_M  (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S)
-#define SPI_FMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_FMEM_DDR_WDAT_SWP_S  3
-/** SPI_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_M  (SPI_MEM_C_FMEM__DDR_WDAT_SWP_V << SPI_MEM_C_FMEM__DDR_WDAT_SWP_S)
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_S  3
+/** SPI_MEM_C_FMEM__DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when DDR mode.
  */
-#define SPI_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_FMEM_DDR_CMD_DIS_M  (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S)
-#define SPI_FMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_FMEM_DDR_CMD_DIS_S  4
-/** SPI_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS_M  (SPI_MEM_C_FMEM__DDR_CMD_DIS_V << SPI_MEM_C_FMEM__DDR_CMD_DIS_S)
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS_S  4
+/** SPI_MEM_C_FMEM__OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the panda device.
  */
-#define SPI_FMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_FMEM_OUTMINBYTELEN_M  (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S)
-#define SPI_FMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_FMEM_OUTMINBYTELEN_S  5
-/** SPI_FMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN_M  (SPI_MEM_C_FMEM__OUTMINBYTELEN_V << SPI_MEM_C_FMEM__OUTMINBYTELEN_S)
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN_S  5
+/** SPI_MEM_C_FMEM__TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
  *  accesses to flash.
  */
-#define SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_FMEM_TX_DDR_MSK_EN_M  (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S)
-#define SPI_FMEM_TX_DDR_MSK_EN_V  0x00000001U
-#define SPI_FMEM_TX_DDR_MSK_EN_S  12
-/** SPI_FMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_M  (SPI_MEM_C_FMEM__TX_DDR_MSK_EN_V << SPI_MEM_C_FMEM__TX_DDR_MSK_EN_S)
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_S  12
+/** SPI_MEM_C_FMEM__RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
  *  accesses to flash.
  */
-#define SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_FMEM_RX_DDR_MSK_EN_M  (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S)
-#define SPI_FMEM_RX_DDR_MSK_EN_V  0x00000001U
-#define SPI_FMEM_RX_DDR_MSK_EN_S  13
-/** SPI_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_M  (SPI_MEM_C_FMEM__RX_DDR_MSK_EN_V << SPI_MEM_C_FMEM__RX_DDR_MSK_EN_S)
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_S  13
+/** SPI_MEM_C_FMEM__USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_FMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_FMEM_USR_DDR_DQS_THD_M  (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S)
-#define SPI_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_FMEM_USR_DDR_DQS_THD_S  14
-/** SPI_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_M  (SPI_MEM_C_FMEM__USR_DDR_DQS_THD_V << SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S)
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S  14
+/** SPI_MEM_C_FMEM__DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_FMEM_DDR_DQS_LOOP_M  (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S)
-#define SPI_FMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_FMEM_DDR_DQS_LOOP_S  21
-/** SPI_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_M  (SPI_MEM_C_FMEM__DDR_DQS_LOOP_V << SPI_MEM_C_FMEM__DDR_DQS_LOOP_S)
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_S  21
+/** SPI_MEM_C_FMEM__CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_FMEM_CLK_DIFF_EN_M  (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S)
-#define SPI_FMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_FMEM_CLK_DIFF_EN_S  24
-/** SPI_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN_M  (SPI_MEM_C_FMEM__CLK_DIFF_EN_V << SPI_MEM_C_FMEM__CLK_DIFF_EN_S)
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN_S  24
+/** SPI_MEM_C_FMEM__DQS_CA_IN : HRO; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_FMEM_DQS_CA_IN_M  (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S)
-#define SPI_FMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_FMEM_DQS_CA_IN_S  26
-/** SPI_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
+#define SPI_MEM_C_FMEM__DQS_CA_IN    (BIT(26))
+#define SPI_MEM_C_FMEM__DQS_CA_IN_M  (SPI_MEM_C_FMEM__DQS_CA_IN_V << SPI_MEM_C_FMEM__DQS_CA_IN_S)
+#define SPI_MEM_C_FMEM__DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_C_FMEM__DQS_CA_IN_S  26
+/** SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_M  (SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_V << SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_C_FMEM__CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to flash. .
  */
-#define SPI_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_FMEM_CLK_DIFF_INV_M  (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S)
-#define SPI_FMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_FMEM_CLK_DIFF_INV_S  28
-/** SPI_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV_M  (SPI_MEM_C_FMEM__CLK_DIFF_INV_V << SPI_MEM_C_FMEM__CLK_DIFF_INV_S)
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV_S  28
+/** SPI_MEM_C_FMEM__OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
  */
-#define SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_FMEM_OCTA_RAM_ADDR_M  (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S)
-#define SPI_FMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_FMEM_OCTA_RAM_ADDR_S  29
-/** SPI_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_M  (SPI_MEM_C_FMEM__OCTA_RAM_ADDR_V << SPI_MEM_C_FMEM__OCTA_RAM_ADDR_S)
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_S  29
+/** SPI_MEM_C_FMEM__HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_FMEM_HYPERBUS_CA_M  (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S)
-#define SPI_FMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_FMEM_HYPERBUS_CA_S  30
+#define SPI_MEM_C_FMEM__HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_C_FMEM__HYPERBUS_CA_M  (SPI_MEM_C_FMEM__HYPERBUS_CA_V << SPI_MEM_C_FMEM__HYPERBUS_CA_S)
+#define SPI_MEM_C_FMEM__HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_C_FMEM__HYPERBUS_CA_S  30
 
-/** SPI_SMEM_DDR_REG register
+/** SPI_MEM_C_SMEM_DDR_REG register
  *  SPI0 external RAM DDR mode control register
  */
-#define SPI_SMEM_DDR_REG (DR_REG_SPI0_BASE + 0xd8)
-/** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
+#define SPI_MEM_C_SMEM_DDR_REG (DR_REG_FLASH_SPI0_BASE + 0xd8)
+/** SPI_MEM_C_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
  *  1: in DDR mode,  0 in SDR mode
  */
-#define SPI_SMEM_DDR_EN    (BIT(0))
-#define SPI_SMEM_DDR_EN_M  (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S)
-#define SPI_SMEM_DDR_EN_V  0x00000001U
-#define SPI_SMEM_DDR_EN_S  0
-/** SPI_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
+#define SPI_MEM_C_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_C_SMEM_DDR_EN_M  (SPI_MEM_C_SMEM_DDR_EN_V << SPI_MEM_C_SMEM_DDR_EN_S)
+#define SPI_MEM_C_SMEM_DDR_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_EN_S  0
+/** SPI_MEM_C_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi DDR mode.
  */
-#define SPI_SMEM_VAR_DUMMY    (BIT(1))
-#define SPI_SMEM_VAR_DUMMY_M  (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S)
-#define SPI_SMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_SMEM_VAR_DUMMY_S  1
-/** SPI_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
+#define SPI_MEM_C_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_C_SMEM_VAR_DUMMY_M  (SPI_MEM_C_SMEM_VAR_DUMMY_V << SPI_MEM_C_SMEM_VAR_DUMMY_S)
+#define SPI_MEM_C_SMEM_VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_C_SMEM_VAR_DUMMY_S  1
+/** SPI_MEM_C_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi DDR mode.
  */
-#define SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_SMEM_DDR_RDAT_SWP_M  (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S)
-#define SPI_SMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_SMEM_DDR_RDAT_SWP_S  2
-/** SPI_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_M  (SPI_MEM_C_SMEM_DDR_RDAT_SWP_V << SPI_MEM_C_SMEM_DDR_RDAT_SWP_S)
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_S  2
+/** SPI_MEM_C_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi DDR mode.
  */
-#define SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_SMEM_DDR_WDAT_SWP_M  (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S)
-#define SPI_SMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_SMEM_DDR_WDAT_SWP_S  3
-/** SPI_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_M  (SPI_MEM_C_SMEM_DDR_WDAT_SWP_V << SPI_MEM_C_SMEM_DDR_WDAT_SWP_S)
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_S  3
+/** SPI_MEM_C_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when DDR mode.
  */
-#define SPI_SMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_SMEM_DDR_CMD_DIS_M  (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S)
-#define SPI_SMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_SMEM_DDR_CMD_DIS_S  4
-/** SPI_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS_M  (SPI_MEM_C_SMEM_DDR_CMD_DIS_V << SPI_MEM_C_SMEM_DDR_CMD_DIS_S)
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS_S  4
+/** SPI_MEM_C_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the DDR psram.
  */
-#define SPI_SMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_SMEM_OUTMINBYTELEN_M  (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S)
-#define SPI_SMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_SMEM_OUTMINBYTELEN_S  5
-/** SPI_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN_M  (SPI_MEM_C_SMEM_OUTMINBYTELEN_V << SPI_MEM_C_SMEM_OUTMINBYTELEN_S)
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN_S  5
+/** SPI_MEM_C_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
  *  accesses to external RAM.
  */
-#define SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_SMEM_TX_DDR_MSK_EN_M  (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S)
-#define SPI_SMEM_TX_DDR_MSK_EN_V  0x00000001U
-#define SPI_SMEM_TX_DDR_MSK_EN_S  12
-/** SPI_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_M  (SPI_MEM_C_SMEM_TX_DDR_MSK_EN_V << SPI_MEM_C_SMEM_TX_DDR_MSK_EN_S)
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_S  12
+/** SPI_MEM_C_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
  *  accesses to external RAM.
  */
-#define SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_SMEM_RX_DDR_MSK_EN_M  (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S)
-#define SPI_SMEM_RX_DDR_MSK_EN_V  0x00000001U
-#define SPI_SMEM_RX_DDR_MSK_EN_S  13
-/** SPI_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_M  (SPI_MEM_C_SMEM_RX_DDR_MSK_EN_V << SPI_MEM_C_SMEM_RX_DDR_MSK_EN_S)
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_S  13
+/** SPI_MEM_C_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_SMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_SMEM_USR_DDR_DQS_THD_M  (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S)
-#define SPI_SMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_SMEM_USR_DDR_DQS_THD_S  14
-/** SPI_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_M  (SPI_MEM_C_SMEM_USR_DDR_DQS_THD_V << SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S)
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S  14
+/** SPI_MEM_C_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_SMEM_DDR_DQS_LOOP_M  (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S)
-#define SPI_SMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_SMEM_DDR_DQS_LOOP_S  21
-/** SPI_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_M  (SPI_MEM_C_SMEM_DDR_DQS_LOOP_V << SPI_MEM_C_SMEM_DDR_DQS_LOOP_S)
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_S  21
+/** SPI_MEM_C_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_SMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_SMEM_CLK_DIFF_EN_M  (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S)
-#define SPI_SMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_SMEM_CLK_DIFF_EN_S  24
-/** SPI_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN_M  (SPI_MEM_C_SMEM_CLK_DIFF_EN_V << SPI_MEM_C_SMEM_CLK_DIFF_EN_S)
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN_S  24
+/** SPI_MEM_C_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_SMEM_DQS_CA_IN    (BIT(26))
-#define SPI_SMEM_DQS_CA_IN_M  (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S)
-#define SPI_SMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_SMEM_DQS_CA_IN_S  26
-/** SPI_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
+#define SPI_MEM_C_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_C_SMEM_DQS_CA_IN_M  (SPI_MEM_C_SMEM_DQS_CA_IN_V << SPI_MEM_C_SMEM_DQS_CA_IN_S)
+#define SPI_MEM_C_SMEM_DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_C_SMEM_DQS_CA_IN_S  26
+/** SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_M  (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_C_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to external RAM. .
  */
-#define SPI_SMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_SMEM_CLK_DIFF_INV_M  (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S)
-#define SPI_SMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_SMEM_CLK_DIFF_INV_S  28
-/** SPI_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV_M  (SPI_MEM_C_SMEM_CLK_DIFF_INV_V << SPI_MEM_C_SMEM_CLK_DIFF_INV_S)
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV_S  28
+/** SPI_MEM_C_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to external RAM, which
  *  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
  *  1'b0}.
  */
-#define SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_SMEM_OCTA_RAM_ADDR_M  (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S)
-#define SPI_SMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_SMEM_OCTA_RAM_ADDR_S  29
-/** SPI_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_M  (SPI_MEM_C_SMEM_OCTA_RAM_ADDR_V << SPI_MEM_C_SMEM_OCTA_RAM_ADDR_S)
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_S  29
+/** SPI_MEM_C_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to external RAM, which
  *  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_SMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_SMEM_HYPERBUS_CA_M  (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S)
-#define SPI_SMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_SMEM_HYPERBUS_CA_S  30
+#define SPI_MEM_C_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_C_SMEM_HYPERBUS_CA_M  (SPI_MEM_C_SMEM_HYPERBUS_CA_V << SPI_MEM_C_SMEM_HYPERBUS_CA_S)
+#define SPI_MEM_C_SMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_C_SMEM_HYPERBUS_CA_S  30
 
-/** SPI_FMEM_PMS0_ATTR_REG register
+/** SPI_MEM_C_FMEM__PMS0_ATTR_REG register
  *  MSPI flash PMS section 0 attribute register
  */
-#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI0_BASE + 0x100)
-/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_FMEM__PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x100)
+/** SPI_MEM_C_FMEM__PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 0 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS0_RD_ATTR_M  (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S)
-#define SPI_FMEM_PMS0_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS0_RD_ATTR_S  0
-/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS0_RD_ATTR_V << SPI_MEM_C_FMEM__PMS0_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 0 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS0_WR_ATTR_M  (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S)
-#define SPI_FMEM_PMS0_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS0_WR_ATTR_S  1
-/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS0_WR_ATTR_V << SPI_MEM_C_FMEM__PMS0_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS0_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and
- *  SPI_FMEM_PMS0_SIZE_REG.
+ *  section 0 is configured by registers SPI_MEM_C_FMEM__PMS0_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS0_SIZE_REG.
  */
-#define SPI_FMEM_PMS0_ECC    (BIT(2))
-#define SPI_FMEM_PMS0_ECC_M  (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S)
-#define SPI_FMEM_PMS0_ECC_V  0x00000001U
-#define SPI_FMEM_PMS0_ECC_S  2
+#define SPI_MEM_C_FMEM__PMS0_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS0_ECC_M  (SPI_MEM_C_FMEM__PMS0_ECC_V << SPI_MEM_C_FMEM__PMS0_ECC_S)
+#define SPI_MEM_C_FMEM__PMS0_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS0_ECC_S  2
 
-/** SPI_FMEM_PMS1_ATTR_REG register
+/** SPI_MEM_C_FMEM__PMS1_ATTR_REG register
  *  MSPI flash PMS section 1 attribute register
  */
-#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI0_BASE + 0x104)
-/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_FMEM__PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x104)
+/** SPI_MEM_C_FMEM__PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 1 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS1_RD_ATTR_M  (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S)
-#define SPI_FMEM_PMS1_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS1_RD_ATTR_S  0
-/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS1_RD_ATTR_V << SPI_MEM_C_FMEM__PMS1_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 1 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS1_WR_ATTR_M  (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S)
-#define SPI_FMEM_PMS1_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS1_WR_ATTR_S  1
-/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS1_WR_ATTR_V << SPI_MEM_C_FMEM__PMS1_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS1_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and
- *  SPI_FMEM_PMS1_SIZE_REG.
+ *  section 1 is configured by registers SPI_MEM_C_FMEM__PMS1_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS1_SIZE_REG.
  */
-#define SPI_FMEM_PMS1_ECC    (BIT(2))
-#define SPI_FMEM_PMS1_ECC_M  (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S)
-#define SPI_FMEM_PMS1_ECC_V  0x00000001U
-#define SPI_FMEM_PMS1_ECC_S  2
+#define SPI_MEM_C_FMEM__PMS1_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS1_ECC_M  (SPI_MEM_C_FMEM__PMS1_ECC_V << SPI_MEM_C_FMEM__PMS1_ECC_S)
+#define SPI_MEM_C_FMEM__PMS1_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS1_ECC_S  2
 
-/** SPI_FMEM_PMS2_ATTR_REG register
+/** SPI_MEM_C_FMEM__PMS2_ATTR_REG register
  *  MSPI flash PMS section 2 attribute register
  */
-#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI0_BASE + 0x108)
-/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_FMEM__PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x108)
+/** SPI_MEM_C_FMEM__PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 2 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS2_RD_ATTR_M  (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S)
-#define SPI_FMEM_PMS2_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS2_RD_ATTR_S  0
-/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS2_RD_ATTR_V << SPI_MEM_C_FMEM__PMS2_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 2 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS2_WR_ATTR_M  (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S)
-#define SPI_FMEM_PMS2_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS2_WR_ATTR_S  1
-/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS2_WR_ATTR_V << SPI_MEM_C_FMEM__PMS2_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS2_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and
- *  SPI_FMEM_PMS2_SIZE_REG.
+ *  section 2 is configured by registers SPI_MEM_C_FMEM__PMS2_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS2_SIZE_REG.
  */
-#define SPI_FMEM_PMS2_ECC    (BIT(2))
-#define SPI_FMEM_PMS2_ECC_M  (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S)
-#define SPI_FMEM_PMS2_ECC_V  0x00000001U
-#define SPI_FMEM_PMS2_ECC_S  2
+#define SPI_MEM_C_FMEM__PMS2_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS2_ECC_M  (SPI_MEM_C_FMEM__PMS2_ECC_V << SPI_MEM_C_FMEM__PMS2_ECC_S)
+#define SPI_MEM_C_FMEM__PMS2_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS2_ECC_S  2
 
-/** SPI_FMEM_PMS3_ATTR_REG register
+/** SPI_MEM_C_FMEM__PMS3_ATTR_REG register
  *  MSPI flash PMS section 3 attribute register
  */
-#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI0_BASE + 0x10c)
-/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_FMEM__PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x10c)
+/** SPI_MEM_C_FMEM__PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 3 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS3_RD_ATTR_M  (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S)
-#define SPI_FMEM_PMS3_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS3_RD_ATTR_S  0
-/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS3_RD_ATTR_V << SPI_MEM_C_FMEM__PMS3_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 3 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS3_WR_ATTR_M  (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S)
-#define SPI_FMEM_PMS3_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS3_WR_ATTR_S  1
-/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS3_WR_ATTR_V << SPI_MEM_C_FMEM__PMS3_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS3_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and
- *  SPI_FMEM_PMS3_SIZE_REG.
+ *  section 3 is configured by registers SPI_MEM_C_FMEM__PMS3_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS3_SIZE_REG.
  */
-#define SPI_FMEM_PMS3_ECC    (BIT(2))
-#define SPI_FMEM_PMS3_ECC_M  (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S)
-#define SPI_FMEM_PMS3_ECC_V  0x00000001U
-#define SPI_FMEM_PMS3_ECC_S  2
+#define SPI_MEM_C_FMEM__PMS3_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS3_ECC_M  (SPI_MEM_C_FMEM__PMS3_ECC_V << SPI_MEM_C_FMEM__PMS3_ECC_S)
+#define SPI_MEM_C_FMEM__PMS3_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS3_ECC_S  2
 
-/** SPI_FMEM_PMS0_ADDR_REG register
+/** SPI_MEM_C_FMEM__PMS0_ADDR_REG register
  *  SPI1 flash PMS section 0 start address register
  */
-#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI0_BASE + 0x110)
-/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_FMEM__PMS0_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x110)
+/** SPI_MEM_C_FMEM__PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 0 start address value
  */
-#define SPI_FMEM_PMS0_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS0_ADDR_S_M  (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S)
-#define SPI_FMEM_PMS0_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS0_ADDR_S_S  0
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S_M  (SPI_MEM_C_FMEM__PMS0_ADDR_S_V << SPI_MEM_C_FMEM__PMS0_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S_S  0
 
-/** SPI_FMEM_PMS1_ADDR_REG register
+/** SPI_MEM_C_FMEM__PMS1_ADDR_REG register
  *  SPI1 flash PMS section 1 start address register
  */
-#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI0_BASE + 0x114)
-/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_FMEM__PMS1_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x114)
+/** SPI_MEM_C_FMEM__PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 1 start address value
  */
-#define SPI_FMEM_PMS1_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS1_ADDR_S_M  (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S)
-#define SPI_FMEM_PMS1_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS1_ADDR_S_S  0
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S_M  (SPI_MEM_C_FMEM__PMS1_ADDR_S_V << SPI_MEM_C_FMEM__PMS1_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S_S  0
 
-/** SPI_FMEM_PMS2_ADDR_REG register
+/** SPI_MEM_C_FMEM__PMS2_ADDR_REG register
  *  SPI1 flash PMS section 2 start address register
  */
-#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI0_BASE + 0x118)
-/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_FMEM__PMS2_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x118)
+/** SPI_MEM_C_FMEM__PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 2 start address value
  */
-#define SPI_FMEM_PMS2_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS2_ADDR_S_M  (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S)
-#define SPI_FMEM_PMS2_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS2_ADDR_S_S  0
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S_M  (SPI_MEM_C_FMEM__PMS2_ADDR_S_V << SPI_MEM_C_FMEM__PMS2_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S_S  0
 
-/** SPI_FMEM_PMS3_ADDR_REG register
+/** SPI_MEM_C_FMEM__PMS3_ADDR_REG register
  *  SPI1 flash PMS section 3 start address register
  */
-#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI0_BASE + 0x11c)
-/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_FMEM__PMS3_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x11c)
+/** SPI_MEM_C_FMEM__PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 3 start address value
  */
-#define SPI_FMEM_PMS3_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS3_ADDR_S_M  (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S)
-#define SPI_FMEM_PMS3_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS3_ADDR_S_S  0
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S_M  (SPI_MEM_C_FMEM__PMS3_ADDR_S_V << SPI_MEM_C_FMEM__PMS3_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S_S  0
 
-/** SPI_FMEM_PMS0_SIZE_REG register
+/** SPI_MEM_C_FMEM__PMS0_SIZE_REG register
  *  SPI1 flash PMS section 0 start address register
  */
-#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI0_BASE + 0x120)
-/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S,
- *  SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE)
+#define SPI_MEM_C_FMEM__PMS0_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x120)
+/** SPI_MEM_C_FMEM__PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 0 address region is (SPI_MEM_C_FMEM__PMS0_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS0_ADDR_S + SPI_MEM_C_FMEM__PMS0_SIZE)
  */
-#define SPI_FMEM_PMS0_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS0_SIZE_M  (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S)
-#define SPI_FMEM_PMS0_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS0_SIZE_S  0
+#define SPI_MEM_C_FMEM__PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS0_SIZE_M  (SPI_MEM_C_FMEM__PMS0_SIZE_V << SPI_MEM_C_FMEM__PMS0_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS0_SIZE_S  0
 
-/** SPI_FMEM_PMS1_SIZE_REG register
+/** SPI_MEM_C_FMEM__PMS1_SIZE_REG register
  *  SPI1 flash PMS section 1 start address register
  */
-#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI0_BASE + 0x124)
-/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S,
- *  SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE)
+#define SPI_MEM_C_FMEM__PMS1_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x124)
+/** SPI_MEM_C_FMEM__PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 1 address region is (SPI_MEM_C_FMEM__PMS1_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS1_ADDR_S + SPI_MEM_C_FMEM__PMS1_SIZE)
  */
-#define SPI_FMEM_PMS1_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS1_SIZE_M  (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S)
-#define SPI_FMEM_PMS1_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS1_SIZE_S  0
+#define SPI_MEM_C_FMEM__PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS1_SIZE_M  (SPI_MEM_C_FMEM__PMS1_SIZE_V << SPI_MEM_C_FMEM__PMS1_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS1_SIZE_S  0
 
-/** SPI_FMEM_PMS2_SIZE_REG register
+/** SPI_MEM_C_FMEM__PMS2_SIZE_REG register
  *  SPI1 flash PMS section 2 start address register
  */
-#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI0_BASE + 0x128)
-/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S,
- *  SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE)
+#define SPI_MEM_C_FMEM__PMS2_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x128)
+/** SPI_MEM_C_FMEM__PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 2 address region is (SPI_MEM_C_FMEM__PMS2_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS2_ADDR_S + SPI_MEM_C_FMEM__PMS2_SIZE)
  */
-#define SPI_FMEM_PMS2_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS2_SIZE_M  (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S)
-#define SPI_FMEM_PMS2_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS2_SIZE_S  0
+#define SPI_MEM_C_FMEM__PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS2_SIZE_M  (SPI_MEM_C_FMEM__PMS2_SIZE_V << SPI_MEM_C_FMEM__PMS2_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS2_SIZE_S  0
 
-/** SPI_FMEM_PMS3_SIZE_REG register
+/** SPI_MEM_C_FMEM__PMS3_SIZE_REG register
  *  SPI1 flash PMS section 3 start address register
  */
-#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI0_BASE + 0x12c)
-/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S,
- *  SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE)
+#define SPI_MEM_C_FMEM__PMS3_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x12c)
+/** SPI_MEM_C_FMEM__PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 3 address region is (SPI_MEM_C_FMEM__PMS3_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS3_ADDR_S + SPI_MEM_C_FMEM__PMS3_SIZE)
  */
-#define SPI_FMEM_PMS3_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS3_SIZE_M  (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S)
-#define SPI_FMEM_PMS3_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS3_SIZE_S  0
+#define SPI_MEM_C_FMEM__PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS3_SIZE_M  (SPI_MEM_C_FMEM__PMS3_SIZE_V << SPI_MEM_C_FMEM__PMS3_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS3_SIZE_S  0
 
-/** SPI_SMEM_PMS0_ATTR_REG register
+/** SPI_MEM_C_SMEM_PMS0_ATTR_REG register
  *  SPI1 flash PMS section 0 start address register
  */
-#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI0_BASE + 0x130)
-/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_SMEM_PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x130)
+/** SPI_MEM_C_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS0_RD_ATTR_M  (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S)
-#define SPI_SMEM_PMS0_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS0_RD_ATTR_S  0
-/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS0_RD_ATTR_V << SPI_MEM_C_SMEM_PMS0_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS0_WR_ATTR_M  (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S)
-#define SPI_SMEM_PMS0_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS0_WR_ATTR_S  1
-/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS0_WR_ATTR_V << SPI_MEM_C_SMEM_PMS0_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and
- *  SPI_SMEM_PMS0_SIZE_REG.
+ *  external RAM PMS section 0 is configured by registers SPI_MEM_C_SMEM_PMS0_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS0_SIZE_REG.
  */
-#define SPI_SMEM_PMS0_ECC    (BIT(2))
-#define SPI_SMEM_PMS0_ECC_M  (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S)
-#define SPI_SMEM_PMS0_ECC_V  0x00000001U
-#define SPI_SMEM_PMS0_ECC_S  2
+#define SPI_MEM_C_SMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS0_ECC_M  (SPI_MEM_C_SMEM_PMS0_ECC_V << SPI_MEM_C_SMEM_PMS0_ECC_S)
+#define SPI_MEM_C_SMEM_PMS0_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS0_ECC_S  2
 
-/** SPI_SMEM_PMS1_ATTR_REG register
+/** SPI_MEM_C_SMEM_PMS1_ATTR_REG register
  *  SPI1 flash PMS section 1 start address register
  */
-#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI0_BASE + 0x134)
-/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_SMEM_PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x134)
+/** SPI_MEM_C_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS1_RD_ATTR_M  (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S)
-#define SPI_SMEM_PMS1_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS1_RD_ATTR_S  0
-/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS1_RD_ATTR_V << SPI_MEM_C_SMEM_PMS1_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS1_WR_ATTR_M  (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S)
-#define SPI_SMEM_PMS1_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS1_WR_ATTR_S  1
-/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS1_WR_ATTR_V << SPI_MEM_C_SMEM_PMS1_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and
- *  SPI_SMEM_PMS1_SIZE_REG.
+ *  external RAM PMS section 1 is configured by registers SPI_MEM_C_SMEM_PMS1_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS1_SIZE_REG.
  */
-#define SPI_SMEM_PMS1_ECC    (BIT(2))
-#define SPI_SMEM_PMS1_ECC_M  (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S)
-#define SPI_SMEM_PMS1_ECC_V  0x00000001U
-#define SPI_SMEM_PMS1_ECC_S  2
+#define SPI_MEM_C_SMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS1_ECC_M  (SPI_MEM_C_SMEM_PMS1_ECC_V << SPI_MEM_C_SMEM_PMS1_ECC_S)
+#define SPI_MEM_C_SMEM_PMS1_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS1_ECC_S  2
 
-/** SPI_SMEM_PMS2_ATTR_REG register
+/** SPI_MEM_C_SMEM_PMS2_ATTR_REG register
  *  SPI1 flash PMS section 2 start address register
  */
-#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI0_BASE + 0x138)
-/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_SMEM_PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x138)
+/** SPI_MEM_C_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS2_RD_ATTR_M  (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S)
-#define SPI_SMEM_PMS2_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS2_RD_ATTR_S  0
-/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS2_RD_ATTR_V << SPI_MEM_C_SMEM_PMS2_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS2_WR_ATTR_M  (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S)
-#define SPI_SMEM_PMS2_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS2_WR_ATTR_S  1
-/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS2_WR_ATTR_V << SPI_MEM_C_SMEM_PMS2_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and
- *  SPI_SMEM_PMS2_SIZE_REG.
+ *  external RAM PMS section 2 is configured by registers SPI_MEM_C_SMEM_PMS2_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS2_SIZE_REG.
  */
-#define SPI_SMEM_PMS2_ECC    (BIT(2))
-#define SPI_SMEM_PMS2_ECC_M  (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S)
-#define SPI_SMEM_PMS2_ECC_V  0x00000001U
-#define SPI_SMEM_PMS2_ECC_S  2
+#define SPI_MEM_C_SMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS2_ECC_M  (SPI_MEM_C_SMEM_PMS2_ECC_V << SPI_MEM_C_SMEM_PMS2_ECC_S)
+#define SPI_MEM_C_SMEM_PMS2_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS2_ECC_S  2
 
-/** SPI_SMEM_PMS3_ATTR_REG register
+/** SPI_MEM_C_SMEM_PMS3_ATTR_REG register
  *  SPI1 flash PMS section 3 start address register
  */
-#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI0_BASE + 0x13c)
-/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_SMEM_PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x13c)
+/** SPI_MEM_C_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS3_RD_ATTR_M  (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S)
-#define SPI_SMEM_PMS3_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS3_RD_ATTR_S  0
-/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS3_RD_ATTR_V << SPI_MEM_C_SMEM_PMS3_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS3_WR_ATTR_M  (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S)
-#define SPI_SMEM_PMS3_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS3_WR_ATTR_S  1
-/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS3_WR_ATTR_V << SPI_MEM_C_SMEM_PMS3_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and
- *  SPI_SMEM_PMS3_SIZE_REG.
+ *  external RAM PMS section 3 is configured by registers SPI_MEM_C_SMEM_PMS3_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS3_SIZE_REG.
  */
-#define SPI_SMEM_PMS3_ECC    (BIT(2))
-#define SPI_SMEM_PMS3_ECC_M  (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S)
-#define SPI_SMEM_PMS3_ECC_V  0x00000001U
-#define SPI_SMEM_PMS3_ECC_S  2
+#define SPI_MEM_C_SMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS3_ECC_M  (SPI_MEM_C_SMEM_PMS3_ECC_V << SPI_MEM_C_SMEM_PMS3_ECC_S)
+#define SPI_MEM_C_SMEM_PMS3_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS3_ECC_S  2
 
-/** SPI_SMEM_PMS0_ADDR_REG register
+/** SPI_MEM_C_SMEM_PMS0_ADDR_REG register
  *  SPI1 external RAM PMS section 0 start address register
  */
-#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI0_BASE + 0x140)
-/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_SMEM_PMS0_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x140)
+/** SPI_MEM_C_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 0 start address value
  */
-#define SPI_SMEM_PMS0_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS0_ADDR_S_M  (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S)
-#define SPI_SMEM_PMS0_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS0_ADDR_S_S  0
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S_M  (SPI_MEM_C_SMEM_PMS0_ADDR_S_V << SPI_MEM_C_SMEM_PMS0_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S_S  0
 
-/** SPI_SMEM_PMS1_ADDR_REG register
+/** SPI_MEM_C_SMEM_PMS1_ADDR_REG register
  *  SPI1 external RAM PMS section 1 start address register
  */
-#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI0_BASE + 0x144)
-/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_SMEM_PMS1_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x144)
+/** SPI_MEM_C_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 1 start address value
  */
-#define SPI_SMEM_PMS1_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS1_ADDR_S_M  (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S)
-#define SPI_SMEM_PMS1_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS1_ADDR_S_S  0
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S_M  (SPI_MEM_C_SMEM_PMS1_ADDR_S_V << SPI_MEM_C_SMEM_PMS1_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S_S  0
 
-/** SPI_SMEM_PMS2_ADDR_REG register
+/** SPI_MEM_C_SMEM_PMS2_ADDR_REG register
  *  SPI1 external RAM PMS section 2 start address register
  */
-#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI0_BASE + 0x148)
-/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_SMEM_PMS2_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x148)
+/** SPI_MEM_C_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 2 start address value
  */
-#define SPI_SMEM_PMS2_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS2_ADDR_S_M  (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S)
-#define SPI_SMEM_PMS2_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS2_ADDR_S_S  0
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S_M  (SPI_MEM_C_SMEM_PMS2_ADDR_S_V << SPI_MEM_C_SMEM_PMS2_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S_S  0
 
-/** SPI_SMEM_PMS3_ADDR_REG register
+/** SPI_MEM_C_SMEM_PMS3_ADDR_REG register
  *  SPI1 external RAM PMS section 3 start address register
  */
-#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI0_BASE + 0x14c)
-/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_SMEM_PMS3_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x14c)
+/** SPI_MEM_C_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 3 start address value
  */
-#define SPI_SMEM_PMS3_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS3_ADDR_S_M  (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S)
-#define SPI_SMEM_PMS3_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS3_ADDR_S_S  0
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S_M  (SPI_MEM_C_SMEM_PMS3_ADDR_S_V << SPI_MEM_C_SMEM_PMS3_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S_S  0
 
-/** SPI_SMEM_PMS0_SIZE_REG register
+/** SPI_MEM_C_SMEM_PMS0_SIZE_REG register
  *  SPI1 external RAM PMS section 0 start address register
  */
-#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI0_BASE + 0x150)
-/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S,
- *  SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE)
+#define SPI_MEM_C_SMEM_PMS0_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x150)
+/** SPI_MEM_C_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 0 address region is (SPI_MEM_C_SMEM_PMS0_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS0_ADDR_S + SPI_MEM_C_SMEM_PMS0_SIZE)
  */
-#define SPI_SMEM_PMS0_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS0_SIZE_M  (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S)
-#define SPI_SMEM_PMS0_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS0_SIZE_S  0
+#define SPI_MEM_C_SMEM_PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS0_SIZE_M  (SPI_MEM_C_SMEM_PMS0_SIZE_V << SPI_MEM_C_SMEM_PMS0_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS0_SIZE_S  0
 
-/** SPI_SMEM_PMS1_SIZE_REG register
+/** SPI_MEM_C_SMEM_PMS1_SIZE_REG register
  *  SPI1 external RAM PMS section 1 start address register
  */
-#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI0_BASE + 0x154)
-/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S,
- *  SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE)
+#define SPI_MEM_C_SMEM_PMS1_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x154)
+/** SPI_MEM_C_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 1 address region is (SPI_MEM_C_SMEM_PMS1_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS1_ADDR_S + SPI_MEM_C_SMEM_PMS1_SIZE)
  */
-#define SPI_SMEM_PMS1_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS1_SIZE_M  (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S)
-#define SPI_SMEM_PMS1_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS1_SIZE_S  0
+#define SPI_MEM_C_SMEM_PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS1_SIZE_M  (SPI_MEM_C_SMEM_PMS1_SIZE_V << SPI_MEM_C_SMEM_PMS1_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS1_SIZE_S  0
 
-/** SPI_SMEM_PMS2_SIZE_REG register
+/** SPI_MEM_C_SMEM_PMS2_SIZE_REG register
  *  SPI1 external RAM PMS section 2 start address register
  */
-#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI0_BASE + 0x158)
-/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S,
- *  SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE)
+#define SPI_MEM_C_SMEM_PMS2_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x158)
+/** SPI_MEM_C_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 2 address region is (SPI_MEM_C_SMEM_PMS2_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS2_ADDR_S + SPI_MEM_C_SMEM_PMS2_SIZE)
  */
-#define SPI_SMEM_PMS2_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS2_SIZE_M  (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S)
-#define SPI_SMEM_PMS2_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS2_SIZE_S  0
+#define SPI_MEM_C_SMEM_PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS2_SIZE_M  (SPI_MEM_C_SMEM_PMS2_SIZE_V << SPI_MEM_C_SMEM_PMS2_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS2_SIZE_S  0
 
-/** SPI_SMEM_PMS3_SIZE_REG register
+/** SPI_MEM_C_SMEM_PMS3_SIZE_REG register
  *  SPI1 external RAM PMS section 3 start address register
  */
-#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI0_BASE + 0x15c)
-/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S,
- *  SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE)
+#define SPI_MEM_C_SMEM_PMS3_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x15c)
+/** SPI_MEM_C_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 3 address region is (SPI_MEM_C_SMEM_PMS3_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS3_ADDR_S + SPI_MEM_C_SMEM_PMS3_SIZE)
  */
-#define SPI_SMEM_PMS3_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS3_SIZE_M  (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S)
-#define SPI_SMEM_PMS3_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS3_SIZE_S  0
+#define SPI_MEM_C_SMEM_PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS3_SIZE_M  (SPI_MEM_C_SMEM_PMS3_SIZE_V << SPI_MEM_C_SMEM_PMS3_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS3_SIZE_S  0
 
-/** SPI_MEM_PMS_REJECT_REG register
+/** SPI_MEM_C_PMS_REJECT_REG register
  *  SPI1 access reject register
  */
-#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI0_BASE + 0x164)
-/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_PMS_REJECT_REG (DR_REG_FLASH_SPI0_BASE + 0x164)
+/** SPI_MEM_C_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
  *  This bits show the first SPI1 access error address. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_REJECT_ADDR    0x07FFFFFFU
-#define SPI_MEM_REJECT_ADDR_M  (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S)
-#define SPI_MEM_REJECT_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_REJECT_ADDR_S  0
-/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0;
+#define SPI_MEM_C_REJECT_ADDR    0x07FFFFFFU
+#define SPI_MEM_C_REJECT_ADDR_M  (SPI_MEM_C_REJECT_ADDR_V << SPI_MEM_C_REJECT_ADDR_S)
+#define SPI_MEM_C_REJECT_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_C_REJECT_ADDR_S  0
+/** SPI_MEM_C_PM_EN : R/W; bitpos: [27]; default: 0;
  *  Set this bit to enable SPI0/1 transfer permission control function.
  */
-#define SPI_MEM_PM_EN    (BIT(27))
-#define SPI_MEM_PM_EN_M  (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S)
-#define SPI_MEM_PM_EN_V  0x00000001U
-#define SPI_MEM_PM_EN_S  27
-/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0;
+#define SPI_MEM_C_PM_EN    (BIT(27))
+#define SPI_MEM_C_PM_EN_M  (SPI_MEM_C_PM_EN_V << SPI_MEM_C_PM_EN_S)
+#define SPI_MEM_C_PM_EN_V  0x00000001U
+#define SPI_MEM_C_PM_EN_S  27
+/** SPI_MEM_C_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0;
  *  1: SPI1 write access error. 0: No write access error. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_LD    (BIT(28))
-#define SPI_MEM_PMS_LD_M  (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S)
-#define SPI_MEM_PMS_LD_V  0x00000001U
-#define SPI_MEM_PMS_LD_S  28
-/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0;
+#define SPI_MEM_C_PMS_LD    (BIT(28))
+#define SPI_MEM_C_PMS_LD_M  (SPI_MEM_C_PMS_LD_V << SPI_MEM_C_PMS_LD_S)
+#define SPI_MEM_C_PMS_LD_V  0x00000001U
+#define SPI_MEM_C_PMS_LD_S  28
+/** SPI_MEM_C_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0;
  *  1: SPI1 read access error. 0: No read access error. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_ST    (BIT(29))
-#define SPI_MEM_PMS_ST_M  (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S)
-#define SPI_MEM_PMS_ST_V  0x00000001U
-#define SPI_MEM_PMS_ST_S  29
-/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0;
+#define SPI_MEM_C_PMS_ST    (BIT(29))
+#define SPI_MEM_C_PMS_ST_M  (SPI_MEM_C_PMS_ST_V << SPI_MEM_C_PMS_ST_S)
+#define SPI_MEM_C_PMS_ST_V  0x00000001U
+#define SPI_MEM_C_PMS_ST_S  29
+/** SPI_MEM_C_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0;
  *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
- *  cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  cleared by when  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_M  (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S)
-#define SPI_MEM_PMS_MULTI_HIT_V  0x00000001U
-#define SPI_MEM_PMS_MULTI_HIT_S  30
-/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0;
+#define SPI_MEM_C_PMS_MULTI_HIT    (BIT(30))
+#define SPI_MEM_C_PMS_MULTI_HIT_M  (SPI_MEM_C_PMS_MULTI_HIT_V << SPI_MEM_C_PMS_MULTI_HIT_S)
+#define SPI_MEM_C_PMS_MULTI_HIT_V  0x00000001U
+#define SPI_MEM_C_PMS_MULTI_HIT_S  30
+/** SPI_MEM_C_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0;
  *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- *  error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  error. It is cleared by when  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_IVD    (BIT(31))
-#define SPI_MEM_PMS_IVD_M  (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S)
-#define SPI_MEM_PMS_IVD_V  0x00000001U
-#define SPI_MEM_PMS_IVD_S  31
+#define SPI_MEM_C_PMS_IVD    (BIT(31))
+#define SPI_MEM_C_PMS_IVD_M  (SPI_MEM_C_PMS_IVD_V << SPI_MEM_C_PMS_IVD_S)
+#define SPI_MEM_C_PMS_IVD_V  0x00000001U
+#define SPI_MEM_C_PMS_IVD_S  31
 
-/** SPI_MEM_ECC_CTRL_REG register
+/** SPI_MEM_C_ECC_CTRL_REG register
  *  MSPI ECC control register
  */
-#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI0_BASE + 0x168)
-/** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0;
+#define SPI_MEM_C_ECC_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x168)
+/** SPI_MEM_C_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0;
  *  This bits show the error times of MSPI ECC read. It is cleared by when
- *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+ *  SPI_MEM_C_ECC_ERR_INT_CLR bit is set.
  */
-#define SPI_MEM_ECC_ERR_CNT    0x0000003FU
-#define SPI_MEM_ECC_ERR_CNT_M  (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S)
-#define SPI_MEM_ECC_ERR_CNT_V  0x0000003FU
-#define SPI_MEM_ECC_ERR_CNT_S  5
-/** SPI_FMEM_ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10;
- *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_C_ECC_ERR_CNT    0x0000003FU
+#define SPI_MEM_C_ECC_ERR_CNT_M  (SPI_MEM_C_ECC_ERR_CNT_V << SPI_MEM_C_ECC_ERR_CNT_S)
+#define SPI_MEM_C_ECC_ERR_CNT_V  0x0000003FU
+#define SPI_MEM_C_ECC_ERR_CNT_S  5
+/** SPI_MEM_C_FMEM__ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10;
+ *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT interrupt.
  */
-#define SPI_FMEM_ECC_ERR_INT_NUM    0x0000003FU
-#define SPI_FMEM_ECC_ERR_INT_NUM_M  (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S)
-#define SPI_FMEM_ECC_ERR_INT_NUM_V  0x0000003FU
-#define SPI_FMEM_ECC_ERR_INT_NUM_S  11
-/** SPI_FMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM    0x0000003FU
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_M  (SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V << SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S)
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V  0x0000003FU
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S  11
+/** SPI_MEM_C_FMEM__ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
  *  Set this bit to calculate the error times of MSPI ECC read when accesses to flash.
  */
-#define SPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_FMEM_ECC_ERR_INT_EN_M  (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S)
-#define SPI_FMEM_ECC_ERR_INT_EN_V  0x00000001U
-#define SPI_FMEM_ECC_ERR_INT_EN_S  17
-/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0;
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_M  (SPI_MEM_C_FMEM__ECC_ERR_INT_EN_V << SPI_MEM_C_FMEM__ECC_ERR_INT_EN_S)
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_S  17
+/** SPI_MEM_C_FMEM__PAGE_SIZE : R/W; bitpos: [19:18]; default: 0;
  *  Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
  *  1024 bytes. 3: 2048 bytes.
  */
-#define SPI_FMEM_PAGE_SIZE    0x00000003U
-#define SPI_FMEM_PAGE_SIZE_M  (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S)
-#define SPI_FMEM_PAGE_SIZE_V  0x00000003U
-#define SPI_FMEM_PAGE_SIZE_S  18
-/** SPI_FMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
+#define SPI_MEM_C_FMEM__PAGE_SIZE    0x00000003U
+#define SPI_MEM_C_FMEM__PAGE_SIZE_M  (SPI_MEM_C_FMEM__PAGE_SIZE_V << SPI_MEM_C_FMEM__PAGE_SIZE_S)
+#define SPI_MEM_C_FMEM__PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_C_FMEM__PAGE_SIZE_S  18
+/** SPI_MEM_C_FMEM__ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
  *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
  *  ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit
  *  should be 0. Otherwise, this bit should be 1.
  */
-#define SPI_FMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_FMEM_ECC_ADDR_EN_M  (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S)
-#define SPI_FMEM_ECC_ADDR_EN_V  0x00000001U
-#define SPI_FMEM_ECC_ADDR_EN_S  20
-/** SPI_MEM_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0;
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN_M  (SPI_MEM_C_FMEM__ECC_ADDR_EN_V << SPI_MEM_C_FMEM__ECC_ADDR_EN_S)
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN_S  20
+/** SPI_MEM_C_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0;
  *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
  */
-#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_M  (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S)
-#define SPI_MEM_USR_ECC_ADDR_EN_V  0x00000001U
-#define SPI_MEM_USR_ECC_ADDR_EN_S  21
-/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1;
- *  1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is
- *  updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and
- *  SPI_MEM_ECC_ERR_ADDR record the first ECC error information.
+#define SPI_MEM_C_USR_ECC_ADDR_EN    (BIT(21))
+#define SPI_MEM_C_USR_ECC_ADDR_EN_M  (SPI_MEM_C_USR_ECC_ADDR_EN_V << SPI_MEM_C_USR_ECC_ADDR_EN_S)
+#define SPI_MEM_C_USR_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_C_USR_ECC_ADDR_EN_S  21
+/** SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1;
+ *  1: The error information in SPI_MEM_C_ECC_ERR_BITS and SPI_MEM_C_ECC_ERR_ADDR is
+ *  updated when there is an ECC error. 0: SPI_MEM_C_ECC_ERR_BITS and
+ *  SPI_MEM_C_ECC_ERR_ADDR record the first ECC error information.
  */
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S)
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x00000001U
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/** SPI_MEM_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0;
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_M  (SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_S)
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_V  0x00000001U
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/** SPI_MEM_C_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0;
  *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
  *  byte 0 bit 0 to byte 15 bit 7)
  */
-#define SPI_MEM_ECC_ERR_BITS    0x0000007FU
-#define SPI_MEM_ECC_ERR_BITS_M  (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S)
-#define SPI_MEM_ECC_ERR_BITS_V  0x0000007FU
-#define SPI_MEM_ECC_ERR_BITS_S  25
+#define SPI_MEM_C_ECC_ERR_BITS    0x0000007FU
+#define SPI_MEM_C_ECC_ERR_BITS_M  (SPI_MEM_C_ECC_ERR_BITS_V << SPI_MEM_C_ECC_ERR_BITS_S)
+#define SPI_MEM_C_ECC_ERR_BITS_V  0x0000007FU
+#define SPI_MEM_C_ECC_ERR_BITS_S  25
 
-/** SPI_MEM_ECC_ERR_ADDR_REG register
+/** SPI_MEM_C_ECC_ERR_ADDR_REG register
  *  MSPI ECC error address register
  */
-#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI0_BASE + 0x16c)
-/** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_ECC_ERR_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x16c)
+/** SPI_MEM_C_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0;
  *  This bits show the first MSPI ECC error address. It is cleared by when
- *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+ *  SPI_MEM_C_ECC_ERR_INT_CLR bit is set.
  */
-#define SPI_MEM_ECC_ERR_ADDR    0x07FFFFFFU
-#define SPI_MEM_ECC_ERR_ADDR_M  (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S)
-#define SPI_MEM_ECC_ERR_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_ECC_ERR_ADDR_S  0
+#define SPI_MEM_C_ECC_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_C_ECC_ERR_ADDR_M  (SPI_MEM_C_ECC_ERR_ADDR_V << SPI_MEM_C_ECC_ERR_ADDR_S)
+#define SPI_MEM_C_ECC_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_C_ECC_ERR_ADDR_S  0
 
-/** SPI_MEM_AXI_ERR_ADDR_REG register
+/** SPI_MEM_C_AXI_ERR_ADDR_REG register
  *  SPI0 AXI request error address.
  */
-#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI0_BASE + 0x170)
-/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+#define SPI_MEM_C_AXI_ERR_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x170)
+/** SPI_MEM_C_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
  *  This bits show the first AXI write/read invalid error or AXI write flash error
- *  address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
- *  SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
+ *  address. It is cleared by when SPI_MEM_C_AXI_WADDR_ERR_INT_CLR,
+ *  SPI_MEM_C_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_C_AXI_RADDR_ERR_IN_CLR bit is set.
  */
-#define SPI_MEM_AXI_ERR_ADDR    0x07FFFFFFU
-#define SPI_MEM_AXI_ERR_ADDR_M  (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S)
-#define SPI_MEM_AXI_ERR_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_AXI_ERR_ADDR_S  0
+#define SPI_MEM_C_AXI_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_C_AXI_ERR_ADDR_M  (SPI_MEM_C_AXI_ERR_ADDR_V << SPI_MEM_C_AXI_ERR_ADDR_S)
+#define SPI_MEM_C_AXI_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_C_AXI_ERR_ADDR_S  0
 
-/** SPI_SMEM_ECC_CTRL_REG register
+/** SPI_MEM_C_SMEM_ECC_CTRL_REG register
  *  MSPI ECC control register
  */
-#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI0_BASE + 0x174)
-/** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
+#define SPI_MEM_C_SMEM_ECC_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x174)
+/** SPI_MEM_C_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
  *  Set this bit to calculate the error times of MSPI ECC read when accesses to
  *  external RAM.
  */
-#define SPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_SMEM_ECC_ERR_INT_EN_M  (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S)
-#define SPI_SMEM_ECC_ERR_INT_EN_V  0x00000001U
-#define SPI_SMEM_ECC_ERR_INT_EN_S  17
-/** SPI_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2;
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_M  (SPI_MEM_C_SMEM_ECC_ERR_INT_EN_V << SPI_MEM_C_SMEM_ECC_ERR_INT_EN_S)
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_S  17
+/** SPI_MEM_C_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2;
  *  Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes.
  *  2: 1024 bytes. 3: 2048 bytes.
  */
-#define SPI_SMEM_PAGE_SIZE    0x00000003U
-#define SPI_SMEM_PAGE_SIZE_M  (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S)
-#define SPI_SMEM_PAGE_SIZE_V  0x00000003U
-#define SPI_SMEM_PAGE_SIZE_S  18
-/** SPI_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
+#define SPI_MEM_C_SMEM_PAGE_SIZE    0x00000003U
+#define SPI_MEM_C_SMEM_PAGE_SIZE_M  (SPI_MEM_C_SMEM_PAGE_SIZE_V << SPI_MEM_C_SMEM_PAGE_SIZE_S)
+#define SPI_MEM_C_SMEM_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_C_SMEM_PAGE_SIZE_S  18
+/** SPI_MEM_C_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
  *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
  *  ECC region or non-ECC region of external RAM. If there is no ECC region in external
  *  RAM, this bit should be 0. Otherwise, this bit should be 1.
  */
-#define SPI_SMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_SMEM_ECC_ADDR_EN_M  (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S)
-#define SPI_SMEM_ECC_ADDR_EN_V  0x00000001U
-#define SPI_SMEM_ECC_ADDR_EN_S  20
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN_M  (SPI_MEM_C_SMEM_ECC_ADDR_EN_V << SPI_MEM_C_SMEM_ECC_ADDR_EN_S)
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN_S  20
 
-/** SPI_SMEM_AXI_ADDR_CTRL_REG register
+/** SPI_MEM_C_SMEM_AXI_ADDR_CTRL_REG register
  *  SPI0 AXI address control register
  */
-#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI0_BASE + 0x178)
-/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
+#define SPI_MEM_C_SMEM_AXI_ADDR_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x178)
+/** SPI_MEM_C_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
  *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
  *  and SPI0 transfers are done. 0: Others.
  */
-#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_M  (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S)
-#define SPI_MEM_ALL_FIFO_EMPTY_V  0x00000001U
-#define SPI_MEM_ALL_FIFO_EMPTY_S  26
-/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1;
+#define SPI_MEM_C_ALL_FIFO_EMPTY    (BIT(26))
+#define SPI_MEM_C_ALL_FIFO_EMPTY_M  (SPI_MEM_C_ALL_FIFO_EMPTY_V << SPI_MEM_C_ALL_FIFO_EMPTY_S)
+#define SPI_MEM_C_ALL_FIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_C_ALL_FIFO_EMPTY_S  26
+/** SPI_MEM_C_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1;
  *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
  */
-#define SPI_RDATA_AFIFO_REMPTY    (BIT(27))
-#define SPI_RDATA_AFIFO_REMPTY_M  (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S)
-#define SPI_RDATA_AFIFO_REMPTY_V  0x00000001U
-#define SPI_RDATA_AFIFO_REMPTY_S  27
-/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1;
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY    (BIT(27))
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY_M  (SPI_MEM_C_RDATA_AFIFO_REMPTY_V << SPI_MEM_C_RDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY_S  27
+/** SPI_MEM_C_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1;
  *  1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
  */
-#define SPI_RADDR_AFIFO_REMPTY    (BIT(28))
-#define SPI_RADDR_AFIFO_REMPTY_M  (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S)
-#define SPI_RADDR_AFIFO_REMPTY_V  0x00000001U
-#define SPI_RADDR_AFIFO_REMPTY_S  28
-/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1;
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY    (BIT(28))
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY_M  (SPI_MEM_C_RADDR_AFIFO_REMPTY_V << SPI_MEM_C_RADDR_AFIFO_REMPTY_S)
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY_S  28
+/** SPI_MEM_C_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1;
  *  1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
  */
-#define SPI_WDATA_AFIFO_REMPTY    (BIT(29))
-#define SPI_WDATA_AFIFO_REMPTY_M  (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S)
-#define SPI_WDATA_AFIFO_REMPTY_V  0x00000001U
-#define SPI_WDATA_AFIFO_REMPTY_S  29
-/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1;
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY    (BIT(29))
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY_M  (SPI_MEM_C_WDATA_AFIFO_REMPTY_V << SPI_MEM_C_WDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY_S  29
+/** SPI_MEM_C_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1;
  *  1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
  */
-#define SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define SPI_WBLEN_AFIFO_REMPTY_M  (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S)
-#define SPI_WBLEN_AFIFO_REMPTY_V  0x00000001U
-#define SPI_WBLEN_AFIFO_REMPTY_S  30
-/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1;
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_M  (SPI_MEM_C_WBLEN_AFIFO_REMPTY_V << SPI_MEM_C_WBLEN_AFIFO_REMPTY_S)
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_S  30
+/** SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1;
  *  This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and
  *  RDATA_AFIFO are empty and spi0_mst_st is IDLE.
  */
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S)
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x00000001U
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_M  (SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_S)
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
 
-/** SPI_MEM_AXI_ERR_RESP_EN_REG register
+/** SPI_MEM_C_AXI_ERR_RESP_EN_REG register
  *  SPI0 AXI error response enable register
  */
-#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI0_BASE + 0x17c)
-/** SPI_MEM_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0;
+#define SPI_MEM_C_AXI_ERR_RESP_EN_REG (DR_REG_FLASH_SPI0_BASE + 0x17c)
+/** SPI_MEM_C_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0;
  *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_VLD    (BIT(0))
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_M  (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S)
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_S  0
-/** SPI_MEM_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0;
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD    (BIT(0))
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_M  (SPI_MEM_C_AW_RESP_EN_MMU_VLD_V << SPI_MEM_C_AW_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_S  0
+/** SPI_MEM_C_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0;
  *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_GID    (BIT(1))
-#define SPI_MEM_AW_RESP_EN_MMU_GID_M  (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S)
-#define SPI_MEM_AW_RESP_EN_MMU_GID_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_GID_S  1
-/** SPI_MEM_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0;
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID    (BIT(1))
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID_M  (SPI_MEM_C_AW_RESP_EN_MMU_GID_V << SPI_MEM_C_AW_RESP_EN_MMU_GID_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID_S  1
+/** SPI_MEM_C_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0;
  *  Set this bit  to enable AXI response function for axi size err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE    (BIT(2))
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M  (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S)
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S  2
-/** SPI_MEM_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0;
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE    (BIT(2))
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_M  (SPI_MEM_C_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_C_AW_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_S  2
+/** SPI_MEM_C_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0;
  *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH    (BIT(3))
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M  (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S)
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S  3
-/** SPI_MEM_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0;
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH    (BIT(3))
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_M  (SPI_MEM_C_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_C_AW_RESP_EN_AXI_FLASH_S)
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_S  3
+/** SPI_MEM_C_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0;
  *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_ECC    (BIT(4))
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_M  (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S)
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_S  4
-/** SPI_MEM_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0;
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC    (BIT(4))
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_M  (SPI_MEM_C_AW_RESP_EN_MMU_ECC_V << SPI_MEM_C_AW_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_S  4
+/** SPI_MEM_C_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0;
  *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_SENS    (BIT(5))
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_M  (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S)
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_S  5
-/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0;
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS    (BIT(5))
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_M  (SPI_MEM_C_AW_RESP_EN_MMU_SENS_V << SPI_MEM_C_AW_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_S  5
+/** SPI_MEM_C_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0;
  *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB    (BIT(6))
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M  (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S)
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S  6
-/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB    (BIT(6))
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_M  (SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_S)
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_S  6
+/** SPI_MEM_C_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0;
  *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_VLD    (BIT(7))
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_M  (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S)
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_S  7
-/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD    (BIT(7))
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_M  (SPI_MEM_C_AR_RESP_EN_MMU_VLD_V << SPI_MEM_C_AR_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_S  7
+/** SPI_MEM_C_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0;
  *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_GID    (BIT(8))
-#define SPI_MEM_AR_RESP_EN_MMU_GID_M  (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S)
-#define SPI_MEM_AR_RESP_EN_MMU_GID_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_GID_S  8
-/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0;
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID    (BIT(8))
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID_M  (SPI_MEM_C_AR_RESP_EN_MMU_GID_V << SPI_MEM_C_AR_RESP_EN_MMU_GID_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID_S  8
+/** SPI_MEM_C_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0;
  *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_ECC    (BIT(9))
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_M  (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S)
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_S  9
-/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0;
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC    (BIT(9))
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_M  (SPI_MEM_C_AR_RESP_EN_MMU_ECC_V << SPI_MEM_C_AR_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_S  9
+/** SPI_MEM_C_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0;
  *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
  *  trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_SENS    (BIT(10))
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_M  (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S)
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_S  10
-/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0;
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS    (BIT(10))
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_M  (SPI_MEM_C_AR_RESP_EN_MMU_SENS_V << SPI_MEM_C_AR_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_S  10
+/** SPI_MEM_C_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0;
  *  Set this bit  to enable AXI response function for axi size err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE    (BIT(11))
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M  (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S)
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S  11
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE    (BIT(11))
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_M  (SPI_MEM_C_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_C_AR_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_S  11
 
-/** SPI_MEM_TIMING_CALI_REG register
+/** SPI_MEM_C_TIMING_CALI_REG register
  *  SPI0 flash timing calibration register
  */
-#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI0_BASE + 0x180)
-/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_TIMING_CALI_REG (DR_REG_FLASH_SPI0_BASE + 0x180)
+/** SPI_MEM_C_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
  *  The bit is used to enable timing adjust clock for all reading operations.
  */
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S)
-#define SPI_MEM_TIMING_CLK_ENA_V  0x00000001U
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_C_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_C_TIMING_CLK_ENA_M  (SPI_MEM_C_TIMING_CLK_ENA_V << SPI_MEM_C_TIMING_CLK_ENA_S)
+#define SPI_MEM_C_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_C_TIMING_CLK_ENA_S  0
+/** SPI_MEM_C_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  The bit is used to enable timing auto-calibration for all reading operations.
  */
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S)
-#define SPI_MEM_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_S  1
-/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+#define SPI_MEM_C_TIMING_CALI    (BIT(1))
+#define SPI_MEM_C_TIMING_CALI_M  (SPI_MEM_C_TIMING_CALI_V << SPI_MEM_C_TIMING_CALI_S)
+#define SPI_MEM_C_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_TIMING_CALI_S  1
+/** SPI_MEM_C_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
  *  add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/** SPI_MEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_C_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
  *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
  *  flash.
  */
-#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_M  (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S)
-#define SPI_MEM_DLL_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_DLL_TIMING_CALI_S  5
-/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0;
+#define SPI_MEM_C_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_C_DLL_TIMING_CALI_M  (SPI_MEM_C_DLL_TIMING_CALI_V << SPI_MEM_C_DLL_TIMING_CALI_S)
+#define SPI_MEM_C_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_DLL_TIMING_CALI_S  5
+/** SPI_MEM_C_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0;
  *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
  */
-#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_M  (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S)
-#define SPI_MEM_TIMING_CALI_UPDATE_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_UPDATE_S  6
+#define SPI_MEM_C_TIMING_CALI_UPDATE    (BIT(6))
+#define SPI_MEM_C_TIMING_CALI_UPDATE_M  (SPI_MEM_C_TIMING_CALI_UPDATE_V << SPI_MEM_C_TIMING_CALI_UPDATE_S)
+#define SPI_MEM_C_TIMING_CALI_UPDATE_V  0x00000001U
+#define SPI_MEM_C_TIMING_CALI_UPDATE_S  6
 
-/** SPI_MEM_DIN_MODE_REG register
+/** SPI_MEM_C_DIN_MODE_REG register
  *  MSPI flash input timing delay mode control register
  */
-#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI0_BASE + 0x184)
-/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
+#define SPI_MEM_C_DIN_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x184)
+/** SPI_MEM_C_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN0_MODE    0x00000007U
-#define SPI_MEM_DIN0_MODE_M  (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S)
-#define SPI_MEM_DIN0_MODE_V  0x00000007U
-#define SPI_MEM_DIN0_MODE_S  0
-/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
+#define SPI_MEM_C_DIN0_MODE    0x00000007U
+#define SPI_MEM_C_DIN0_MODE_M  (SPI_MEM_C_DIN0_MODE_V << SPI_MEM_C_DIN0_MODE_S)
+#define SPI_MEM_C_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN0_MODE_S  0
+/** SPI_MEM_C_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN1_MODE    0x00000007U
-#define SPI_MEM_DIN1_MODE_M  (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S)
-#define SPI_MEM_DIN1_MODE_V  0x00000007U
-#define SPI_MEM_DIN1_MODE_S  3
-/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
+#define SPI_MEM_C_DIN1_MODE    0x00000007U
+#define SPI_MEM_C_DIN1_MODE_M  (SPI_MEM_C_DIN1_MODE_V << SPI_MEM_C_DIN1_MODE_S)
+#define SPI_MEM_C_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN1_MODE_S  3
+/** SPI_MEM_C_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN2_MODE    0x00000007U
-#define SPI_MEM_DIN2_MODE_M  (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S)
-#define SPI_MEM_DIN2_MODE_V  0x00000007U
-#define SPI_MEM_DIN2_MODE_S  6
-/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
+#define SPI_MEM_C_DIN2_MODE    0x00000007U
+#define SPI_MEM_C_DIN2_MODE_M  (SPI_MEM_C_DIN2_MODE_V << SPI_MEM_C_DIN2_MODE_S)
+#define SPI_MEM_C_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN2_MODE_S  6
+/** SPI_MEM_C_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN3_MODE    0x00000007U
-#define SPI_MEM_DIN3_MODE_M  (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S)
-#define SPI_MEM_DIN3_MODE_V  0x00000007U
-#define SPI_MEM_DIN3_MODE_S  9
-/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
+#define SPI_MEM_C_DIN3_MODE    0x00000007U
+#define SPI_MEM_C_DIN3_MODE_M  (SPI_MEM_C_DIN3_MODE_V << SPI_MEM_C_DIN3_MODE_S)
+#define SPI_MEM_C_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN3_MODE_S  9
+/** SPI_MEM_C_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN4_MODE    0x00000007U
-#define SPI_MEM_DIN4_MODE_M  (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S)
-#define SPI_MEM_DIN4_MODE_V  0x00000007U
-#define SPI_MEM_DIN4_MODE_S  12
-/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
+#define SPI_MEM_C_DIN4_MODE    0x00000007U
+#define SPI_MEM_C_DIN4_MODE_M  (SPI_MEM_C_DIN4_MODE_V << SPI_MEM_C_DIN4_MODE_S)
+#define SPI_MEM_C_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN4_MODE_S  12
+/** SPI_MEM_C_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN5_MODE    0x00000007U
-#define SPI_MEM_DIN5_MODE_M  (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S)
-#define SPI_MEM_DIN5_MODE_V  0x00000007U
-#define SPI_MEM_DIN5_MODE_S  15
-/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
+#define SPI_MEM_C_DIN5_MODE    0x00000007U
+#define SPI_MEM_C_DIN5_MODE_M  (SPI_MEM_C_DIN5_MODE_V << SPI_MEM_C_DIN5_MODE_S)
+#define SPI_MEM_C_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN5_MODE_S  15
+/** SPI_MEM_C_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN6_MODE    0x00000007U
-#define SPI_MEM_DIN6_MODE_M  (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S)
-#define SPI_MEM_DIN6_MODE_V  0x00000007U
-#define SPI_MEM_DIN6_MODE_S  18
-/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
+#define SPI_MEM_C_DIN6_MODE    0x00000007U
+#define SPI_MEM_C_DIN6_MODE_M  (SPI_MEM_C_DIN6_MODE_V << SPI_MEM_C_DIN6_MODE_S)
+#define SPI_MEM_C_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN6_MODE_S  18
+/** SPI_MEM_C_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN7_MODE    0x00000007U
-#define SPI_MEM_DIN7_MODE_M  (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S)
-#define SPI_MEM_DIN7_MODE_V  0x00000007U
-#define SPI_MEM_DIN7_MODE_S  21
-/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
+#define SPI_MEM_C_DIN7_MODE    0x00000007U
+#define SPI_MEM_C_DIN7_MODE_M  (SPI_MEM_C_DIN7_MODE_V << SPI_MEM_C_DIN7_MODE_S)
+#define SPI_MEM_C_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN7_MODE_S  21
+/** SPI_MEM_C_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DINS_MODE    0x00000007U
-#define SPI_MEM_DINS_MODE_M  (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S)
-#define SPI_MEM_DINS_MODE_V  0x00000007U
-#define SPI_MEM_DINS_MODE_S  24
+#define SPI_MEM_C_DINS_MODE    0x00000007U
+#define SPI_MEM_C_DINS_MODE_M  (SPI_MEM_C_DINS_MODE_V << SPI_MEM_C_DINS_MODE_S)
+#define SPI_MEM_C_DINS_MODE_V  0x00000007U
+#define SPI_MEM_C_DINS_MODE_S  24
 
-/** SPI_MEM_DIN_NUM_REG register
+/** SPI_MEM_C_DIN_NUM_REG register
  *  MSPI flash input timing delay number control register
  */
-#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI0_BASE + 0x188)
-/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_C_DIN_NUM_REG (DR_REG_FLASH_SPI0_BASE + 0x188)
+/** SPI_MEM_C_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN0_NUM    0x00000003U
-#define SPI_MEM_DIN0_NUM_M  (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S)
-#define SPI_MEM_DIN0_NUM_V  0x00000003U
-#define SPI_MEM_DIN0_NUM_S  0
-/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+#define SPI_MEM_C_DIN0_NUM    0x00000003U
+#define SPI_MEM_C_DIN0_NUM_M  (SPI_MEM_C_DIN0_NUM_V << SPI_MEM_C_DIN0_NUM_S)
+#define SPI_MEM_C_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN0_NUM_S  0
+/** SPI_MEM_C_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN1_NUM    0x00000003U
-#define SPI_MEM_DIN1_NUM_M  (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S)
-#define SPI_MEM_DIN1_NUM_V  0x00000003U
-#define SPI_MEM_DIN1_NUM_S  2
-/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+#define SPI_MEM_C_DIN1_NUM    0x00000003U
+#define SPI_MEM_C_DIN1_NUM_M  (SPI_MEM_C_DIN1_NUM_V << SPI_MEM_C_DIN1_NUM_S)
+#define SPI_MEM_C_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN1_NUM_S  2
+/** SPI_MEM_C_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN2_NUM    0x00000003U
-#define SPI_MEM_DIN2_NUM_M  (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S)
-#define SPI_MEM_DIN2_NUM_V  0x00000003U
-#define SPI_MEM_DIN2_NUM_S  4
-/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+#define SPI_MEM_C_DIN2_NUM    0x00000003U
+#define SPI_MEM_C_DIN2_NUM_M  (SPI_MEM_C_DIN2_NUM_V << SPI_MEM_C_DIN2_NUM_S)
+#define SPI_MEM_C_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN2_NUM_S  4
+/** SPI_MEM_C_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN3_NUM    0x00000003U
-#define SPI_MEM_DIN3_NUM_M  (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S)
-#define SPI_MEM_DIN3_NUM_V  0x00000003U
-#define SPI_MEM_DIN3_NUM_S  6
-/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+#define SPI_MEM_C_DIN3_NUM    0x00000003U
+#define SPI_MEM_C_DIN3_NUM_M  (SPI_MEM_C_DIN3_NUM_V << SPI_MEM_C_DIN3_NUM_S)
+#define SPI_MEM_C_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN3_NUM_S  6
+/** SPI_MEM_C_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN4_NUM    0x00000003U
-#define SPI_MEM_DIN4_NUM_M  (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S)
-#define SPI_MEM_DIN4_NUM_V  0x00000003U
-#define SPI_MEM_DIN4_NUM_S  8
-/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+#define SPI_MEM_C_DIN4_NUM    0x00000003U
+#define SPI_MEM_C_DIN4_NUM_M  (SPI_MEM_C_DIN4_NUM_V << SPI_MEM_C_DIN4_NUM_S)
+#define SPI_MEM_C_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN4_NUM_S  8
+/** SPI_MEM_C_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN5_NUM    0x00000003U
-#define SPI_MEM_DIN5_NUM_M  (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S)
-#define SPI_MEM_DIN5_NUM_V  0x00000003U
-#define SPI_MEM_DIN5_NUM_S  10
-/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+#define SPI_MEM_C_DIN5_NUM    0x00000003U
+#define SPI_MEM_C_DIN5_NUM_M  (SPI_MEM_C_DIN5_NUM_V << SPI_MEM_C_DIN5_NUM_S)
+#define SPI_MEM_C_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN5_NUM_S  10
+/** SPI_MEM_C_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN6_NUM    0x00000003U
-#define SPI_MEM_DIN6_NUM_M  (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S)
-#define SPI_MEM_DIN6_NUM_V  0x00000003U
-#define SPI_MEM_DIN6_NUM_S  12
-/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+#define SPI_MEM_C_DIN6_NUM    0x00000003U
+#define SPI_MEM_C_DIN6_NUM_M  (SPI_MEM_C_DIN6_NUM_V << SPI_MEM_C_DIN6_NUM_S)
+#define SPI_MEM_C_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN6_NUM_S  12
+/** SPI_MEM_C_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN7_NUM    0x00000003U
-#define SPI_MEM_DIN7_NUM_M  (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S)
-#define SPI_MEM_DIN7_NUM_V  0x00000003U
-#define SPI_MEM_DIN7_NUM_S  14
-/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
+#define SPI_MEM_C_DIN7_NUM    0x00000003U
+#define SPI_MEM_C_DIN7_NUM_M  (SPI_MEM_C_DIN7_NUM_V << SPI_MEM_C_DIN7_NUM_S)
+#define SPI_MEM_C_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN7_NUM_S  14
+/** SPI_MEM_C_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DINS_NUM    0x00000003U
-#define SPI_MEM_DINS_NUM_M  (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S)
-#define SPI_MEM_DINS_NUM_V  0x00000003U
-#define SPI_MEM_DINS_NUM_S  16
+#define SPI_MEM_C_DINS_NUM    0x00000003U
+#define SPI_MEM_C_DINS_NUM_M  (SPI_MEM_C_DINS_NUM_V << SPI_MEM_C_DINS_NUM_S)
+#define SPI_MEM_C_DINS_NUM_V  0x00000003U
+#define SPI_MEM_C_DINS_NUM_S  16
 
-/** SPI_MEM_DOUT_MODE_REG register
+/** SPI_MEM_C_DOUT_MODE_REG register
  *  MSPI flash output timing adjustment control register
  */
-#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI0_BASE + 0x18c)
-/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_C_DOUT_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x18c)
+/** SPI_MEM_C_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S)
-#define SPI_MEM_DOUT0_MODE_V  0x00000001U
-#define SPI_MEM_DOUT0_MODE_S  0
-/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_C_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_C_DOUT0_MODE_M  (SPI_MEM_C_DOUT0_MODE_V << SPI_MEM_C_DOUT0_MODE_S)
+#define SPI_MEM_C_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT0_MODE_S  0
+/** SPI_MEM_C_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S)
-#define SPI_MEM_DOUT1_MODE_V  0x00000001U
-#define SPI_MEM_DOUT1_MODE_S  1
-/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_C_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_C_DOUT1_MODE_M  (SPI_MEM_C_DOUT1_MODE_V << SPI_MEM_C_DOUT1_MODE_S)
+#define SPI_MEM_C_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT1_MODE_S  1
+/** SPI_MEM_C_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S)
-#define SPI_MEM_DOUT2_MODE_V  0x00000001U
-#define SPI_MEM_DOUT2_MODE_S  2
-/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+#define SPI_MEM_C_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_C_DOUT2_MODE_M  (SPI_MEM_C_DOUT2_MODE_V << SPI_MEM_C_DOUT2_MODE_S)
+#define SPI_MEM_C_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT2_MODE_S  2
+/** SPI_MEM_C_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S)
-#define SPI_MEM_DOUT3_MODE_V  0x00000001U
-#define SPI_MEM_DOUT3_MODE_S  3
-/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_C_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_C_DOUT3_MODE_M  (SPI_MEM_C_DOUT3_MODE_V << SPI_MEM_C_DOUT3_MODE_S)
+#define SPI_MEM_C_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT3_MODE_S  3
+/** SPI_MEM_C_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_DOUT4_MODE_M  (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S)
-#define SPI_MEM_DOUT4_MODE_V  0x00000001U
-#define SPI_MEM_DOUT4_MODE_S  4
-/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_C_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_C_DOUT4_MODE_M  (SPI_MEM_C_DOUT4_MODE_V << SPI_MEM_C_DOUT4_MODE_S)
+#define SPI_MEM_C_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT4_MODE_S  4
+/** SPI_MEM_C_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_DOUT5_MODE_M  (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S)
-#define SPI_MEM_DOUT5_MODE_V  0x00000001U
-#define SPI_MEM_DOUT5_MODE_S  5
-/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_C_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_C_DOUT5_MODE_M  (SPI_MEM_C_DOUT5_MODE_V << SPI_MEM_C_DOUT5_MODE_S)
+#define SPI_MEM_C_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT5_MODE_S  5
+/** SPI_MEM_C_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_DOUT6_MODE_M  (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S)
-#define SPI_MEM_DOUT6_MODE_V  0x00000001U
-#define SPI_MEM_DOUT6_MODE_S  6
-/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_C_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_C_DOUT6_MODE_M  (SPI_MEM_C_DOUT6_MODE_V << SPI_MEM_C_DOUT6_MODE_S)
+#define SPI_MEM_C_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT6_MODE_S  6
+/** SPI_MEM_C_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_DOUT7_MODE_M  (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S)
-#define SPI_MEM_DOUT7_MODE_V  0x00000001U
-#define SPI_MEM_DOUT7_MODE_S  7
-/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_C_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_C_DOUT7_MODE_M  (SPI_MEM_C_DOUT7_MODE_V << SPI_MEM_C_DOUT7_MODE_S)
+#define SPI_MEM_C_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT7_MODE_S  7
+/** SPI_MEM_C_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_DOUTS_MODE_M  (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S)
-#define SPI_MEM_DOUTS_MODE_V  0x00000001U
-#define SPI_MEM_DOUTS_MODE_S  8
+#define SPI_MEM_C_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_C_DOUTS_MODE_M  (SPI_MEM_C_DOUTS_MODE_V << SPI_MEM_C_DOUTS_MODE_S)
+#define SPI_MEM_C_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUTS_MODE_S  8
 
-/** SPI_SMEM_TIMING_CALI_REG register
+/** SPI_MEM_C_SMEM_TIMING_CALI_REG register
  *  MSPI external RAM timing calibration register
  */
-#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI0_BASE + 0x190)
-/** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1;
+#define SPI_MEM_C_SMEM_TIMING_CALI_REG (DR_REG_FLASH_SPI0_BASE + 0x190)
+/** SPI_MEM_C_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1;
  *  For sram, the bit is used to enable timing adjust clock for all reading operations.
  */
-#define SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_SMEM_TIMING_CLK_ENA_M  (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S)
-#define SPI_SMEM_TIMING_CLK_ENA_V  0x00000001U
-#define SPI_SMEM_TIMING_CLK_ENA_S  0
-/** SPI_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0;
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_M  (SPI_MEM_C_SMEM_TIMING_CLK_ENA_V << SPI_MEM_C_SMEM_TIMING_CLK_ENA_S)
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_S  0
+/** SPI_MEM_C_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0;
  *  For sram, the bit is used to enable timing auto-calibration for all reading
  *  operations.
  */
-#define SPI_SMEM_TIMING_CALI    (BIT(1))
-#define SPI_SMEM_TIMING_CALI_M  (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S)
-#define SPI_SMEM_TIMING_CALI_V  0x00000001U
-#define SPI_SMEM_TIMING_CALI_S  1
-/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0;
+#define SPI_MEM_C_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_C_SMEM_TIMING_CALI_M  (SPI_MEM_C_SMEM_TIMING_CALI_V << SPI_MEM_C_SMEM_TIMING_CALI_S)
+#define SPI_MEM_C_SMEM_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_SMEM_TIMING_CALI_S  1
+/** SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0;
  *  For sram, add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/** SPI_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_C_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
  *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
  *  EXT_RAM.
  */
-#define SPI_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_SMEM_DLL_TIMING_CALI_M  (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S)
-#define SPI_SMEM_DLL_TIMING_CALI_V  0x00000001U
-#define SPI_SMEM_DLL_TIMING_CALI_S  5
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_M  (SPI_MEM_C_SMEM_DLL_TIMING_CALI_V << SPI_MEM_C_SMEM_DLL_TIMING_CALI_S)
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_S  5
 
-/** SPI_SMEM_DIN_MODE_REG register
+/** SPI_MEM_C_SMEM_DIN_MODE_REG register
  *  MSPI external RAM input timing delay mode control register
  */
-#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI0_BASE + 0x194)
-/** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0;
+#define SPI_MEM_C_SMEM_DIN_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x194)
+/** SPI_MEM_C_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN0_MODE    0x00000007U
-#define SPI_SMEM_DIN0_MODE_M  (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S)
-#define SPI_SMEM_DIN0_MODE_V  0x00000007U
-#define SPI_SMEM_DIN0_MODE_S  0
-/** SPI_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0;
+#define SPI_MEM_C_SMEM_DIN0_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN0_MODE_M  (SPI_MEM_C_SMEM_DIN0_MODE_V << SPI_MEM_C_SMEM_DIN0_MODE_S)
+#define SPI_MEM_C_SMEM_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN0_MODE_S  0
+/** SPI_MEM_C_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN1_MODE    0x00000007U
-#define SPI_SMEM_DIN1_MODE_M  (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S)
-#define SPI_SMEM_DIN1_MODE_V  0x00000007U
-#define SPI_SMEM_DIN1_MODE_S  3
-/** SPI_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0;
+#define SPI_MEM_C_SMEM_DIN1_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN1_MODE_M  (SPI_MEM_C_SMEM_DIN1_MODE_V << SPI_MEM_C_SMEM_DIN1_MODE_S)
+#define SPI_MEM_C_SMEM_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN1_MODE_S  3
+/** SPI_MEM_C_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN2_MODE    0x00000007U
-#define SPI_SMEM_DIN2_MODE_M  (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S)
-#define SPI_SMEM_DIN2_MODE_V  0x00000007U
-#define SPI_SMEM_DIN2_MODE_S  6
-/** SPI_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0;
+#define SPI_MEM_C_SMEM_DIN2_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN2_MODE_M  (SPI_MEM_C_SMEM_DIN2_MODE_V << SPI_MEM_C_SMEM_DIN2_MODE_S)
+#define SPI_MEM_C_SMEM_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN2_MODE_S  6
+/** SPI_MEM_C_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN3_MODE    0x00000007U
-#define SPI_SMEM_DIN3_MODE_M  (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S)
-#define SPI_SMEM_DIN3_MODE_V  0x00000007U
-#define SPI_SMEM_DIN3_MODE_S  9
-/** SPI_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0;
+#define SPI_MEM_C_SMEM_DIN3_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN3_MODE_M  (SPI_MEM_C_SMEM_DIN3_MODE_V << SPI_MEM_C_SMEM_DIN3_MODE_S)
+#define SPI_MEM_C_SMEM_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN3_MODE_S  9
+/** SPI_MEM_C_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN4_MODE    0x00000007U
-#define SPI_SMEM_DIN4_MODE_M  (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S)
-#define SPI_SMEM_DIN4_MODE_V  0x00000007U
-#define SPI_SMEM_DIN4_MODE_S  12
-/** SPI_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0;
+#define SPI_MEM_C_SMEM_DIN4_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN4_MODE_M  (SPI_MEM_C_SMEM_DIN4_MODE_V << SPI_MEM_C_SMEM_DIN4_MODE_S)
+#define SPI_MEM_C_SMEM_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN4_MODE_S  12
+/** SPI_MEM_C_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN5_MODE    0x00000007U
-#define SPI_SMEM_DIN5_MODE_M  (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S)
-#define SPI_SMEM_DIN5_MODE_V  0x00000007U
-#define SPI_SMEM_DIN5_MODE_S  15
-/** SPI_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0;
+#define SPI_MEM_C_SMEM_DIN5_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN5_MODE_M  (SPI_MEM_C_SMEM_DIN5_MODE_V << SPI_MEM_C_SMEM_DIN5_MODE_S)
+#define SPI_MEM_C_SMEM_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN5_MODE_S  15
+/** SPI_MEM_C_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN6_MODE    0x00000007U
-#define SPI_SMEM_DIN6_MODE_M  (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S)
-#define SPI_SMEM_DIN6_MODE_V  0x00000007U
-#define SPI_SMEM_DIN6_MODE_S  18
-/** SPI_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0;
+#define SPI_MEM_C_SMEM_DIN6_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN6_MODE_M  (SPI_MEM_C_SMEM_DIN6_MODE_V << SPI_MEM_C_SMEM_DIN6_MODE_S)
+#define SPI_MEM_C_SMEM_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN6_MODE_S  18
+/** SPI_MEM_C_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN7_MODE    0x00000007U
-#define SPI_SMEM_DIN7_MODE_M  (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S)
-#define SPI_SMEM_DIN7_MODE_V  0x00000007U
-#define SPI_SMEM_DIN7_MODE_S  21
-/** SPI_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0;
+#define SPI_MEM_C_SMEM_DIN7_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN7_MODE_M  (SPI_MEM_C_SMEM_DIN7_MODE_V << SPI_MEM_C_SMEM_DIN7_MODE_S)
+#define SPI_MEM_C_SMEM_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN7_MODE_S  21
+/** SPI_MEM_C_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DINS_MODE    0x00000007U
-#define SPI_SMEM_DINS_MODE_M  (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S)
-#define SPI_SMEM_DINS_MODE_V  0x00000007U
-#define SPI_SMEM_DINS_MODE_S  24
+#define SPI_MEM_C_SMEM_DINS_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DINS_MODE_M  (SPI_MEM_C_SMEM_DINS_MODE_V << SPI_MEM_C_SMEM_DINS_MODE_S)
+#define SPI_MEM_C_SMEM_DINS_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DINS_MODE_S  24
 
-/** SPI_SMEM_DIN_NUM_REG register
+/** SPI_MEM_C_SMEM_DIN_NUM_REG register
  *  MSPI external RAM input timing delay number control register
  */
-#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI0_BASE + 0x198)
-/** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0;
+#define SPI_MEM_C_SMEM_DIN_NUM_REG (DR_REG_FLASH_SPI0_BASE + 0x198)
+/** SPI_MEM_C_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN0_NUM    0x00000003U
-#define SPI_SMEM_DIN0_NUM_M  (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S)
-#define SPI_SMEM_DIN0_NUM_V  0x00000003U
-#define SPI_SMEM_DIN0_NUM_S  0
-/** SPI_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0;
+#define SPI_MEM_C_SMEM_DIN0_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN0_NUM_M  (SPI_MEM_C_SMEM_DIN0_NUM_V << SPI_MEM_C_SMEM_DIN0_NUM_S)
+#define SPI_MEM_C_SMEM_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN0_NUM_S  0
+/** SPI_MEM_C_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN1_NUM    0x00000003U
-#define SPI_SMEM_DIN1_NUM_M  (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S)
-#define SPI_SMEM_DIN1_NUM_V  0x00000003U
-#define SPI_SMEM_DIN1_NUM_S  2
-/** SPI_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0;
+#define SPI_MEM_C_SMEM_DIN1_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN1_NUM_M  (SPI_MEM_C_SMEM_DIN1_NUM_V << SPI_MEM_C_SMEM_DIN1_NUM_S)
+#define SPI_MEM_C_SMEM_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN1_NUM_S  2
+/** SPI_MEM_C_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN2_NUM    0x00000003U
-#define SPI_SMEM_DIN2_NUM_M  (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S)
-#define SPI_SMEM_DIN2_NUM_V  0x00000003U
-#define SPI_SMEM_DIN2_NUM_S  4
-/** SPI_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0;
+#define SPI_MEM_C_SMEM_DIN2_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN2_NUM_M  (SPI_MEM_C_SMEM_DIN2_NUM_V << SPI_MEM_C_SMEM_DIN2_NUM_S)
+#define SPI_MEM_C_SMEM_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN2_NUM_S  4
+/** SPI_MEM_C_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN3_NUM    0x00000003U
-#define SPI_SMEM_DIN3_NUM_M  (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S)
-#define SPI_SMEM_DIN3_NUM_V  0x00000003U
-#define SPI_SMEM_DIN3_NUM_S  6
-/** SPI_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
+#define SPI_MEM_C_SMEM_DIN3_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN3_NUM_M  (SPI_MEM_C_SMEM_DIN3_NUM_V << SPI_MEM_C_SMEM_DIN3_NUM_S)
+#define SPI_MEM_C_SMEM_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN3_NUM_S  6
+/** SPI_MEM_C_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN4_NUM    0x00000003U
-#define SPI_SMEM_DIN4_NUM_M  (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S)
-#define SPI_SMEM_DIN4_NUM_V  0x00000003U
-#define SPI_SMEM_DIN4_NUM_S  8
-/** SPI_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
+#define SPI_MEM_C_SMEM_DIN4_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN4_NUM_M  (SPI_MEM_C_SMEM_DIN4_NUM_V << SPI_MEM_C_SMEM_DIN4_NUM_S)
+#define SPI_MEM_C_SMEM_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN4_NUM_S  8
+/** SPI_MEM_C_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN5_NUM    0x00000003U
-#define SPI_SMEM_DIN5_NUM_M  (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S)
-#define SPI_SMEM_DIN5_NUM_V  0x00000003U
-#define SPI_SMEM_DIN5_NUM_S  10
-/** SPI_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
+#define SPI_MEM_C_SMEM_DIN5_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN5_NUM_M  (SPI_MEM_C_SMEM_DIN5_NUM_V << SPI_MEM_C_SMEM_DIN5_NUM_S)
+#define SPI_MEM_C_SMEM_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN5_NUM_S  10
+/** SPI_MEM_C_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN6_NUM    0x00000003U
-#define SPI_SMEM_DIN6_NUM_M  (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S)
-#define SPI_SMEM_DIN6_NUM_V  0x00000003U
-#define SPI_SMEM_DIN6_NUM_S  12
-/** SPI_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
+#define SPI_MEM_C_SMEM_DIN6_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN6_NUM_M  (SPI_MEM_C_SMEM_DIN6_NUM_V << SPI_MEM_C_SMEM_DIN6_NUM_S)
+#define SPI_MEM_C_SMEM_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN6_NUM_S  12
+/** SPI_MEM_C_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN7_NUM    0x00000003U
-#define SPI_SMEM_DIN7_NUM_M  (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S)
-#define SPI_SMEM_DIN7_NUM_V  0x00000003U
-#define SPI_SMEM_DIN7_NUM_S  14
-/** SPI_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0;
+#define SPI_MEM_C_SMEM_DIN7_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN7_NUM_M  (SPI_MEM_C_SMEM_DIN7_NUM_V << SPI_MEM_C_SMEM_DIN7_NUM_S)
+#define SPI_MEM_C_SMEM_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN7_NUM_S  14
+/** SPI_MEM_C_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DINS_NUM    0x00000003U
-#define SPI_SMEM_DINS_NUM_M  (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S)
-#define SPI_SMEM_DINS_NUM_V  0x00000003U
-#define SPI_SMEM_DINS_NUM_S  16
+#define SPI_MEM_C_SMEM_DINS_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DINS_NUM_M  (SPI_MEM_C_SMEM_DINS_NUM_V << SPI_MEM_C_SMEM_DINS_NUM_S)
+#define SPI_MEM_C_SMEM_DINS_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DINS_NUM_S  16
 
-/** SPI_SMEM_DOUT_MODE_REG register
+/** SPI_MEM_C_SMEM_DOUT_MODE_REG register
  *  MSPI external RAM output timing adjustment control register
  */
-#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI0_BASE + 0x19c)
-/** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x19c)
+/** SPI_MEM_C_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT0_MODE    (BIT(0))
-#define SPI_SMEM_DOUT0_MODE_M  (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S)
-#define SPI_SMEM_DOUT0_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT0_MODE_S  0
-/** SPI_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_C_SMEM_DOUT0_MODE_M  (SPI_MEM_C_SMEM_DOUT0_MODE_V << SPI_MEM_C_SMEM_DOUT0_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT0_MODE_S  0
+/** SPI_MEM_C_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT1_MODE    (BIT(1))
-#define SPI_SMEM_DOUT1_MODE_M  (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S)
-#define SPI_SMEM_DOUT1_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT1_MODE_S  1
-/** SPI_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_C_SMEM_DOUT1_MODE_M  (SPI_MEM_C_SMEM_DOUT1_MODE_V << SPI_MEM_C_SMEM_DOUT1_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT1_MODE_S  1
+/** SPI_MEM_C_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT2_MODE    (BIT(2))
-#define SPI_SMEM_DOUT2_MODE_M  (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S)
-#define SPI_SMEM_DOUT2_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT2_MODE_S  2
-/** SPI_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_C_SMEM_DOUT2_MODE_M  (SPI_MEM_C_SMEM_DOUT2_MODE_V << SPI_MEM_C_SMEM_DOUT2_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT2_MODE_S  2
+/** SPI_MEM_C_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT3_MODE    (BIT(3))
-#define SPI_SMEM_DOUT3_MODE_M  (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S)
-#define SPI_SMEM_DOUT3_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT3_MODE_S  3
-/** SPI_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_C_SMEM_DOUT3_MODE_M  (SPI_MEM_C_SMEM_DOUT3_MODE_V << SPI_MEM_C_SMEM_DOUT3_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT3_MODE_S  3
+/** SPI_MEM_C_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT4_MODE    (BIT(4))
-#define SPI_SMEM_DOUT4_MODE_M  (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S)
-#define SPI_SMEM_DOUT4_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT4_MODE_S  4
-/** SPI_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_C_SMEM_DOUT4_MODE_M  (SPI_MEM_C_SMEM_DOUT4_MODE_V << SPI_MEM_C_SMEM_DOUT4_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT4_MODE_S  4
+/** SPI_MEM_C_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT5_MODE    (BIT(5))
-#define SPI_SMEM_DOUT5_MODE_M  (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S)
-#define SPI_SMEM_DOUT5_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT5_MODE_S  5
-/** SPI_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_C_SMEM_DOUT5_MODE_M  (SPI_MEM_C_SMEM_DOUT5_MODE_V << SPI_MEM_C_SMEM_DOUT5_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT5_MODE_S  5
+/** SPI_MEM_C_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT6_MODE    (BIT(6))
-#define SPI_SMEM_DOUT6_MODE_M  (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S)
-#define SPI_SMEM_DOUT6_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT6_MODE_S  6
-/** SPI_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_C_SMEM_DOUT6_MODE_M  (SPI_MEM_C_SMEM_DOUT6_MODE_V << SPI_MEM_C_SMEM_DOUT6_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT6_MODE_S  6
+/** SPI_MEM_C_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT7_MODE    (BIT(7))
-#define SPI_SMEM_DOUT7_MODE_M  (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S)
-#define SPI_SMEM_DOUT7_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT7_MODE_S  7
-/** SPI_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0;
+#define SPI_MEM_C_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_C_SMEM_DOUT7_MODE_M  (SPI_MEM_C_SMEM_DOUT7_MODE_V << SPI_MEM_C_SMEM_DOUT7_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT7_MODE_S  7
+/** SPI_MEM_C_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUTS_MODE    (BIT(8))
-#define SPI_SMEM_DOUTS_MODE_M  (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S)
-#define SPI_SMEM_DOUTS_MODE_V  0x00000001U
-#define SPI_SMEM_DOUTS_MODE_S  8
+#define SPI_MEM_C_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_C_SMEM_DOUTS_MODE_M  (SPI_MEM_C_SMEM_DOUTS_MODE_V << SPI_MEM_C_SMEM_DOUTS_MODE_S)
+#define SPI_MEM_C_SMEM_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUTS_MODE_S  8
 
-/** SPI_SMEM_AC_REG register
+/** SPI_MEM_C_SMEM_AC_REG register
  *  MSPI external RAM ECC and SPI CS timing control register
  */
-#define SPI_SMEM_AC_REG (DR_REG_SPI0_BASE + 0x1a0)
-/** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0;
+#define SPI_MEM_C_SMEM_AC_REG (DR_REG_FLASH_SPI0_BASE + 0x1a0)
+/** SPI_MEM_C_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0;
  *  For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
  *  disable.
  */
-#define SPI_SMEM_CS_SETUP    (BIT(0))
-#define SPI_SMEM_CS_SETUP_M  (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S)
-#define SPI_SMEM_CS_SETUP_V  0x00000001U
-#define SPI_SMEM_CS_SETUP_S  0
-/** SPI_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0;
+#define SPI_MEM_C_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_C_SMEM_CS_SETUP_M  (SPI_MEM_C_SMEM_CS_SETUP_V << SPI_MEM_C_SMEM_CS_SETUP_S)
+#define SPI_MEM_C_SMEM_CS_SETUP_V  0x00000001U
+#define SPI_MEM_C_SMEM_CS_SETUP_S  0
+/** SPI_MEM_C_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0;
  *  For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.
  */
-#define SPI_SMEM_CS_HOLD    (BIT(1))
-#define SPI_SMEM_CS_HOLD_M  (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S)
-#define SPI_SMEM_CS_HOLD_V  0x00000001U
-#define SPI_SMEM_CS_HOLD_S  1
-/** SPI_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1;
+#define SPI_MEM_C_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_C_SMEM_CS_HOLD_M  (SPI_MEM_C_SMEM_CS_HOLD_V << SPI_MEM_C_SMEM_CS_HOLD_S)
+#define SPI_MEM_C_SMEM_CS_HOLD_V  0x00000001U
+#define SPI_MEM_C_SMEM_CS_HOLD_S  1
+/** SPI_MEM_C_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1;
  *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
  *  spi_mem_cs_setup bit.
  */
-#define SPI_SMEM_CS_SETUP_TIME    0x0000001FU
-#define SPI_SMEM_CS_SETUP_TIME_M  (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S)
-#define SPI_SMEM_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_SMEM_CS_SETUP_TIME_S  2
-/** SPI_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1;
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME_M  (SPI_MEM_C_SMEM_CS_SETUP_TIME_V << SPI_MEM_C_SMEM_CS_SETUP_TIME_S)
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME_S  2
+/** SPI_MEM_C_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1;
  *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
  *  combined with spi_mem_cs_hold bit.
  */
-#define SPI_SMEM_CS_HOLD_TIME    0x0000001FU
-#define SPI_SMEM_CS_HOLD_TIME_M  (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S)
-#define SPI_SMEM_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_SMEM_CS_HOLD_TIME_S  7
-/** SPI_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3;
- *  SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME_M  (SPI_MEM_C_SMEM_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_CS_HOLD_TIME_S)
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME_S  7
+/** SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3;
+ *  SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
  *  cycles in ECC mode when accessed external RAM.
  */
-#define SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007U
-#define SPI_SMEM_ECC_CS_HOLD_TIME_M  (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S)
-#define SPI_SMEM_ECC_CS_HOLD_TIME_V  0x00000007U
-#define SPI_SMEM_ECC_CS_HOLD_TIME_S  12
-/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1;
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_M  (SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S  12
+/** SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1;
  *  1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when
  *  accesses external RAM.
  */
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S)
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/** SPI_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0;
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/** SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0;
  *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
  *  accesses external RAM.
  */
-#define SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_M  (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S)
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x00000001U
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
-/** SPI_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0;
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_M  (SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S  16
+/** SPI_MEM_C_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0;
  *  These bits are used to set the minimum CS high time tSHSL between SPI burst
- *  transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1)
+ *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1)
  *  MSPI core clock cycles.
  */
-#define SPI_SMEM_CS_HOLD_DELAY    0x0000003FU
-#define SPI_SMEM_CS_HOLD_DELAY_M  (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S)
-#define SPI_SMEM_CS_HOLD_DELAY_V  0x0000003FU
-#define SPI_SMEM_CS_HOLD_DELAY_S  25
-/** SPI_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 1;
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_M  (SPI_MEM_C_SMEM_CS_HOLD_DELAY_V << SPI_MEM_C_SMEM_CS_HOLD_DELAY_S)
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_S  25
+/** SPI_MEM_C_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 1;
  *  Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
  *  transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter
  *  whether there is an ECC region or not.
  */
-#define SPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define SPI_SMEM_SPLIT_TRANS_EN_M  (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S)
-#define SPI_SMEM_SPLIT_TRANS_EN_V  0x00000001U
-#define SPI_SMEM_SPLIT_TRANS_EN_S  31
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_M  (SPI_MEM_C_SMEM_SPLIT_TRANS_EN_V << SPI_MEM_C_SMEM_SPLIT_TRANS_EN_S)
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_S  31
 
-/** SPI_MEM_CLOCK_GATE_REG register
+/** SPI_MEM_C_CLOCK_GATE_REG register
  *  SPI0 clock gate register
  */
-#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI0_BASE + 0x200)
-/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI0_BASE + 0x200)
+/** SPI_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Register clock gate enable signal. 1: Enable. 0: Disable.
  */
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
-#define SPI_CLK_EN_V  0x00000001U
-#define SPI_CLK_EN_S  0
+#define SPI_MEM_C_CLK_EN    (BIT(0))
+#define SPI_MEM_C_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
+#define SPI_MEM_C_CLK_EN_V  0x00000001U
+#define SPI_MEM_C_CLK_EN_S  0
 
-/** SPI_MEM_XTS_PLAIN_BASE_REG register
+/** SPI_MEM_C_XTS_PLAIN_BASE_REG register
  *  The base address of the memory that stores plaintext in Manual Encryption
  */
-#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI0_BASE + 0x300)
-/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
+#define SPI_MEM_C_XTS_PLAIN_BASE_REG (DR_REG_FLASH_SPI0_BASE + 0x300)
+/** SPI_MEM_C_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
  *  This field is only used to generate include file in c case. This field is useless.
  *  Please do not use this field.
  */
-#define SPI_XTS_PLAIN    0xFFFFFFFFU
-#define SPI_XTS_PLAIN_M  (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S)
-#define SPI_XTS_PLAIN_V  0xFFFFFFFFU
-#define SPI_XTS_PLAIN_S  0
+#define SPI_MEM_C_XTS_PLAIN    0xFFFFFFFFU
+#define SPI_MEM_C_XTS_PLAIN_M  (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S)
+#define SPI_MEM_C_XTS_PLAIN_V  0xFFFFFFFFU
+#define SPI_MEM_C_XTS_PLAIN_S  0
 
-/** SPI_MEM_XTS_LINESIZE_REG register
+/** SPI_MEM_C_XTS_LINESIZE_REG register
  *  Manual Encryption Line-Size register
  */
-#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI0_BASE + 0x340)
-/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_C_XTS_LINESIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x340)
+/** SPI_MEM_C_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
  *  This bits stores the line-size parameter which will be used in manual encryption
  *  calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
  *  32-bytes, 2: 64-bytes, 3:reserved.
  */
-#define SPI_XTS_LINESIZE    0x00000003U
-#define SPI_XTS_LINESIZE_M  (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S)
-#define SPI_XTS_LINESIZE_V  0x00000003U
-#define SPI_XTS_LINESIZE_S  0
+#define SPI_MEM_C_XTS_LINESIZE    0x00000003U
+#define SPI_MEM_C_XTS_LINESIZE_M  (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S)
+#define SPI_MEM_C_XTS_LINESIZE_V  0x00000003U
+#define SPI_MEM_C_XTS_LINESIZE_S  0
 
-/** SPI_MEM_XTS_DESTINATION_REG register
+/** SPI_MEM_C_XTS_DESTINATION_REG register
  *  Manual Encryption destination register
  */
-#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI0_BASE + 0x344)
-/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_C_XTS_DESTINATION_REG (DR_REG_FLASH_SPI0_BASE + 0x344)
+/** SPI_MEM_C_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
  *  This bit stores the destination parameter which will be used in manual encryption
  *  calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
  */
-#define SPI_XTS_DESTINATION    (BIT(0))
-#define SPI_XTS_DESTINATION_M  (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S)
-#define SPI_XTS_DESTINATION_V  0x00000001U
-#define SPI_XTS_DESTINATION_S  0
+#define SPI_MEM_C_XTS_DESTINATION    (BIT(0))
+#define SPI_MEM_C_XTS_DESTINATION_M  (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S)
+#define SPI_MEM_C_XTS_DESTINATION_V  0x00000001U
+#define SPI_MEM_C_XTS_DESTINATION_S  0
 
-/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register
+/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI0_BASE + 0x348)
-/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG (DR_REG_FLASH_SPI0_BASE + 0x348)
+/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
  *  This bits stores the physical-address parameter which will be used in manual
  *  encryption calculation. This value should aligned with byte number decided by
  *  line-size parameter.
  */
-#define SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFFU
-#define SPI_XTS_PHYSICAL_ADDRESS_M  (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S)
-#define SPI_XTS_PHYSICAL_ADDRESS_V  0x03FFFFFFU
-#define SPI_XTS_PHYSICAL_ADDRESS_S  0
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS    0x03FFFFFFU
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_M  (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S)
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V  0x03FFFFFFU
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_S  0
 
-/** SPI_MEM_XTS_TRIGGER_REG register
+/** SPI_MEM_C_XTS_TRIGGER_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI0_BASE + 0x34c)
+#define SPI_MEM_C_XTS_TRIGGER_REG (DR_REG_FLASH_SPI0_BASE + 0x34c)
 /** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0;
  *  Set this bit to trigger the process of manual encryption calculation. This action
  *  should only be asserted when manual encryption status is 0. After this action,
@@ -2570,167 +2570,167 @@ extern "C" {
 #define SPI_XTS_TRIGGER_V  0x00000001U
 #define SPI_XTS_TRIGGER_S  0
 
-/** SPI_MEM_XTS_RELEASE_REG register
+/** SPI_MEM_C_XTS_RELEASE_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI0_BASE + 0x350)
-/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0;
+#define SPI_MEM_C_XTS_RELEASE_REG (DR_REG_FLASH_SPI0_BASE + 0x350)
+/** SPI_MEM_C_XTS_RELEASE : WT; bitpos: [0]; default: 0;
  *  Set this bit to release encrypted result to mspi. This action should only be
  *  asserted when manual encryption status is 2. After this action, manual encryption
  *  status will become 3.
  */
-#define SPI_XTS_RELEASE    (BIT(0))
-#define SPI_XTS_RELEASE_M  (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S)
-#define SPI_XTS_RELEASE_V  0x00000001U
-#define SPI_XTS_RELEASE_S  0
+#define SPI_MEM_C_XTS_RELEASE    (BIT(0))
+#define SPI_MEM_C_XTS_RELEASE_M  (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S)
+#define SPI_MEM_C_XTS_RELEASE_V  0x00000001U
+#define SPI_MEM_C_XTS_RELEASE_S  0
 
-/** SPI_MEM_XTS_DESTROY_REG register
+/** SPI_MEM_C_XTS_DESTROY_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI0_BASE + 0x354)
-/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0;
+#define SPI_MEM_C_XTS_DESTROY_REG (DR_REG_FLASH_SPI0_BASE + 0x354)
+/** SPI_MEM_C_XTS_DESTROY : WT; bitpos: [0]; default: 0;
  *  Set this bit to destroy encrypted result. This action should be asserted only when
  *  manual encryption status is 3. After this action, manual encryption status will
  *  become 0.
  */
-#define SPI_XTS_DESTROY    (BIT(0))
-#define SPI_XTS_DESTROY_M  (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S)
-#define SPI_XTS_DESTROY_V  0x00000001U
-#define SPI_XTS_DESTROY_S  0
+#define SPI_MEM_C_XTS_DESTROY    (BIT(0))
+#define SPI_MEM_C_XTS_DESTROY_M  (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S)
+#define SPI_MEM_C_XTS_DESTROY_V  0x00000001U
+#define SPI_MEM_C_XTS_DESTROY_S  0
 
-/** SPI_MEM_XTS_STATE_REG register
+/** SPI_MEM_C_XTS_STATE_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI0_BASE + 0x358)
-/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0;
+#define SPI_MEM_C_XTS_STATE_REG (DR_REG_FLASH_SPI0_BASE + 0x358)
+/** SPI_MEM_C_XTS_STATE : RO; bitpos: [1:0]; default: 0;
  *  This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
  *  calculation, 2: encryption calculation is done but the encrypted result is
  *  invisible to mspi, 3: the encrypted result is visible to mspi.
  */
-#define SPI_XTS_STATE    0x00000003U
-#define SPI_XTS_STATE_M  (SPI_XTS_STATE_V << SPI_XTS_STATE_S)
-#define SPI_XTS_STATE_V  0x00000003U
-#define SPI_XTS_STATE_S  0
+#define SPI_MEM_C_XTS_STATE    0x00000003U
+#define SPI_MEM_C_XTS_STATE_M  (SPI_XTS_STATE_V << SPI_XTS_STATE_S)
+#define SPI_MEM_C_XTS_STATE_V  0x00000003U
+#define SPI_MEM_C_XTS_STATE_S  0
 
-/** SPI_MEM_XTS_DATE_REG register
+/** SPI_MEM_C_XTS_DATE_REG register
  *  Manual Encryption version register
  */
-#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI0_BASE + 0x35c)
-/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176;
+#define SPI_MEM_C_XTS_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x35c)
+/** SPI_MEM_C_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176;
  *  This bits stores the last modified-time of manual encryption feature.
  */
-#define SPI_XTS_DATE    0x3FFFFFFFU
-#define SPI_XTS_DATE_M  (SPI_XTS_DATE_V << SPI_XTS_DATE_S)
-#define SPI_XTS_DATE_V  0x3FFFFFFFU
-#define SPI_XTS_DATE_S  0
+#define SPI_MEM_C_XTS_DATE    0x3FFFFFFFU
+#define SPI_MEM_C_XTS_DATE_M  (SPI_XTS_DATE_V << SPI_XTS_DATE_S)
+#define SPI_MEM_C_XTS_DATE_V  0x3FFFFFFFU
+#define SPI_MEM_C_XTS_DATE_S  0
 
-/** SPI_MEM_MMU_ITEM_CONTENT_REG register
+/** SPI_MEM_C_MMU_ITEM_CONTENT_REG register
  *  MSPI-MMU item content register
  */
-#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI0_BASE + 0x37c)
-/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
+#define SPI_MEM_C_MMU_ITEM_CONTENT_REG (DR_REG_FLASH_SPI0_BASE + 0x37c)
+/** SPI_MEM_C_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
  *  MSPI-MMU item content
  */
-#define SPI_MMU_ITEM_CONTENT    0xFFFFFFFFU
-#define SPI_MMU_ITEM_CONTENT_M  (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S)
-#define SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFFU
-#define SPI_MMU_ITEM_CONTENT_S  0
+#define SPI_MEM_C_MMU_ITEM_CONTENT    0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_CONTENT_M  (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S)
+#define SPI_MEM_C_MMU_ITEM_CONTENT_V  0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_CONTENT_S  0
 
-/** SPI_MEM_MMU_ITEM_INDEX_REG register
+/** SPI_MEM_C_MMU_ITEM_INDEX_REG register
  *  MSPI-MMU item index register
  */
-#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI0_BASE + 0x380)
-/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
+#define SPI_MEM_C_MMU_ITEM_INDEX_REG (DR_REG_FLASH_SPI0_BASE + 0x380)
+/** SPI_MEM_C_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
  *  MSPI-MMU item index
  */
-#define SPI_MMU_ITEM_INDEX    0xFFFFFFFFU
-#define SPI_MMU_ITEM_INDEX_M  (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S)
-#define SPI_MMU_ITEM_INDEX_V  0xFFFFFFFFU
-#define SPI_MMU_ITEM_INDEX_S  0
+#define SPI_MEM_C_MMU_ITEM_INDEX    0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_INDEX_M  (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S)
+#define SPI_MEM_C_MMU_ITEM_INDEX_V  0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_INDEX_S  0
 
-/** SPI_MEM_MMU_POWER_CTRL_REG register
+/** SPI_MEM_C_MMU_POWER_CTRL_REG register
  *  MSPI MMU power control register
  */
-#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI0_BASE + 0x384)
-/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_C_MMU_POWER_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x384)
+/** SPI_MEM_C_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
  *  Set this bit to enable mmu-memory clock force on
  */
-#define SPI_MMU_MEM_FORCE_ON    (BIT(0))
-#define SPI_MMU_MEM_FORCE_ON_M  (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S)
-#define SPI_MMU_MEM_FORCE_ON_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_ON_S  0
-/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_C_MMU_MEM_FORCE_ON    (BIT(0))
+#define SPI_MEM_C_MMU_MEM_FORCE_ON_M  (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S)
+#define SPI_MEM_C_MMU_MEM_FORCE_ON_V  0x00000001U
+#define SPI_MEM_C_MMU_MEM_FORCE_ON_S  0
+/** SPI_MEM_C_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
  *  Set this bit to force mmu-memory powerdown
  */
-#define SPI_MMU_MEM_FORCE_PD    (BIT(1))
-#define SPI_MMU_MEM_FORCE_PD_M  (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S)
-#define SPI_MMU_MEM_FORCE_PD_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_PD_S  1
-/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+#define SPI_MEM_C_MMU_MEM_FORCE_PD    (BIT(1))
+#define SPI_MEM_C_MMU_MEM_FORCE_PD_M  (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S)
+#define SPI_MEM_C_MMU_MEM_FORCE_PD_V  0x00000001U
+#define SPI_MEM_C_MMU_MEM_FORCE_PD_S  1
+/** SPI_MEM_C_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
  *  Set this bit to force mmu-memory powerup, in this case, the power should also be
  *  controlled by rtc.
  */
-#define SPI_MMU_MEM_FORCE_PU    (BIT(2))
-#define SPI_MMU_MEM_FORCE_PU_M  (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S)
-#define SPI_MMU_MEM_FORCE_PU_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_PU_S  2
-/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0;
+#define SPI_MEM_C_MMU_MEM_FORCE_PU    (BIT(2))
+#define SPI_MEM_C_MMU_MEM_FORCE_PU_M  (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S)
+#define SPI_MEM_C_MMU_MEM_FORCE_PU_V  0x00000001U
+#define SPI_MEM_C_MMU_MEM_FORCE_PU_S  2
+/** SPI_MEM_C_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0;
  *  0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8
  */
-#define SPI_MMU_PAGE_SIZE    0x00000003U
-#define SPI_MMU_PAGE_SIZE_M  (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S)
-#define SPI_MMU_PAGE_SIZE_V  0x00000003U
-#define SPI_MMU_PAGE_SIZE_S  3
-/** SPI_MEM_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896;
+#define SPI_MEM_C_MMU_PAGE_SIZE    0x00000003U
+#define SPI_MEM_C_MMU_PAGE_SIZE_M  (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S)
+#define SPI_MEM_C_MMU_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_C_MMU_PAGE_SIZE_S  3
+/** SPI_MEM_C_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896;
  *  MMU PSRAM aux control register
  */
-#define SPI_MEM_AUX_CTRL    0x00003FFFU
-#define SPI_MEM_AUX_CTRL_M  (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S)
-#define SPI_MEM_AUX_CTRL_V  0x00003FFFU
-#define SPI_MEM_AUX_CTRL_S  16
+#define SPI_MEM_C_AUX_CTRL    0x00003FFFU
+#define SPI_MEM_C_AUX_CTRL_M  (SPI_MEM_C_AUX_CTRL_V << SPI_MEM_C_AUX_CTRL_S)
+#define SPI_MEM_C_AUX_CTRL_V  0x00003FFFU
+#define SPI_MEM_C_AUX_CTRL_S  16
 
-/** SPI_MEM_DPA_CTRL_REG register
+/** SPI_MEM_C_DPA_CTRL_REG register
  *  SPI memory cryption DPA register
  */
-#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI0_BASE + 0x388)
-/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
+#define SPI_MEM_C_DPA_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x388)
+/** SPI_MEM_C_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
  *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
  *  The bigger the number is, the more secure the cryption is. (Note that the
  *  performance of cryption will decrease together with this number increasing)
  */
-#define SPI_CRYPT_SECURITY_LEVEL    0x00000007U
-#define SPI_CRYPT_SECURITY_LEVEL_M  (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S)
-#define SPI_CRYPT_SECURITY_LEVEL_V  0x00000007U
-#define SPI_CRYPT_SECURITY_LEVEL_S  0
-/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1;
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL    0x00000007U
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_M  (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S)
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_V  0x00000007U
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_S  0
+/** SPI_MEM_C_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1;
  *  Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the
  *  calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that
  *  using key 1.
  */
-#define SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define SPI_CRYPT_CALC_D_DPA_EN_M  (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S)
-#define SPI_CRYPT_CALC_D_DPA_EN_V  0x00000001U
-#define SPI_CRYPT_CALC_D_DPA_EN_S  3
-/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_M  (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S)
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_V  0x00000001U
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_S  3
+/** SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0;
  *  1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and
  *  SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.
  */
-#define SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define SPI_CRYPT_DPA_SELECT_REGISTER_M  (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S)
-#define SPI_CRYPT_DPA_SELECT_REGISTER_V  0x00000001U
-#define SPI_CRYPT_DPA_SELECT_REGISTER_S  4
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_M  (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S)
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_V  0x00000001U
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_S  4
 
-/** SPI_MEM_DATE_REG register
+/** SPI_MEM_C_DATE_REG register
  *  SPI0 version control register
  */
-#define SPI_MEM_DATE_REG (DR_REG_SPI0_BASE + 0x3fc)
-/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36712560;
+#define SPI_MEM_C_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x3fc)
+/** SPI_MEM_C_DATE : R/W; bitpos: [27:0]; default: 36712560;
  *  SPI0 register version.
  */
-#define SPI_MEM_DATE    0x0FFFFFFFU
-#define SPI_MEM_DATE_M  (SPI_MEM_DATE_V << SPI_MEM_DATE_S)
-#define SPI_MEM_DATE_V  0x0FFFFFFFU
-#define SPI_MEM_DATE_S  0
+#define SPI_MEM_C_DATE    0x0FFFFFFFU
+#define SPI_MEM_C_DATE_M  (SPI_MEM_C_DATE_V << SPI_MEM_C_DATE_S)
+#define SPI_MEM_C_DATE_V  0x0FFFFFFFU
+#define SPI_MEM_C_DATE_S  0
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h b/components/soc/esp32p4/include/soc/spi_mem_c_struct.h
index d20011f596..208d6dde4d 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_c_struct.h
@@ -30,7 +30,7 @@ typedef union {
         uint32_t mem_slv_st:4;
         uint32_t reserved_8:10;
         /** mem_usr : HRO; bitpos: [18]; default: 0;
-         *  SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
+         *  SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared.  An operation
          *  will be triggered when the bit is set. The bit will be cleared once the operation
          *  done.1: enable 0: disable.
          */
@@ -38,7 +38,7 @@ typedef union {
         uint32_t reserved_19:13;
     };
     uint32_t val;
-} spi_mem_cmd_reg_t;
+} spi_mem_c_cmd_reg_t;
 
 /** Type of mem_axi_err_addr register
  *  SPI0 AXI request error address.
@@ -47,14 +47,14 @@ typedef union {
     struct {
         /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first AXI write/read invalid error or AXI write flash error
-         *  address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
-         *  SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
+         *  address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR,
+         *  spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set.
          */
         uint32_t mem_axi_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_axi_err_addr_reg_t;
+} spi_mem_c_axi_err_addr_reg_t;
 
 
 /** Group: Flash Control and configuration registers */
@@ -108,8 +108,8 @@ typedef union {
         uint32_t mem_fcmd_oct:1;
         uint32_t reserved_10:3;
         /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT
-         *  and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.
+         *  This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT
+         *  and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable.
          */
         uint32_t mem_fastrd_mode:1;
         /** mem_fread_dual : R/W; bitpos: [14]; default: 0;
@@ -157,7 +157,7 @@ typedef union {
         uint32_t mem_data_ie_always_on:1;
     };
     uint32_t val;
-} spi_mem_ctrl_reg_t;
+} spi_mem_c_ctrl_reg_t;
 
 /** Type of mem_ctrl1 register
  *  SPI0 control1 register.
@@ -188,7 +188,7 @@ typedef union {
         /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
          *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
          *  when there is a ECC error in AXI read data. The ECC error information is recorded
-         *  in SPI_MEM_ECC_ERR_ADDR_REG.
+         *  in spi_mem_c_C_ECC_ERR_ADDR_REG.
          */
         uint32_t mem_rresp_ecc_err_en:1;
         /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0;
@@ -200,9 +200,9 @@ typedef union {
          */
         uint32_t mem_aw_splice_en:1;
         /** mem_ram0_en : HRO; bitpos: [27]; default: 1;
-         *  When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be
-         *  accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1
-         *  will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+         *  When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be
+         *  accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1
+         *  will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
          *  accessed at the same time.
          */
         uint32_t mem_ram0_en:1;
@@ -229,7 +229,7 @@ typedef union {
         uint32_t mem_txfifo_rst:1;
     };
     uint32_t val;
-} spi_mem_ctrl1_reg_t;
+} spi_mem_c_ctrl1_reg_t;
 
 /** Type of mem_ctrl2 register
  *  SPI0 control2 register.
@@ -238,16 +238,16 @@ typedef union {
     struct {
         /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1;
          *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
-         *  SPI_MEM_CS_SETUP bit.
+         *  spi_mem_c_C_CS_SETUP bit.
          */
         uint32_t mem_cs_setup_time:5;
         /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1;
          *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
-         *  SPI_MEM_CS_HOLD bit.
+         *  spi_mem_c_C_CS_HOLD bit.
          */
         uint32_t mem_cs_hold_time:5;
         /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3;
-         *  SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+         *  spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
          *  mode when accessed flash.
          */
         uint32_t mem_ecc_cs_hold_time:3;
@@ -270,7 +270,7 @@ typedef union {
         uint32_t mem_split_trans_en:1;
         /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
          *  These bits are used to set the minimum CS high time tSHSL between SPI burst
-         *  transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
+         *  transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI
          *  core clock cycles.
          */
         uint32_t mem_cs_hold_delay:6;
@@ -280,7 +280,7 @@ typedef union {
         uint32_t mem_sync_reset:1;
     };
     uint32_t val;
-} spi_mem_ctrl2_reg_t;
+} spi_mem_c_ctrl2_reg_t;
 
 /** Type of mem_misc register
  *  SPI0 misc register
@@ -307,7 +307,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_misc_reg_t;
+} spi_mem_c_misc_reg_t;
 
 /** Type of mem_cache_fctrl register
  *  SPI0 bit mode control register.
@@ -326,7 +326,7 @@ typedef union {
         uint32_t close_axi_inf_en:1;
     };
     uint32_t val;
-} spi_mem_cache_fctrl_reg_t;
+} spi_mem_c_cache_fctrl_reg_t;
 
 /** Type of mem_ddr register
  *  SPI0 flash DDR mode control register
@@ -373,7 +373,7 @@ typedef union {
         uint32_t fmem_usr_ddr_dqs_thd:7;
         /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -410,7 +410,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_mem_ddr_reg_t;
+} spi_mem_c_ddr_reg_t;
 
 
 /** Group: Clock control and configuration registers */
@@ -420,16 +420,16 @@ typedef union {
 typedef union {
     struct {
         /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
+         *  In the master mode it must be equal to spi_mem_c_clkcnt_N.
          */
         uint32_t mem_clkcnt_l:8;
         /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+         *  In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1).
          */
         uint32_t mem_clkcnt_h:8;
         /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
+         *  In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is
+         *  system/(spi_mem_c_clkcnt_N+1)
          */
         uint32_t mem_clkcnt_n:8;
         uint32_t reserved_24:7;
@@ -440,7 +440,7 @@ typedef union {
         uint32_t mem_clk_equ_sysclk:1;
     };
     uint32_t val;
-} spi_mem_clock_reg_t;
+} spi_mem_c_clock_reg_t;
 
 /** Type of mem_clock_gate register
  *  SPI0 clock gate register
@@ -454,7 +454,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_clock_gate_reg_t;
+} spi_mem_c_clock_gate_reg_t;
 
 
 /** Group: Flash User-defined control registers */
@@ -474,7 +474,7 @@ typedef union {
         uint32_t mem_cs_setup:1;
         uint32_t reserved_8:1;
         /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+         *  The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
          */
         uint32_t mem_ck_out_edge:1;
         uint32_t reserved_10:16;
@@ -490,7 +490,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_user_reg_t;
+} spi_mem_c_user_reg_t;
 
 /** Type of mem_user1 register
  *  SPI0 user1 register.
@@ -498,7 +498,7 @@ typedef union {
 typedef union {
     struct {
         /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+         *  The length in spi_mem_c_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
         uint32_t mem_usr_dummy_cyclelen:6;
@@ -513,7 +513,7 @@ typedef union {
         uint32_t mem_usr_addr_bitlen:6;
     };
     uint32_t val;
-} spi_mem_user1_reg_t;
+} spi_mem_c_user1_reg_t;
 
 /** Type of mem_user2 register
  *  SPI0 user2 register.
@@ -531,7 +531,7 @@ typedef union {
         uint32_t mem_usr_command_bitlen:4;
     };
     uint32_t val;
-} spi_mem_user2_reg_t;
+} spi_mem_c_user2_reg_t;
 
 
 /** Group: External RAM Control and configuration registers */
@@ -564,7 +564,7 @@ typedef union {
         uint32_t smem_data_ie_always_on:1;
     };
     uint32_t val;
-} spi_mem_sram_cmd_reg_t;
+} spi_mem_c_sram_cmd_reg_t;
 
 /** Type of smem_ddr register
  *  SPI0 external RAM DDR mode control register
@@ -611,7 +611,7 @@ typedef union {
         uint32_t smem_usr_ddr_dqs_thd:7;
         /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -649,7 +649,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_smem_ddr_reg_t;
+} spi_mem_c_smem_ddr_reg_t;
 
 /** Type of smem_ac register
  *  MSPI external RAM ECC and SPI CS timing control register
@@ -667,16 +667,16 @@ typedef union {
         uint32_t smem_cs_hold:1;
         /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1;
          *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
-         *  spi_mem_cs_setup bit.
+         *  spi_mem_c_cs_setup bit.
          */
         uint32_t smem_cs_setup_time:5;
         /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1;
          *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
-         *  combined with spi_mem_cs_hold bit.
+         *  combined with spi_mem_c_cs_hold bit.
          */
         uint32_t smem_cs_hold_time:5;
         /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3;
-         *  SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+         *  SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
          *  cycles in ECC mode when accessed external RAM.
          */
         uint32_t smem_ecc_cs_hold_time:3;
@@ -693,7 +693,7 @@ typedef union {
         uint32_t reserved_17:8;
         /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0;
          *  These bits are used to set the minimum CS high time tSHSL between SPI burst
-         *  transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1)
+         *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1)
          *  MSPI core clock cycles.
          */
         uint32_t smem_cs_hold_delay:6;
@@ -705,7 +705,7 @@ typedef union {
         uint32_t smem_split_trans_en:1;
     };
     uint32_t val;
-} spi_smem_ac_reg_t;
+} spi_mem_c_smem_ac_reg_t;
 
 
 /** Group: State control register */
@@ -722,7 +722,7 @@ typedef union {
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_fsm_reg_t;
+} spi_mem_c_fsm_reg_t;
 
 
 /** Group: Interrupt registers */
@@ -733,37 +733,37 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_ena:1;
         /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_ena:1;
         /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_ena:1;
         /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_ena:1;
         /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_ena:1;
         /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_ena:1;
         /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int__ena:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_ena_reg_t;
+} spi_mem_c_int_ena_reg_t;
 
 /** Type of mem_int_clr register
  *  SPI0 interrupt clear register
@@ -772,37 +772,37 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_clr:1;
         /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_clr:1;
         /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The clear bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_clr:1;
         /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0;
-         *  The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_clr:1;
         /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_clr:1;
         /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_clr:1;
         /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int_clr:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_clr_reg_t;
+} spi_mem_c_int_clr_reg_t;
 
 /** Type of mem_int_raw register
  *  SPI0 interrupt raw register
@@ -811,53 +811,53 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+         *  The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
         uint32_t mem_slv_st_end_int_raw:1;
         /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+         *  The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
         uint32_t mem_mst_st_end_int_raw:1;
         /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0;
-         *  The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set
-         *  and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
-         *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When
-         *  SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is
+         *  The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set
+         *  and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+         *  of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When
+         *  SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is
          *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
-         *  than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and
-         *  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+         *  than spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and
+         *  SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
          *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
-         *  SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN
+         *  spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN
          *  are cleared, this bit will not be triggered.
          */
         uint32_t mem_ecc_err_int_raw:1;
         /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+         *  The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
          *  rejected. 0: Others.
          */
         uint32_t mem_pms_reject_int_raw:1;
         /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+         *  The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
         uint32_t mem_axi_raddr_err_int_raw:1;
         /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+         *  The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
          *  flash request is received. 0: Others.
          */
         uint32_t mem_axi_wr_flash_err_int_raw:1;
         /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+         *  The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
         uint32_t mem_axi_waddr_err_int_raw:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_raw_reg_t;
+} spi_mem_c_int_raw_reg_t;
 
 /** Type of mem_int_st register
  *  SPI0 interrupt status register
@@ -866,37 +866,37 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_st:1;
         /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The status bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_st:1;
         /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0;
-         *  The status bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The status bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_st:1;
         /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0;
-         *  The status bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_st:1;
         /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_st:1;
         /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_st:1;
         /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int_st:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_st_reg_t;
+} spi_mem_c_int_st_reg_t;
 
 
 /** Group: PMS control and configuration registers */
@@ -915,14 +915,14 @@ typedef union {
         uint32_t fmem_pmsn_wr_attr:1;
         /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
          *  SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
-         *  section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and
-         *  SPI_FMEM_PMSn_SIZE_REG.
+         *  section n is configured by registers SPI_MEM_C_FMEM__PMSn_ADDR_REG and
+         *  SPI_MEM_C_FMEM__PMSn_SIZE_REG.
          */
         uint32_t fmem_pmsn_ecc:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} spi_fmem_pmsn_attr_reg_t;
+} spi_mem_c_fmem_pmsn_attr_reg_t;
 
 /** Type of fmem_pmsn_addr register
  *  SPI1 flash PMS section n start address register
@@ -936,7 +936,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_fmem_pmsn_addr_reg_t;
+} spi_mem_c_fmem_pmsn_addr_reg_t;
 
 /** Type of fmem_pmsn_size register
  *  SPI1 flash PMS section n start address register
@@ -944,14 +944,14 @@ typedef union {
 typedef union {
     struct {
         /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
-         *  SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S,
-         *  SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE)
+         *  SPI1 flash PMS section n address region is (SPI_MEM_C_FMEM__PMSn_ADDR_S,
+         *  SPI_MEM_C_FMEM__PMSn_ADDR_S + SPI_MEM_C_FMEM__PMSn_SIZE)
          */
         uint32_t fmem_pmsn_size:15;
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} spi_fmem_pmsn_size_reg_t;
+} spi_mem_c_fmem_pmsn_size_reg_t;
 
 /** Type of smem_pmsn_attr register
  *  SPI1 flash PMS section n start address register
@@ -968,14 +968,14 @@ typedef union {
         uint32_t smem_pmsn_wr_attr:1;
         /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
          *  SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The
-         *  external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and
-         *  SPI_SMEM_PMSn_SIZE_REG.
+         *  external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG and
+         *  SPI_MEM_C_SMEM_PMSn_SIZE_REG.
          */
         uint32_t smem_pmsn_ecc:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} spi_smem_pmsn_attr_reg_t;
+} spi_mem_c_smem_pmsn_attr_reg_t;
 
 /** Type of smem_pmsn_addr register
  *  SPI1 external RAM PMS section n start address register
@@ -989,7 +989,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_smem_pmsn_addr_reg_t;
+} spi_mem_c_smem_pmsn_addr_reg_t;
 
 /** Type of smem_pmsn_size register
  *  SPI1 external RAM PMS section n start address register
@@ -997,14 +997,14 @@ typedef union {
 typedef union {
     struct {
         /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
-         *  SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S,
-         *  SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE)
+         *  SPI1 external RAM PMS section n address region is (SPI_MEM_C_SMEM_PMSn_ADDR_S,
+         *  SPI_MEM_C_SMEM_PMSn_ADDR_S + SPI_MEM_C_SMEM_PMSn_SIZE)
          */
         uint32_t smem_pmsn_size:15;
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} spi_smem_pmsn_size_reg_t;
+} spi_mem_c_smem_pmsn_size_reg_t;
 
 /** Type of mem_pms_reject register
  *  SPI1 access reject register
@@ -1013,7 +1013,7 @@ typedef union {
     struct {
         /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first SPI1 access error address. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_reject_addr:27;
         /** mem_pm_en : R/W; bitpos: [27]; default: 0;
@@ -1022,27 +1022,27 @@ typedef union {
         uint32_t mem_pm_en:1;
         /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
          *  1: SPI1 write access error. 0: No write access error. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_ld:1;
         /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0;
          *  1: SPI1 read access error. 0: No read access error. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_st:1;
         /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
          *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
-         *  cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_multi_hit:1;
         /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
          *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
-         *  error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  error. It is cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_ivd:1;
     };
     uint32_t val;
-} spi_mem_pms_reject_reg_t;
+} spi_mem_c_pms_reject_reg_t;
 
 
 /** Group: MSPI ECC registers */
@@ -1054,11 +1054,11 @@ typedef union {
         uint32_t reserved_0:5;
         /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0;
          *  This bits show the error times of MSPI ECC read. It is cleared by when
-         *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+         *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
          */
         uint32_t mem_ecc_err_cnt:6;
         /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10;
-         *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.
+         *  Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t fmem_ecc_err_int_num:6;
         /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0;
@@ -1082,9 +1082,9 @@ typedef union {
         uint32_t mem_usr_ecc_addr_en:1;
         uint32_t reserved_22:2;
         /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1;
-         *  1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is
-         *  updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and
-         *  SPI_MEM_ECC_ERR_ADDR record the first ECC error information.
+         *  1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is
+         *  updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and
+         *  spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information.
          */
         uint32_t mem_ecc_continue_record_err_en:1;
         /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0;
@@ -1094,7 +1094,7 @@ typedef union {
         uint32_t mem_ecc_err_bits:7;
     };
     uint32_t val;
-} spi_mem_ecc_ctrl_reg_t;
+} spi_mem_c_ecc_ctrl_reg_t;
 
 /** Type of mem_ecc_err_addr register
  *  MSPI ECC error address register
@@ -1103,13 +1103,13 @@ typedef union {
     struct {
         /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0;
          *  This bits show the first MSPI ECC error address. It is cleared by when
-         *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+         *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
          */
         uint32_t mem_ecc_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_ecc_err_addr_reg_t;
+} spi_mem_c_ecc_err_addr_reg_t;
 
 /** Type of smem_ecc_ctrl register
  *  MSPI ECC control register
@@ -1136,7 +1136,7 @@ typedef union {
         uint32_t reserved_21:11;
     };
     uint32_t val;
-} spi_smem_ecc_ctrl_reg_t;
+} spi_mem_c_smem_ecc_ctrl_reg_t;
 
 
 /** Group: Status and state control registers */
@@ -1174,7 +1174,7 @@ typedef union {
         uint32_t all_axi_trans_afifo_empty:1;
     };
     uint32_t val;
-} spi_smem_axi_addr_ctrl_reg_t;
+} spi_mem_c_smem_axi_addr_ctrl_reg_t;
 
 /** Type of mem_axi_err_resp_en register
  *  SPI0 AXI error response enable register
@@ -1233,7 +1233,7 @@ typedef union {
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_axi_err_resp_en_reg_t;
+} spi_mem_c_axi_err_resp_en_reg_t;
 
 
 /** Group: Flash timing registers */
@@ -1266,7 +1266,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} spi_mem_timing_cali_reg_t;
+} spi_mem_c_timing_cali_reg_t;
 
 /** Type of mem_din_mode register
  *  MSPI flash input timing delay mode control register
@@ -1334,7 +1334,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_din_mode_reg_t;
+} spi_mem_c_din_mode_reg_t;
 
 /** Type of mem_din_num register
  *  MSPI flash input timing delay number control register
@@ -1389,7 +1389,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} spi_mem_din_num_reg_t;
+} spi_mem_c_din_num_reg_t;
 
 /** Type of mem_dout_mode register
  *  MSPI flash output timing adjustment control register
@@ -1457,7 +1457,7 @@ typedef union {
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_mem_dout_mode_reg_t;
+} spi_mem_c_dout_mode_reg_t;
 
 
 /** Group: External RAM timing registers */
@@ -1487,7 +1487,7 @@ typedef union {
         uint32_t reserved_6:26;
     };
     uint32_t val;
-} spi_smem_timing_cali_reg_t;
+} spi_mem_c_smem_timing_cali_reg_t;
 
 /** Type of smem_din_mode register
  *  MSPI external RAM input timing delay mode control register
@@ -1560,7 +1560,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_smem_din_mode_reg_t;
+} spi_mem_c_smem_din_mode_reg_t;
 
 /** Type of smem_din_num register
  *  MSPI external RAM input timing delay number control register
@@ -1615,7 +1615,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} spi_smem_din_num_reg_t;
+} spi_mem_c_smem_din_num_reg_t;
 
 /** Type of smem_dout_mode register
  *  MSPI external RAM output timing adjustment control register
@@ -1688,7 +1688,7 @@ typedef union {
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_smem_dout_mode_reg_t;
+} spi_mem_c_smem_dout_mode_reg_t;
 
 
 /** Group: Manual Encryption plaintext Memory */
@@ -1704,7 +1704,7 @@ typedef union {
         uint32_t xts_plain:32;
     };
     uint32_t val;
-} spi_mem_xts_plain_base_reg_t;
+} spi_mem_c_xts_plain_base_reg_t;
 
 
 /** Group: Manual Encryption configuration registers */
@@ -1722,7 +1722,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} spi_mem_xts_linesize_reg_t;
+} spi_mem_c_xts_linesize_reg_t;
 
 /** Type of mem_xts_destination register
  *  Manual Encryption destination register
@@ -1737,7 +1737,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_destination_reg_t;
+} spi_mem_c_xts_destination_reg_t;
 
 /** Type of mem_xts_physical_address register
  *  Manual Encryption physical address register
@@ -1753,7 +1753,7 @@ typedef union {
         uint32_t reserved_26:6;
     };
     uint32_t val;
-} spi_mem_xts_physical_address_reg_t;
+} spi_mem_c_xts_physical_address_reg_t;
 
 
 /** Group: Manual Encryption control and status registers */
@@ -1772,7 +1772,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_trigger_reg_t;
+} spi_mem_c_xts_trigger_reg_t;
 
 /** Type of mem_xts_release register
  *  Manual Encryption physical address register
@@ -1788,7 +1788,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_release_reg_t;
+} spi_mem_c_xts_release_reg_t;
 
 /** Type of mem_xts_destroy register
  *  Manual Encryption physical address register
@@ -1804,7 +1804,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_destroy_reg_t;
+} spi_mem_c_xts_destroy_reg_t;
 
 /** Type of mem_xts_state register
  *  Manual Encryption physical address register
@@ -1820,7 +1820,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} spi_mem_xts_state_reg_t;
+} spi_mem_c_xts_state_reg_t;
 
 
 /** Group: Manual Encryption version control register */
@@ -1836,7 +1836,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_xts_date_reg_t;
+} spi_mem_c_xts_date_reg_t;
 
 
 /** Group: MMU access registers */
@@ -1851,7 +1851,7 @@ typedef union {
         uint32_t mmu_item_content:32;
     };
     uint32_t val;
-} spi_mem_mmu_item_content_reg_t;
+} spi_mem_c_mmu_item_content_reg_t;
 
 /** Type of mem_mmu_item_index register
  *  MSPI-MMU item index register
@@ -1864,7 +1864,7 @@ typedef union {
         uint32_t mmu_item_index:32;
     };
     uint32_t val;
-} spi_mem_mmu_item_index_reg_t;
+} spi_mem_c_mmu_item_index_reg_t;
 
 
 /** Group: MMU power control and configuration registers */
@@ -1898,7 +1898,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_mmu_power_ctrl_reg_t;
+} spi_mem_c_mmu_power_ctrl_reg_t;
 
 
 /** Group: External mem cryption DPA registers */
@@ -1927,7 +1927,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} spi_mem_dpa_ctrl_reg_t;
+} spi_mem_c_dpa_ctrl_reg_t;
 
 
 /** Group: Version control register */
@@ -1943,84 +1943,84 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} spi_mem_date_reg_t;
+} spi_mem_c_date_reg_t;
 
 
-typedef struct {
-    volatile spi_mem_cmd_reg_t mem_cmd;
+typedef struct spi_mem_c_dev_s {
+    volatile spi_mem_c_cmd_reg_t mem_cmd;
     uint32_t reserved_004;
-    volatile spi_mem_ctrl_reg_t mem_ctrl;
-    volatile spi_mem_ctrl1_reg_t mem_ctrl1;
-    volatile spi_mem_ctrl2_reg_t mem_ctrl2;
-    volatile spi_mem_clock_reg_t mem_clock;
-    volatile spi_mem_user_reg_t mem_user;
-    volatile spi_mem_user1_reg_t mem_user1;
-    volatile spi_mem_user2_reg_t mem_user2;
+    volatile spi_mem_c_ctrl_reg_t mem_ctrl;
+    volatile spi_mem_c_ctrl1_reg_t mem_ctrl1;
+    volatile spi_mem_c_ctrl2_reg_t mem_ctrl2;
+    volatile spi_mem_c_clock_reg_t mem_clock;
+    volatile spi_mem_c_user_reg_t mem_user;
+    volatile spi_mem_c_user1_reg_t mem_user1;
+    volatile spi_mem_c_user2_reg_t mem_user2;
     uint32_t reserved_024[4];
-    volatile spi_mem_misc_reg_t mem_misc;
+    volatile spi_mem_c_misc_reg_t mem_misc;
     uint32_t reserved_038;
-    volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl;
+    volatile spi_mem_c_cache_fctrl_reg_t mem_cache_fctrl;
     uint32_t reserved_040;
-    volatile spi_mem_sram_cmd_reg_t mem_sram_cmd;
+    volatile spi_mem_c_sram_cmd_reg_t mem_sram_cmd;
     uint32_t reserved_048[3];
-    volatile spi_mem_fsm_reg_t mem_fsm;
+    volatile spi_mem_c_fsm_reg_t mem_fsm;
     uint32_t reserved_058[26];
-    volatile spi_mem_int_ena_reg_t mem_int_ena;
-    volatile spi_mem_int_clr_reg_t mem_int_clr;
-    volatile spi_mem_int_raw_reg_t mem_int_raw;
-    volatile spi_mem_int_st_reg_t mem_int_st;
+    volatile spi_mem_c_int_ena_reg_t mem_int_ena;
+    volatile spi_mem_c_int_clr_reg_t mem_int_clr;
+    volatile spi_mem_c_int_raw_reg_t mem_int_raw;
+    volatile spi_mem_c_int_st_reg_t mem_int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_ddr_reg_t mem_ddr;
-    volatile spi_smem_ddr_reg_t smem_ddr;
+    volatile spi_mem_c_ddr_reg_t mem_ddr;
+    volatile spi_mem_c_smem_ddr_reg_t smem_ddr;
     uint32_t reserved_0dc[9];
-    volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
-    volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
-    volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
-    volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
-    volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
-    volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4];
+    volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
+    volatile spi_mem_c_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
+    volatile spi_mem_c_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
+    volatile spi_mem_c_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
+    volatile spi_mem_c_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
+    volatile spi_mem_c_smem_pmsn_size_reg_t smem_pmsn_size[4];
     uint32_t reserved_160;
-    volatile spi_mem_pms_reject_reg_t mem_pms_reject;
-    volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl;
-    volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr;
-    volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr;
-    volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
-    volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
-    volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en;
-    volatile spi_mem_timing_cali_reg_t mem_timing_cali;
-    volatile spi_mem_din_mode_reg_t mem_din_mode;
-    volatile spi_mem_din_num_reg_t mem_din_num;
-    volatile spi_mem_dout_mode_reg_t mem_dout_mode;
-    volatile spi_smem_timing_cali_reg_t smem_timing_cali;
-    volatile spi_smem_din_mode_reg_t smem_din_mode;
-    volatile spi_smem_din_num_reg_t smem_din_num;
-    volatile spi_smem_dout_mode_reg_t smem_dout_mode;
-    volatile spi_smem_ac_reg_t smem_ac;
+    volatile spi_mem_c_pms_reject_reg_t mem_pms_reject;
+    volatile spi_mem_c_ecc_ctrl_reg_t mem_ecc_ctrl;
+    volatile spi_mem_c_ecc_err_addr_reg_t mem_ecc_err_addr;
+    volatile spi_mem_c_axi_err_addr_reg_t mem_axi_err_addr;
+    volatile spi_mem_c_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
+    volatile spi_mem_c_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
+    volatile spi_mem_c_axi_err_resp_en_reg_t mem_axi_err_resp_en;
+    volatile spi_mem_c_timing_cali_reg_t mem_timing_cali;
+    volatile spi_mem_c_din_mode_reg_t mem_din_mode;
+    volatile spi_mem_c_din_num_reg_t mem_din_num;
+    volatile spi_mem_c_dout_mode_reg_t mem_dout_mode;
+    volatile spi_mem_c_smem_timing_cali_reg_t smem_timing_cali;
+    volatile spi_mem_c_smem_din_mode_reg_t smem_din_mode;
+    volatile spi_mem_c_smem_din_num_reg_t smem_din_num;
+    volatile spi_mem_c_smem_dout_mode_reg_t smem_dout_mode;
+    volatile spi_mem_c_smem_ac_reg_t smem_ac;
     uint32_t reserved_1a4[23];
-    volatile spi_mem_clock_gate_reg_t mem_clock_gate;
+    volatile spi_mem_c_clock_gate_reg_t mem_clock_gate;
     uint32_t reserved_204[63];
-    volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base;
+    volatile spi_mem_c_xts_plain_base_reg_t mem_xts_plain_base;
     uint32_t reserved_304[15];
-    volatile spi_mem_xts_linesize_reg_t mem_xts_linesize;
-    volatile spi_mem_xts_destination_reg_t mem_xts_destination;
-    volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address;
-    volatile spi_mem_xts_trigger_reg_t mem_xts_trigger;
-    volatile spi_mem_xts_release_reg_t mem_xts_release;
-    volatile spi_mem_xts_destroy_reg_t mem_xts_destroy;
-    volatile spi_mem_xts_state_reg_t mem_xts_state;
-    volatile spi_mem_xts_date_reg_t mem_xts_date;
+    volatile spi_mem_c_xts_linesize_reg_t mem_xts_linesize;
+    volatile spi_mem_c_xts_destination_reg_t mem_xts_destination;
+    volatile spi_mem_c_xts_physical_address_reg_t mem_xts_physical_address;
+    volatile spi_mem_c_xts_trigger_reg_t mem_xts_trigger;
+    volatile spi_mem_c_xts_release_reg_t mem_xts_release;
+    volatile spi_mem_c_xts_destroy_reg_t mem_xts_destroy;
+    volatile spi_mem_c_xts_state_reg_t mem_xts_state;
+    volatile spi_mem_c_xts_date_reg_t mem_xts_date;
     uint32_t reserved_360[7];
-    volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content;
-    volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index;
-    volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
-    volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl;
+    volatile spi_mem_c_mmu_item_content_reg_t mem_mmu_item_content;
+    volatile spi_mem_c_mmu_item_index_reg_t mem_mmu_item_index;
+    volatile spi_mem_c_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
+    volatile spi_mem_c_dpa_ctrl_reg_t mem_dpa_ctrl;
     uint32_t reserved_38c[28];
-    volatile spi_mem_date_reg_t mem_date;
+    volatile spi_mem_c_date_reg_t mem_date;
 } spi_mem_c_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure");
+_Static_assert(sizeof(spi_mem_c_dev_t) == 0x400, "Invalid size of spi_mem_c_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32p4/include/soc/spi_mem_reg.h b/components/soc/esp32p4/include/soc/spi_mem_reg.h
index 3c58d02d89..1a559cf575 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_reg.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_reg.h
@@ -1,16 +1,16 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_SPI_MEM_REG_H_
-#define _SOC_SPI_MEM_REG_H_
+#pragma once
 
+#include <stdint.h>
+#include "soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
 /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
@@ -3442,7 +3442,3 @@ formance of cryption will decrease together with this number increasing).*/
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h b/components/soc/esp32p4/include/soc/spi_mem_s_reg.h
index 2e156ebe1c..9133d8694f 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_s_reg.h
@@ -11,2871 +11,2871 @@
 extern "C" {
 #endif
 
-/** SPI_MEM_CMD_REG register
+/** SPI_MEM_S_CMD_REG register
  *  SPI0 FSM status register
  */
-#define SPI_MEM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x0)
-/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
+#define SPI_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x0)
+/** SPI_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0;
  *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
  *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
  *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
  */
-#define SPI_MEM_MST_ST    0x0000000FU
-#define SPI_MEM_MST_ST_M  (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S)
-#define SPI_MEM_MST_ST_V  0x0000000FU
-#define SPI_MEM_MST_ST_S  0
-/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
+#define SPI_MEM_S_MST_ST    0x0000000FU
+#define SPI_MEM_S_MST_ST_M  (SPI_MEM_S_MST_ST_V << SPI_MEM_S_MST_ST_S)
+#define SPI_MEM_S_MST_ST_V  0x0000000FU
+#define SPI_MEM_S_MST_ST_S  0
+/** SPI_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0;
  *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
  *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
  *  6:write data state, 7: done state, 8: read data end state.
  */
-#define SPI_MEM_SLV_ST    0x0000000FU
-#define SPI_MEM_SLV_ST_M  (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S)
-#define SPI_MEM_SLV_ST_V  0x0000000FU
-#define SPI_MEM_SLV_ST_S  4
-/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0;
- *  SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
+#define SPI_MEM_S_SLV_ST    0x0000000FU
+#define SPI_MEM_S_SLV_ST_M  (SPI_MEM_S_SLV_ST_V << SPI_MEM_S_SLV_ST_S)
+#define SPI_MEM_S_SLV_ST_V  0x0000000FU
+#define SPI_MEM_S_SLV_ST_S  4
+/** SPI_MEM_S_USR : HRO; bitpos: [18]; default: 0;
+ *  SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared.  An operation
  *  will be triggered when the bit is set. The bit will be cleared once the operation
  *  done.1: enable 0: disable.
  */
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (SPI_MEM_USR_V << SPI_MEM_USR_S)
-#define SPI_MEM_USR_V  0x00000001U
-#define SPI_MEM_USR_S  18
+#define SPI_MEM_S_USR    (BIT(18))
+#define SPI_MEM_S_USR_M  (SPI_MEM_S_USR_V << SPI_MEM_S_USR_S)
+#define SPI_MEM_S_USR_V  0x00000001U
+#define SPI_MEM_S_USR_S  18
 
-/** SPI_MEM_CTRL_REG register
+/** SPI_MEM_S_CTRL_REG register
  *  SPI0 control register.
  */
-#define SPI_MEM_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x8)
-/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x8)
+/** SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
  *  of SPI_DQS is output by the MSPI controller.
  */
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S)
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S  0
+/** SPI_MEM_S_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
  *  of SPI_IO[7:0] is output by the MSPI controller.
  */
-#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S)
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_S_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_S  1
+/** SPI_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
  *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
  *  output by the MSPI controller in the first half part of dummy phase. It is used to
  *  mask invalid SPI_DQS in the half part of dummy phase.
  */
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S)
-#define SPI_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI_MEM_FDUMMY_RIN_S  2
-/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+#define SPI_MEM_S_FDUMMY_RIN    (BIT(2))
+#define SPI_MEM_S_FDUMMY_RIN_M  (SPI_MEM_S_FDUMMY_RIN_V << SPI_MEM_S_FDUMMY_RIN_S)
+#define SPI_MEM_S_FDUMMY_RIN_V  0x00000001U
+#define SPI_MEM_S_FDUMMY_RIN_S  2
+/** SPI_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
  *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
  *  output by the MSPI controller in the second half part of dummy phase. It is used to
  *  pre-drive flash.
  */
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S)
-#define SPI_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_FDUMMY_WOUT    (BIT(3))
+#define SPI_MEM_S_FDUMMY_WOUT_M  (SPI_MEM_S_FDUMMY_WOUT_V << SPI_MEM_S_FDUMMY_WOUT_S)
+#define SPI_MEM_S_FDUMMY_WOUT_V  0x00000001U
+#define SPI_MEM_S_FDUMMY_WOUT_S  3
+/** SPI_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
  *  Apply 8 signals during write-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S)
-#define SPI_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI_MEM_FDOUT_OCT_S  4
-/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_S_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_S_FDOUT_OCT_M  (SPI_MEM_S_FDOUT_OCT_V << SPI_MEM_S_FDOUT_OCT_S)
+#define SPI_MEM_S_FDOUT_OCT_V  0x00000001U
+#define SPI_MEM_S_FDOUT_OCT_S  4
+/** SPI_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0;
  *  Apply 8 signals during read-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S)
-#define SPI_MEM_FDIN_OCT_V  0x00000001U
-#define SPI_MEM_FDIN_OCT_S  5
-/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_S_FDIN_OCT    (BIT(5))
+#define SPI_MEM_S_FDIN_OCT_M  (SPI_MEM_S_FDIN_OCT_V << SPI_MEM_S_FDIN_OCT_S)
+#define SPI_MEM_S_FDIN_OCT_V  0x00000001U
+#define SPI_MEM_S_FDIN_OCT_S  5
+/** SPI_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0;
  *  Apply 8 signals during address phase 1:enable 0: disable
  */
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S)
-#define SPI_MEM_FADDR_OCT_V  0x00000001U
-#define SPI_MEM_FADDR_OCT_S  6
-/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_S_FADDR_OCT    (BIT(6))
+#define SPI_MEM_S_FADDR_OCT_M  (SPI_MEM_S_FADDR_OCT_V << SPI_MEM_S_FADDR_OCT_S)
+#define SPI_MEM_S_FADDR_OCT_V  0x00000001U
+#define SPI_MEM_S_FADDR_OCT_S  6
+/** SPI_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
  *  Apply 4 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S)
-#define SPI_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI_MEM_FCMD_QUAD_S  8
-/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0;
+#define SPI_MEM_S_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_S_FCMD_QUAD_M  (SPI_MEM_S_FCMD_QUAD_V << SPI_MEM_S_FCMD_QUAD_S)
+#define SPI_MEM_S_FCMD_QUAD_V  0x00000001U
+#define SPI_MEM_S_FCMD_QUAD_S  8
+/** SPI_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0;
  *  Apply 8 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S)
-#define SPI_MEM_FCMD_OCT_V  0x00000001U
-#define SPI_MEM_FCMD_OCT_S  9
-/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT
- *  and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.
+#define SPI_MEM_S_FCMD_OCT    (BIT(9))
+#define SPI_MEM_S_FCMD_OCT_M  (SPI_MEM_S_FCMD_OCT_V << SPI_MEM_S_FCMD_OCT_S)
+#define SPI_MEM_S_FCMD_OCT_V  0x00000001U
+#define SPI_MEM_S_FCMD_OCT_S  9
+/** SPI_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT
+ *  and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable.
  */
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S)
-#define SPI_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI_MEM_FASTRD_MODE_S  13
-/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+#define SPI_MEM_S_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_S_FASTRD_MODE_M  (SPI_MEM_S_FASTRD_MODE_V << SPI_MEM_S_FASTRD_MODE_S)
+#define SPI_MEM_S_FASTRD_MODE_V  0x00000001U
+#define SPI_MEM_S_FASTRD_MODE_S  13
+/** SPI_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
  *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S)
-#define SPI_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI_MEM_FREAD_DUAL_S  14
-/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
+#define SPI_MEM_S_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_S_FREAD_DUAL_M  (SPI_MEM_S_FREAD_DUAL_V << SPI_MEM_S_FREAD_DUAL_S)
+#define SPI_MEM_S_FREAD_DUAL_V  0x00000001U
+#define SPI_MEM_S_FREAD_DUAL_S  14
+/** SPI_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1;
  *  The bit is used to set MISO line polarity, 1: high 0, low
  */
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S)
-#define SPI_MEM_Q_POL_V  0x00000001U
-#define SPI_MEM_Q_POL_S  18
-/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1;
+#define SPI_MEM_S_Q_POL    (BIT(18))
+#define SPI_MEM_S_Q_POL_M  (SPI_MEM_S_Q_POL_V << SPI_MEM_S_Q_POL_S)
+#define SPI_MEM_S_Q_POL_V  0x00000001U
+#define SPI_MEM_S_Q_POL_S  18
+/** SPI_MEM_S_D_POL : R/W; bitpos: [19]; default: 1;
  *  The bit is used to set MOSI line polarity, 1: high 0, low
  */
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S)
-#define SPI_MEM_D_POL_V  0x00000001U
-#define SPI_MEM_D_POL_S  19
-/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+#define SPI_MEM_S_D_POL    (BIT(19))
+#define SPI_MEM_S_D_POL_M  (SPI_MEM_S_D_POL_V << SPI_MEM_S_D_POL_S)
+#define SPI_MEM_S_D_POL_V  0x00000001U
+#define SPI_MEM_S_D_POL_S  19
+/** SPI_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
  *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S)
-#define SPI_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI_MEM_FREAD_QUAD_S  20
-/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
+#define SPI_MEM_S_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_S_FREAD_QUAD_M  (SPI_MEM_S_FREAD_QUAD_V << SPI_MEM_S_FREAD_QUAD_S)
+#define SPI_MEM_S_FREAD_QUAD_V  0x00000001U
+#define SPI_MEM_S_FREAD_QUAD_S  20
+/** SPI_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1;
  *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
  */
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S)
-#define SPI_MEM_WP_REG_V  0x00000001U
-#define SPI_MEM_WP_REG_S  21
-/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+#define SPI_MEM_S_WP_REG    (BIT(21))
+#define SPI_MEM_S_WP_REG_M  (SPI_MEM_S_WP_REG_V << SPI_MEM_S_WP_REG_S)
+#define SPI_MEM_S_WP_REG_V  0x00000001U
+#define SPI_MEM_S_WP_REG_S  21
+/** SPI_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0;
  *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S)
-#define SPI_MEM_FREAD_DIO_V  0x00000001U
-#define SPI_MEM_FREAD_DIO_S  23
-/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+#define SPI_MEM_S_FREAD_DIO    (BIT(23))
+#define SPI_MEM_S_FREAD_DIO_M  (SPI_MEM_S_FREAD_DIO_V << SPI_MEM_S_FREAD_DIO_S)
+#define SPI_MEM_S_FREAD_DIO_V  0x00000001U
+#define SPI_MEM_S_FREAD_DIO_S  23
+/** SPI_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0;
  *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S)
-#define SPI_MEM_FREAD_QIO_V  0x00000001U
-#define SPI_MEM_FREAD_QIO_S  24
-/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0;
+#define SPI_MEM_S_FREAD_QIO    (BIT(24))
+#define SPI_MEM_S_FREAD_QIO_M  (SPI_MEM_S_FREAD_QIO_V << SPI_MEM_S_FREAD_QIO_S)
+#define SPI_MEM_S_FREAD_QIO_V  0x00000001U
+#define SPI_MEM_S_FREAD_QIO_S  24
+/** SPI_MEM_S_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0;
  *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
  *  1. 0: Others.
  */
-#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S)
-#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON_M  (SPI_MEM_S_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_S_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
  *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
  *  always 1. 0: Others.
  */
-#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S)
-#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON_M  (SPI_MEM_S_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON_S  31
 
-/** SPI_MEM_CTRL1_REG register
+/** SPI_MEM_S_CTRL1_REG register
  *  SPI0 control1 register.
  */
-#define SPI_MEM_CTRL1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc)
-/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc)
+/** SPI_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
  *  SPI clock is alwasy on.
  */
-#define SPI_MEM_CLK_MODE    0x00000003U
-#define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
-#define SPI_MEM_CLK_MODE_V  0x00000003U
-#define SPI_MEM_CLK_MODE_S  0
-/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
+#define SPI_MEM_S_CLK_MODE    0x00000003U
+#define SPI_MEM_S_CLK_MODE_M  (SPI_MEM_S_CLK_MODE_V << SPI_MEM_S_CLK_MODE_S)
+#define SPI_MEM_S_CLK_MODE_V  0x00000003U
+#define SPI_MEM_S_CLK_MODE_S  0
+/** SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
  *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
  *  the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
  */
-#define SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define SPI_AR_SIZE0_1_SUPPORT_EN_M  (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S)
-#define SPI_AR_SIZE0_1_SUPPORT_EN_V  0x00000001U
-#define SPI_AR_SIZE0_1_SUPPORT_EN_S  21
-/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S  21
+/** SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
  *  1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
  */
-#define SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define SPI_AW_SIZE0_1_SUPPORT_EN_M  (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S)
-#define SPI_AW_SIZE0_1_SUPPORT_EN_V  0x00000001U
-#define SPI_AW_SIZE0_1_SUPPORT_EN_S  22
-/** SPI_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1;
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S  22
+/** SPI_MEM_S_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1;
  *  1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
  *  Reply AXI read data to AXI bus when all the read data is available.
  */
-#define SPI_AXI_RDATA_BACK_FAST    (BIT(23))
-#define SPI_AXI_RDATA_BACK_FAST_M  (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S)
-#define SPI_AXI_RDATA_BACK_FAST_V  0x00000001U
-#define SPI_AXI_RDATA_BACK_FAST_S  23
-/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST    (BIT(23))
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST_M  (SPI_MEM_S_AXI_RDATA_BACK_FAST_V << SPI_MEM_S_AXI_RDATA_BACK_FAST_S)
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST_V  0x00000001U
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST_S  23
+/** SPI_MEM_S_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
  *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
  *  when there is a ECC error in AXI read data. The ECC error information is recorded
- *  in SPI_MEM_ECC_ERR_ADDR_REG.
+ *  in SPI_MEM_S_ECC_ERR_ADDR_REG.
  */
-#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_M  (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S)
-#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x00000001U
-#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
-/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0;
+#define SPI_MEM_S_RRESP_ECC_ERR_EN    (BIT(24))
+#define SPI_MEM_S_RRESP_ECC_ERR_EN_M  (SPI_MEM_S_RRESP_ECC_ERR_EN_V << SPI_MEM_S_RRESP_ECC_ERR_EN_S)
+#define SPI_MEM_S_RRESP_ECC_ERR_EN_V  0x00000001U
+#define SPI_MEM_S_RRESP_ECC_ERR_EN_S  24
+/** SPI_MEM_S_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0;
  *  Set this bit to enable AXI Read Splice-transfer.
  */
-#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_M  (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S)
-#define SPI_MEM_AR_SPLICE_EN_V  0x00000001U
-#define SPI_MEM_AR_SPLICE_EN_S  25
-/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0;
+#define SPI_MEM_S_AR_SPLICE_EN    (BIT(25))
+#define SPI_MEM_S_AR_SPLICE_EN_M  (SPI_MEM_S_AR_SPLICE_EN_V << SPI_MEM_S_AR_SPLICE_EN_S)
+#define SPI_MEM_S_AR_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_S_AR_SPLICE_EN_S  25
+/** SPI_MEM_S_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0;
  *  Set this bit to enable AXI Write Splice-transfer.
  */
-#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_M  (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S)
-#define SPI_MEM_AW_SPLICE_EN_V  0x00000001U
-#define SPI_MEM_AW_SPLICE_EN_S  26
-/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1;
- *  When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be
- *  accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1
- *  will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+#define SPI_MEM_S_AW_SPLICE_EN    (BIT(26))
+#define SPI_MEM_S_AW_SPLICE_EN_M  (SPI_MEM_S_AW_SPLICE_EN_V << SPI_MEM_S_AW_SPLICE_EN_S)
+#define SPI_MEM_S_AW_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_S_AW_SPLICE_EN_S  26
+/** SPI_MEM_S_RAM0_EN : HRO; bitpos: [27]; default: 1;
+ *  When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be
+ *  accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1
+ *  will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
  *  accessed at the same time.
  */
-#define SPI_MEM_RAM0_EN    (BIT(27))
-#define SPI_MEM_RAM0_EN_M  (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S)
-#define SPI_MEM_RAM0_EN_V  0x00000001U
-#define SPI_MEM_RAM0_EN_S  27
-/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0;
+#define SPI_MEM_S_RAM0_EN    (BIT(27))
+#define SPI_MEM_S_RAM0_EN_M  (SPI_MEM_S_RAM0_EN_V << SPI_MEM_S_RAM0_EN_S)
+#define SPI_MEM_S_RAM0_EN_V  0x00000001U
+#define SPI_MEM_S_RAM0_EN_S  27
+/** SPI_MEM_S_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0;
  *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
  *  same time.
  */
-#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_M  (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S)
-#define SPI_MEM_DUAL_RAM_EN_V  0x00000001U
-#define SPI_MEM_DUAL_RAM_EN_S  28
-/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1;
+#define SPI_MEM_S_DUAL_RAM_EN    (BIT(28))
+#define SPI_MEM_S_DUAL_RAM_EN_M  (SPI_MEM_S_DUAL_RAM_EN_V << SPI_MEM_S_DUAL_RAM_EN_S)
+#define SPI_MEM_S_DUAL_RAM_EN_V  0x00000001U
+#define SPI_MEM_S_DUAL_RAM_EN_S  28
+/** SPI_MEM_S_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1;
  *  Set this bit to write data faster, do not wait write data has been stored in
  *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
  *  in  tx_bus_fifo_l2.
  */
-#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_M  (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S)
-#define SPI_MEM_FAST_WRITE_EN_V  0x00000001U
-#define SPI_MEM_FAST_WRITE_EN_S  29
-/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0;
+#define SPI_MEM_S_FAST_WRITE_EN    (BIT(29))
+#define SPI_MEM_S_FAST_WRITE_EN_M  (SPI_MEM_S_FAST_WRITE_EN_V << SPI_MEM_S_FAST_WRITE_EN_S)
+#define SPI_MEM_S_FAST_WRITE_EN_V  0x00000001U
+#define SPI_MEM_S_FAST_WRITE_EN_S  29
+/** SPI_MEM_S_RXFIFO_RST : WT; bitpos: [30]; default: 0;
  *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
  *  receive signals from AXI.  Set this bit to reset these FIFO.
  */
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S)
-#define SPI_MEM_RXFIFO_RST_V  0x00000001U
-#define SPI_MEM_RXFIFO_RST_S  30
-/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0;
+#define SPI_MEM_S_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_S_RXFIFO_RST_M  (SPI_MEM_S_RXFIFO_RST_V << SPI_MEM_S_RXFIFO_RST_S)
+#define SPI_MEM_S_RXFIFO_RST_V  0x00000001U
+#define SPI_MEM_S_RXFIFO_RST_S  30
+/** SPI_MEM_S_TXFIFO_RST : WT; bitpos: [31]; default: 0;
  *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
  *  send signals to AXI. Set this bit to reset these FIFO.
  */
-#define SPI_MEM_TXFIFO_RST    (BIT(31))
-#define SPI_MEM_TXFIFO_RST_M  (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S)
-#define SPI_MEM_TXFIFO_RST_V  0x00000001U
-#define SPI_MEM_TXFIFO_RST_S  31
+#define SPI_MEM_S_TXFIFO_RST    (BIT(31))
+#define SPI_MEM_S_TXFIFO_RST_M  (SPI_MEM_S_TXFIFO_RST_V << SPI_MEM_S_TXFIFO_RST_S)
+#define SPI_MEM_S_TXFIFO_RST_V  0x00000001U
+#define SPI_MEM_S_TXFIFO_RST_S  31
 
-/** SPI_MEM_CTRL2_REG register
+/** SPI_MEM_S_CTRL2_REG register
  *  SPI0 control2 register.
  */
-#define SPI_MEM_CTRL2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10)
-/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
+#define SPI_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10)
+/** SPI_MEM_S_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
  *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
- *  SPI_MEM_CS_SETUP bit.
+ *  SPI_MEM_S_CS_SETUP bit.
  */
-#define SPI_MEM_CS_SETUP_TIME    0x0000001FU
-#define SPI_MEM_CS_SETUP_TIME_M  (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S)
-#define SPI_MEM_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_MEM_CS_SETUP_TIME_S  0
-/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1;
+#define SPI_MEM_S_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_S_CS_SETUP_TIME_M  (SPI_MEM_S_CS_SETUP_TIME_V << SPI_MEM_S_CS_SETUP_TIME_S)
+#define SPI_MEM_S_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_S_CS_SETUP_TIME_S  0
+/** SPI_MEM_S_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1;
  *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
- *  SPI_MEM_CS_HOLD bit.
+ *  SPI_MEM_S_CS_HOLD bit.
  */
-#define SPI_MEM_CS_HOLD_TIME    0x0000001FU
-#define SPI_MEM_CS_HOLD_TIME_M  (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S)
-#define SPI_MEM_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3;
- *  SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+#define SPI_MEM_S_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_S_CS_HOLD_TIME_M  (SPI_MEM_S_CS_HOLD_TIME_V << SPI_MEM_S_CS_HOLD_TIME_S)
+#define SPI_MEM_S_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_S_CS_HOLD_TIME_S  5
+/** SPI_MEM_S_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3;
+ *  SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
  *  mode when accessed flash.
  */
-#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007U
-#define SPI_MEM_ECC_CS_HOLD_TIME_M  (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S)
-#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x00000007U
-#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
-/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1;
+#define SPI_MEM_S_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_S_ECC_CS_HOLD_TIME_M  (SPI_MEM_S_ECC_CS_HOLD_TIME_V << SPI_MEM_S_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_S_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_S_ECC_CS_HOLD_TIME_S  10
+/** SPI_MEM_S_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1;
  *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
  *  accesses flash.
  */
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S)
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0;
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S  13
+/** SPI_MEM_S_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0;
  *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
  *  accesses flash.
  */
-#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S)
-#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x00000001U
-#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1;
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN_M  (SPI_MEM_S_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN_S  14
+/** SPI_MEM_S_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1;
  *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
  *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
  *  matter whether there is an ECC region or not.
  */
-#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_M  (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S)
-#define SPI_MEM_SPLIT_TRANS_EN_V  0x00000001U
-#define SPI_MEM_SPLIT_TRANS_EN_S  24
-/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
+#define SPI_MEM_S_SPLIT_TRANS_EN    (BIT(24))
+#define SPI_MEM_S_SPLIT_TRANS_EN_M  (SPI_MEM_S_SPLIT_TRANS_EN_V << SPI_MEM_S_SPLIT_TRANS_EN_S)
+#define SPI_MEM_S_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_S_SPLIT_TRANS_EN_S  24
+/** SPI_MEM_S_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
  *  These bits are used to set the minimum CS high time tSHSL between SPI burst
- *  transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
+ *  transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI
  *  core clock cycles.
  */
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003FU
-#define SPI_MEM_CS_HOLD_DELAY_M  (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S)
-#define SPI_MEM_CS_HOLD_DELAY_V  0x0000003FU
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
+#define SPI_MEM_S_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_S_CS_HOLD_DELAY_M  (SPI_MEM_S_CS_HOLD_DELAY_V << SPI_MEM_S_CS_HOLD_DELAY_S)
+#define SPI_MEM_S_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_S_CS_HOLD_DELAY_S  25
+/** SPI_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0;
  *  The spi0_mst_st and spi0_slv_st will be reset.
  */
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S)
-#define SPI_MEM_SYNC_RESET_V  0x00000001U
-#define SPI_MEM_SYNC_RESET_S  31
+#define SPI_MEM_S_SYNC_RESET    (BIT(31))
+#define SPI_MEM_S_SYNC_RESET_M  (SPI_MEM_S_SYNC_RESET_V << SPI_MEM_S_SYNC_RESET_S)
+#define SPI_MEM_S_SYNC_RESET_V  0x00000001U
+#define SPI_MEM_S_SYNC_RESET_S  31
 
-/** SPI_MEM_CLOCK_REG register
+/** SPI_MEM_S_CLOCK_REG register
  *  SPI clock division control register.
  */
-#define SPI_MEM_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14)
-/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
- *  In the master mode it must be equal to spi_mem_clkcnt_N.
+#define SPI_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14)
+/** SPI_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to SPI_MEM_S_clkcnt_N.
  */
-#define SPI_MEM_CLKCNT_L    0x000000FFU
-#define SPI_MEM_CLKCNT_L_M  (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
-#define SPI_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI_MEM_CLKCNT_L_S  0
-/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
- *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+#define SPI_MEM_S_CLKCNT_L    0x000000FFU
+#define SPI_MEM_S_CLKCNT_L_M  (SPI_MEM_S_CLKCNT_L_V << SPI_MEM_S_CLKCNT_L_S)
+#define SPI_MEM_S_CLKCNT_L_V  0x000000FFU
+#define SPI_MEM_S_CLKCNT_L_S  0
+/** SPI_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((SPI_MEM_S_clkcnt_N+1)/2-1).
  */
-#define SPI_MEM_CLKCNT_H    0x000000FFU
-#define SPI_MEM_CLKCNT_H_M  (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
-#define SPI_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI_MEM_CLKCNT_H_S  8
-/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
- *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- *  system/(spi_mem_clkcnt_N+1)
+#define SPI_MEM_S_CLKCNT_H    0x000000FFU
+#define SPI_MEM_S_CLKCNT_H_M  (SPI_MEM_S_CLKCNT_H_V << SPI_MEM_S_CLKCNT_H_S)
+#define SPI_MEM_S_CLKCNT_H_V  0x000000FFU
+#define SPI_MEM_S_CLKCNT_H_S  8
+/** SPI_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of SPI_MEM_S_clk. So SPI_MEM_S_clk frequency is
+ *  system/(SPI_MEM_S_clkcnt_N+1)
  */
-#define SPI_MEM_CLKCNT_N    0x000000FFU
-#define SPI_MEM_CLKCNT_N_M  (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
-#define SPI_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI_MEM_CLKCNT_N_S  16
-/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+#define SPI_MEM_S_CLKCNT_N    0x000000FFU
+#define SPI_MEM_S_CLKCNT_N_M  (SPI_MEM_S_CLKCNT_N_V << SPI_MEM_S_CLKCNT_N_S)
+#define SPI_MEM_S_CLKCNT_N_V  0x000000FFU
+#define SPI_MEM_S_CLKCNT_N_S  16
+/** SPI_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
  *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
  *  clock.
  */
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S)
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+#define SPI_MEM_S_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_S_CLK_EQU_SYSCLK_M  (SPI_MEM_S_CLK_EQU_SYSCLK_V << SPI_MEM_S_CLK_EQU_SYSCLK_S)
+#define SPI_MEM_S_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_MEM_S_CLK_EQU_SYSCLK_S  31
 
-/** SPI_MEM_USER_REG register
+/** SPI_MEM_S_USER_REG register
  *  SPI0 user register.
  */
-#define SPI_MEM_USER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18)
-/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_S_USER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18)
+/** SPI_MEM_S_CS_HOLD : R/W; bitpos: [6]; default: 0;
  *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
  */
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S)
-#define SPI_MEM_CS_HOLD_V  0x00000001U
-#define SPI_MEM_CS_HOLD_S  6
-/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_S_CS_HOLD    (BIT(6))
+#define SPI_MEM_S_CS_HOLD_M  (SPI_MEM_S_CS_HOLD_V << SPI_MEM_S_CS_HOLD_S)
+#define SPI_MEM_S_CS_HOLD_V  0x00000001U
+#define SPI_MEM_S_CS_HOLD_S  6
+/** SPI_MEM_S_CS_SETUP : R/W; bitpos: [7]; default: 0;
  *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
  */
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S)
-#define SPI_MEM_CS_SETUP_V  0x00000001U
-#define SPI_MEM_CS_SETUP_S  7
-/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+#define SPI_MEM_S_CS_SETUP    (BIT(7))
+#define SPI_MEM_S_CS_SETUP_M  (SPI_MEM_S_CS_SETUP_V << SPI_MEM_S_CS_SETUP_S)
+#define SPI_MEM_S_CS_SETUP_V  0x00000001U
+#define SPI_MEM_S_CS_SETUP_S  7
+/** SPI_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
  */
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S)
-#define SPI_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+#define SPI_MEM_S_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_S_CK_OUT_EDGE_M  (SPI_MEM_S_CK_OUT_EDGE_V << SPI_MEM_S_CK_OUT_EDGE_S)
+#define SPI_MEM_S_CK_OUT_EDGE_V  0x00000001U
+#define SPI_MEM_S_CK_OUT_EDGE_S  9
+/** SPI_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
  *  spi clock is disable in dummy phase when the bit is enable.
  */
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S)
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+#define SPI_MEM_S_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_S_USR_DUMMY_IDLE_M  (SPI_MEM_S_USR_DUMMY_IDLE_V << SPI_MEM_S_USR_DUMMY_IDLE_S)
+#define SPI_MEM_S_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_MEM_S_USR_DUMMY_IDLE_S  26
+/** SPI_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0;
  *  This bit enable the dummy phase of an operation.
  */
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S)
-#define SPI_MEM_USR_DUMMY_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_S  29
+#define SPI_MEM_S_USR_DUMMY    (BIT(29))
+#define SPI_MEM_S_USR_DUMMY_M  (SPI_MEM_S_USR_DUMMY_V << SPI_MEM_S_USR_DUMMY_S)
+#define SPI_MEM_S_USR_DUMMY_V  0x00000001U
+#define SPI_MEM_S_USR_DUMMY_S  29
 
-/** SPI_MEM_USER1_REG register
+/** SPI_MEM_S_USER1_REG register
  *  SPI0 user1 register.
  */
-#define SPI_MEM_USER1_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1c)
-/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
- *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+#define SPI_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1c)
+/** SPI_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in SPI_MEM_S_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1).
  */
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1;
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN_M  (SPI_MEM_S_USR_DUMMY_CYCLELEN_V << SPI_MEM_S_USR_DUMMY_CYCLELEN_S)
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MEM_S_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1;
  *  SPI0 USR_CMD read or write data byte length -1
  */
-#define SPI_MEM_USR_DBYTELEN    0x00000007U
-#define SPI_MEM_USR_DBYTELEN_M  (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S)
-#define SPI_MEM_USR_DBYTELEN_V  0x00000007U
-#define SPI_MEM_USR_DBYTELEN_S  6
-/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+#define SPI_MEM_S_USR_DBYTELEN    0x00000007U
+#define SPI_MEM_S_USR_DBYTELEN_M  (SPI_MEM_S_USR_DBYTELEN_V << SPI_MEM_S_USR_DBYTELEN_S)
+#define SPI_MEM_S_USR_DBYTELEN_V  0x00000007U
+#define SPI_MEM_S_USR_DBYTELEN_S  6
+/** SPI_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
  *  The length in bits of address phase. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_M  (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S)
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
+#define SPI_MEM_S_USR_ADDR_BITLEN    0x0000003FU
+#define SPI_MEM_S_USR_ADDR_BITLEN_M  (SPI_MEM_S_USR_ADDR_BITLEN_V << SPI_MEM_S_USR_ADDR_BITLEN_S)
+#define SPI_MEM_S_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI_MEM_S_USR_ADDR_BITLEN_S  26
 
-/** SPI_MEM_USER2_REG register
+/** SPI_MEM_S_USER2_REG register
  *  SPI0 user2 register.
  */
-#define SPI_MEM_USER2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x20)
-/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+#define SPI_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x20)
+/** SPI_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command.
  */
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_M  (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S)
-#define SPI_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+#define SPI_MEM_S_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_MEM_S_USR_COMMAND_VALUE_M  (SPI_MEM_S_USR_COMMAND_VALUE_V << SPI_MEM_S_USR_COMMAND_VALUE_S)
+#define SPI_MEM_S_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_MEM_S_USR_COMMAND_VALUE_S  0
+/** SPI_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
  *  The length in bits of command phase. The register value shall be (bit_num-1)
  */
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_M  (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S)
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+#define SPI_MEM_S_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_MEM_S_USR_COMMAND_BITLEN_M  (SPI_MEM_S_USR_COMMAND_BITLEN_V << SPI_MEM_S_USR_COMMAND_BITLEN_S)
+#define SPI_MEM_S_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_MEM_S_USR_COMMAND_BITLEN_S  28
 
-/** SPI_MEM_MISC_REG register
+/** SPI_MEM_S_MISC_REG register
  *  SPI0 misc register
  */
-#define SPI_MEM_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34)
-/** SPI_MEM_FSUB_PIN : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34)
+/** SPI_MEM_S_FSUB_PIN : R/W; bitpos: [7]; default: 0;
  *  For SPI0,  flash is connected to SUBPINs.
  */
-#define SPI_MEM_FSUB_PIN    (BIT(7))
-#define SPI_MEM_FSUB_PIN_M  (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S)
-#define SPI_MEM_FSUB_PIN_V  0x00000001U
-#define SPI_MEM_FSUB_PIN_S  7
-/** SPI_MEM_SSUB_PIN : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_S_FSUB_PIN    (BIT(7))
+#define SPI_MEM_S_FSUB_PIN_M  (SPI_MEM_S_FSUB_PIN_V << SPI_MEM_S_FSUB_PIN_S)
+#define SPI_MEM_S_FSUB_PIN_V  0x00000001U
+#define SPI_MEM_S_FSUB_PIN_S  7
+/** SPI_MEM_S_SSUB_PIN : R/W; bitpos: [8]; default: 0;
  *  For SPI0,  sram is connected to SUBPINs.
  */
-#define SPI_MEM_SSUB_PIN    (BIT(8))
-#define SPI_MEM_SSUB_PIN_M  (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S)
-#define SPI_MEM_SSUB_PIN_V  0x00000001U
-#define SPI_MEM_SSUB_PIN_S  8
-/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+#define SPI_MEM_S_SSUB_PIN    (BIT(8))
+#define SPI_MEM_S_SSUB_PIN_M  (SPI_MEM_S_SSUB_PIN_V << SPI_MEM_S_SSUB_PIN_S)
+#define SPI_MEM_S_SSUB_PIN_V  0x00000001U
+#define SPI_MEM_S_SSUB_PIN_S  8
+/** SPI_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
  *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
  */
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S)
-#define SPI_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+#define SPI_MEM_S_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_S_CK_IDLE_EDGE_M  (SPI_MEM_S_CK_IDLE_EDGE_V << SPI_MEM_S_CK_IDLE_EDGE_S)
+#define SPI_MEM_S_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_MEM_S_CK_IDLE_EDGE_S  9
+/** SPI_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
  *  SPI_CS line keep low when the bit is set.
  */
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S)
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+#define SPI_MEM_S_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_S_CS_KEEP_ACTIVE_M  (SPI_MEM_S_CS_KEEP_ACTIVE_V << SPI_MEM_S_CS_KEEP_ACTIVE_S)
+#define SPI_MEM_S_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_MEM_S_CS_KEEP_ACTIVE_S  10
 
-/** SPI_MEM_CACHE_FCTRL_REG register
+/** SPI_MEM_S_CACHE_FCTRL_REG register
  *  SPI0 bit mode control register.
  */
-#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c)
-/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1;
+#define SPI_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c)
+/** SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1;
  *  Set this bit to check AXI read/write the same address region.
  */
-#define SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_M  (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S)
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x00000001U
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
-/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1;
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_M  (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S)
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_V  0x00000001U
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_S  30
+/** SPI_MEM_S_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1;
  *  Set this bit to close AXI read/write transfer to MSPI, which means that only
  *  SLV_ERR will be replied to BRESP/RRESP.
  */
-#define SPI_CLOSE_AXI_INF_EN    (BIT(31))
-#define SPI_CLOSE_AXI_INF_EN_M  (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S)
-#define SPI_CLOSE_AXI_INF_EN_V  0x00000001U
-#define SPI_CLOSE_AXI_INF_EN_S  31
+#define SPI_MEM_S_CLOSE_AXI_INF_EN    (BIT(31))
+#define SPI_MEM_S_CLOSE_AXI_INF_EN_M  (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S)
+#define SPI_MEM_S_CLOSE_AXI_INF_EN_V  0x00000001U
+#define SPI_MEM_S_CLOSE_AXI_INF_EN_S  31
 
-/** SPI_MEM_SRAM_CMD_REG register
+/** SPI_MEM_S_SRAM_CMD_REG register
  *  SPI0 external RAM mode control register
  */
-#define SPI_MEM_SRAM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x44)
-/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0;
+#define SPI_MEM_S_SRAM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x44)
+/** SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
  *  the level of SPI_DQS is output by the MSPI controller.
  */
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S)
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0;
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/** SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0;
  *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
  *  the level of SPI_IO[7:0] is output by the MSPI controller.
  */
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M  (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S)
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0;
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/** SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0;
  *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are
  *  always 1. 0: Others.
  */
-#define SPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_M  (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S)
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_S  30
-/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_M  (SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
  *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0]
  *  are always 1. 0: Others.
  */
-#define SPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_M  (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S)
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_S  31
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_M  (SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S  31
 
-/** SPI_MEM_FSM_REG register
+/** SPI_MEM_S_FSM_REG register
  *  SPI0 FSM status register
  */
-#define SPI_MEM_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54)
-/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
+#define SPI_MEM_S_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54)
+/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
  *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
  */
-#define SPI_MEM_LOCK_DELAY_TIME    0x0000001FU
-#define SPI_MEM_LOCK_DELAY_TIME_M  (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S)
-#define SPI_MEM_LOCK_DELAY_TIME_V  0x0000001FU
-#define SPI_MEM_LOCK_DELAY_TIME_S  7
+#define SPI_MEM_S_LOCK_DELAY_TIME    0x0000001FU
+#define SPI_MEM_S_LOCK_DELAY_TIME_M  (SPI_MEM_S_LOCK_DELAY_TIME_V << SPI_MEM_S_LOCK_DELAY_TIME_S)
+#define SPI_MEM_S_LOCK_DELAY_TIME_V  0x0000001FU
+#define SPI_MEM_S_LOCK_DELAY_TIME_S  7
 
-/** SPI_MEM_INT_ENA_REG register
+/** SPI_MEM_S_INT_ENA_REG register
  *  SPI0 interrupt enable register
  */
-#define SPI_MEM_INT_ENA_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc0)
-/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc0)
+/** SPI_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI_MEM_S_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_ENA_M  (SPI_MEM_S_SLV_ST_END_INT_ENA_V << SPI_MEM_S_SLV_ST_END_INT_ENA_S)
+#define SPI_MEM_S_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_ENA_S  3
+/** SPI_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S)
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_S_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_ENA_M  (SPI_MEM_S_MST_ST_END_INT_ENA_V << SPI_MEM_S_MST_ST_END_INT_ENA_S)
+#define SPI_MEM_S_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_ENA_S  4
+/** SPI_MEM_S_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt.
  */
-#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_M  (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S)
-#define SPI_MEM_ECC_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_ENA_S  5
-/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
+#define SPI_MEM_S_ECC_ERR_INT_ENA    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_ENA_M  (SPI_MEM_S_ECC_ERR_INT_ENA_V << SPI_MEM_S_ECC_ERR_INT_ENA_S)
+#define SPI_MEM_S_ECC_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_ENA_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
  */
-#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_M  (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S)
-#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+#define SPI_MEM_S_PMS_REJECT_INT_ENA    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_ENA_M  (SPI_MEM_S_PMS_REJECT_INT_ENA_V << SPI_MEM_S_PMS_REJECT_INT_ENA_S)
+#define SPI_MEM_S_PMS_REJECT_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_ENA_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M  (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S  9
-/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_M  (SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
  */
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA    (BIT(28))
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M  (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S)
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V  0x00000001U
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S  28
-/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
  */
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA    (BIT(29))
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M  (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S)
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V  0x00000001U
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S  29
-/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
  */
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA    (BIT(30))
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M  (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S)
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V  0x00000001U
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S  30
-/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
  */
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA    (BIT(31))
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M  (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S)
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V  0x00000001U
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S  31
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S  31
 
-/** SPI_MEM_INT_CLR_REG register
+/** SPI_MEM_S_INT_CLR_REG register
  *  SPI0 interrupt clear register
  */
-#define SPI_MEM_INT_CLR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc4)
-/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc4)
+/** SPI_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI_MEM_S_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_CLR_M  (SPI_MEM_S_SLV_ST_END_INT_CLR_V << SPI_MEM_S_SLV_ST_END_INT_CLR_S)
+#define SPI_MEM_S_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_CLR_S  3
+/** SPI_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S)
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The clear bit for SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_S_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_CLR_M  (SPI_MEM_S_MST_ST_END_INT_CLR_V << SPI_MEM_S_MST_ST_END_INT_CLR_S)
+#define SPI_MEM_S_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_CLR_S  4
+/** SPI_MEM_S_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt.
  */
-#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_M  (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S)
-#define SPI_MEM_ECC_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_CLR_S  5
-/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.
+#define SPI_MEM_S_ECC_ERR_INT_CLR    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_CLR_M  (SPI_MEM_S_ECC_ERR_INT_CLR_V << SPI_MEM_S_ECC_ERR_INT_CLR_S)
+#define SPI_MEM_S_ECC_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_CLR_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
  */
-#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_M  (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S)
-#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+#define SPI_MEM_S_PMS_REJECT_INT_CLR    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_CLR_M  (SPI_MEM_S_PMS_REJECT_INT_CLR_V << SPI_MEM_S_PMS_REJECT_INT_CLR_S)
+#define SPI_MEM_S_PMS_REJECT_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_CLR_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
- *  The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0;
- *  The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
-/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0;
- *  The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_M  (SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
  */
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR    (BIT(28))
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M  (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S)
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V  0x00000001U
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S  28
-/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0;
- *  The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
  */
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR    (BIT(29))
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M  (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S)
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V  0x00000001U
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S  29
-/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0;
- *  The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
  */
-#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR    (BIT(30))
-#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M  (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S)
-#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V  0x00000001U
-#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S  30
-/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0;
- *  The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
  */
-#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR    (BIT(31))
-#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M  (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S)
-#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V  0x00000001U
-#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S  31
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S  31
 
-/** SPI_MEM_INT_RAW_REG register
+/** SPI_MEM_S_INT_RAW_REG register
  *  SPI0 interrupt raw register
  */
-#define SPI_MEM_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8)
-/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+#define SPI_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8)
+/** SPI_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
  *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
  *  Others
  */
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+#define SPI_MEM_S_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_RAW_M  (SPI_MEM_S_SLV_ST_END_INT_RAW_V << SPI_MEM_S_SLV_ST_END_INT_RAW_S)
+#define SPI_MEM_S_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_RAW_S  3
+/** SPI_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
  *  changed from non idle state to idle state. 0: Others.
  */
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S)
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set
- *  and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
- *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When
- *  SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is
+#define SPI_MEM_S_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_RAW_M  (SPI_MEM_S_MST_ST_END_INT_RAW_V << SPI_MEM_S_MST_ST_END_INT_RAW_S)
+#define SPI_MEM_S_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_RAW_S  4
+/** SPI_MEM_S_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set
+ *  and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+ *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When
+ *  SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is
  *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
- *  than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and
- *  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+ *  than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and
+ *  SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
  *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
- *  SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN
+ *  SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN
  *  are cleared, this bit will not be triggered.
  */
-#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_M  (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S)
-#define SPI_MEM_ECC_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_RAW_S  5
-/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+#define SPI_MEM_S_ECC_ERR_INT_RAW    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_RAW_M  (SPI_MEM_S_ECC_ERR_INT_RAW_V << SPI_MEM_S_ECC_ERR_INT_RAW_S)
+#define SPI_MEM_S_ECC_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_RAW_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
  *  rejected. 0: Others.
  */
-#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_M  (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S)
-#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+#define SPI_MEM_S_PMS_REJECT_INT_RAW    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_RAW_M  (SPI_MEM_S_PMS_REJECT_INT_RAW_V << SPI_MEM_S_PMS_REJECT_INT_RAW_S)
+#define SPI_MEM_S_PMS_REJECT_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_RAW_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
  *  address is invalid by compared to MMU configuration. 0: Others.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
  *  flash request is received. 0: Others.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
  *  address is invalid by compared to MMU configuration. 0: Others.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
-/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_M  (SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
  *  connected to SPI_DQS1 is overflow.
  */
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW    (BIT(28))
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M  (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S)
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V  0x00000001U
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S  28
-/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
  *  connected to SPI_DQS is overflow.
  */
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW    (BIT(29))
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M  (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S)
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V  0x00000001U
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S  29
-/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
  *  underflow.
  */
-#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW    (BIT(30))
-#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M  (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S)
-#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V  0x00000001U
-#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S  30
-/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
  *  underflow.
  */
-#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW    (BIT(31))
-#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M  (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S)
-#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V  0x00000001U
-#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S  31
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S  31
 
-/** SPI_MEM_INT_ST_REG register
+/** SPI_MEM_S_INT_ST_REG register
  *  SPI0 interrupt status register
  */
-#define SPI_MEM_INT_ST_REG (DR_REG_PSRAM_MSPI0_BASE + 0xcc)
-/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+#define SPI_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI0_BASE + 0xcc)
+/** SPI_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
  */
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S)
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+#define SPI_MEM_S_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_ST_M  (SPI_MEM_S_SLV_ST_END_INT_ST_V << SPI_MEM_S_SLV_ST_END_INT_ST_S)
+#define SPI_MEM_S_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_ST_S  3
+/** SPI_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI_MEM_S_MST_ST_END_INT interrupt.
  */
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S)
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The status bit for SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_S_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_ST_M  (SPI_MEM_S_MST_ST_END_INT_ST_V << SPI_MEM_S_MST_ST_END_INT_ST_S)
+#define SPI_MEM_S_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_ST_S  4
+/** SPI_MEM_S_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The status bit for SPI_MEM_S_ECC_ERR_INT interrupt.
  */
-#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_M  (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S)
-#define SPI_MEM_ECC_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_ST_S  5
-/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0;
- *  The status bit for SPI_MEM_PMS_REJECT_INT interrupt.
+#define SPI_MEM_S_ECC_ERR_INT_ST    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_ST_M  (SPI_MEM_S_ECC_ERR_INT_ST_V << SPI_MEM_S_ECC_ERR_INT_ST_S)
+#define SPI_MEM_S_ECC_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_ST_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
  */
-#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_M  (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S)
-#define SPI_MEM_PMS_REJECT_INT_ST_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_ST_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+#define SPI_MEM_S_PMS_REJECT_INT_ST    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_ST_M  (SPI_MEM_S_PMS_REJECT_INT_ST_V << SPI_MEM_S_PMS_REJECT_INT_ST_S)
+#define SPI_MEM_S_PMS_REJECT_INT_ST_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_ST_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
  */
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
-/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0;
- *  The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_M  (SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0;
+ *  The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
  */
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST    (BIT(28))
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M  (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S)
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V  0x00000001U
-#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S  28
-/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0;
- *  The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0;
+ *  The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
  */
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST    (BIT(29))
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M  (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S)
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V  0x00000001U
-#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S  29
-/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0;
- *  The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0;
+ *  The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
  */
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ST    (BIT(30))
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M  (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S)
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V  0x00000001U
-#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S  30
-/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0;
- *  The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0;
+ *  The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
  */
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ST    (BIT(31))
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M  (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S)
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V  0x00000001U
-#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S  31
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S  31
 
-/** SPI_MEM_DDR_REG register
+/** SPI_MEM_S_DDR_REG register
  *  SPI0 flash DDR mode control register
  */
-#define SPI_MEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd4)
-/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd4)
+/** SPI_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
  *  1: in DDR mode,  0 in SDR mode
  */
-#define SPI_FMEM_DDR_EN    (BIT(0))
-#define SPI_FMEM_DDR_EN_M  (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S)
-#define SPI_FMEM_DDR_EN_V  0x00000001U
-#define SPI_FMEM_DDR_EN_S  0
-/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_FMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_S_FMEM_DDR_EN_M  (SPI_MEM_S_FMEM_DDR_EN_V << SPI_MEM_S_FMEM_DDR_EN_S)
+#define SPI_MEM_S_FMEM_DDR_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_EN_S  0
+/** SPI_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi DDR mode.
  */
-#define SPI_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_FMEM_VAR_DUMMY_M  (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S)
-#define SPI_FMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_FMEM_VAR_DUMMY_S  1
-/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_S_FMEM_VAR_DUMMY_M  (SPI_MEM_S_FMEM_VAR_DUMMY_V << SPI_MEM_S_FMEM_VAR_DUMMY_S)
+#define SPI_MEM_S_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_S_FMEM_VAR_DUMMY_S  1
+/** SPI_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi DDR mode.
  */
-#define SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_FMEM_DDR_RDAT_SWP_M  (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S)
-#define SPI_FMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_FMEM_DDR_RDAT_SWP_S  2
-/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_M  (SPI_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI_MEM_S_FMEM_DDR_RDAT_SWP_S)
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_S  2
+/** SPI_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi DDR mode.
  */
-#define SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_FMEM_DDR_WDAT_SWP_M  (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S)
-#define SPI_FMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_FMEM_DDR_WDAT_SWP_S  3
-/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_M  (SPI_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI_MEM_S_FMEM_DDR_WDAT_SWP_S)
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_S  3
+/** SPI_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when DDR mode.
  */
-#define SPI_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_FMEM_DDR_CMD_DIS_M  (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S)
-#define SPI_FMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_FMEM_DDR_CMD_DIS_S  4
-/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS_M  (SPI_MEM_S_FMEM_DDR_CMD_DIS_V << SPI_MEM_S_FMEM_DDR_CMD_DIS_S)
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS_S  4
+/** SPI_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the panda device.
  */
-#define SPI_FMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_FMEM_OUTMINBYTELEN_M  (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S)
-#define SPI_FMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_FMEM_OUTMINBYTELEN_S  5
-/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1;
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN_M  (SPI_MEM_S_FMEM_OUTMINBYTELEN_V << SPI_MEM_S_FMEM_OUTMINBYTELEN_S)
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN_S  5
+/** SPI_MEM_S_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
  *  accesses to flash.
  */
-#define SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_FMEM_TX_DDR_MSK_EN_M  (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S)
-#define SPI_FMEM_TX_DDR_MSK_EN_V  0x00000001U
-#define SPI_FMEM_TX_DDR_MSK_EN_S  12
-/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1;
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_M  (SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S)
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S  12
+/** SPI_MEM_S_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
  *  accesses to flash.
  */
-#define SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_FMEM_RX_DDR_MSK_EN_M  (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S)
-#define SPI_FMEM_RX_DDR_MSK_EN_V  0x00000001U
-#define SPI_FMEM_RX_DDR_MSK_EN_S  13
-/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_M  (SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S)
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S  13
+/** SPI_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_FMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_FMEM_USR_DDR_DQS_THD_M  (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S)
-#define SPI_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_FMEM_USR_DDR_DQS_THD_S  14
-/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_M  (SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S)
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_FMEM_DDR_DQS_LOOP_M  (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S)
-#define SPI_FMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_FMEM_DDR_DQS_LOOP_S  21
-/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_M  (SPI_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI_MEM_S_FMEM_DDR_DQS_LOOP_S)
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_S  21
+/** SPI_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_FMEM_CLK_DIFF_EN_M  (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S)
-#define SPI_FMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_FMEM_CLK_DIFF_EN_S  24
-/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN_M  (SPI_MEM_S_FMEM_CLK_DIFF_EN_V << SPI_MEM_S_FMEM_CLK_DIFF_EN_S)
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN_S  24
+/** SPI_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_FMEM_DQS_CA_IN_M  (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S)
-#define SPI_FMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_FMEM_DQS_CA_IN_S  26
-/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
+#define SPI_MEM_S_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_S_FMEM_DQS_CA_IN_M  (SPI_MEM_S_FMEM_DQS_CA_IN_V << SPI_MEM_S_FMEM_DQS_CA_IN_S)
+#define SPI_MEM_S_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_S_FMEM_DQS_CA_IN_S  26
+/** SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to flash. .
  */
-#define SPI_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_FMEM_CLK_DIFF_INV_M  (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S)
-#define SPI_FMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_FMEM_CLK_DIFF_INV_S  28
-/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV_M  (SPI_MEM_S_FMEM_CLK_DIFF_INV_V << SPI_MEM_S_FMEM_CLK_DIFF_INV_S)
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV_S  28
+/** SPI_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
  */
-#define SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_FMEM_OCTA_RAM_ADDR_M  (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S)
-#define SPI_FMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_FMEM_OCTA_RAM_ADDR_S  29
-/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_M  (SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S)
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_FMEM_HYPERBUS_CA_M  (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S)
-#define SPI_FMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_FMEM_HYPERBUS_CA_S  30
+#define SPI_MEM_S_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_S_FMEM_HYPERBUS_CA_M  (SPI_MEM_S_FMEM_HYPERBUS_CA_V << SPI_MEM_S_FMEM_HYPERBUS_CA_S)
+#define SPI_MEM_S_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_S_FMEM_HYPERBUS_CA_S  30
 
-/** SPI_SMEM_DDR_REG register
+/** SPI_MEM_S_SMEM_DDR_REG register
  *  SPI0 external RAM DDR mode control register
  */
-#define SPI_SMEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd8)
-/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_SMEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd8)
+/** SPI_MEM_S_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
  *  1: in DDR mode,  0 in SDR mode
  */
-#define SPI_SMEM_DDR_EN    (BIT(0))
-#define SPI_SMEM_DDR_EN_M  (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S)
-#define SPI_SMEM_DDR_EN_V  0x00000001U
-#define SPI_SMEM_DDR_EN_S  0
-/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_S_SMEM_DDR_EN_M  (SPI_MEM_S_SMEM_DDR_EN_V << SPI_MEM_S_SMEM_DDR_EN_S)
+#define SPI_MEM_S_SMEM_DDR_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_EN_S  0
+/** SPI_MEM_S_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi DDR mode.
  */
-#define SPI_SMEM_VAR_DUMMY    (BIT(1))
-#define SPI_SMEM_VAR_DUMMY_M  (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S)
-#define SPI_SMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_SMEM_VAR_DUMMY_S  1
-/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_S_SMEM_VAR_DUMMY_M  (SPI_MEM_S_SMEM_VAR_DUMMY_V << SPI_MEM_S_SMEM_VAR_DUMMY_S)
+#define SPI_MEM_S_SMEM_VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_S_SMEM_VAR_DUMMY_S  1
+/** SPI_MEM_S_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi DDR mode.
  */
-#define SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_SMEM_DDR_RDAT_SWP_M  (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S)
-#define SPI_SMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_SMEM_DDR_RDAT_SWP_S  2
-/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_M  (SPI_MEM_S_SMEM_DDR_RDAT_SWP_V << SPI_MEM_S_SMEM_DDR_RDAT_SWP_S)
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_S  2
+/** SPI_MEM_S_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi DDR mode.
  */
-#define SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_SMEM_DDR_WDAT_SWP_M  (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S)
-#define SPI_SMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_SMEM_DDR_WDAT_SWP_S  3
-/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_M  (SPI_MEM_S_SMEM_DDR_WDAT_SWP_V << SPI_MEM_S_SMEM_DDR_WDAT_SWP_S)
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_S  3
+/** SPI_MEM_S_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when DDR mode.
  */
-#define SPI_SMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_SMEM_DDR_CMD_DIS_M  (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S)
-#define SPI_SMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_SMEM_DDR_CMD_DIS_S  4
-/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS_M  (SPI_MEM_S_SMEM_DDR_CMD_DIS_V << SPI_MEM_S_SMEM_DDR_CMD_DIS_S)
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS_S  4
+/** SPI_MEM_S_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the DDR psram.
  */
-#define SPI_SMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_SMEM_OUTMINBYTELEN_M  (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S)
-#define SPI_SMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_SMEM_OUTMINBYTELEN_S  5
-/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1;
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN_M  (SPI_MEM_S_SMEM_OUTMINBYTELEN_V << SPI_MEM_S_SMEM_OUTMINBYTELEN_S)
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN_S  5
+/** SPI_MEM_S_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
  *  accesses to external RAM.
  */
-#define SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_SMEM_TX_DDR_MSK_EN_M  (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S)
-#define SPI_SMEM_TX_DDR_MSK_EN_V  0x00000001U
-#define SPI_SMEM_TX_DDR_MSK_EN_S  12
-/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1;
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_M  (SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S)
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S  12
+/** SPI_MEM_S_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1;
  *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
  *  accesses to external RAM.
  */
-#define SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_SMEM_RX_DDR_MSK_EN_M  (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S)
-#define SPI_SMEM_RX_DDR_MSK_EN_V  0x00000001U
-#define SPI_SMEM_RX_DDR_MSK_EN_S  13
-/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_M  (SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S)
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S  13
+/** SPI_MEM_S_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_SMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_SMEM_USR_DDR_DQS_THD_M  (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S)
-#define SPI_SMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_SMEM_USR_DDR_DQS_THD_S  14
-/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_M  (SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S)
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S  14
+/** SPI_MEM_S_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_SMEM_DDR_DQS_LOOP_M  (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S)
-#define SPI_SMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_SMEM_DDR_DQS_LOOP_S  21
-/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_M  (SPI_MEM_S_SMEM_DDR_DQS_LOOP_V << SPI_MEM_S_SMEM_DDR_DQS_LOOP_S)
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_S  21
+/** SPI_MEM_S_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_SMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_SMEM_CLK_DIFF_EN_M  (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S)
-#define SPI_SMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_SMEM_CLK_DIFF_EN_S  24
-/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN_M  (SPI_MEM_S_SMEM_CLK_DIFF_EN_V << SPI_MEM_S_SMEM_CLK_DIFF_EN_S)
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN_S  24
+/** SPI_MEM_S_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_SMEM_DQS_CA_IN    (BIT(26))
-#define SPI_SMEM_DQS_CA_IN_M  (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S)
-#define SPI_SMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_SMEM_DQS_CA_IN_S  26
-/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
+#define SPI_MEM_S_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_S_SMEM_DQS_CA_IN_M  (SPI_MEM_S_SMEM_DQS_CA_IN_V << SPI_MEM_S_SMEM_DQS_CA_IN_S)
+#define SPI_MEM_S_SMEM_DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_S_SMEM_DQS_CA_IN_S  26
+/** SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_M  (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_S_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to external RAM. .
  */
-#define SPI_SMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_SMEM_CLK_DIFF_INV_M  (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S)
-#define SPI_SMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_SMEM_CLK_DIFF_INV_S  28
-/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV_M  (SPI_MEM_S_SMEM_CLK_DIFF_INV_V << SPI_MEM_S_SMEM_CLK_DIFF_INV_S)
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV_S  28
+/** SPI_MEM_S_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to external RAM, which
  *  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
  *  1'b0}.
  */
-#define SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_SMEM_OCTA_RAM_ADDR_M  (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S)
-#define SPI_SMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_SMEM_OCTA_RAM_ADDR_S  29
-/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_M  (SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S)
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S  29
+/** SPI_MEM_S_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to external RAM, which
  *  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_SMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_SMEM_HYPERBUS_CA_M  (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S)
-#define SPI_SMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_SMEM_HYPERBUS_CA_S  30
+#define SPI_MEM_S_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_S_SMEM_HYPERBUS_CA_M  (SPI_MEM_S_SMEM_HYPERBUS_CA_V << SPI_MEM_S_SMEM_HYPERBUS_CA_S)
+#define SPI_MEM_S_SMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_S_SMEM_HYPERBUS_CA_S  30
 
-/** SPI_FMEM_PMS0_ATTR_REG register
+/** SPI_MEM_S_FMEM_PMS0_ATTR_REG register
  *  MSPI flash PMS section 0 attribute register
  */
-#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100)
-/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100)
+/** SPI_MEM_S_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 0 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS0_RD_ATTR_M  (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S)
-#define SPI_FMEM_PMS0_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS0_RD_ATTR_S  0
-/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS0_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 0 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS0_WR_ATTR_M  (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S)
-#define SPI_FMEM_PMS0_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS0_WR_ATTR_S  1
-/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS0_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and
- *  SPI_FMEM_PMS0_SIZE_REG.
+ *  section 0 is configured by registers SPI_MEM_S_FMEM_PMS0_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS0_SIZE_REG.
  */
-#define SPI_FMEM_PMS0_ECC    (BIT(2))
-#define SPI_FMEM_PMS0_ECC_M  (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S)
-#define SPI_FMEM_PMS0_ECC_V  0x00000001U
-#define SPI_FMEM_PMS0_ECC_S  2
+#define SPI_MEM_S_FMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS0_ECC_M  (SPI_MEM_S_FMEM_PMS0_ECC_V << SPI_MEM_S_FMEM_PMS0_ECC_S)
+#define SPI_MEM_S_FMEM_PMS0_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS0_ECC_S  2
 
-/** SPI_FMEM_PMS1_ATTR_REG register
+/** SPI_MEM_S_FMEM_PMS1_ATTR_REG register
  *  MSPI flash PMS section 1 attribute register
  */
-#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104)
-/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104)
+/** SPI_MEM_S_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 1 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS1_RD_ATTR_M  (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S)
-#define SPI_FMEM_PMS1_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS1_RD_ATTR_S  0
-/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS1_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 1 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS1_WR_ATTR_M  (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S)
-#define SPI_FMEM_PMS1_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS1_WR_ATTR_S  1
-/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS1_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and
- *  SPI_FMEM_PMS1_SIZE_REG.
+ *  section 1 is configured by registers SPI_MEM_S_FMEM_PMS1_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS1_SIZE_REG.
  */
-#define SPI_FMEM_PMS1_ECC    (BIT(2))
-#define SPI_FMEM_PMS1_ECC_M  (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S)
-#define SPI_FMEM_PMS1_ECC_V  0x00000001U
-#define SPI_FMEM_PMS1_ECC_S  2
+#define SPI_MEM_S_FMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS1_ECC_M  (SPI_MEM_S_FMEM_PMS1_ECC_V << SPI_MEM_S_FMEM_PMS1_ECC_S)
+#define SPI_MEM_S_FMEM_PMS1_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS1_ECC_S  2
 
-/** SPI_FMEM_PMS2_ATTR_REG register
+/** SPI_MEM_S_FMEM_PMS2_ATTR_REG register
  *  MSPI flash PMS section 2 attribute register
  */
-#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108)
-/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108)
+/** SPI_MEM_S_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 2 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS2_RD_ATTR_M  (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S)
-#define SPI_FMEM_PMS2_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS2_RD_ATTR_S  0
-/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS2_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 2 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS2_WR_ATTR_M  (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S)
-#define SPI_FMEM_PMS2_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS2_WR_ATTR_S  1
-/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS2_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and
- *  SPI_FMEM_PMS2_SIZE_REG.
+ *  section 2 is configured by registers SPI_MEM_S_FMEM_PMS2_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS2_SIZE_REG.
  */
-#define SPI_FMEM_PMS2_ECC    (BIT(2))
-#define SPI_FMEM_PMS2_ECC_M  (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S)
-#define SPI_FMEM_PMS2_ECC_V  0x00000001U
-#define SPI_FMEM_PMS2_ECC_S  2
+#define SPI_MEM_S_FMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS2_ECC_M  (SPI_MEM_S_FMEM_PMS2_ECC_V << SPI_MEM_S_FMEM_PMS2_ECC_S)
+#define SPI_MEM_S_FMEM_PMS2_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS2_ECC_S  2
 
-/** SPI_FMEM_PMS3_ATTR_REG register
+/** SPI_MEM_S_FMEM_PMS3_ATTR_REG register
  *  MSPI flash PMS section 3 attribute register
  */
-#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c)
-/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c)
+/** SPI_MEM_S_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 flash PMS section 3 read accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS3_RD_ATTR_M  (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S)
-#define SPI_FMEM_PMS3_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS3_RD_ATTR_S  0
-/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS3_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 flash PMS section 3 write accessible. 0: Not allowed.
  */
-#define SPI_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS3_WR_ATTR_M  (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S)
-#define SPI_FMEM_PMS3_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS3_WR_ATTR_S  1
-/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS3_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and
- *  SPI_FMEM_PMS3_SIZE_REG.
+ *  section 3 is configured by registers SPI_MEM_S_FMEM_PMS3_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS3_SIZE_REG.
  */
-#define SPI_FMEM_PMS3_ECC    (BIT(2))
-#define SPI_FMEM_PMS3_ECC_M  (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S)
-#define SPI_FMEM_PMS3_ECC_V  0x00000001U
-#define SPI_FMEM_PMS3_ECC_S  2
+#define SPI_MEM_S_FMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS3_ECC_M  (SPI_MEM_S_FMEM_PMS3_ECC_V << SPI_MEM_S_FMEM_PMS3_ECC_S)
+#define SPI_MEM_S_FMEM_PMS3_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS3_ECC_S  2
 
-/** SPI_FMEM_PMS0_ADDR_REG register
+/** SPI_MEM_S_FMEM_PMS0_ADDR_REG register
  *  SPI1 flash PMS section 0 start address register
  */
-#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110)
-/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110)
+/** SPI_MEM_S_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 0 start address value
  */
-#define SPI_FMEM_PMS0_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS0_ADDR_S_M  (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S)
-#define SPI_FMEM_PMS0_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS0_ADDR_S_S  0
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S_M  (SPI_MEM_S_FMEM_PMS0_ADDR_S_V << SPI_MEM_S_FMEM_PMS0_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S_S  0
 
-/** SPI_FMEM_PMS1_ADDR_REG register
+/** SPI_MEM_S_FMEM_PMS1_ADDR_REG register
  *  SPI1 flash PMS section 1 start address register
  */
-#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114)
-/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114)
+/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 1 start address value
  */
-#define SPI_FMEM_PMS1_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS1_ADDR_S_M  (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S)
-#define SPI_FMEM_PMS1_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS1_ADDR_S_S  0
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S_M  (SPI_MEM_S_FMEM_PMS1_ADDR_S_V << SPI_MEM_S_FMEM_PMS1_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S_S  0
 
-/** SPI_FMEM_PMS2_ADDR_REG register
+/** SPI_MEM_S_FMEM_PMS2_ADDR_REG register
  *  SPI1 flash PMS section 2 start address register
  */
-#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118)
-/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118)
+/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 2 start address value
  */
-#define SPI_FMEM_PMS2_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS2_ADDR_S_M  (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S)
-#define SPI_FMEM_PMS2_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS2_ADDR_S_S  0
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S_M  (SPI_MEM_S_FMEM_PMS2_ADDR_S_V << SPI_MEM_S_FMEM_PMS2_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S_S  0
 
-/** SPI_FMEM_PMS3_ADDR_REG register
+/** SPI_MEM_S_FMEM_PMS3_ADDR_REG register
  *  SPI1 flash PMS section 3 start address register
  */
-#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c)
-/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c)
+/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 flash PMS section 3 start address value
  */
-#define SPI_FMEM_PMS3_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS3_ADDR_S_M  (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S)
-#define SPI_FMEM_PMS3_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS3_ADDR_S_S  0
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S_M  (SPI_MEM_S_FMEM_PMS3_ADDR_S_V << SPI_MEM_S_FMEM_PMS3_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S_S  0
 
-/** SPI_FMEM_PMS0_SIZE_REG register
+/** SPI_MEM_S_FMEM_PMS0_SIZE_REG register
  *  SPI1 flash PMS section 0 start address register
  */
-#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120)
-/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S,
- *  SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE)
+#define SPI_MEM_S_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120)
+/** SPI_MEM_S_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 0 address region is (SPI_MEM_S_FMEM_PMS0_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS0_ADDR_S + SPI_MEM_S_FMEM_PMS0_SIZE)
  */
-#define SPI_FMEM_PMS0_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS0_SIZE_M  (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S)
-#define SPI_FMEM_PMS0_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS0_SIZE_S  0
+#define SPI_MEM_S_FMEM_PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS0_SIZE_M  (SPI_MEM_S_FMEM_PMS0_SIZE_V << SPI_MEM_S_FMEM_PMS0_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS0_SIZE_S  0
 
-/** SPI_FMEM_PMS1_SIZE_REG register
+/** SPI_MEM_S_FMEM_PMS1_SIZE_REG register
  *  SPI1 flash PMS section 1 start address register
  */
-#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124)
-/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S,
- *  SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE)
+#define SPI_MEM_S_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124)
+/** SPI_MEM_S_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 1 address region is (SPI_MEM_S_FMEM_PMS1_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS1_ADDR_S + SPI_MEM_S_FMEM_PMS1_SIZE)
  */
-#define SPI_FMEM_PMS1_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS1_SIZE_M  (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S)
-#define SPI_FMEM_PMS1_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS1_SIZE_S  0
+#define SPI_MEM_S_FMEM_PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS1_SIZE_M  (SPI_MEM_S_FMEM_PMS1_SIZE_V << SPI_MEM_S_FMEM_PMS1_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS1_SIZE_S  0
 
-/** SPI_FMEM_PMS2_SIZE_REG register
+/** SPI_MEM_S_FMEM_PMS2_SIZE_REG register
  *  SPI1 flash PMS section 2 start address register
  */
-#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128)
-/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S,
- *  SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE)
+#define SPI_MEM_S_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128)
+/** SPI_MEM_S_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 2 address region is (SPI_MEM_S_FMEM_PMS2_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS2_ADDR_S + SPI_MEM_S_FMEM_PMS2_SIZE)
  */
-#define SPI_FMEM_PMS2_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS2_SIZE_M  (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S)
-#define SPI_FMEM_PMS2_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS2_SIZE_S  0
+#define SPI_MEM_S_FMEM_PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS2_SIZE_M  (SPI_MEM_S_FMEM_PMS2_SIZE_V << SPI_MEM_S_FMEM_PMS2_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS2_SIZE_S  0
 
-/** SPI_FMEM_PMS3_SIZE_REG register
+/** SPI_MEM_S_FMEM_PMS3_SIZE_REG register
  *  SPI1 flash PMS section 3 start address register
  */
-#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c)
-/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S,
- *  SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE)
+#define SPI_MEM_S_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c)
+/** SPI_MEM_S_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 3 address region is (SPI_MEM_S_FMEM_PMS3_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS3_ADDR_S + SPI_MEM_S_FMEM_PMS3_SIZE)
  */
-#define SPI_FMEM_PMS3_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS3_SIZE_M  (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S)
-#define SPI_FMEM_PMS3_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS3_SIZE_S  0
+#define SPI_MEM_S_FMEM_PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS3_SIZE_M  (SPI_MEM_S_FMEM_PMS3_SIZE_V << SPI_MEM_S_FMEM_PMS3_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS3_SIZE_S  0
 
-/** SPI_SMEM_PMS0_ATTR_REG register
+/** SPI_MEM_S_SMEM_PMS0_ATTR_REG register
  *  SPI1 flash PMS section 0 start address register
  */
-#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130)
-/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130)
+/** SPI_MEM_S_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS0_RD_ATTR_M  (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S)
-#define SPI_SMEM_PMS0_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS0_RD_ATTR_S  0
-/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS0_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS0_WR_ATTR_M  (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S)
-#define SPI_SMEM_PMS0_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS0_WR_ATTR_S  1
-/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS0_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and
- *  SPI_SMEM_PMS0_SIZE_REG.
+ *  external RAM PMS section 0 is configured by registers SPI_MEM_S_SMEM_PMS0_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS0_SIZE_REG.
  */
-#define SPI_SMEM_PMS0_ECC    (BIT(2))
-#define SPI_SMEM_PMS0_ECC_M  (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S)
-#define SPI_SMEM_PMS0_ECC_V  0x00000001U
-#define SPI_SMEM_PMS0_ECC_S  2
+#define SPI_MEM_S_SMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS0_ECC_M  (SPI_MEM_S_SMEM_PMS0_ECC_V << SPI_MEM_S_SMEM_PMS0_ECC_S)
+#define SPI_MEM_S_SMEM_PMS0_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS0_ECC_S  2
 
-/** SPI_SMEM_PMS1_ATTR_REG register
+/** SPI_MEM_S_SMEM_PMS1_ATTR_REG register
  *  SPI1 flash PMS section 1 start address register
  */
-#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134)
-/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134)
+/** SPI_MEM_S_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS1_RD_ATTR_M  (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S)
-#define SPI_SMEM_PMS1_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS1_RD_ATTR_S  0
-/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS1_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS1_WR_ATTR_M  (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S)
-#define SPI_SMEM_PMS1_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS1_WR_ATTR_S  1
-/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS1_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and
- *  SPI_SMEM_PMS1_SIZE_REG.
+ *  external RAM PMS section 1 is configured by registers SPI_MEM_S_SMEM_PMS1_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS1_SIZE_REG.
  */
-#define SPI_SMEM_PMS1_ECC    (BIT(2))
-#define SPI_SMEM_PMS1_ECC_M  (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S)
-#define SPI_SMEM_PMS1_ECC_V  0x00000001U
-#define SPI_SMEM_PMS1_ECC_S  2
+#define SPI_MEM_S_SMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS1_ECC_M  (SPI_MEM_S_SMEM_PMS1_ECC_V << SPI_MEM_S_SMEM_PMS1_ECC_S)
+#define SPI_MEM_S_SMEM_PMS1_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS1_ECC_S  2
 
-/** SPI_SMEM_PMS2_ATTR_REG register
+/** SPI_MEM_S_SMEM_PMS2_ATTR_REG register
  *  SPI1 flash PMS section 2 start address register
  */
-#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138)
-/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138)
+/** SPI_MEM_S_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS2_RD_ATTR_M  (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S)
-#define SPI_SMEM_PMS2_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS2_RD_ATTR_S  0
-/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS2_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS2_WR_ATTR_M  (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S)
-#define SPI_SMEM_PMS2_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS2_WR_ATTR_S  1
-/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS2_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and
- *  SPI_SMEM_PMS2_SIZE_REG.
+ *  external RAM PMS section 2 is configured by registers SPI_MEM_S_SMEM_PMS2_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS2_SIZE_REG.
  */
-#define SPI_SMEM_PMS2_ECC    (BIT(2))
-#define SPI_SMEM_PMS2_ECC_M  (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S)
-#define SPI_SMEM_PMS2_ECC_V  0x00000001U
-#define SPI_SMEM_PMS2_ECC_S  2
+#define SPI_MEM_S_SMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS2_ECC_M  (SPI_MEM_S_SMEM_PMS2_ECC_V << SPI_MEM_S_SMEM_PMS2_ECC_S)
+#define SPI_MEM_S_SMEM_PMS2_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS2_ECC_S  2
 
-/** SPI_SMEM_PMS3_ATTR_REG register
+/** SPI_MEM_S_SMEM_PMS3_ATTR_REG register
  *  SPI1 flash PMS section 3 start address register
  */
-#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c)
-/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c)
+/** SPI_MEM_S_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
  *  1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS3_RD_ATTR_M  (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S)
-#define SPI_SMEM_PMS3_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS3_RD_ATTR_S  0
-/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS3_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
  *  1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed.
  */
-#define SPI_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS3_WR_ATTR_M  (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S)
-#define SPI_SMEM_PMS3_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS3_WR_ATTR_S  1
-/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS3_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
  *  SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and
- *  SPI_SMEM_PMS3_SIZE_REG.
+ *  external RAM PMS section 3 is configured by registers SPI_MEM_S_SMEM_PMS3_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS3_SIZE_REG.
  */
-#define SPI_SMEM_PMS3_ECC    (BIT(2))
-#define SPI_SMEM_PMS3_ECC_M  (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S)
-#define SPI_SMEM_PMS3_ECC_V  0x00000001U
-#define SPI_SMEM_PMS3_ECC_S  2
+#define SPI_MEM_S_SMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS3_ECC_M  (SPI_MEM_S_SMEM_PMS3_ECC_V << SPI_MEM_S_SMEM_PMS3_ECC_S)
+#define SPI_MEM_S_SMEM_PMS3_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS3_ECC_S  2
 
-/** SPI_SMEM_PMS0_ADDR_REG register
+/** SPI_MEM_S_SMEM_PMS0_ADDR_REG register
  *  SPI1 external RAM PMS section 0 start address register
  */
-#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140)
-/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140)
+/** SPI_MEM_S_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 0 start address value
  */
-#define SPI_SMEM_PMS0_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS0_ADDR_S_M  (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S)
-#define SPI_SMEM_PMS0_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS0_ADDR_S_S  0
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S_M  (SPI_MEM_S_SMEM_PMS0_ADDR_S_V << SPI_MEM_S_SMEM_PMS0_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S_S  0
 
-/** SPI_SMEM_PMS1_ADDR_REG register
+/** SPI_MEM_S_SMEM_PMS1_ADDR_REG register
  *  SPI1 external RAM PMS section 1 start address register
  */
-#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144)
-/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144)
+/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 1 start address value
  */
-#define SPI_SMEM_PMS1_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS1_ADDR_S_M  (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S)
-#define SPI_SMEM_PMS1_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS1_ADDR_S_S  0
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S_M  (SPI_MEM_S_SMEM_PMS1_ADDR_S_V << SPI_MEM_S_SMEM_PMS1_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S_S  0
 
-/** SPI_SMEM_PMS2_ADDR_REG register
+/** SPI_MEM_S_SMEM_PMS2_ADDR_REG register
  *  SPI1 external RAM PMS section 2 start address register
  */
-#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148)
-/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148)
+/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 2 start address value
  */
-#define SPI_SMEM_PMS2_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS2_ADDR_S_M  (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S)
-#define SPI_SMEM_PMS2_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS2_ADDR_S_S  0
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S_M  (SPI_MEM_S_SMEM_PMS2_ADDR_S_V << SPI_MEM_S_SMEM_PMS2_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S_S  0
 
-/** SPI_SMEM_PMS3_ADDR_REG register
+/** SPI_MEM_S_SMEM_PMS3_ADDR_REG register
  *  SPI1 external RAM PMS section 3 start address register
  */
-#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c)
-/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c)
+/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
  *  SPI1 external RAM PMS section 3 start address value
  */
-#define SPI_SMEM_PMS3_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS3_ADDR_S_M  (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S)
-#define SPI_SMEM_PMS3_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS3_ADDR_S_S  0
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S_M  (SPI_MEM_S_SMEM_PMS3_ADDR_S_V << SPI_MEM_S_SMEM_PMS3_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S_S  0
 
-/** SPI_SMEM_PMS0_SIZE_REG register
+/** SPI_MEM_S_SMEM_PMS0_SIZE_REG register
  *  SPI1 external RAM PMS section 0 start address register
  */
-#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150)
-/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S,
- *  SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE)
+#define SPI_MEM_S_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150)
+/** SPI_MEM_S_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 0 address region is (SPI_MEM_S_SMEM_PMS0_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS0_ADDR_S + SPI_MEM_S_SMEM_PMS0_SIZE)
  */
-#define SPI_SMEM_PMS0_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS0_SIZE_M  (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S)
-#define SPI_SMEM_PMS0_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS0_SIZE_S  0
+#define SPI_MEM_S_SMEM_PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS0_SIZE_M  (SPI_MEM_S_SMEM_PMS0_SIZE_V << SPI_MEM_S_SMEM_PMS0_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS0_SIZE_S  0
 
-/** SPI_SMEM_PMS1_SIZE_REG register
+/** SPI_MEM_S_SMEM_PMS1_SIZE_REG register
  *  SPI1 external RAM PMS section 1 start address register
  */
-#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154)
-/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S,
- *  SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE)
+#define SPI_MEM_S_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154)
+/** SPI_MEM_S_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 1 address region is (SPI_MEM_S_SMEM_PMS1_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS1_ADDR_S + SPI_MEM_S_SMEM_PMS1_SIZE)
  */
-#define SPI_SMEM_PMS1_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS1_SIZE_M  (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S)
-#define SPI_SMEM_PMS1_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS1_SIZE_S  0
+#define SPI_MEM_S_SMEM_PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS1_SIZE_M  (SPI_MEM_S_SMEM_PMS1_SIZE_V << SPI_MEM_S_SMEM_PMS1_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS1_SIZE_S  0
 
-/** SPI_SMEM_PMS2_SIZE_REG register
+/** SPI_MEM_S_SMEM_PMS2_SIZE_REG register
  *  SPI1 external RAM PMS section 2 start address register
  */
-#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158)
-/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S,
- *  SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE)
+#define SPI_MEM_S_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158)
+/** SPI_MEM_S_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 2 address region is (SPI_MEM_S_SMEM_PMS2_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS2_ADDR_S + SPI_MEM_S_SMEM_PMS2_SIZE)
  */
-#define SPI_SMEM_PMS2_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS2_SIZE_M  (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S)
-#define SPI_SMEM_PMS2_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS2_SIZE_S  0
+#define SPI_MEM_S_SMEM_PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS2_SIZE_M  (SPI_MEM_S_SMEM_PMS2_SIZE_V << SPI_MEM_S_SMEM_PMS2_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS2_SIZE_S  0
 
-/** SPI_SMEM_PMS3_SIZE_REG register
+/** SPI_MEM_S_SMEM_PMS3_SIZE_REG register
  *  SPI1 external RAM PMS section 3 start address register
  */
-#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c)
-/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S,
- *  SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE)
+#define SPI_MEM_S_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c)
+/** SPI_MEM_S_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 3 address region is (SPI_MEM_S_SMEM_PMS3_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS3_ADDR_S + SPI_MEM_S_SMEM_PMS3_SIZE)
  */
-#define SPI_SMEM_PMS3_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS3_SIZE_M  (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S)
-#define SPI_SMEM_PMS3_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS3_SIZE_S  0
+#define SPI_MEM_S_SMEM_PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS3_SIZE_M  (SPI_MEM_S_SMEM_PMS3_SIZE_V << SPI_MEM_S_SMEM_PMS3_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS3_SIZE_S  0
 
-/** SPI_MEM_PMS_REJECT_REG register
+/** SPI_MEM_S_PMS_REJECT_REG register
  *  SPI1 access reject register
  */
-#define SPI_MEM_PMS_REJECT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x164)
-/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_PMS_REJECT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x164)
+/** SPI_MEM_S_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
  *  This bits show the first SPI1 access error address. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_REJECT_ADDR    0x07FFFFFFU
-#define SPI_MEM_REJECT_ADDR_M  (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S)
-#define SPI_MEM_REJECT_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_REJECT_ADDR_S  0
-/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0;
+#define SPI_MEM_S_REJECT_ADDR    0x07FFFFFFU
+#define SPI_MEM_S_REJECT_ADDR_M  (SPI_MEM_S_REJECT_ADDR_V << SPI_MEM_S_REJECT_ADDR_S)
+#define SPI_MEM_S_REJECT_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_S_REJECT_ADDR_S  0
+/** SPI_MEM_S_PM_EN : R/W; bitpos: [27]; default: 0;
  *  Set this bit to enable SPI0/1 transfer permission control function.
  */
-#define SPI_MEM_PM_EN    (BIT(27))
-#define SPI_MEM_PM_EN_M  (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S)
-#define SPI_MEM_PM_EN_V  0x00000001U
-#define SPI_MEM_PM_EN_S  27
-/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0;
+#define SPI_MEM_S_PM_EN    (BIT(27))
+#define SPI_MEM_S_PM_EN_M  (SPI_MEM_S_PM_EN_V << SPI_MEM_S_PM_EN_S)
+#define SPI_MEM_S_PM_EN_V  0x00000001U
+#define SPI_MEM_S_PM_EN_S  27
+/** SPI_MEM_S_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0;
  *  1: SPI1 write access error. 0: No write access error. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_LD    (BIT(28))
-#define SPI_MEM_PMS_LD_M  (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S)
-#define SPI_MEM_PMS_LD_V  0x00000001U
-#define SPI_MEM_PMS_LD_S  28
-/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0;
+#define SPI_MEM_S_PMS_LD    (BIT(28))
+#define SPI_MEM_S_PMS_LD_M  (SPI_MEM_S_PMS_LD_V << SPI_MEM_S_PMS_LD_S)
+#define SPI_MEM_S_PMS_LD_V  0x00000001U
+#define SPI_MEM_S_PMS_LD_S  28
+/** SPI_MEM_S_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0;
  *  1: SPI1 read access error. 0: No read access error. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_ST    (BIT(29))
-#define SPI_MEM_PMS_ST_M  (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S)
-#define SPI_MEM_PMS_ST_V  0x00000001U
-#define SPI_MEM_PMS_ST_S  29
-/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0;
+#define SPI_MEM_S_PMS_ST    (BIT(29))
+#define SPI_MEM_S_PMS_ST_M  (SPI_MEM_S_PMS_ST_V << SPI_MEM_S_PMS_ST_S)
+#define SPI_MEM_S_PMS_ST_V  0x00000001U
+#define SPI_MEM_S_PMS_ST_S  29
+/** SPI_MEM_S_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0;
  *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
- *  cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_M  (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S)
-#define SPI_MEM_PMS_MULTI_HIT_V  0x00000001U
-#define SPI_MEM_PMS_MULTI_HIT_S  30
-/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0;
+#define SPI_MEM_S_PMS_MULTI_HIT    (BIT(30))
+#define SPI_MEM_S_PMS_MULTI_HIT_M  (SPI_MEM_S_PMS_MULTI_HIT_V << SPI_MEM_S_PMS_MULTI_HIT_S)
+#define SPI_MEM_S_PMS_MULTI_HIT_V  0x00000001U
+#define SPI_MEM_S_PMS_MULTI_HIT_S  30
+/** SPI_MEM_S_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0;
  *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- *  error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+ *  error. It is cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
  */
-#define SPI_MEM_PMS_IVD    (BIT(31))
-#define SPI_MEM_PMS_IVD_M  (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S)
-#define SPI_MEM_PMS_IVD_V  0x00000001U
-#define SPI_MEM_PMS_IVD_S  31
+#define SPI_MEM_S_PMS_IVD    (BIT(31))
+#define SPI_MEM_S_PMS_IVD_M  (SPI_MEM_S_PMS_IVD_V << SPI_MEM_S_PMS_IVD_S)
+#define SPI_MEM_S_PMS_IVD_V  0x00000001U
+#define SPI_MEM_S_PMS_IVD_S  31
 
-/** SPI_MEM_ECC_CTRL_REG register
+/** SPI_MEM_S_ECC_CTRL_REG register
  *  MSPI ECC control register
  */
-#define SPI_MEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x168)
-/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0;
+#define SPI_MEM_S_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x168)
+/** SPI_MEM_S_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0;
  *  This bits show the error times of MSPI ECC read. It is cleared by when
- *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+ *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
  */
-#define SPI_MEM_ECC_ERR_CNT    0x0000003FU
-#define SPI_MEM_ECC_ERR_CNT_M  (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S)
-#define SPI_MEM_ECC_ERR_CNT_V  0x0000003FU
-#define SPI_MEM_ECC_ERR_CNT_S  5
-/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10;
- *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.
+#define SPI_MEM_S_ECC_ERR_CNT    0x0000003FU
+#define SPI_MEM_S_ECC_ERR_CNT_M  (SPI_MEM_S_ECC_ERR_CNT_V << SPI_MEM_S_ECC_ERR_CNT_S)
+#define SPI_MEM_S_ECC_ERR_CNT_V  0x0000003FU
+#define SPI_MEM_S_ECC_ERR_CNT_S  5
+/** SPI_MEM_S_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10;
+ *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt.
  */
-#define SPI_FMEM_ECC_ERR_INT_NUM    0x0000003FU
-#define SPI_FMEM_ECC_ERR_INT_NUM_M  (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S)
-#define SPI_FMEM_ECC_ERR_INT_NUM_V  0x0000003FU
-#define SPI_FMEM_ECC_ERR_INT_NUM_S  11
-/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0;
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM    0x0000003FU
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_M  (SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V << SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S)
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V  0x0000003FU
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S  11
+/** SPI_MEM_S_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0;
  *  Set this bit to calculate the error times of MSPI ECC read when accesses to flash.
  */
-#define SPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_FMEM_ECC_ERR_INT_EN_M  (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S)
-#define SPI_FMEM_ECC_ERR_INT_EN_V  0x00000001U
-#define SPI_FMEM_ECC_ERR_INT_EN_S  17
-/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0;
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_M  (SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S)
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S  17
+/** SPI_MEM_S_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0;
  *  Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
  *  1024 bytes. 3: 2048 bytes.
  */
-#define SPI_FMEM_PAGE_SIZE    0x00000003U
-#define SPI_FMEM_PAGE_SIZE_M  (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S)
-#define SPI_FMEM_PAGE_SIZE_V  0x00000003U
-#define SPI_FMEM_PAGE_SIZE_S  18
-/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0;
+#define SPI_MEM_S_FMEM_PAGE_SIZE    0x00000003U
+#define SPI_MEM_S_FMEM_PAGE_SIZE_M  (SPI_MEM_S_FMEM_PAGE_SIZE_V << SPI_MEM_S_FMEM_PAGE_SIZE_S)
+#define SPI_MEM_S_FMEM_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_S_FMEM_PAGE_SIZE_S  18
+/** SPI_MEM_S_FMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0;
  *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
  *  ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit
  *  should be 0. Otherwise, this bit should be 1.
  */
-#define SPI_FMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_FMEM_ECC_ADDR_EN_M  (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S)
-#define SPI_FMEM_ECC_ADDR_EN_V  0x00000001U
-#define SPI_FMEM_ECC_ADDR_EN_S  20
-/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0;
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN_M  (SPI_MEM_S_FMEM_ECC_ADDR_EN_V << SPI_MEM_S_FMEM_ECC_ADDR_EN_S)
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN_S  20
+/** SPI_MEM_S_USR_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0;
  *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
  */
-#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_M  (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S)
-#define SPI_MEM_USR_ECC_ADDR_EN_V  0x00000001U
-#define SPI_MEM_USR_ECC_ADDR_EN_S  21
-/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1;
- *  1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is
- *  updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and
- *  SPI_MEM_ECC_ERR_ADDR record the first ECC error information.
+#define SPI_MEM_S_USR_ECC_ADDR_EN    (BIT(21))
+#define SPI_MEM_S_USR_ECC_ADDR_EN_M  (SPI_MEM_S_USR_ECC_ADDR_EN_V << SPI_MEM_S_USR_ECC_ADDR_EN_S)
+#define SPI_MEM_S_USR_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_S_USR_ECC_ADDR_EN_S  21
+/** SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1;
+ *  1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is
+ *  updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and
+ *  SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information.
  */
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S)
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x00000001U
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0;
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_M  (SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S)
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V  0x00000001U
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/** SPI_MEM_S_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0;
  *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
  *  byte 0 bit 0 to byte 15 bit 7)
  */
-#define SPI_MEM_ECC_ERR_BITS    0x0000007FU
-#define SPI_MEM_ECC_ERR_BITS_M  (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S)
-#define SPI_MEM_ECC_ERR_BITS_V  0x0000007FU
-#define SPI_MEM_ECC_ERR_BITS_S  25
+#define SPI_MEM_S_ECC_ERR_BITS    0x0000007FU
+#define SPI_MEM_S_ECC_ERR_BITS_M  (SPI_MEM_S_ECC_ERR_BITS_V << SPI_MEM_S_ECC_ERR_BITS_S)
+#define SPI_MEM_S_ECC_ERR_BITS_V  0x0000007FU
+#define SPI_MEM_S_ECC_ERR_BITS_S  25
 
-/** SPI_MEM_ECC_ERR_ADDR_REG register
+/** SPI_MEM_S_ECC_ERR_ADDR_REG register
  *  MSPI ECC error address register
  */
-#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x16c)
-/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_ECC_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x16c)
+/** SPI_MEM_S_ECC_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
  *  This bits show the first MSPI ECC error address. It is cleared by when
- *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+ *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
  */
-#define SPI_MEM_ECC_ERR_ADDR    0x07FFFFFFU
-#define SPI_MEM_ECC_ERR_ADDR_M  (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S)
-#define SPI_MEM_ECC_ERR_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_ECC_ERR_ADDR_S  0
+#define SPI_MEM_S_ECC_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_S_ECC_ERR_ADDR_M  (SPI_MEM_S_ECC_ERR_ADDR_V << SPI_MEM_S_ECC_ERR_ADDR_S)
+#define SPI_MEM_S_ECC_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_S_ECC_ERR_ADDR_S  0
 
-/** SPI_MEM_AXI_ERR_ADDR_REG register
+/** SPI_MEM_S_AXI_ERR_ADDR_REG register
  *  SPI0 AXI request error address.
  */
-#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x170)
-/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+#define SPI_MEM_S_AXI_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x170)
+/** SPI_MEM_S_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
  *  This bits show the first AXI write/read invalid error or AXI write flash error
- *  address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
- *  SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
+ *  address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR,
+ *  SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set.
  */
-#define SPI_MEM_AXI_ERR_ADDR    0x07FFFFFFU
-#define SPI_MEM_AXI_ERR_ADDR_M  (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S)
-#define SPI_MEM_AXI_ERR_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_AXI_ERR_ADDR_S  0
+#define SPI_MEM_S_AXI_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_S_AXI_ERR_ADDR_M  (SPI_MEM_S_AXI_ERR_ADDR_V << SPI_MEM_S_AXI_ERR_ADDR_S)
+#define SPI_MEM_S_AXI_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_S_AXI_ERR_ADDR_S  0
 
-/** SPI_SMEM_ECC_CTRL_REG register
+/** SPI_MEM_S_SMEM_ECC_CTRL_REG register
  *  MSPI ECC control register
  */
-#define SPI_SMEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x174)
-/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0;
+#define SPI_MEM_S_SMEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x174)
+/** SPI_MEM_S_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0;
  *  Set this bit to calculate the error times of MSPI ECC read when accesses to
  *  external RAM.
  */
-#define SPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_SMEM_ECC_ERR_INT_EN_M  (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S)
-#define SPI_SMEM_ECC_ERR_INT_EN_V  0x00000001U
-#define SPI_SMEM_ECC_ERR_INT_EN_S  17
-/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2;
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_M  (SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S)
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S  17
+/** SPI_MEM_S_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2;
  *  Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes.
  *  2: 1024 bytes. 3: 2048 bytes.
  */
-#define SPI_SMEM_PAGE_SIZE    0x00000003U
-#define SPI_SMEM_PAGE_SIZE_M  (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S)
-#define SPI_SMEM_PAGE_SIZE_V  0x00000003U
-#define SPI_SMEM_PAGE_SIZE_S  18
-/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0;
+#define SPI_MEM_S_SMEM_PAGE_SIZE    0x00000003U
+#define SPI_MEM_S_SMEM_PAGE_SIZE_M  (SPI_MEM_S_SMEM_PAGE_SIZE_V << SPI_MEM_S_SMEM_PAGE_SIZE_S)
+#define SPI_MEM_S_SMEM_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_S_SMEM_PAGE_SIZE_S  18
+/** SPI_MEM_S_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0;
  *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
  *  ECC region or non-ECC region of external RAM. If there is no ECC region in external
  *  RAM, this bit should be 0. Otherwise, this bit should be 1.
  */
-#define SPI_SMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_SMEM_ECC_ADDR_EN_M  (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S)
-#define SPI_SMEM_ECC_ADDR_EN_V  0x00000001U
-#define SPI_SMEM_ECC_ADDR_EN_S  20
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN_M  (SPI_MEM_S_SMEM_ECC_ADDR_EN_V << SPI_MEM_S_SMEM_ECC_ADDR_EN_S)
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN_S  20
 
-/** SPI_SMEM_AXI_ADDR_CTRL_REG register
+/** SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG register
  *  SPI0 AXI address control register
  */
-#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x178)
-/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
+#define SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x178)
+/** SPI_MEM_S_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
  *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
  *  and SPI0 transfers are done. 0: Others.
  */
-#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_M  (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S)
-#define SPI_MEM_ALL_FIFO_EMPTY_V  0x00000001U
-#define SPI_MEM_ALL_FIFO_EMPTY_S  26
-/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1;
+#define SPI_MEM_S_ALL_FIFO_EMPTY    (BIT(26))
+#define SPI_MEM_S_ALL_FIFO_EMPTY_M  (SPI_MEM_S_ALL_FIFO_EMPTY_V << SPI_MEM_S_ALL_FIFO_EMPTY_S)
+#define SPI_MEM_S_ALL_FIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_S_ALL_FIFO_EMPTY_S  26
+/** SPI_MEM_S_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1;
  *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
  */
-#define SPI_RDATA_AFIFO_REMPTY    (BIT(27))
-#define SPI_RDATA_AFIFO_REMPTY_M  (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S)
-#define SPI_RDATA_AFIFO_REMPTY_V  0x00000001U
-#define SPI_RDATA_AFIFO_REMPTY_S  27
-/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1;
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY    (BIT(27))
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY_M  (SPI_MEM_S_RDATA_AFIFO_REMPTY_V << SPI_MEM_S_RDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY_S  27
+/** SPI_MEM_S_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1;
  *  1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
  */
-#define SPI_RADDR_AFIFO_REMPTY    (BIT(28))
-#define SPI_RADDR_AFIFO_REMPTY_M  (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S)
-#define SPI_RADDR_AFIFO_REMPTY_V  0x00000001U
-#define SPI_RADDR_AFIFO_REMPTY_S  28
-/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1;
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY    (BIT(28))
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY_M  (SPI_MEM_S_RADDR_AFIFO_REMPTY_V << SPI_MEM_S_RADDR_AFIFO_REMPTY_S)
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY_S  28
+/** SPI_MEM_S_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1;
  *  1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
  */
-#define SPI_WDATA_AFIFO_REMPTY    (BIT(29))
-#define SPI_WDATA_AFIFO_REMPTY_M  (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S)
-#define SPI_WDATA_AFIFO_REMPTY_V  0x00000001U
-#define SPI_WDATA_AFIFO_REMPTY_S  29
-/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1;
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY    (BIT(29))
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY_M  (SPI_MEM_S_WDATA_AFIFO_REMPTY_V << SPI_MEM_S_WDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY_S  29
+/** SPI_MEM_S_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1;
  *  1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
  */
-#define SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define SPI_WBLEN_AFIFO_REMPTY_M  (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S)
-#define SPI_WBLEN_AFIFO_REMPTY_V  0x00000001U
-#define SPI_WBLEN_AFIFO_REMPTY_S  30
-/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1;
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_M  (SPI_MEM_S_WBLEN_AFIFO_REMPTY_V << SPI_MEM_S_WBLEN_AFIFO_REMPTY_S)
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_S  30
+/** SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1;
  *  This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and
  *  RDATA_AFIFO are empty and spi0_mst_st is IDLE.
  */
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S)
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x00000001U
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_M  (SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S)
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
 
-/** SPI_MEM_AXI_ERR_RESP_EN_REG register
+/** SPI_MEM_S_AXI_ERR_RESP_EN_REG register
  *  SPI0 AXI error response enable register
  */
-#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_PSRAM_MSPI0_BASE + 0x17c)
-/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_AXI_ERR_RESP_EN_REG (DR_REG_PSRAM_MSPI0_BASE + 0x17c)
+/** SPI_MEM_S_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0;
  *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_VLD    (BIT(0))
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_M  (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S)
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_S  0
-/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD    (BIT(0))
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_M  (SPI_MEM_S_AW_RESP_EN_MMU_VLD_V << SPI_MEM_S_AW_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_S  0
+/** SPI_MEM_S_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0;
  *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_GID    (BIT(1))
-#define SPI_MEM_AW_RESP_EN_MMU_GID_M  (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S)
-#define SPI_MEM_AW_RESP_EN_MMU_GID_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_GID_S  1
-/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID    (BIT(1))
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID_M  (SPI_MEM_S_AW_RESP_EN_MMU_GID_V << SPI_MEM_S_AW_RESP_EN_MMU_GID_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID_S  1
+/** SPI_MEM_S_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0;
  *  Set this bit  to enable AXI response function for axi size err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE    (BIT(2))
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M  (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S)
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S  2
-/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0;
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE    (BIT(2))
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_M  (SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S  2
+/** SPI_MEM_S_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0;
  *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH    (BIT(3))
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M  (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S)
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S  3
-/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH    (BIT(3))
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_M  (SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S)
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S  3
+/** SPI_MEM_S_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0;
  *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_ECC    (BIT(4))
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_M  (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S)
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_S  4
-/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC    (BIT(4))
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_M  (SPI_MEM_S_AW_RESP_EN_MMU_ECC_V << SPI_MEM_S_AW_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_S  4
+/** SPI_MEM_S_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0;
  *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_MMU_SENS    (BIT(5))
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_M  (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S)
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_S  5
-/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS    (BIT(5))
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_M  (SPI_MEM_S_AW_RESP_EN_MMU_SENS_V << SPI_MEM_S_AW_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_S  5
+/** SPI_MEM_S_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0;
  *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
  */
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB    (BIT(6))
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M  (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S)
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S  6
-/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB    (BIT(6))
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_M  (SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S)
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S  6
+/** SPI_MEM_S_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0;
  *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_VLD    (BIT(7))
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_M  (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S)
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_S  7
-/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD    (BIT(7))
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_M  (SPI_MEM_S_AR_RESP_EN_MMU_VLD_V << SPI_MEM_S_AR_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_S  7
+/** SPI_MEM_S_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0;
  *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_GID    (BIT(8))
-#define SPI_MEM_AR_RESP_EN_MMU_GID_M  (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S)
-#define SPI_MEM_AR_RESP_EN_MMU_GID_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_GID_S  8
-/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0;
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID    (BIT(8))
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID_M  (SPI_MEM_S_AR_RESP_EN_MMU_GID_V << SPI_MEM_S_AR_RESP_EN_MMU_GID_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID_S  8
+/** SPI_MEM_S_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0;
  *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_ECC    (BIT(9))
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_M  (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S)
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_S  9
-/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0;
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC    (BIT(9))
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_M  (SPI_MEM_S_AR_RESP_EN_MMU_ECC_V << SPI_MEM_S_AR_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_S  9
+/** SPI_MEM_S_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0;
  *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
  *  trans.
  */
-#define SPI_MEM_AR_RESP_EN_MMU_SENS    (BIT(10))
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_M  (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S)
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_S  10
-/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0;
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS    (BIT(10))
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_M  (SPI_MEM_S_AR_RESP_EN_MMU_SENS_V << SPI_MEM_S_AR_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_S  10
+/** SPI_MEM_S_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0;
  *  Set this bit  to enable AXI response function for axi size err in axi read trans.
  */
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE    (BIT(11))
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M  (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S)
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S  11
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE    (BIT(11))
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_M  (SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S  11
 
-/** SPI_MEM_TIMING_CALI_REG register
+/** SPI_MEM_S_TIMING_CALI_REG register
  *  SPI0 flash timing calibration register
  */
-#define SPI_MEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x180)
-/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x180)
+/** SPI_MEM_S_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
  *  The bit is used to enable timing adjust clock for all reading operations.
  */
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S)
-#define SPI_MEM_TIMING_CLK_ENA_V  0x00000001U
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_S_TIMING_CLK_ENA_M  (SPI_MEM_S_TIMING_CLK_ENA_V << SPI_MEM_S_TIMING_CLK_ENA_S)
+#define SPI_MEM_S_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_S_TIMING_CLK_ENA_S  0
+/** SPI_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  The bit is used to enable timing auto-calibration for all reading operations.
  */
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S)
-#define SPI_MEM_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_S  1
-/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+#define SPI_MEM_S_TIMING_CALI    (BIT(1))
+#define SPI_MEM_S_TIMING_CALI_M  (SPI_MEM_S_TIMING_CALI_V << SPI_MEM_S_TIMING_CALI_S)
+#define SPI_MEM_S_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_TIMING_CALI_S  1
+/** SPI_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
  *  add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_S_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0;
  *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
  *  flash.
  */
-#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_M  (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S)
-#define SPI_MEM_DLL_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_DLL_TIMING_CALI_S  5
-/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0;
+#define SPI_MEM_S_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_S_DLL_TIMING_CALI_M  (SPI_MEM_S_DLL_TIMING_CALI_V << SPI_MEM_S_DLL_TIMING_CALI_S)
+#define SPI_MEM_S_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_DLL_TIMING_CALI_S  5
+/** SPI_MEM_S_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0;
  *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
  */
-#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_M  (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S)
-#define SPI_MEM_TIMING_CALI_UPDATE_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_UPDATE_S  6
+#define SPI_MEM_S_TIMING_CALI_UPDATE    (BIT(6))
+#define SPI_MEM_S_TIMING_CALI_UPDATE_M  (SPI_MEM_S_TIMING_CALI_UPDATE_V << SPI_MEM_S_TIMING_CALI_UPDATE_S)
+#define SPI_MEM_S_TIMING_CALI_UPDATE_V  0x00000001U
+#define SPI_MEM_S_TIMING_CALI_UPDATE_S  6
 
-/** SPI_MEM_DIN_MODE_REG register
+/** SPI_MEM_S_DIN_MODE_REG register
  *  MSPI flash input timing delay mode control register
  */
-#define SPI_MEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x184)
-/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
+#define SPI_MEM_S_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x184)
+/** SPI_MEM_S_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN0_MODE    0x00000007U
-#define SPI_MEM_DIN0_MODE_M  (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S)
-#define SPI_MEM_DIN0_MODE_V  0x00000007U
-#define SPI_MEM_DIN0_MODE_S  0
-/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
+#define SPI_MEM_S_DIN0_MODE    0x00000007U
+#define SPI_MEM_S_DIN0_MODE_M  (SPI_MEM_S_DIN0_MODE_V << SPI_MEM_S_DIN0_MODE_S)
+#define SPI_MEM_S_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN0_MODE_S  0
+/** SPI_MEM_S_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN1_MODE    0x00000007U
-#define SPI_MEM_DIN1_MODE_M  (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S)
-#define SPI_MEM_DIN1_MODE_V  0x00000007U
-#define SPI_MEM_DIN1_MODE_S  3
-/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
+#define SPI_MEM_S_DIN1_MODE    0x00000007U
+#define SPI_MEM_S_DIN1_MODE_M  (SPI_MEM_S_DIN1_MODE_V << SPI_MEM_S_DIN1_MODE_S)
+#define SPI_MEM_S_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN1_MODE_S  3
+/** SPI_MEM_S_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN2_MODE    0x00000007U
-#define SPI_MEM_DIN2_MODE_M  (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S)
-#define SPI_MEM_DIN2_MODE_V  0x00000007U
-#define SPI_MEM_DIN2_MODE_S  6
-/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
+#define SPI_MEM_S_DIN2_MODE    0x00000007U
+#define SPI_MEM_S_DIN2_MODE_M  (SPI_MEM_S_DIN2_MODE_V << SPI_MEM_S_DIN2_MODE_S)
+#define SPI_MEM_S_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN2_MODE_S  6
+/** SPI_MEM_S_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_MEM_DIN3_MODE    0x00000007U
-#define SPI_MEM_DIN3_MODE_M  (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S)
-#define SPI_MEM_DIN3_MODE_V  0x00000007U
-#define SPI_MEM_DIN3_MODE_S  9
-/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
+#define SPI_MEM_S_DIN3_MODE    0x00000007U
+#define SPI_MEM_S_DIN3_MODE_M  (SPI_MEM_S_DIN3_MODE_V << SPI_MEM_S_DIN3_MODE_S)
+#define SPI_MEM_S_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN3_MODE_S  9
+/** SPI_MEM_S_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN4_MODE    0x00000007U
-#define SPI_MEM_DIN4_MODE_M  (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S)
-#define SPI_MEM_DIN4_MODE_V  0x00000007U
-#define SPI_MEM_DIN4_MODE_S  12
-/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
+#define SPI_MEM_S_DIN4_MODE    0x00000007U
+#define SPI_MEM_S_DIN4_MODE_M  (SPI_MEM_S_DIN4_MODE_V << SPI_MEM_S_DIN4_MODE_S)
+#define SPI_MEM_S_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN4_MODE_S  12
+/** SPI_MEM_S_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN5_MODE    0x00000007U
-#define SPI_MEM_DIN5_MODE_M  (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S)
-#define SPI_MEM_DIN5_MODE_V  0x00000007U
-#define SPI_MEM_DIN5_MODE_S  15
-/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
+#define SPI_MEM_S_DIN5_MODE    0x00000007U
+#define SPI_MEM_S_DIN5_MODE_M  (SPI_MEM_S_DIN5_MODE_V << SPI_MEM_S_DIN5_MODE_S)
+#define SPI_MEM_S_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN5_MODE_S  15
+/** SPI_MEM_S_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN6_MODE    0x00000007U
-#define SPI_MEM_DIN6_MODE_M  (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S)
-#define SPI_MEM_DIN6_MODE_V  0x00000007U
-#define SPI_MEM_DIN6_MODE_S  18
-/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
+#define SPI_MEM_S_DIN6_MODE    0x00000007U
+#define SPI_MEM_S_DIN6_MODE_M  (SPI_MEM_S_DIN6_MODE_V << SPI_MEM_S_DIN6_MODE_S)
+#define SPI_MEM_S_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN6_MODE_S  18
+/** SPI_MEM_S_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DIN7_MODE    0x00000007U
-#define SPI_MEM_DIN7_MODE_M  (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S)
-#define SPI_MEM_DIN7_MODE_V  0x00000007U
-#define SPI_MEM_DIN7_MODE_S  21
-/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
+#define SPI_MEM_S_DIN7_MODE    0x00000007U
+#define SPI_MEM_S_DIN7_MODE_M  (SPI_MEM_S_DIN7_MODE_V << SPI_MEM_S_DIN7_MODE_S)
+#define SPI_MEM_S_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN7_MODE_S  21
+/** SPI_MEM_S_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
  *  with the spi_clk
  */
-#define SPI_MEM_DINS_MODE    0x00000007U
-#define SPI_MEM_DINS_MODE_M  (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S)
-#define SPI_MEM_DINS_MODE_V  0x00000007U
-#define SPI_MEM_DINS_MODE_S  24
+#define SPI_MEM_S_DINS_MODE    0x00000007U
+#define SPI_MEM_S_DINS_MODE_M  (SPI_MEM_S_DINS_MODE_V << SPI_MEM_S_DINS_MODE_S)
+#define SPI_MEM_S_DINS_MODE_V  0x00000007U
+#define SPI_MEM_S_DINS_MODE_S  24
 
-/** SPI_MEM_DIN_NUM_REG register
+/** SPI_MEM_S_DIN_NUM_REG register
  *  MSPI flash input timing delay number control register
  */
-#define SPI_MEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x188)
-/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_S_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x188)
+/** SPI_MEM_S_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN0_NUM    0x00000003U
-#define SPI_MEM_DIN0_NUM_M  (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S)
-#define SPI_MEM_DIN0_NUM_V  0x00000003U
-#define SPI_MEM_DIN0_NUM_S  0
-/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+#define SPI_MEM_S_DIN0_NUM    0x00000003U
+#define SPI_MEM_S_DIN0_NUM_M  (SPI_MEM_S_DIN0_NUM_V << SPI_MEM_S_DIN0_NUM_S)
+#define SPI_MEM_S_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN0_NUM_S  0
+/** SPI_MEM_S_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN1_NUM    0x00000003U
-#define SPI_MEM_DIN1_NUM_M  (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S)
-#define SPI_MEM_DIN1_NUM_V  0x00000003U
-#define SPI_MEM_DIN1_NUM_S  2
-/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+#define SPI_MEM_S_DIN1_NUM    0x00000003U
+#define SPI_MEM_S_DIN1_NUM_M  (SPI_MEM_S_DIN1_NUM_V << SPI_MEM_S_DIN1_NUM_S)
+#define SPI_MEM_S_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN1_NUM_S  2
+/** SPI_MEM_S_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN2_NUM    0x00000003U
-#define SPI_MEM_DIN2_NUM_M  (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S)
-#define SPI_MEM_DIN2_NUM_V  0x00000003U
-#define SPI_MEM_DIN2_NUM_S  4
-/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+#define SPI_MEM_S_DIN2_NUM    0x00000003U
+#define SPI_MEM_S_DIN2_NUM_M  (SPI_MEM_S_DIN2_NUM_V << SPI_MEM_S_DIN2_NUM_S)
+#define SPI_MEM_S_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN2_NUM_S  4
+/** SPI_MEM_S_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN3_NUM    0x00000003U
-#define SPI_MEM_DIN3_NUM_M  (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S)
-#define SPI_MEM_DIN3_NUM_V  0x00000003U
-#define SPI_MEM_DIN3_NUM_S  6
-/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+#define SPI_MEM_S_DIN3_NUM    0x00000003U
+#define SPI_MEM_S_DIN3_NUM_M  (SPI_MEM_S_DIN3_NUM_V << SPI_MEM_S_DIN3_NUM_S)
+#define SPI_MEM_S_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN3_NUM_S  6
+/** SPI_MEM_S_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN4_NUM    0x00000003U
-#define SPI_MEM_DIN4_NUM_M  (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S)
-#define SPI_MEM_DIN4_NUM_V  0x00000003U
-#define SPI_MEM_DIN4_NUM_S  8
-/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+#define SPI_MEM_S_DIN4_NUM    0x00000003U
+#define SPI_MEM_S_DIN4_NUM_M  (SPI_MEM_S_DIN4_NUM_V << SPI_MEM_S_DIN4_NUM_S)
+#define SPI_MEM_S_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN4_NUM_S  8
+/** SPI_MEM_S_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN5_NUM    0x00000003U
-#define SPI_MEM_DIN5_NUM_M  (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S)
-#define SPI_MEM_DIN5_NUM_V  0x00000003U
-#define SPI_MEM_DIN5_NUM_S  10
-/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+#define SPI_MEM_S_DIN5_NUM    0x00000003U
+#define SPI_MEM_S_DIN5_NUM_M  (SPI_MEM_S_DIN5_NUM_V << SPI_MEM_S_DIN5_NUM_S)
+#define SPI_MEM_S_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN5_NUM_S  10
+/** SPI_MEM_S_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN6_NUM    0x00000003U
-#define SPI_MEM_DIN6_NUM_M  (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S)
-#define SPI_MEM_DIN6_NUM_V  0x00000003U
-#define SPI_MEM_DIN6_NUM_S  12
-/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+#define SPI_MEM_S_DIN6_NUM    0x00000003U
+#define SPI_MEM_S_DIN6_NUM_M  (SPI_MEM_S_DIN6_NUM_V << SPI_MEM_S_DIN6_NUM_S)
+#define SPI_MEM_S_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN6_NUM_S  12
+/** SPI_MEM_S_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DIN7_NUM    0x00000003U
-#define SPI_MEM_DIN7_NUM_M  (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S)
-#define SPI_MEM_DIN7_NUM_V  0x00000003U
-#define SPI_MEM_DIN7_NUM_S  14
-/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
+#define SPI_MEM_S_DIN7_NUM    0x00000003U
+#define SPI_MEM_S_DIN7_NUM_M  (SPI_MEM_S_DIN7_NUM_V << SPI_MEM_S_DIN7_NUM_S)
+#define SPI_MEM_S_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN7_NUM_S  14
+/** SPI_MEM_S_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_MEM_DINS_NUM    0x00000003U
-#define SPI_MEM_DINS_NUM_M  (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S)
-#define SPI_MEM_DINS_NUM_V  0x00000003U
-#define SPI_MEM_DINS_NUM_S  16
+#define SPI_MEM_S_DINS_NUM    0x00000003U
+#define SPI_MEM_S_DINS_NUM_M  (SPI_MEM_S_DINS_NUM_V << SPI_MEM_S_DINS_NUM_S)
+#define SPI_MEM_S_DINS_NUM_V  0x00000003U
+#define SPI_MEM_S_DINS_NUM_S  16
 
-/** SPI_MEM_DOUT_MODE_REG register
+/** SPI_MEM_S_DOUT_MODE_REG register
  *  MSPI flash output timing adjustment control register
  */
-#define SPI_MEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18c)
-/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18c)
+/** SPI_MEM_S_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S)
-#define SPI_MEM_DOUT0_MODE_V  0x00000001U
-#define SPI_MEM_DOUT0_MODE_S  0
-/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_S_DOUT0_MODE_M  (SPI_MEM_S_DOUT0_MODE_V << SPI_MEM_S_DOUT0_MODE_S)
+#define SPI_MEM_S_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT0_MODE_S  0
+/** SPI_MEM_S_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S)
-#define SPI_MEM_DOUT1_MODE_V  0x00000001U
-#define SPI_MEM_DOUT1_MODE_S  1
-/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_S_DOUT1_MODE_M  (SPI_MEM_S_DOUT1_MODE_V << SPI_MEM_S_DOUT1_MODE_S)
+#define SPI_MEM_S_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT1_MODE_S  1
+/** SPI_MEM_S_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S)
-#define SPI_MEM_DOUT2_MODE_V  0x00000001U
-#define SPI_MEM_DOUT2_MODE_S  2
-/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+#define SPI_MEM_S_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_S_DOUT2_MODE_M  (SPI_MEM_S_DOUT2_MODE_V << SPI_MEM_S_DOUT2_MODE_S)
+#define SPI_MEM_S_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT2_MODE_S  2
+/** SPI_MEM_S_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S)
-#define SPI_MEM_DOUT3_MODE_V  0x00000001U
-#define SPI_MEM_DOUT3_MODE_S  3
-/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_S_DOUT3_MODE_M  (SPI_MEM_S_DOUT3_MODE_V << SPI_MEM_S_DOUT3_MODE_S)
+#define SPI_MEM_S_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT3_MODE_S  3
+/** SPI_MEM_S_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_DOUT4_MODE_M  (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S)
-#define SPI_MEM_DOUT4_MODE_V  0x00000001U
-#define SPI_MEM_DOUT4_MODE_S  4
-/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_S_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_S_DOUT4_MODE_M  (SPI_MEM_S_DOUT4_MODE_V << SPI_MEM_S_DOUT4_MODE_S)
+#define SPI_MEM_S_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT4_MODE_S  4
+/** SPI_MEM_S_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_DOUT5_MODE_M  (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S)
-#define SPI_MEM_DOUT5_MODE_V  0x00000001U
-#define SPI_MEM_DOUT5_MODE_S  5
-/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_S_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_S_DOUT5_MODE_M  (SPI_MEM_S_DOUT5_MODE_V << SPI_MEM_S_DOUT5_MODE_S)
+#define SPI_MEM_S_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT5_MODE_S  5
+/** SPI_MEM_S_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_DOUT6_MODE_M  (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S)
-#define SPI_MEM_DOUT6_MODE_V  0x00000001U
-#define SPI_MEM_DOUT6_MODE_S  6
-/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_S_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_S_DOUT6_MODE_M  (SPI_MEM_S_DOUT6_MODE_V << SPI_MEM_S_DOUT6_MODE_S)
+#define SPI_MEM_S_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT6_MODE_S  6
+/** SPI_MEM_S_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_DOUT7_MODE_M  (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S)
-#define SPI_MEM_DOUT7_MODE_V  0x00000001U
-#define SPI_MEM_DOUT7_MODE_S  7
-/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_S_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_S_DOUT7_MODE_M  (SPI_MEM_S_DOUT7_MODE_V << SPI_MEM_S_DOUT7_MODE_S)
+#define SPI_MEM_S_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT7_MODE_S  7
+/** SPI_MEM_S_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the spi_clk
  */
-#define SPI_MEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_DOUTS_MODE_M  (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S)
-#define SPI_MEM_DOUTS_MODE_V  0x00000001U
-#define SPI_MEM_DOUTS_MODE_S  8
+#define SPI_MEM_S_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_S_DOUTS_MODE_M  (SPI_MEM_S_DOUTS_MODE_V << SPI_MEM_S_DOUTS_MODE_S)
+#define SPI_MEM_S_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUTS_MODE_S  8
 
-/** SPI_SMEM_TIMING_CALI_REG register
+/** SPI_MEM_S_SMEM_TIMING_CALI_REG register
  *  MSPI external RAM timing calibration register
  */
-#define SPI_SMEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x190)
-/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
+#define SPI_MEM_S_SMEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x190)
+/** SPI_MEM_S_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
  *  For sram, the bit is used to enable timing adjust clock for all reading operations.
  */
-#define SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_SMEM_TIMING_CLK_ENA_M  (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S)
-#define SPI_SMEM_TIMING_CLK_ENA_V  0x00000001U
-#define SPI_SMEM_TIMING_CLK_ENA_S  0
-/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_M  (SPI_MEM_S_SMEM_TIMING_CLK_ENA_V << SPI_MEM_S_SMEM_TIMING_CLK_ENA_S)
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_S  0
+/** SPI_MEM_S_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  For sram, the bit is used to enable timing auto-calibration for all reading
  *  operations.
  */
-#define SPI_SMEM_TIMING_CALI    (BIT(1))
-#define SPI_SMEM_TIMING_CALI_M  (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S)
-#define SPI_SMEM_TIMING_CALI_V  0x00000001U
-#define SPI_SMEM_TIMING_CALI_S  1
-/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+#define SPI_MEM_S_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_S_SMEM_TIMING_CALI_M  (SPI_MEM_S_SMEM_TIMING_CALI_V << SPI_MEM_S_SMEM_TIMING_CALI_S)
+#define SPI_MEM_S_SMEM_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_SMEM_TIMING_CALI_S  1
+/** SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
  *  For sram, add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_S_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0;
  *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
  *  EXT_RAM.
  */
-#define SPI_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_SMEM_DLL_TIMING_CALI_M  (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S)
-#define SPI_SMEM_DLL_TIMING_CALI_V  0x00000001U
-#define SPI_SMEM_DLL_TIMING_CALI_S  5
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_M  (SPI_MEM_S_SMEM_DLL_TIMING_CALI_V << SPI_MEM_S_SMEM_DLL_TIMING_CALI_S)
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_S  5
 
-/** SPI_SMEM_DIN_MODE_REG register
+/** SPI_MEM_S_SMEM_DIN_MODE_REG register
  *  MSPI external RAM input timing delay mode control register
  */
-#define SPI_SMEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x194)
-/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
+#define SPI_MEM_S_SMEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x194)
+/** SPI_MEM_S_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN0_MODE    0x00000007U
-#define SPI_SMEM_DIN0_MODE_M  (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S)
-#define SPI_SMEM_DIN0_MODE_V  0x00000007U
-#define SPI_SMEM_DIN0_MODE_S  0
-/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
+#define SPI_MEM_S_SMEM_DIN0_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN0_MODE_M  (SPI_MEM_S_SMEM_DIN0_MODE_V << SPI_MEM_S_SMEM_DIN0_MODE_S)
+#define SPI_MEM_S_SMEM_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN0_MODE_S  0
+/** SPI_MEM_S_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN1_MODE    0x00000007U
-#define SPI_SMEM_DIN1_MODE_M  (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S)
-#define SPI_SMEM_DIN1_MODE_V  0x00000007U
-#define SPI_SMEM_DIN1_MODE_S  3
-/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
+#define SPI_MEM_S_SMEM_DIN1_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN1_MODE_M  (SPI_MEM_S_SMEM_DIN1_MODE_V << SPI_MEM_S_SMEM_DIN1_MODE_S)
+#define SPI_MEM_S_SMEM_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN1_MODE_S  3
+/** SPI_MEM_S_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN2_MODE    0x00000007U
-#define SPI_SMEM_DIN2_MODE_M  (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S)
-#define SPI_SMEM_DIN2_MODE_V  0x00000007U
-#define SPI_SMEM_DIN2_MODE_S  6
-/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
+#define SPI_MEM_S_SMEM_DIN2_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN2_MODE_M  (SPI_MEM_S_SMEM_DIN2_MODE_V << SPI_MEM_S_SMEM_DIN2_MODE_S)
+#define SPI_MEM_S_SMEM_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN2_MODE_S  6
+/** SPI_MEM_S_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN3_MODE    0x00000007U
-#define SPI_SMEM_DIN3_MODE_M  (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S)
-#define SPI_SMEM_DIN3_MODE_V  0x00000007U
-#define SPI_SMEM_DIN3_MODE_S  9
-/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
+#define SPI_MEM_S_SMEM_DIN3_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN3_MODE_M  (SPI_MEM_S_SMEM_DIN3_MODE_V << SPI_MEM_S_SMEM_DIN3_MODE_S)
+#define SPI_MEM_S_SMEM_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN3_MODE_S  9
+/** SPI_MEM_S_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN4_MODE    0x00000007U
-#define SPI_SMEM_DIN4_MODE_M  (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S)
-#define SPI_SMEM_DIN4_MODE_V  0x00000007U
-#define SPI_SMEM_DIN4_MODE_S  12
-/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
+#define SPI_MEM_S_SMEM_DIN4_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN4_MODE_M  (SPI_MEM_S_SMEM_DIN4_MODE_V << SPI_MEM_S_SMEM_DIN4_MODE_S)
+#define SPI_MEM_S_SMEM_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN4_MODE_S  12
+/** SPI_MEM_S_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN5_MODE    0x00000007U
-#define SPI_SMEM_DIN5_MODE_M  (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S)
-#define SPI_SMEM_DIN5_MODE_V  0x00000007U
-#define SPI_SMEM_DIN5_MODE_S  15
-/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
+#define SPI_MEM_S_SMEM_DIN5_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN5_MODE_M  (SPI_MEM_S_SMEM_DIN5_MODE_V << SPI_MEM_S_SMEM_DIN5_MODE_S)
+#define SPI_MEM_S_SMEM_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN5_MODE_S  15
+/** SPI_MEM_S_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN6_MODE    0x00000007U
-#define SPI_SMEM_DIN6_MODE_M  (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S)
-#define SPI_SMEM_DIN6_MODE_V  0x00000007U
-#define SPI_SMEM_DIN6_MODE_S  18
-/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
+#define SPI_MEM_S_SMEM_DIN6_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN6_MODE_M  (SPI_MEM_S_SMEM_DIN6_MODE_V << SPI_MEM_S_SMEM_DIN6_MODE_S)
+#define SPI_MEM_S_SMEM_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN6_MODE_S  18
+/** SPI_MEM_S_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN7_MODE    0x00000007U
-#define SPI_SMEM_DIN7_MODE_M  (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S)
-#define SPI_SMEM_DIN7_MODE_V  0x00000007U
-#define SPI_SMEM_DIN7_MODE_S  21
-/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
+#define SPI_MEM_S_SMEM_DIN7_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN7_MODE_M  (SPI_MEM_S_SMEM_DIN7_MODE_V << SPI_MEM_S_SMEM_DIN7_MODE_S)
+#define SPI_MEM_S_SMEM_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN7_MODE_S  21
+/** SPI_MEM_S_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DINS_MODE    0x00000007U
-#define SPI_SMEM_DINS_MODE_M  (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S)
-#define SPI_SMEM_DINS_MODE_V  0x00000007U
-#define SPI_SMEM_DINS_MODE_S  24
+#define SPI_MEM_S_SMEM_DINS_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DINS_MODE_M  (SPI_MEM_S_SMEM_DINS_MODE_V << SPI_MEM_S_SMEM_DINS_MODE_S)
+#define SPI_MEM_S_SMEM_DINS_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DINS_MODE_S  24
 
-/** SPI_SMEM_DIN_NUM_REG register
+/** SPI_MEM_S_SMEM_DIN_NUM_REG register
  *  MSPI external RAM input timing delay number control register
  */
-#define SPI_SMEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x198)
-/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_S_SMEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x198)
+/** SPI_MEM_S_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN0_NUM    0x00000003U
-#define SPI_SMEM_DIN0_NUM_M  (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S)
-#define SPI_SMEM_DIN0_NUM_V  0x00000003U
-#define SPI_SMEM_DIN0_NUM_S  0
-/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+#define SPI_MEM_S_SMEM_DIN0_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN0_NUM_M  (SPI_MEM_S_SMEM_DIN0_NUM_V << SPI_MEM_S_SMEM_DIN0_NUM_S)
+#define SPI_MEM_S_SMEM_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN0_NUM_S  0
+/** SPI_MEM_S_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN1_NUM    0x00000003U
-#define SPI_SMEM_DIN1_NUM_M  (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S)
-#define SPI_SMEM_DIN1_NUM_V  0x00000003U
-#define SPI_SMEM_DIN1_NUM_S  2
-/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+#define SPI_MEM_S_SMEM_DIN1_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN1_NUM_M  (SPI_MEM_S_SMEM_DIN1_NUM_V << SPI_MEM_S_SMEM_DIN1_NUM_S)
+#define SPI_MEM_S_SMEM_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN1_NUM_S  2
+/** SPI_MEM_S_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN2_NUM    0x00000003U
-#define SPI_SMEM_DIN2_NUM_M  (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S)
-#define SPI_SMEM_DIN2_NUM_V  0x00000003U
-#define SPI_SMEM_DIN2_NUM_S  4
-/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+#define SPI_MEM_S_SMEM_DIN2_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN2_NUM_M  (SPI_MEM_S_SMEM_DIN2_NUM_V << SPI_MEM_S_SMEM_DIN2_NUM_S)
+#define SPI_MEM_S_SMEM_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN2_NUM_S  4
+/** SPI_MEM_S_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN3_NUM    0x00000003U
-#define SPI_SMEM_DIN3_NUM_M  (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S)
-#define SPI_SMEM_DIN3_NUM_V  0x00000003U
-#define SPI_SMEM_DIN3_NUM_S  6
-/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+#define SPI_MEM_S_SMEM_DIN3_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN3_NUM_M  (SPI_MEM_S_SMEM_DIN3_NUM_V << SPI_MEM_S_SMEM_DIN3_NUM_S)
+#define SPI_MEM_S_SMEM_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN3_NUM_S  6
+/** SPI_MEM_S_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN4_NUM    0x00000003U
-#define SPI_SMEM_DIN4_NUM_M  (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S)
-#define SPI_SMEM_DIN4_NUM_V  0x00000003U
-#define SPI_SMEM_DIN4_NUM_S  8
-/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+#define SPI_MEM_S_SMEM_DIN4_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN4_NUM_M  (SPI_MEM_S_SMEM_DIN4_NUM_V << SPI_MEM_S_SMEM_DIN4_NUM_S)
+#define SPI_MEM_S_SMEM_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN4_NUM_S  8
+/** SPI_MEM_S_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN5_NUM    0x00000003U
-#define SPI_SMEM_DIN5_NUM_M  (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S)
-#define SPI_SMEM_DIN5_NUM_V  0x00000003U
-#define SPI_SMEM_DIN5_NUM_S  10
-/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+#define SPI_MEM_S_SMEM_DIN5_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN5_NUM_M  (SPI_MEM_S_SMEM_DIN5_NUM_V << SPI_MEM_S_SMEM_DIN5_NUM_S)
+#define SPI_MEM_S_SMEM_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN5_NUM_S  10
+/** SPI_MEM_S_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN6_NUM    0x00000003U
-#define SPI_SMEM_DIN6_NUM_M  (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S)
-#define SPI_SMEM_DIN6_NUM_V  0x00000003U
-#define SPI_SMEM_DIN6_NUM_S  12
-/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+#define SPI_MEM_S_SMEM_DIN6_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN6_NUM_M  (SPI_MEM_S_SMEM_DIN6_NUM_V << SPI_MEM_S_SMEM_DIN6_NUM_S)
+#define SPI_MEM_S_SMEM_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN6_NUM_S  12
+/** SPI_MEM_S_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN7_NUM    0x00000003U
-#define SPI_SMEM_DIN7_NUM_M  (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S)
-#define SPI_SMEM_DIN7_NUM_V  0x00000003U
-#define SPI_SMEM_DIN7_NUM_S  14
-/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
+#define SPI_MEM_S_SMEM_DIN7_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN7_NUM_M  (SPI_MEM_S_SMEM_DIN7_NUM_V << SPI_MEM_S_SMEM_DIN7_NUM_S)
+#define SPI_MEM_S_SMEM_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN7_NUM_S  14
+/** SPI_MEM_S_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DINS_NUM    0x00000003U
-#define SPI_SMEM_DINS_NUM_M  (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S)
-#define SPI_SMEM_DINS_NUM_V  0x00000003U
-#define SPI_SMEM_DINS_NUM_S  16
+#define SPI_MEM_S_SMEM_DINS_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DINS_NUM_M  (SPI_MEM_S_SMEM_DINS_NUM_V << SPI_MEM_S_SMEM_DINS_NUM_S)
+#define SPI_MEM_S_SMEM_DINS_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DINS_NUM_S  16
 
-/** SPI_SMEM_DOUT_MODE_REG register
+/** SPI_MEM_S_SMEM_DOUT_MODE_REG register
  *  MSPI external RAM output timing adjustment control register
  */
-#define SPI_SMEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x19c)
-/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x19c)
+/** SPI_MEM_S_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT0_MODE    (BIT(0))
-#define SPI_SMEM_DOUT0_MODE_M  (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S)
-#define SPI_SMEM_DOUT0_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT0_MODE_S  0
-/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_S_SMEM_DOUT0_MODE_M  (SPI_MEM_S_SMEM_DOUT0_MODE_V << SPI_MEM_S_SMEM_DOUT0_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT0_MODE_S  0
+/** SPI_MEM_S_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT1_MODE    (BIT(1))
-#define SPI_SMEM_DOUT1_MODE_M  (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S)
-#define SPI_SMEM_DOUT1_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT1_MODE_S  1
-/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_S_SMEM_DOUT1_MODE_M  (SPI_MEM_S_SMEM_DOUT1_MODE_V << SPI_MEM_S_SMEM_DOUT1_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT1_MODE_S  1
+/** SPI_MEM_S_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT2_MODE    (BIT(2))
-#define SPI_SMEM_DOUT2_MODE_M  (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S)
-#define SPI_SMEM_DOUT2_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT2_MODE_S  2
-/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_S_SMEM_DOUT2_MODE_M  (SPI_MEM_S_SMEM_DOUT2_MODE_V << SPI_MEM_S_SMEM_DOUT2_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT2_MODE_S  2
+/** SPI_MEM_S_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT3_MODE    (BIT(3))
-#define SPI_SMEM_DOUT3_MODE_M  (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S)
-#define SPI_SMEM_DOUT3_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT3_MODE_S  3
-/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_S_SMEM_DOUT3_MODE_M  (SPI_MEM_S_SMEM_DOUT3_MODE_V << SPI_MEM_S_SMEM_DOUT3_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT3_MODE_S  3
+/** SPI_MEM_S_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT4_MODE    (BIT(4))
-#define SPI_SMEM_DOUT4_MODE_M  (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S)
-#define SPI_SMEM_DOUT4_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT4_MODE_S  4
-/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_S_SMEM_DOUT4_MODE_M  (SPI_MEM_S_SMEM_DOUT4_MODE_V << SPI_MEM_S_SMEM_DOUT4_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT4_MODE_S  4
+/** SPI_MEM_S_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT5_MODE    (BIT(5))
-#define SPI_SMEM_DOUT5_MODE_M  (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S)
-#define SPI_SMEM_DOUT5_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT5_MODE_S  5
-/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_S_SMEM_DOUT5_MODE_M  (SPI_MEM_S_SMEM_DOUT5_MODE_V << SPI_MEM_S_SMEM_DOUT5_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT5_MODE_S  5
+/** SPI_MEM_S_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT6_MODE    (BIT(6))
-#define SPI_SMEM_DOUT6_MODE_M  (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S)
-#define SPI_SMEM_DOUT6_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT6_MODE_S  6
-/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_S_SMEM_DOUT6_MODE_M  (SPI_MEM_S_SMEM_DOUT6_MODE_V << SPI_MEM_S_SMEM_DOUT6_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT6_MODE_S  6
+/** SPI_MEM_S_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT7_MODE    (BIT(7))
-#define SPI_SMEM_DOUT7_MODE_M  (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S)
-#define SPI_SMEM_DOUT7_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT7_MODE_S  7
-/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_S_SMEM_DOUT7_MODE_M  (SPI_MEM_S_SMEM_DOUT7_MODE_V << SPI_MEM_S_SMEM_DOUT7_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT7_MODE_S  7
+/** SPI_MEM_S_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUTS_MODE    (BIT(8))
-#define SPI_SMEM_DOUTS_MODE_M  (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S)
-#define SPI_SMEM_DOUTS_MODE_V  0x00000001U
-#define SPI_SMEM_DOUTS_MODE_S  8
+#define SPI_MEM_S_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_S_SMEM_DOUTS_MODE_M  (SPI_MEM_S_SMEM_DOUTS_MODE_V << SPI_MEM_S_SMEM_DOUTS_MODE_S)
+#define SPI_MEM_S_SMEM_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUTS_MODE_S  8
 
-/** SPI_SMEM_AC_REG register
+/** SPI_MEM_S_SMEM_AC_REG register
  *  MSPI external RAM ECC and SPI CS timing control register
  */
-#define SPI_SMEM_AC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a0)
-/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_SMEM_AC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a0)
+/** SPI_MEM_S_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0;
  *  For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
  *  disable.
  */
-#define SPI_SMEM_CS_SETUP    (BIT(0))
-#define SPI_SMEM_CS_SETUP_M  (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S)
-#define SPI_SMEM_CS_SETUP_V  0x00000001U
-#define SPI_SMEM_CS_SETUP_S  0
-/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_S_SMEM_CS_SETUP_M  (SPI_MEM_S_SMEM_CS_SETUP_V << SPI_MEM_S_SMEM_CS_SETUP_S)
+#define SPI_MEM_S_SMEM_CS_SETUP_V  0x00000001U
+#define SPI_MEM_S_SMEM_CS_SETUP_S  0
+/** SPI_MEM_S_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0;
  *  For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.
  */
-#define SPI_SMEM_CS_HOLD    (BIT(1))
-#define SPI_SMEM_CS_HOLD_M  (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S)
-#define SPI_SMEM_CS_HOLD_V  0x00000001U
-#define SPI_SMEM_CS_HOLD_S  1
-/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1;
+#define SPI_MEM_S_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_S_SMEM_CS_HOLD_M  (SPI_MEM_S_SMEM_CS_HOLD_V << SPI_MEM_S_SMEM_CS_HOLD_S)
+#define SPI_MEM_S_SMEM_CS_HOLD_V  0x00000001U
+#define SPI_MEM_S_SMEM_CS_HOLD_S  1
+/** SPI_MEM_S_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1;
  *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
- *  spi_mem_cs_setup bit.
+ *  SPI_MEM_S_cs_setup bit.
  */
-#define SPI_SMEM_CS_SETUP_TIME    0x0000001FU
-#define SPI_SMEM_CS_SETUP_TIME_M  (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S)
-#define SPI_SMEM_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_SMEM_CS_SETUP_TIME_S  2
-/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1;
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME_M  (SPI_MEM_S_SMEM_CS_SETUP_TIME_V << SPI_MEM_S_SMEM_CS_SETUP_TIME_S)
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME_S  2
+/** SPI_MEM_S_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1;
  *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
- *  combined with spi_mem_cs_hold bit.
+ *  combined with SPI_MEM_S_cs_hold bit.
  */
-#define SPI_SMEM_CS_HOLD_TIME    0x0000001FU
-#define SPI_SMEM_CS_HOLD_TIME_M  (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S)
-#define SPI_SMEM_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_SMEM_CS_HOLD_TIME_S  7
-/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3;
- *  SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME_M  (SPI_MEM_S_SMEM_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_CS_HOLD_TIME_S)
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME_S  7
+/** SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3;
+ *  SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
  *  cycles in ECC mode when accessed external RAM.
  */
-#define SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007U
-#define SPI_SMEM_ECC_CS_HOLD_TIME_M  (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S)
-#define SPI_SMEM_ECC_CS_HOLD_TIME_V  0x00000007U
-#define SPI_SMEM_ECC_CS_HOLD_TIME_S  12
-/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1;
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_M  (SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S  12
+/** SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1;
  *  1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when
  *  accesses external RAM.
  */
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S)
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0;
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/** SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0;
  *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
  *  accesses external RAM.
  */
-#define SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_M  (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S)
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x00000001U
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
-/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_M  (SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S  16
+/** SPI_MEM_S_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
  *  These bits are used to set the minimum CS high time tSHSL between SPI burst
- *  transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1)
+ *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1)
  *  MSPI core clock cycles.
  */
-#define SPI_SMEM_CS_HOLD_DELAY    0x0000003FU
-#define SPI_SMEM_CS_HOLD_DELAY_M  (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S)
-#define SPI_SMEM_CS_HOLD_DELAY_V  0x0000003FU
-#define SPI_SMEM_CS_HOLD_DELAY_S  25
-/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 1;
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_M  (SPI_MEM_S_SMEM_CS_HOLD_DELAY_V << SPI_MEM_S_SMEM_CS_HOLD_DELAY_S)
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_S  25
+/** SPI_MEM_S_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 1;
  *  Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
  *  transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter
  *  whether there is an ECC region or not.
  */
-#define SPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define SPI_SMEM_SPLIT_TRANS_EN_M  (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S)
-#define SPI_SMEM_SPLIT_TRANS_EN_V  0x00000001U
-#define SPI_SMEM_SPLIT_TRANS_EN_S  31
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_M  (SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V << SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S)
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S  31
 
-/** SPI_SMEM_DIN_HEX_MODE_REG register
+/** SPI_MEM_S_SMEM_DIN_HEX_MODE_REG register
  *  MSPI 16x external RAM input timing delay mode control register
  */
-#define SPI_SMEM_DIN_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a4)
-/** SPI_SMEM_DIN08_MODE : R/W; bitpos: [2:0]; default: 0;
+#define SPI_MEM_S_SMEM_DIN_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a4)
+/** SPI_MEM_S_SMEM_DIN08_MODE : R/W; bitpos: [2:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN08_MODE    0x00000007U
-#define SPI_SMEM_DIN08_MODE_M  (SPI_SMEM_DIN08_MODE_V << SPI_SMEM_DIN08_MODE_S)
-#define SPI_SMEM_DIN08_MODE_V  0x00000007U
-#define SPI_SMEM_DIN08_MODE_S  0
-/** SPI_SMEM_DIN09_MODE : R/W; bitpos: [5:3]; default: 0;
+#define SPI_MEM_S_SMEM_DIN08_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN08_MODE_M  (SPI_MEM_S_SMEM_DIN08_MODE_V << SPI_MEM_S_SMEM_DIN08_MODE_S)
+#define SPI_MEM_S_SMEM_DIN08_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN08_MODE_S  0
+/** SPI_MEM_S_SMEM_DIN09_MODE : R/W; bitpos: [5:3]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN09_MODE    0x00000007U
-#define SPI_SMEM_DIN09_MODE_M  (SPI_SMEM_DIN09_MODE_V << SPI_SMEM_DIN09_MODE_S)
-#define SPI_SMEM_DIN09_MODE_V  0x00000007U
-#define SPI_SMEM_DIN09_MODE_S  3
-/** SPI_SMEM_DIN10_MODE : R/W; bitpos: [8:6]; default: 0;
+#define SPI_MEM_S_SMEM_DIN09_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN09_MODE_M  (SPI_MEM_S_SMEM_DIN09_MODE_V << SPI_MEM_S_SMEM_DIN09_MODE_S)
+#define SPI_MEM_S_SMEM_DIN09_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN09_MODE_S  3
+/** SPI_MEM_S_SMEM_DIN10_MODE : R/W; bitpos: [8:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN10_MODE    0x00000007U
-#define SPI_SMEM_DIN10_MODE_M  (SPI_SMEM_DIN10_MODE_V << SPI_SMEM_DIN10_MODE_S)
-#define SPI_SMEM_DIN10_MODE_V  0x00000007U
-#define SPI_SMEM_DIN10_MODE_S  6
-/** SPI_SMEM_DIN11_MODE : R/W; bitpos: [11:9]; default: 0;
+#define SPI_MEM_S_SMEM_DIN10_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN10_MODE_M  (SPI_MEM_S_SMEM_DIN10_MODE_V << SPI_MEM_S_SMEM_DIN10_MODE_S)
+#define SPI_MEM_S_SMEM_DIN10_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN10_MODE_S  6
+/** SPI_MEM_S_SMEM_DIN11_MODE : R/W; bitpos: [11:9]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN11_MODE    0x00000007U
-#define SPI_SMEM_DIN11_MODE_M  (SPI_SMEM_DIN11_MODE_V << SPI_SMEM_DIN11_MODE_S)
-#define SPI_SMEM_DIN11_MODE_V  0x00000007U
-#define SPI_SMEM_DIN11_MODE_S  9
-/** SPI_SMEM_DIN12_MODE : R/W; bitpos: [14:12]; default: 0;
+#define SPI_MEM_S_SMEM_DIN11_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN11_MODE_M  (SPI_MEM_S_SMEM_DIN11_MODE_V << SPI_MEM_S_SMEM_DIN11_MODE_S)
+#define SPI_MEM_S_SMEM_DIN11_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN11_MODE_S  9
+/** SPI_MEM_S_SMEM_DIN12_MODE : R/W; bitpos: [14:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN12_MODE    0x00000007U
-#define SPI_SMEM_DIN12_MODE_M  (SPI_SMEM_DIN12_MODE_V << SPI_SMEM_DIN12_MODE_S)
-#define SPI_SMEM_DIN12_MODE_V  0x00000007U
-#define SPI_SMEM_DIN12_MODE_S  12
-/** SPI_SMEM_DIN13_MODE : R/W; bitpos: [17:15]; default: 0;
+#define SPI_MEM_S_SMEM_DIN12_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN12_MODE_M  (SPI_MEM_S_SMEM_DIN12_MODE_V << SPI_MEM_S_SMEM_DIN12_MODE_S)
+#define SPI_MEM_S_SMEM_DIN12_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN12_MODE_S  12
+/** SPI_MEM_S_SMEM_DIN13_MODE : R/W; bitpos: [17:15]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN13_MODE    0x00000007U
-#define SPI_SMEM_DIN13_MODE_M  (SPI_SMEM_DIN13_MODE_V << SPI_SMEM_DIN13_MODE_S)
-#define SPI_SMEM_DIN13_MODE_V  0x00000007U
-#define SPI_SMEM_DIN13_MODE_S  15
-/** SPI_SMEM_DIN14_MODE : R/W; bitpos: [20:18]; default: 0;
+#define SPI_MEM_S_SMEM_DIN13_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN13_MODE_M  (SPI_MEM_S_SMEM_DIN13_MODE_V << SPI_MEM_S_SMEM_DIN13_MODE_S)
+#define SPI_MEM_S_SMEM_DIN13_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN13_MODE_S  15
+/** SPI_MEM_S_SMEM_DIN14_MODE : R/W; bitpos: [20:18]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN14_MODE    0x00000007U
-#define SPI_SMEM_DIN14_MODE_M  (SPI_SMEM_DIN14_MODE_V << SPI_SMEM_DIN14_MODE_S)
-#define SPI_SMEM_DIN14_MODE_V  0x00000007U
-#define SPI_SMEM_DIN14_MODE_S  18
-/** SPI_SMEM_DIN15_MODE : R/W; bitpos: [23:21]; default: 0;
+#define SPI_MEM_S_SMEM_DIN14_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN14_MODE_M  (SPI_MEM_S_SMEM_DIN14_MODE_V << SPI_MEM_S_SMEM_DIN14_MODE_S)
+#define SPI_MEM_S_SMEM_DIN14_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN14_MODE_S  18
+/** SPI_MEM_S_SMEM_DIN15_MODE : R/W; bitpos: [23:21]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DIN15_MODE    0x00000007U
-#define SPI_SMEM_DIN15_MODE_M  (SPI_SMEM_DIN15_MODE_V << SPI_SMEM_DIN15_MODE_S)
-#define SPI_SMEM_DIN15_MODE_V  0x00000007U
-#define SPI_SMEM_DIN15_MODE_S  21
-/** SPI_SMEM_DINS_HEX_MODE : R/W; bitpos: [26:24]; default: 0;
+#define SPI_MEM_S_SMEM_DIN15_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN15_MODE_M  (SPI_MEM_S_SMEM_DIN15_MODE_V << SPI_MEM_S_SMEM_DIN15_MODE_S)
+#define SPI_MEM_S_SMEM_DIN15_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN15_MODE_S  21
+/** SPI_MEM_S_SMEM_DINS_HEX_MODE : R/W; bitpos: [26:24]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
  *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
  *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
  *  spi_clk high edge,  6: input with the spi_clk low edge
  */
-#define SPI_SMEM_DINS_HEX_MODE    0x00000007U
-#define SPI_SMEM_DINS_HEX_MODE_M  (SPI_SMEM_DINS_HEX_MODE_V << SPI_SMEM_DINS_HEX_MODE_S)
-#define SPI_SMEM_DINS_HEX_MODE_V  0x00000007U
-#define SPI_SMEM_DINS_HEX_MODE_S  24
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE_M  (SPI_MEM_S_SMEM_DINS_HEX_MODE_V << SPI_MEM_S_SMEM_DINS_HEX_MODE_S)
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE_S  24
 
-/** SPI_SMEM_DIN_HEX_NUM_REG register
+/** SPI_MEM_S_SMEM_DIN_HEX_NUM_REG register
  *  MSPI 16x external RAM input timing delay number control register
  */
-#define SPI_SMEM_DIN_HEX_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a8)
-/** SPI_SMEM_DIN08_NUM : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_S_SMEM_DIN_HEX_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a8)
+/** SPI_MEM_S_SMEM_DIN08_NUM : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN08_NUM    0x00000003U
-#define SPI_SMEM_DIN08_NUM_M  (SPI_SMEM_DIN08_NUM_V << SPI_SMEM_DIN08_NUM_S)
-#define SPI_SMEM_DIN08_NUM_V  0x00000003U
-#define SPI_SMEM_DIN08_NUM_S  0
-/** SPI_SMEM_DIN09_NUM : R/W; bitpos: [3:2]; default: 0;
+#define SPI_MEM_S_SMEM_DIN08_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN08_NUM_M  (SPI_MEM_S_SMEM_DIN08_NUM_V << SPI_MEM_S_SMEM_DIN08_NUM_S)
+#define SPI_MEM_S_SMEM_DIN08_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN08_NUM_S  0
+/** SPI_MEM_S_SMEM_DIN09_NUM : R/W; bitpos: [3:2]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN09_NUM    0x00000003U
-#define SPI_SMEM_DIN09_NUM_M  (SPI_SMEM_DIN09_NUM_V << SPI_SMEM_DIN09_NUM_S)
-#define SPI_SMEM_DIN09_NUM_V  0x00000003U
-#define SPI_SMEM_DIN09_NUM_S  2
-/** SPI_SMEM_DIN10_NUM : R/W; bitpos: [5:4]; default: 0;
+#define SPI_MEM_S_SMEM_DIN09_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN09_NUM_M  (SPI_MEM_S_SMEM_DIN09_NUM_V << SPI_MEM_S_SMEM_DIN09_NUM_S)
+#define SPI_MEM_S_SMEM_DIN09_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN09_NUM_S  2
+/** SPI_MEM_S_SMEM_DIN10_NUM : R/W; bitpos: [5:4]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN10_NUM    0x00000003U
-#define SPI_SMEM_DIN10_NUM_M  (SPI_SMEM_DIN10_NUM_V << SPI_SMEM_DIN10_NUM_S)
-#define SPI_SMEM_DIN10_NUM_V  0x00000003U
-#define SPI_SMEM_DIN10_NUM_S  4
-/** SPI_SMEM_DIN11_NUM : R/W; bitpos: [7:6]; default: 0;
+#define SPI_MEM_S_SMEM_DIN10_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN10_NUM_M  (SPI_MEM_S_SMEM_DIN10_NUM_V << SPI_MEM_S_SMEM_DIN10_NUM_S)
+#define SPI_MEM_S_SMEM_DIN10_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN10_NUM_S  4
+/** SPI_MEM_S_SMEM_DIN11_NUM : R/W; bitpos: [7:6]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN11_NUM    0x00000003U
-#define SPI_SMEM_DIN11_NUM_M  (SPI_SMEM_DIN11_NUM_V << SPI_SMEM_DIN11_NUM_S)
-#define SPI_SMEM_DIN11_NUM_V  0x00000003U
-#define SPI_SMEM_DIN11_NUM_S  6
-/** SPI_SMEM_DIN12_NUM : R/W; bitpos: [9:8]; default: 0;
+#define SPI_MEM_S_SMEM_DIN11_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN11_NUM_M  (SPI_MEM_S_SMEM_DIN11_NUM_V << SPI_MEM_S_SMEM_DIN11_NUM_S)
+#define SPI_MEM_S_SMEM_DIN11_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN11_NUM_S  6
+/** SPI_MEM_S_SMEM_DIN12_NUM : R/W; bitpos: [9:8]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN12_NUM    0x00000003U
-#define SPI_SMEM_DIN12_NUM_M  (SPI_SMEM_DIN12_NUM_V << SPI_SMEM_DIN12_NUM_S)
-#define SPI_SMEM_DIN12_NUM_V  0x00000003U
-#define SPI_SMEM_DIN12_NUM_S  8
-/** SPI_SMEM_DIN13_NUM : R/W; bitpos: [11:10]; default: 0;
+#define SPI_MEM_S_SMEM_DIN12_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN12_NUM_M  (SPI_MEM_S_SMEM_DIN12_NUM_V << SPI_MEM_S_SMEM_DIN12_NUM_S)
+#define SPI_MEM_S_SMEM_DIN12_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN12_NUM_S  8
+/** SPI_MEM_S_SMEM_DIN13_NUM : R/W; bitpos: [11:10]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN13_NUM    0x00000003U
-#define SPI_SMEM_DIN13_NUM_M  (SPI_SMEM_DIN13_NUM_V << SPI_SMEM_DIN13_NUM_S)
-#define SPI_SMEM_DIN13_NUM_V  0x00000003U
-#define SPI_SMEM_DIN13_NUM_S  10
-/** SPI_SMEM_DIN14_NUM : R/W; bitpos: [13:12]; default: 0;
+#define SPI_MEM_S_SMEM_DIN13_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN13_NUM_M  (SPI_MEM_S_SMEM_DIN13_NUM_V << SPI_MEM_S_SMEM_DIN13_NUM_S)
+#define SPI_MEM_S_SMEM_DIN13_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN13_NUM_S  10
+/** SPI_MEM_S_SMEM_DIN14_NUM : R/W; bitpos: [13:12]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN14_NUM    0x00000003U
-#define SPI_SMEM_DIN14_NUM_M  (SPI_SMEM_DIN14_NUM_V << SPI_SMEM_DIN14_NUM_S)
-#define SPI_SMEM_DIN14_NUM_V  0x00000003U
-#define SPI_SMEM_DIN14_NUM_S  12
-/** SPI_SMEM_DIN15_NUM : R/W; bitpos: [15:14]; default: 0;
+#define SPI_MEM_S_SMEM_DIN14_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN14_NUM_M  (SPI_MEM_S_SMEM_DIN14_NUM_V << SPI_MEM_S_SMEM_DIN14_NUM_S)
+#define SPI_MEM_S_SMEM_DIN14_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN14_NUM_S  12
+/** SPI_MEM_S_SMEM_DIN15_NUM : R/W; bitpos: [15:14]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DIN15_NUM    0x00000003U
-#define SPI_SMEM_DIN15_NUM_M  (SPI_SMEM_DIN15_NUM_V << SPI_SMEM_DIN15_NUM_S)
-#define SPI_SMEM_DIN15_NUM_V  0x00000003U
-#define SPI_SMEM_DIN15_NUM_S  14
-/** SPI_SMEM_DINS_HEX_NUM : R/W; bitpos: [17:16]; default: 0;
+#define SPI_MEM_S_SMEM_DIN15_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN15_NUM_M  (SPI_MEM_S_SMEM_DIN15_NUM_V << SPI_MEM_S_SMEM_DIN15_NUM_S)
+#define SPI_MEM_S_SMEM_DIN15_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN15_NUM_S  14
+/** SPI_MEM_S_SMEM_DINS_HEX_NUM : R/W; bitpos: [17:16]; default: 0;
  *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...
  */
-#define SPI_SMEM_DINS_HEX_NUM    0x00000003U
-#define SPI_SMEM_DINS_HEX_NUM_M  (SPI_SMEM_DINS_HEX_NUM_V << SPI_SMEM_DINS_HEX_NUM_S)
-#define SPI_SMEM_DINS_HEX_NUM_V  0x00000003U
-#define SPI_SMEM_DINS_HEX_NUM_S  16
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM_M  (SPI_MEM_S_SMEM_DINS_HEX_NUM_V << SPI_MEM_S_SMEM_DINS_HEX_NUM_S)
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM_S  16
 
-/** SPI_SMEM_DOUT_HEX_MODE_REG register
+/** SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG register
  *  MSPI 16x external RAM output timing adjustment control register
  */
-#define SPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1ac)
-/** SPI_SMEM_DOUT08_MODE : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1ac)
+/** SPI_MEM_S_SMEM_DOUT08_MODE : R/W; bitpos: [0]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT08_MODE    (BIT(0))
-#define SPI_SMEM_DOUT08_MODE_M  (SPI_SMEM_DOUT08_MODE_V << SPI_SMEM_DOUT08_MODE_S)
-#define SPI_SMEM_DOUT08_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT08_MODE_S  0
-/** SPI_SMEM_DOUT09_MODE : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT08_MODE    (BIT(0))
+#define SPI_MEM_S_SMEM_DOUT08_MODE_M  (SPI_MEM_S_SMEM_DOUT08_MODE_V << SPI_MEM_S_SMEM_DOUT08_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT08_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT08_MODE_S  0
+/** SPI_MEM_S_SMEM_DOUT09_MODE : R/W; bitpos: [1]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT09_MODE    (BIT(1))
-#define SPI_SMEM_DOUT09_MODE_M  (SPI_SMEM_DOUT09_MODE_V << SPI_SMEM_DOUT09_MODE_S)
-#define SPI_SMEM_DOUT09_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT09_MODE_S  1
-/** SPI_SMEM_DOUT10_MODE : R/W; bitpos: [2]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT09_MODE    (BIT(1))
+#define SPI_MEM_S_SMEM_DOUT09_MODE_M  (SPI_MEM_S_SMEM_DOUT09_MODE_V << SPI_MEM_S_SMEM_DOUT09_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT09_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT09_MODE_S  1
+/** SPI_MEM_S_SMEM_DOUT10_MODE : R/W; bitpos: [2]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT10_MODE    (BIT(2))
-#define SPI_SMEM_DOUT10_MODE_M  (SPI_SMEM_DOUT10_MODE_V << SPI_SMEM_DOUT10_MODE_S)
-#define SPI_SMEM_DOUT10_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT10_MODE_S  2
-/** SPI_SMEM_DOUT11_MODE : R/W; bitpos: [3]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT10_MODE    (BIT(2))
+#define SPI_MEM_S_SMEM_DOUT10_MODE_M  (SPI_MEM_S_SMEM_DOUT10_MODE_V << SPI_MEM_S_SMEM_DOUT10_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT10_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT10_MODE_S  2
+/** SPI_MEM_S_SMEM_DOUT11_MODE : R/W; bitpos: [3]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT11_MODE    (BIT(3))
-#define SPI_SMEM_DOUT11_MODE_M  (SPI_SMEM_DOUT11_MODE_V << SPI_SMEM_DOUT11_MODE_S)
-#define SPI_SMEM_DOUT11_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT11_MODE_S  3
-/** SPI_SMEM_DOUT12_MODE : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT11_MODE    (BIT(3))
+#define SPI_MEM_S_SMEM_DOUT11_MODE_M  (SPI_MEM_S_SMEM_DOUT11_MODE_V << SPI_MEM_S_SMEM_DOUT11_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT11_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT11_MODE_S  3
+/** SPI_MEM_S_SMEM_DOUT12_MODE : R/W; bitpos: [4]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT12_MODE    (BIT(4))
-#define SPI_SMEM_DOUT12_MODE_M  (SPI_SMEM_DOUT12_MODE_V << SPI_SMEM_DOUT12_MODE_S)
-#define SPI_SMEM_DOUT12_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT12_MODE_S  4
-/** SPI_SMEM_DOUT13_MODE : R/W; bitpos: [5]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT12_MODE    (BIT(4))
+#define SPI_MEM_S_SMEM_DOUT12_MODE_M  (SPI_MEM_S_SMEM_DOUT12_MODE_V << SPI_MEM_S_SMEM_DOUT12_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT12_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT12_MODE_S  4
+/** SPI_MEM_S_SMEM_DOUT13_MODE : R/W; bitpos: [5]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT13_MODE    (BIT(5))
-#define SPI_SMEM_DOUT13_MODE_M  (SPI_SMEM_DOUT13_MODE_V << SPI_SMEM_DOUT13_MODE_S)
-#define SPI_SMEM_DOUT13_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT13_MODE_S  5
-/** SPI_SMEM_DOUT14_MODE : R/W; bitpos: [6]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT13_MODE    (BIT(5))
+#define SPI_MEM_S_SMEM_DOUT13_MODE_M  (SPI_MEM_S_SMEM_DOUT13_MODE_V << SPI_MEM_S_SMEM_DOUT13_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT13_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT13_MODE_S  5
+/** SPI_MEM_S_SMEM_DOUT14_MODE : R/W; bitpos: [6]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT14_MODE    (BIT(6))
-#define SPI_SMEM_DOUT14_MODE_M  (SPI_SMEM_DOUT14_MODE_V << SPI_SMEM_DOUT14_MODE_S)
-#define SPI_SMEM_DOUT14_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT14_MODE_S  6
-/** SPI_SMEM_DOUT15_MODE : R/W; bitpos: [7]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT14_MODE    (BIT(6))
+#define SPI_MEM_S_SMEM_DOUT14_MODE_M  (SPI_MEM_S_SMEM_DOUT14_MODE_V << SPI_MEM_S_SMEM_DOUT14_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT14_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT14_MODE_S  6
+/** SPI_MEM_S_SMEM_DOUT15_MODE : R/W; bitpos: [7]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUT15_MODE    (BIT(7))
-#define SPI_SMEM_DOUT15_MODE_M  (SPI_SMEM_DOUT15_MODE_V << SPI_SMEM_DOUT15_MODE_S)
-#define SPI_SMEM_DOUT15_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT15_MODE_S  7
-/** SPI_SMEM_DOUTS_HEX_MODE : R/W; bitpos: [8]; default: 0;
+#define SPI_MEM_S_SMEM_DOUT15_MODE    (BIT(7))
+#define SPI_MEM_S_SMEM_DOUT15_MODE_M  (SPI_MEM_S_SMEM_DOUT15_MODE_V << SPI_MEM_S_SMEM_DOUT15_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT15_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT15_MODE_S  7
+/** SPI_MEM_S_SMEM_DOUTS_HEX_MODE : R/W; bitpos: [8]; default: 0;
  *  the output signals are delayed by system clock cycles, 0: output without delayed,
  *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
  *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
  *  with the spi_clk high edge ,6: output with the spi_clk low edge
  */
-#define SPI_SMEM_DOUTS_HEX_MODE    (BIT(8))
-#define SPI_SMEM_DOUTS_HEX_MODE_M  (SPI_SMEM_DOUTS_HEX_MODE_V << SPI_SMEM_DOUTS_HEX_MODE_S)
-#define SPI_SMEM_DOUTS_HEX_MODE_V  0x00000001U
-#define SPI_SMEM_DOUTS_HEX_MODE_S  8
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE    (BIT(8))
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_M  (SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V << SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S)
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S  8
 
-/** SPI_MEM_CLOCK_GATE_REG register
+/** SPI_MEM_S_CLOCK_GATE_REG register
  *  SPI0 clock gate register
  */
-#define SPI_MEM_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x200)
+#define SPI_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x200)
 /** SPI_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Register clock gate enable signal. 1: Enable. 0: Disable.
  */
@@ -2884,121 +2884,121 @@ extern "C" {
 #define SPI_CLK_EN_V  0x00000001U
 #define SPI_CLK_EN_S  0
 
-/** SPI_MEM_XTS_PLAIN_BASE_REG register
+/** SPI_MEM_S_XTS_PLAIN_BASE_REG register
  *  The base address of the memory that stores plaintext in Manual Encryption
  */
-#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x300)
-/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
+#define SPI_MEM_S_XTS_PLAIN_BASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x300)
+/** SPI_MEM_S_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
  *  This field is only used to generate include file in c case. This field is useless.
  *  Please do not use this field.
  */
-#define SPI_XTS_PLAIN    0xFFFFFFFFU
-#define SPI_XTS_PLAIN_M  (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S)
-#define SPI_XTS_PLAIN_V  0xFFFFFFFFU
-#define SPI_XTS_PLAIN_S  0
+#define SPI_MEM_S_XTS_PLAIN    0xFFFFFFFFU
+#define SPI_MEM_S_XTS_PLAIN_M  (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S)
+#define SPI_MEM_S_XTS_PLAIN_V  0xFFFFFFFFU
+#define SPI_MEM_S_XTS_PLAIN_S  0
 
-/** SPI_MEM_XTS_LINESIZE_REG register
+/** SPI_MEM_S_XTS_LINESIZE_REG register
  *  Manual Encryption Line-Size register
  */
-#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x340)
-/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
+#define SPI_MEM_S_XTS_LINESIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x340)
+/** SPI_MEM_S_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
  *  This bits stores the line-size parameter which will be used in manual encryption
  *  calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
  *  32-bytes, 2: 64-bytes, 3:reserved.
  */
-#define SPI_XTS_LINESIZE    0x00000003U
-#define SPI_XTS_LINESIZE_M  (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S)
-#define SPI_XTS_LINESIZE_V  0x00000003U
-#define SPI_XTS_LINESIZE_S  0
+#define SPI_MEM_S_XTS_LINESIZE    0x00000003U
+#define SPI_MEM_S_XTS_LINESIZE_M  (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S)
+#define SPI_MEM_S_XTS_LINESIZE_V  0x00000003U
+#define SPI_MEM_S_XTS_LINESIZE_S  0
 
-/** SPI_MEM_XTS_DESTINATION_REG register
+/** SPI_MEM_S_XTS_DESTINATION_REG register
  *  Manual Encryption destination register
  */
-#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_PSRAM_MSPI0_BASE + 0x344)
-/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_XTS_DESTINATION_REG (DR_REG_PSRAM_MSPI0_BASE + 0x344)
+/** SPI_MEM_S_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
  *  This bit stores the destination parameter which will be used in manual encryption
  *  calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
  */
-#define SPI_XTS_DESTINATION    (BIT(0))
-#define SPI_XTS_DESTINATION_M  (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S)
-#define SPI_XTS_DESTINATION_V  0x00000001U
-#define SPI_XTS_DESTINATION_S  0
+#define SPI_MEM_S_XTS_DESTINATION    (BIT(0))
+#define SPI_MEM_S_XTS_DESTINATION_M  (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S)
+#define SPI_MEM_S_XTS_DESTINATION_V  0x00000001U
+#define SPI_MEM_S_XTS_DESTINATION_S  0
 
-/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register
+/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348)
-/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348)
+/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
  *  This bits stores the physical-address parameter which will be used in manual
  *  encryption calculation. This value should aligned with byte number decided by
  *  line-size parameter.
  */
-#define SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFFU
-#define SPI_XTS_PHYSICAL_ADDRESS_M  (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S)
-#define SPI_XTS_PHYSICAL_ADDRESS_V  0x03FFFFFFU
-#define SPI_XTS_PHYSICAL_ADDRESS_S  0
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS    0x03FFFFFFU
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_M  (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S)
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V  0x03FFFFFFU
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S  0
 
-/** SPI_MEM_XTS_TRIGGER_REG register
+/** SPI_MEM_S_XTS_TRIGGER_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34c)
-/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0;
+#define SPI_MEM_S_XTS_TRIGGER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34c)
+/** SPI_MEM_S_XTS_TRIGGER : WT; bitpos: [0]; default: 0;
  *  Set this bit to trigger the process of manual encryption calculation. This action
  *  should only be asserted when manual encryption status is 0. After this action,
  *  manual encryption status becomes 1. After calculation is done, manual encryption
  *  status becomes 2.
  */
-#define SPI_XTS_TRIGGER    (BIT(0))
-#define SPI_XTS_TRIGGER_M  (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S)
-#define SPI_XTS_TRIGGER_V  0x00000001U
-#define SPI_XTS_TRIGGER_S  0
+#define SPI_MEM_S_XTS_TRIGGER    (BIT(0))
+#define SPI_MEM_S_XTS_TRIGGER_M  (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S)
+#define SPI_MEM_S_XTS_TRIGGER_V  0x00000001U
+#define SPI_MEM_S_XTS_TRIGGER_S  0
 
-/** SPI_MEM_XTS_RELEASE_REG register
+/** SPI_MEM_S_XTS_RELEASE_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_RELEASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x350)
-/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0;
+#define SPI_MEM_S_XTS_RELEASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x350)
+/** SPI_MEM_S_XTS_RELEASE : WT; bitpos: [0]; default: 0;
  *  Set this bit to release encrypted result to mspi. This action should only be
  *  asserted when manual encryption status is 2. After this action, manual encryption
  *  status will become 3.
  */
-#define SPI_XTS_RELEASE    (BIT(0))
-#define SPI_XTS_RELEASE_M  (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S)
-#define SPI_XTS_RELEASE_V  0x00000001U
-#define SPI_XTS_RELEASE_S  0
+#define SPI_MEM_S_XTS_RELEASE    (BIT(0))
+#define SPI_MEM_S_XTS_RELEASE_M  (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S)
+#define SPI_MEM_S_XTS_RELEASE_V  0x00000001U
+#define SPI_MEM_S_XTS_RELEASE_S  0
 
-/** SPI_MEM_XTS_DESTROY_REG register
+/** SPI_MEM_S_XTS_DESTROY_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_DESTROY_REG (DR_REG_PSRAM_MSPI0_BASE + 0x354)
-/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0;
+#define SPI_MEM_S_XTS_DESTROY_REG (DR_REG_PSRAM_MSPI0_BASE + 0x354)
+/** SPI_MEM_S_XTS_DESTROY : WT; bitpos: [0]; default: 0;
  *  Set this bit to destroy encrypted result. This action should be asserted only when
  *  manual encryption status is 3. After this action, manual encryption status will
  *  become 0.
  */
-#define SPI_XTS_DESTROY    (BIT(0))
-#define SPI_XTS_DESTROY_M  (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S)
-#define SPI_XTS_DESTROY_V  0x00000001U
-#define SPI_XTS_DESTROY_S  0
+#define SPI_MEM_S_XTS_DESTROY    (BIT(0))
+#define SPI_MEM_S_XTS_DESTROY_M  (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S)
+#define SPI_MEM_S_XTS_DESTROY_V  0x00000001U
+#define SPI_MEM_S_XTS_DESTROY_S  0
 
-/** SPI_MEM_XTS_STATE_REG register
+/** SPI_MEM_S_XTS_STATE_REG register
  *  Manual Encryption physical address register
  */
-#define SPI_MEM_XTS_STATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x358)
-/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0;
+#define SPI_MEM_S_XTS_STATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x358)
+/** SPI_MEM_S_XTS_STATE : RO; bitpos: [1:0]; default: 0;
  *  This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
  *  calculation, 2: encryption calculation is done but the encrypted result is
  *  invisible to mspi, 3: the encrypted result is visible to mspi.
  */
-#define SPI_XTS_STATE    0x00000003U
-#define SPI_XTS_STATE_M  (SPI_XTS_STATE_V << SPI_XTS_STATE_S)
-#define SPI_XTS_STATE_V  0x00000003U
-#define SPI_XTS_STATE_S  0
+#define SPI_MEM_S_XTS_STATE    0x00000003U
+#define SPI_MEM_S_XTS_STATE_M  (SPI_XTS_STATE_V << SPI_XTS_STATE_S)
+#define SPI_MEM_S_XTS_STATE_V  0x00000003U
+#define SPI_MEM_S_XTS_STATE_S  0
 
-/** SPI_MEM_XTS_DATE_REG register
+/** SPI_MEM_S_XTS_DATE_REG register
  *  Manual Encryption version register
  */
-#define SPI_MEM_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c)
+#define SPI_MEM_S_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c)
 /** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176;
  *  This bits stores the last modified-time of manual encryption feature.
  */
@@ -3007,106 +3007,106 @@ extern "C" {
 #define SPI_XTS_DATE_V  0x3FFFFFFFU
 #define SPI_XTS_DATE_S  0
 
-/** SPI_MEM_MMU_ITEM_CONTENT_REG register
+/** SPI_MEM_S_MMU_ITEM_CONTENT_REG register
  *  MSPI-MMU item content register
  */
-#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x37c)
-/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
+#define SPI_MEM_S_MMU_ITEM_CONTENT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x37c)
+/** SPI_MEM_S_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
  *  MSPI-MMU item content
  */
-#define SPI_MMU_ITEM_CONTENT    0xFFFFFFFFU
-#define SPI_MMU_ITEM_CONTENT_M  (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S)
-#define SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFFU
-#define SPI_MMU_ITEM_CONTENT_S  0
+#define SPI_MEM_S_MMU_ITEM_CONTENT    0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_CONTENT_M  (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S)
+#define SPI_MEM_S_MMU_ITEM_CONTENT_V  0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_CONTENT_S  0
 
-/** SPI_MEM_MMU_ITEM_INDEX_REG register
+/** SPI_MEM_S_MMU_ITEM_INDEX_REG register
  *  MSPI-MMU item index register
  */
-#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_PSRAM_MSPI0_BASE + 0x380)
-/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
+#define SPI_MEM_S_MMU_ITEM_INDEX_REG (DR_REG_PSRAM_MSPI0_BASE + 0x380)
+/** SPI_MEM_S_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
  *  MSPI-MMU item index
  */
-#define SPI_MMU_ITEM_INDEX    0xFFFFFFFFU
-#define SPI_MMU_ITEM_INDEX_M  (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S)
-#define SPI_MMU_ITEM_INDEX_V  0xFFFFFFFFU
-#define SPI_MMU_ITEM_INDEX_S  0
+#define SPI_MEM_S_MMU_ITEM_INDEX    0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_INDEX_M  (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S)
+#define SPI_MEM_S_MMU_ITEM_INDEX_V  0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_INDEX_S  0
 
-/** SPI_MEM_MMU_POWER_CTRL_REG register
+/** SPI_MEM_S_MMU_POWER_CTRL_REG register
  *  MSPI MMU power control register
  */
-#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x384)
-/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
+#define SPI_MEM_S_MMU_POWER_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x384)
+/** SPI_MEM_S_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
  *  Set this bit to enable mmu-memory clock force on
  */
-#define SPI_MMU_MEM_FORCE_ON    (BIT(0))
-#define SPI_MMU_MEM_FORCE_ON_M  (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S)
-#define SPI_MMU_MEM_FORCE_ON_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_ON_S  0
-/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+#define SPI_MEM_S_MMU_MEM_FORCE_ON    (BIT(0))
+#define SPI_MEM_S_MMU_MEM_FORCE_ON_M  (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S)
+#define SPI_MEM_S_MMU_MEM_FORCE_ON_V  0x00000001U
+#define SPI_MEM_S_MMU_MEM_FORCE_ON_S  0
+/** SPI_MEM_S_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
  *  Set this bit to force mmu-memory powerdown
  */
-#define SPI_MMU_MEM_FORCE_PD    (BIT(1))
-#define SPI_MMU_MEM_FORCE_PD_M  (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S)
-#define SPI_MMU_MEM_FORCE_PD_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_PD_S  1
-/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+#define SPI_MEM_S_MMU_MEM_FORCE_PD    (BIT(1))
+#define SPI_MEM_S_MMU_MEM_FORCE_PD_M  (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S)
+#define SPI_MEM_S_MMU_MEM_FORCE_PD_V  0x00000001U
+#define SPI_MEM_S_MMU_MEM_FORCE_PD_S  1
+/** SPI_MEM_S_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
  *  Set this bit to force mmu-memory powerup, in this case, the power should also be
  *  controlled by rtc.
  */
-#define SPI_MMU_MEM_FORCE_PU    (BIT(2))
-#define SPI_MMU_MEM_FORCE_PU_M  (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S)
-#define SPI_MMU_MEM_FORCE_PU_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_PU_S  2
-/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896;
+#define SPI_MEM_S_MMU_MEM_FORCE_PU    (BIT(2))
+#define SPI_MEM_S_MMU_MEM_FORCE_PU_M  (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S)
+#define SPI_MEM_S_MMU_MEM_FORCE_PU_V  0x00000001U
+#define SPI_MEM_S_MMU_MEM_FORCE_PU_S  2
+/** SPI_MEM_S_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896;
  *  MMU PSRAM aux control register
  */
-#define SPI_MEM_AUX_CTRL    0x00003FFFU
-#define SPI_MEM_AUX_CTRL_M  (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S)
-#define SPI_MEM_AUX_CTRL_V  0x00003FFFU
-#define SPI_MEM_AUX_CTRL_S  16
+#define SPI_MEM_S_AUX_CTRL    0x00003FFFU
+#define SPI_MEM_S_AUX_CTRL_M  (SPI_MEM_S_AUX_CTRL_V << SPI_MEM_S_AUX_CTRL_S)
+#define SPI_MEM_S_AUX_CTRL_V  0x00003FFFU
+#define SPI_MEM_S_AUX_CTRL_S  16
 
-/** SPI_MEM_DPA_CTRL_REG register
+/** SPI_MEM_S_DPA_CTRL_REG register
  *  SPI memory cryption DPA register
  */
-#define SPI_MEM_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388)
-/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
+#define SPI_MEM_S_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388)
+/** SPI_MEM_S_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
  *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
  *  The bigger the number is, the more secure the cryption is. (Note that the
  *  performance of cryption will decrease together with this number increasing)
  */
-#define SPI_CRYPT_SECURITY_LEVEL    0x00000007U
-#define SPI_CRYPT_SECURITY_LEVEL_M  (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S)
-#define SPI_CRYPT_SECURITY_LEVEL_V  0x00000007U
-#define SPI_CRYPT_SECURITY_LEVEL_S  0
-/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1;
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL    0x00000007U
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_M  (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S)
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_V  0x00000007U
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_S  0
+/** SPI_MEM_S_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1;
  *  Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the
  *  calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that
  *  using key 1.
  */
-#define SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define SPI_CRYPT_CALC_D_DPA_EN_M  (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S)
-#define SPI_CRYPT_CALC_D_DPA_EN_V  0x00000001U
-#define SPI_CRYPT_CALC_D_DPA_EN_S  3
-/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0;
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_M  (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S)
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_V  0x00000001U
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_S  3
+/** SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0;
  *  1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and
  *  SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.
  */
-#define SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define SPI_CRYPT_DPA_SELECT_REGISTER_M  (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S)
-#define SPI_CRYPT_DPA_SELECT_REGISTER_V  0x00000001U
-#define SPI_CRYPT_DPA_SELECT_REGISTER_S  4
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_M  (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S)
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V  0x00000001U
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S  4
 
-/** SPI_MEM_DATE_REG register
+/** SPI_MEM_S_DATE_REG register
  *  SPI0 version control register
  */
-#define SPI_MEM_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc)
-/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36712704;
+#define SPI_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc)
+/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 36712704;
  *  SPI0 register version.
  */
-#define SPI_MEM_DATE    0x0FFFFFFFU
-#define SPI_MEM_DATE_M  (SPI_MEM_DATE_V << SPI_MEM_DATE_S)
-#define SPI_MEM_DATE_V  0x0FFFFFFFU
-#define SPI_MEM_DATE_S  0
+#define SPI_MEM_S_DATE    0x0FFFFFFFU
+#define SPI_MEM_S_DATE_M  (SPI_MEM_S_DATE_V << SPI_MEM_S_DATE_S)
+#define SPI_MEM_S_DATE_V  0x0FFFFFFFU
+#define SPI_MEM_S_DATE_S  0
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h b/components/soc/esp32p4/include/soc/spi_mem_s_struct.h
index ead95c5e04..fd28bddac6 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_s_struct.h
@@ -30,7 +30,7 @@ typedef union {
         uint32_t mem_slv_st:4;
         uint32_t reserved_8:10;
         /** mem_usr : HRO; bitpos: [18]; default: 0;
-         *  SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
+         *  SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared.  An operation
          *  will be triggered when the bit is set. The bit will be cleared once the operation
          *  done.1: enable 0: disable.
          */
@@ -38,7 +38,7 @@ typedef union {
         uint32_t reserved_19:13;
     };
     uint32_t val;
-} spi_mem_cmd_reg_t;
+} spi_mem_s_cmd_reg_t;
 
 /** Type of mem_axi_err_addr register
  *  SPI0 AXI request error address.
@@ -47,14 +47,14 @@ typedef union {
     struct {
         /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first AXI write/read invalid error or AXI write flash error
-         *  address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
-         *  SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
+         *  address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR,
+         *  SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set.
          */
         uint32_t mem_axi_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_axi_err_addr_reg_t;
+} spi_mem_s_axi_err_addr_reg_t;
 
 
 /** Group: Flash Control and configuration registers */
@@ -108,8 +108,8 @@ typedef union {
         uint32_t mem_fcmd_oct:1;
         uint32_t reserved_10:3;
         /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT
-         *  and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.
+         *  This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT
+         *  and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable.
          */
         uint32_t mem_fastrd_mode:1;
         /** mem_fread_dual : R/W; bitpos: [14]; default: 0;
@@ -157,7 +157,7 @@ typedef union {
         uint32_t mem_data_ie_always_on:1;
     };
     uint32_t val;
-} spi_mem_ctrl_reg_t;
+} spi_mem_s_ctrl_reg_t;
 
 /** Type of mem_ctrl1 register
  *  SPI0 control1 register.
@@ -188,7 +188,7 @@ typedef union {
         /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
          *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
          *  when there is a ECC error in AXI read data. The ECC error information is recorded
-         *  in SPI_MEM_ECC_ERR_ADDR_REG.
+         *  in SPI_MEM_S_ECC_ERR_ADDR_REG.
          */
         uint32_t mem_rresp_ecc_err_en:1;
         /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0;
@@ -200,9 +200,9 @@ typedef union {
          */
         uint32_t mem_aw_splice_en:1;
         /** mem_ram0_en : HRO; bitpos: [27]; default: 1;
-         *  When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be
-         *  accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1
-         *  will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+         *  When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be
+         *  accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1
+         *  will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
          *  accessed at the same time.
          */
         uint32_t mem_ram0_en:1;
@@ -229,7 +229,7 @@ typedef union {
         uint32_t mem_txfifo_rst:1;
     };
     uint32_t val;
-} spi_mem_ctrl1_reg_t;
+} spi_mem_s_ctrl1_reg_t;
 
 /** Type of mem_ctrl2 register
  *  SPI0 control2 register.
@@ -238,16 +238,16 @@ typedef union {
     struct {
         /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1;
          *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
-         *  SPI_MEM_CS_SETUP bit.
+         *  SPI_MEM_S_CS_SETUP bit.
          */
         uint32_t mem_cs_setup_time:5;
         /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1;
          *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
-         *  SPI_MEM_CS_HOLD bit.
+         *  SPI_MEM_S_CS_HOLD bit.
          */
         uint32_t mem_cs_hold_time:5;
         /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3;
-         *  SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+         *  SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
          *  mode when accessed flash.
          */
         uint32_t mem_ecc_cs_hold_time:3;
@@ -270,7 +270,7 @@ typedef union {
         uint32_t mem_split_trans_en:1;
         /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
          *  These bits are used to set the minimum CS high time tSHSL between SPI burst
-         *  transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
+         *  transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI
          *  core clock cycles.
          */
         uint32_t mem_cs_hold_delay:6;
@@ -280,7 +280,7 @@ typedef union {
         uint32_t mem_sync_reset:1;
     };
     uint32_t val;
-} spi_mem_ctrl2_reg_t;
+} spi_mem_s_ctrl2_reg_t;
 
 /** Type of mem_misc register
  *  SPI0 misc register
@@ -307,7 +307,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_misc_reg_t;
+} spi_mem_s_misc_reg_t;
 
 /** Type of mem_cache_fctrl register
  *  SPI0 bit mode control register.
@@ -326,7 +326,7 @@ typedef union {
         uint32_t close_axi_inf_en:1;
     };
     uint32_t val;
-} spi_mem_cache_fctrl_reg_t;
+} spi_mem_s_cache_fctrl_reg_t;
 
 /** Type of mem_ddr register
  *  SPI0 flash DDR mode control register
@@ -373,7 +373,7 @@ typedef union {
         uint32_t fmem_usr_ddr_dqs_thd:7;
         /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -410,7 +410,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_mem_ddr_reg_t;
+} spi_mem_s_ddr_reg_t;
 
 
 /** Group: Clock control and configuration registers */
@@ -420,16 +420,16 @@ typedef union {
 typedef union {
     struct {
         /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
+         *  In the master mode it must be equal to spi_mem_s_clkcnt_N.
          */
         uint32_t mem_clkcnt_l:8;
         /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+         *  In the master mode it must be floor((spi_mem_s_clkcnt_N+1)/2-1).
          */
         uint32_t mem_clkcnt_h:8;
         /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
+         *  In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is
+         *  system/(spi_mem_s_clkcnt_N+1)
          */
         uint32_t mem_clkcnt_n:8;
         uint32_t reserved_24:7;
@@ -440,7 +440,7 @@ typedef union {
         uint32_t mem_clk_equ_sysclk:1;
     };
     uint32_t val;
-} spi_mem_clock_reg_t;
+} spi_mem_s_clock_reg_t;
 
 /** Type of mem_clock_gate register
  *  SPI0 clock gate register
@@ -454,7 +454,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_clock_gate_reg_t;
+} spi_mem_s_clock_gate_reg_t;
 
 
 /** Group: Flash User-defined control registers */
@@ -474,7 +474,7 @@ typedef union {
         uint32_t mem_cs_setup:1;
         uint32_t reserved_8:1;
         /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+         *  The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
          */
         uint32_t mem_ck_out_edge:1;
         uint32_t reserved_10:16;
@@ -490,7 +490,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_user_reg_t;
+} spi_mem_s_user_reg_t;
 
 /** Type of mem_user1 register
  *  SPI0 user1 register.
@@ -498,7 +498,7 @@ typedef union {
 typedef union {
     struct {
         /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+         *  The length in spi_mem_s_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
         uint32_t mem_usr_dummy_cyclelen:6;
@@ -513,7 +513,7 @@ typedef union {
         uint32_t mem_usr_addr_bitlen:6;
     };
     uint32_t val;
-} spi_mem_user1_reg_t;
+} spi_mem_s_user1_reg_t;
 
 /** Type of mem_user2 register
  *  SPI0 user2 register.
@@ -531,7 +531,7 @@ typedef union {
         uint32_t mem_usr_command_bitlen:4;
     };
     uint32_t val;
-} spi_mem_user2_reg_t;
+} spi_mem_s_user2_reg_t;
 
 
 /** Group: External RAM Control and configuration registers */
@@ -564,7 +564,7 @@ typedef union {
         uint32_t smem_data_ie_always_on:1;
     };
     uint32_t val;
-} spi_mem_sram_cmd_reg_t;
+} spi_mem_s_sram_cmd_reg_t;
 
 /** Type of smem_ddr register
  *  SPI0 external RAM DDR mode control register
@@ -611,7 +611,7 @@ typedef union {
         uint32_t smem_usr_ddr_dqs_thd:7;
         /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -649,7 +649,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_smem_ddr_reg_t;
+} spi_mem_s_smem_ddr_reg_t;
 
 /** Type of smem_ac register
  *  MSPI external RAM ECC and SPI CS timing control register
@@ -667,16 +667,16 @@ typedef union {
         uint32_t smem_cs_hold:1;
         /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1;
          *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
-         *  spi_mem_cs_setup bit.
+         *  spi_mem_s_cs_setup bit.
          */
         uint32_t smem_cs_setup_time:5;
         /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1;
          *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
-         *  combined with spi_mem_cs_hold bit.
+         *  combined with spi_mem_s_cs_hold bit.
          */
         uint32_t smem_cs_hold_time:5;
         /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3;
-         *  SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+         *  SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
          *  cycles in ECC mode when accessed external RAM.
          */
         uint32_t smem_ecc_cs_hold_time:3;
@@ -693,7 +693,7 @@ typedef union {
         uint32_t reserved_17:8;
         /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
          *  These bits are used to set the minimum CS high time tSHSL between SPI burst
-         *  transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1)
+         *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1)
          *  MSPI core clock cycles.
          */
         uint32_t smem_cs_hold_delay:6;
@@ -705,7 +705,7 @@ typedef union {
         uint32_t smem_split_trans_en:1;
     };
     uint32_t val;
-} spi_smem_ac_reg_t;
+} spi_mem_s_smem_ac_reg_t;
 
 
 /** Group: State control register */
@@ -722,7 +722,7 @@ typedef union {
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_fsm_reg_t;
+} spi_mem_s_fsm_reg_t;
 
 
 /** Group: Interrupt registers */
@@ -733,53 +733,53 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_ena:1;
         /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_ena:1;
         /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_ena:1;
         /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_ena:1;
         /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_ena:1;
         /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_ena:1;
         /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int__ena:1;
         uint32_t reserved_10:18;
         /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0;
-         *  The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
+         *  The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
          */
         uint32_t mem_dqs0_afifo_ovf_int_ena:1;
         /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0;
-         *  The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
+         *  The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
          */
         uint32_t mem_dqs1_afifo_ovf_int_ena:1;
         /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0;
-         *  The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
+         *  The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
          */
         uint32_t mem_bus_fifo1_udf_int_ena:1;
         /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0;
-         *  The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
+         *  The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
          */
         uint32_t mem_bus_fifo0_udf_int_ena:1;
     };
     uint32_t val;
-} spi_mem_int_ena_reg_t;
+} spi_mem_s_int_ena_reg_t;
 
 /** Type of mem_int_clr register
  *  SPI0 interrupt clear register
@@ -788,53 +788,53 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_clr:1;
         /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_clr:1;
         /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0;
-         *  The clear bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_clr:1;
         /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0;
-         *  The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_clr:1;
         /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_clr:1;
         /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_clr:1;
         /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int_clr:1;
         uint32_t reserved_10:18;
         /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0;
-         *  The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
+         *  The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
          */
         uint32_t mem_dqs0_afifo_ovf_int_clr:1;
         /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0;
-         *  The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
+         *  The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
          */
         uint32_t mem_dqs1_afifo_ovf_int_clr:1;
         /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0;
-         *  The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
+         *  The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
          */
         uint32_t mem_bus_fifo1_udf_int_clr:1;
         /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0;
-         *  The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
+         *  The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
          */
         uint32_t mem_bus_fifo0_udf_int_clr:1;
     };
     uint32_t val;
-} spi_mem_int_clr_reg_t;
+} spi_mem_s_int_clr_reg_t;
 
 /** Type of mem_int_raw register
  *  SPI0 interrupt raw register
@@ -843,73 +843,73 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+         *  The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
         uint32_t mem_slv_st_end_int_raw:1;
         /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+         *  The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
         uint32_t mem_mst_st_end_int_raw:1;
         /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set
-         *  and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
-         *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When
-         *  SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is
+         *  The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set
+         *  and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+         *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When
+         *  SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is
          *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
-         *  than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and
-         *  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+         *  than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and
+         *  SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
          *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
-         *  SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN
+         *  SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN
          *  are cleared, this bit will not be triggered.
          */
         uint32_t mem_ecc_err_int_raw:1;
         /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+         *  The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
          *  rejected. 0: Others.
          */
         uint32_t mem_pms_reject_int_raw:1;
         /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+         *  The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
         uint32_t mem_axi_raddr_err_int_raw:1;
         /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+         *  The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
          *  flash request is received. 0: Others.
          */
         uint32_t mem_axi_wr_flash_err_int_raw:1;
         /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+         *  The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
         uint32_t mem_axi_waddr_err_int_raw:1;
         uint32_t reserved_10:18;
         /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+         *  The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
          *  connected to SPI_DQS1 is overflow.
          */
         uint32_t mem_dqs0_afifo_ovf_int_raw:1;
         /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+         *  The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
          *  connected to SPI_DQS is overflow.
          */
         uint32_t mem_dqs1_afifo_ovf_int_raw:1;
         /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
+         *  The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
          *  underflow.
          */
         uint32_t mem_bus_fifo1_udf_int_raw:1;
         /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
+         *  The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
          *  underflow.
          */
         uint32_t mem_bus_fifo0_udf_int_raw:1;
     };
     uint32_t val;
-} spi_mem_int_raw_reg_t;
+} spi_mem_s_int_raw_reg_t;
 
 /** Type of mem_int_st register
  *  SPI0 interrupt status register
@@ -918,53 +918,53 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_st:1;
         /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The status bit for SPI_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_st:1;
         /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0;
-         *  The status bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The status bit for SPI_MEM_S_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_st:1;
         /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0;
-         *  The status bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_st:1;
         /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_st:1;
         /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_st:1;
         /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int_st:1;
         uint32_t reserved_10:18;
         /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0;
-         *  The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
+         *  The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
          */
         uint32_t mem_dqs0_afifo_ovf_int_st:1;
         /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0;
-         *  The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
+         *  The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
          */
         uint32_t mem_dqs1_afifo_ovf_int_st:1;
         /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0;
-         *  The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
+         *  The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
          */
         uint32_t mem_bus_fifo1_udf_int_st:1;
         /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0;
-         *  The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
+         *  The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
          */
         uint32_t mem_bus_fifo0_udf_int_st:1;
     };
     uint32_t val;
-} spi_mem_int_st_reg_t;
+} spi_mem_s_int_st_reg_t;
 
 
 /** Group: PMS control and configuration registers */
@@ -983,14 +983,14 @@ typedef union {
         uint32_t fmem_pmsn_wr_attr:1;
         /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
          *  SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
-         *  section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and
-         *  SPI_FMEM_PMSn_SIZE_REG.
+         *  section n is configured by registers SPI_MEM_S_FMEM_PMSn_ADDR_REG and
+         *  SPI_MEM_S_FMEM_PMSn_SIZE_REG.
          */
         uint32_t fmem_pmsn_ecc:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} spi_fmem_pmsn_attr_reg_t;
+} spi_mem_s_fmem_pmsn_attr_reg_t;
 
 /** Type of fmem_pmsn_addr register
  *  SPI1 flash PMS section n start address register
@@ -1004,7 +1004,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_fmem_pmsn_addr_reg_t;
+} spi_mem_s_fmem_pmsn_addr_reg_t;
 
 /** Type of fmem_pmsn_size register
  *  SPI1 flash PMS section n start address register
@@ -1012,14 +1012,14 @@ typedef union {
 typedef union {
     struct {
         /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
-         *  SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S,
-         *  SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE)
+         *  SPI1 flash PMS section n address region is (SPI_MEM_S_FMEM_PMSn_ADDR_S,
+         *  SPI_MEM_S_FMEM_PMSn_ADDR_S + SPI_MEM_S_FMEM_PMSn_SIZE)
          */
         uint32_t fmem_pmsn_size:15;
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} spi_fmem_pmsn_size_reg_t;
+} spi_mem_s_fmem_pmsn_size_reg_t;
 
 /** Type of smem_pmsn_attr register
  *  SPI1 flash PMS section n start address register
@@ -1036,14 +1036,14 @@ typedef union {
         uint32_t smem_pmsn_wr_attr:1;
         /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
          *  SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The
-         *  external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and
-         *  SPI_SMEM_PMSn_SIZE_REG.
+         *  external RAM PMS section n is configured by registers SPI_MEM_S_SMEM_PMSn_ADDR_REG and
+         *  SPI_MEM_S_SMEM_PMSn_SIZE_REG.
          */
         uint32_t smem_pmsn_ecc:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} spi_smem_pmsn_attr_reg_t;
+} spi_mem_s_smem_pmsn_attr_reg_t;
 
 /** Type of smem_pmsn_addr register
  *  SPI1 external RAM PMS section n start address register
@@ -1057,7 +1057,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_smem_pmsn_addr_reg_t;
+} spi_mem_s_smem_pmsn_addr_reg_t;
 
 /** Type of smem_pmsn_size register
  *  SPI1 external RAM PMS section n start address register
@@ -1065,14 +1065,14 @@ typedef union {
 typedef union {
     struct {
         /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
-         *  SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S,
-         *  SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE)
+         *  SPI1 external RAM PMS section n address region is (SPI_MEM_S_SMEM_PMSn_ADDR_S,
+         *  SPI_MEM_S_SMEM_PMSn_ADDR_S + SPI_MEM_S_SMEM_PMSn_SIZE)
          */
         uint32_t smem_pmsn_size:15;
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} spi_smem_pmsn_size_reg_t;
+} spi_mem_s_smem_pmsn_size_reg_t;
 
 /** Type of mem_pms_reject register
  *  SPI1 access reject register
@@ -1081,7 +1081,7 @@ typedef union {
     struct {
         /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first SPI1 access error address. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_reject_addr:27;
         /** mem_pm_en : R/W; bitpos: [27]; default: 0;
@@ -1090,27 +1090,27 @@ typedef union {
         uint32_t mem_pm_en:1;
         /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
          *  1: SPI1 write access error. 0: No write access error. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_ld:1;
         /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0;
          *  1: SPI1 read access error. 0: No read access error. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_st:1;
         /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
          *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
-         *  cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_multi_hit:1;
         /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
          *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
-         *  error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  error. It is cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_ivd:1;
     };
     uint32_t val;
-} spi_mem_pms_reject_reg_t;
+} spi_mem_s_pms_reject_reg_t;
 
 
 /** Group: MSPI ECC registers */
@@ -1122,11 +1122,11 @@ typedef union {
         uint32_t reserved_0:5;
         /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0;
          *  This bits show the error times of MSPI ECC read. It is cleared by when
-         *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+         *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
          */
         uint32_t mem_ecc_err_cnt:6;
         /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10;
-         *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.
+         *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt.
          */
         uint32_t fmem_ecc_err_int_num:6;
         /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0;
@@ -1150,9 +1150,9 @@ typedef union {
         uint32_t mem_usr_ecc_addr_en:1;
         uint32_t reserved_22:2;
         /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1;
-         *  1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is
-         *  updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and
-         *  SPI_MEM_ECC_ERR_ADDR record the first ECC error information.
+         *  1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is
+         *  updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and
+         *  SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information.
          */
         uint32_t mem_ecc_continue_record_err_en:1;
         /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0;
@@ -1162,7 +1162,7 @@ typedef union {
         uint32_t mem_ecc_err_bits:7;
     };
     uint32_t val;
-} spi_mem_ecc_ctrl_reg_t;
+} spi_mem_s_ecc_ctrl_reg_t;
 
 /** Type of mem_ecc_err_addr register
  *  MSPI ECC error address register
@@ -1171,13 +1171,13 @@ typedef union {
     struct {
         /** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first MSPI ECC error address. It is cleared by when
-         *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+         *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
          */
         uint32_t mem_ecc_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_ecc_err_addr_reg_t;
+} spi_mem_s_ecc_err_addr_reg_t;
 
 /** Type of smem_ecc_ctrl register
  *  MSPI ECC control register
@@ -1204,7 +1204,7 @@ typedef union {
         uint32_t reserved_21:11;
     };
     uint32_t val;
-} spi_smem_ecc_ctrl_reg_t;
+} spi_mem_s_smem_ecc_ctrl_reg_t;
 
 
 /** Group: Status and state control registers */
@@ -1242,7 +1242,7 @@ typedef union {
         uint32_t all_axi_trans_afifo_empty:1;
     };
     uint32_t val;
-} spi_smem_axi_addr_ctrl_reg_t;
+} spi_mem_s_smem_axi_addr_ctrl_reg_t;
 
 /** Type of mem_axi_err_resp_en register
  *  SPI0 AXI error response enable register
@@ -1301,7 +1301,7 @@ typedef union {
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_axi_err_resp_en_reg_t;
+} spi_mem_s_axi_err_resp_en_reg_t;
 
 
 /** Group: Flash timing registers */
@@ -1334,7 +1334,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} spi_mem_timing_cali_reg_t;
+} spi_mem_s_timing_cali_reg_t;
 
 /** Type of mem_din_mode register
  *  MSPI flash input timing delay mode control register
@@ -1402,7 +1402,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_din_mode_reg_t;
+} spi_mem_s_din_mode_reg_t;
 
 /** Type of mem_din_num register
  *  MSPI flash input timing delay number control register
@@ -1457,7 +1457,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} spi_mem_din_num_reg_t;
+} spi_mem_s_din_num_reg_t;
 
 /** Type of mem_dout_mode register
  *  MSPI flash output timing adjustment control register
@@ -1525,7 +1525,7 @@ typedef union {
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_mem_dout_mode_reg_t;
+} spi_mem_s_dout_mode_reg_t;
 
 
 /** Group: External RAM timing registers */
@@ -1555,7 +1555,7 @@ typedef union {
         uint32_t reserved_6:26;
     };
     uint32_t val;
-} spi_smem_timing_cali_reg_t;
+} spi_mem_s_smem_timing_cali_reg_t;
 
 /** Type of smem_din_mode register
  *  MSPI external RAM input timing delay mode control register
@@ -1628,7 +1628,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_smem_din_mode_reg_t;
+} spi_mem_s_smem_din_mode_reg_t;
 
 /** Type of smem_din_num register
  *  MSPI external RAM input timing delay number control register
@@ -1683,7 +1683,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} spi_smem_din_num_reg_t;
+} spi_mem_s_smem_din_num_reg_t;
 
 /** Type of smem_dout_mode register
  *  MSPI external RAM output timing adjustment control register
@@ -1756,7 +1756,7 @@ typedef union {
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_smem_dout_mode_reg_t;
+} spi_mem_s_smem_dout_mode_reg_t;
 
 /** Type of smem_din_hex_mode register
  *  MSPI 16x external RAM input timing delay mode control register
@@ -1829,7 +1829,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_smem_din_hex_mode_reg_t;
+} spi_mem_s_smem_din_hex_mode_reg_t;
 
 /** Type of smem_din_hex_num register
  *  MSPI 16x external RAM input timing delay number control register
@@ -1884,7 +1884,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} spi_smem_din_hex_num_reg_t;
+} spi_mem_s_smem_din_hex_num_reg_t;
 
 /** Type of smem_dout_hex_mode register
  *  MSPI 16x external RAM output timing adjustment control register
@@ -1957,7 +1957,7 @@ typedef union {
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_smem_dout_hex_mode_reg_t;
+} spi_mem_s_smem_dout_hex_mode_reg_t;
 
 
 /** Group: Manual Encryption plaintext Memory */
@@ -1973,7 +1973,7 @@ typedef union {
         uint32_t xts_plain:32;
     };
     uint32_t val;
-} spi_mem_xts_plain_base_reg_t;
+} spi_mem_s_xts_plain_base_reg_t;
 
 
 /** Group: Manual Encryption configuration registers */
@@ -1991,7 +1991,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} spi_mem_xts_linesize_reg_t;
+} spi_mem_s_xts_linesize_reg_t;
 
 /** Type of mem_xts_destination register
  *  Manual Encryption destination register
@@ -2006,7 +2006,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_destination_reg_t;
+} spi_mem_s_xts_destination_reg_t;
 
 /** Type of mem_xts_physical_address register
  *  Manual Encryption physical address register
@@ -2022,7 +2022,7 @@ typedef union {
         uint32_t reserved_26:6;
     };
     uint32_t val;
-} spi_mem_xts_physical_address_reg_t;
+} spi_mem_s_xts_physical_address_reg_t;
 
 
 /** Group: Manual Encryption control and status registers */
@@ -2041,7 +2041,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_trigger_reg_t;
+} spi_mem_s_xts_trigger_reg_t;
 
 /** Type of mem_xts_release register
  *  Manual Encryption physical address register
@@ -2057,7 +2057,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_release_reg_t;
+} spi_mem_s_xts_release_reg_t;
 
 /** Type of mem_xts_destroy register
  *  Manual Encryption physical address register
@@ -2073,7 +2073,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_destroy_reg_t;
+} spi_mem_s_xts_destroy_reg_t;
 
 /** Type of mem_xts_state register
  *  Manual Encryption physical address register
@@ -2089,7 +2089,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} spi_mem_xts_state_reg_t;
+} spi_mem_s_xts_state_reg_t;
 
 
 /** Group: Manual Encryption version control register */
@@ -2105,7 +2105,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_xts_date_reg_t;
+} spi_mem_s_xts_date_reg_t;
 
 
 /** Group: MMU access registers */
@@ -2120,7 +2120,7 @@ typedef union {
         uint32_t mmu_item_content:32;
     };
     uint32_t val;
-} spi_mem_mmu_item_content_reg_t;
+} spi_mem_s_mmu_item_content_reg_t;
 
 /** Type of mem_mmu_item_index register
  *  MSPI-MMU item index register
@@ -2133,7 +2133,7 @@ typedef union {
         uint32_t mmu_item_index:32;
     };
     uint32_t val;
-} spi_mem_mmu_item_index_reg_t;
+} spi_mem_s_mmu_item_index_reg_t;
 
 
 /** Group: MMU power control and configuration registers */
@@ -2163,7 +2163,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_mmu_power_ctrl_reg_t;
+} spi_mem_s_mmu_power_ctrl_reg_t;
 
 
 /** Group: External mem cryption DPA registers */
@@ -2192,7 +2192,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} spi_mem_dpa_ctrl_reg_t;
+} spi_mem_s_dpa_ctrl_reg_t;
 
 
 /** Group: Version control register */
@@ -2208,87 +2208,87 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} spi_mem_date_reg_t;
+} spi_mem_s_date_reg_t;
 
 
-typedef struct {
-    volatile spi_mem_cmd_reg_t mem_cmd;
+typedef struct spi_mem_s_dev_s {
+    volatile spi_mem_s_cmd_reg_t mem_cmd;
     uint32_t reserved_004;
-    volatile spi_mem_ctrl_reg_t mem_ctrl;
-    volatile spi_mem_ctrl1_reg_t mem_ctrl1;
-    volatile spi_mem_ctrl2_reg_t mem_ctrl2;
-    volatile spi_mem_clock_reg_t mem_clock;
-    volatile spi_mem_user_reg_t mem_user;
-    volatile spi_mem_user1_reg_t mem_user1;
-    volatile spi_mem_user2_reg_t mem_user2;
+    volatile spi_mem_s_ctrl_reg_t mem_ctrl;
+    volatile spi_mem_s_ctrl1_reg_t mem_ctrl1;
+    volatile spi_mem_s_ctrl2_reg_t mem_ctrl2;
+    volatile spi_mem_s_clock_reg_t mem_clock;
+    volatile spi_mem_s_user_reg_t mem_user;
+    volatile spi_mem_s_user1_reg_t mem_user1;
+    volatile spi_mem_s_user2_reg_t mem_user2;
     uint32_t reserved_024[4];
-    volatile spi_mem_misc_reg_t mem_misc;
+    volatile spi_mem_s_misc_reg_t mem_misc;
     uint32_t reserved_038;
-    volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl;
+    volatile spi_mem_s_cache_fctrl_reg_t mem_cache_fctrl;
     uint32_t reserved_040;
-    volatile spi_mem_sram_cmd_reg_t mem_sram_cmd;
+    volatile spi_mem_s_sram_cmd_reg_t mem_sram_cmd;
     uint32_t reserved_048[3];
-    volatile spi_mem_fsm_reg_t mem_fsm;
+    volatile spi_mem_s_fsm_reg_t mem_fsm;
     uint32_t reserved_058[26];
-    volatile spi_mem_int_ena_reg_t mem_int_ena;
-    volatile spi_mem_int_clr_reg_t mem_int_clr;
-    volatile spi_mem_int_raw_reg_t mem_int_raw;
-    volatile spi_mem_int_st_reg_t mem_int_st;
+    volatile spi_mem_s_int_ena_reg_t mem_int_ena;
+    volatile spi_mem_s_int_clr_reg_t mem_int_clr;
+    volatile spi_mem_s_int_raw_reg_t mem_int_raw;
+    volatile spi_mem_s_int_st_reg_t mem_int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_ddr_reg_t mem_ddr;
-    volatile spi_smem_ddr_reg_t smem_ddr;
+    volatile spi_mem_s_ddr_reg_t mem_ddr;
+    volatile spi_mem_s_smem_ddr_reg_t smem_ddr;
     uint32_t reserved_0dc[9];
-    volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
-    volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
-    volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
-    volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
-    volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
-    volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4];
+    volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
+    volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
+    volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
+    volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
+    volatile spi_mem_s_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
+    volatile spi_mem_s_smem_pmsn_size_reg_t smem_pmsn_size[4];
     uint32_t reserved_160;
-    volatile spi_mem_pms_reject_reg_t mem_pms_reject;
-    volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl;
-    volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr;
-    volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr;
-    volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
-    volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
-    volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en;
-    volatile spi_mem_timing_cali_reg_t mem_timing_cali;
-    volatile spi_mem_din_mode_reg_t mem_din_mode;
-    volatile spi_mem_din_num_reg_t mem_din_num;
-    volatile spi_mem_dout_mode_reg_t mem_dout_mode;
-    volatile spi_smem_timing_cali_reg_t smem_timing_cali;
-    volatile spi_smem_din_mode_reg_t smem_din_mode;
-    volatile spi_smem_din_num_reg_t smem_din_num;
-    volatile spi_smem_dout_mode_reg_t smem_dout_mode;
-    volatile spi_smem_ac_reg_t smem_ac;
-    volatile spi_smem_din_hex_mode_reg_t smem_din_hex_mode;
-    volatile spi_smem_din_hex_num_reg_t smem_din_hex_num;
-    volatile spi_smem_dout_hex_mode_reg_t smem_dout_hex_mode;
+    volatile spi_mem_s_pms_reject_reg_t mem_pms_reject;
+    volatile spi_mem_s_ecc_ctrl_reg_t mem_ecc_ctrl;
+    volatile spi_mem_s_ecc_err_addr_reg_t mem_ecc_err_addr;
+    volatile spi_mem_s_axi_err_addr_reg_t mem_axi_err_addr;
+    volatile spi_mem_s_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
+    volatile spi_mem_s_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
+    volatile spi_mem_s_axi_err_resp_en_reg_t mem_axi_err_resp_en;
+    volatile spi_mem_s_timing_cali_reg_t mem_timing_cali;
+    volatile spi_mem_s_din_mode_reg_t mem_din_mode;
+    volatile spi_mem_s_din_num_reg_t mem_din_num;
+    volatile spi_mem_s_dout_mode_reg_t mem_dout_mode;
+    volatile spi_mem_s_smem_timing_cali_reg_t smem_timing_cali;
+    volatile spi_mem_s_smem_din_mode_reg_t smem_din_mode;
+    volatile spi_mem_s_smem_din_num_reg_t smem_din_num;
+    volatile spi_mem_s_smem_dout_mode_reg_t smem_dout_mode;
+    volatile spi_mem_s_smem_ac_reg_t smem_ac;
+    volatile spi_mem_s_smem_din_hex_mode_reg_t smem_din_hex_mode;
+    volatile spi_mem_s_smem_din_hex_num_reg_t smem_din_hex_num;
+    volatile spi_mem_s_smem_dout_hex_mode_reg_t smem_dout_hex_mode;
     uint32_t reserved_1b0[20];
-    volatile spi_mem_clock_gate_reg_t mem_clock_gate;
+    volatile spi_mem_s_clock_gate_reg_t mem_clock_gate;
     uint32_t reserved_204[63];
-    volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base;
+    volatile spi_mem_s_xts_plain_base_reg_t mem_xts_plain_base;
     uint32_t reserved_304[15];
-    volatile spi_mem_xts_linesize_reg_t mem_xts_linesize;
-    volatile spi_mem_xts_destination_reg_t mem_xts_destination;
-    volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address;
-    volatile spi_mem_xts_trigger_reg_t mem_xts_trigger;
-    volatile spi_mem_xts_release_reg_t mem_xts_release;
-    volatile spi_mem_xts_destroy_reg_t mem_xts_destroy;
-    volatile spi_mem_xts_state_reg_t mem_xts_state;
-    volatile spi_mem_xts_date_reg_t mem_xts_date;
+    volatile spi_mem_s_xts_linesize_reg_t mem_xts_linesize;
+    volatile spi_mem_s_xts_destination_reg_t mem_xts_destination;
+    volatile spi_mem_s_xts_physical_address_reg_t mem_xts_physical_address;
+    volatile spi_mem_s_xts_trigger_reg_t mem_xts_trigger;
+    volatile spi_mem_s_xts_release_reg_t mem_xts_release;
+    volatile spi_mem_s_xts_destroy_reg_t mem_xts_destroy;
+    volatile spi_mem_s_xts_state_reg_t mem_xts_state;
+    volatile spi_mem_s_xts_date_reg_t mem_xts_date;
     uint32_t reserved_360[7];
-    volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content;
-    volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index;
-    volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
-    volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl;
+    volatile spi_mem_s_mmu_item_content_reg_t mem_mmu_item_content;
+    volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index;
+    volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
+    volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl;
     uint32_t reserved_38c[28];
-    volatile spi_mem_date_reg_t mem_date;
+    volatile spi_mem_s_date_reg_t mem_date;
 } spi_mem_s_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure");
+_Static_assert(sizeof(spi_mem_s_dev_t) == 0x400, "Invalid size of spi_mem_s_dev_t structure");
 #endif
 
 #ifdef __cplusplus

From 8cf0e5d5b861f15c4a22fa86155fb4c8bea19fd6 Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Thu, 29 Jun 2023 16:38:27 +0800
Subject: [PATCH 05/13] feat(soc): rename rtc_wdt_reg to lp_wdt_reg

---
 .../soc/esp32p4/include/soc/lp_wdt_reg.h      | 763 +++++++-----------
 .../soc/esp32p4/include/soc/lp_wdt_struct.h   | 454 +++++++----
 .../soc/esp32p4/include/soc/rtc_wdt_reg.h     | 324 --------
 .../soc/esp32p4/include/soc/rtc_wdt_struct.h  | 309 -------
 4 files changed, 577 insertions(+), 1273 deletions(-)
 delete mode 100644 components/soc/esp32p4/include/soc/rtc_wdt_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/rtc_wdt_struct.h

diff --git a/components/soc/esp32p4/include/soc/lp_wdt_reg.h b/components/soc/esp32p4/include/soc/lp_wdt_reg.h
index f1cfb609e2..c2fcd17511 100644
--- a/components/soc/esp32p4/include/soc/lp_wdt_reg.h
+++ b/components/soc/esp32p4/include/soc/lp_wdt_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -11,506 +11,313 @@
 extern "C" {
 #endif
 
-// TODO: IDF-5730 (better to rename and move to wdt_types.h?)
-/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
-#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
-#define RTC_WDT_RESET_LENGTH_100_NS    0
-#define RTC_WDT_RESET_LENGTH_200_NS    1
-#define RTC_WDT_RESET_LENGTH_300_NS    2
-#define RTC_WDT_RESET_LENGTH_400_NS    3
-#define RTC_WDT_RESET_LENGTH_500_NS    4
-#define RTC_WDT_RESET_LENGTH_800_NS    5
-#define RTC_WDT_RESET_LENGTH_1600_NS   6
-#define RTC_WDT_RESET_LENGTH_3200_NS   7
-
-#define LP_WDT_RTC_WDTCONFIG0_REG          (DR_REG_LP_WDT_BASE + 0x0)
-/* LP_WDT_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define LP_WDT_WDT_EN    (BIT(31))
-#define LP_WDT_WDT_EN_M  (BIT(31))
-#define LP_WDT_WDT_EN_V  0x1
-#define LP_WDT_WDT_EN_S  31
-/* LP_WDT_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
-reset stage en.*/
-#define LP_WDT_WDT_STG0    0x00000007
-#define LP_WDT_WDT_STG0_M  ((LP_WDT_WDT_STG0_V)<<(LP_WDT_WDT_STG0_S))
-#define LP_WDT_WDT_STG0_V  0x7
-#define LP_WDT_WDT_STG0_S  28
-/* LP_WDT_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
-reset stage en.*/
-#define LP_WDT_WDT_STG1    0x00000007
-#define LP_WDT_WDT_STG1_M  ((LP_WDT_WDT_STG1_V)<<(LP_WDT_WDT_STG1_S))
-#define LP_WDT_WDT_STG1_V  0x7
-#define LP_WDT_WDT_STG1_S  25
-/* LP_WDT_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
-reset stage en.*/
-#define LP_WDT_WDT_STG2    0x00000007
-#define LP_WDT_WDT_STG2_M  ((LP_WDT_WDT_STG2_V)<<(LP_WDT_WDT_STG2_S))
-#define LP_WDT_WDT_STG2_V  0x7
-#define LP_WDT_WDT_STG2_S  22
-/* LP_WDT_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
-reset stage en.*/
-#define LP_WDT_WDT_STG3    0x00000007
-#define LP_WDT_WDT_STG3_M  ((LP_WDT_WDT_STG3_V)<<(LP_WDT_WDT_STG3_S))
-#define LP_WDT_WDT_STG3_V  0x7
-#define LP_WDT_WDT_STG3_S  19
-/* LP_WDT_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
-/*description: CPU reset counter length.*/
-#define LP_WDT_WDT_CPU_RESET_LENGTH    0x00000007
-#define LP_WDT_WDT_CPU_RESET_LENGTH_M  ((LP_WDT_WDT_CPU_RESET_LENGTH_V)<<(LP_WDT_WDT_CPU_RESET_LENGTH_S))
-#define LP_WDT_WDT_CPU_RESET_LENGTH_V  0x7
-#define LP_WDT_WDT_CPU_RESET_LENGTH_S  16
-/* LP_WDT_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
-/*description: system reset counter length.*/
-#define LP_WDT_WDT_SYS_RESET_LENGTH    0x00000007
-#define LP_WDT_WDT_SYS_RESET_LENGTH_M  ((LP_WDT_WDT_SYS_RESET_LENGTH_V)<<(LP_WDT_WDT_SYS_RESET_LENGTH_S))
-#define LP_WDT_WDT_SYS_RESET_LENGTH_V  0x7
-#define LP_WDT_WDT_SYS_RESET_LENGTH_S  13
-/* LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
-/*description: enable WDT in flash boot.*/
+/** LP_WDT_CONFIG0_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
+/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_PAUSE_IN_SLP    (BIT(9))
+#define LP_WDT_WDT_PAUSE_IN_SLP_M  (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
+#define LP_WDT_WDT_PAUSE_IN_SLP_V  0x00000001U
+#define LP_WDT_WDT_PAUSE_IN_SLP_S  9
+/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_APPCPU_RESET_EN    (BIT(10))
+#define LP_WDT_WDT_APPCPU_RESET_EN_M  (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
+#define LP_WDT_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define LP_WDT_WDT_APPCPU_RESET_EN_S  10
+/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_PROCPU_RESET_EN    (BIT(11))
+#define LP_WDT_WDT_PROCPU_RESET_EN_M  (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
+#define LP_WDT_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define LP_WDT_WDT_PROCPU_RESET_EN_S  11
+/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
+ *  need_des
+ */
 #define LP_WDT_WDT_FLASHBOOT_MOD_EN    (BIT(12))
-#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
-#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M  (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
 #define LP_WDT_WDT_FLASHBOOT_MOD_EN_S  12
-/* LP_WDT_WDT_PAUSE_IN_SLP : R/W ;bitpos:[11] ;default: 1'd1 ; */
-/*description: pause WDT in sleep.*/
-#define LP_WDT_WDT_PAUSE_IN_SLP    (BIT(11))
-#define LP_WDT_WDT_PAUSE_IN_SLP_M  (BIT(11))
-#define LP_WDT_WDT_PAUSE_IN_SLP_V  0x1
-#define LP_WDT_WDT_PAUSE_IN_SLP_S  11
-/* LP_WDT_WDT_CHIP_RESET_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: wdt reset whole chip enable.*/
-#define LP_WDT_WDT_CHIP_RESET_EN    (BIT(10))
-#define LP_WDT_WDT_CHIP_RESET_EN_M  (BIT(10))
-#define LP_WDT_WDT_CHIP_RESET_EN_V  0x1
-#define LP_WDT_WDT_CHIP_RESET_EN_S  10
-/* LP_WDT_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[9:2] ;default: 8'd20 ; */
-/*description: chip reset siginal pulse width.*/
-#define LP_WDT_WDT_CHIP_RESET_WIDTH    0x000000FF
-#define LP_WDT_WDT_CHIP_RESET_WIDTH_M  ((LP_WDT_WDT_CHIP_RESET_WIDTH_V)<<(LP_WDT_WDT_CHIP_RESET_WIDTH_S))
-#define LP_WDT_WDT_CHIP_RESET_WIDTH_V  0xFF
-#define LP_WDT_WDT_CHIP_RESET_WIDTH_S  2
+/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_SYS_RESET_LENGTH    0x00000007U
+#define LP_WDT_WDT_SYS_RESET_LENGTH_M  (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
+#define LP_WDT_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define LP_WDT_WDT_SYS_RESET_LENGTH_S  13
+/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_CPU_RESET_LENGTH    0x00000007U
+#define LP_WDT_WDT_CPU_RESET_LENGTH_M  (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
+#define LP_WDT_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define LP_WDT_WDT_CPU_RESET_LENGTH_S  16
+/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG3    0x00000007U
+#define LP_WDT_WDT_STG3_M  (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
+#define LP_WDT_WDT_STG3_V  0x00000007U
+#define LP_WDT_WDT_STG3_S  19
+/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG2    0x00000007U
+#define LP_WDT_WDT_STG2_M  (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
+#define LP_WDT_WDT_STG2_V  0x00000007U
+#define LP_WDT_WDT_STG2_S  22
+/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG1    0x00000007U
+#define LP_WDT_WDT_STG1_M  (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
+#define LP_WDT_WDT_STG1_V  0x00000007U
+#define LP_WDT_WDT_STG1_S  25
+/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG0    0x00000007U
+#define LP_WDT_WDT_STG0_M  (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
+#define LP_WDT_WDT_STG0_V  0x00000007U
+#define LP_WDT_WDT_STG0_S  28
+/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_EN    (BIT(31))
+#define LP_WDT_WDT_EN_M  (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
+#define LP_WDT_WDT_EN_V  0x00000001U
+#define LP_WDT_WDT_EN_S  31
 
-#define LP_WDT_RTC_WDTCPURST_REG          (DR_REG_LP_WDT_BASE + 0x4)
-/* LP_WDT_WDT_CORE0CPU_RESET_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: enable WDT reset CORE0 CPU.*/
-#define LP_WDT_WDT_CORE0CPU_RESET_EN    (BIT(31))
-#define LP_WDT_WDT_CORE0CPU_RESET_EN_M  (BIT(31))
-#define LP_WDT_WDT_CORE0CPU_RESET_EN_V  0x1
-#define LP_WDT_WDT_CORE0CPU_RESET_EN_S  31
-/* LP_WDT_WDT_CORE1CPU_RESET_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: enable WDT reset CORE1 CPU.*/
-#define LP_WDT_WDT_CORE1CPU_RESET_EN    (BIT(30))
-#define LP_WDT_WDT_CORE1CPU_RESET_EN_M  (BIT(30))
-#define LP_WDT_WDT_CORE1CPU_RESET_EN_V  0x1
-#define LP_WDT_WDT_CORE1CPU_RESET_EN_S  30
-/* LP_WDT_WDT_CORE2CPU_RESET_EN : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: enable WDT reset CORE2 CPU.*/
-#define LP_WDT_WDT_CORE2CPU_RESET_EN    (BIT(29))
-#define LP_WDT_WDT_CORE2CPU_RESET_EN_M  (BIT(29))
-#define LP_WDT_WDT_CORE2CPU_RESET_EN_V  0x1
-#define LP_WDT_WDT_CORE2CPU_RESET_EN_S  29
-/* LP_WDT_WDT_CORE3CPU_RESET_EN : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: enable WDT reset CORE3 CPU.*/
-#define LP_WDT_WDT_CORE3CPU_RESET_EN    (BIT(28))
-#define LP_WDT_WDT_CORE3CPU_RESET_EN_M  (BIT(28))
-#define LP_WDT_WDT_CORE3CPU_RESET_EN_V  0x1
-#define LP_WDT_WDT_CORE3CPU_RESET_EN_S  28
-/* LP_WDT_WDT_LP_CPU_RESET_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: enable WDT reset LP CPU.*/
-#define LP_WDT_WDT_LP_CPU_RESET_EN    (BIT(27))
-#define LP_WDT_WDT_LP_CPU_RESET_EN_M  (BIT(27))
-#define LP_WDT_WDT_LP_CPU_RESET_EN_V  0x1
-#define LP_WDT_WDT_LP_CPU_RESET_EN_S  27
-/* LP_WDT_WDT_LP_PERI_RESET_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: enable WDT reset LP PERI.*/
-#define LP_WDT_WDT_LP_PERI_RESET_EN    (BIT(26))
-#define LP_WDT_WDT_LP_PERI_RESET_EN_M  (BIT(26))
-#define LP_WDT_WDT_LP_PERI_RESET_EN_V  0x1
-#define LP_WDT_WDT_LP_PERI_RESET_EN_S  26
-
-#define LP_WDT_RTC_WDTCONFIG1_REG          (DR_REG_LP_WDT_BASE + 0x8)
-/* LP_WDT_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
-/*description: .*/
-#define LP_WDT_WDT_STG0_HOLD    0xFFFFFFFF
-#define LP_WDT_WDT_STG0_HOLD_M  ((LP_WDT_WDT_STG0_HOLD_V)<<(LP_WDT_WDT_STG0_HOLD_S))
-#define LP_WDT_WDT_STG0_HOLD_V  0xFFFFFFFF
+/** LP_WDT_CONFIG1_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
+/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG0_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG0_HOLD_M  (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
+#define LP_WDT_WDT_STG0_HOLD_V  0xFFFFFFFFU
 #define LP_WDT_WDT_STG0_HOLD_S  0
 
-#define LP_WDT_RTC_WDTCONFIG2_REG          (DR_REG_LP_WDT_BASE + 0xC)
-/* LP_WDT_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
-/*description: .*/
-#define LP_WDT_WDT_STG1_HOLD    0xFFFFFFFF
-#define LP_WDT_WDT_STG1_HOLD_M  ((LP_WDT_WDT_STG1_HOLD_V)<<(LP_WDT_WDT_STG1_HOLD_S))
-#define LP_WDT_WDT_STG1_HOLD_V  0xFFFFFFFF
+/** LP_WDT_CONFIG2_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
+/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG1_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG1_HOLD_M  (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
+#define LP_WDT_WDT_STG1_HOLD_V  0xFFFFFFFFU
 #define LP_WDT_WDT_STG1_HOLD_S  0
 
-#define LP_WDT_RTC_WDTCONFIG3_REG          (DR_REG_LP_WDT_BASE + 0x10)
-/* LP_WDT_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: .*/
-#define LP_WDT_WDT_STG2_HOLD    0xFFFFFFFF
-#define LP_WDT_WDT_STG2_HOLD_M  ((LP_WDT_WDT_STG2_HOLD_V)<<(LP_WDT_WDT_STG2_HOLD_S))
-#define LP_WDT_WDT_STG2_HOLD_V  0xFFFFFFFF
+/** LP_WDT_CONFIG3_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
+/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG2_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG2_HOLD_M  (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
+#define LP_WDT_WDT_STG2_HOLD_V  0xFFFFFFFFU
 #define LP_WDT_WDT_STG2_HOLD_S  0
 
-#define LP_WDT_RTC_WDTCONFIG4_REG          (DR_REG_LP_WDT_BASE + 0x14)
-/* LP_WDT_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: .*/
-#define LP_WDT_WDT_STG3_HOLD    0xFFFFFFFF
-#define LP_WDT_WDT_STG3_HOLD_M  ((LP_WDT_WDT_STG3_HOLD_V)<<(LP_WDT_WDT_STG3_HOLD_S))
-#define LP_WDT_WDT_STG3_HOLD_V  0xFFFFFFFF
+/** LP_WDT_CONFIG4_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
+/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG3_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG3_HOLD_M  (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
+#define LP_WDT_WDT_STG3_HOLD_V  0xFFFFFFFFU
 #define LP_WDT_WDT_STG3_HOLD_S  0
 
-#define LP_WDT_RTC_WDTFEED_REG          (DR_REG_LP_WDT_BASE + 0x18)
-/* LP_WDT_RTC_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
-/*description: .*/
-#define LP_WDT_RTC_WDT_FEED    (BIT(31))
-#define LP_WDT_RTC_WDT_FEED_M  (BIT(31))
-#define LP_WDT_RTC_WDT_FEED_V  0x1
-#define LP_WDT_RTC_WDT_FEED_S  31
+/** LP_WDT_FEED_REG register
+ *  need_des
+ */
+#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
+/** LP_WDT_FEED : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_FEED    (BIT(31))
+#define LP_WDT_FEED_M  (LP_WDT_FEED_V << LP_WDT_FEED_S)
+#define LP_WDT_FEED_V  0x00000001U
+#define LP_WDT_FEED_S  31
 
-#define LP_WDT_RTC_WDTWPROTECT_REG          (DR_REG_LP_WDT_BASE + 0x1C)
-/* LP_WDT_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
-/*description: .*/
-#define LP_WDT_WDT_WKEY    0xFFFFFFFF
-#define LP_WDT_WDT_WKEY_M  ((LP_WDT_WDT_WKEY_V)<<(LP_WDT_WDT_WKEY_S))
-#define LP_WDT_WDT_WKEY_V  0xFFFFFFFF
+/** LP_WDT_WPROTECT_REG register
+ *  need_des
+ */
+#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
+/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_WKEY    0xFFFFFFFFU
+#define LP_WDT_WDT_WKEY_M  (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
+#define LP_WDT_WDT_WKEY_V  0xFFFFFFFFU
 #define LP_WDT_WDT_WKEY_S  0
 
-#define LP_WDT_RTC_SWD_CONF_REG          (DR_REG_LP_WDT_BASE + 0x20)
-/* LP_WDT_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: automatically feed swd when int comes.*/
-#define LP_WDT_SWD_AUTO_FEED_EN    (BIT(31))
-#define LP_WDT_SWD_AUTO_FEED_EN_M  (BIT(31))
-#define LP_WDT_SWD_AUTO_FEED_EN_V  0x1
-#define LP_WDT_SWD_AUTO_FEED_EN_S  31
-/* LP_WDT_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: disabel SWD.*/
-#define LP_WDT_SWD_DISABLE    (BIT(30))
-#define LP_WDT_SWD_DISABLE_M  (BIT(30))
-#define LP_WDT_SWD_DISABLE_V  0x1
-#define LP_WDT_SWD_DISABLE_S  30
-/* LP_WDT_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Sw feed swd.*/
-#define LP_WDT_SWD_FEED    (BIT(29))
-#define LP_WDT_SWD_FEED_M  (BIT(29))
-#define LP_WDT_SWD_FEED_V  0x1
-#define LP_WDT_SWD_FEED_S  29
-/* LP_WDT_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: reset swd reset flag.*/
-#define LP_WDT_SWD_RST_FLAG_CLR    (BIT(28))
-#define LP_WDT_SWD_RST_FLAG_CLR_M  (BIT(28))
-#define LP_WDT_SWD_RST_FLAG_CLR_V  0x1
-#define LP_WDT_SWD_RST_FLAG_CLR_S  28
-/* LP_WDT_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
-/*description: adjust signal width send to swd.*/
-#define LP_WDT_SWD_SIGNAL_WIDTH    0x000003FF
-#define LP_WDT_SWD_SIGNAL_WIDTH_M  ((LP_WDT_SWD_SIGNAL_WIDTH_V)<<(LP_WDT_SWD_SIGNAL_WIDTH_S))
-#define LP_WDT_SWD_SIGNAL_WIDTH_V  0x3FF
-#define LP_WDT_SWD_SIGNAL_WIDTH_S  18
-/* LP_WDT_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: swd interrupt for feeding.*/
-#define LP_WDT_SWD_FEED_INT    (BIT(1))
-#define LP_WDT_SWD_FEED_INT_M  (BIT(1))
-#define LP_WDT_SWD_FEED_INT_V  0x1
-#define LP_WDT_SWD_FEED_INT_S  1
-/* LP_WDT_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: swd reset flag.*/
+/** LP_WDT_SWD_CONFIG_REG register
+ *  need_des
+ */
+#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
+/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
 #define LP_WDT_SWD_RESET_FLAG    (BIT(0))
-#define LP_WDT_SWD_RESET_FLAG_M  (BIT(0))
-#define LP_WDT_SWD_RESET_FLAG_V  0x1
+#define LP_WDT_SWD_RESET_FLAG_M  (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
+#define LP_WDT_SWD_RESET_FLAG_V  0x00000001U
 #define LP_WDT_SWD_RESET_FLAG_S  0
+/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_AUTO_FEED_EN    (BIT(18))
+#define LP_WDT_SWD_AUTO_FEED_EN_M  (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
+#define LP_WDT_SWD_AUTO_FEED_EN_V  0x00000001U
+#define LP_WDT_SWD_AUTO_FEED_EN_S  18
+/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_RST_FLAG_CLR    (BIT(19))
+#define LP_WDT_SWD_RST_FLAG_CLR_M  (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
+#define LP_WDT_SWD_RST_FLAG_CLR_V  0x00000001U
+#define LP_WDT_SWD_RST_FLAG_CLR_S  19
+/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
+ *  need_des
+ */
+#define LP_WDT_SWD_SIGNAL_WIDTH    0x000003FFU
+#define LP_WDT_SWD_SIGNAL_WIDTH_M  (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
+#define LP_WDT_SWD_SIGNAL_WIDTH_V  0x000003FFU
+#define LP_WDT_SWD_SIGNAL_WIDTH_S  20
+/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_DISABLE    (BIT(30))
+#define LP_WDT_SWD_DISABLE_M  (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
+#define LP_WDT_SWD_DISABLE_V  0x00000001U
+#define LP_WDT_SWD_DISABLE_S  30
+/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_FEED    (BIT(31))
+#define LP_WDT_SWD_FEED_M  (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
+#define LP_WDT_SWD_FEED_V  0x00000001U
+#define LP_WDT_SWD_FEED_S  31
 
-#define LP_WDT_RTC_SWD_WPROTECT_REG          (DR_REG_LP_WDT_BASE + 0x24)
-/* LP_WDT_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
-/*description: swd write protect.*/
-#define LP_WDT_SWD_WKEY    0xFFFFFFFF
-#define LP_WDT_SWD_WKEY_M  ((LP_WDT_SWD_WKEY_V)<<(LP_WDT_SWD_WKEY_S))
-#define LP_WDT_SWD_WKEY_V  0xFFFFFFFF
+/** LP_WDT_SWD_WPROTECT_REG register
+ *  need_des
+ */
+#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
+/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_WKEY    0xFFFFFFFFU
+#define LP_WDT_SWD_WKEY_M  (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
+#define LP_WDT_SWD_WKEY_V  0xFFFFFFFFU
 #define LP_WDT_SWD_WKEY_S  0
 
-#define LP_WDT_WDT_CLK_EN_REG          (DR_REG_LP_WDT_BASE + 0x28)
-/* LP_WDT_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define LP_WDT_CLK_EN    (BIT(0))
-#define LP_WDT_CLK_EN_M  (BIT(0))
-#define LP_WDT_CLK_EN_V  0x1
-#define LP_WDT_CLK_EN_S  0
+/** LP_WDT_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
+/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_RAW    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_RAW_M  (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
+#define LP_WDT_SUPER_WDT_INT_RAW_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_RAW_S  30
+/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_RAW    (BIT(31))
+#define LP_WDT_LP_WDT_INT_RAW_M  (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
+#define LP_WDT_LP_WDT_INT_RAW_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_RAW_S  31
 
-#define LP_WDT_INT_ENA_RTC_W1TS_REG          (DR_REG_LP_WDT_BASE + 0x2C)
-/* LP_WDT_RTC_SWD_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define LP_WDT_RTC_SWD_INT_ENA_W1TS    (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ENA_W1TS_M  (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ENA_W1TS_V  0x1
-#define LP_WDT_RTC_SWD_INT_ENA_W1TS_S  1
-/* LP_WDT_RTC_WDT_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define LP_WDT_RTC_WDT_INT_ENA_W1TS    (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ENA_W1TS_M  (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ENA_W1TS_V  0x1
-#define LP_WDT_RTC_WDT_INT_ENA_W1TS_S  0
+/** LP_WDT_INT_ST_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
+/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_ST    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_ST_M  (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
+#define LP_WDT_SUPER_WDT_INT_ST_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_ST_S  30
+/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_ST    (BIT(31))
+#define LP_WDT_LP_WDT_INT_ST_M  (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
+#define LP_WDT_LP_WDT_INT_ST_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_ST_S  31
 
-#define LP_WDT_INT_ENA_RTC_W1TC_REG          (DR_REG_LP_WDT_BASE + 0x30)
-/* LP_WDT_RTC_SWD_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define LP_WDT_RTC_SWD_INT_ENA_W1TC    (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ENA_W1TC_M  (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ENA_W1TC_V  0x1
-#define LP_WDT_RTC_SWD_INT_ENA_W1TC_S  1
-/* LP_WDT_RTC_WDT_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define LP_WDT_RTC_WDT_INT_ENA_W1TC    (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ENA_W1TC_M  (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ENA_W1TC_V  0x1
-#define LP_WDT_RTC_WDT_INT_ENA_W1TC_S  0
+/** LP_WDT_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
+/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_ENA    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_ENA_M  (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
+#define LP_WDT_SUPER_WDT_INT_ENA_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_ENA_S  30
+/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_ENA    (BIT(31))
+#define LP_WDT_LP_WDT_INT_ENA_M  (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
+#define LP_WDT_LP_WDT_INT_ENA_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_ENA_S  31
 
-#define LP_WDT_INT_ENA_RTC_REG          (DR_REG_LP_WDT_BASE + 0x34)
-/* LP_WDT_RTC_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: enable xtal32k_dead  interrupt.*/
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA    (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_M  (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_V  0x1
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_S  2
-/* LP_WDT_RTC_SWD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define LP_WDT_RTC_SWD_INT_ENA    (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ENA_M  (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ENA_V  0x1
-#define LP_WDT_RTC_SWD_INT_ENA_S  1
-/* LP_WDT_RTC_WDT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define LP_WDT_RTC_WDT_INT_ENA    (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ENA_M  (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ENA_V  0x1
-#define LP_WDT_RTC_WDT_INT_ENA_S  0
-
-#define LP_WDT_INT_RAW_RTC_REG          (DR_REG_LP_WDT_BASE + 0x38)
-/* LP_WDT_RTC_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: xtal32k dead detection interrupt raw.*/
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW    (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_M  (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_V  0x1
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_S  2
-/* LP_WDT_RTC_SWD_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: super watch dog interrupt raw.*/
-#define LP_WDT_RTC_SWD_INT_RAW    (BIT(1))
-#define LP_WDT_RTC_SWD_INT_RAW_M  (BIT(1))
-#define LP_WDT_RTC_SWD_INT_RAW_V  0x1
-#define LP_WDT_RTC_SWD_INT_RAW_S  1
-/* LP_WDT_RTC_WDT_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt raw.*/
-#define LP_WDT_RTC_WDT_INT_RAW    (BIT(0))
-#define LP_WDT_RTC_WDT_INT_RAW_M  (BIT(0))
-#define LP_WDT_RTC_WDT_INT_RAW_V  0x1
-#define LP_WDT_RTC_WDT_INT_RAW_S  0
-
-#define LP_WDT_INT_SWD_ST_RTC_REG          (DR_REG_LP_WDT_BASE + 0x3C)
-/* LP_WDT_RTC_XTAL32K_DEAD_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: xtal32k dead detection interrupt state.*/
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST    (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_M  (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_V  0x1
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_S  2
-/* LP_WDT_RTC_SWD_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: super watch dog interrupt state.*/
-#define LP_WDT_RTC_SWD_INT_ST    (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ST_M  (BIT(1))
-#define LP_WDT_RTC_SWD_INT_ST_V  0x1
-#define LP_WDT_RTC_SWD_INT_ST_S  1
-/* LP_WDT_RTC_WDT_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: watch dog interrupt state.*/
-#define LP_WDT_RTC_WDT_INT_ST    (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ST_M  (BIT(0))
-#define LP_WDT_RTC_WDT_INT_ST_V  0x1
-#define LP_WDT_RTC_WDT_INT_ST_S  0
-
-#define LP_WDT_INT_CLR_RTC_REG          (DR_REG_LP_WDT_BASE + 0x40)
-/* LP_WDT_RTC_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state.*/
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR    (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_M  (BIT(2))
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_V  0x1
-#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_S  2
-/* LP_WDT_RTC_SWD_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Clear super watch dog interrupt state.*/
-#define LP_WDT_RTC_SWD_INT_CLR    (BIT(1))
-#define LP_WDT_RTC_SWD_INT_CLR_M  (BIT(1))
-#define LP_WDT_RTC_SWD_INT_CLR_V  0x1
-#define LP_WDT_RTC_SWD_INT_CLR_S  1
-/* LP_WDT_RTC_WDT_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state.*/
-#define LP_WDT_RTC_WDT_INT_CLR    (BIT(0))
-#define LP_WDT_RTC_WDT_INT_CLR_M  (BIT(0))
-#define LP_WDT_RTC_WDT_INT_CLR_V  0x1
-#define LP_WDT_RTC_WDT_INT_CLR_S  0
-
-#define LP_WDT_RTC_EXT_XTL_CONF_REG          (DR_REG_LP_WDT_BASE + 0x44)
-/* LP_WDT_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define LP_WDT_XTL_EXT_CTR_EN    (BIT(31))
-#define LP_WDT_XTL_EXT_CTR_EN_M  (BIT(31))
-#define LP_WDT_XTL_EXT_CTR_EN_V  0x1
-#define LP_WDT_XTL_EXT_CTR_EN_S  31
-/* LP_WDT_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: power down XTAL at high level; 1: power down XTAL at low level.*/
-#define LP_WDT_XTL_EXT_CTR_LV    (BIT(30))
-#define LP_WDT_XTL_EXT_CTR_LV_M  (BIT(30))
-#define LP_WDT_XTL_EXT_CTR_LV_V  0x1
-#define LP_WDT_XTL_EXT_CTR_LV_S  30
-/* LP_WDT_RTC_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C.*/
-#define LP_WDT_RTC_XTAL32K_GPIO_SEL    (BIT(23))
-#define LP_WDT_RTC_XTAL32K_GPIO_SEL_M  (BIT(23))
-#define LP_WDT_RTC_XTAL32K_GPIO_SEL_V  0x1
-#define LP_WDT_RTC_XTAL32K_GPIO_SEL_S  23
-/* LP_WDT_RTC_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
-/*description: state of 32k_wdt.*/
-#define LP_WDT_RTC_WDT_STATE    0x00000007
-#define LP_WDT_RTC_WDT_STATE_M  ((LP_WDT_RTC_WDT_STATE_V)<<(LP_WDT_RTC_WDT_STATE_S))
-#define LP_WDT_RTC_WDT_STATE_V  0x7
-#define LP_WDT_RTC_WDT_STATE_S  20
-/* LP_WDT_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
-/*description: DAC_XTAL_32K.*/
-#define LP_WDT_DAC_XTAL_32K    0x00000007
-#define LP_WDT_DAC_XTAL_32K_M  ((LP_WDT_DAC_XTAL_32K_V)<<(LP_WDT_DAC_XTAL_32K_S))
-#define LP_WDT_DAC_XTAL_32K_V  0x7
-#define LP_WDT_DAC_XTAL_32K_S  17
-/* LP_WDT_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: XPD_XTAL_32K.*/
-#define LP_WDT_XPD_XTAL_32K    (BIT(16))
-#define LP_WDT_XPD_XTAL_32K_M  (BIT(16))
-#define LP_WDT_XPD_XTAL_32K_V  0x1
-#define LP_WDT_XPD_XTAL_32K_S  16
-/* LP_WDT_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
-/*description: DRES_XTAL_32K.*/
-#define LP_WDT_DRES_XTAL_32K    0x00000007
-#define LP_WDT_DRES_XTAL_32K_M  ((LP_WDT_DRES_XTAL_32K_V)<<(LP_WDT_DRES_XTAL_32K_S))
-#define LP_WDT_DRES_XTAL_32K_V  0x7
-#define LP_WDT_DRES_XTAL_32K_S  13
-/* LP_WDT_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: xtal_32k gm control.*/
-#define LP_WDT_DGM_XTAL_32K    0x00000007
-#define LP_WDT_DGM_XTAL_32K_M  ((LP_WDT_DGM_XTAL_32K_V)<<(LP_WDT_DGM_XTAL_32K_S))
-#define LP_WDT_DGM_XTAL_32K_V  0x7
-#define LP_WDT_DGM_XTAL_32K_S  10
-/* LP_WDT_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 0: single-end buffer 1: differential buffer.*/
-#define LP_WDT_DBUF_XTAL_32K    (BIT(9))
-#define LP_WDT_DBUF_XTAL_32K_M  (BIT(9))
-#define LP_WDT_DBUF_XTAL_32K_V  0x1
-#define LP_WDT_DBUF_XTAL_32K_S  9
-/* LP_WDT_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: apply an internal clock to help xtal 32k to start.*/
-#define LP_WDT_ENCKINIT_XTAL_32K    (BIT(8))
-#define LP_WDT_ENCKINIT_XTAL_32K_M  (BIT(8))
-#define LP_WDT_ENCKINIT_XTAL_32K_V  0x1
-#define LP_WDT_ENCKINIT_XTAL_32K_S  8
-/* LP_WDT_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: Xtal 32k xpd control by sw or fsm.*/
-#define LP_WDT_XTAL32K_XPD_FORCE    (BIT(7))
-#define LP_WDT_XTAL32K_XPD_FORCE_M  (BIT(7))
-#define LP_WDT_XTAL32K_XPD_FORCE_V  0x1
-#define LP_WDT_XTAL32K_XPD_FORCE_S  7
-/* LP_WDT_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: xtal 32k switch back xtal when xtal is restarted.*/
-#define LP_WDT_XTAL32K_AUTO_RETURN    (BIT(6))
-#define LP_WDT_XTAL32K_AUTO_RETURN_M  (BIT(6))
-#define LP_WDT_XTAL32K_AUTO_RETURN_V  0x1
-#define LP_WDT_XTAL32K_AUTO_RETURN_S  6
-/* LP_WDT_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: xtal 32k restart xtal when xtal is dead.*/
-#define LP_WDT_XTAL32K_AUTO_RESTART    (BIT(5))
-#define LP_WDT_XTAL32K_AUTO_RESTART_M  (BIT(5))
-#define LP_WDT_XTAL32K_AUTO_RESTART_V  0x1
-#define LP_WDT_XTAL32K_AUTO_RESTART_S  5
-/* LP_WDT_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: xtal 32k switch to back up clock when xtal is dead.*/
-#define LP_WDT_XTAL32K_AUTO_BACKUP    (BIT(4))
-#define LP_WDT_XTAL32K_AUTO_BACKUP_M  (BIT(4))
-#define LP_WDT_XTAL32K_AUTO_BACKUP_V  0x1
-#define LP_WDT_XTAL32K_AUTO_BACKUP_S  4
-/* LP_WDT_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: xtal 32k external xtal clock force on.*/
-#define LP_WDT_XTAL32K_EXT_CLK_FO    (BIT(3))
-#define LP_WDT_XTAL32K_EXT_CLK_FO_M  (BIT(3))
-#define LP_WDT_XTAL32K_EXT_CLK_FO_V  0x1
-#define LP_WDT_XTAL32K_EXT_CLK_FO_S  3
-/* LP_WDT_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog sw reset.*/
-#define LP_WDT_XTAL32K_WDT_RESET    (BIT(2))
-#define LP_WDT_XTAL32K_WDT_RESET_M  (BIT(2))
-#define LP_WDT_XTAL32K_WDT_RESET_V  0x1
-#define LP_WDT_XTAL32K_WDT_RESET_S  2
-/* LP_WDT_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog clock force on.*/
-#define LP_WDT_XTAL32K_WDT_CLK_FO    (BIT(1))
-#define LP_WDT_XTAL32K_WDT_CLK_FO_M  (BIT(1))
-#define LP_WDT_XTAL32K_WDT_CLK_FO_V  0x1
-#define LP_WDT_XTAL32K_WDT_CLK_FO_S  1
-/* LP_WDT_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog enable.*/
-#define LP_WDT_XTAL32K_WDT_EN    (BIT(0))
-#define LP_WDT_XTAL32K_WDT_EN_M  (BIT(0))
-#define LP_WDT_XTAL32K_WDT_EN_V  0x1
-#define LP_WDT_XTAL32K_WDT_EN_S  0
-
-#define LP_WDT_RTC_XTAL32K_CLK_FACTOR_REG          (DR_REG_LP_WDT_BASE + 0x48)
-/* LP_WDT_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: xtal 32k watch dog backup clock factor.*/
-#define LP_WDT_XTAL32K_CLK_FACTOR    0xFFFFFFFF
-#define LP_WDT_XTAL32K_CLK_FACTOR_M  ((LP_WDT_XTAL32K_CLK_FACTOR_V)<<(LP_WDT_XTAL32K_CLK_FACTOR_S))
-#define LP_WDT_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
-#define LP_WDT_XTAL32K_CLK_FACTOR_S  0
-
-#define LP_WDT_RTC_XTAL32K_CONF_REG          (DR_REG_LP_WDT_BASE + 0x5C)
-/* LP_WDT_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: if restarted xtal32k period is smaller than this, it is regarded as stable.*/
-#define LP_WDT_XTAL32K_STABLE_THRES    0x0000000F
-#define LP_WDT_XTAL32K_STABLE_THRES_M  ((LP_WDT_XTAL32K_STABLE_THRES_V)<<(LP_WDT_XTAL32K_STABLE_THRES_S))
-#define LP_WDT_XTAL32K_STABLE_THRES_V  0xF
-#define LP_WDT_XTAL32K_STABLE_THRES_S  28
-/* LP_WDT_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
-/*description: If no clock detected for this amount of time,32k is regarded as dead.*/
-#define LP_WDT_XTAL32K_WDT_TIMEOUT    0x000000FF
-#define LP_WDT_XTAL32K_WDT_TIMEOUT_M  ((LP_WDT_XTAL32K_WDT_TIMEOUT_V)<<(LP_WDT_XTAL32K_WDT_TIMEOUT_S))
-#define LP_WDT_XTAL32K_WDT_TIMEOUT_V  0xFF
-#define LP_WDT_XTAL32K_WDT_TIMEOUT_S  20
-/* LP_WDT_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
-/*description: cycles to wait to repower on xtal 32k.*/
-#define LP_WDT_XTAL32K_RESTART_WAIT    0x0000FFFF
-#define LP_WDT_XTAL32K_RESTART_WAIT_M  ((LP_WDT_XTAL32K_RESTART_WAIT_V)<<(LP_WDT_XTAL32K_RESTART_WAIT_S))
-#define LP_WDT_XTAL32K_RESTART_WAIT_V  0xFFFF
-#define LP_WDT_XTAL32K_RESTART_WAIT_S  4
-/* LP_WDT_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: cycles to wait to return noral xtal 32k.*/
-#define LP_WDT_XTAL32K_RETURN_WAIT    0x0000000F
-#define LP_WDT_XTAL32K_RETURN_WAIT_M  ((LP_WDT_XTAL32K_RETURN_WAIT_V)<<(LP_WDT_XTAL32K_RETURN_WAIT_S))
-#define LP_WDT_XTAL32K_RETURN_WAIT_V  0xF
-#define LP_WDT_XTAL32K_RETURN_WAIT_S  0
-
-#define LP_WDT_RTC_EFUSE_FORCE_REG          (DR_REG_LP_WDT_BASE + 0x60)
-/* LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: lp_wdt flashboot en default choose efuse control bit.*/
-#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE    (BIT(1))
-#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_M  (BIT(1))
-#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_V  0x1
-#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_S  1
-/* LP_WDT_SWD_DISABLE_EFUSE_FORCE : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: swd disable default choose efuse control bit.*/
-#define LP_WDT_SWD_DISABLE_EFUSE_FORCE    (BIT(0))
-#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_M  (BIT(0))
-#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_V  0x1
-#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_S  0
+/** LP_WDT_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
+/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_CLR    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_CLR_M  (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
+#define LP_WDT_SUPER_WDT_INT_CLR_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_CLR_S  30
+/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_CLR    (BIT(31))
+#define LP_WDT_LP_WDT_INT_CLR_M  (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
+#define LP_WDT_LP_WDT_INT_CLR_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_CLR_S  31
 
+/** LP_WDT_DATE_REG register
+ *  need_des
+ */
+#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
+/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_DATE    0x7FFFFFFFU
+#define LP_WDT_LP_WDT_DATE_M  (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
+#define LP_WDT_LP_WDT_DATE_V  0x7FFFFFFFU
+#define LP_WDT_LP_WDT_DATE_S  0
+/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_CLK_EN    (BIT(31))
+#define LP_WDT_CLK_EN_M  (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
+#define LP_WDT_CLK_EN_V  0x00000001U
+#define LP_WDT_CLK_EN_S  31
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/lp_wdt_struct.h b/components/soc/esp32p4/include/soc/lp_wdt_struct.h
index 5d37d8ad9d..2e8976accd 100644
--- a/components/soc/esp32p4/include/soc/lp_wdt_struct.h
+++ b/components/soc/esp32p4/include/soc/lp_wdt_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,171 +10,301 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t reserved0                     :    2;
-            uint32_t wdt_chip_reset_width          :    8;  /*chip reset siginal pulse width*/
-            uint32_t wdt_chip_reset_en             :    1;  /*wdt reset whole chip enable*/
-            uint32_t wdt_pause_in_slp              :    1;  /*pause WDT in sleep*/
-            uint32_t wdt_flashboot_mod_en          :    1;  /*enable WDT in flash boot*/
-            uint32_t wdt_sys_reset_length          :    3;  /*system reset counter length*/
-            uint32_t wdt_cpu_reset_length          :    3;  /*CPU reset counter length*/
-            uint32_t wdt_stg3                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
-            uint32_t wdt_stg2                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
-            uint32_t wdt_stg1                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
-            uint32_t wdt_stg0                      :    3;  /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
-            uint32_t wdt_en                        :    1;
-        };
-        uint32_t val;
-    } wdtconfig0;
-    union {
-        struct {
-            uint32_t reserved0                     :    26;
-            uint32_t wdt_lp_peri_reset_en          :    1;  /*enable WDT reset LP PERI*/
-            uint32_t wdt_lp_cpu_reset_en           :    1;  /*enable WDT reset LP CPU*/
-            uint32_t wdt_core3cpu_reset_en         :    1;  /*enable WDT reset CORE3 CPU*/
-            uint32_t wdt_core2cpu_reset_en         :    1;  /*enable WDT reset CORE2 CPU*/
-            uint32_t wdt_core1cpu_reset_en         :    1;  /*enable WDT reset CORE1 CPU*/
-            uint32_t wdt_core0cpu_reset_en         :    1;  /*enable WDT reset CORE0 CPU*/
-        };
-        uint32_t val;
-    } wdtcpurst;
-    uint32_t wdtconfig1;
-    uint32_t wdtconfig2;
-    uint32_t wdtconfig3;
-    uint32_t wdtconfig4;
-    union {
-        struct {
-            uint32_t reserved0                     :    31;
-            uint32_t wdt_feed                      :    1;
-        };
-        uint32_t val;
-    } wdtfeed;
-    uint32_t wdtwprotect;
-    union {
-        struct {
-            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
-            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
-            uint32_t reserved2                     :    16;
-            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
-            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
-            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
-            uint32_t swd_disable                   :    1;  /*disabel SWD*/
-            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
-        };
-        uint32_t val;
-    } swd_conf;
-    uint32_t swd_wprotect;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } wdt_clk_en;
-    union {
-        struct {
-            uint32_t wdt                           :    1;  /*enable RTC WDT interrupt*/
-            uint32_t swd                           :    1;  /*enable super watch dog interrupt*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } int_ena_w1ts;
-    union {
-        struct {
-            uint32_t wdt                           :    1;  /*enable RTC WDT interrupt*/
-            uint32_t swd                           :    1;  /*enable super watch dog interrupt*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } int_ena_w1tc;
-    union {
-        struct {
-            uint32_t wdt                           :    1;  /*enable RTC WDT interrupt*/
-            uint32_t swd                           :    1;  /*enable super watch dog interrupt*/
-            uint32_t xtal32k_dead                  :    1;  /*enable xtal32k_dead  interrupt*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t wdt                           :    1;  /*RTC WDT interrupt raw*/
-            uint32_t swd                           :    1;  /*super watch dog interrupt raw*/
-            uint32_t xtal32k_dead                  :    1;  /*xtal32k dead detection interrupt raw*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t wdt                           :    1;  /*watch dog interrupt state*/
-            uint32_t swd                           :    1;  /*super watch dog interrupt state*/
-            uint32_t xtal32k_dead                  :    1;  /*xtal32k dead detection interrupt state*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } int_swd_st;
-    union {
-        struct {
-            uint32_t wdt                           :    1;  /*Clear RTC WDT interrupt state*/
-            uint32_t swd                           :    1;  /*Clear super watch dog interrupt state*/
-            uint32_t xtal32k_dead                  :    1;  /*Clear RTC WDT interrupt state*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t xtal32k_wdt_en                :    1;  /*xtal 32k watch dog enable*/
-            uint32_t xtal32k_wdt_clk_fo            :    1;  /*xtal 32k watch dog clock force on*/
-            uint32_t xtal32k_wdt_reset             :    1;  /*xtal 32k watch dog sw reset*/
-            uint32_t xtal32k_ext_clk_fo            :    1;  /*xtal 32k external xtal clock force on*/
-            uint32_t xtal32k_auto_backup           :    1;  /*xtal 32k switch to back up clock when xtal is dead*/
-            uint32_t xtal32k_auto_restart          :    1;  /*xtal 32k restart xtal when xtal is dead*/
-            uint32_t xtal32k_auto_return           :    1;  /*xtal 32k switch back xtal when xtal is restarted*/
-            uint32_t xtal32k_xpd_force             :    1;  /*Xtal 32k xpd control by sw or fsm*/
-            uint32_t enckinit_xtal_32k             :    1;  /*apply an internal clock to help xtal 32k to start*/
-            uint32_t dbuf_xtal_32k                 :    1;  /*0: single-end buffer 1: differential buffer*/
-            uint32_t dgm_xtal_32k                  :    3;  /*xtal_32k gm control*/
-            uint32_t dres_xtal_32k                 :    3;  /*DRES_XTAL_32K*/
-            uint32_t xpd_xtal_32k                  :    1;  /*XPD_XTAL_32K*/
-            uint32_t dac_xtal_32k                  :    3;  /*DAC_XTAL_32K*/
-            uint32_t wdt_state                     :    3;  /*state of 32k_wdt*/
-            uint32_t xtal32k_gpio_sel              :    1;  /*XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C*/
-            uint32_t reserved24                    :    6;
-            uint32_t xtl_ext_ctr_lv                :    1;  /*0: power down XTAL at high level; 1: power down XTAL at low level*/
-            uint32_t xtl_ext_ctr_en                :    1;
-        };
-        uint32_t val;
-    } ext_xtl_conf;
-    uint32_t xtal32k_clk_factor;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    union {
-        struct {
-            uint32_t xtal32k_return_wait           :    4;  /*cycles to wait to return noral xtal 32k*/
-            uint32_t xtal32k_restart_wait          :    16;  /*cycles to wait to repower on xtal 32k*/
-            uint32_t xtal32k_wdt_timeout           :    8;  /*If no clock detected for this amount of time,32k is regarded as dead*/
-            uint32_t xtal32k_stable_thres          :    4;  /*if restarted xtal32k period is smaller than this, it is regarded as stable*/
-        };
-        uint32_t val;
-    } xtal32k_conf;
-    union {
-        struct {
-            uint32_t swd_disable_efuse_force       :    1;  /*swd disable default choose efuse control bit*/
-            uint32_t wdt_flashboot_efuse_force     :    1;  /*lp_wdt flashboot en default choose efuse control bit*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } efuse_force;
+/** Group: configure_register */
+/** Type of config0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_pause_in_slp:1;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_appcpu_reset_en:1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_procpu_reset_en:1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_flashboot_mod_en:1;
+        /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_sys_reset_length:3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_cpu_reset_length:3;
+        /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg3:3;
+        /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg2:3;
+        /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg1:3;
+        /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg0:3;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_en:1;
+    };
+    uint32_t val;
+} lp_wdt_config0_reg_t;
+
+/** Type of config1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
+         *  need_des
+         */
+        uint32_t wdt_stg0_hold:32;
+    };
+    uint32_t val;
+} lp_wdt_config1_reg_t;
+
+/** Type of config2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
+         *  need_des
+         */
+        uint32_t wdt_stg1_hold:32;
+    };
+    uint32_t val;
+} lp_wdt_config2_reg_t;
+
+/** Type of config3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t wdt_stg2_hold:32;
+    };
+    uint32_t val;
+} lp_wdt_config3_reg_t;
+
+/** Type of config4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t wdt_stg3_hold:32;
+    };
+    uint32_t val;
+} lp_wdt_config4_reg_t;
+
+/** Type of feed register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** feed : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t feed:1;
+    };
+    uint32_t val;
+} lp_wdt_feed_reg_t;
+
+/** Type of wprotect register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_wkey:32;
+    };
+    uint32_t val;
+} lp_wdt_wprotect_reg_t;
+
+/** Type of swd_config register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** swd_reset_flag : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_reset_flag:1;
+        uint32_t reserved_1:17;
+        /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_auto_feed_en:1;
+        /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_rst_flag_clr:1;
+        /** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
+         *  need_des
+         */
+        uint32_t swd_signal_width:10;
+        /** swd_disable : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_disable:1;
+        /** swd_feed : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_feed:1;
+    };
+    uint32_t val;
+} lp_wdt_swd_config_reg_t;
+
+/** Type of swd_wprotect register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** swd_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_wkey:32;
+    };
+    uint32_t val;
+} lp_wdt_swd_wprotect_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_raw:1;
+        /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_raw:1;
+    };
+    uint32_t val;
+} lp_wdt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_st:1;
+        /** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_st:1;
+    };
+    uint32_t val;
+} lp_wdt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_ena:1;
+        /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_ena:1;
+    };
+    uint32_t val;
+} lp_wdt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_clr:1;
+        /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_clr:1;
+    };
+    uint32_t val;
+} lp_wdt_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
+         *  need_des
+         */
+        uint32_t lp_wdt_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_wdt_date_reg_t;
+
+
+typedef struct {
+    volatile lp_wdt_config0_reg_t config0;
+    volatile lp_wdt_config1_reg_t config1;
+    volatile lp_wdt_config2_reg_t config2;
+    volatile lp_wdt_config3_reg_t config3;
+    volatile lp_wdt_config4_reg_t config4;
+    volatile lp_wdt_feed_reg_t feed;
+    volatile lp_wdt_wprotect_reg_t wprotect;
+    volatile lp_wdt_swd_config_reg_t swd_config;
+    volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
+    volatile lp_wdt_int_raw_reg_t int_raw;
+    volatile lp_wdt_int_st_reg_t int_st;
+    volatile lp_wdt_int_ena_reg_t int_ena;
+    volatile lp_wdt_int_clr_reg_t int_clr;
+    uint32_t reserved_034[242];
+    volatile lp_wdt_date_reg_t date;
 } lp_wdt_dev_t;
 
 extern lp_wdt_dev_t LP_WDT;
 
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32p4/include/soc/rtc_wdt_reg.h b/components/soc/esp32p4/include/soc/rtc_wdt_reg.h
deleted file mode 100644
index 8d502d3f56..0000000000
--- a/components/soc/esp32p4/include/soc/rtc_wdt_reg.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** RTC_WDT_CONFIG0_REG register
- *  need_des
- */
-#define RTC_WDT_CONFIG0_REG (DR_REG_RTC_WDT_BASE + 0x0)
-/** RTC_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
- *  need_des
- */
-#define RTC_WDT_WDT_PAUSE_IN_SLP    (BIT(9))
-#define RTC_WDT_WDT_PAUSE_IN_SLP_M  (RTC_WDT_WDT_PAUSE_IN_SLP_V << RTC_WDT_WDT_PAUSE_IN_SLP_S)
-#define RTC_WDT_WDT_PAUSE_IN_SLP_V  0x00000001U
-#define RTC_WDT_WDT_PAUSE_IN_SLP_S  9
-/** RTC_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_APPCPU_RESET_EN    (BIT(10))
-#define RTC_WDT_WDT_APPCPU_RESET_EN_M  (RTC_WDT_WDT_APPCPU_RESET_EN_V << RTC_WDT_WDT_APPCPU_RESET_EN_S)
-#define RTC_WDT_WDT_APPCPU_RESET_EN_V  0x00000001U
-#define RTC_WDT_WDT_APPCPU_RESET_EN_S  10
-/** RTC_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_PROCPU_RESET_EN    (BIT(11))
-#define RTC_WDT_WDT_PROCPU_RESET_EN_M  (RTC_WDT_WDT_PROCPU_RESET_EN_V << RTC_WDT_WDT_PROCPU_RESET_EN_S)
-#define RTC_WDT_WDT_PROCPU_RESET_EN_V  0x00000001U
-#define RTC_WDT_WDT_PROCPU_RESET_EN_S  11
-/** RTC_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
- *  need_des
- */
-#define RTC_WDT_WDT_FLASHBOOT_MOD_EN    (BIT(12))
-#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_M  (RTC_WDT_WDT_FLASHBOOT_MOD_EN_V << RTC_WDT_WDT_FLASHBOOT_MOD_EN_S)
-#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
-#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_S  12
-/** RTC_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
- *  need_des
- */
-#define RTC_WDT_WDT_SYS_RESET_LENGTH    0x00000007U
-#define RTC_WDT_WDT_SYS_RESET_LENGTH_M  (RTC_WDT_WDT_SYS_RESET_LENGTH_V << RTC_WDT_WDT_SYS_RESET_LENGTH_S)
-#define RTC_WDT_WDT_SYS_RESET_LENGTH_V  0x00000007U
-#define RTC_WDT_WDT_SYS_RESET_LENGTH_S  13
-/** RTC_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
- *  need_des
- */
-#define RTC_WDT_WDT_CPU_RESET_LENGTH    0x00000007U
-#define RTC_WDT_WDT_CPU_RESET_LENGTH_M  (RTC_WDT_WDT_CPU_RESET_LENGTH_V << RTC_WDT_WDT_CPU_RESET_LENGTH_S)
-#define RTC_WDT_WDT_CPU_RESET_LENGTH_V  0x00000007U
-#define RTC_WDT_WDT_CPU_RESET_LENGTH_S  16
-/** RTC_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_STG3    0x00000007U
-#define RTC_WDT_WDT_STG3_M  (RTC_WDT_WDT_STG3_V << RTC_WDT_WDT_STG3_S)
-#define RTC_WDT_WDT_STG3_V  0x00000007U
-#define RTC_WDT_WDT_STG3_S  19
-/** RTC_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_STG2    0x00000007U
-#define RTC_WDT_WDT_STG2_M  (RTC_WDT_WDT_STG2_V << RTC_WDT_WDT_STG2_S)
-#define RTC_WDT_WDT_STG2_V  0x00000007U
-#define RTC_WDT_WDT_STG2_S  22
-/** RTC_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_STG1    0x00000007U
-#define RTC_WDT_WDT_STG1_M  (RTC_WDT_WDT_STG1_V << RTC_WDT_WDT_STG1_S)
-#define RTC_WDT_WDT_STG1_V  0x00000007U
-#define RTC_WDT_WDT_STG1_S  25
-/** RTC_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_STG0    0x00000007U
-#define RTC_WDT_WDT_STG0_M  (RTC_WDT_WDT_STG0_V << RTC_WDT_WDT_STG0_S)
-#define RTC_WDT_WDT_STG0_V  0x00000007U
-#define RTC_WDT_WDT_STG0_S  28
-/** RTC_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_EN    (BIT(31))
-#define RTC_WDT_WDT_EN_M  (RTC_WDT_WDT_EN_V << RTC_WDT_WDT_EN_S)
-#define RTC_WDT_WDT_EN_V  0x00000001U
-#define RTC_WDT_WDT_EN_S  31
-
-/** RTC_WDT_CONFIG1_REG register
- *  need_des
- */
-#define RTC_WDT_CONFIG1_REG (DR_REG_RTC_WDT_BASE + 0x4)
-/** RTC_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
- *  need_des
- */
-#define RTC_WDT_WDT_STG0_HOLD    0xFFFFFFFFU
-#define RTC_WDT_WDT_STG0_HOLD_M  (RTC_WDT_WDT_STG0_HOLD_V << RTC_WDT_WDT_STG0_HOLD_S)
-#define RTC_WDT_WDT_STG0_HOLD_V  0xFFFFFFFFU
-#define RTC_WDT_WDT_STG0_HOLD_S  0
-
-/** RTC_WDT_CONFIG2_REG register
- *  need_des
- */
-#define RTC_WDT_CONFIG2_REG (DR_REG_RTC_WDT_BASE + 0x8)
-/** RTC_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
- *  need_des
- */
-#define RTC_WDT_WDT_STG1_HOLD    0xFFFFFFFFU
-#define RTC_WDT_WDT_STG1_HOLD_M  (RTC_WDT_WDT_STG1_HOLD_V << RTC_WDT_WDT_STG1_HOLD_S)
-#define RTC_WDT_WDT_STG1_HOLD_V  0xFFFFFFFFU
-#define RTC_WDT_WDT_STG1_HOLD_S  0
-
-/** RTC_WDT_CONFIG3_REG register
- *  need_des
- */
-#define RTC_WDT_CONFIG3_REG (DR_REG_RTC_WDT_BASE + 0xc)
-/** RTC_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
- *  need_des
- */
-#define RTC_WDT_WDT_STG2_HOLD    0xFFFFFFFFU
-#define RTC_WDT_WDT_STG2_HOLD_M  (RTC_WDT_WDT_STG2_HOLD_V << RTC_WDT_WDT_STG2_HOLD_S)
-#define RTC_WDT_WDT_STG2_HOLD_V  0xFFFFFFFFU
-#define RTC_WDT_WDT_STG2_HOLD_S  0
-
-/** RTC_WDT_CONFIG4_REG register
- *  need_des
- */
-#define RTC_WDT_CONFIG4_REG (DR_REG_RTC_WDT_BASE + 0x10)
-/** RTC_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
- *  need_des
- */
-#define RTC_WDT_WDT_STG3_HOLD    0xFFFFFFFFU
-#define RTC_WDT_WDT_STG3_HOLD_M  (RTC_WDT_WDT_STG3_HOLD_V << RTC_WDT_WDT_STG3_HOLD_S)
-#define RTC_WDT_WDT_STG3_HOLD_V  0xFFFFFFFFU
-#define RTC_WDT_WDT_STG3_HOLD_S  0
-
-/** RTC_WDT_FEED_REG register
- *  need_des
- */
-#define RTC_WDT_FEED_REG (DR_REG_RTC_WDT_BASE + 0x14)
-/** RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_FEED    (BIT(31))
-#define RTC_WDT_FEED_M  (RTC_WDT_FEED_V << RTC_WDT_FEED_S)
-#define RTC_WDT_FEED_V  0x00000001U
-#define RTC_WDT_FEED_S  31
-
-/** RTC_WDT_WPROTECT_REG register
- *  need_des
- */
-#define RTC_WDT_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x18)
-/** RTC_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define RTC_WDT_WDT_WKEY    0xFFFFFFFFU
-#define RTC_WDT_WDT_WKEY_M  (RTC_WDT_WDT_WKEY_V << RTC_WDT_WDT_WKEY_S)
-#define RTC_WDT_WDT_WKEY_V  0xFFFFFFFFU
-#define RTC_WDT_WDT_WKEY_S  0
-
-/** RTC_WDT_SWD_CONFIG_REG register
- *  need_des
- */
-#define RTC_WDT_SWD_CONFIG_REG (DR_REG_RTC_WDT_BASE + 0x1c)
-/** RTC_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SWD_RESET_FLAG    (BIT(0))
-#define RTC_WDT_SWD_RESET_FLAG_M  (RTC_WDT_SWD_RESET_FLAG_V << RTC_WDT_SWD_RESET_FLAG_S)
-#define RTC_WDT_SWD_RESET_FLAG_V  0x00000001U
-#define RTC_WDT_SWD_RESET_FLAG_S  0
-/** RTC_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SWD_AUTO_FEED_EN    (BIT(18))
-#define RTC_WDT_SWD_AUTO_FEED_EN_M  (RTC_WDT_SWD_AUTO_FEED_EN_V << RTC_WDT_SWD_AUTO_FEED_EN_S)
-#define RTC_WDT_SWD_AUTO_FEED_EN_V  0x00000001U
-#define RTC_WDT_SWD_AUTO_FEED_EN_S  18
-/** RTC_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SWD_RST_FLAG_CLR    (BIT(19))
-#define RTC_WDT_SWD_RST_FLAG_CLR_M  (RTC_WDT_SWD_RST_FLAG_CLR_V << RTC_WDT_SWD_RST_FLAG_CLR_S)
-#define RTC_WDT_SWD_RST_FLAG_CLR_V  0x00000001U
-#define RTC_WDT_SWD_RST_FLAG_CLR_S  19
-/** RTC_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
- *  need_des
- */
-#define RTC_WDT_SWD_SIGNAL_WIDTH    0x000003FFU
-#define RTC_WDT_SWD_SIGNAL_WIDTH_M  (RTC_WDT_SWD_SIGNAL_WIDTH_V << RTC_WDT_SWD_SIGNAL_WIDTH_S)
-#define RTC_WDT_SWD_SIGNAL_WIDTH_V  0x000003FFU
-#define RTC_WDT_SWD_SIGNAL_WIDTH_S  20
-/** RTC_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SWD_DISABLE    (BIT(30))
-#define RTC_WDT_SWD_DISABLE_M  (RTC_WDT_SWD_DISABLE_V << RTC_WDT_SWD_DISABLE_S)
-#define RTC_WDT_SWD_DISABLE_V  0x00000001U
-#define RTC_WDT_SWD_DISABLE_S  30
-/** RTC_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SWD_FEED    (BIT(31))
-#define RTC_WDT_SWD_FEED_M  (RTC_WDT_SWD_FEED_V << RTC_WDT_SWD_FEED_S)
-#define RTC_WDT_SWD_FEED_V  0x00000001U
-#define RTC_WDT_SWD_FEED_S  31
-
-/** RTC_WDT_SWD_WPROTECT_REG register
- *  need_des
- */
-#define RTC_WDT_SWD_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x20)
-/** RTC_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SWD_WKEY    0xFFFFFFFFU
-#define RTC_WDT_SWD_WKEY_M  (RTC_WDT_SWD_WKEY_V << RTC_WDT_SWD_WKEY_S)
-#define RTC_WDT_SWD_WKEY_V  0xFFFFFFFFU
-#define RTC_WDT_SWD_WKEY_S  0
-
-/** RTC_WDT_INT_RAW_REG register
- *  need_des
- */
-#define RTC_WDT_INT_RAW_REG (DR_REG_RTC_WDT_BASE + 0x24)
-/** RTC_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SUPER_WDT_INT_RAW    (BIT(30))
-#define RTC_WDT_SUPER_WDT_INT_RAW_M  (RTC_WDT_SUPER_WDT_INT_RAW_V << RTC_WDT_SUPER_WDT_INT_RAW_S)
-#define RTC_WDT_SUPER_WDT_INT_RAW_V  0x00000001U
-#define RTC_WDT_SUPER_WDT_INT_RAW_S  30
-/** RTC_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_LP_WDT_INT_RAW    (BIT(31))
-#define RTC_WDT_LP_WDT_INT_RAW_M  (RTC_WDT_LP_WDT_INT_RAW_V << RTC_WDT_LP_WDT_INT_RAW_S)
-#define RTC_WDT_LP_WDT_INT_RAW_V  0x00000001U
-#define RTC_WDT_LP_WDT_INT_RAW_S  31
-
-/** RTC_WDT_INT_ST_REG register
- *  need_des
- */
-#define RTC_WDT_INT_ST_REG (DR_REG_RTC_WDT_BASE + 0x28)
-/** RTC_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SUPER_WDT_INT_ST    (BIT(30))
-#define RTC_WDT_SUPER_WDT_INT_ST_M  (RTC_WDT_SUPER_WDT_INT_ST_V << RTC_WDT_SUPER_WDT_INT_ST_S)
-#define RTC_WDT_SUPER_WDT_INT_ST_V  0x00000001U
-#define RTC_WDT_SUPER_WDT_INT_ST_S  30
-/** RTC_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_LP_WDT_INT_ST    (BIT(31))
-#define RTC_WDT_LP_WDT_INT_ST_M  (RTC_WDT_LP_WDT_INT_ST_V << RTC_WDT_LP_WDT_INT_ST_S)
-#define RTC_WDT_LP_WDT_INT_ST_V  0x00000001U
-#define RTC_WDT_LP_WDT_INT_ST_S  31
-
-/** RTC_WDT_INT_ENA_REG register
- *  need_des
- */
-#define RTC_WDT_INT_ENA_REG (DR_REG_RTC_WDT_BASE + 0x2c)
-/** RTC_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SUPER_WDT_INT_ENA    (BIT(30))
-#define RTC_WDT_SUPER_WDT_INT_ENA_M  (RTC_WDT_SUPER_WDT_INT_ENA_V << RTC_WDT_SUPER_WDT_INT_ENA_S)
-#define RTC_WDT_SUPER_WDT_INT_ENA_V  0x00000001U
-#define RTC_WDT_SUPER_WDT_INT_ENA_S  30
-/** RTC_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_LP_WDT_INT_ENA    (BIT(31))
-#define RTC_WDT_LP_WDT_INT_ENA_M  (RTC_WDT_LP_WDT_INT_ENA_V << RTC_WDT_LP_WDT_INT_ENA_S)
-#define RTC_WDT_LP_WDT_INT_ENA_V  0x00000001U
-#define RTC_WDT_LP_WDT_INT_ENA_S  31
-
-/** RTC_WDT_INT_CLR_REG register
- *  need_des
- */
-#define RTC_WDT_INT_CLR_REG (DR_REG_RTC_WDT_BASE + 0x30)
-/** RTC_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_WDT_SUPER_WDT_INT_CLR    (BIT(30))
-#define RTC_WDT_SUPER_WDT_INT_CLR_M  (RTC_WDT_SUPER_WDT_INT_CLR_V << RTC_WDT_SUPER_WDT_INT_CLR_S)
-#define RTC_WDT_SUPER_WDT_INT_CLR_V  0x00000001U
-#define RTC_WDT_SUPER_WDT_INT_CLR_S  30
-/** RTC_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_LP_WDT_INT_CLR    (BIT(31))
-#define RTC_WDT_LP_WDT_INT_CLR_M  (RTC_WDT_LP_WDT_INT_CLR_V << RTC_WDT_LP_WDT_INT_CLR_S)
-#define RTC_WDT_LP_WDT_INT_CLR_V  0x00000001U
-#define RTC_WDT_LP_WDT_INT_CLR_S  31
-
-/** RTC_WDT_DATE_REG register
- *  need_des
- */
-#define RTC_WDT_DATE_REG (DR_REG_RTC_WDT_BASE + 0x3fc)
-/** RTC_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
- *  need_des
- */
-#define RTC_WDT_LP_WDT_DATE    0x7FFFFFFFU
-#define RTC_WDT_LP_WDT_DATE_M  (RTC_WDT_LP_WDT_DATE_V << RTC_WDT_LP_WDT_DATE_S)
-#define RTC_WDT_LP_WDT_DATE_V  0x7FFFFFFFU
-#define RTC_WDT_LP_WDT_DATE_S  0
-/** RTC_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_WDT_CLK_EN    (BIT(31))
-#define RTC_WDT_CLK_EN_M  (RTC_WDT_CLK_EN_V << RTC_WDT_CLK_EN_S)
-#define RTC_WDT_CLK_EN_V  0x00000001U
-#define RTC_WDT_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/rtc_wdt_struct.h b/components/soc/esp32p4/include/soc/rtc_wdt_struct.h
deleted file mode 100644
index 2c96355399..0000000000
--- a/components/soc/esp32p4/include/soc/rtc_wdt_struct.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of config0 register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_pause_in_slp:1;
-        /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_appcpu_reset_en:1;
-        /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_procpu_reset_en:1;
-        /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_flashboot_mod_en:1;
-        /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_sys_reset_length:3;
-        /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_cpu_reset_length:3;
-        /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg3:3;
-        /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg2:3;
-        /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg1:3;
-        /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg0:3;
-        /** wdt_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_en:1;
-    };
-    uint32_t val;
-} rtc_wdt_config0_reg_t;
-
-/** Type of config1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
-         *  need_des
-         */
-        uint32_t wdt_stg0_hold:32;
-    };
-    uint32_t val;
-} rtc_wdt_config1_reg_t;
-
-/** Type of config2 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
-         *  need_des
-         */
-        uint32_t wdt_stg1_hold:32;
-    };
-    uint32_t val;
-} rtc_wdt_config2_reg_t;
-
-/** Type of config3 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
-         *  need_des
-         */
-        uint32_t wdt_stg2_hold:32;
-    };
-    uint32_t val;
-} rtc_wdt_config3_reg_t;
-
-/** Type of config4 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
-         *  need_des
-         */
-        uint32_t wdt_stg3_hold:32;
-    };
-    uint32_t val;
-} rtc_wdt_config4_reg_t;
-
-/** Type of feed register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** feed : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t feed:1;
-    };
-    uint32_t val;
-} rtc_wdt_feed_reg_t;
-
-/** Type of wprotect register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_wkey:32;
-    };
-    uint32_t val;
-} rtc_wdt_wprotect_reg_t;
-
-/** Type of swd_config register
- *  need_des
- */
-typedef union {
-    struct {
-        /** swd_reset_flag : RO; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_reset_flag:1;
-        uint32_t reserved_1:17;
-        /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_auto_feed_en:1;
-        /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_rst_flag_clr:1;
-        /** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
-         *  need_des
-         */
-        uint32_t swd_signal_width:10;
-        /** swd_disable : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_disable:1;
-        /** swd_feed : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_feed:1;
-    };
-    uint32_t val;
-} rtc_wdt_swd_config_reg_t;
-
-/** Type of swd_wprotect register
- *  need_des
- */
-typedef union {
-    struct {
-        /** swd_wkey : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_wkey:32;
-    };
-    uint32_t val;
-} rtc_wdt_swd_wprotect_reg_t;
-
-/** Type of int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_raw:1;
-        /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_raw:1;
-    };
-    uint32_t val;
-} rtc_wdt_int_raw_reg_t;
-
-/** Type of int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_st:1;
-        /** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_st:1;
-    };
-    uint32_t val;
-} rtc_wdt_int_st_reg_t;
-
-/** Type of int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_ena:1;
-        /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_ena:1;
-    };
-    uint32_t val;
-} rtc_wdt_int_ena_reg_t;
-
-/** Type of int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_clr:1;
-        /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_clr:1;
-    };
-    uint32_t val;
-} rtc_wdt_int_clr_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
-         *  need_des
-         */
-        uint32_t lp_wdt_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} rtc_wdt_date_reg_t;
-
-
-typedef struct {
-    volatile rtc_wdt_config0_reg_t config0;
-    volatile rtc_wdt_config1_reg_t config1;
-    volatile rtc_wdt_config2_reg_t config2;
-    volatile rtc_wdt_config3_reg_t config3;
-    volatile rtc_wdt_config4_reg_t config4;
-    volatile rtc_wdt_feed_reg_t feed;
-    volatile rtc_wdt_wprotect_reg_t wprotect;
-    volatile rtc_wdt_swd_config_reg_t swd_config;
-    volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect;
-    volatile rtc_wdt_int_raw_reg_t int_raw;
-    volatile rtc_wdt_int_st_reg_t int_st;
-    volatile rtc_wdt_int_ena_reg_t int_ena;
-    volatile rtc_wdt_int_clr_reg_t int_clr;
-    uint32_t reserved_034[242];
-    volatile rtc_wdt_date_reg_t date;
-} rtc_wdt_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(rtc_wdt_dev_t) == 0x400, "Invalid size of rtc_wdt_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif

From 2f6ce0cc17e6a6fadd479f544c67931536ed4f7a Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Tue, 4 Jul 2023 17:17:57 +0800
Subject: [PATCH 06/13] fix(regi2c): wrong ADC_CALI_PD_WORKAROUND on c6, h2

---
 components/esp_hw_support/regi2c_ctrl.c          |  7 ++-----
 components/soc/esp32c6/include/soc/regi2c_defs.h | 10 +---------
 components/soc/esp32h2/include/soc/regi2c_defs.h |  7 -------
 3 files changed, 3 insertions(+), 21 deletions(-)

diff --git a/components/esp_hw_support/regi2c_ctrl.c b/components/esp_hw_support/regi2c_ctrl.c
index 8681c91aae..1d63f66686 100644
--- a/components/esp_hw_support/regi2c_ctrl.c
+++ b/components/esp_hw_support/regi2c_ctrl.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -79,7 +79,7 @@ void IRAM_ATTR regi2c_analog_cali_reg_write(void)
         regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
     }
 }
-
+#endif   //#if ADC_CALI_PD_WORKAROUND
 
 /**
  * REGI2C_SARADC reference count
@@ -109,6 +109,3 @@ void regi2c_saradc_disable(void)
     regi2c_exit_critical();
 
 }
-
-
-#endif   //#if ADC_CALI_PD_WORKAROUND
diff --git a/components/soc/esp32c6/include/soc/regi2c_defs.h b/components/soc/esp32c6/include/soc/regi2c_defs.h
index 397a42c2a3..38db4f1595 100644
--- a/components/soc/esp32c6/include/soc/regi2c_defs.h
+++ b/components/soc/esp32c6/include/soc/regi2c_defs.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,11 +27,3 @@
 #define ANA_CONFIG2_M    BIT(18)
 
 #define ANA_I2C_SAR_FORCE_PU BIT(16)
-
-
-/**
- * Restore regi2c analog calibration related configuration registers.
- * This is a workaround, and is fixed on later chips
- */
-#define REGI2C_ANA_CALI_PD_WORKAROUND    1
-#define REGI2C_ANA_CALI_BYTE_NUM         8
diff --git a/components/soc/esp32h2/include/soc/regi2c_defs.h b/components/soc/esp32h2/include/soc/regi2c_defs.h
index c7991ec3e0..e9611d885e 100644
--- a/components/soc/esp32h2/include/soc/regi2c_defs.h
+++ b/components/soc/esp32h2/include/soc/regi2c_defs.h
@@ -26,10 +26,3 @@
 #define ANA_CONFIG2_M    BIT(18)
 
 #define ANA_I2C_SAR_FORCE_PU BIT(16)
-
-/**
- * Restore regi2c analog calibration related configuration registers.
- * This is a workaround, and is fixed on later chips
- */
-#define REGI2C_ANA_CALI_PD_WORKAROUND    1
-#define REGI2C_ANA_CALI_BYTE_NUM         8

From 65bfa590da6349d4aae55d4861abba0f5026db0b Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Tue, 4 Jul 2023 17:18:13 +0800
Subject: [PATCH 07/13] feat(soc): soc updates

---
 components/hal/include/hal/i2c_types.h        |    3 +-
 .../soc/esp32c6/include/soc/parl_io_struct.h  |    2 +-
 components/soc/esp32p4/adc_periph.c           |   13 +-
 components/soc/esp32p4/gdma_periph.c          |   18 +-
 components/soc/esp32p4/gpio_periph.c          |   94 +-
 components/soc/esp32p4/i2c_periph.c           |    8 -
 components/soc/esp32p4/i2s_periph.c           |   20 -
 .../esp32p4/include/modem/modem_lpcon_reg.h   |  382 --
 .../include/modem/modem_lpcon_struct.h        |  178 -
 .../esp32p4/include/modem/modem_syscon_reg.h  |  612 --
 .../include/modem/modem_syscon_struct.h       |  205 -
 .../soc/esp32p4/include/modem/reg_base.h      |    9 -
 .../soc/esp32p4/include/soc/adc_channel.h     |   21 -
 .../soc/esp32p4/include/soc/apb_saradc_reg.h  |  884 ---
 .../esp32p4/include/soc/apb_saradc_struct.h   |  757 ---
 components/soc/esp32p4/include/soc/clic_reg.h |    9 +-
 .../soc/esp32p4/include/soc/clint_reg.h       |  163 -
 .../soc/esp32p4/include/soc/clk_tree_defs.h   |  206 +-
 .../soc/esp32p4/include/soc/clkout_channel.h  |    3 +-
 .../esp32p4/include/soc/core0_interrupt_reg.h | 1624 -----
 .../include/soc/core0_interrupt_struct.h      | 2298 -------
 .../esp32p4/include/soc/core1_interrupt_reg.h | 1624 -----
 .../include/soc/core1_interrupt_struct.h      | 2298 -------
 .../soc/esp32p4/include/soc/extmem_reg.h      |  871 ---
 .../soc/esp32p4/include/soc/extmem_struct.h   | 5747 -----------------
 .../soc/esp32p4/include/soc/gdma_channel.h    |   10 -
 .../soc/esp32p4/include/soc/gpio_pins.h       |    2 -
 .../soc/esp32p4/include/soc/gpio_sd_reg.h     | 1455 -----
 .../soc/esp32p4/include/soc/gpio_sd_struct.h  |  771 ---
 .../soc/esp32p4/include/soc/gpio_sig_map.h    |    6 +-
 .../esp32p4/include/soc/hardware_lock_reg.h   |   76 -
 .../include/soc/hardware_lock_struct.h        |   99 -
 components/soc/esp32p4/include/soc/hinf_reg.h |  647 --
 .../soc/esp32p4/include/soc/hinf_struct.h     |  555 --
 components/soc/esp32p4/include/soc/host_reg.h | 3883 -----------
 .../soc/esp32p4/include/soc/host_struct.h     | 2738 --------
 .../soc/esp32p4/include/soc/hp_apm_reg.h      | 1838 ------
 .../soc/esp32p4/include/soc/hp_apm_struct.h   | 1670 -----
 .../soc/esp32p4/include/soc/hp_clkrst_reg.h   |  629 --
 .../soc/esp32p4/include/soc/hwcrypto_reg.h    |  178 -
 .../soc/esp32p4/include/soc/i2c_ext_reg.h     | 1521 -----
 .../soc/esp32p4/include/soc/i2c_ext_struct.h  | 1276 ----
 .../esp32p4/include/soc/interrupt_core0_reg.h | 2162 ++++---
 .../include/soc/interrupt_core0_struct.h      | 2298 +++++++
 .../esp32p4/include/soc/interrupt_core1_reg.h | 2162 ++++---
 .../include/soc/interrupt_core1_struct.h      | 2298 +++++++
 .../include/soc/interrupt_matrix_reg.h        |  999 ---
 .../include/soc/interrupt_matrix_struct.h     | 1254 ----
 .../soc/esp32p4/include/soc/interrupt_reg.h   |    4 +-
 .../soc/esp32p4/include/soc/intpri_reg.h      |  574 --
 .../soc/esp32p4/include/soc/intpri_struct.h   |  256 -
 .../soc/esp32p4/include/soc/iomux_reg.h       | 5143 ---------------
 .../soc/esp32p4/include/soc/iomux_struct.h    | 3429 ----------
 .../soc/esp32p4/include/soc/lcd_cam_reg.h     | 2049 +++---
 .../soc/esp32p4/include/soc/lcd_cam_struct.h  | 1138 +++-
 .../soc/esp32p4/include/soc/lcdcam_reg.h      | 1145 ----
 .../soc/esp32p4/include/soc/lcdcam_struct.h   |  855 ---
 .../soc/esp32p4/include/soc/lp_aon_reg.h      |  418 --
 .../soc/esp32p4/include/soc/lp_aon_struct.h   |  306 -
 .../esp32p4/include/soc/lp_aonclkrst_reg.h    | 1036 ---
 .../esp32p4/include/soc/lp_aonclkrst_struct.h |  795 ---
 .../soc/esp32p4/include/soc/lp_apm0_reg.h     |  506 --
 .../soc/esp32p4/include/soc/lp_apm0_struct.h  |  499 --
 .../soc/esp32p4/include/soc/lp_apm_reg.h      |  582 --
 .../soc/esp32p4/include/soc/lp_apm_struct.h   |  583 --
 .../soc/esp32p4/include/soc/lp_clkrst_reg.h   | 1012 ++-
 .../esp32p4/include/soc/lp_clkrst_struct.h    |  656 +-
 .../soc/esp32p4/include/soc/lp_gpio_struct.h  |    4 +-
 .../soc/esp32p4/include/soc/lp_io_reg.h       | 1263 ----
 .../soc/esp32p4/include/soc/lp_io_struct.h    |  362 --
 .../soc/esp32p4/include/soc/lp_iomux_struct.h |    2 +-
 .../soc/esp32p4/include/soc/lp_sys_reg.h      | 1349 ----
 .../soc/esp32p4/include/soc/lp_sys_struct.h   | 1333 ----
 .../soc/esp32p4/include/soc/lp_tee_reg.h      |   65 -
 .../soc/esp32p4/include/soc/lp_tee_struct.h   |   95 -
 .../soc/esp32p4/include/soc/mem_monitor_reg.h |  166 -
 .../esp32p4/include/soc/mem_monitor_struct.h  |  328 -
 components/soc/esp32p4/include/soc/mmu.h      |   17 +-
 .../soc/esp32p4/include/soc/otp_debug_reg.h   | 1600 -----
 .../esp32p4/include/soc/otp_debug_struct.h    | 2137 ------
 .../soc/esp32p4/include/soc/parl_io_struct.h  |    2 +-
 components/soc/esp32p4/include/soc/pcr_reg.h  | 2065 ------
 components/soc/esp32p4/include/soc/plic_reg.h |  631 --
 .../soc/esp32p4/include/soc/pmu_icg_mapping.h |   65 +-
 components/soc/esp32p4/include/soc/pwm_reg.h  | 4514 -------------
 .../soc/esp32p4/include/soc/pwm_struct.h      | 2166 -------
 components/soc/esp32p4/include/soc/reg_base.h |   71 +-
 .../soc/esp32p4/include/soc/regi2c_bbpll.h    |  161 +-
 .../soc/esp32p4/include/soc/regi2c_bias.h     |    7 -
 .../soc/esp32p4/include/soc/regi2c_brownout.h |    7 -
 .../soc/esp32p4/include/soc/regi2c_defs.h     |    8 -
 .../soc/esp32p4/include/soc/regi2c_lp_bias.h  |   41 +-
 .../soc/esp32p4/include/soc/regi2c_saradc.h   |   63 -
 .../soc/esp32p4/include/soc/reset_reasons.h   |    2 +-
 components/soc/esp32p4/include/soc/rtc.h      |    4 +-
 .../soc/esp32p4/include/soc/rtc_io_channel.h  |   25 -
 .../soc/esp32p4/include/soc/rtc_io_reg.h      |    3 +-
 .../soc/esp32p4/include/soc/rtc_io_struct.h   |    6 +-
 .../soc/esp32p4/include/soc/sdio_slave_pins.h |   14 -
 .../soc/esp32p4/include/soc/sdmmc_pins.h      |   35 +-
 components/soc/esp32p4/include/soc/slc_reg.h  | 4301 ------------
 .../soc/esp32p4/include/soc/slc_struct.h      | 3253 ----------
 components/soc/esp32p4/include/soc/soc.h      |    1 +
 .../soc/esp32p4/include/soc/spi_mem_struct.h  |    2 +-
 components/soc/esp32p4/include/soc/spi_pins.h |   21 +-
 .../soc/esp32p4/include/soc/sys_clkrst_reg.h  | 1118 ----
 components/soc/esp32p4/include/soc/tee_reg.h  |  455 --
 .../soc/esp32p4/include/soc/tee_struct.h      |  573 --
 .../soc/esp32p4/include/soc/twaifd_reg.h      | 1795 -----
 .../soc/esp32p4/include/soc/twaifd_struct.h   | 1548 -----
 .../soc/esp32p4/include/soc/uart_channel.h    |    9 -
 .../soc/esp32p4/include/soc/uart_pins.h       |   24 -
 .../soc/esp32p4/include/soc/usb_device_reg.h  | 1282 ----
 .../esp32p4/include/soc/usb_device_struct.h   | 1044 ---
 .../soc/esp32p4/ld/esp32p4.peripherals.ld     |   12 +-
 components/soc/esp32p4/ledc_periph.c          |    4 +-
 components/soc/esp32p4/mcpwm_periph.c         |   72 +-
 components/soc/esp32p4/parlio_periph.c        |   56 +-
 components/soc/esp32p4/pcnt_periph.c          |   57 +-
 components/soc/esp32p4/rmt_periph.c           |   25 +-
 components/soc/esp32p4/rtc_io_periph.c        |   32 +-
 components/soc/esp32p4/sdio_slave_periph.c    |   10 +-
 components/soc/esp32p4/sdm_periph.c           |   15 +-
 components/soc/esp32p4/sdmmc_periph.c         |   48 +-
 components/soc/esp32p4/spi_periph.c           |   40 +-
 .../soc/esp32p4/temperature_sensor_periph.c   |    7 +-
 components/soc/esp32p4/timer_periph.c         |   15 +-
 components/soc/esp32p4/twai_periph.c          |   21 +-
 components/soc/esp32p4/uart_periph.c          |   66 -
 components/soc/include/soc/rtc_cntl_periph.h  |   22 +-
 130 files changed, 10749 insertions(+), 91352 deletions(-)
 delete mode 100644 components/soc/esp32p4/include/modem/modem_lpcon_reg.h
 delete mode 100644 components/soc/esp32p4/include/modem/modem_lpcon_struct.h
 delete mode 100644 components/soc/esp32p4/include/modem/modem_syscon_reg.h
 delete mode 100644 components/soc/esp32p4/include/modem/modem_syscon_struct.h
 delete mode 100644 components/soc/esp32p4/include/modem/reg_base.h
 delete mode 100644 components/soc/esp32p4/include/soc/apb_saradc_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/apb_saradc_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/clint_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/core0_interrupt_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/core0_interrupt_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/core1_interrupt_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/core1_interrupt_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/extmem_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/extmem_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/gpio_sd_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/gpio_sd_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/hardware_lock_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/hardware_lock_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/hinf_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/hinf_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/host_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/host_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/hp_apm_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/hp_apm_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/hp_clkrst_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/hwcrypto_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/i2c_ext_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/i2c_ext_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/interrupt_core0_struct.h
 create mode 100644 components/soc/esp32p4/include/soc/interrupt_core1_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/interrupt_matrix_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/interrupt_matrix_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/intpri_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/intpri_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/iomux_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/iomux_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lcdcam_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lcdcam_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_aon_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_aon_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_apm0_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_apm0_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_apm_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_apm_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_io_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_io_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_sys_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_sys_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_tee_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/lp_tee_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/mem_monitor_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/mem_monitor_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/otp_debug_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/otp_debug_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/pcr_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/plic_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/pwm_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/pwm_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/sdio_slave_pins.h
 delete mode 100644 components/soc/esp32p4/include/soc/slc_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/slc_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/sys_clkrst_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/tee_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/tee_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/twaifd_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/twaifd_struct.h
 delete mode 100644 components/soc/esp32p4/include/soc/usb_device_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/usb_device_struct.h

diff --git a/components/hal/include/hal/i2c_types.h b/components/hal/include/hal/i2c_types.h
index 5e37c7e411..ea733f3566 100644
--- a/components/hal/include/hal/i2c_types.h
+++ b/components/hal/include/hal/i2c_types.h
@@ -92,11 +92,12 @@ typedef struct {
     int timeout; /*!< timeout value */
 } i2c_hal_timing_config_t;
 
-
+#if SOC_I2C_SUPPORTED
 /**
  * @brief I2C group clock source
  */
 typedef soc_periph_i2c_clk_src_t i2c_clock_source_t;
+#endif
 
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32c6/include/soc/parl_io_struct.h b/components/soc/esp32c6/include/soc/parl_io_struct.h
index 21b5f63495..816a7de3ef 100644
--- a/components/soc/esp32c6/include/soc/parl_io_struct.h
+++ b/components/soc/esp32c6/include/soc/parl_io_struct.h
@@ -14,7 +14,7 @@ extern "C" {
 /** Type of rx_cfg0 register
  *  Parallel RX module configuration register0.
  */
-typedef volatile union {
+typedef union {
     struct {
         /** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0;
          *  Write 0 to select eof generated manchnism by configured data byte length. Write 1
diff --git a/components/soc/esp32p4/adc_periph.c b/components/soc/esp32p4/adc_periph.c
index 050fb96675..47081cfc68 100644
--- a/components/soc/esp32p4/adc_periph.c
+++ b/components/soc/esp32p4/adc_periph.c
@@ -7,15 +7,4 @@
 #include "soc/adc_periph.h"
 
 /* Store IO number corresponding to the ADC channel number. */
-const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
-    /* ADC1 */
-    {
-        ADC1_CHANNEL_0_GPIO_NUM,
-        ADC1_CHANNEL_1_GPIO_NUM,
-        ADC1_CHANNEL_2_GPIO_NUM,
-        ADC1_CHANNEL_3_GPIO_NUM,
-        ADC1_CHANNEL_4_GPIO_NUM,
-        ADC1_CHANNEL_5_GPIO_NUM,
-        ADC1_CHANNEL_6_GPIO_NUM,
-    },
-};
+const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {};
diff --git a/components/soc/esp32p4/gdma_periph.c b/components/soc/esp32p4/gdma_periph.c
index 5ddc769de5..890525bc2b 100644
--- a/components/soc/esp32p4/gdma_periph.c
+++ b/components/soc/esp32p4/gdma_periph.c
@@ -6,20 +6,4 @@
 
 #include "soc/gdma_periph.h"
 
-const gdma_signal_conn_t gdma_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_GDMA_MODULE,
-            .pairs = {
-                [0]  = {
-                    .rx_irq_id = ETS_DMA2D_IN_CH0_INTR_SOURCE,
-                    .tx_irq_id = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
-                },
-                [1]  = {
-                    .rx_irq_id = ETS_DMA2D_IN_CH1_INTR_SOURCE,
-                    .tx_irq_id = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
-                },
-            }
-        }
-    }
-};
+const gdma_signal_conn_t gdma_periph_signals = {};
diff --git a/components/soc/esp32p4/gpio_periph.c b/components/soc/esp32p4/gpio_periph.c
index c8158d5e19..c23436882a 100644
--- a/components/soc/esp32p4/gpio_periph.c
+++ b/components/soc/esp32p4/gpio_periph.c
@@ -7,99 +7,13 @@
 #include "soc/gpio_periph.h"
 
 const uint32_t GPIO_PIN_MUX_REG[] = {
-    IO_MUX_GPIO0_REG,
-    IO_MUX_GPIO1_REG,
-    IO_MUX_GPIO2_REG,
-    IO_MUX_GPIO3_REG,
-    IO_MUX_GPIO4_REG,
-    IO_MUX_GPIO5_REG,
-    IO_MUX_GPIO6_REG,
-    IO_MUX_GPIO7_REG,
-    IO_MUX_GPIO8_REG,
-    IO_MUX_GPIO9_REG,
-    IO_MUX_GPIO10_REG,
-    IO_MUX_GPIO11_REG,
-    IO_MUX_GPIO12_REG,
-    IO_MUX_GPIO13_REG,
-    IO_MUX_GPIO14_REG,
-    IO_MUX_GPIO15_REG,
-    IO_MUX_GPIO16_REG,
-    IO_MUX_GPIO17_REG,
-    IO_MUX_GPIO18_REG,
-    IO_MUX_GPIO19_REG,
-    IO_MUX_GPIO20_REG,
-    IO_MUX_GPIO21_REG,
-    IO_MUX_GPIO22_REG,
-    IO_MUX_GPIO23_REG,
-    IO_MUX_GPIO24_REG,
-    IO_MUX_GPIO25_REG,
-    IO_MUX_GPIO26_REG,
-    IO_MUX_GPIO27_REG,
-    IO_MUX_GPIO28_REG,
-    IO_MUX_GPIO29_REG,
-    IO_MUX_GPIO30_REG,
-    IO_MUX_GPIO31_REG,
-    IO_MUX_GPIO32_REG,
-    IO_MUX_GPIO33_REG,
-    IO_MUX_GPIO34_REG,
-    IO_MUX_GPIO35_REG,
-    IO_MUX_GPIO36_REG,
-    IO_MUX_GPIO37_REG,
-    IO_MUX_GPIO38_REG,
-    IO_MUX_GPIO39_REG,
-    IO_MUX_GPIO40_REG,
-    IO_MUX_GPIO41_REG,
-    IO_MUX_GPIO42_REG,
-    IO_MUX_GPIO43_REG,
-    IO_MUX_GPIO44_REG,
-    IO_MUX_GPIO45_REG,
-    IO_MUX_GPIO46_REG,
-    IO_MUX_GPIO47_REG,
-    IO_MUX_GPIO48_REG,
-    IO_MUX_GPIO49_REG,
-    IO_MUX_GPIO50_REG,
-    IO_MUX_GPIO51_REG,
-    IO_MUX_GPIO52_REG,
-    IO_MUX_GPIO53_REG,
-    IO_MUX_GPIO54_REG,
-    IO_MUX_GPIO55_REG,
-    IO_MUX_GPIO56_REG,
+
 };
 
-_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
+// _Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
 
 const uint32_t GPIO_HOLD_MASK[] = {
-    BIT(0),          //GPIO0   // LP_AON_GPIO_HOLD0_REG
-    BIT(1),          //GPIO1
-    BIT(2),          //GPIO2
-    BIT(3),          //GPIO3
-    BIT(4),          //GPIO4
-    BIT(5),          //GPIO5
-    BIT(6),          //GPIO6
-    BIT(7),          //GPIO7
-    BIT(8),          //GPIO8
-    BIT(9),          //GPIO9
-    BIT(10),         //GPIO10
-    BIT(11),         //GPIO11
-    BIT(12),         //GPIO12
-    BIT(13),         //GPIO13
-    BIT(14),         //GPIO14
-    BIT(15),         //GPIO15
-    BIT(16),         //GPIO16
-    BIT(17),         //GPIO17
-    BIT(18),         //GPIO18
-    BIT(19),         //GPIO19
-    BIT(20),         //GPIO20
-    BIT(21),         //GPIO21
-    BIT(22),         //GPIO22
-    BIT(23),         //GPIO23
-    BIT(24),         //GPIO24
-    BIT(25),         //GPIO25
-    BIT(26),         //GPIO26
-    BIT(27),         //GPIO27
-    BIT(28),         //GPIO28
-    BIT(29),         //GPIO29
-    BIT(30),         //GPIO30
+
 };
 
-_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
+// _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
diff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c
index dd08f58a60..b444a1255d 100644
--- a/components/soc/esp32p4/i2c_periph.c
+++ b/components/soc/esp32p4/i2c_periph.c
@@ -11,12 +11,4 @@
  Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
-    {
-        .sda_out_sig = I2CEXT0_SDA_OUT_IDX,
-        .sda_in_sig = I2CEXT0_SDA_IN_IDX,
-        .scl_out_sig = I2CEXT0_SCL_OUT_IDX,
-        .scl_in_sig = I2CEXT0_SCL_IN_IDX,
-        .irq = ETS_I2C_EXT0_INTR_SOURCE,
-        .module = PERIPH_I2C0_MODULE,
-    },
 };
diff --git a/components/soc/esp32p4/i2s_periph.c b/components/soc/esp32p4/i2s_periph.c
index 15a7ff4fff..1e466a3433 100644
--- a/components/soc/esp32p4/i2s_periph.c
+++ b/components/soc/esp32p4/i2s_periph.c
@@ -11,24 +11,4 @@
  Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
-    {
-        .mck_out_sig  = 0,
-
-        .m_tx_bck_sig = 0,
-        .m_rx_bck_sig = 0,
-        .m_tx_ws_sig  = 0,
-        .m_rx_ws_sig  = 0,
-
-        .s_tx_bck_sig = 0,
-        .s_rx_bck_sig = 0,
-        .s_tx_ws_sig  = 0,
-        .s_rx_ws_sig  = 0,
-
-        .data_out_sigs[0] = 0,
-        .data_out_sigs[1] = 0,
-        .data_in_sig  = 0,
-
-        .irq          = -1,
-        .module       = PERIPH_I2S1_MODULE,
-    }
 };
diff --git a/components/soc/esp32p4/include/modem/modem_lpcon_reg.h b/components/soc/esp32p4/include/modem/modem_lpcon_reg.h
deleted file mode 100644
index 63889d3e68..0000000000
--- a/components/soc/esp32p4/include/modem/modem_lpcon_reg.h
+++ /dev/null
@@ -1,382 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "modem/reg_base.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
-/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_EN    (BIT(0))
-#define MODEM_LPCON_CLK_EN_M  (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
-#define MODEM_LPCON_CLK_EN_V  0x00000001U
-#define MODEM_LPCON_CLK_EN_S  0
-/* MODEM_LPCON_CLK_DEBUG_ENA : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_DEBUG_ENA    (BIT(1))
-#define MODEM_LPCON_CLK_DEBUG_ENA_M  (MODEM_LPCON_CLK_DEBUG_ENA_V << MODEM_LPCON_CLK_DEBUG_ENA_S)
-#define MODEM_LPCON_CLK_DEBUG_ENA_V  0x00000001U
-#define MODEM_LPCON_CLK_DEBUG_ENA_S  1
-
-#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
-/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW    (BIT(0))
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S)
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V  0x00000001U
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S  0
-/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST    (BIT(1))
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S)
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V  0x00000001U
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S  1
-/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL    (BIT(2))
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S)
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V  0x00000001U
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S  2
-/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K    (BIT(3))
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S)
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V  0x00000001U
-#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S  3
-/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM    0x00000FFFU
-#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M  (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)
-#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V  0x00000FFFU
-#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S  4
-
-#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
-/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW    (BIT(0))
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V  0x00000001U
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S  0
-/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST    (BIT(1))
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V  0x00000001U
-#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S  1
-/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL    (BIT(2))
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M  (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V  0x00000001U
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S  2
-/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K    (BIT(3))
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M  (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V  0x00000001U
-#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S  3
-/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM    0x00000FFFU
-#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M  (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
-#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V  0x00000FFFU
-#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S  4
-
-#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
-/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW    (BIT(0))
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S)
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V  0x00000001U
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S  0
-/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST    (BIT(1))
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S)
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V  0x00000001U
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S  1
-/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL    (BIT(2))
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S)
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V  0x00000001U
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S  2
-/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K    (BIT(3))
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S)
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V  0x00000001U
-#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S  3
-/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM    0x00000FFFU
-#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M  (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)
-#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V  0x00000FFFU
-#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S  4
-
-#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
-/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M    (BIT(0))
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M  (MODEM_LPCON_CLK_I2C_MST_SEL_160M_V << MODEM_LPCON_CLK_I2C_MST_SEL_160M_S)
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V  0x00000001U
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S  0
-
-#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
-/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_MODEM_32K_SEL    0x00000003U
-#define MODEM_LPCON_CLK_MODEM_32K_SEL_M  (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S)
-#define MODEM_LPCON_CLK_MODEM_32K_SEL_V  0x00000003U
-#define MODEM_LPCON_CLK_MODEM_32K_SEL_S  0
-
-#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
-/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_EN    (BIT(0))
-#define MODEM_LPCON_CLK_WIFIPWR_EN_M  (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S)
-#define MODEM_LPCON_CLK_WIFIPWR_EN_V  0x00000001U
-#define MODEM_LPCON_CLK_WIFIPWR_EN_S  0
-/* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_EN    (BIT(1))
-#define MODEM_LPCON_CLK_COEX_EN_M  (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
-#define MODEM_LPCON_CLK_COEX_EN_V  0x00000001U
-#define MODEM_LPCON_CLK_COEX_EN_S  1
-/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_I2C_MST_EN    (BIT(2))
-#define MODEM_LPCON_CLK_I2C_MST_EN_M  (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
-#define MODEM_LPCON_CLK_I2C_MST_EN_V  0x00000001U
-#define MODEM_LPCON_CLK_I2C_MST_EN_S  2
-/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_TIMER_EN    (BIT(3))
-#define MODEM_LPCON_CLK_LP_TIMER_EN_M  (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S)
-#define MODEM_LPCON_CLK_LP_TIMER_EN_V  0x00000001U
-#define MODEM_LPCON_CLK_LP_TIMER_EN_S  3
-
-#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
-/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_FO    (BIT(0))
-#define MODEM_LPCON_CLK_WIFIPWR_FO_M  (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S)
-#define MODEM_LPCON_CLK_WIFIPWR_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_WIFIPWR_FO_S  0
-/* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_FO    (BIT(1))
-#define MODEM_LPCON_CLK_COEX_FO_M  (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
-#define MODEM_LPCON_CLK_COEX_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_COEX_FO_S  1
-/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_I2C_MST_FO    (BIT(2))
-#define MODEM_LPCON_CLK_I2C_MST_FO_M  (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
-#define MODEM_LPCON_CLK_I2C_MST_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_I2C_MST_FO_S  2
-/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_TIMER_FO    (BIT(3))
-#define MODEM_LPCON_CLK_LP_TIMER_FO_M  (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S)
-#define MODEM_LPCON_CLK_LP_TIMER_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_LP_TIMER_FO_S  3
-/* MODEM_LPCON_CLK_BCMEM_FO : R/W; bitpos: [4]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_BCMEM_FO    (BIT(4))
-#define MODEM_LPCON_CLK_BCMEM_FO_M  (MODEM_LPCON_CLK_BCMEM_FO_V << MODEM_LPCON_CLK_BCMEM_FO_S)
-#define MODEM_LPCON_CLK_BCMEM_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_BCMEM_FO_S  4
-/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W; bitpos: [5]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_I2C_MST_MEM_FO    (BIT(5))
-#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M  (MODEM_LPCON_CLK_I2C_MST_MEM_FO_V << MODEM_LPCON_CLK_I2C_MST_MEM_FO_S)
-#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S  5
-/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W; bitpos: [6]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO    (BIT(6))
-#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M  (MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V << MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S)
-#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S  6
-/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W; bitpos: [7]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_PBUS_MEM_FO    (BIT(7))
-#define MODEM_LPCON_CLK_PBUS_MEM_FO_M  (MODEM_LPCON_CLK_PBUS_MEM_FO_V << MODEM_LPCON_CLK_PBUS_MEM_FO_S)
-#define MODEM_LPCON_CLK_PBUS_MEM_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_PBUS_MEM_FO_S  7
-/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W; bitpos: [8]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_AGC_MEM_FO    (BIT(8))
-#define MODEM_LPCON_CLK_AGC_MEM_FO_M  (MODEM_LPCON_CLK_AGC_MEM_FO_V << MODEM_LPCON_CLK_AGC_MEM_FO_S)
-#define MODEM_LPCON_CLK_AGC_MEM_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_AGC_MEM_FO_S  8
-/* MODEM_LPCON_CLK_DC_MEM_FO : R/W; bitpos: [9]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_DC_MEM_FO    (BIT(9))
-#define MODEM_LPCON_CLK_DC_MEM_FO_M  (MODEM_LPCON_CLK_DC_MEM_FO_V << MODEM_LPCON_CLK_DC_MEM_FO_S)
-#define MODEM_LPCON_CLK_DC_MEM_FO_V  0x00000001U
-#define MODEM_LPCON_CLK_DC_MEM_FO_S  9
-
-#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
-/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP    0x0000000FU
-#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M  (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)
-#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V  0x0000000FU
-#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S  16
-/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_COEX_ST_MAP    0x0000000FU
-#define MODEM_LPCON_CLK_COEX_ST_MAP_M  (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S)
-#define MODEM_LPCON_CLK_COEX_ST_MAP_V  0x0000000FU
-#define MODEM_LPCON_CLK_COEX_ST_MAP_S  20
-/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_I2C_MST_ST_MAP    0x0000000FU
-#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M  (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)
-#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V  0x0000000FU
-#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S  24
-/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CLK_LP_APB_ST_MAP    0x0000000FU
-#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M  (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S)
-#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V  0x0000000FU
-#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S  28
-
-#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
-/* MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_LPCON_RST_WIFIPWR    (BIT(0))
-#define MODEM_LPCON_RST_WIFIPWR_M  (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S)
-#define MODEM_LPCON_RST_WIFIPWR_V  0x00000001U
-#define MODEM_LPCON_RST_WIFIPWR_S  0
-/* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_RST_COEX    (BIT(1))
-#define MODEM_LPCON_RST_COEX_M  (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
-#define MODEM_LPCON_RST_COEX_V  0x00000001U
-#define MODEM_LPCON_RST_COEX_S  1
-/* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_LPCON_RST_I2C_MST    (BIT(2))
-#define MODEM_LPCON_RST_I2C_MST_M  (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
-#define MODEM_LPCON_RST_I2C_MST_V  0x00000001U
-#define MODEM_LPCON_RST_I2C_MST_S  2
-/* MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_LPCON_RST_LP_TIMER    (BIT(3))
-#define MODEM_LPCON_RST_LP_TIMER_M  (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S)
-#define MODEM_LPCON_RST_LP_TIMER_V  0x00000001U
-#define MODEM_LPCON_RST_LP_TIMER_S  3
-
-#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
-/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1; */
-/*description: */
-#define MODEM_LPCON_DC_MEM_FORCE_PU    (BIT(0))
-#define MODEM_LPCON_DC_MEM_FORCE_PU_M  (MODEM_LPCON_DC_MEM_FORCE_PU_V << MODEM_LPCON_DC_MEM_FORCE_PU_S)
-#define MODEM_LPCON_DC_MEM_FORCE_PU_V  0x00000001U
-#define MODEM_LPCON_DC_MEM_FORCE_PU_S  0
-/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_LPCON_DC_MEM_FORCE_PD    (BIT(1))
-#define MODEM_LPCON_DC_MEM_FORCE_PD_M  (MODEM_LPCON_DC_MEM_FORCE_PD_V << MODEM_LPCON_DC_MEM_FORCE_PD_S)
-#define MODEM_LPCON_DC_MEM_FORCE_PD_V  0x00000001U
-#define MODEM_LPCON_DC_MEM_FORCE_PD_S  1
-/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; */
-/*description: */
-#define MODEM_LPCON_AGC_MEM_FORCE_PU    (BIT(2))
-#define MODEM_LPCON_AGC_MEM_FORCE_PU_M  (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S)
-#define MODEM_LPCON_AGC_MEM_FORCE_PU_V  0x00000001U
-#define MODEM_LPCON_AGC_MEM_FORCE_PU_S  2
-/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_LPCON_AGC_MEM_FORCE_PD    (BIT(3))
-#define MODEM_LPCON_AGC_MEM_FORCE_PD_M  (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S)
-#define MODEM_LPCON_AGC_MEM_FORCE_PD_V  0x00000001U
-#define MODEM_LPCON_AGC_MEM_FORCE_PD_S  3
-/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; */
-/*description: */
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU    (BIT(4))
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M  (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S)
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V  0x00000001U
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S  4
-/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; */
-/*description: */
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD    (BIT(5))
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M  (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S)
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V  0x00000001U
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S  5
-/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W; bitpos: [6]; default: 0; */
-/*description: */
-#define MODEM_LPCON_BC_MEM_FORCE_PU    (BIT(6))
-#define MODEM_LPCON_BC_MEM_FORCE_PU_M  (MODEM_LPCON_BC_MEM_FORCE_PU_V << MODEM_LPCON_BC_MEM_FORCE_PU_S)
-#define MODEM_LPCON_BC_MEM_FORCE_PU_V  0x00000001U
-#define MODEM_LPCON_BC_MEM_FORCE_PU_S  6
-/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W; bitpos: [7]; default: 0; */
-/*description: */
-#define MODEM_LPCON_BC_MEM_FORCE_PD    (BIT(7))
-#define MODEM_LPCON_BC_MEM_FORCE_PD_M  (MODEM_LPCON_BC_MEM_FORCE_PD_V << MODEM_LPCON_BC_MEM_FORCE_PD_S)
-#define MODEM_LPCON_BC_MEM_FORCE_PD_V  0x00000001U
-#define MODEM_LPCON_BC_MEM_FORCE_PD_S  7
-/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0; */
-/*description: */
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU    (BIT(8))
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M  (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S)
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V  0x00000001U
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S  8
-/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0; */
-/*description: */
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD    (BIT(9))
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M  (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S)
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V  0x00000001U
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S  9
-/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU    (BIT(10))
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M  (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S)
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V  0x00000001U
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S  10
-/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0; */
-/*description: */
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD    (BIT(11))
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M  (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S)
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V  0x00000001U
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S  11
-/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0; */
-/*description: */
-#define MODEM_LPCON_MODEM_PWR_MEM_WP    0x00000007U
-#define MODEM_LPCON_MODEM_PWR_MEM_WP_M  (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S)
-#define MODEM_LPCON_MODEM_PWR_MEM_WP_V  0x00000007U
-#define MODEM_LPCON_MODEM_PWR_MEM_WP_S  12
-/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 4; */
-/*description: */
-#define MODEM_LPCON_MODEM_PWR_MEM_WA    0x00000007U
-#define MODEM_LPCON_MODEM_PWR_MEM_WA_M  (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S)
-#define MODEM_LPCON_MODEM_PWR_MEM_WA_V  0x00000007U
-#define MODEM_LPCON_MODEM_PWR_MEM_WA_S  15
-/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0; */
-/*description: */
-#define MODEM_LPCON_MODEM_PWR_MEM_RA    0x00000003U
-#define MODEM_LPCON_MODEM_PWR_MEM_RA_M  (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S)
-#define MODEM_LPCON_MODEM_PWR_MEM_RA_V  0x00000003U
-#define MODEM_LPCON_MODEM_PWR_MEM_RA_S  18
-
-#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x2c)
-/* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35676736; */
-/*description: */
-#define MODEM_LPCON_DATE    0x0FFFFFFFU
-#define MODEM_LPCON_DATE_M  (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
-#define MODEM_LPCON_DATE_V  0x0FFFFFFFU
-#define MODEM_LPCON_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/modem/modem_lpcon_struct.h b/components/soc/esp32p4/include/modem/modem_lpcon_struct.h
deleted file mode 100644
index f27074fcee..0000000000
--- a/components/soc/esp32p4/include/modem/modem_lpcon_struct.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef union {
-    struct {
-        uint32_t clk_en:1;
-        uint32_t clk_debug_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} modem_lpcon_test_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_lp_timer_sel_osc_slow:1;
-        uint32_t clk_lp_timer_sel_osc_fast:1;
-        uint32_t clk_lp_timer_sel_xtal:1;
-        uint32_t clk_lp_timer_sel_xtal32k:1;
-        uint32_t clk_lp_timer_div_num:12;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} modem_lpcon_lp_timer_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_coex_lp_sel_osc_slow:1;
-        uint32_t clk_coex_lp_sel_osc_fast:1;
-        uint32_t clk_coex_lp_sel_xtal:1;
-        uint32_t clk_coex_lp_sel_xtal32k:1;
-        uint32_t clk_coex_lp_div_num:12;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} modem_lpcon_coex_lp_clk_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_wifipwr_lp_sel_osc_slow:1;
-        uint32_t clk_wifipwr_lp_sel_osc_fast:1;
-        uint32_t clk_wifipwr_lp_sel_xtal:1;
-        uint32_t clk_wifipwr_lp_sel_xtal32k:1;
-        uint32_t clk_wifipwr_lp_div_num:12;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} modem_lpcon_wifi_lp_clk_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_i2c_mst_sel_160m:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} modem_lpcon_i2c_mst_clk_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_modem_32k_sel:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} modem_lpcon_modem_32k_clk_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_wifipwr_en:1;
-        uint32_t clk_coex_en:1;
-        uint32_t clk_i2c_mst_en:1;
-        uint32_t clk_lp_timer_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} modem_lpcon_clk_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_wifipwr_fo:1;
-        uint32_t clk_coex_fo:1;
-        uint32_t clk_i2c_mst_fo:1;
-        uint32_t clk_lp_timer_fo:1;
-        uint32_t clk_bcmem_fo:1;
-        uint32_t clk_i2c_mst_mem_fo:1;
-        uint32_t clk_chan_freq_mem_fo:1;
-        uint32_t clk_pbus_mem_fo:1;
-        uint32_t clk_agc_mem_fo:1;
-        uint32_t clk_dc_mem_fo:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} modem_lpcon_clk_conf_force_on_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        uint32_t clk_wifipwr_st_map:4;
-        uint32_t clk_coex_st_map:4;
-        uint32_t clk_i2c_mst_st_map:4;
-        uint32_t clk_lp_apb_st_map:4;
-    };
-    uint32_t val;
-} modem_lpcon_clk_conf_power_st_reg_t;
-
-typedef union {
-    struct {
-        uint32_t rst_wifipwr:1;
-        uint32_t rst_coex:1;
-        uint32_t rst_i2c_mst:1;
-        uint32_t rst_lp_timer:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} modem_lpcon_rst_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t dc_mem_force_pu:1;
-        uint32_t dc_mem_force_pd:1;
-        uint32_t agc_mem_force_pu:1;
-        uint32_t agc_mem_force_pd:1;
-        uint32_t pbus_mem_force_pu:1;
-        uint32_t pbus_mem_force_pd:1;
-        uint32_t bc_mem_force_pu:1;
-        uint32_t bc_mem_force_pd:1;
-        uint32_t i2c_mst_mem_force_pu:1;
-        uint32_t i2c_mst_mem_force_pd:1;
-        uint32_t chan_freq_mem_force_pu:1;
-        uint32_t chan_freq_mem_force_pd:1;
-        uint32_t modem_pwr_mem_wp:3;
-        uint32_t modem_pwr_mem_wa:3;
-        uint32_t modem_pwr_mem_ra:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} modem_lpcon_mem_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} modem_lpcon_date_reg_t;
-
-
-typedef struct {
-    volatile modem_lpcon_test_conf_reg_t test_conf;
-    volatile modem_lpcon_lp_timer_conf_reg_t lp_timer_conf;
-    volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf;
-    volatile modem_lpcon_wifi_lp_clk_conf_reg_t wifi_lp_clk_conf;
-    volatile modem_lpcon_i2c_mst_clk_conf_reg_t i2c_mst_clk_conf;
-    volatile modem_lpcon_modem_32k_clk_conf_reg_t modem_32k_clk_conf;
-    volatile modem_lpcon_clk_conf_reg_t clk_conf;
-    volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on;
-    volatile modem_lpcon_clk_conf_power_st_reg_t clk_conf_power_st;
-    volatile modem_lpcon_rst_conf_reg_t rst_conf;
-    volatile modem_lpcon_mem_conf_reg_t mem_conf;
-    volatile modem_lpcon_date_reg_t date;
-} modem_lpcon_dev_t;
-
-extern modem_lpcon_dev_t MODEM_LPCON;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(modem_lpcon_dev_t) == 0x30, "Invalid size of modem_lpcon_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/modem/modem_syscon_reg.h b/components/soc/esp32p4/include/modem/modem_syscon_reg.h
deleted file mode 100644
index 2feabbd036..0000000000
--- a/components/soc/esp32p4/include/modem/modem_syscon_reg.h
+++ /dev/null
@@ -1,612 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- *//*description: */
-#pragma once
-
-#include <stdint.h>
-#include "modem/reg_base.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
-/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_EN    (BIT(0))
-#define MODEM_SYSCON_CLK_EN_M  (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S)
-#define MODEM_SYSCON_CLK_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_EN_S  0
-
-#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
-/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 1; */
-/*description: */
-#define MODEM_SYSCON_CLK_DATA_DUMP_MUX    (BIT(21))
-#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M  (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S)
-#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V  0x00000001U
-#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S  21
-/* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_ETM_EN    (BIT(22))
-#define MODEM_SYSCON_CLK_ETM_EN_M  (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S)
-#define MODEM_SYSCON_CLK_ETM_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_ETM_EN_S  22
-/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_ZB_APB_EN    (BIT(23))
-#define MODEM_SYSCON_CLK_ZB_APB_EN_M  (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S)
-#define MODEM_SYSCON_CLK_ZB_APB_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_ZB_APB_EN_S  23
-/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [24]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_ZB_MAC_EN    (BIT(24))
-#define MODEM_SYSCON_CLK_ZB_MAC_EN_M  (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S)
-#define MODEM_SYSCON_CLK_ZB_MAC_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_ZB_MAC_EN_S  24
-/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN    (BIT(25))
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S  25
-/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN    (BIT(26))
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S  26
-/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN    (BIT(27))
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S  27
-/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN    (BIT(28))
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S  28
-/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_EN    (BIT(29))
-#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S  29
-/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_BLE_TIMER_EN    (BIT(30))
-#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M  (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S)
-#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S  30
-/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_DATA_DUMP_EN    (BIT(31))
-#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M  (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S)
-#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S  31
-
-#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8)
-/* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_ETM_FO    (BIT(22))
-#define MODEM_SYSCON_CLK_ETM_FO_M  (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S)
-#define MODEM_SYSCON_CLK_ETM_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_ETM_FO_S  22
-/* MODEM_SYSCON_CLK_ZB_APB_FO : R/W; bitpos: [23]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_ZB_APB_FO    (BIT(23))
-#define MODEM_SYSCON_CLK_ZB_APB_FO_M  (MODEM_SYSCON_CLK_ZB_APB_FO_V << MODEM_SYSCON_CLK_ZB_APB_FO_S)
-#define MODEM_SYSCON_CLK_ZB_APB_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_ZB_APB_FO_S  23
-/* MODEM_SYSCON_CLK_ZB_MAC_FO : R/W; bitpos: [24]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_ZB_MAC_FO    (BIT(24))
-#define MODEM_SYSCON_CLK_ZB_MAC_FO_M  (MODEM_SYSCON_CLK_ZB_MAC_FO_V << MODEM_SYSCON_CLK_ZB_MAC_FO_S)
-#define MODEM_SYSCON_CLK_ZB_MAC_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_ZB_MAC_FO_S  24
-/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO : R/W; bitpos: [25]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO    (BIT(25))
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S  25
-/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO : R/W; bitpos: [26]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO    (BIT(26))
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S  26
-/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO : R/W; bitpos: [27]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO    (BIT(27))
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S  27
-/* MODEM_SYSCON_CLK_MODEM_SEC_APB_FO : R/W; bitpos: [28]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO    (BIT(28))
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S  28
-/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_SEC_FO    (BIT(29))
-#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S)
-#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S  29
-/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_BLE_TIMER_FO    (BIT(30))
-#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M  (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S)
-#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S  30
-/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_DATA_DUMP_FO    (BIT(31))
-#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M  (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S)
-#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S  31
-
-#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc)
-/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_ZB_ST_MAP    0x0000000FU
-#define MODEM_SYSCON_CLK_ZB_ST_MAP_M  (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S)
-#define MODEM_SYSCON_CLK_ZB_ST_MAP_V  0x0000000FU
-#define MODEM_SYSCON_CLK_ZB_ST_MAP_S  8
-/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_ST_MAP    0x0000000FU
-#define MODEM_SYSCON_CLK_FE_ST_MAP_M  (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S)
-#define MODEM_SYSCON_CLK_FE_ST_MAP_V  0x0000000FU
-#define MODEM_SYSCON_CLK_FE_ST_MAP_S  12
-/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_BT_ST_MAP    0x0000000FU
-#define MODEM_SYSCON_CLK_BT_ST_MAP_M  (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S)
-#define MODEM_SYSCON_CLK_BT_ST_MAP_V  0x0000000FU
-#define MODEM_SYSCON_CLK_BT_ST_MAP_S  16
-/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFI_ST_MAP    0x0000000FU
-#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M  (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S)
-#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V  0x0000000FU
-#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S  20
-/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP    0x0000000FU
-#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M  (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)
-#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V  0x0000000FU
-#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S  24
-/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP    0x0000000FU
-#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M  (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)
-#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V  0x0000000FU
-#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S  28
-
-#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
-/* MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_WIFIBB    (BIT(8))
-#define MODEM_SYSCON_RST_WIFIBB_M  (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S)
-#define MODEM_SYSCON_RST_WIFIBB_V  0x00000001U
-#define MODEM_SYSCON_RST_WIFIBB_S  8
-/* MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [10]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_WIFIMAC    (BIT(10))
-#define MODEM_SYSCON_RST_WIFIMAC_M  (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S)
-#define MODEM_SYSCON_RST_WIFIMAC_V  0x00000001U
-#define MODEM_SYSCON_RST_WIFIMAC_S  10
-/* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_FE    (BIT(14))
-#define MODEM_SYSCON_RST_FE_M  (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S)
-#define MODEM_SYSCON_RST_FE_V  0x00000001U
-#define MODEM_SYSCON_RST_FE_S  14
-/* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_BTMAC_APB    (BIT(15))
-#define MODEM_SYSCON_RST_BTMAC_APB_M  (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S)
-#define MODEM_SYSCON_RST_BTMAC_APB_V  0x00000001U
-#define MODEM_SYSCON_RST_BTMAC_APB_S  15
-/* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_BTMAC    (BIT(16))
-#define MODEM_SYSCON_RST_BTMAC_M  (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S)
-#define MODEM_SYSCON_RST_BTMAC_V  0x00000001U
-#define MODEM_SYSCON_RST_BTMAC_S  16
-/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_BTBB_APB    (BIT(17))
-#define MODEM_SYSCON_RST_BTBB_APB_M  (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S)
-#define MODEM_SYSCON_RST_BTBB_APB_V  0x00000001U
-#define MODEM_SYSCON_RST_BTBB_APB_S  17
-/* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_BTBB    (BIT(18))
-#define MODEM_SYSCON_RST_BTBB_M  (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S)
-#define MODEM_SYSCON_RST_BTBB_V  0x00000001U
-#define MODEM_SYSCON_RST_BTBB_S  18
-/* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_ETM    (BIT(22))
-#define MODEM_SYSCON_RST_ETM_M  (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S)
-#define MODEM_SYSCON_RST_ETM_V  0x00000001U
-#define MODEM_SYSCON_RST_ETM_S  22
-/* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_ZBMAC    (BIT(24))
-#define MODEM_SYSCON_RST_ZBMAC_M  (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S)
-#define MODEM_SYSCON_RST_ZBMAC_V  0x00000001U
-#define MODEM_SYSCON_RST_ZBMAC_S  24
-/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_MODEM_ECB    (BIT(25))
-#define MODEM_SYSCON_RST_MODEM_ECB_M  (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S)
-#define MODEM_SYSCON_RST_MODEM_ECB_V  0x00000001U
-#define MODEM_SYSCON_RST_MODEM_ECB_S  25
-/* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_MODEM_CCM    (BIT(26))
-#define MODEM_SYSCON_RST_MODEM_CCM_M  (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S)
-#define MODEM_SYSCON_RST_MODEM_CCM_V  0x00000001U
-#define MODEM_SYSCON_RST_MODEM_CCM_S  26
-/* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_MODEM_BAH    (BIT(27))
-#define MODEM_SYSCON_RST_MODEM_BAH_M  (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S)
-#define MODEM_SYSCON_RST_MODEM_BAH_V  0x00000001U
-#define MODEM_SYSCON_RST_MODEM_BAH_S  27
-/* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_MODEM_SEC    (BIT(29))
-#define MODEM_SYSCON_RST_MODEM_SEC_M  (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S)
-#define MODEM_SYSCON_RST_MODEM_SEC_V  0x00000001U
-#define MODEM_SYSCON_RST_MODEM_SEC_S  29
-/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_BLE_TIMER    (BIT(30))
-#define MODEM_SYSCON_RST_BLE_TIMER_M  (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S)
-#define MODEM_SYSCON_RST_BLE_TIMER_V  0x00000001U
-#define MODEM_SYSCON_RST_BLE_TIMER_S  30
-/* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_RST_DATA_DUMP    (BIT(31))
-#define MODEM_SYSCON_RST_DATA_DUMP_M  (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S)
-#define MODEM_SYSCON_RST_DATA_DUMP_V  0x00000001U
-#define MODEM_SYSCON_RST_DATA_DUMP_S  31
-
-#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14)
-/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_22M_EN    (BIT(0))
-#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S  0
-/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_40M_EN    (BIT(1))
-#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S  1
-/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_44M_EN    (BIT(2))
-#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S  2
-/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_80M_EN    (BIT(3))
-#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S  3
-/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_40X_EN    (BIT(4))
-#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S  4
-/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_80X_EN    (BIT(5))
-#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S  5
-/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN    (BIT(6))
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S  6
-/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN    (BIT(7))
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S  7
-/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN    (BIT(8))
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S  8
-/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIMAC_EN    (BIT(9))
-#define MODEM_SYSCON_CLK_WIFIMAC_EN_M  (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S)
-#define MODEM_SYSCON_CLK_WIFIMAC_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIMAC_EN_S  9
-/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFI_APB_EN    (BIT(10))
-#define MODEM_SYSCON_CLK_WIFI_APB_EN_M  (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S)
-#define MODEM_SYSCON_CLK_WIFI_APB_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFI_APB_EN_S  10
-/* MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_20M_EN    (BIT(11))
-#define MODEM_SYSCON_CLK_FE_20M_EN_M  (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S)
-#define MODEM_SYSCON_CLK_FE_20M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_20M_EN_S  11
-/* MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_40M_EN    (BIT(12))
-#define MODEM_SYSCON_CLK_FE_40M_EN_M  (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S)
-#define MODEM_SYSCON_CLK_FE_40M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_40M_EN_S  12
-/* MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_80M_EN    (BIT(13))
-#define MODEM_SYSCON_CLK_FE_80M_EN_M  (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S)
-#define MODEM_SYSCON_CLK_FE_80M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_80M_EN_S  13
-/* MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_160M_EN    (BIT(14))
-#define MODEM_SYSCON_CLK_FE_160M_EN_M  (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S)
-#define MODEM_SYSCON_CLK_FE_160M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_160M_EN_S  14
-/* MODEM_SYSCON_CLK_FE_CAL_160M_EN : R/W; bitpos: [15]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_CAL_160M_EN    (BIT(15))
-#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_M  (MODEM_SYSCON_CLK_FE_CAL_160M_EN_V << MODEM_SYSCON_CLK_FE_CAL_160M_EN_S)
-#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_S  15
-/* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_APB_EN    (BIT(16))
-#define MODEM_SYSCON_CLK_FE_APB_EN_M  (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S)
-#define MODEM_SYSCON_CLK_FE_APB_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_APB_EN_S  16
-/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_BT_APB_EN    (BIT(17))
-#define MODEM_SYSCON_CLK_BT_APB_EN_M  (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S)
-#define MODEM_SYSCON_CLK_BT_APB_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_BT_APB_EN_S  17
-/* MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_BT_EN    (BIT(18))
-#define MODEM_SYSCON_CLK_BT_EN_M  (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S)
-#define MODEM_SYSCON_CLK_BT_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_BT_EN_S  18
-/* MODEM_SYSCON_CLK_WIFIBB_480M_EN : R/W; bitpos: [19]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_480M_EN    (BIT(19))
-#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_480M_EN_V << MODEM_SYSCON_CLK_WIFIBB_480M_EN_S)
-#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_S  19
-/* MODEM_SYSCON_CLK_FE_480M_EN : R/W; bitpos: [20]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_480M_EN    (BIT(20))
-#define MODEM_SYSCON_CLK_FE_480M_EN_M  (MODEM_SYSCON_CLK_FE_480M_EN_V << MODEM_SYSCON_CLK_FE_480M_EN_S)
-#define MODEM_SYSCON_CLK_FE_480M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_480M_EN_S  20
-/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN : R/W; bitpos: [21]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN    (BIT(21))
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_M  (MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S)
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S  21
-/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN : R/W; bitpos: [22]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN    (BIT(22))
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_M  (MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S)
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S  22
-/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN : R/W; bitpos: [23]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN    (BIT(23))
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_M  (MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S)
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S  23
-
-#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x18)
-/* MODEM_SYSCON_CLK_WIFIBB_22M_FO : R/W; bitpos: [0]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_22M_FO    (BIT(0))
-#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_22M_FO_V << MODEM_SYSCON_CLK_WIFIBB_22M_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_S  0
-/* MODEM_SYSCON_CLK_WIFIBB_40M_FO : R/W; bitpos: [1]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_40M_FO    (BIT(1))
-#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40M_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_S  1
-/* MODEM_SYSCON_CLK_WIFIBB_44M_FO : R/W; bitpos: [2]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_44M_FO    (BIT(2))
-#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_44M_FO_V << MODEM_SYSCON_CLK_WIFIBB_44M_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_S  2
-/* MODEM_SYSCON_CLK_WIFIBB_80M_FO : R/W; bitpos: [3]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_80M_FO    (BIT(3))
-#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80M_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_S  3
-/* MODEM_SYSCON_CLK_WIFIBB_40X_FO : R/W; bitpos: [4]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_40X_FO    (BIT(4))
-#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40X_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_S  4
-/* MODEM_SYSCON_CLK_WIFIBB_80X_FO : R/W; bitpos: [5]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_80X_FO    (BIT(5))
-#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80X_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_S  5
-/* MODEM_SYSCON_CLK_WIFIBB_40X1_FO : R/W; bitpos: [6]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO    (BIT(6))
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S  6
-/* MODEM_SYSCON_CLK_WIFIBB_80X1_FO : R/W; bitpos: [7]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO    (BIT(7))
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S  7
-/* MODEM_SYSCON_CLK_WIFIBB_160X1_FO : R/W; bitpos: [8]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO    (BIT(8))
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S  8
-/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [9]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIMAC_FO    (BIT(9))
-#define MODEM_SYSCON_CLK_WIFIMAC_FO_M  (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S)
-#define MODEM_SYSCON_CLK_WIFIMAC_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIMAC_FO_S  9
-/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [10]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFI_APB_FO    (BIT(10))
-#define MODEM_SYSCON_CLK_WIFI_APB_FO_M  (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S)
-#define MODEM_SYSCON_CLK_WIFI_APB_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFI_APB_FO_S  10
-/* MODEM_SYSCON_CLK_FE_20M_FO : R/W; bitpos: [11]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_20M_FO    (BIT(11))
-#define MODEM_SYSCON_CLK_FE_20M_FO_M  (MODEM_SYSCON_CLK_FE_20M_FO_V << MODEM_SYSCON_CLK_FE_20M_FO_S)
-#define MODEM_SYSCON_CLK_FE_20M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_20M_FO_S  11
-/* MODEM_SYSCON_CLK_FE_40M_FO : R/W; bitpos: [12]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_40M_FO    (BIT(12))
-#define MODEM_SYSCON_CLK_FE_40M_FO_M  (MODEM_SYSCON_CLK_FE_40M_FO_V << MODEM_SYSCON_CLK_FE_40M_FO_S)
-#define MODEM_SYSCON_CLK_FE_40M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_40M_FO_S  12
-/* MODEM_SYSCON_CLK_FE_80M_FO : R/W; bitpos: [13]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_80M_FO    (BIT(13))
-#define MODEM_SYSCON_CLK_FE_80M_FO_M  (MODEM_SYSCON_CLK_FE_80M_FO_V << MODEM_SYSCON_CLK_FE_80M_FO_S)
-#define MODEM_SYSCON_CLK_FE_80M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_80M_FO_S  13
-/* MODEM_SYSCON_CLK_FE_160M_FO : R/W; bitpos: [14]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_160M_FO    (BIT(14))
-#define MODEM_SYSCON_CLK_FE_160M_FO_M  (MODEM_SYSCON_CLK_FE_160M_FO_V << MODEM_SYSCON_CLK_FE_160M_FO_S)
-#define MODEM_SYSCON_CLK_FE_160M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_160M_FO_S  14
-/* MODEM_SYSCON_CLK_FE_CAL_160M_FO : R/W; bitpos: [15]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_CAL_160M_FO    (BIT(15))
-#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_M  (MODEM_SYSCON_CLK_FE_CAL_160M_FO_V << MODEM_SYSCON_CLK_FE_CAL_160M_FO_S)
-#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_S  15
-/* MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [16]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_APB_FO    (BIT(16))
-#define MODEM_SYSCON_CLK_FE_APB_FO_M  (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S)
-#define MODEM_SYSCON_CLK_FE_APB_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_APB_FO_S  16
-/* MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [17]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_BT_APB_FO    (BIT(17))
-#define MODEM_SYSCON_CLK_BT_APB_FO_M  (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S)
-#define MODEM_SYSCON_CLK_BT_APB_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_BT_APB_FO_S  17
-/* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_BT_FO    (BIT(18))
-#define MODEM_SYSCON_CLK_BT_FO_M  (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S)
-#define MODEM_SYSCON_CLK_BT_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_BT_FO_S  18
-/* MODEM_SYSCON_CLK_WIFIBB_480M_FO : R/W; bitpos: [19]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_WIFIBB_480M_FO    (BIT(19))
-#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_480M_FO_V << MODEM_SYSCON_CLK_WIFIBB_480M_FO_S)
-#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_S  19
-/* MODEM_SYSCON_CLK_FE_480M_FO : R/W; bitpos: [20]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_480M_FO    (BIT(20))
-#define MODEM_SYSCON_CLK_FE_480M_FO_M  (MODEM_SYSCON_CLK_FE_480M_FO_V << MODEM_SYSCON_CLK_FE_480M_FO_S)
-#define MODEM_SYSCON_CLK_FE_480M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_480M_FO_S  20
-/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO : R/W; bitpos: [21]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO    (BIT(21))
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_M  (MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S)
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S  21
-/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO : R/W; bitpos: [22]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO    (BIT(22))
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_M  (MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S)
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S  22
-/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO : R/W; bitpos: [23]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO    (BIT(23))
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_M  (MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S)
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V  0x00000001U
-#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S  23
-
-#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c)
-/* MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_WIFI_BB_CFG    0xFFFFFFFFU
-#define MODEM_SYSCON_WIFI_BB_CFG_M  (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S)
-#define MODEM_SYSCON_WIFI_BB_CFG_V  0xFFFFFFFFU
-#define MODEM_SYSCON_WIFI_BB_CFG_S  0
-
-#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20)
-/* MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_MODEM_MEM_WP    0x00000007U
-#define MODEM_SYSCON_MODEM_MEM_WP_M  (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S)
-#define MODEM_SYSCON_MODEM_MEM_WP_V  0x00000007U
-#define MODEM_SYSCON_MODEM_MEM_WP_S  0
-/* MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 4; */
-/*description: */
-#define MODEM_SYSCON_MODEM_MEM_WA    0x00000007U
-#define MODEM_SYSCON_MODEM_MEM_WA_M  (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S)
-#define MODEM_SYSCON_MODEM_MEM_WA_V  0x00000007U
-#define MODEM_SYSCON_MODEM_MEM_WA_S  3
-/* MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0; */
-/*description: */
-#define MODEM_SYSCON_MODEM_MEM_RA    0x00000003U
-#define MODEM_SYSCON_MODEM_MEM_RA_M  (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S)
-#define MODEM_SYSCON_MODEM_MEM_RA_V  0x00000003U
-#define MODEM_SYSCON_MODEM_MEM_RA_S  6
-
-#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24)
-/* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 35676928; */
-/*description: */
-#define MODEM_SYSCON_DATE    0x0FFFFFFFU
-#define MODEM_SYSCON_DATE_M  (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S)
-#define MODEM_SYSCON_DATE_V  0x0FFFFFFFU
-#define MODEM_SYSCON_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/modem/modem_syscon_struct.h b/components/soc/esp32p4/include/modem/modem_syscon_struct.h
deleted file mode 100644
index 2635e741b9..0000000000
--- a/components/soc/esp32p4/include/modem/modem_syscon_struct.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef union {
-    struct {
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} modem_syscon_test_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        uint32_t clk_data_dump_mux:1;
-        uint32_t clk_etm_en:1;
-        uint32_t clk_zb_apb_en:1;
-        uint32_t clk_zb_mac_en:1;
-        uint32_t clk_modem_sec_ecb_en:1;
-        uint32_t clk_modem_sec_ccm_en:1;
-        uint32_t clk_modem_sec_bah_en:1;
-        uint32_t clk_modem_sec_apb_en:1;
-        uint32_t clk_modem_sec_en:1;
-        uint32_t clk_ble_timer_en:1;
-        uint32_t clk_data_dump_en:1;
-    };
-    uint32_t val;
-} modem_syscon_clk_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        uint32_t clk_etm_fo:1;
-        uint32_t clk_zb_apb_fo:1;
-        uint32_t clk_zb_mac_fo:1;
-        uint32_t clk_modem_sec_ecb_fo:1;
-        uint32_t clk_modem_sec_ccm_fo:1;
-        uint32_t clk_modem_sec_bah_fo:1;
-        uint32_t clk_modem_sec_apb_fo:1;
-        uint32_t clk_modem_sec_fo:1;
-        uint32_t clk_ble_timer_fo:1;
-        uint32_t clk_data_dump_fo:1;
-    };
-    uint32_t val;
-} modem_syscon_clk_conf_force_on_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        uint32_t clk_zb_st_map:4;
-        uint32_t clk_fe_st_map:4;
-        uint32_t clk_bt_st_map:4;
-        uint32_t clk_wifi_st_map:4;
-        uint32_t clk_modem_peri_st_map:4;
-        uint32_t clk_modem_apb_st_map:4;
-    };
-    uint32_t val;
-} modem_syscon_clk_conf_power_st_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        uint32_t rst_wifibb:1;
-        uint32_t reserved_9:1;
-        uint32_t rst_wifimac:1;
-        uint32_t reserved_11:3;
-        uint32_t rst_fe:1;
-        uint32_t rst_btmac_apb:1;
-        uint32_t rst_btmac:1;
-        uint32_t rst_btbb_apb:1;
-        uint32_t rst_btbb:1;
-        uint32_t reserved_19:3;
-        uint32_t rst_etm:1;
-        uint32_t reserved_23:1;
-        uint32_t rst_zbmac:1;
-        uint32_t rst_modem_ecb:1;
-        uint32_t rst_modem_ccm:1;
-        uint32_t rst_modem_bah:1;
-        uint32_t reserved_28:1;
-        uint32_t rst_modem_sec:1;
-        uint32_t rst_ble_timer:1;
-        uint32_t rst_data_dump:1;
-    };
-    uint32_t val;
-} modem_syscon_modem_rst_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_wifibb_22m_en:1;
-        uint32_t clk_wifibb_40m_en:1;
-        uint32_t clk_wifibb_44m_en:1;
-        uint32_t clk_wifibb_80m_en:1;
-        uint32_t clk_wifibb_40x_en:1;
-        uint32_t clk_wifibb_80x_en:1;
-        uint32_t clk_wifibb_40x1_en:1;
-        uint32_t clk_wifibb_80x1_en:1;
-        uint32_t clk_wifibb_160x1_en:1;
-        uint32_t clk_wifimac_en:1;
-        uint32_t clk_wifi_apb_en:1;
-        uint32_t clk_fe_20m_en:1;
-        uint32_t clk_fe_40m_en:1;
-        uint32_t clk_fe_80m_en:1;
-        uint32_t clk_fe_160m_en:1;
-        uint32_t clk_fe_cal_160m_en:1;
-        uint32_t clk_fe_apb_en:1;
-        uint32_t clk_bt_apb_en:1;
-        uint32_t clk_bt_en:1;
-        uint32_t clk_wifibb_480m_en:1;
-        uint32_t clk_fe_480m_en:1;
-        uint32_t clk_fe_anamode_40m_en:1;
-        uint32_t clk_fe_anamode_80m_en:1;
-        uint32_t clk_fe_anamode_160m_en:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} modem_syscon_clk_conf1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clk_wifibb_22m_fo:1;
-        uint32_t clk_wifibb_40m_fo:1;
-        uint32_t clk_wifibb_44m_fo:1;
-        uint32_t clk_wifibb_80m_fo:1;
-        uint32_t clk_wifibb_40x_fo:1;
-        uint32_t clk_wifibb_80x_fo:1;
-        uint32_t clk_wifibb_40x1_fo:1;
-        uint32_t clk_wifibb_80x1_fo:1;
-        uint32_t clk_wifibb_160x1_fo:1;
-        uint32_t clk_wifimac_fo:1;
-        uint32_t clk_wifi_apb_fo:1;
-        uint32_t clk_fe_20m_fo:1;
-        uint32_t clk_fe_40m_fo:1;
-        uint32_t clk_fe_80m_fo:1;
-        uint32_t clk_fe_160m_fo:1;
-        uint32_t clk_fe_cal_160m_fo:1;
-        uint32_t clk_fe_apb_fo:1;
-        uint32_t clk_bt_apb_fo:1;
-        uint32_t clk_bt_fo:1;
-        uint32_t clk_wifibb_480m_fo:1;
-        uint32_t clk_fe_480m_fo:1;
-        uint32_t clk_fe_anamode_40m_fo:1;
-        uint32_t clk_fe_anamode_80m_fo:1;
-        uint32_t clk_fe_anamode_160m_fo:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} modem_syscon_clk_conf1_force_on_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wifi_bb_cfg:32;
-    };
-    uint32_t val;
-} modem_syscon_wifi_bb_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modem_mem_wp:3;
-        uint32_t modem_mem_wa:3;
-        uint32_t modem_mem_ra:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} modem_syscon_mem_conf_reg_t;
-
-typedef union {
-    struct {
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} modem_syscon_date_reg_t;
-
-
-typedef struct {
-    volatile modem_syscon_test_conf_reg_t test_conf;
-    volatile modem_syscon_clk_conf_reg_t clk_conf;
-    volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on;
-    volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st;
-    volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf;
-    volatile modem_syscon_clk_conf1_reg_t clk_conf1;
-    volatile modem_syscon_clk_conf1_force_on_reg_t clk_conf1_force_on;
-    volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
-    volatile modem_syscon_mem_conf_reg_t mem_conf;
-    volatile modem_syscon_date_reg_t date;
-} modem_syscon_dev_t;
-
-extern modem_syscon_dev_t MODEM_SYSCON;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/modem/reg_base.h b/components/soc/esp32p4/include/modem/reg_base.h
deleted file mode 100644
index 7a0254eac0..0000000000
--- a/components/soc/esp32p4/include/modem/reg_base.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-#define DR_REG_MODEM_SYSCON_BASE  0x600A9800
-#define DR_REG_MODEM_LPCON_BASE   0x600AF000
diff --git a/components/soc/esp32p4/include/soc/adc_channel.h b/components/soc/esp32p4/include/soc/adc_channel.h
index dcdfb8633b..d2aa55b41e 100644
--- a/components/soc/esp32p4/include/soc/adc_channel.h
+++ b/components/soc/esp32p4/include/soc/adc_channel.h
@@ -5,24 +5,3 @@
  */
 
 #pragma once
-
-#define ADC1_GPIO0_CHANNEL      0
-#define ADC1_CHANNEL_0_GPIO_NUM 0
-
-#define ADC1_GPIO1_CHANNEL      1
-#define ADC1_CHANNEL_1_GPIO_NUM 1
-
-#define ADC1_GPIO2_CHANNEL      2
-#define ADC1_CHANNEL_2_GPIO_NUM 2
-
-#define ADC1_GPIO3_CHANNEL      3
-#define ADC1_CHANNEL_3_GPIO_NUM 3
-
-#define ADC1_GPIO4_CHANNEL      4
-#define ADC1_CHANNEL_4_GPIO_NUM 4
-
-#define ADC1_GPIO5_CHANNEL      5
-#define ADC1_CHANNEL_5_GPIO_NUM 5
-
-#define ADC1_GPIO6_CHANNEL      6
-#define ADC1_CHANNEL_6_GPIO_NUM 6
diff --git a/components/soc/esp32p4/include/soc/apb_saradc_reg.h b/components/soc/esp32p4/include/soc/apb_saradc_reg.h
deleted file mode 100644
index 933120275b..0000000000
--- a/components/soc/esp32p4/include/soc/apb_saradc_reg.h
+++ /dev/null
@@ -1,884 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** APB_SARADC_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
-/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
- *  select software enable saradc sample
- */
-#define APB_SARADC_SARADC_START_FORCE    (BIT(0))
-#define APB_SARADC_SARADC_START_FORCE_M  (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
-#define APB_SARADC_SARADC_START_FORCE_V  0x00000001U
-#define APB_SARADC_SARADC_START_FORCE_S  0
-/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
- *  software enable saradc sample
- */
-#define APB_SARADC_SARADC_START    (BIT(1))
-#define APB_SARADC_SARADC_START_M  (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
-#define APB_SARADC_SARADC_START_V  0x00000001U
-#define APB_SARADC_SARADC_START_S  1
-/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
- *  SAR clock gated
- */
-#define APB_SARADC_SARADC_SAR_CLK_GATED    (BIT(6))
-#define APB_SARADC_SARADC_SAR_CLK_GATED_M  (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
-#define APB_SARADC_SARADC_SAR_CLK_GATED_V  0x00000001U
-#define APB_SARADC_SARADC_SAR_CLK_GATED_S  6
-/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
- *  SAR clock divider
- */
-#define APB_SARADC_SARADC_SAR_CLK_DIV    0x000000FFU
-#define APB_SARADC_SARADC_SAR_CLK_DIV_M  (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
-#define APB_SARADC_SARADC_SAR_CLK_DIV_V  0x000000FFU
-#define APB_SARADC_SARADC_SAR_CLK_DIV_S  7
-/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
- *  0 ~ 15 means length 1 ~ 16
- */
-#define APB_SARADC_SARADC_SAR_PATT_LEN    0x00000007U
-#define APB_SARADC_SARADC_SAR_PATT_LEN_M  (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
-#define APB_SARADC_SARADC_SAR_PATT_LEN_V  0x00000007U
-#define APB_SARADC_SARADC_SAR_PATT_LEN_S  15
-/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
- *  clear the pointer of pattern table for DIG ADC1 CTRL
- */
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR    (BIT(23))
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M  (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V  0x00000001U
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S  23
-/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
- *  force option to xpd sar blocks
- */
-#define APB_SARADC_SARADC_XPD_SAR_FORCE    0x00000003U
-#define APB_SARADC_SARADC_XPD_SAR_FORCE_M  (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
-#define APB_SARADC_SARADC_XPD_SAR_FORCE_V  0x00000003U
-#define APB_SARADC_SARADC_XPD_SAR_FORCE_S  27
-/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
- *  enable saradc2 power detect driven func.
- */
-#define APB_SARADC_SARADC2_PWDET_DRV    (BIT(29))
-#define APB_SARADC_SARADC2_PWDET_DRV_M  (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
-#define APB_SARADC_SARADC2_PWDET_DRV_V  0x00000001U
-#define APB_SARADC_SARADC2_PWDET_DRV_S  29
-/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
- *  wait arbit signal stable after sar_done
- */
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE    0x00000003U
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M  (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V  0x00000003U
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S  30
-
-/** APB_SARADC_CTRL2_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
-/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
- *  enable max meas num
- */
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT    (BIT(0))
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M  (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V  0x00000001U
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S  0
-/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
- *  max conversion number
- */
-#define APB_SARADC_SARADC_MAX_MEAS_NUM    0x000000FFU
-#define APB_SARADC_SARADC_MAX_MEAS_NUM_M  (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
-#define APB_SARADC_SARADC_MAX_MEAS_NUM_V  0x000000FFU
-#define APB_SARADC_SARADC_MAX_MEAS_NUM_S  1
-/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
- *  1: data to DIG ADC1 CTRL is inverted, otherwise not
- */
-#define APB_SARADC_SARADC_SAR1_INV    (BIT(9))
-#define APB_SARADC_SARADC_SAR1_INV_M  (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
-#define APB_SARADC_SARADC_SAR1_INV_V  0x00000001U
-#define APB_SARADC_SARADC_SAR1_INV_S  9
-/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
- *  1: data to DIG ADC2 CTRL is inverted, otherwise not
- */
-#define APB_SARADC_SARADC_SAR2_INV    (BIT(10))
-#define APB_SARADC_SARADC_SAR2_INV_M  (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
-#define APB_SARADC_SARADC_SAR2_INV_V  0x00000001U
-#define APB_SARADC_SARADC_SAR2_INV_S  10
-/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
- *  to set saradc timer target
- */
-#define APB_SARADC_SARADC_TIMER_TARGET    0x00000FFFU
-#define APB_SARADC_SARADC_TIMER_TARGET_M  (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
-#define APB_SARADC_SARADC_TIMER_TARGET_V  0x00000FFFU
-#define APB_SARADC_SARADC_TIMER_TARGET_S  12
-/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
- *  to enable saradc timer trigger
- */
-#define APB_SARADC_SARADC_TIMER_EN    (BIT(24))
-#define APB_SARADC_SARADC_TIMER_EN_M  (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
-#define APB_SARADC_SARADC_TIMER_EN_V  0x00000001U
-#define APB_SARADC_SARADC_TIMER_EN_S  24
-
-/** APB_SARADC_FILTER_CTRL1_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
-/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
- *  Factor of saradc filter1
- */
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1    0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M  (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V  0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S  26
-/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
- *  Factor of saradc filter0
- */
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0    0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M  (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V  0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S  29
-
-/** APB_SARADC_FSM_WAIT_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc)
-/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8;
- *  saradc_xpd_wait
- */
-#define APB_SARADC_SARADC_XPD_WAIT    0x000000FFU
-#define APB_SARADC_SARADC_XPD_WAIT_M  (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S)
-#define APB_SARADC_SARADC_XPD_WAIT_V  0x000000FFU
-#define APB_SARADC_SARADC_XPD_WAIT_S  0
-/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8;
- *  saradc_rstb_wait
- */
-#define APB_SARADC_SARADC_RSTB_WAIT    0x000000FFU
-#define APB_SARADC_SARADC_RSTB_WAIT_M  (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S)
-#define APB_SARADC_SARADC_RSTB_WAIT_V  0x000000FFU
-#define APB_SARADC_SARADC_RSTB_WAIT_S  8
-/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255;
- *  saradc_standby_wait
- */
-#define APB_SARADC_SARADC_STANDBY_WAIT    0x000000FFU
-#define APB_SARADC_SARADC_STANDBY_WAIT_M  (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S)
-#define APB_SARADC_SARADC_STANDBY_WAIT_V  0x000000FFU
-#define APB_SARADC_SARADC_STANDBY_WAIT_S  16
-
-/** APB_SARADC_SAR1_STATUS_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
-/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912;
- *  saradc1 status about data and channel
- */
-#define APB_SARADC_SARADC_SAR1_STATUS    0xFFFFFFFFU
-#define APB_SARADC_SARADC_SAR1_STATUS_M  (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S)
-#define APB_SARADC_SARADC_SAR1_STATUS_V  0xFFFFFFFFU
-#define APB_SARADC_SARADC_SAR1_STATUS_S  0
-
-/** APB_SARADC_SAR2_STATUS_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
-/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912;
- *  saradc2 status about data and channel
- */
-#define APB_SARADC_SARADC_SAR2_STATUS    0xFFFFFFFFU
-#define APB_SARADC_SARADC_SAR2_STATUS_M  (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S)
-#define APB_SARADC_SARADC_SAR2_STATUS_V  0xFFFFFFFFU
-#define APB_SARADC_SARADC_SAR2_STATUS_S  0
-
-/** APB_SARADC_SAR_PATT_TAB1_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
-/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
- *  item 0 ~ 3 for pattern table 1 (each item one byte)
- */
-#define APB_SARADC_SARADC_SAR_PATT_TAB1    0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB1_M  (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
-#define APB_SARADC_SARADC_SAR_PATT_TAB1_V  0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB1_S  0
-
-/** APB_SARADC_SAR_PATT_TAB2_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
-/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
- *  Item 4 ~ 7 for pattern table 1 (each item one byte)
- */
-#define APB_SARADC_SARADC_SAR_PATT_TAB2    0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB2_M  (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
-#define APB_SARADC_SARADC_SAR_PATT_TAB2_V  0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB2_S  0
-
-/** APB_SARADC_ONETIME_SAMPLE_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
-/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
- *  configure onetime atten
- */
-#define APB_SARADC_SARADC_ONETIME_ATTEN    0x00000003U
-#define APB_SARADC_SARADC_ONETIME_ATTEN_M  (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
-#define APB_SARADC_SARADC_ONETIME_ATTEN_V  0x00000003U
-#define APB_SARADC_SARADC_ONETIME_ATTEN_S  23
-/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
- *  configure onetime channel
- */
-#define APB_SARADC_SARADC_ONETIME_CHANNEL    0x0000000FU
-#define APB_SARADC_SARADC_ONETIME_CHANNEL_M  (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
-#define APB_SARADC_SARADC_ONETIME_CHANNEL_V  0x0000000FU
-#define APB_SARADC_SARADC_ONETIME_CHANNEL_S  25
-/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
- *  trigger adc onetime sample
- */
-#define APB_SARADC_SARADC_ONETIME_START    (BIT(29))
-#define APB_SARADC_SARADC_ONETIME_START_M  (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
-#define APB_SARADC_SARADC_ONETIME_START_V  0x00000001U
-#define APB_SARADC_SARADC_ONETIME_START_S  29
-/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
- *  enable adc2 onetime sample
- */
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE    (BIT(30))
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M  (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V  0x00000001U
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S  30
-/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
- *  enable adc1 onetime sample
- */
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE    (BIT(31))
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M  (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V  0x00000001U
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S  31
-
-/** APB_SARADC_ARB_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
-/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
- *  adc2 arbiter force to enableapb controller
- */
-#define APB_SARADC_ADC_ARB_APB_FORCE    (BIT(2))
-#define APB_SARADC_ADC_ARB_APB_FORCE_M  (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
-#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
-/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
- *  adc2 arbiter force to enable rtc controller
- */
-#define APB_SARADC_ADC_ARB_RTC_FORCE    (BIT(3))
-#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
-#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
-/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
- *  adc2 arbiter force to enable wifi controller
- */
-#define APB_SARADC_ADC_ARB_WIFI_FORCE    (BIT(4))
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
-/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
- *  adc2 arbiter force grant
- */
-#define APB_SARADC_ADC_ARB_GRANT_FORCE    (BIT(5))
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
-/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
- *  Set adc2 arbiterapb priority
- */
-#define APB_SARADC_ADC_ARB_APB_PRIORITY    0x00000003U
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x00000003U
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
-/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
- *  Set adc2 arbiter rtc priority
- */
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY    0x00000003U
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x00000003U
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
-/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
- *  Set adc2 arbiter wifi priority
- */
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY    0x00000003U
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x00000003U
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
-/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
- *  adc2 arbiter uses fixed priority
- */
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY    (BIT(12))
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x00000001U
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
-
-/** APB_SARADC_FILTER_CTRL0_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
-/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
- *  configure filter1 to adc channel
- */
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1    0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M  (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S  18
-/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
- *  configure filter0 to adc channel
- */
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0    0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M  (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S  22
-/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
- *  enable apb_adc1_filter
- */
-#define APB_SARADC_APB_SARADC_FILTER_RESET    (BIT(31))
-#define APB_SARADC_APB_SARADC_FILTER_RESET_M  (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
-#define APB_SARADC_APB_SARADC_FILTER_RESET_V  0x00000001U
-#define APB_SARADC_APB_SARADC_FILTER_RESET_S  31
-
-/** APB_SARADC_SAR1DATA_STATUS_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
-/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
- *  saradc1 data
- */
-#define APB_SARADC_APB_SARADC1_DATA    0x0001FFFFU
-#define APB_SARADC_APB_SARADC1_DATA_M  (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
-#define APB_SARADC_APB_SARADC1_DATA_V  0x0001FFFFU
-#define APB_SARADC_APB_SARADC1_DATA_S  0
-
-/** APB_SARADC_SAR2DATA_STATUS_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
-/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
- *  saradc2 data
- */
-#define APB_SARADC_APB_SARADC2_DATA    0x0001FFFFU
-#define APB_SARADC_APB_SARADC2_DATA_M  (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
-#define APB_SARADC_APB_SARADC2_DATA_V  0x0001FFFFU
-#define APB_SARADC_APB_SARADC2_DATA_S  0
-
-/** APB_SARADC_THRES0_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
-/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
- *  configure thres0 to adc channel
- */
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL    0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M  (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S  0
-/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
- *  saradc thres0 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_S  5
-/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
- *  saradc thres0 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_LOW_M  (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_LOW_S  18
-
-/** APB_SARADC_THRES1_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
-/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
- *  configure thres1 to adc channel
- */
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL    0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M  (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S  0
-/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
- *  saradc thres1 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_S  5
-/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
- *  saradc thres1 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_LOW_M  (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_LOW_S  18
-
-/** APB_SARADC_THRES_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
-/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
- *  enable thres to all channel
- */
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M  (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S  27
-/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
- *  enable thres1
- */
-#define APB_SARADC_APB_SARADC_THRES1_EN    (BIT(30))
-#define APB_SARADC_APB_SARADC_THRES1_EN_M  (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
-#define APB_SARADC_APB_SARADC_THRES1_EN_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_EN_S  30
-/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
- *  enable thres0
- */
-#define APB_SARADC_APB_SARADC_THRES0_EN    (BIT(31))
-#define APB_SARADC_APB_SARADC_THRES0_EN_M  (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
-#define APB_SARADC_APB_SARADC_THRES0_EN_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_EN_S  31
-
-/** APB_SARADC_INT_ENA_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
-/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  tsens low  interrupt enable
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M  (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  saradc2 done interrupt enable
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M  (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  saradc1 done interrupt enable
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M  (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S  31
-
-/** APB_SARADC_INT_RAW_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
-/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  saradc tsens  interrupt raw
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M  (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  saradc2 done interrupt raw
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M  (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  saradc1 done interrupt raw
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M  (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S  31
-
-/** APB_SARADC_INT_ST_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
-/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
- *  saradc tsens  interrupt state
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M  (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
- *  saradc2 done interrupt state
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M  (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
- *  saradc1 done interrupt state
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M  (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S  31
-
-/** APB_SARADC_INT_CLR_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
-/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
- *  saradc tsens  interrupt clear
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M  (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
- *  saradc2 done interrupt clear
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M  (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
- *  saradc1 done interrupt clear
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M  (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S  31
-
-/** APB_SARADC_DMA_CONF_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
-/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
- *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
- */
-#define APB_SARADC_APB_ADC_EOF_NUM    0x0000FFFFU
-#define APB_SARADC_APB_ADC_EOF_NUM_M  (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
-#define APB_SARADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
-#define APB_SARADC_APB_ADC_EOF_NUM_S  0
-/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
- *  reset_apb_adc_state
- */
-#define APB_SARADC_APB_ADC_RESET_FSM    (BIT(30))
-#define APB_SARADC_APB_ADC_RESET_FSM_M  (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
-#define APB_SARADC_APB_ADC_RESET_FSM_V  0x00000001U
-#define APB_SARADC_APB_ADC_RESET_FSM_S  30
-/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
- *  enable apb_adc use spi_dma
- */
-#define APB_SARADC_APB_ADC_TRANS    (BIT(31))
-#define APB_SARADC_APB_ADC_TRANS_M  (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
-#define APB_SARADC_APB_ADC_TRANS_V  0x00000001U
-#define APB_SARADC_APB_ADC_TRANS_S  31
-
-/** APB_SARADC_CLKM_CONF_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
-/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
- *  Integral I2S clock divider value
- */
-#define APB_SARADC_CLKM_DIV_NUM    0x000000FFU
-#define APB_SARADC_CLKM_DIV_NUM_M  (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
-#define APB_SARADC_CLKM_DIV_NUM_V  0x000000FFU
-#define APB_SARADC_CLKM_DIV_NUM_S  0
-/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
- *  Fractional clock divider numerator value
- */
-#define APB_SARADC_CLKM_DIV_B    0x0000003FU
-#define APB_SARADC_CLKM_DIV_B_M  (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
-#define APB_SARADC_CLKM_DIV_B_V  0x0000003FU
-#define APB_SARADC_CLKM_DIV_B_S  8
-/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
- *  Fractional clock divider denominator value
- */
-#define APB_SARADC_CLKM_DIV_A    0x0000003FU
-#define APB_SARADC_CLKM_DIV_A_M  (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
-#define APB_SARADC_CLKM_DIV_A_V  0x0000003FU
-#define APB_SARADC_CLKM_DIV_A_S  14
-/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
- *  reg clk en
- */
-#define APB_SARADC_CLK_EN    (BIT(20))
-#define APB_SARADC_CLK_EN_M  (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
-#define APB_SARADC_CLK_EN_V  0x00000001U
-#define APB_SARADC_CLK_EN_S  20
-/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
- *  Set this bit to enable clk_apll
- */
-#define APB_SARADC_CLK_SEL    0x00000003U
-#define APB_SARADC_CLK_SEL_M  (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
-#define APB_SARADC_CLK_SEL_V  0x00000003U
-#define APB_SARADC_CLK_SEL_S  21
-
-/** APB_SARADC_APB_TSENS_CTRL_REG register
- *  digital tsens configure register
- */
-#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
-/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
- *  temperature sensor data out
- */
-#define APB_SARADC_TSENS_OUT    0x000000FFU
-#define APB_SARADC_TSENS_OUT_M  (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
-#define APB_SARADC_TSENS_OUT_V  0x000000FFU
-#define APB_SARADC_TSENS_OUT_S  0
-/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
- *  invert temperature sensor data
- */
-#define APB_SARADC_TSENS_IN_INV    (BIT(13))
-#define APB_SARADC_TSENS_IN_INV_M  (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
-#define APB_SARADC_TSENS_IN_INV_V  0x00000001U
-#define APB_SARADC_TSENS_IN_INV_S  13
-/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
- *  temperature sensor clock divider
- */
-#define APB_SARADC_TSENS_CLK_DIV    0x000000FFU
-#define APB_SARADC_TSENS_CLK_DIV_M  (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
-#define APB_SARADC_TSENS_CLK_DIV_V  0x000000FFU
-#define APB_SARADC_TSENS_CLK_DIV_S  14
-/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
- *  temperature sensor power up
- */
-#define APB_SARADC_TSENS_PU    (BIT(22))
-#define APB_SARADC_TSENS_PU_M  (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
-#define APB_SARADC_TSENS_PU_V  0x00000001U
-#define APB_SARADC_TSENS_PU_S  22
-
-/** APB_SARADC_TSENS_CTRL2_REG register
- *  digital tsens configure register
- */
-#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
-/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2;
- *  the time that power up tsens need wait
- */
-#define APB_SARADC_TSENS_XPD_WAIT    0x00000FFFU
-#define APB_SARADC_TSENS_XPD_WAIT_M  (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S)
-#define APB_SARADC_TSENS_XPD_WAIT_V  0x00000FFFU
-#define APB_SARADC_TSENS_XPD_WAIT_S  0
-/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0;
- *  force power up tsens
- */
-#define APB_SARADC_TSENS_XPD_FORCE    0x00000003U
-#define APB_SARADC_TSENS_XPD_FORCE_M  (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S)
-#define APB_SARADC_TSENS_XPD_FORCE_V  0x00000003U
-#define APB_SARADC_TSENS_XPD_FORCE_S  12
-/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1;
- *  inv tsens clk
- */
-#define APB_SARADC_TSENS_CLK_INV    (BIT(14))
-#define APB_SARADC_TSENS_CLK_INV_M  (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S)
-#define APB_SARADC_TSENS_CLK_INV_V  0x00000001U
-#define APB_SARADC_TSENS_CLK_INV_S  14
-/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
- *  tsens clk select
- */
-#define APB_SARADC_TSENS_CLK_SEL    (BIT(15))
-#define APB_SARADC_TSENS_CLK_SEL_M  (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
-#define APB_SARADC_TSENS_CLK_SEL_V  0x00000001U
-#define APB_SARADC_TSENS_CLK_SEL_S  15
-
-/** APB_SARADC_CALI_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
-/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
- *  saradc cali factor
- */
-#define APB_SARADC_APB_SARADC_CALI_CFG    0x0001FFFFU
-#define APB_SARADC_APB_SARADC_CALI_CFG_M  (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
-#define APB_SARADC_APB_SARADC_CALI_CFG_V  0x0001FFFFU
-#define APB_SARADC_APB_SARADC_CALI_CFG_S  0
-
-/** APB_TSENS_WAKE_REG register
- *  digital tsens configure register
- */
-#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
-/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
- *  reg_wakeup_th_low
- */
-#define APB_SARADC_WAKEUP_TH_LOW    0x000000FFU
-#define APB_SARADC_WAKEUP_TH_LOW_M  (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
-#define APB_SARADC_WAKEUP_TH_LOW_V  0x000000FFU
-#define APB_SARADC_WAKEUP_TH_LOW_S  0
-/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
- *  reg_wakeup_th_high
- */
-#define APB_SARADC_WAKEUP_TH_HIGH    0x000000FFU
-#define APB_SARADC_WAKEUP_TH_HIGH_M  (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
-#define APB_SARADC_WAKEUP_TH_HIGH_V  0x000000FFU
-#define APB_SARADC_WAKEUP_TH_HIGH_S  8
-/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
- *  reg_wakeup_over_upper_th
- */
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH    (BIT(16))
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M  (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V  0x00000001U
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S  16
-/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
- *  reg_wakeup_mode
- */
-#define APB_SARADC_WAKEUP_MODE    (BIT(17))
-#define APB_SARADC_WAKEUP_MODE_M  (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
-#define APB_SARADC_WAKEUP_MODE_V  0x00000001U
-#define APB_SARADC_WAKEUP_MODE_S  17
-/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
- *  reg_wakeup_en
- */
-#define APB_SARADC_WAKEUP_EN    (BIT(18))
-#define APB_SARADC_WAKEUP_EN_M  (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
-#define APB_SARADC_WAKEUP_EN_V  0x00000001U
-#define APB_SARADC_WAKEUP_EN_S  18
-
-/** APB_TSENS_SAMPLE_REG register
- *  digital tsens configure register
- */
-#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
-/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
- *  HW sample rate
- */
-#define APB_SARADC_TSENS_SAMPLE_RATE    0x0000FFFFU
-#define APB_SARADC_TSENS_SAMPLE_RATE_M  (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
-#define APB_SARADC_TSENS_SAMPLE_RATE_V  0x0000FFFFU
-#define APB_SARADC_TSENS_SAMPLE_RATE_S  0
-/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
- *  HW sample en
- */
-#define APB_SARADC_TSENS_SAMPLE_EN    (BIT(16))
-#define APB_SARADC_TSENS_SAMPLE_EN_M  (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
-#define APB_SARADC_TSENS_SAMPLE_EN_V  0x00000001U
-#define APB_SARADC_TSENS_SAMPLE_EN_S  16
-
-/** APB_SARADC_CTRL_DATE_REG register
- *  version
- */
-#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
-/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
- *  version
- */
-#define APB_SARADC_DATE    0xFFFFFFFFU
-#define APB_SARADC_DATE_M  (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
-#define APB_SARADC_DATE_V  0xFFFFFFFFU
-#define APB_SARADC_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/apb_saradc_struct.h b/components/soc/esp32p4/include/soc/apb_saradc_struct.h
deleted file mode 100644
index b76d6cfb5b..0000000000
--- a/components/soc/esp32p4/include/soc/apb_saradc_struct.h
+++ /dev/null
@@ -1,757 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configure Register */
-/** Type of saradc_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
-         *  select software enable saradc sample
-         */
-        uint32_t saradc_saradc_start_force:1;
-        /** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
-         *  software enable saradc sample
-         */
-        uint32_t saradc_saradc_start:1;
-        uint32_t reserved_2:4;
-        /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
-         *  SAR clock gated
-         */
-        uint32_t saradc_saradc_sar_clk_gated:1;
-        /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
-         *  SAR clock divider
-         */
-        uint32_t saradc_saradc_sar_clk_div:8;
-        /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
-         *  0 ~ 15 means length 1 ~ 16
-         */
-        uint32_t saradc_saradc_sar_patt_len:3;
-        uint32_t reserved_18:5;
-        /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
-         *  clear the pointer of pattern table for DIG ADC1 CTRL
-         */
-        uint32_t saradc_saradc_sar_patt_p_clear:1;
-        uint32_t reserved_24:3;
-        /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
-         *  force option to xpd sar blocks
-         */
-        uint32_t saradc_saradc_xpd_sar_force:2;
-        /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
-         *  enable saradc2 power detect driven func.
-         */
-        uint32_t saradc_saradc2_pwdet_drv:1;
-        /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
-         *  wait arbit signal stable after sar_done
-         */
-        uint32_t saradc_saradc_wait_arb_cycle:2;
-    };
-    uint32_t val;
-} apb_saradc_ctrl_reg_t;
-
-/** Type of saradc_ctrl2 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
-         *  enable max meas num
-         */
-        uint32_t saradc_saradc_meas_num_limit:1;
-        /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
-         *  max conversion number
-         */
-        uint32_t saradc_saradc_max_meas_num:8;
-        /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
-         *  1: data to DIG ADC1 CTRL is inverted, otherwise not
-         */
-        uint32_t saradc_saradc_sar1_inv:1;
-        /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
-         *  1: data to DIG ADC2 CTRL is inverted, otherwise not
-         */
-        uint32_t saradc_saradc_sar2_inv:1;
-        uint32_t reserved_11:1;
-        /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
-         *  to set saradc timer target
-         */
-        uint32_t saradc_saradc_timer_target:12;
-        /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
-         *  to enable saradc timer trigger
-         */
-        uint32_t saradc_saradc_timer_en:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} apb_saradc_ctrl2_reg_t;
-
-/** Type of saradc_filter_ctrl1 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
-         *  Factor of saradc filter1
-         */
-        uint32_t saradc_apb_saradc_filter_factor1:3;
-        /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
-         *  Factor of saradc filter0
-         */
-        uint32_t saradc_apb_saradc_filter_factor0:3;
-    };
-    uint32_t val;
-} apb_saradc_filter_ctrl1_reg_t;
-
-/** Type of saradc_fsm_wait register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8;
-         *  saradc_xpd_wait
-         */
-        uint32_t saradc_saradc_xpd_wait:8;
-        /** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8;
-         *  saradc_rstb_wait
-         */
-        uint32_t saradc_saradc_rstb_wait:8;
-        /** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255;
-         *  saradc_standby_wait
-         */
-        uint32_t saradc_saradc_standby_wait:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} apb_saradc_fsm_wait_reg_t;
-
-/** Type of saradc_sar1_status register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912;
-         *  saradc1 status about data and channel
-         */
-        uint32_t saradc_saradc_sar1_status:32;
-    };
-    uint32_t val;
-} apb_saradc_sar1_status_reg_t;
-
-/** Type of saradc_sar2_status register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912;
-         *  saradc2 status about data and channel
-         */
-        uint32_t saradc_saradc_sar2_status:32;
-    };
-    uint32_t val;
-} apb_saradc_sar2_status_reg_t;
-
-/** Type of saradc_sar_patt_tab1 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
-         *  item 0 ~ 3 for pattern table 1 (each item one byte)
-         */
-        uint32_t saradc_saradc_sar_patt_tab1:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} apb_saradc_sar_patt_tab1_reg_t;
-
-/** Type of saradc_sar_patt_tab2 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
-         *  Item 4 ~ 7 for pattern table 1 (each item one byte)
-         */
-        uint32_t saradc_saradc_sar_patt_tab2:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} apb_saradc_sar_patt_tab2_reg_t;
-
-/** Type of saradc_onetime_sample register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:23;
-        /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
-         *  configure onetime atten
-         */
-        uint32_t saradc_saradc_onetime_atten:2;
-        /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
-         *  configure onetime channel
-         */
-        uint32_t saradc_saradc_onetime_channel:4;
-        /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
-         *  trigger adc onetime sample
-         */
-        uint32_t saradc_saradc_onetime_start:1;
-        /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
-         *  enable adc2 onetime sample
-         */
-        uint32_t saradc_saradc2_onetime_sample:1;
-        /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
-         *  enable adc1 onetime sample
-         */
-        uint32_t saradc_saradc1_onetime_sample:1;
-    };
-    uint32_t val;
-} apb_saradc_onetime_sample_reg_t;
-
-/** Type of saradc_arb_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
-         *  adc2 arbiter force to enableapb controller
-         */
-        uint32_t saradc_adc_arb_apb_force:1;
-        /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
-         *  adc2 arbiter force to enable rtc controller
-         */
-        uint32_t saradc_adc_arb_rtc_force:1;
-        /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
-         *  adc2 arbiter force to enable wifi controller
-         */
-        uint32_t saradc_adc_arb_wifi_force:1;
-        /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
-         *  adc2 arbiter force grant
-         */
-        uint32_t saradc_adc_arb_grant_force:1;
-        /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
-         *  Set adc2 arbiterapb priority
-         */
-        uint32_t saradc_adc_arb_apb_priority:2;
-        /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
-         *  Set adc2 arbiter rtc priority
-         */
-        uint32_t saradc_adc_arb_rtc_priority:2;
-        /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
-         *  Set adc2 arbiter wifi priority
-         */
-        uint32_t saradc_adc_arb_wifi_priority:2;
-        /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
-         *  adc2 arbiter uses fixed priority
-         */
-        uint32_t saradc_adc_arb_fix_priority:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} apb_saradc_arb_ctrl_reg_t;
-
-/** Type of saradc_filter_ctrl0 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:18;
-        /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
-         *  configure filter1 to adc channel
-         */
-        uint32_t saradc_apb_saradc_filter_channel1:4;
-        /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
-         *  configure filter0 to adc channel
-         */
-        uint32_t saradc_apb_saradc_filter_channel0:4;
-        uint32_t reserved_26:5;
-        /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
-         *  enable apb_adc1_filter
-         */
-        uint32_t saradc_apb_saradc_filter_reset:1;
-    };
-    uint32_t val;
-} apb_saradc_filter_ctrl0_reg_t;
-
-/** Type of saradc_sar1data_status register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
-         *  saradc1 data
-         */
-        uint32_t saradc_apb_saradc1_data:17;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_saradc_sar1data_status_reg_t;
-
-/** Type of saradc_sar2data_status register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
-         *  saradc2 data
-         */
-        uint32_t saradc_apb_saradc2_data:17;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_saradc_sar2data_status_reg_t;
-
-/** Type of saradc_thres0_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
-         *  configure thres0 to adc channel
-         */
-        uint32_t saradc_apb_saradc_thres0_channel:4;
-        uint32_t reserved_4:1;
-        /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
-         *  saradc thres0 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres0_high:13;
-        /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
-         *  saradc thres0 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres0_low:13;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} apb_saradc_thres0_ctrl_reg_t;
-
-/** Type of saradc_thres1_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
-         *  configure thres1 to adc channel
-         */
-        uint32_t saradc_apb_saradc_thres1_channel:4;
-        uint32_t reserved_4:1;
-        /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
-         *  saradc thres1 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres1_high:13;
-        /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
-         *  saradc thres1 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres1_low:13;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} apb_saradc_thres1_ctrl_reg_t;
-
-/** Type of saradc_thres_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
-         *  enable thres to all channel
-         */
-        uint32_t saradc_apb_saradc_thres_all_en:1;
-        uint32_t reserved_28:2;
-        /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
-         *  enable thres1
-         */
-        uint32_t saradc_apb_saradc_thres1_en:1;
-        /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
-         *  enable thres0
-         */
-        uint32_t saradc_apb_saradc_thres0_en:1;
-    };
-    uint32_t val;
-} apb_saradc_thres_ctrl_reg_t;
-
-/** Type of saradc_int_ena register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
-         *  tsens low  interrupt enable
-         */
-        uint32_t saradc_apb_saradc_tsens_int_ena:1;
-        /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
-        /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
-        /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
-        /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
-        /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt enable
-         */
-        uint32_t saradc_apb_saradc2_done_int_ena:1;
-        /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt enable
-         */
-        uint32_t saradc_apb_saradc1_done_int_ena:1;
-    };
-    uint32_t val;
-} apb_saradc_int_ena_reg_t;
-
-/** Type of saradc_int_raw register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  saradc tsens  interrupt raw
-         */
-        uint32_t saradc_apb_saradc_tsens_int_raw:1;
-        /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
-        /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
-        /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
-        /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
-        /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt raw
-         */
-        uint32_t saradc_apb_saradc2_done_int_raw:1;
-        /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt raw
-         */
-        uint32_t saradc_apb_saradc1_done_int_raw:1;
-    };
-    uint32_t val;
-} apb_saradc_int_raw_reg_t;
-
-/** Type of saradc_int_st register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
-         *  saradc tsens  interrupt state
-         */
-        uint32_t saradc_apb_saradc_tsens_int_st:1;
-        /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_st:1;
-        /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_st:1;
-        /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_st:1;
-        /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_st:1;
-        /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt state
-         */
-        uint32_t saradc_apb_saradc2_done_int_st:1;
-        /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt state
-         */
-        uint32_t saradc_apb_saradc1_done_int_st:1;
-    };
-    uint32_t val;
-} apb_saradc_int_st_reg_t;
-
-/** Type of saradc_int_clr register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
-         *  saradc tsens  interrupt clear
-         */
-        uint32_t saradc_apb_saradc_tsens_int_clr:1;
-        /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
-        /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
-        /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
-        /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
-        /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt clear
-         */
-        uint32_t saradc_apb_saradc2_done_int_clr:1;
-        /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt clear
-         */
-        uint32_t saradc_apb_saradc1_done_int_clr:1;
-    };
-    uint32_t val;
-} apb_saradc_int_clr_reg_t;
-
-/** Type of saradc_dma_conf register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
-         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
-         */
-        uint32_t saradc_apb_adc_eof_num:16;
-        uint32_t reserved_16:14;
-        /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
-         *  reset_apb_adc_state
-         */
-        uint32_t saradc_apb_adc_reset_fsm:1;
-        /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
-         *  enable apb_adc use spi_dma
-         */
-        uint32_t saradc_apb_adc_trans:1;
-    };
-    uint32_t val;
-} apb_saradc_dma_conf_reg_t;
-
-/** Type of saradc_clkm_conf register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
-         *  Integral I2S clock divider value
-         */
-        uint32_t saradc_clkm_div_num:8;
-        /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
-         *  Fractional clock divider numerator value
-         */
-        uint32_t saradc_clkm_div_b:6;
-        /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
-         *  Fractional clock divider denominator value
-         */
-        uint32_t saradc_clkm_div_a:6;
-        /** saradc_clk_en : R/W; bitpos: [20]; default: 0;
-         *  reg clk en
-         */
-        uint32_t saradc_clk_en:1;
-        /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
-         *  Set this bit to enable clk_apll
-         */
-        uint32_t saradc_clk_sel:2;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} apb_saradc_clkm_conf_reg_t;
-
-/** Type of saradc_apb_tsens_ctrl register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
-         *  temperature sensor data out
-         */
-        uint32_t saradc_tsens_out:8;
-        uint32_t reserved_8:5;
-        /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
-         *  invert temperature sensor data
-         */
-        uint32_t saradc_tsens_in_inv:1;
-        /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
-         *  temperature sensor clock divider
-         */
-        uint32_t saradc_tsens_clk_div:8;
-        /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
-         *  temperature sensor power up
-         */
-        uint32_t saradc_tsens_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} apb_saradc_apb_tsens_ctrl_reg_t;
-
-/** Type of saradc_tsens_ctrl2 register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        /** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2;
-         *  the time that power up tsens need wait
-         */
-        uint32_t saradc_tsens_xpd_wait:12;
-        /** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0;
-         *  force power up tsens
-         */
-        uint32_t saradc_tsens_xpd_force:2;
-        /** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1;
-         *  inv tsens clk
-         */
-        uint32_t saradc_tsens_clk_inv:1;
-        /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
-         *  tsens clk select
-         */
-        uint32_t saradc_tsens_clk_sel:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} apb_saradc_tsens_ctrl2_reg_t;
-
-/** Type of saradc_cali register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
-         *  saradc cali factor
-         */
-        uint32_t saradc_apb_saradc_cali_cfg:17;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_saradc_cali_reg_t;
-
-/** Type of tsens_wake register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
-         *  reg_wakeup_th_low
-         */
-        uint32_t saradc_wakeup_th_low:8;
-        /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
-         *  reg_wakeup_th_high
-         */
-        uint32_t saradc_wakeup_th_high:8;
-        /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
-         *  reg_wakeup_over_upper_th
-         */
-        uint32_t saradc_wakeup_over_upper_th:1;
-        /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
-         *  reg_wakeup_mode
-         */
-        uint32_t saradc_wakeup_mode:1;
-        /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
-         *  reg_wakeup_en
-         */
-        uint32_t saradc_wakeup_en:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} apb_tsens_wake_reg_t;
-
-/** Type of tsens_sample register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
-         *  HW sample rate
-         */
-        uint32_t saradc_tsens_sample_rate:16;
-        /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
-         *  HW sample en
-         */
-        uint32_t saradc_tsens_sample_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_tsens_sample_reg_t;
-
-/** Type of saradc_ctrl_date register
- *  version
- */
-typedef union {
-    struct {
-        /** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
-         *  version
-         */
-        uint32_t saradc_date:32;
-    };
-    uint32_t val;
-} apb_saradc_ctrl_date_reg_t;
-
-
-typedef struct apb_dev_t {
-    volatile apb_saradc_ctrl_reg_t saradc_ctrl;
-    volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
-    volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
-    volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait;
-    volatile apb_saradc_sar1_status_reg_t saradc_sar1_status;
-    volatile apb_saradc_sar2_status_reg_t saradc_sar2_status;
-    volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
-    volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
-    volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
-    volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
-    volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
-    volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
-    volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
-    volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
-    volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
-    volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
-    volatile apb_saradc_int_ena_reg_t saradc_int_ena;
-    volatile apb_saradc_int_raw_reg_t saradc_int_raw;
-    volatile apb_saradc_int_st_reg_t saradc_int_st;
-    volatile apb_saradc_int_clr_reg_t saradc_int_clr;
-    volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
-    volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
-    volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
-    volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
-    volatile apb_saradc_cali_reg_t saradc_cali;
-    volatile apb_tsens_wake_reg_t tsens_wake;
-    volatile apb_tsens_sample_reg_t tsens_sample;
-    uint32_t reserved_06c[228];
-    volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
-} apb_dev_t;
-
-extern apb_dev_t APB_SARADC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/clic_reg.h b/components/soc/esp32p4/include/soc/clic_reg.h
index 3c170302af..29853d2b5d 100644
--- a/components/soc/esp32p4/include/soc/clic_reg.h
+++ b/components/soc/esp32p4/include/soc/clic_reg.h
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#define _CLIC_REG_H_
-
+#pragma once
 
+#include <stdint.h>
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -106,5 +107,3 @@ extern "C" {
 #ifdef __cplusplus
 }
 #endif
-
-#endif /*_CLIC_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/clint_reg.h b/components/soc/esp32p4/include/soc/clint_reg.h
deleted file mode 100644
index 5ce015e17f..0000000000
--- a/components/soc/esp32p4/include/soc/clint_reg.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DR_REG_CLINT_M_BASE(i)    ( 0x20001800 + (i) * 0x100 )
-#define DR_REG_CLINT_U_BASE(i)    ( 0x20001C00 + (i) * 0x100 )
-
-/*CLINT MINT*/
-#define CLINT_MINT_SIP_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x0)
-/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_SIP    0xFFFFFFFF
-#define CLINT_CPU_MINT_SIP_M  ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S))
-#define CLINT_CPU_MINT_SIP_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_SIP_S  0
-
-#define CLINT_MINT_TIMECTL_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x4)
-/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define CLINT_MINT_SAMPLING_MODE    0x00000003
-#define CLINT_MINT_SAMPLING_MODE_M  ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
-#define CLINT_MINT_SAMPLING_MODE_V  0x3
-#define CLINT_MINT_SAMPLING_MODE_S  4
-/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_MINT_COUNTER_OVERFLOW  (BIT(3))
-#define CLINT_MINT_COUNTER_OVERFLOW_M  (BIT(3))
-#define CLINT_MINT_COUNTER_OVERFLOW_V  0x1
-#define CLINT_MINT_COUNTER_OVERFLOW_S  3
-/* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_MINT_TIMERINT_PENDING  (BIT(2))
-#define CLINT_MINT_TIMERINT_PENDING_M  (BIT(2))
-#define CLINT_MINT_TIMERINT_PENDING_V  0x1
-#define CLINT_MINT_TIMERINT_PENDING_S  2
-/* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_MINT_TIMERINT_EN  (BIT(1))
-#define CLINT_MINT_TIMERINT_EN_M  (BIT(1))
-#define CLINT_MINT_TIMERINT_EN_V  0x1
-#define CLINT_MINT_TIMERINT_EN_S  1
-/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_MINT_COUNTER_EN  (BIT(0))
-#define CLINT_MINT_COUNTER_EN_M  (BIT(0))
-#define CLINT_MINT_COUNTER_EN_V  0x1
-#define CLINT_MINT_COUNTER_EN_S  0
-
-#define CLINT_MINT_MTIME_L_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x8)
-/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIME_L    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_L_M  ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
-#define CLINT_CPU_MINT_MTIME_L_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_L_S  0
-
-#define CLINT_MINT_MTIME_H_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0xC)
-/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIME_H    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_H_M  ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
-#define CLINT_CPU_MINT_MTIME_H_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_H_S  0
-
-#define CLINT_MINT_MTIMECMP_L_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x10)
-/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIMECMP_L    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_L_M  ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
-#define CLINT_CPU_MINT_MTIMECMP_L_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_L_S  0
-
-#define CLINT_MINT_MTIMECMP_H_REG(i)          (DR_REG_CLINT_M_BASE(i) + 0x14)
-/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIMECMP_H    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_H_M  ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
-#define CLINT_CPU_MINT_MTIMECMP_H_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_H_S  0
-
-/*CLINT UINT*/
-#define CLINT_UINT_SIP_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x0)
-/* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define CLINT_CPU_UINT_SIP    0xFFFFFFFF
-#define CLINT_CPU_UINT_SIP_M  ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S))
-#define CLINT_CPU_UINT_SIP_V  0xFFFFFFFF
-#define CLINT_CPU_UINT_SIP_S  0
-
-#define CLINT_UINT_TIMECTL_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x4)
-/* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define CLINT_UINT_SAMPLING_MODE    0x00000003
-#define CLINT_UINT_SAMPLING_MODE_M  ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S))
-#define CLINT_UINT_SAMPLING_MODE_V  0x3
-#define CLINT_UINT_SAMPLING_MODE_S  4
-/* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_UINT_COUNTER_OVERFLOW  (BIT(3))
-#define CLINT_UINT_COUNTER_OVERFLOW_M  (BIT(3))
-#define CLINT_UINT_COUNTER_OVERFLOW_V  0x1
-#define CLINT_UINT_COUNTER_OVERFLOW_S  3
-/* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_UINT_TIMERINT_PENDING  (BIT(2))
-#define CLINT_UINT_TIMERINT_PENDING_M  (BIT(2))
-#define CLINT_UINT_TIMERINT_PENDING_V  0x1
-#define CLINT_UINT_TIMERINT_PENDING_S  2
-/* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_UINT_TIMERINT_EN  (BIT(1))
-#define CLINT_UINT_TIMERINT_EN_M  (BIT(1))
-#define CLINT_UINT_TIMERINT_EN_V  0x1
-#define CLINT_UINT_TIMERINT_EN_S  1
-/* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_UINT_COUNTER_EN  (BIT(0))
-#define CLINT_UINT_COUNTER_EN_M  (BIT(0))
-#define CLINT_UINT_COUNTER_EN_V  0x1
-#define CLINT_UINT_COUNTER_EN_S  0
-
-#define CLINT_UINT_UTIME_L_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x8)
-/* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_UINT_UTIME_L    0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIME_L_M  ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S))
-#define CLINT_CPU_UINT_UTIME_L_V  0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIME_L_S  0
-
-#define CLINT_UINT_UTIME_H_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0xC)
-/* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_UINT_UTIME_H    0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIME_H_M  ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S))
-#define CLINT_CPU_UINT_UTIME_H_V  0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIME_H_S  0
-
-#define CLINT_UINT_UTIMECMP_L_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x10)
-/* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_UINT_UTIMECMP_L    0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIMECMP_L_M  ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S))
-#define CLINT_CPU_UINT_UTIMECMP_L_V  0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIMECMP_L_S  0
-
-#define CLINT_UINT_UTIMECMP_H_REG(i)          (DR_REG_CLINT_U_BASE(i) + 0x14)
-/* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_UINT_UTIMECMP_H    0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIMECMP_H_M  ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S))
-#define CLINT_CPU_UINT_UTIMECMP_H_V  0xFFFFFFFF
-#define CLINT_CPU_UINT_UTIMECMP_H_S  0
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 6e421b6437..e6a690eb8b 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -10,7 +10,7 @@ extern "C" {
 #endif
 
 /*
- ************************* ESP32C6 Root Clock Source ****************************
+ ************************* ESP32P4 Root Clock Source ****************************
  * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
  *
  *    This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
@@ -126,6 +126,7 @@ typedef enum {
 
 //////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
 
+//TODO: IDF-7486
 /**
  * @brief Type of SYSTIMER clock source
  */
@@ -137,83 +138,19 @@ typedef enum {
 
 //////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of GPTimer
- *
- * The following code can be used to iterate all possible clocks:
- * @code{c}
- * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
- * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
- *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
- *     // Test GPTimer with the clock `clk`
- * }
- * @endcode
- */
-#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
 
-/**
- * @brief Type of GPTimer clock source
- */
-typedef enum {
-    GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
-    GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
-    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
-} soc_periph_gptimer_clk_src_t;
-
-/**
- * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
- */
-typedef enum {
-    TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,     /*!< Timer group clock source is PLL_F80M */
-    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,             /*!< Timer group clock source is XTAL */
-    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,      /*!< Timer group clock source default choice is PLL_F80M */
-} soc_periph_tg_clk_src_legacy_t;
 
 //////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of RMT
- */
-#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
 
-/**
- * @brief Type of RMT clock source
- */
-typedef enum {
-    RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
-    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
-    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
-} soc_periph_rmt_clk_src_t;
-
-/**
- * @brief Type of RMT clock source, reserved for the legacy RMT driver
- */
-typedef enum {
-    RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
-    RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,         /*!< RMT source clock is XTAL */
-    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< RMT source clock default choice is PLL_F80M */
-} soc_periph_rmt_clk_src_legacy_t;
 
 //////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of Temperature Sensor
- */
-#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
 
-/**
- * @brief Type of Temp Sensor clock source
- */
-typedef enum {
-    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
-} soc_periph_temperature_sensor_clk_src_t;
 
 ///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
 
+//TODO: IDF-6511
 /**
  * @brief Type of UART clock source, reserved for the legacy UART driver
  */
@@ -226,69 +163,19 @@ typedef enum {
 
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of MCPWM Timer
- */
-#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
 
-/**
- * @brief Type of MCPWM timer clock source
- */
-typedef enum {
-    MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
-    MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
-} soc_periph_mcpwm_timer_clk_src_t;
 
-/**
- * @brief Array initializer for all supported clock sources of MCPWM Capture Timer
- */
-#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
+///////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
 
-/**
- * @brief Type of MCPWM capture clock source
- */
-typedef enum {
-    MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
-    MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
-} soc_periph_mcpwm_capture_clk_src_t;
 
-///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of I2S
- */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief I2S clock source enum
- */
-typedef enum {
-    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
-    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
-    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
-} soc_periph_i2s_clk_src_t;
 
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of I2C
- */
-#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief Type of I2C clock source.
- */
-typedef enum {
-    I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
-    I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,                  /*!< Select RC_FAST as the source clock */
-    I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,                     /*!< Select XTAL as the default source clock */
-} soc_periph_i2c_clk_src_t;
 
 
 /////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
 
+//TODO: IDF-7502
 /**
  * @brief Array initializer for all supported clock sources of SPI
  */
@@ -306,71 +193,19 @@ typedef enum {
 
 //////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of SDM
- */
-#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Sigma Delta Modulator clock source
- */
-typedef enum {
-    SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
-    SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
-    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
-} soc_periph_sdm_clk_src_t;
 
 //////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of Glitch Filter
- */
-#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Glitch filter clock source
- */
-
-typedef enum {
-    GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
-    GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
-    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
-} soc_periph_glitch_filter_clk_src_t;
 
 //////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of TWAI
- */
-#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL}
-
-/**
- * @brief TWAI clock source
- */
-typedef enum {
-    TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the source clock */
-    TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
-} soc_periph_twai_clk_src_t;
 
 //////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of ADC digital controller
- */
-#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief ADC digital controller clock source
- */
-typedef enum {
-    ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-    ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,   /*!< Select PLL_F80M as the source clock */
-    ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
-    ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M as the default clock choice */
-} soc_periph_adc_digi_clk_src_t;
 
 //////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
 
+//TODO: IDF-6516
 /**
  * @brief Array initializer for all supported clock sources of MWDT
  */
@@ -388,38 +223,9 @@ typedef enum {
 
 //////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of LEDC
- */
-#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief Type of LEDC clock source, reserved for the legacy LEDC driver
- */
-typedef enum {
-    LEDC_AUTO_CLK = 0,                              /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
-    LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M clock as the source clock */
-    LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
-    LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-
-    LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
-} soc_periph_ledc_clk_src_legacy_t;
 
 //////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
 
-/**
- * @brief Array initializer for all supported clock sources of PARLIO
- */
-#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
-
-/**
- * @brief PARLIO clock source
- */
-typedef enum {
-    PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-    PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
-    PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M,   /*!< Select PLL_F240M as the default clock choice */
-} soc_periph_parlio_clk_src_t;
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h
index 035248b78d..d3ba233faa 100644
--- a/components/soc/esp32p4/include/soc/clkout_channel.h
+++ b/components/soc/esp32p4/include/soc/clkout_channel.h
@@ -5,4 +5,5 @@
  */
 #pragma once
 
-// ESP32C6 CLKOUT signals has no corresponding iomux pins
+//Copied from C6, please check. TODO: IDF-7526
+// ESP32P4 CLKOUT signals has no corresponding iomux pins
diff --git a/components/soc/esp32p4/include/soc/core0_interrupt_reg.h b/components/soc/esp32p4/include/soc/core0_interrupt_reg.h
deleted file mode 100644
index a71a12b423..0000000000
--- a/components/soc/esp32p4/include/soc/core0_interrupt_reg.h
+++ /dev/null
@@ -1,1624 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** CORE0_LP_RTC_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_RTC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x0)
-/** CORE0_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_RTC_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_RTC_INT_MAP_M  (CORE0_CORE0_LP_RTC_INT_MAP_V << CORE0_CORE0_LP_RTC_INT_MAP_S)
-#define CORE0_CORE0_LP_RTC_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_RTC_INT_MAP_S  0
-
-/** CORE0_LP_WDT_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x4)
-/** CORE0_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_WDT_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_WDT_INT_MAP_M  (CORE0_CORE0_LP_WDT_INT_MAP_V << CORE0_CORE0_LP_WDT_INT_MAP_S)
-#define CORE0_CORE0_LP_WDT_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_WDT_INT_MAP_S  0
-
-/** CORE0_LP_TIMER_REG_0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x8)
-/** CORE0_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_M  (CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S)
-#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S  0
-
-/** CORE0_LP_TIMER_REG_1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc)
-/** CORE0_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_M  (CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S)
-#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S  0
-
-/** CORE0_MB_HP_INT_MAP_REG register
- *  NA
- */
-#define CORE0_MB_HP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x10)
-/** CORE0_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_MB_HP_INT_MAP    0x0000003FU
-#define CORE0_CORE0_MB_HP_INT_MAP_M  (CORE0_CORE0_MB_HP_INT_MAP_V << CORE0_CORE0_MB_HP_INT_MAP_S)
-#define CORE0_CORE0_MB_HP_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_MB_HP_INT_MAP_S  0
-
-/** CORE0_MB_LP_INT_MAP_REG register
- *  NA
- */
-#define CORE0_MB_LP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x14)
-/** CORE0_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_MB_LP_INT_MAP    0x0000003FU
-#define CORE0_CORE0_MB_LP_INT_MAP_M  (CORE0_CORE0_MB_LP_INT_MAP_V << CORE0_CORE0_MB_LP_INT_MAP_S)
-#define CORE0_CORE0_MB_LP_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_MB_LP_INT_MAP_S  0
-
-/** CORE0_PMU_REG_0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x18)
-/** CORE0_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PMU_REG_0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PMU_REG_0_INT_MAP_M  (CORE0_CORE0_PMU_REG_0_INT_MAP_V << CORE0_CORE0_PMU_REG_0_INT_MAP_S)
-#define CORE0_CORE0_PMU_REG_0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PMU_REG_0_INT_MAP_S  0
-
-/** CORE0_PMU_REG_1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c)
-/** CORE0_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PMU_REG_1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PMU_REG_1_INT_MAP_M  (CORE0_CORE0_PMU_REG_1_INT_MAP_V << CORE0_CORE0_PMU_REG_1_INT_MAP_S)
-#define CORE0_CORE0_PMU_REG_1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PMU_REG_1_INT_MAP_S  0
-
-/** CORE0_LP_ANAPERI_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x20)
-/** CORE0_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_ANAPERI_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_ANAPERI_INT_MAP_M  (CORE0_CORE0_LP_ANAPERI_INT_MAP_V << CORE0_CORE0_LP_ANAPERI_INT_MAP_S)
-#define CORE0_CORE0_LP_ANAPERI_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_ANAPERI_INT_MAP_S  0
-
-/** CORE0_LP_ADC_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_ADC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x24)
-/** CORE0_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_ADC_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_ADC_INT_MAP_M  (CORE0_CORE0_LP_ADC_INT_MAP_V << CORE0_CORE0_LP_ADC_INT_MAP_S)
-#define CORE0_CORE0_LP_ADC_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_ADC_INT_MAP_S  0
-
-/** CORE0_LP_GPIO_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_GPIO_INT_MAP_REG (DR_REG_CORE0_BASE + 0x28)
-/** CORE0_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_GPIO_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_GPIO_INT_MAP_M  (CORE0_CORE0_LP_GPIO_INT_MAP_V << CORE0_CORE0_LP_GPIO_INT_MAP_S)
-#define CORE0_CORE0_LP_GPIO_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_GPIO_INT_MAP_S  0
-
-/** CORE0_LP_I2C_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_I2C_INT_MAP_REG (DR_REG_CORE0_BASE + 0x2c)
-/** CORE0_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_I2C_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_I2C_INT_MAP_M  (CORE0_CORE0_LP_I2C_INT_MAP_V << CORE0_CORE0_LP_I2C_INT_MAP_S)
-#define CORE0_CORE0_LP_I2C_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_I2C_INT_MAP_S  0
-
-/** CORE0_LP_I2S_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_I2S_INT_MAP_REG (DR_REG_CORE0_BASE + 0x30)
-/** CORE0_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_I2S_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_I2S_INT_MAP_M  (CORE0_CORE0_LP_I2S_INT_MAP_V << CORE0_CORE0_LP_I2S_INT_MAP_S)
-#define CORE0_CORE0_LP_I2S_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_I2S_INT_MAP_S  0
-
-/** CORE0_LP_SPI_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_SPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x34)
-/** CORE0_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_SPI_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_SPI_INT_MAP_M  (CORE0_CORE0_LP_SPI_INT_MAP_V << CORE0_CORE0_LP_SPI_INT_MAP_S)
-#define CORE0_CORE0_LP_SPI_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_SPI_INT_MAP_S  0
-
-/** CORE0_LP_TOUCH_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_CORE0_BASE + 0x38)
-/** CORE0_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_TOUCH_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_TOUCH_INT_MAP_M  (CORE0_CORE0_LP_TOUCH_INT_MAP_V << CORE0_CORE0_LP_TOUCH_INT_MAP_S)
-#define CORE0_CORE0_LP_TOUCH_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_TOUCH_INT_MAP_S  0
-
-/** CORE0_LP_TSENS_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_TSENS_INT_MAP_REG (DR_REG_CORE0_BASE + 0x3c)
-/** CORE0_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_TSENS_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_TSENS_INT_MAP_M  (CORE0_CORE0_LP_TSENS_INT_MAP_V << CORE0_CORE0_LP_TSENS_INT_MAP_S)
-#define CORE0_CORE0_LP_TSENS_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_TSENS_INT_MAP_S  0
-
-/** CORE0_LP_UART_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_UART_INT_MAP_REG (DR_REG_CORE0_BASE + 0x40)
-/** CORE0_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_UART_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_UART_INT_MAP_M  (CORE0_CORE0_LP_UART_INT_MAP_V << CORE0_CORE0_LP_UART_INT_MAP_S)
-#define CORE0_CORE0_LP_UART_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_UART_INT_MAP_S  0
-
-/** CORE0_LP_EFUSE_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x44)
-/** CORE0_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_EFUSE_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_EFUSE_INT_MAP_M  (CORE0_CORE0_LP_EFUSE_INT_MAP_V << CORE0_CORE0_LP_EFUSE_INT_MAP_S)
-#define CORE0_CORE0_LP_EFUSE_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_EFUSE_INT_MAP_S  0
-
-/** CORE0_LP_SW_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_SW_INT_MAP_REG (DR_REG_CORE0_BASE + 0x48)
-/** CORE0_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_SW_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_SW_INT_MAP_M  (CORE0_CORE0_LP_SW_INT_MAP_V << CORE0_CORE0_LP_SW_INT_MAP_S)
-#define CORE0_CORE0_LP_SW_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_SW_INT_MAP_S  0
-
-/** CORE0_LP_SYSREG_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x4c)
-/** CORE0_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_SYSREG_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_SYSREG_INT_MAP_M  (CORE0_CORE0_LP_SYSREG_INT_MAP_V << CORE0_CORE0_LP_SYSREG_INT_MAP_S)
-#define CORE0_CORE0_LP_SYSREG_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_SYSREG_INT_MAP_S  0
-
-/** CORE0_LP_HUK_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LP_HUK_INT_MAP_REG (DR_REG_CORE0_BASE + 0x50)
-/** CORE0_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LP_HUK_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LP_HUK_INT_MAP_M  (CORE0_CORE0_LP_HUK_INT_MAP_V << CORE0_CORE0_LP_HUK_INT_MAP_S)
-#define CORE0_CORE0_LP_HUK_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LP_HUK_INT_MAP_S  0
-
-/** CORE0_SYS_ICM_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SYS_ICM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x54)
-/** CORE0_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SYS_ICM_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SYS_ICM_INT_MAP_M  (CORE0_CORE0_SYS_ICM_INT_MAP_V << CORE0_CORE0_SYS_ICM_INT_MAP_S)
-#define CORE0_CORE0_SYS_ICM_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SYS_ICM_INT_MAP_S  0
-
-/** CORE0_USB_DEVICE_INT_MAP_REG register
- *  NA
- */
-#define CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x58)
-/** CORE0_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_USB_DEVICE_INT_MAP    0x0000003FU
-#define CORE0_CORE0_USB_DEVICE_INT_MAP_M  (CORE0_CORE0_USB_DEVICE_INT_MAP_V << CORE0_CORE0_USB_DEVICE_INT_MAP_S)
-#define CORE0_CORE0_USB_DEVICE_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_USB_DEVICE_INT_MAP_S  0
-
-/** CORE0_SDIO_HOST_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_CORE0_BASE + 0x5c)
-/** CORE0_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SDIO_HOST_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SDIO_HOST_INT_MAP_M  (CORE0_CORE0_SDIO_HOST_INT_MAP_V << CORE0_CORE0_SDIO_HOST_INT_MAP_S)
-#define CORE0_CORE0_SDIO_HOST_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SDIO_HOST_INT_MAP_S  0
-
-/** CORE0_GDMA_INT_MAP_REG register
- *  NA
- */
-#define CORE0_GDMA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x60)
-/** CORE0_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_GDMA_INT_MAP    0x0000003FU
-#define CORE0_CORE0_GDMA_INT_MAP_M  (CORE0_CORE0_GDMA_INT_MAP_V << CORE0_CORE0_GDMA_INT_MAP_S)
-#define CORE0_CORE0_GDMA_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_GDMA_INT_MAP_S  0
-
-/** CORE0_SPI2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SPI2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x64)
-/** CORE0_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SPI2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SPI2_INT_MAP_M  (CORE0_CORE0_SPI2_INT_MAP_V << CORE0_CORE0_SPI2_INT_MAP_S)
-#define CORE0_CORE0_SPI2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SPI2_INT_MAP_S  0
-
-/** CORE0_SPI3_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SPI3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x68)
-/** CORE0_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SPI3_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SPI3_INT_MAP_M  (CORE0_CORE0_SPI3_INT_MAP_V << CORE0_CORE0_SPI3_INT_MAP_S)
-#define CORE0_CORE0_SPI3_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SPI3_INT_MAP_S  0
-
-/** CORE0_I2S0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_I2S0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x6c)
-/** CORE0_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_I2S0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_I2S0_INT_MAP_M  (CORE0_CORE0_I2S0_INT_MAP_V << CORE0_CORE0_I2S0_INT_MAP_S)
-#define CORE0_CORE0_I2S0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_I2S0_INT_MAP_S  0
-
-/** CORE0_I2S1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_I2S1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x70)
-/** CORE0_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_I2S1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_I2S1_INT_MAP_M  (CORE0_CORE0_I2S1_INT_MAP_V << CORE0_CORE0_I2S1_INT_MAP_S)
-#define CORE0_CORE0_I2S1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_I2S1_INT_MAP_S  0
-
-/** CORE0_I2S2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_I2S2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x74)
-/** CORE0_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_I2S2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_I2S2_INT_MAP_M  (CORE0_CORE0_I2S2_INT_MAP_V << CORE0_CORE0_I2S2_INT_MAP_S)
-#define CORE0_CORE0_I2S2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_I2S2_INT_MAP_S  0
-
-/** CORE0_UHCI0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_UHCI0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x78)
-/** CORE0_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_UHCI0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_UHCI0_INT_MAP_M  (CORE0_CORE0_UHCI0_INT_MAP_V << CORE0_CORE0_UHCI0_INT_MAP_S)
-#define CORE0_CORE0_UHCI0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_UHCI0_INT_MAP_S  0
-
-/** CORE0_UART0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_UART0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x7c)
-/** CORE0_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_UART0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_UART0_INT_MAP_M  (CORE0_CORE0_UART0_INT_MAP_V << CORE0_CORE0_UART0_INT_MAP_S)
-#define CORE0_CORE0_UART0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_UART0_INT_MAP_S  0
-
-/** CORE0_UART1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_UART1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x80)
-/** CORE0_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_UART1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_UART1_INT_MAP_M  (CORE0_CORE0_UART1_INT_MAP_V << CORE0_CORE0_UART1_INT_MAP_S)
-#define CORE0_CORE0_UART1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_UART1_INT_MAP_S  0
-
-/** CORE0_UART2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_UART2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x84)
-/** CORE0_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_UART2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_UART2_INT_MAP_M  (CORE0_CORE0_UART2_INT_MAP_V << CORE0_CORE0_UART2_INT_MAP_S)
-#define CORE0_CORE0_UART2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_UART2_INT_MAP_S  0
-
-/** CORE0_UART3_INT_MAP_REG register
- *  NA
- */
-#define CORE0_UART3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x88)
-/** CORE0_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_UART3_INT_MAP    0x0000003FU
-#define CORE0_CORE0_UART3_INT_MAP_M  (CORE0_CORE0_UART3_INT_MAP_V << CORE0_CORE0_UART3_INT_MAP_S)
-#define CORE0_CORE0_UART3_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_UART3_INT_MAP_S  0
-
-/** CORE0_UART4_INT_MAP_REG register
- *  NA
- */
-#define CORE0_UART4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x8c)
-/** CORE0_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_UART4_INT_MAP    0x0000003FU
-#define CORE0_CORE0_UART4_INT_MAP_M  (CORE0_CORE0_UART4_INT_MAP_V << CORE0_CORE0_UART4_INT_MAP_S)
-#define CORE0_CORE0_UART4_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_UART4_INT_MAP_S  0
-
-/** CORE0_LCD_CAM_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LCD_CAM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x90)
-/** CORE0_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LCD_CAM_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LCD_CAM_INT_MAP_M  (CORE0_CORE0_LCD_CAM_INT_MAP_V << CORE0_CORE0_LCD_CAM_INT_MAP_S)
-#define CORE0_CORE0_LCD_CAM_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LCD_CAM_INT_MAP_S  0
-
-/** CORE0_ADC_INT_MAP_REG register
- *  NA
- */
-#define CORE0_ADC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x94)
-/** CORE0_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_ADC_INT_MAP    0x0000003FU
-#define CORE0_CORE0_ADC_INT_MAP_M  (CORE0_CORE0_ADC_INT_MAP_V << CORE0_CORE0_ADC_INT_MAP_S)
-#define CORE0_CORE0_ADC_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_ADC_INT_MAP_S  0
-
-/** CORE0_PWM0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PWM0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x98)
-/** CORE0_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PWM0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PWM0_INT_MAP_M  (CORE0_CORE0_PWM0_INT_MAP_V << CORE0_CORE0_PWM0_INT_MAP_S)
-#define CORE0_CORE0_PWM0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PWM0_INT_MAP_S  0
-
-/** CORE0_PWM1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PWM1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x9c)
-/** CORE0_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PWM1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PWM1_INT_MAP_M  (CORE0_CORE0_PWM1_INT_MAP_V << CORE0_CORE0_PWM1_INT_MAP_S)
-#define CORE0_CORE0_PWM1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PWM1_INT_MAP_S  0
-
-/** CORE0_CAN0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CAN0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa0)
-/** CORE0_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CAN0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CAN0_INT_MAP_M  (CORE0_CORE0_CAN0_INT_MAP_V << CORE0_CORE0_CAN0_INT_MAP_S)
-#define CORE0_CORE0_CAN0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CAN0_INT_MAP_S  0
-
-/** CORE0_CAN1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CAN1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa4)
-/** CORE0_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CAN1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CAN1_INT_MAP_M  (CORE0_CORE0_CAN1_INT_MAP_V << CORE0_CORE0_CAN1_INT_MAP_S)
-#define CORE0_CORE0_CAN1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CAN1_INT_MAP_S  0
-
-/** CORE0_CAN2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CAN2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa8)
-/** CORE0_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CAN2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CAN2_INT_MAP_M  (CORE0_CORE0_CAN2_INT_MAP_V << CORE0_CORE0_CAN2_INT_MAP_S)
-#define CORE0_CORE0_CAN2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CAN2_INT_MAP_S  0
-
-/** CORE0_RMT_INT_MAP_REG register
- *  NA
- */
-#define CORE0_RMT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xac)
-/** CORE0_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_RMT_INT_MAP    0x0000003FU
-#define CORE0_CORE0_RMT_INT_MAP_M  (CORE0_CORE0_RMT_INT_MAP_V << CORE0_CORE0_RMT_INT_MAP_S)
-#define CORE0_CORE0_RMT_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_RMT_INT_MAP_S  0
-
-/** CORE0_I2C0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_I2C0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb0)
-/** CORE0_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_I2C0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_I2C0_INT_MAP_M  (CORE0_CORE0_I2C0_INT_MAP_V << CORE0_CORE0_I2C0_INT_MAP_S)
-#define CORE0_CORE0_I2C0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_I2C0_INT_MAP_S  0
-
-/** CORE0_I2C1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_I2C1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb4)
-/** CORE0_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_I2C1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_I2C1_INT_MAP_M  (CORE0_CORE0_I2C1_INT_MAP_V << CORE0_CORE0_I2C1_INT_MAP_S)
-#define CORE0_CORE0_I2C1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_I2C1_INT_MAP_S  0
-
-/** CORE0_TIMERGRP0_T0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb8)
-/** CORE0_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S)
-#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S  0
-
-/** CORE0_TIMERGRP0_T1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xbc)
-/** CORE0_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S)
-#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S  0
-
-/** CORE0_TIMERGRP0_WDT_INT_MAP_REG register
- *  NA
- */
-#define CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc0)
-/** CORE0_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP    0x0000003FU
-#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S)
-#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S  0
-
-/** CORE0_TIMERGRP1_T0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc4)
-/** CORE0_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S)
-#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S  0
-
-/** CORE0_TIMERGRP1_T1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc8)
-/** CORE0_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S)
-#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S  0
-
-/** CORE0_TIMERGRP1_WDT_INT_MAP_REG register
- *  NA
- */
-#define CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xcc)
-/** CORE0_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP    0x0000003FU
-#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S)
-#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S  0
-
-/** CORE0_LEDC_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LEDC_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd0)
-/** CORE0_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LEDC_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LEDC_INT_MAP_M  (CORE0_CORE0_LEDC_INT_MAP_V << CORE0_CORE0_LEDC_INT_MAP_S)
-#define CORE0_CORE0_LEDC_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LEDC_INT_MAP_S  0
-
-/** CORE0_SYSTIMER_TARGET0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd4)
-/** CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S)
-#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
-
-/** CORE0_SYSTIMER_TARGET1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd8)
-/** CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S)
-#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
-
-/** CORE0_SYSTIMER_TARGET2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xdc)
-/** CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S)
-#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
-
-/** CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe0)
-/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S)
-#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S  0
-
-/** CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe4)
-/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S)
-#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S  0
-
-/** CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe8)
-/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S)
-#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S  0
-
-/** CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xec)
-/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S)
-#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S  0
-
-/** CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf0)
-/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S)
-#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S  0
-
-/** CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf4)
-/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S)
-#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S  0
-
-/** CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf8)
-/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S)
-#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S  0
-
-/** CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xfc)
-/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S)
-#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S  0
-
-/** CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x100)
-/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S)
-#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S  0
-
-/** CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x104)
-/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S)
-#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S  0
-
-/** CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x108)
-/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S)
-#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S  0
-
-/** CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x10c)
-/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S)
-#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S  0
-
-/** CORE0_RSA_INT_MAP_REG register
- *  NA
- */
-#define CORE0_RSA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x110)
-/** CORE0_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_RSA_INT_MAP    0x0000003FU
-#define CORE0_CORE0_RSA_INT_MAP_M  (CORE0_CORE0_RSA_INT_MAP_V << CORE0_CORE0_RSA_INT_MAP_S)
-#define CORE0_CORE0_RSA_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_RSA_INT_MAP_S  0
-
-/** CORE0_AES_INT_MAP_REG register
- *  NA
- */
-#define CORE0_AES_INT_MAP_REG (DR_REG_CORE0_BASE + 0x114)
-/** CORE0_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_AES_INT_MAP    0x0000003FU
-#define CORE0_CORE0_AES_INT_MAP_M  (CORE0_CORE0_AES_INT_MAP_V << CORE0_CORE0_AES_INT_MAP_S)
-#define CORE0_CORE0_AES_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_AES_INT_MAP_S  0
-
-/** CORE0_SHA_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SHA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x118)
-/** CORE0_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SHA_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SHA_INT_MAP_M  (CORE0_CORE0_SHA_INT_MAP_V << CORE0_CORE0_SHA_INT_MAP_S)
-#define CORE0_CORE0_SHA_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SHA_INT_MAP_S  0
-
-/** CORE0_ECC_INT_MAP_REG register
- *  NA
- */
-#define CORE0_ECC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x11c)
-/** CORE0_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_ECC_INT_MAP    0x0000003FU
-#define CORE0_CORE0_ECC_INT_MAP_M  (CORE0_CORE0_ECC_INT_MAP_V << CORE0_CORE0_ECC_INT_MAP_S)
-#define CORE0_CORE0_ECC_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_ECC_INT_MAP_S  0
-
-/** CORE0_ECDSA_INT_MAP_REG register
- *  NA
- */
-#define CORE0_ECDSA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x120)
-/** CORE0_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_ECDSA_INT_MAP    0x0000003FU
-#define CORE0_CORE0_ECDSA_INT_MAP_M  (CORE0_CORE0_ECDSA_INT_MAP_V << CORE0_CORE0_ECDSA_INT_MAP_S)
-#define CORE0_CORE0_ECDSA_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_ECDSA_INT_MAP_S  0
-
-/** CORE0_KM_INT_MAP_REG register
- *  NA
- */
-#define CORE0_KM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x124)
-/** CORE0_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_KM_INT_MAP    0x0000003FU
-#define CORE0_CORE0_KM_INT_MAP_M  (CORE0_CORE0_KM_INT_MAP_V << CORE0_CORE0_KM_INT_MAP_S)
-#define CORE0_CORE0_KM_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_KM_INT_MAP_S  0
-
-/** CORE0_GPIO_INT0_MAP_REG register
- *  NA
- */
-#define CORE0_GPIO_INT0_MAP_REG (DR_REG_CORE0_BASE + 0x128)
-/** CORE0_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_GPIO_INT0_MAP    0x0000003FU
-#define CORE0_CORE0_GPIO_INT0_MAP_M  (CORE0_CORE0_GPIO_INT0_MAP_V << CORE0_CORE0_GPIO_INT0_MAP_S)
-#define CORE0_CORE0_GPIO_INT0_MAP_V  0x0000003FU
-#define CORE0_CORE0_GPIO_INT0_MAP_S  0
-
-/** CORE0_GPIO_INT1_MAP_REG register
- *  NA
- */
-#define CORE0_GPIO_INT1_MAP_REG (DR_REG_CORE0_BASE + 0x12c)
-/** CORE0_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_GPIO_INT1_MAP    0x0000003FU
-#define CORE0_CORE0_GPIO_INT1_MAP_M  (CORE0_CORE0_GPIO_INT1_MAP_V << CORE0_CORE0_GPIO_INT1_MAP_S)
-#define CORE0_CORE0_GPIO_INT1_MAP_V  0x0000003FU
-#define CORE0_CORE0_GPIO_INT1_MAP_S  0
-
-/** CORE0_GPIO_INT2_MAP_REG register
- *  NA
- */
-#define CORE0_GPIO_INT2_MAP_REG (DR_REG_CORE0_BASE + 0x130)
-/** CORE0_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_GPIO_INT2_MAP    0x0000003FU
-#define CORE0_CORE0_GPIO_INT2_MAP_M  (CORE0_CORE0_GPIO_INT2_MAP_V << CORE0_CORE0_GPIO_INT2_MAP_S)
-#define CORE0_CORE0_GPIO_INT2_MAP_V  0x0000003FU
-#define CORE0_CORE0_GPIO_INT2_MAP_S  0
-
-/** CORE0_GPIO_INT3_MAP_REG register
- *  NA
- */
-#define CORE0_GPIO_INT3_MAP_REG (DR_REG_CORE0_BASE + 0x134)
-/** CORE0_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_GPIO_INT3_MAP    0x0000003FU
-#define CORE0_CORE0_GPIO_INT3_MAP_M  (CORE0_CORE0_GPIO_INT3_MAP_V << CORE0_CORE0_GPIO_INT3_MAP_S)
-#define CORE0_CORE0_GPIO_INT3_MAP_V  0x0000003FU
-#define CORE0_CORE0_GPIO_INT3_MAP_S  0
-
-/** CORE0_GPIO_PAD_COMP_INT_MAP_REG register
- *  NA
- */
-#define CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x138)
-/** CORE0_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP    0x0000003FU
-#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_M  (CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S)
-#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S  0
-
-/** CORE0_CPU_INT_FROM_CPU_0_MAP_REG register
- *  NA
- */
-#define CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_CORE0_BASE + 0x13c)
-/** CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP    0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S)
-#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V  0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S  0
-
-/** CORE0_CPU_INT_FROM_CPU_1_MAP_REG register
- *  NA
- */
-#define CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_CORE0_BASE + 0x140)
-/** CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP    0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S)
-#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V  0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S  0
-
-/** CORE0_CPU_INT_FROM_CPU_2_MAP_REG register
- *  NA
- */
-#define CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_CORE0_BASE + 0x144)
-/** CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP    0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S)
-#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V  0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S  0
-
-/** CORE0_CPU_INT_FROM_CPU_3_MAP_REG register
- *  NA
- */
-#define CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_CORE0_BASE + 0x148)
-/** CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP    0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S)
-#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V  0x0000003FU
-#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S  0
-
-/** CORE0_CACHE_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CACHE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x14c)
-/** CORE0_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CACHE_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CACHE_INT_MAP_M  (CORE0_CORE0_CACHE_INT_MAP_V << CORE0_CORE0_CACHE_INT_MAP_S)
-#define CORE0_CORE0_CACHE_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CACHE_INT_MAP_S  0
-
-/** CORE0_FLASH_MSPI_INT_MAP_REG register
- *  NA
- */
-#define CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x150)
-/** CORE0_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_FLASH_MSPI_INT_MAP    0x0000003FU
-#define CORE0_CORE0_FLASH_MSPI_INT_MAP_M  (CORE0_CORE0_FLASH_MSPI_INT_MAP_V << CORE0_CORE0_FLASH_MSPI_INT_MAP_S)
-#define CORE0_CORE0_FLASH_MSPI_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_FLASH_MSPI_INT_MAP_S  0
-
-/** CORE0_CSI_BRIDGE_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x154)
-/** CORE0_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CSI_BRIDGE_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_M  (CORE0_CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CORE0_CSI_BRIDGE_INT_MAP_S)
-#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_S  0
-
-/** CORE0_DSI_BRIDGE_INT_MAP_REG register
- *  NA
- */
-#define CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x158)
-/** CORE0_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_DSI_BRIDGE_INT_MAP    0x0000003FU
-#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_M  (CORE0_CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_CORE0_DSI_BRIDGE_INT_MAP_S)
-#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_S  0
-
-/** CORE0_CSI_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CSI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x15c)
-/** CORE0_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CSI_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CSI_INT_MAP_M  (CORE0_CORE0_CSI_INT_MAP_V << CORE0_CORE0_CSI_INT_MAP_S)
-#define CORE0_CORE0_CSI_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CSI_INT_MAP_S  0
-
-/** CORE0_DSI_INT_MAP_REG register
- *  NA
- */
-#define CORE0_DSI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x160)
-/** CORE0_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_DSI_INT_MAP    0x0000003FU
-#define CORE0_CORE0_DSI_INT_MAP_M  (CORE0_CORE0_DSI_INT_MAP_V << CORE0_CORE0_DSI_INT_MAP_S)
-#define CORE0_CORE0_DSI_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_DSI_INT_MAP_S  0
-
-/** CORE0_GMII_PHY_INT_MAP_REG register
- *  NA
- */
-#define CORE0_GMII_PHY_INT_MAP_REG (DR_REG_CORE0_BASE + 0x164)
-/** CORE0_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_GMII_PHY_INT_MAP    0x0000003FU
-#define CORE0_CORE0_GMII_PHY_INT_MAP_M  (CORE0_CORE0_GMII_PHY_INT_MAP_V << CORE0_CORE0_GMII_PHY_INT_MAP_S)
-#define CORE0_CORE0_GMII_PHY_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_GMII_PHY_INT_MAP_S  0
-
-/** CORE0_LPI_INT_MAP_REG register
- *  NA
- */
-#define CORE0_LPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x168)
-/** CORE0_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_LPI_INT_MAP    0x0000003FU
-#define CORE0_CORE0_LPI_INT_MAP_M  (CORE0_CORE0_LPI_INT_MAP_V << CORE0_CORE0_LPI_INT_MAP_S)
-#define CORE0_CORE0_LPI_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_LPI_INT_MAP_S  0
-
-/** CORE0_PMT_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PMT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x16c)
-/** CORE0_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PMT_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PMT_INT_MAP_M  (CORE0_CORE0_PMT_INT_MAP_V << CORE0_CORE0_PMT_INT_MAP_S)
-#define CORE0_CORE0_PMT_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PMT_INT_MAP_S  0
-
-/** CORE0_SBD_INT_MAP_REG register
- *  NA
- */
-#define CORE0_SBD_INT_MAP_REG (DR_REG_CORE0_BASE + 0x170)
-/** CORE0_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_SBD_INT_MAP    0x0000003FU
-#define CORE0_CORE0_SBD_INT_MAP_M  (CORE0_CORE0_SBD_INT_MAP_V << CORE0_CORE0_SBD_INT_MAP_S)
-#define CORE0_CORE0_SBD_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_SBD_INT_MAP_S  0
-
-/** CORE0_USB_OTG_INT_MAP_REG register
- *  NA
- */
-#define CORE0_USB_OTG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x174)
-/** CORE0_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_USB_OTG_INT_MAP    0x0000003FU
-#define CORE0_CORE0_USB_OTG_INT_MAP_M  (CORE0_CORE0_USB_OTG_INT_MAP_V << CORE0_CORE0_USB_OTG_INT_MAP_S)
-#define CORE0_CORE0_USB_OTG_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_USB_OTG_INT_MAP_S  0
-
-/** CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register
- *  NA
- */
-#define CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x178)
-/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003FU
-#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)
-#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
-
-/** CORE0_JPEG_INT_MAP_REG register
- *  NA
- */
-#define CORE0_JPEG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x17c)
-/** CORE0_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_JPEG_INT_MAP    0x0000003FU
-#define CORE0_CORE0_JPEG_INT_MAP_M  (CORE0_CORE0_JPEG_INT_MAP_V << CORE0_CORE0_JPEG_INT_MAP_S)
-#define CORE0_CORE0_JPEG_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_JPEG_INT_MAP_S  0
-
-/** CORE0_PPA_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PPA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x180)
-/** CORE0_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PPA_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PPA_INT_MAP_M  (CORE0_CORE0_PPA_INT_MAP_V << CORE0_CORE0_PPA_INT_MAP_S)
-#define CORE0_CORE0_PPA_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PPA_INT_MAP_S  0
-
-/** CORE0_CORE0_TRACE_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CORE0_TRACE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x184)
-/** CORE0_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CORE0_TRACE_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CORE0_TRACE_INT_MAP_M  (CORE0_CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_CORE0_TRACE_INT_MAP_S)
-#define CORE0_CORE0_CORE0_TRACE_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CORE0_TRACE_INT_MAP_S  0
-
-/** CORE0_CORE1_TRACE_INT_MAP_REG register
- *  NA
- */
-#define CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x188)
-/** CORE0_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_CORE1_TRACE_INT_MAP    0x0000003FU
-#define CORE0_CORE0_CORE1_TRACE_INT_MAP_M  (CORE0_CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE0_CORE1_TRACE_INT_MAP_S)
-#define CORE0_CORE0_CORE1_TRACE_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_CORE1_TRACE_INT_MAP_S  0
-
-/** CORE0_HP_CORE_CTRL_INT_MAP_REG register
- *  NA
- */
-#define CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_CORE0_BASE + 0x18c)
-/** CORE0_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP    0x0000003FU
-#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_M  (CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S)
-#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S  0
-
-/** CORE0_ISP_INT_MAP_REG register
- *  NA
- */
-#define CORE0_ISP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x190)
-/** CORE0_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_ISP_INT_MAP    0x0000003FU
-#define CORE0_CORE0_ISP_INT_MAP_M  (CORE0_CORE0_ISP_INT_MAP_V << CORE0_CORE0_ISP_INT_MAP_S)
-#define CORE0_CORE0_ISP_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_ISP_INT_MAP_S  0
-
-/** CORE0_I3C_MST_INT_MAP_REG register
- *  NA
- */
-#define CORE0_I3C_MST_INT_MAP_REG (DR_REG_CORE0_BASE + 0x194)
-/** CORE0_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_I3C_MST_INT_MAP    0x0000003FU
-#define CORE0_CORE0_I3C_MST_INT_MAP_M  (CORE0_CORE0_I3C_MST_INT_MAP_V << CORE0_CORE0_I3C_MST_INT_MAP_S)
-#define CORE0_CORE0_I3C_MST_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_I3C_MST_INT_MAP_S  0
-
-/** CORE0_I3C_SLV_INT_MAP_REG register
- *  NA
- */
-#define CORE0_I3C_SLV_INT_MAP_REG (DR_REG_CORE0_BASE + 0x198)
-/** CORE0_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_I3C_SLV_INT_MAP    0x0000003FU
-#define CORE0_CORE0_I3C_SLV_INT_MAP_M  (CORE0_CORE0_I3C_SLV_INT_MAP_V << CORE0_CORE0_I3C_SLV_INT_MAP_S)
-#define CORE0_CORE0_I3C_SLV_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_I3C_SLV_INT_MAP_S  0
-
-/** CORE0_USB_OTG11_INT_MAP_REG register
- *  NA
- */
-#define CORE0_USB_OTG11_INT_MAP_REG (DR_REG_CORE0_BASE + 0x19c)
-/** CORE0_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_USB_OTG11_INT_MAP    0x0000003FU
-#define CORE0_CORE0_USB_OTG11_INT_MAP_M  (CORE0_CORE0_USB_OTG11_INT_MAP_V << CORE0_CORE0_USB_OTG11_INT_MAP_S)
-#define CORE0_CORE0_USB_OTG11_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_USB_OTG11_INT_MAP_S  0
-
-/** CORE0_DMA2D_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a0)
-/** CORE0_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S)
-#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S  0
-
-/** CORE0_DMA2D_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a4)
-/** CORE0_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S)
-#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S  0
-
-/** CORE0_DMA2D_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a8)
-/** CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S)
-#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S  0
-
-/** CORE0_DMA2D_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1ac)
-/** CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S)
-#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S  0
-
-/** CORE0_DMA2D_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b0)
-/** CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S)
-#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S  0
-
-/** CORE0_PSRAM_MSPI_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b4)
-/** CORE0_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PSRAM_MSPI_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_M  (CORE0_CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_CORE0_PSRAM_MSPI_INT_MAP_S)
-#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_S  0
-
-/** CORE0_HP_SYSREG_INT_MAP_REG register
- *  NA
- */
-#define CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b8)
-/** CORE0_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_HP_SYSREG_INT_MAP    0x0000003FU
-#define CORE0_CORE0_HP_SYSREG_INT_MAP_M  (CORE0_CORE0_HP_SYSREG_INT_MAP_V << CORE0_CORE0_HP_SYSREG_INT_MAP_S)
-#define CORE0_CORE0_HP_SYSREG_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_HP_SYSREG_INT_MAP_S  0
-
-/** CORE0_PCNT_INT_MAP_REG register
- *  NA
- */
-#define CORE0_PCNT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1bc)
-/** CORE0_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_PCNT_INT_MAP    0x0000003FU
-#define CORE0_CORE0_PCNT_INT_MAP_M  (CORE0_CORE0_PCNT_INT_MAP_V << CORE0_CORE0_PCNT_INT_MAP_S)
-#define CORE0_CORE0_PCNT_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_PCNT_INT_MAP_S  0
-
-/** CORE0_HP_PAU_INT_MAP_REG register
- *  NA
- */
-#define CORE0_HP_PAU_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c0)
-/** CORE0_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_HP_PAU_INT_MAP    0x0000003FU
-#define CORE0_CORE0_HP_PAU_INT_MAP_M  (CORE0_CORE0_HP_PAU_INT_MAP_V << CORE0_CORE0_HP_PAU_INT_MAP_S)
-#define CORE0_CORE0_HP_PAU_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_HP_PAU_INT_MAP_S  0
-
-/** CORE0_HP_PARLIO_RX_INT_MAP_REG register
- *  NA
- */
-#define CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c4)
-/** CORE0_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP    0x0000003FU
-#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_M  (CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S)
-#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S  0
-
-/** CORE0_HP_PARLIO_TX_INT_MAP_REG register
- *  NA
- */
-#define CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c8)
-/** CORE0_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP    0x0000003FU
-#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_M  (CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S)
-#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1cc)
-/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d0)
-/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d4)
-/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d8)
-/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1dc)
-/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e0)
-/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e4)
-/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e8)
-/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1ec)
-/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f0)
-/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S  0
-
-/** CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f4)
-/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S)
-#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S  0
-
-/** CORE0_H264_REG_INT_MAP_REG register
- *  NA
- */
-#define CORE0_H264_REG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f8)
-/** CORE0_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_H264_REG_INT_MAP    0x0000003FU
-#define CORE0_CORE0_H264_REG_INT_MAP_M  (CORE0_CORE0_H264_REG_INT_MAP_V << CORE0_CORE0_H264_REG_INT_MAP_S)
-#define CORE0_CORE0_H264_REG_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_H264_REG_INT_MAP_S  0
-
-/** CORE0_ASSIST_DEBUG_INT_MAP_REG register
- *  NA
- */
-#define CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1fc)
-/** CORE0_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP    0x0000003FU
-#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_M  (CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S)
-#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V  0x0000003FU
-#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S  0
-
-/** CORE0_INTR_STATUS_REG_0_REG register
- *  NA
- */
-#define CORE0_INTR_STATUS_REG_0_REG (DR_REG_CORE0_BASE + 0x200)
-/** CORE0_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_INTR_STATUS_0    0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_0_M  (CORE0_CORE0_INTR_STATUS_0_V << CORE0_CORE0_INTR_STATUS_0_S)
-#define CORE0_CORE0_INTR_STATUS_0_V  0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_0_S  0
-
-/** CORE0_INTR_STATUS_REG_1_REG register
- *  NA
- */
-#define CORE0_INTR_STATUS_REG_1_REG (DR_REG_CORE0_BASE + 0x204)
-/** CORE0_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_INTR_STATUS_1    0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_1_M  (CORE0_CORE0_INTR_STATUS_1_V << CORE0_CORE0_INTR_STATUS_1_S)
-#define CORE0_CORE0_INTR_STATUS_1_V  0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_1_S  0
-
-/** CORE0_INTR_STATUS_REG_2_REG register
- *  NA
- */
-#define CORE0_INTR_STATUS_REG_2_REG (DR_REG_CORE0_BASE + 0x208)
-/** CORE0_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_INTR_STATUS_2    0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_2_M  (CORE0_CORE0_INTR_STATUS_2_V << CORE0_CORE0_INTR_STATUS_2_S)
-#define CORE0_CORE0_INTR_STATUS_2_V  0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_2_S  0
-
-/** CORE0_INTR_STATUS_REG_3_REG register
- *  NA
- */
-#define CORE0_INTR_STATUS_REG_3_REG (DR_REG_CORE0_BASE + 0x20c)
-/** CORE0_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE0_CORE0_INTR_STATUS_3    0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_3_M  (CORE0_CORE0_INTR_STATUS_3_V << CORE0_CORE0_INTR_STATUS_3_S)
-#define CORE0_CORE0_INTR_STATUS_3_V  0xFFFFFFFFU
-#define CORE0_CORE0_INTR_STATUS_3_S  0
-
-/** CORE0_CLOCK_GATE_REG register
- *  NA
- */
-#define CORE0_CLOCK_GATE_REG (DR_REG_CORE0_BASE + 0x210)
-/** CORE0_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  NA
- */
-#define CORE0_CORE0_REG_CLK_EN    (BIT(0))
-#define CORE0_CORE0_REG_CLK_EN_M  (CORE0_CORE0_REG_CLK_EN_V << CORE0_CORE0_REG_CLK_EN_S)
-#define CORE0_CORE0_REG_CLK_EN_V  0x00000001U
-#define CORE0_CORE0_REG_CLK_EN_S  0
-
-/** CORE0_INTERRUPT_REG_DATE_REG register
- *  NA
- */
-#define CORE0_INTERRUPT_REG_DATE_REG (DR_REG_CORE0_BASE + 0x3fc)
-/** CORE0_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752;
- *  NA
- */
-#define CORE0_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
-#define CORE0_CORE0_INTERRUPT_REG_DATE_M  (CORE0_CORE0_INTERRUPT_REG_DATE_V << CORE0_CORE0_INTERRUPT_REG_DATE_S)
-#define CORE0_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
-#define CORE0_CORE0_INTERRUPT_REG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/core0_interrupt_struct.h b/components/soc/esp32p4/include/soc/core0_interrupt_struct.h
deleted file mode 100644
index 0fc7cf301c..0000000000
--- a/components/soc/esp32p4/include/soc/core0_interrupt_struct.h
+++ /dev/null
@@ -1,2298 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: CORE0 LP RTC INT MAP REG */
-/** Type of lp_rtc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_rtc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_rtc_int_map_reg_t;
-
-
-/** Group: CORE0 LP WDT INT MAP REG */
-/** Type of lp_wdt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_wdt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_wdt_int_map_reg_t;
-
-
-/** Group: CORE0 LP TIMER REG 0 INT MAP REG */
-/** Type of lp_timer_reg_0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_timer_reg_0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_timer_reg_0_int_map_reg_t;
-
-
-/** Group: CORE0 LP TIMER REG 1 INT MAP REG */
-/** Type of lp_timer_reg_1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_timer_reg_1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_timer_reg_1_int_map_reg_t;
-
-
-/** Group: CORE0 MB HP INT MAP REG */
-/** Type of mb_hp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_mb_hp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_mb_hp_int_map_reg_t;
-
-
-/** Group: CORE0 MB LP INT MAP REG */
-/** Type of mb_lp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_mb_lp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_mb_lp_int_map_reg_t;
-
-
-/** Group: CORE0 PMU REG 0 INT MAP REG */
-/** Type of pmu_reg_0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_pmu_reg_0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_pmu_reg_0_int_map_reg_t;
-
-
-/** Group: CORE0 PMU REG 1 INT MAP REG */
-/** Type of pmu_reg_1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_pmu_reg_1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_pmu_reg_1_int_map_reg_t;
-
-
-/** Group: CORE0 LP ANAPERI INT MAP REG */
-/** Type of lp_anaperi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_anaperi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_anaperi_int_map_reg_t;
-
-
-/** Group: CORE0 LP ADC INT MAP REG */
-/** Type of lp_adc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_adc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_adc_int_map_reg_t;
-
-
-/** Group: CORE0 LP GPIO INT MAP REG */
-/** Type of lp_gpio_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_gpio_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_gpio_int_map_reg_t;
-
-
-/** Group: CORE0 LP I2C INT MAP REG */
-/** Type of lp_i2c_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_i2c_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_i2c_int_map_reg_t;
-
-
-/** Group: CORE0 LP I2S INT MAP REG */
-/** Type of lp_i2s_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_i2s_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_i2s_int_map_reg_t;
-
-
-/** Group: CORE0 LP SPI INT MAP REG */
-/** Type of lp_spi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_spi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_spi_int_map_reg_t;
-
-
-/** Group: CORE0 LP TOUCH INT MAP REG */
-/** Type of lp_touch_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_touch_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_touch_int_map_reg_t;
-
-
-/** Group: CORE0 LP TSENS INT MAP REG */
-/** Type of lp_tsens_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_tsens_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_tsens_int_map_reg_t;
-
-
-/** Group: CORE0 LP UART INT MAP REG */
-/** Type of lp_uart_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_uart_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_uart_int_map_reg_t;
-
-
-/** Group: CORE0 LP EFUSE INT MAP REG */
-/** Type of lp_efuse_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_efuse_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_efuse_int_map_reg_t;
-
-
-/** Group: CORE0 LP SW INT MAP REG */
-/** Type of lp_sw_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_sw_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_sw_int_map_reg_t;
-
-
-/** Group: CORE0 LP SYSREG INT MAP REG */
-/** Type of lp_sysreg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_sysreg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_sysreg_int_map_reg_t;
-
-
-/** Group: CORE0 LP HUK INT MAP REG */
-/** Type of lp_huk_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lp_huk_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lp_huk_int_map_reg_t;
-
-
-/** Group: CORE0 SYS ICM INT MAP REG */
-/** Type of sys_icm_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_sys_icm_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_sys_icm_int_map_reg_t;
-
-
-/** Group: CORE0 USB DEVICE INT MAP REG */
-/** Type of usb_device_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_usb_device_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_usb_device_int_map_reg_t;
-
-
-/** Group: CORE0 SDIO HOST INT MAP REG */
-/** Type of sdio_host_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_sdio_host_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_sdio_host_int_map_reg_t;
-
-
-/** Group: CORE0 GDMA INT MAP REG */
-/** Type of gdma_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_gdma_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_gdma_int_map_reg_t;
-
-
-/** Group: CORE0 SPI2 INT MAP REG */
-/** Type of spi2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_spi2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_spi2_int_map_reg_t;
-
-
-/** Group: CORE0 SPI3 INT MAP REG */
-/** Type of spi3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_spi3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_spi3_int_map_reg_t;
-
-
-/** Group: CORE0 I2S0 INT MAP REG */
-/** Type of i2s0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_i2s0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_i2s0_int_map_reg_t;
-
-
-/** Group: CORE0 I2S1 INT MAP REG */
-/** Type of i2s1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_i2s1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_i2s1_int_map_reg_t;
-
-
-/** Group: CORE0 I2S2 INT MAP REG */
-/** Type of i2s2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_i2s2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_i2s2_int_map_reg_t;
-
-
-/** Group: CORE0 UHCI0 INT MAP REG */
-/** Type of uhci0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_uhci0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_uhci0_int_map_reg_t;
-
-
-/** Group: CORE0 UART0 INT MAP REG */
-/** Type of uart0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_uart0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_uart0_int_map_reg_t;
-
-
-/** Group: CORE0 UART1 INT MAP REG */
-/** Type of uart1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_uart1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_uart1_int_map_reg_t;
-
-
-/** Group: CORE0 UART2 INT MAP REG */
-/** Type of uart2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_uart2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_uart2_int_map_reg_t;
-
-
-/** Group: CORE0 UART3 INT MAP REG */
-/** Type of uart3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_uart3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_uart3_int_map_reg_t;
-
-
-/** Group: CORE0 UART4 INT MAP REG */
-/** Type of uart4_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_uart4_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_uart4_int_map_reg_t;
-
-
-/** Group: CORE0 LCD CAM INT MAP REG */
-/** Type of lcd_cam_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lcd_cam_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lcd_cam_int_map_reg_t;
-
-
-/** Group: CORE0 ADC INT MAP REG */
-/** Type of adc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_adc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_adc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_adc_int_map_reg_t;
-
-
-/** Group: CORE0 PWM0 INT MAP REG */
-/** Type of pwm0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_pwm0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_pwm0_int_map_reg_t;
-
-
-/** Group: CORE0 PWM1 INT MAP REG */
-/** Type of pwm1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_pwm1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_pwm1_int_map_reg_t;
-
-
-/** Group: CORE0 CAN0 INT MAP REG */
-/** Type of can0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_can0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_can0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_can0_int_map_reg_t;
-
-
-/** Group: CORE0 CAN1 INT MAP REG */
-/** Type of can1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_can1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_can1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_can1_int_map_reg_t;
-
-
-/** Group: CORE0 CAN2 INT MAP REG */
-/** Type of can2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_can2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_can2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_can2_int_map_reg_t;
-
-
-/** Group: CORE0 RMT INT MAP REG */
-/** Type of rmt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_rmt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_rmt_int_map_reg_t;
-
-
-/** Group: CORE0 I2C0 INT MAP REG */
-/** Type of i2c0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_i2c0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_i2c0_int_map_reg_t;
-
-
-/** Group: CORE0 I2C1 INT MAP REG */
-/** Type of i2c1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_i2c1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_i2c1_int_map_reg_t;
-
-
-/** Group: CORE0 TIMERGRP0 T0 INT MAP REG */
-/** Type of timergrp0_t0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_timergrp0_t0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_timergrp0_t0_int_map_reg_t;
-
-
-/** Group: CORE0 TIMERGRP0 T1 INT MAP REG */
-/** Type of timergrp0_t1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_timergrp0_t1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_timergrp0_t1_int_map_reg_t;
-
-
-/** Group: CORE0 TIMERGRP0 WDT INT MAP REG */
-/** Type of timergrp0_wdt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_timergrp0_wdt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_timergrp0_wdt_int_map_reg_t;
-
-
-/** Group: CORE0 TIMERGRP1 T0 INT MAP REG */
-/** Type of timergrp1_t0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_timergrp1_t0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_timergrp1_t0_int_map_reg_t;
-
-
-/** Group: CORE0 TIMERGRP1 T1 INT MAP REG */
-/** Type of timergrp1_t1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_timergrp1_t1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_timergrp1_t1_int_map_reg_t;
-
-
-/** Group: CORE0 TIMERGRP1 WDT INT MAP REG */
-/** Type of timergrp1_wdt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_timergrp1_wdt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_timergrp1_wdt_int_map_reg_t;
-
-
-/** Group: CORE0 LEDC INT MAP REG */
-/** Type of ledc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ledc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ledc_int_map_reg_t;
-
-
-/** Group: CORE0 SYSTIMER TARGET0 INT MAP REG */
-/** Type of systimer_target0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_systimer_target0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_systimer_target0_int_map_reg_t;
-
-
-/** Group: CORE0 SYSTIMER TARGET1 INT MAP REG */
-/** Type of systimer_target1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_systimer_target1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_systimer_target1_int_map_reg_t;
-
-
-/** Group: CORE0 SYSTIMER TARGET2 INT MAP REG */
-/** Type of systimer_target2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_systimer_target2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_systimer_target2_int_map_reg_t;
-
-
-/** Group: CORE0 AHB PDMA IN CH0 INT MAP REG */
-/** Type of ahb_pdma_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ahb_pdma_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ahb_pdma_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 AHB PDMA IN CH1 INT MAP REG */
-/** Type of ahb_pdma_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ahb_pdma_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ahb_pdma_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 AHB PDMA IN CH2 INT MAP REG */
-/** Type of ahb_pdma_in_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ahb_pdma_in_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ahb_pdma_in_ch2_int_map_reg_t;
-
-
-/** Group: CORE0 AHB PDMA OUT CH0 INT MAP REG */
-/** Type of ahb_pdma_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ahb_pdma_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ahb_pdma_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 AHB PDMA OUT CH1 INT MAP REG */
-/** Type of ahb_pdma_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ahb_pdma_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ahb_pdma_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 AHB PDMA OUT CH2 INT MAP REG */
-/** Type of ahb_pdma_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ahb_pdma_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ahb_pdma_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE0 AXI PDMA IN CH0 INT MAP REG */
-/** Type of axi_pdma_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_axi_pdma_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_axi_pdma_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 AXI PDMA IN CH1 INT MAP REG */
-/** Type of axi_pdma_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_axi_pdma_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_axi_pdma_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 AXI PDMA IN CH2 INT MAP REG */
-/** Type of axi_pdma_in_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_axi_pdma_in_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_axi_pdma_in_ch2_int_map_reg_t;
-
-
-/** Group: CORE0 AXI PDMA OUT CH0 INT MAP REG */
-/** Type of axi_pdma_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_axi_pdma_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_axi_pdma_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 AXI PDMA OUT CH1 INT MAP REG */
-/** Type of axi_pdma_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_axi_pdma_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_axi_pdma_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 AXI PDMA OUT CH2 INT MAP REG */
-/** Type of axi_pdma_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_axi_pdma_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_axi_pdma_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE0 RSA INT MAP REG */
-/** Type of rsa_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_rsa_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_rsa_int_map_reg_t;
-
-
-/** Group: CORE0 AES INT MAP REG */
-/** Type of aes_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_aes_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_aes_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_aes_int_map_reg_t;
-
-
-/** Group: CORE0 SHA INT MAP REG */
-/** Type of sha_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_sha_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_sha_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_sha_int_map_reg_t;
-
-
-/** Group: CORE0 ECC INT MAP REG */
-/** Type of ecc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ecc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ecc_int_map_reg_t;
-
-
-/** Group: CORE0 ECDSA INT MAP REG */
-/** Type of ecdsa_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ecdsa_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ecdsa_int_map_reg_t;
-
-
-/** Group: CORE0 KM INT MAP REG */
-/** Type of km_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_km_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_km_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_km_int_map_reg_t;
-
-
-/** Group: CORE0 GPIO INT0 MAP REG */
-/** Type of gpio_int0_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_gpio_int0_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_gpio_int0_map_reg_t;
-
-
-/** Group: CORE0 GPIO INT1 MAP REG */
-/** Type of gpio_int1_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_gpio_int1_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_gpio_int1_map_reg_t;
-
-
-/** Group: CORE0 GPIO INT2 MAP REG */
-/** Type of gpio_int2_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_gpio_int2_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_gpio_int2_map_reg_t;
-
-
-/** Group: CORE0 GPIO INT3 MAP REG */
-/** Type of gpio_int3_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_gpio_int3_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_gpio_int3_map_reg_t;
-
-
-/** Group: CORE0 GPIO PAD COMP INT MAP REG */
-/** Type of gpio_pad_comp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_gpio_pad_comp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_gpio_pad_comp_int_map_reg_t;
-
-
-/** Group: CORE0 CPU INT FROM CPU 0 MAP REG */
-/** Type of cpu_int_from_cpu_0_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_cpu_int_from_cpu_0_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_cpu_int_from_cpu_0_map_reg_t;
-
-
-/** Group: CORE0 CPU INT FROM CPU 1 MAP REG */
-/** Type of cpu_int_from_cpu_1_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_cpu_int_from_cpu_1_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_cpu_int_from_cpu_1_map_reg_t;
-
-
-/** Group: CORE0 CPU INT FROM CPU 2 MAP REG */
-/** Type of cpu_int_from_cpu_2_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_cpu_int_from_cpu_2_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_cpu_int_from_cpu_2_map_reg_t;
-
-
-/** Group: CORE0 CPU INT FROM CPU 3 MAP REG */
-/** Type of cpu_int_from_cpu_3_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_cpu_int_from_cpu_3_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_cpu_int_from_cpu_3_map_reg_t;
-
-
-/** Group: CORE0 CACHE INT MAP REG */
-/** Type of cache_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_cache_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_cache_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_cache_int_map_reg_t;
-
-
-/** Group: CORE0 FLASH MSPI INT MAP REG */
-/** Type of flash_mspi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_flash_mspi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_flash_mspi_int_map_reg_t;
-
-
-/** Group: CORE0 CSI BRIDGE INT MAP REG */
-/** Type of csi_bridge_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_csi_bridge_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_csi_bridge_int_map_reg_t;
-
-
-/** Group: CORE0 DSI BRIDGE INT MAP REG */
-/** Type of dsi_bridge_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_dsi_bridge_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_dsi_bridge_int_map_reg_t;
-
-
-/** Group: CORE0 CSI INT MAP REG */
-/** Type of csi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_csi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_csi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_csi_int_map_reg_t;
-
-
-/** Group: CORE0 DSI INT MAP REG */
-/** Type of dsi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_dsi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_dsi_int_map_reg_t;
-
-
-/** Group: CORE0 GMII PHY INT MAP REG */
-/** Type of gmii_phy_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_gmii_phy_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_gmii_phy_int_map_reg_t;
-
-
-/** Group: CORE0 LPI INT MAP REG */
-/** Type of lpi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_lpi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_lpi_int_map_reg_t;
-
-
-/** Group: CORE0 PMT INT MAP REG */
-/** Type of pmt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_pmt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_pmt_int_map_reg_t;
-
-
-/** Group: CORE0 SBD INT MAP REG */
-/** Type of sbd_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_sbd_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_sbd_int_map_reg_t;
-
-
-/** Group: CORE0 USB OTG INT MAP REG */
-/** Type of usb_otg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_usb_otg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_usb_otg_int_map_reg_t;
-
-
-/** Group: CORE0 USB OTG ENDP MULTI PROC INT MAP REG */
-/** Type of usb_otg_endp_multi_proc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_usb_otg_endp_multi_proc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_usb_otg_endp_multi_proc_int_map_reg_t;
-
-
-/** Group: CORE0 JPEG INT MAP REG */
-/** Type of jpeg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_jpeg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_jpeg_int_map_reg_t;
-
-
-/** Group: CORE0 PPA INT MAP REG */
-/** Type of ppa_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_ppa_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_ppa_int_map_reg_t;
-
-
-/** Group: CORE0 CORE0 TRACE INT MAP REG */
-/** Type of core0_trace_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_core0_trace_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_core0_trace_int_map_reg_t;
-
-
-/** Group: CORE0 CORE1 TRACE INT MAP REG */
-/** Type of core1_trace_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_core1_trace_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_core1_trace_int_map_reg_t;
-
-
-/** Group: CORE0 HP CORE CTRL INT MAP REG */
-/** Type of hp_core_ctrl_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_hp_core_ctrl_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_hp_core_ctrl_int_map_reg_t;
-
-
-/** Group: CORE0 ISP INT MAP REG */
-/** Type of isp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_isp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_isp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_isp_int_map_reg_t;
-
-
-/** Group: CORE0 I3C MST INT MAP REG */
-/** Type of i3c_mst_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_i3c_mst_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_i3c_mst_int_map_reg_t;
-
-
-/** Group: CORE0 I3C SLV INT MAP REG */
-/** Type of i3c_slv_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_i3c_slv_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_i3c_slv_int_map_reg_t;
-
-
-/** Group: CORE0 USB OTG11 INT MAP REG */
-/** Type of usb_otg11_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_usb_otg11_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_usb_otg11_int_map_reg_t;
-
-
-/** Group: CORE0 DMA2D IN CH0 INT MAP REG */
-/** Type of dma2d_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_dma2d_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_dma2d_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 DMA2D IN CH1 INT MAP REG */
-/** Type of dma2d_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_dma2d_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_dma2d_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 DMA2D OUT CH0 INT MAP REG */
-/** Type of dma2d_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_dma2d_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_dma2d_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 DMA2D OUT CH1 INT MAP REG */
-/** Type of dma2d_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_dma2d_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_dma2d_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 DMA2D OUT CH2 INT MAP REG */
-/** Type of dma2d_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_dma2d_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_dma2d_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE0 PSRAM MSPI INT MAP REG */
-/** Type of psram_mspi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_psram_mspi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_psram_mspi_int_map_reg_t;
-
-
-/** Group: CORE0 HP SYSREG INT MAP REG */
-/** Type of hp_sysreg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_hp_sysreg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_hp_sysreg_int_map_reg_t;
-
-
-/** Group: CORE0 PCNT INT MAP REG */
-/** Type of pcnt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_pcnt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_pcnt_int_map_reg_t;
-
-
-/** Group: CORE0 HP PAU INT MAP REG */
-/** Type of hp_pau_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_hp_pau_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_hp_pau_int_map_reg_t;
-
-
-/** Group: CORE0 HP PARLIO RX INT MAP REG */
-/** Type of hp_parlio_rx_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_hp_parlio_rx_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_hp_parlio_rx_int_map_reg_t;
-
-
-/** Group: CORE0 HP PARLIO TX INT MAP REG */
-/** Type of hp_parlio_tx_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_hp_parlio_tx_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_hp_parlio_tx_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D OUT CH0 INT MAP REG */
-/** Type of h264_dma2d_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D OUT CH1 INT MAP REG */
-/** Type of h264_dma2d_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D OUT CH2 INT MAP REG */
-/** Type of h264_dma2d_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D OUT CH3 INT MAP REG */
-/** Type of h264_dma2d_out_ch3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_out_ch3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_out_ch3_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D OUT CH4 INT MAP REG */
-/** Type of h264_dma2d_out_ch4_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_out_ch4_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_out_ch4_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D IN CH0 INT MAP REG */
-/** Type of h264_dma2d_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D IN CH1 INT MAP REG */
-/** Type of h264_dma2d_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D IN CH2 INT MAP REG */
-/** Type of h264_dma2d_in_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_in_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_in_ch2_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D IN CH3 INT MAP REG */
-/** Type of h264_dma2d_in_ch3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_in_ch3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_in_ch3_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D IN CH4 INT MAP REG */
-/** Type of h264_dma2d_in_ch4_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_in_ch4_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_in_ch4_int_map_reg_t;
-
-
-/** Group: CORE0 H264 DMA2D IN CH5 INT MAP REG */
-/** Type of h264_dma2d_in_ch5_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_dma2d_in_ch5_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_dma2d_in_ch5_int_map_reg_t;
-
-
-/** Group: CORE0 H264 REG INT MAP REG */
-/** Type of h264_reg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_h264_reg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_h264_reg_int_map_reg_t;
-
-
-/** Group: CORE0 ASSIST DEBUG INT MAP REG */
-/** Type of assist_debug_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_assist_debug_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core0_assist_debug_int_map_reg_t;
-
-
-/** Group: CORE0 INTR STATUS REG 0 REG */
-/** Type of intr_status_reg_0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_intr_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_intr_status_0:32;
-    };
-    uint32_t val;
-} core0_intr_status_reg_0_reg_t;
-
-
-/** Group: CORE0 INTR STATUS REG 1 REG */
-/** Type of intr_status_reg_1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_intr_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_intr_status_1:32;
-    };
-    uint32_t val;
-} core0_intr_status_reg_1_reg_t;
-
-
-/** Group: CORE0 INTR STATUS REG 2 REG */
-/** Type of intr_status_reg_2 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_intr_status_2 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_intr_status_2:32;
-    };
-    uint32_t val;
-} core0_intr_status_reg_2_reg_t;
-
-
-/** Group: CORE0 INTR STATUS REG 3 REG */
-/** Type of intr_status_reg_3 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_intr_status_3 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core0_intr_status_3:32;
-    };
-    uint32_t val;
-} core0_intr_status_reg_3_reg_t;
-
-
-/** Group: CORE0 CLOCK GATE REG */
-/** Type of clock_gate register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t core0_reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} core0_clock_gate_reg_t;
-
-
-/** Group: CORE0 INTERRUPT REG DATE REG */
-/** Type of interrupt_reg_date register
- *  NA
- */
-typedef union {
-    struct {
-        /** core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752;
-         *  NA
-         */
-        uint32_t core0_interrupt_reg_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} core0_interrupt_reg_date_reg_t;
-
-
-typedef struct {
-    volatile core0_lp_rtc_int_map_reg_t lp_rtc_int_map;
-    volatile core0_lp_wdt_int_map_reg_t lp_wdt_int_map;
-    volatile core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map;
-    volatile core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map;
-    volatile core0_mb_hp_int_map_reg_t mb_hp_int_map;
-    volatile core0_mb_lp_int_map_reg_t mb_lp_int_map;
-    volatile core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map;
-    volatile core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map;
-    volatile core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map;
-    volatile core0_lp_adc_int_map_reg_t lp_adc_int_map;
-    volatile core0_lp_gpio_int_map_reg_t lp_gpio_int_map;
-    volatile core0_lp_i2c_int_map_reg_t lp_i2c_int_map;
-    volatile core0_lp_i2s_int_map_reg_t lp_i2s_int_map;
-    volatile core0_lp_spi_int_map_reg_t lp_spi_int_map;
-    volatile core0_lp_touch_int_map_reg_t lp_touch_int_map;
-    volatile core0_lp_tsens_int_map_reg_t lp_tsens_int_map;
-    volatile core0_lp_uart_int_map_reg_t lp_uart_int_map;
-    volatile core0_lp_efuse_int_map_reg_t lp_efuse_int_map;
-    volatile core0_lp_sw_int_map_reg_t lp_sw_int_map;
-    volatile core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map;
-    volatile core0_lp_huk_int_map_reg_t lp_huk_int_map;
-    volatile core0_sys_icm_int_map_reg_t sys_icm_int_map;
-    volatile core0_usb_device_int_map_reg_t usb_device_int_map;
-    volatile core0_sdio_host_int_map_reg_t sdio_host_int_map;
-    volatile core0_gdma_int_map_reg_t gdma_int_map;
-    volatile core0_spi2_int_map_reg_t spi2_int_map;
-    volatile core0_spi3_int_map_reg_t spi3_int_map;
-    volatile core0_i2s0_int_map_reg_t i2s0_int_map;
-    volatile core0_i2s1_int_map_reg_t i2s1_int_map;
-    volatile core0_i2s2_int_map_reg_t i2s2_int_map;
-    volatile core0_uhci0_int_map_reg_t uhci0_int_map;
-    volatile core0_uart0_int_map_reg_t uart0_int_map;
-    volatile core0_uart1_int_map_reg_t uart1_int_map;
-    volatile core0_uart2_int_map_reg_t uart2_int_map;
-    volatile core0_uart3_int_map_reg_t uart3_int_map;
-    volatile core0_uart4_int_map_reg_t uart4_int_map;
-    volatile core0_lcd_cam_int_map_reg_t lcd_cam_int_map;
-    volatile core0_adc_int_map_reg_t adc_int_map;
-    volatile core0_pwm0_int_map_reg_t pwm0_int_map;
-    volatile core0_pwm1_int_map_reg_t pwm1_int_map;
-    volatile core0_can0_int_map_reg_t can0_int_map;
-    volatile core0_can1_int_map_reg_t can1_int_map;
-    volatile core0_can2_int_map_reg_t can2_int_map;
-    volatile core0_rmt_int_map_reg_t rmt_int_map;
-    volatile core0_i2c0_int_map_reg_t i2c0_int_map;
-    volatile core0_i2c1_int_map_reg_t i2c1_int_map;
-    volatile core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map;
-    volatile core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map;
-    volatile core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map;
-    volatile core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map;
-    volatile core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map;
-    volatile core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map;
-    volatile core0_ledc_int_map_reg_t ledc_int_map;
-    volatile core0_systimer_target0_int_map_reg_t systimer_target0_int_map;
-    volatile core0_systimer_target1_int_map_reg_t systimer_target1_int_map;
-    volatile core0_systimer_target2_int_map_reg_t systimer_target2_int_map;
-    volatile core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map;
-    volatile core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map;
-    volatile core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map;
-    volatile core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map;
-    volatile core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map;
-    volatile core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map;
-    volatile core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map;
-    volatile core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map;
-    volatile core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map;
-    volatile core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map;
-    volatile core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map;
-    volatile core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map;
-    volatile core0_rsa_int_map_reg_t rsa_int_map;
-    volatile core0_aes_int_map_reg_t aes_int_map;
-    volatile core0_sha_int_map_reg_t sha_int_map;
-    volatile core0_ecc_int_map_reg_t ecc_int_map;
-    volatile core0_ecdsa_int_map_reg_t ecdsa_int_map;
-    volatile core0_km_int_map_reg_t km_int_map;
-    volatile core0_gpio_int0_map_reg_t gpio_int0_map;
-    volatile core0_gpio_int1_map_reg_t gpio_int1_map;
-    volatile core0_gpio_int2_map_reg_t gpio_int2_map;
-    volatile core0_gpio_int3_map_reg_t gpio_int3_map;
-    volatile core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map;
-    volatile core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map;
-    volatile core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map;
-    volatile core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map;
-    volatile core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map;
-    volatile core0_cache_int_map_reg_t cache_int_map;
-    volatile core0_flash_mspi_int_map_reg_t flash_mspi_int_map;
-    volatile core0_csi_bridge_int_map_reg_t csi_bridge_int_map;
-    volatile core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map;
-    volatile core0_csi_int_map_reg_t csi_int_map;
-    volatile core0_dsi_int_map_reg_t dsi_int_map;
-    volatile core0_gmii_phy_int_map_reg_t gmii_phy_int_map;
-    volatile core0_lpi_int_map_reg_t lpi_int_map;
-    volatile core0_pmt_int_map_reg_t pmt_int_map;
-    volatile core0_sbd_int_map_reg_t sbd_int_map;
-    volatile core0_usb_otg_int_map_reg_t usb_otg_int_map;
-    volatile core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map;
-    volatile core0_jpeg_int_map_reg_t jpeg_int_map;
-    volatile core0_ppa_int_map_reg_t ppa_int_map;
-    volatile core0_core0_trace_int_map_reg_t core0_trace_int_map;
-    volatile core0_core1_trace_int_map_reg_t core1_trace_int_map;
-    volatile core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map;
-    volatile core0_isp_int_map_reg_t isp_int_map;
-    volatile core0_i3c_mst_int_map_reg_t i3c_mst_int_map;
-    volatile core0_i3c_slv_int_map_reg_t i3c_slv_int_map;
-    volatile core0_usb_otg11_int_map_reg_t usb_otg11_int_map;
-    volatile core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map;
-    volatile core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map;
-    volatile core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map;
-    volatile core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map;
-    volatile core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map;
-    volatile core0_psram_mspi_int_map_reg_t psram_mspi_int_map;
-    volatile core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map;
-    volatile core0_pcnt_int_map_reg_t pcnt_int_map;
-    volatile core0_hp_pau_int_map_reg_t hp_pau_int_map;
-    volatile core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map;
-    volatile core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map;
-    volatile core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map;
-    volatile core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map;
-    volatile core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map;
-    volatile core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map;
-    volatile core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map;
-    volatile core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map;
-    volatile core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map;
-    volatile core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map;
-    volatile core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map;
-    volatile core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map;
-    volatile core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map;
-    volatile core0_h264_reg_int_map_reg_t h264_reg_int_map;
-    volatile core0_assist_debug_int_map_reg_t assist_debug_int_map;
-    volatile core0_intr_status_reg_0_reg_t intr_status_reg_0;
-    volatile core0_intr_status_reg_1_reg_t intr_status_reg_1;
-    volatile core0_intr_status_reg_2_reg_t intr_status_reg_2;
-    volatile core0_intr_status_reg_3_reg_t intr_status_reg_3;
-    volatile core0_clock_gate_reg_t clock_gate;
-    uint32_t reserved_214[122];
-    volatile core0_interrupt_reg_date_reg_t interrupt_reg_date;
-} core0_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(core0_dev_t) == 0x400, "Invalid size of core0_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/core1_interrupt_reg.h b/components/soc/esp32p4/include/soc/core1_interrupt_reg.h
deleted file mode 100644
index f7a6bd5409..0000000000
--- a/components/soc/esp32p4/include/soc/core1_interrupt_reg.h
+++ /dev/null
@@ -1,1624 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** CORE1_LP_RTC_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_RTC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x0)
-/** CORE1_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_RTC_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_RTC_INT_MAP_M  (CORE1_CORE1_LP_RTC_INT_MAP_V << CORE1_CORE1_LP_RTC_INT_MAP_S)
-#define CORE1_CORE1_LP_RTC_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_RTC_INT_MAP_S  0
-
-/** CORE1_LP_WDT_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x4)
-/** CORE1_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_WDT_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_WDT_INT_MAP_M  (CORE1_CORE1_LP_WDT_INT_MAP_V << CORE1_CORE1_LP_WDT_INT_MAP_S)
-#define CORE1_CORE1_LP_WDT_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_WDT_INT_MAP_S  0
-
-/** CORE1_LP_TIMER_REG_0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x8)
-/** CORE1_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_M  (CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S)
-#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S  0
-
-/** CORE1_LP_TIMER_REG_1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc)
-/** CORE1_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_M  (CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S)
-#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S  0
-
-/** CORE1_MB_HP_INT_MAP_REG register
- *  NA
- */
-#define CORE1_MB_HP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x10)
-/** CORE1_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_MB_HP_INT_MAP    0x0000003FU
-#define CORE1_CORE1_MB_HP_INT_MAP_M  (CORE1_CORE1_MB_HP_INT_MAP_V << CORE1_CORE1_MB_HP_INT_MAP_S)
-#define CORE1_CORE1_MB_HP_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_MB_HP_INT_MAP_S  0
-
-/** CORE1_MB_LP_INT_MAP_REG register
- *  NA
- */
-#define CORE1_MB_LP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x14)
-/** CORE1_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_MB_LP_INT_MAP    0x0000003FU
-#define CORE1_CORE1_MB_LP_INT_MAP_M  (CORE1_CORE1_MB_LP_INT_MAP_V << CORE1_CORE1_MB_LP_INT_MAP_S)
-#define CORE1_CORE1_MB_LP_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_MB_LP_INT_MAP_S  0
-
-/** CORE1_PMU_REG_0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x18)
-/** CORE1_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PMU_REG_0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PMU_REG_0_INT_MAP_M  (CORE1_CORE1_PMU_REG_0_INT_MAP_V << CORE1_CORE1_PMU_REG_0_INT_MAP_S)
-#define CORE1_CORE1_PMU_REG_0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PMU_REG_0_INT_MAP_S  0
-
-/** CORE1_PMU_REG_1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c)
-/** CORE1_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PMU_REG_1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PMU_REG_1_INT_MAP_M  (CORE1_CORE1_PMU_REG_1_INT_MAP_V << CORE1_CORE1_PMU_REG_1_INT_MAP_S)
-#define CORE1_CORE1_PMU_REG_1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PMU_REG_1_INT_MAP_S  0
-
-/** CORE1_LP_ANAPERI_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x20)
-/** CORE1_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_ANAPERI_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_ANAPERI_INT_MAP_M  (CORE1_CORE1_LP_ANAPERI_INT_MAP_V << CORE1_CORE1_LP_ANAPERI_INT_MAP_S)
-#define CORE1_CORE1_LP_ANAPERI_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_ANAPERI_INT_MAP_S  0
-
-/** CORE1_LP_ADC_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_ADC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x24)
-/** CORE1_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_ADC_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_ADC_INT_MAP_M  (CORE1_CORE1_LP_ADC_INT_MAP_V << CORE1_CORE1_LP_ADC_INT_MAP_S)
-#define CORE1_CORE1_LP_ADC_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_ADC_INT_MAP_S  0
-
-/** CORE1_LP_GPIO_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_GPIO_INT_MAP_REG (DR_REG_CORE1_BASE + 0x28)
-/** CORE1_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_GPIO_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_GPIO_INT_MAP_M  (CORE1_CORE1_LP_GPIO_INT_MAP_V << CORE1_CORE1_LP_GPIO_INT_MAP_S)
-#define CORE1_CORE1_LP_GPIO_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_GPIO_INT_MAP_S  0
-
-/** CORE1_LP_I2C_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_I2C_INT_MAP_REG (DR_REG_CORE1_BASE + 0x2c)
-/** CORE1_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_I2C_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_I2C_INT_MAP_M  (CORE1_CORE1_LP_I2C_INT_MAP_V << CORE1_CORE1_LP_I2C_INT_MAP_S)
-#define CORE1_CORE1_LP_I2C_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_I2C_INT_MAP_S  0
-
-/** CORE1_LP_I2S_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_I2S_INT_MAP_REG (DR_REG_CORE1_BASE + 0x30)
-/** CORE1_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_I2S_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_I2S_INT_MAP_M  (CORE1_CORE1_LP_I2S_INT_MAP_V << CORE1_CORE1_LP_I2S_INT_MAP_S)
-#define CORE1_CORE1_LP_I2S_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_I2S_INT_MAP_S  0
-
-/** CORE1_LP_SPI_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_SPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x34)
-/** CORE1_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_SPI_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_SPI_INT_MAP_M  (CORE1_CORE1_LP_SPI_INT_MAP_V << CORE1_CORE1_LP_SPI_INT_MAP_S)
-#define CORE1_CORE1_LP_SPI_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_SPI_INT_MAP_S  0
-
-/** CORE1_LP_TOUCH_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_CORE1_BASE + 0x38)
-/** CORE1_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_TOUCH_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_TOUCH_INT_MAP_M  (CORE1_CORE1_LP_TOUCH_INT_MAP_V << CORE1_CORE1_LP_TOUCH_INT_MAP_S)
-#define CORE1_CORE1_LP_TOUCH_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_TOUCH_INT_MAP_S  0
-
-/** CORE1_LP_TSENS_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_TSENS_INT_MAP_REG (DR_REG_CORE1_BASE + 0x3c)
-/** CORE1_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_TSENS_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_TSENS_INT_MAP_M  (CORE1_CORE1_LP_TSENS_INT_MAP_V << CORE1_CORE1_LP_TSENS_INT_MAP_S)
-#define CORE1_CORE1_LP_TSENS_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_TSENS_INT_MAP_S  0
-
-/** CORE1_LP_UART_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_UART_INT_MAP_REG (DR_REG_CORE1_BASE + 0x40)
-/** CORE1_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_UART_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_UART_INT_MAP_M  (CORE1_CORE1_LP_UART_INT_MAP_V << CORE1_CORE1_LP_UART_INT_MAP_S)
-#define CORE1_CORE1_LP_UART_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_UART_INT_MAP_S  0
-
-/** CORE1_LP_EFUSE_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x44)
-/** CORE1_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_EFUSE_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_EFUSE_INT_MAP_M  (CORE1_CORE1_LP_EFUSE_INT_MAP_V << CORE1_CORE1_LP_EFUSE_INT_MAP_S)
-#define CORE1_CORE1_LP_EFUSE_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_EFUSE_INT_MAP_S  0
-
-/** CORE1_LP_SW_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_SW_INT_MAP_REG (DR_REG_CORE1_BASE + 0x48)
-/** CORE1_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_SW_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_SW_INT_MAP_M  (CORE1_CORE1_LP_SW_INT_MAP_V << CORE1_CORE1_LP_SW_INT_MAP_S)
-#define CORE1_CORE1_LP_SW_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_SW_INT_MAP_S  0
-
-/** CORE1_LP_SYSREG_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x4c)
-/** CORE1_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_SYSREG_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_SYSREG_INT_MAP_M  (CORE1_CORE1_LP_SYSREG_INT_MAP_V << CORE1_CORE1_LP_SYSREG_INT_MAP_S)
-#define CORE1_CORE1_LP_SYSREG_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_SYSREG_INT_MAP_S  0
-
-/** CORE1_LP_HUK_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LP_HUK_INT_MAP_REG (DR_REG_CORE1_BASE + 0x50)
-/** CORE1_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LP_HUK_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LP_HUK_INT_MAP_M  (CORE1_CORE1_LP_HUK_INT_MAP_V << CORE1_CORE1_LP_HUK_INT_MAP_S)
-#define CORE1_CORE1_LP_HUK_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LP_HUK_INT_MAP_S  0
-
-/** CORE1_SYS_ICM_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SYS_ICM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x54)
-/** CORE1_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SYS_ICM_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SYS_ICM_INT_MAP_M  (CORE1_CORE1_SYS_ICM_INT_MAP_V << CORE1_CORE1_SYS_ICM_INT_MAP_S)
-#define CORE1_CORE1_SYS_ICM_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SYS_ICM_INT_MAP_S  0
-
-/** CORE1_USB_DEVICE_INT_MAP_REG register
- *  NA
- */
-#define CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x58)
-/** CORE1_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_USB_DEVICE_INT_MAP    0x0000003FU
-#define CORE1_CORE1_USB_DEVICE_INT_MAP_M  (CORE1_CORE1_USB_DEVICE_INT_MAP_V << CORE1_CORE1_USB_DEVICE_INT_MAP_S)
-#define CORE1_CORE1_USB_DEVICE_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_USB_DEVICE_INT_MAP_S  0
-
-/** CORE1_SDIO_HOST_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_CORE1_BASE + 0x5c)
-/** CORE1_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SDIO_HOST_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SDIO_HOST_INT_MAP_M  (CORE1_CORE1_SDIO_HOST_INT_MAP_V << CORE1_CORE1_SDIO_HOST_INT_MAP_S)
-#define CORE1_CORE1_SDIO_HOST_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SDIO_HOST_INT_MAP_S  0
-
-/** CORE1_GDMA_INT_MAP_REG register
- *  NA
- */
-#define CORE1_GDMA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x60)
-/** CORE1_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_GDMA_INT_MAP    0x0000003FU
-#define CORE1_CORE1_GDMA_INT_MAP_M  (CORE1_CORE1_GDMA_INT_MAP_V << CORE1_CORE1_GDMA_INT_MAP_S)
-#define CORE1_CORE1_GDMA_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_GDMA_INT_MAP_S  0
-
-/** CORE1_SPI2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SPI2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x64)
-/** CORE1_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SPI2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SPI2_INT_MAP_M  (CORE1_CORE1_SPI2_INT_MAP_V << CORE1_CORE1_SPI2_INT_MAP_S)
-#define CORE1_CORE1_SPI2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SPI2_INT_MAP_S  0
-
-/** CORE1_SPI3_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SPI3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x68)
-/** CORE1_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SPI3_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SPI3_INT_MAP_M  (CORE1_CORE1_SPI3_INT_MAP_V << CORE1_CORE1_SPI3_INT_MAP_S)
-#define CORE1_CORE1_SPI3_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SPI3_INT_MAP_S  0
-
-/** CORE1_I2S0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_I2S0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x6c)
-/** CORE1_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_I2S0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_I2S0_INT_MAP_M  (CORE1_CORE1_I2S0_INT_MAP_V << CORE1_CORE1_I2S0_INT_MAP_S)
-#define CORE1_CORE1_I2S0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_I2S0_INT_MAP_S  0
-
-/** CORE1_I2S1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_I2S1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x70)
-/** CORE1_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_I2S1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_I2S1_INT_MAP_M  (CORE1_CORE1_I2S1_INT_MAP_V << CORE1_CORE1_I2S1_INT_MAP_S)
-#define CORE1_CORE1_I2S1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_I2S1_INT_MAP_S  0
-
-/** CORE1_I2S2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_I2S2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x74)
-/** CORE1_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_I2S2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_I2S2_INT_MAP_M  (CORE1_CORE1_I2S2_INT_MAP_V << CORE1_CORE1_I2S2_INT_MAP_S)
-#define CORE1_CORE1_I2S2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_I2S2_INT_MAP_S  0
-
-/** CORE1_UHCI0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_UHCI0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x78)
-/** CORE1_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_UHCI0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_UHCI0_INT_MAP_M  (CORE1_CORE1_UHCI0_INT_MAP_V << CORE1_CORE1_UHCI0_INT_MAP_S)
-#define CORE1_CORE1_UHCI0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_UHCI0_INT_MAP_S  0
-
-/** CORE1_UART0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_UART0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x7c)
-/** CORE1_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_UART0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_UART0_INT_MAP_M  (CORE1_CORE1_UART0_INT_MAP_V << CORE1_CORE1_UART0_INT_MAP_S)
-#define CORE1_CORE1_UART0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_UART0_INT_MAP_S  0
-
-/** CORE1_UART1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_UART1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x80)
-/** CORE1_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_UART1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_UART1_INT_MAP_M  (CORE1_CORE1_UART1_INT_MAP_V << CORE1_CORE1_UART1_INT_MAP_S)
-#define CORE1_CORE1_UART1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_UART1_INT_MAP_S  0
-
-/** CORE1_UART2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_UART2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x84)
-/** CORE1_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_UART2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_UART2_INT_MAP_M  (CORE1_CORE1_UART2_INT_MAP_V << CORE1_CORE1_UART2_INT_MAP_S)
-#define CORE1_CORE1_UART2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_UART2_INT_MAP_S  0
-
-/** CORE1_UART3_INT_MAP_REG register
- *  NA
- */
-#define CORE1_UART3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x88)
-/** CORE1_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_UART3_INT_MAP    0x0000003FU
-#define CORE1_CORE1_UART3_INT_MAP_M  (CORE1_CORE1_UART3_INT_MAP_V << CORE1_CORE1_UART3_INT_MAP_S)
-#define CORE1_CORE1_UART3_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_UART3_INT_MAP_S  0
-
-/** CORE1_UART4_INT_MAP_REG register
- *  NA
- */
-#define CORE1_UART4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x8c)
-/** CORE1_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_UART4_INT_MAP    0x0000003FU
-#define CORE1_CORE1_UART4_INT_MAP_M  (CORE1_CORE1_UART4_INT_MAP_V << CORE1_CORE1_UART4_INT_MAP_S)
-#define CORE1_CORE1_UART4_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_UART4_INT_MAP_S  0
-
-/** CORE1_LCD_CAM_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LCD_CAM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x90)
-/** CORE1_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LCD_CAM_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LCD_CAM_INT_MAP_M  (CORE1_CORE1_LCD_CAM_INT_MAP_V << CORE1_CORE1_LCD_CAM_INT_MAP_S)
-#define CORE1_CORE1_LCD_CAM_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LCD_CAM_INT_MAP_S  0
-
-/** CORE1_ADC_INT_MAP_REG register
- *  NA
- */
-#define CORE1_ADC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x94)
-/** CORE1_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_ADC_INT_MAP    0x0000003FU
-#define CORE1_CORE1_ADC_INT_MAP_M  (CORE1_CORE1_ADC_INT_MAP_V << CORE1_CORE1_ADC_INT_MAP_S)
-#define CORE1_CORE1_ADC_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_ADC_INT_MAP_S  0
-
-/** CORE1_PWM0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PWM0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x98)
-/** CORE1_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PWM0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PWM0_INT_MAP_M  (CORE1_CORE1_PWM0_INT_MAP_V << CORE1_CORE1_PWM0_INT_MAP_S)
-#define CORE1_CORE1_PWM0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PWM0_INT_MAP_S  0
-
-/** CORE1_PWM1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PWM1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x9c)
-/** CORE1_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PWM1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PWM1_INT_MAP_M  (CORE1_CORE1_PWM1_INT_MAP_V << CORE1_CORE1_PWM1_INT_MAP_S)
-#define CORE1_CORE1_PWM1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PWM1_INT_MAP_S  0
-
-/** CORE1_CAN0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CAN0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa0)
-/** CORE1_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CAN0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CAN0_INT_MAP_M  (CORE1_CORE1_CAN0_INT_MAP_V << CORE1_CORE1_CAN0_INT_MAP_S)
-#define CORE1_CORE1_CAN0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CAN0_INT_MAP_S  0
-
-/** CORE1_CAN1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CAN1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa4)
-/** CORE1_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CAN1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CAN1_INT_MAP_M  (CORE1_CORE1_CAN1_INT_MAP_V << CORE1_CORE1_CAN1_INT_MAP_S)
-#define CORE1_CORE1_CAN1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CAN1_INT_MAP_S  0
-
-/** CORE1_CAN2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CAN2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa8)
-/** CORE1_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CAN2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CAN2_INT_MAP_M  (CORE1_CORE1_CAN2_INT_MAP_V << CORE1_CORE1_CAN2_INT_MAP_S)
-#define CORE1_CORE1_CAN2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CAN2_INT_MAP_S  0
-
-/** CORE1_RMT_INT_MAP_REG register
- *  NA
- */
-#define CORE1_RMT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xac)
-/** CORE1_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_RMT_INT_MAP    0x0000003FU
-#define CORE1_CORE1_RMT_INT_MAP_M  (CORE1_CORE1_RMT_INT_MAP_V << CORE1_CORE1_RMT_INT_MAP_S)
-#define CORE1_CORE1_RMT_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_RMT_INT_MAP_S  0
-
-/** CORE1_I2C0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_I2C0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb0)
-/** CORE1_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_I2C0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_I2C0_INT_MAP_M  (CORE1_CORE1_I2C0_INT_MAP_V << CORE1_CORE1_I2C0_INT_MAP_S)
-#define CORE1_CORE1_I2C0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_I2C0_INT_MAP_S  0
-
-/** CORE1_I2C1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_I2C1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb4)
-/** CORE1_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_I2C1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_I2C1_INT_MAP_M  (CORE1_CORE1_I2C1_INT_MAP_V << CORE1_CORE1_I2C1_INT_MAP_S)
-#define CORE1_CORE1_I2C1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_I2C1_INT_MAP_S  0
-
-/** CORE1_TIMERGRP0_T0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb8)
-/** CORE1_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_M  (CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S)
-#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S  0
-
-/** CORE1_TIMERGRP0_T1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xbc)
-/** CORE1_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_M  (CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S)
-#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S  0
-
-/** CORE1_TIMERGRP0_WDT_INT_MAP_REG register
- *  NA
- */
-#define CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc0)
-/** CORE1_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP    0x0000003FU
-#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_M  (CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S)
-#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S  0
-
-/** CORE1_TIMERGRP1_T0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc4)
-/** CORE1_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_M  (CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S)
-#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S  0
-
-/** CORE1_TIMERGRP1_T1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc8)
-/** CORE1_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_M  (CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S)
-#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S  0
-
-/** CORE1_TIMERGRP1_WDT_INT_MAP_REG register
- *  NA
- */
-#define CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xcc)
-/** CORE1_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP    0x0000003FU
-#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_M  (CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S)
-#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S  0
-
-/** CORE1_LEDC_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LEDC_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd0)
-/** CORE1_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LEDC_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LEDC_INT_MAP_M  (CORE1_CORE1_LEDC_INT_MAP_V << CORE1_CORE1_LEDC_INT_MAP_S)
-#define CORE1_CORE1_LEDC_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LEDC_INT_MAP_S  0
-
-/** CORE1_SYSTIMER_TARGET0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd4)
-/** CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_M  (CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S)
-#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S  0
-
-/** CORE1_SYSTIMER_TARGET1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd8)
-/** CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_M  (CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S)
-#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S  0
-
-/** CORE1_SYSTIMER_TARGET2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xdc)
-/** CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_M  (CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S)
-#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S  0
-
-/** CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe0)
-/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S)
-#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S  0
-
-/** CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe4)
-/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S)
-#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S  0
-
-/** CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe8)
-/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S)
-#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S  0
-
-/** CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xec)
-/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S)
-#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S  0
-
-/** CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf0)
-/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S)
-#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S  0
-
-/** CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf4)
-/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S)
-#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S  0
-
-/** CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf8)
-/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S)
-#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S  0
-
-/** CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xfc)
-/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S)
-#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S  0
-
-/** CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x100)
-/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S)
-#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S  0
-
-/** CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x104)
-/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S)
-#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S  0
-
-/** CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x108)
-/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S)
-#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S  0
-
-/** CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x10c)
-/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S)
-#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S  0
-
-/** CORE1_RSA_INT_MAP_REG register
- *  NA
- */
-#define CORE1_RSA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x110)
-/** CORE1_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_RSA_INT_MAP    0x0000003FU
-#define CORE1_CORE1_RSA_INT_MAP_M  (CORE1_CORE1_RSA_INT_MAP_V << CORE1_CORE1_RSA_INT_MAP_S)
-#define CORE1_CORE1_RSA_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_RSA_INT_MAP_S  0
-
-/** CORE1_AES_INT_MAP_REG register
- *  NA
- */
-#define CORE1_AES_INT_MAP_REG (DR_REG_CORE1_BASE + 0x114)
-/** CORE1_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_AES_INT_MAP    0x0000003FU
-#define CORE1_CORE1_AES_INT_MAP_M  (CORE1_CORE1_AES_INT_MAP_V << CORE1_CORE1_AES_INT_MAP_S)
-#define CORE1_CORE1_AES_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_AES_INT_MAP_S  0
-
-/** CORE1_SHA_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SHA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x118)
-/** CORE1_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SHA_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SHA_INT_MAP_M  (CORE1_CORE1_SHA_INT_MAP_V << CORE1_CORE1_SHA_INT_MAP_S)
-#define CORE1_CORE1_SHA_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SHA_INT_MAP_S  0
-
-/** CORE1_ECC_INT_MAP_REG register
- *  NA
- */
-#define CORE1_ECC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x11c)
-/** CORE1_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_ECC_INT_MAP    0x0000003FU
-#define CORE1_CORE1_ECC_INT_MAP_M  (CORE1_CORE1_ECC_INT_MAP_V << CORE1_CORE1_ECC_INT_MAP_S)
-#define CORE1_CORE1_ECC_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_ECC_INT_MAP_S  0
-
-/** CORE1_ECDSA_INT_MAP_REG register
- *  NA
- */
-#define CORE1_ECDSA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x120)
-/** CORE1_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_ECDSA_INT_MAP    0x0000003FU
-#define CORE1_CORE1_ECDSA_INT_MAP_M  (CORE1_CORE1_ECDSA_INT_MAP_V << CORE1_CORE1_ECDSA_INT_MAP_S)
-#define CORE1_CORE1_ECDSA_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_ECDSA_INT_MAP_S  0
-
-/** CORE1_KM_INT_MAP_REG register
- *  NA
- */
-#define CORE1_KM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x124)
-/** CORE1_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_KM_INT_MAP    0x0000003FU
-#define CORE1_CORE1_KM_INT_MAP_M  (CORE1_CORE1_KM_INT_MAP_V << CORE1_CORE1_KM_INT_MAP_S)
-#define CORE1_CORE1_KM_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_KM_INT_MAP_S  0
-
-/** CORE1_GPIO_INT0_MAP_REG register
- *  NA
- */
-#define CORE1_GPIO_INT0_MAP_REG (DR_REG_CORE1_BASE + 0x128)
-/** CORE1_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_GPIO_INT0_MAP    0x0000003FU
-#define CORE1_CORE1_GPIO_INT0_MAP_M  (CORE1_CORE1_GPIO_INT0_MAP_V << CORE1_CORE1_GPIO_INT0_MAP_S)
-#define CORE1_CORE1_GPIO_INT0_MAP_V  0x0000003FU
-#define CORE1_CORE1_GPIO_INT0_MAP_S  0
-
-/** CORE1_GPIO_INT1_MAP_REG register
- *  NA
- */
-#define CORE1_GPIO_INT1_MAP_REG (DR_REG_CORE1_BASE + 0x12c)
-/** CORE1_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_GPIO_INT1_MAP    0x0000003FU
-#define CORE1_CORE1_GPIO_INT1_MAP_M  (CORE1_CORE1_GPIO_INT1_MAP_V << CORE1_CORE1_GPIO_INT1_MAP_S)
-#define CORE1_CORE1_GPIO_INT1_MAP_V  0x0000003FU
-#define CORE1_CORE1_GPIO_INT1_MAP_S  0
-
-/** CORE1_GPIO_INT2_MAP_REG register
- *  NA
- */
-#define CORE1_GPIO_INT2_MAP_REG (DR_REG_CORE1_BASE + 0x130)
-/** CORE1_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_GPIO_INT2_MAP    0x0000003FU
-#define CORE1_CORE1_GPIO_INT2_MAP_M  (CORE1_CORE1_GPIO_INT2_MAP_V << CORE1_CORE1_GPIO_INT2_MAP_S)
-#define CORE1_CORE1_GPIO_INT2_MAP_V  0x0000003FU
-#define CORE1_CORE1_GPIO_INT2_MAP_S  0
-
-/** CORE1_GPIO_INT3_MAP_REG register
- *  NA
- */
-#define CORE1_GPIO_INT3_MAP_REG (DR_REG_CORE1_BASE + 0x134)
-/** CORE1_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_GPIO_INT3_MAP    0x0000003FU
-#define CORE1_CORE1_GPIO_INT3_MAP_M  (CORE1_CORE1_GPIO_INT3_MAP_V << CORE1_CORE1_GPIO_INT3_MAP_S)
-#define CORE1_CORE1_GPIO_INT3_MAP_V  0x0000003FU
-#define CORE1_CORE1_GPIO_INT3_MAP_S  0
-
-/** CORE1_GPIO_PAD_COMP_INT_MAP_REG register
- *  NA
- */
-#define CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x138)
-/** CORE1_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP    0x0000003FU
-#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_M  (CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V << CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S)
-#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S  0
-
-/** CORE1_CPU_INT_FROM_CPU_0_MAP_REG register
- *  NA
- */
-#define CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_CORE1_BASE + 0x13c)
-/** CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP    0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S)
-#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V  0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S  0
-
-/** CORE1_CPU_INT_FROM_CPU_1_MAP_REG register
- *  NA
- */
-#define CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_CORE1_BASE + 0x140)
-/** CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP    0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S)
-#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V  0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S  0
-
-/** CORE1_CPU_INT_FROM_CPU_2_MAP_REG register
- *  NA
- */
-#define CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_CORE1_BASE + 0x144)
-/** CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP    0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S)
-#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V  0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S  0
-
-/** CORE1_CPU_INT_FROM_CPU_3_MAP_REG register
- *  NA
- */
-#define CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_CORE1_BASE + 0x148)
-/** CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP    0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S)
-#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V  0x0000003FU
-#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S  0
-
-/** CORE1_CACHE_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CACHE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x14c)
-/** CORE1_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CACHE_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CACHE_INT_MAP_M  (CORE1_CORE1_CACHE_INT_MAP_V << CORE1_CORE1_CACHE_INT_MAP_S)
-#define CORE1_CORE1_CACHE_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CACHE_INT_MAP_S  0
-
-/** CORE1_FLASH_MSPI_INT_MAP_REG register
- *  NA
- */
-#define CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x150)
-/** CORE1_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_FLASH_MSPI_INT_MAP    0x0000003FU
-#define CORE1_CORE1_FLASH_MSPI_INT_MAP_M  (CORE1_CORE1_FLASH_MSPI_INT_MAP_V << CORE1_CORE1_FLASH_MSPI_INT_MAP_S)
-#define CORE1_CORE1_FLASH_MSPI_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_FLASH_MSPI_INT_MAP_S  0
-
-/** CORE1_CSI_BRIDGE_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x154)
-/** CORE1_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CSI_BRIDGE_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_M  (CORE1_CORE1_CSI_BRIDGE_INT_MAP_V << CORE1_CORE1_CSI_BRIDGE_INT_MAP_S)
-#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_S  0
-
-/** CORE1_DSI_BRIDGE_INT_MAP_REG register
- *  NA
- */
-#define CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x158)
-/** CORE1_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_DSI_BRIDGE_INT_MAP    0x0000003FU
-#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_M  (CORE1_CORE1_DSI_BRIDGE_INT_MAP_V << CORE1_CORE1_DSI_BRIDGE_INT_MAP_S)
-#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_S  0
-
-/** CORE1_CSI_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CSI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x15c)
-/** CORE1_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CSI_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CSI_INT_MAP_M  (CORE1_CORE1_CSI_INT_MAP_V << CORE1_CORE1_CSI_INT_MAP_S)
-#define CORE1_CORE1_CSI_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CSI_INT_MAP_S  0
-
-/** CORE1_DSI_INT_MAP_REG register
- *  NA
- */
-#define CORE1_DSI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x160)
-/** CORE1_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_DSI_INT_MAP    0x0000003FU
-#define CORE1_CORE1_DSI_INT_MAP_M  (CORE1_CORE1_DSI_INT_MAP_V << CORE1_CORE1_DSI_INT_MAP_S)
-#define CORE1_CORE1_DSI_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_DSI_INT_MAP_S  0
-
-/** CORE1_GMII_PHY_INT_MAP_REG register
- *  NA
- */
-#define CORE1_GMII_PHY_INT_MAP_REG (DR_REG_CORE1_BASE + 0x164)
-/** CORE1_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_GMII_PHY_INT_MAP    0x0000003FU
-#define CORE1_CORE1_GMII_PHY_INT_MAP_M  (CORE1_CORE1_GMII_PHY_INT_MAP_V << CORE1_CORE1_GMII_PHY_INT_MAP_S)
-#define CORE1_CORE1_GMII_PHY_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_GMII_PHY_INT_MAP_S  0
-
-/** CORE1_LPI_INT_MAP_REG register
- *  NA
- */
-#define CORE1_LPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x168)
-/** CORE1_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_LPI_INT_MAP    0x0000003FU
-#define CORE1_CORE1_LPI_INT_MAP_M  (CORE1_CORE1_LPI_INT_MAP_V << CORE1_CORE1_LPI_INT_MAP_S)
-#define CORE1_CORE1_LPI_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_LPI_INT_MAP_S  0
-
-/** CORE1_PMT_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PMT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x16c)
-/** CORE1_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PMT_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PMT_INT_MAP_M  (CORE1_CORE1_PMT_INT_MAP_V << CORE1_CORE1_PMT_INT_MAP_S)
-#define CORE1_CORE1_PMT_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PMT_INT_MAP_S  0
-
-/** CORE1_SBD_INT_MAP_REG register
- *  NA
- */
-#define CORE1_SBD_INT_MAP_REG (DR_REG_CORE1_BASE + 0x170)
-/** CORE1_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_SBD_INT_MAP    0x0000003FU
-#define CORE1_CORE1_SBD_INT_MAP_M  (CORE1_CORE1_SBD_INT_MAP_V << CORE1_CORE1_SBD_INT_MAP_S)
-#define CORE1_CORE1_SBD_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_SBD_INT_MAP_S  0
-
-/** CORE1_USB_OTG_INT_MAP_REG register
- *  NA
- */
-#define CORE1_USB_OTG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x174)
-/** CORE1_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_USB_OTG_INT_MAP    0x0000003FU
-#define CORE1_CORE1_USB_OTG_INT_MAP_M  (CORE1_CORE1_USB_OTG_INT_MAP_V << CORE1_CORE1_USB_OTG_INT_MAP_S)
-#define CORE1_CORE1_USB_OTG_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_USB_OTG_INT_MAP_S  0
-
-/** CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register
- *  NA
- */
-#define CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x178)
-/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003FU
-#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)
-#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
-
-/** CORE1_JPEG_INT_MAP_REG register
- *  NA
- */
-#define CORE1_JPEG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x17c)
-/** CORE1_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_JPEG_INT_MAP    0x0000003FU
-#define CORE1_CORE1_JPEG_INT_MAP_M  (CORE1_CORE1_JPEG_INT_MAP_V << CORE1_CORE1_JPEG_INT_MAP_S)
-#define CORE1_CORE1_JPEG_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_JPEG_INT_MAP_S  0
-
-/** CORE1_PPA_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PPA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x180)
-/** CORE1_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PPA_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PPA_INT_MAP_M  (CORE1_CORE1_PPA_INT_MAP_V << CORE1_CORE1_PPA_INT_MAP_S)
-#define CORE1_CORE1_PPA_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PPA_INT_MAP_S  0
-
-/** CORE1_CORE0_TRACE_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x184)
-/** CORE1_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CORE0_TRACE_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CORE0_TRACE_INT_MAP_M  (CORE1_CORE1_CORE0_TRACE_INT_MAP_V << CORE1_CORE1_CORE0_TRACE_INT_MAP_S)
-#define CORE1_CORE1_CORE0_TRACE_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CORE0_TRACE_INT_MAP_S  0
-
-/** CORE1_CORE1_TRACE_INT_MAP_REG register
- *  NA
- */
-#define CORE1_CORE1_TRACE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x188)
-/** CORE1_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_CORE1_TRACE_INT_MAP    0x0000003FU
-#define CORE1_CORE1_CORE1_TRACE_INT_MAP_M  (CORE1_CORE1_CORE1_TRACE_INT_MAP_V << CORE1_CORE1_CORE1_TRACE_INT_MAP_S)
-#define CORE1_CORE1_CORE1_TRACE_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_CORE1_TRACE_INT_MAP_S  0
-
-/** CORE1_HP_CORE_CTRL_INT_MAP_REG register
- *  NA
- */
-#define CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_CORE1_BASE + 0x18c)
-/** CORE1_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP    0x0000003FU
-#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_M  (CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V << CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S)
-#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S  0
-
-/** CORE1_ISP_INT_MAP_REG register
- *  NA
- */
-#define CORE1_ISP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x190)
-/** CORE1_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_ISP_INT_MAP    0x0000003FU
-#define CORE1_CORE1_ISP_INT_MAP_M  (CORE1_CORE1_ISP_INT_MAP_V << CORE1_CORE1_ISP_INT_MAP_S)
-#define CORE1_CORE1_ISP_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_ISP_INT_MAP_S  0
-
-/** CORE1_I3C_MST_INT_MAP_REG register
- *  NA
- */
-#define CORE1_I3C_MST_INT_MAP_REG (DR_REG_CORE1_BASE + 0x194)
-/** CORE1_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_I3C_MST_INT_MAP    0x0000003FU
-#define CORE1_CORE1_I3C_MST_INT_MAP_M  (CORE1_CORE1_I3C_MST_INT_MAP_V << CORE1_CORE1_I3C_MST_INT_MAP_S)
-#define CORE1_CORE1_I3C_MST_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_I3C_MST_INT_MAP_S  0
-
-/** CORE1_I3C_SLV_INT_MAP_REG register
- *  NA
- */
-#define CORE1_I3C_SLV_INT_MAP_REG (DR_REG_CORE1_BASE + 0x198)
-/** CORE1_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_I3C_SLV_INT_MAP    0x0000003FU
-#define CORE1_CORE1_I3C_SLV_INT_MAP_M  (CORE1_CORE1_I3C_SLV_INT_MAP_V << CORE1_CORE1_I3C_SLV_INT_MAP_S)
-#define CORE1_CORE1_I3C_SLV_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_I3C_SLV_INT_MAP_S  0
-
-/** CORE1_USB_OTG11_INT_MAP_REG register
- *  NA
- */
-#define CORE1_USB_OTG11_INT_MAP_REG (DR_REG_CORE1_BASE + 0x19c)
-/** CORE1_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_USB_OTG11_INT_MAP    0x0000003FU
-#define CORE1_CORE1_USB_OTG11_INT_MAP_M  (CORE1_CORE1_USB_OTG11_INT_MAP_V << CORE1_CORE1_USB_OTG11_INT_MAP_S)
-#define CORE1_CORE1_USB_OTG11_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_USB_OTG11_INT_MAP_S  0
-
-/** CORE1_DMA2D_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a0)
-/** CORE1_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_M  (CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S)
-#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S  0
-
-/** CORE1_DMA2D_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a4)
-/** CORE1_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_M  (CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S)
-#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S  0
-
-/** CORE1_DMA2D_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a8)
-/** CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_M  (CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S)
-#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S  0
-
-/** CORE1_DMA2D_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1ac)
-/** CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_M  (CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S)
-#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S  0
-
-/** CORE1_DMA2D_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b0)
-/** CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_M  (CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S)
-#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S  0
-
-/** CORE1_PSRAM_MSPI_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b4)
-/** CORE1_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PSRAM_MSPI_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_M  (CORE1_CORE1_PSRAM_MSPI_INT_MAP_V << CORE1_CORE1_PSRAM_MSPI_INT_MAP_S)
-#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_S  0
-
-/** CORE1_HP_SYSREG_INT_MAP_REG register
- *  NA
- */
-#define CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b8)
-/** CORE1_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_HP_SYSREG_INT_MAP    0x0000003FU
-#define CORE1_CORE1_HP_SYSREG_INT_MAP_M  (CORE1_CORE1_HP_SYSREG_INT_MAP_V << CORE1_CORE1_HP_SYSREG_INT_MAP_S)
-#define CORE1_CORE1_HP_SYSREG_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_HP_SYSREG_INT_MAP_S  0
-
-/** CORE1_PCNT_INT_MAP_REG register
- *  NA
- */
-#define CORE1_PCNT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1bc)
-/** CORE1_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_PCNT_INT_MAP    0x0000003FU
-#define CORE1_CORE1_PCNT_INT_MAP_M  (CORE1_CORE1_PCNT_INT_MAP_V << CORE1_CORE1_PCNT_INT_MAP_S)
-#define CORE1_CORE1_PCNT_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_PCNT_INT_MAP_S  0
-
-/** CORE1_HP_PAU_INT_MAP_REG register
- *  NA
- */
-#define CORE1_HP_PAU_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c0)
-/** CORE1_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_HP_PAU_INT_MAP    0x0000003FU
-#define CORE1_CORE1_HP_PAU_INT_MAP_M  (CORE1_CORE1_HP_PAU_INT_MAP_V << CORE1_CORE1_HP_PAU_INT_MAP_S)
-#define CORE1_CORE1_HP_PAU_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_HP_PAU_INT_MAP_S  0
-
-/** CORE1_HP_PARLIO_RX_INT_MAP_REG register
- *  NA
- */
-#define CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c4)
-/** CORE1_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP    0x0000003FU
-#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_M  (CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S)
-#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S  0
-
-/** CORE1_HP_PARLIO_TX_INT_MAP_REG register
- *  NA
- */
-#define CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c8)
-/** CORE1_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP    0x0000003FU
-#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_M  (CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S)
-#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1cc)
-/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d0)
-/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d4)
-/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d8)
-/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1dc)
-/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e0)
-/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e4)
-/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e8)
-/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1ec)
-/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f0)
-/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S  0
-
-/** CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f4)
-/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S)
-#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S  0
-
-/** CORE1_H264_REG_INT_MAP_REG register
- *  NA
- */
-#define CORE1_H264_REG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f8)
-/** CORE1_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_H264_REG_INT_MAP    0x0000003FU
-#define CORE1_CORE1_H264_REG_INT_MAP_M  (CORE1_CORE1_H264_REG_INT_MAP_V << CORE1_CORE1_H264_REG_INT_MAP_S)
-#define CORE1_CORE1_H264_REG_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_H264_REG_INT_MAP_S  0
-
-/** CORE1_ASSIST_DEBUG_INT_MAP_REG register
- *  NA
- */
-#define CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1fc)
-/** CORE1_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP    0x0000003FU
-#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_M  (CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V << CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S)
-#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V  0x0000003FU
-#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S  0
-
-/** CORE1_INTR_STATUS_REG_0_REG register
- *  NA
- */
-#define CORE1_INTR_STATUS_REG_0_REG (DR_REG_CORE1_BASE + 0x200)
-/** CORE1_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_INTR_STATUS_0    0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_0_M  (CORE1_CORE1_INTR_STATUS_0_V << CORE1_CORE1_INTR_STATUS_0_S)
-#define CORE1_CORE1_INTR_STATUS_0_V  0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_0_S  0
-
-/** CORE1_INTR_STATUS_REG_1_REG register
- *  NA
- */
-#define CORE1_INTR_STATUS_REG_1_REG (DR_REG_CORE1_BASE + 0x204)
-/** CORE1_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_INTR_STATUS_1    0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_1_M  (CORE1_CORE1_INTR_STATUS_1_V << CORE1_CORE1_INTR_STATUS_1_S)
-#define CORE1_CORE1_INTR_STATUS_1_V  0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_1_S  0
-
-/** CORE1_INTR_STATUS_REG_2_REG register
- *  NA
- */
-#define CORE1_INTR_STATUS_REG_2_REG (DR_REG_CORE1_BASE + 0x208)
-/** CORE1_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_INTR_STATUS_2    0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_2_M  (CORE1_CORE1_INTR_STATUS_2_V << CORE1_CORE1_INTR_STATUS_2_S)
-#define CORE1_CORE1_INTR_STATUS_2_V  0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_2_S  0
-
-/** CORE1_INTR_STATUS_REG_3_REG register
- *  NA
- */
-#define CORE1_INTR_STATUS_REG_3_REG (DR_REG_CORE1_BASE + 0x20c)
-/** CORE1_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define CORE1_CORE1_INTR_STATUS_3    0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_3_M  (CORE1_CORE1_INTR_STATUS_3_V << CORE1_CORE1_INTR_STATUS_3_S)
-#define CORE1_CORE1_INTR_STATUS_3_V  0xFFFFFFFFU
-#define CORE1_CORE1_INTR_STATUS_3_S  0
-
-/** CORE1_CLOCK_GATE_REG register
- *  NA
- */
-#define CORE1_CLOCK_GATE_REG (DR_REG_CORE1_BASE + 0x210)
-/** CORE1_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  NA
- */
-#define CORE1_CORE1_REG_CLK_EN    (BIT(0))
-#define CORE1_CORE1_REG_CLK_EN_M  (CORE1_CORE1_REG_CLK_EN_V << CORE1_CORE1_REG_CLK_EN_S)
-#define CORE1_CORE1_REG_CLK_EN_V  0x00000001U
-#define CORE1_CORE1_REG_CLK_EN_S  0
-
-/** CORE1_INTERRUPT_REG_DATE_REG register
- *  NA
- */
-#define CORE1_INTERRUPT_REG_DATE_REG (DR_REG_CORE1_BASE + 0x3fc)
-/** CORE1_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752;
- *  NA
- */
-#define CORE1_CORE1_INTERRUPT_REG_DATE    0x0FFFFFFFU
-#define CORE1_CORE1_INTERRUPT_REG_DATE_M  (CORE1_CORE1_INTERRUPT_REG_DATE_V << CORE1_CORE1_INTERRUPT_REG_DATE_S)
-#define CORE1_CORE1_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
-#define CORE1_CORE1_INTERRUPT_REG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/core1_interrupt_struct.h b/components/soc/esp32p4/include/soc/core1_interrupt_struct.h
deleted file mode 100644
index 38dbda26b3..0000000000
--- a/components/soc/esp32p4/include/soc/core1_interrupt_struct.h
+++ /dev/null
@@ -1,2298 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: CORE1 LP RTC INT MAP REG */
-/** Type of lp_rtc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_rtc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_rtc_int_map_reg_t;
-
-
-/** Group: CORE1 LP WDT INT MAP REG */
-/** Type of lp_wdt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_wdt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_wdt_int_map_reg_t;
-
-
-/** Group: CORE1 LP TIMER REG 0 INT MAP REG */
-/** Type of lp_timer_reg_0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_timer_reg_0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_timer_reg_0_int_map_reg_t;
-
-
-/** Group: CORE1 LP TIMER REG 1 INT MAP REG */
-/** Type of lp_timer_reg_1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_timer_reg_1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_timer_reg_1_int_map_reg_t;
-
-
-/** Group: CORE1 MB HP INT MAP REG */
-/** Type of mb_hp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_mb_hp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_mb_hp_int_map_reg_t;
-
-
-/** Group: CORE1 MB LP INT MAP REG */
-/** Type of mb_lp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_mb_lp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_mb_lp_int_map_reg_t;
-
-
-/** Group: CORE1 PMU REG 0 INT MAP REG */
-/** Type of pmu_reg_0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_pmu_reg_0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_pmu_reg_0_int_map_reg_t;
-
-
-/** Group: CORE1 PMU REG 1 INT MAP REG */
-/** Type of pmu_reg_1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_pmu_reg_1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_pmu_reg_1_int_map_reg_t;
-
-
-/** Group: CORE1 LP ANAPERI INT MAP REG */
-/** Type of lp_anaperi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_anaperi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_anaperi_int_map_reg_t;
-
-
-/** Group: CORE1 LP ADC INT MAP REG */
-/** Type of lp_adc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_adc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_adc_int_map_reg_t;
-
-
-/** Group: CORE1 LP GPIO INT MAP REG */
-/** Type of lp_gpio_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_gpio_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_gpio_int_map_reg_t;
-
-
-/** Group: CORE1 LP I2C INT MAP REG */
-/** Type of lp_i2c_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_i2c_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_i2c_int_map_reg_t;
-
-
-/** Group: CORE1 LP I2S INT MAP REG */
-/** Type of lp_i2s_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_i2s_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_i2s_int_map_reg_t;
-
-
-/** Group: CORE1 LP SPI INT MAP REG */
-/** Type of lp_spi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_spi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_spi_int_map_reg_t;
-
-
-/** Group: CORE1 LP TOUCH INT MAP REG */
-/** Type of lp_touch_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_touch_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_touch_int_map_reg_t;
-
-
-/** Group: CORE1 LP TSENS INT MAP REG */
-/** Type of lp_tsens_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_tsens_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_tsens_int_map_reg_t;
-
-
-/** Group: CORE1 LP UART INT MAP REG */
-/** Type of lp_uart_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_uart_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_uart_int_map_reg_t;
-
-
-/** Group: CORE1 LP EFUSE INT MAP REG */
-/** Type of lp_efuse_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_efuse_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_efuse_int_map_reg_t;
-
-
-/** Group: CORE1 LP SW INT MAP REG */
-/** Type of lp_sw_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_sw_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_sw_int_map_reg_t;
-
-
-/** Group: CORE1 LP SYSREG INT MAP REG */
-/** Type of lp_sysreg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_sysreg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_sysreg_int_map_reg_t;
-
-
-/** Group: CORE1 LP HUK INT MAP REG */
-/** Type of lp_huk_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lp_huk_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lp_huk_int_map_reg_t;
-
-
-/** Group: CORE1 SYS ICM INT MAP REG */
-/** Type of sys_icm_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_sys_icm_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_sys_icm_int_map_reg_t;
-
-
-/** Group: CORE1 USB DEVICE INT MAP REG */
-/** Type of usb_device_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_usb_device_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_usb_device_int_map_reg_t;
-
-
-/** Group: CORE1 SDIO HOST INT MAP REG */
-/** Type of sdio_host_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_sdio_host_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_sdio_host_int_map_reg_t;
-
-
-/** Group: CORE1 GDMA INT MAP REG */
-/** Type of gdma_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_gdma_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_gdma_int_map_reg_t;
-
-
-/** Group: CORE1 SPI2 INT MAP REG */
-/** Type of spi2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_spi2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_spi2_int_map_reg_t;
-
-
-/** Group: CORE1 SPI3 INT MAP REG */
-/** Type of spi3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_spi3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_spi3_int_map_reg_t;
-
-
-/** Group: CORE1 I2S0 INT MAP REG */
-/** Type of i2s0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_i2s0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_i2s0_int_map_reg_t;
-
-
-/** Group: CORE1 I2S1 INT MAP REG */
-/** Type of i2s1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_i2s1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_i2s1_int_map_reg_t;
-
-
-/** Group: CORE1 I2S2 INT MAP REG */
-/** Type of i2s2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_i2s2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_i2s2_int_map_reg_t;
-
-
-/** Group: CORE1 UHCI0 INT MAP REG */
-/** Type of uhci0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_uhci0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_uhci0_int_map_reg_t;
-
-
-/** Group: CORE1 UART0 INT MAP REG */
-/** Type of uart0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_uart0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_uart0_int_map_reg_t;
-
-
-/** Group: CORE1 UART1 INT MAP REG */
-/** Type of uart1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_uart1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_uart1_int_map_reg_t;
-
-
-/** Group: CORE1 UART2 INT MAP REG */
-/** Type of uart2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_uart2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_uart2_int_map_reg_t;
-
-
-/** Group: CORE1 UART3 INT MAP REG */
-/** Type of uart3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_uart3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_uart3_int_map_reg_t;
-
-
-/** Group: CORE1 UART4 INT MAP REG */
-/** Type of uart4_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_uart4_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_uart4_int_map_reg_t;
-
-
-/** Group: CORE1 LCD CAM INT MAP REG */
-/** Type of lcd_cam_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lcd_cam_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lcd_cam_int_map_reg_t;
-
-
-/** Group: CORE1 ADC INT MAP REG */
-/** Type of adc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_adc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_adc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_adc_int_map_reg_t;
-
-
-/** Group: CORE1 PWM0 INT MAP REG */
-/** Type of pwm0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_pwm0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_pwm0_int_map_reg_t;
-
-
-/** Group: CORE1 PWM1 INT MAP REG */
-/** Type of pwm1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_pwm1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_pwm1_int_map_reg_t;
-
-
-/** Group: CORE1 CAN0 INT MAP REG */
-/** Type of can0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_can0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_can0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_can0_int_map_reg_t;
-
-
-/** Group: CORE1 CAN1 INT MAP REG */
-/** Type of can1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_can1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_can1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_can1_int_map_reg_t;
-
-
-/** Group: CORE1 CAN2 INT MAP REG */
-/** Type of can2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_can2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_can2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_can2_int_map_reg_t;
-
-
-/** Group: CORE1 RMT INT MAP REG */
-/** Type of rmt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_rmt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_rmt_int_map_reg_t;
-
-
-/** Group: CORE1 I2C0 INT MAP REG */
-/** Type of i2c0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_i2c0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_i2c0_int_map_reg_t;
-
-
-/** Group: CORE1 I2C1 INT MAP REG */
-/** Type of i2c1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_i2c1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_i2c1_int_map_reg_t;
-
-
-/** Group: CORE1 TIMERGRP0 T0 INT MAP REG */
-/** Type of timergrp0_t0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_timergrp0_t0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_timergrp0_t0_int_map_reg_t;
-
-
-/** Group: CORE1 TIMERGRP0 T1 INT MAP REG */
-/** Type of timergrp0_t1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_timergrp0_t1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_timergrp0_t1_int_map_reg_t;
-
-
-/** Group: CORE1 TIMERGRP0 WDT INT MAP REG */
-/** Type of timergrp0_wdt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_timergrp0_wdt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_timergrp0_wdt_int_map_reg_t;
-
-
-/** Group: CORE1 TIMERGRP1 T0 INT MAP REG */
-/** Type of timergrp1_t0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_timergrp1_t0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_timergrp1_t0_int_map_reg_t;
-
-
-/** Group: CORE1 TIMERGRP1 T1 INT MAP REG */
-/** Type of timergrp1_t1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_timergrp1_t1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_timergrp1_t1_int_map_reg_t;
-
-
-/** Group: CORE1 TIMERGRP1 WDT INT MAP REG */
-/** Type of timergrp1_wdt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_timergrp1_wdt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_timergrp1_wdt_int_map_reg_t;
-
-
-/** Group: CORE1 LEDC INT MAP REG */
-/** Type of ledc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ledc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ledc_int_map_reg_t;
-
-
-/** Group: CORE1 SYSTIMER TARGET0 INT MAP REG */
-/** Type of systimer_target0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_systimer_target0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_systimer_target0_int_map_reg_t;
-
-
-/** Group: CORE1 SYSTIMER TARGET1 INT MAP REG */
-/** Type of systimer_target1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_systimer_target1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_systimer_target1_int_map_reg_t;
-
-
-/** Group: CORE1 SYSTIMER TARGET2 INT MAP REG */
-/** Type of systimer_target2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_systimer_target2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_systimer_target2_int_map_reg_t;
-
-
-/** Group: CORE1 AHB PDMA IN CH0 INT MAP REG */
-/** Type of ahb_pdma_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ahb_pdma_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ahb_pdma_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 AHB PDMA IN CH1 INT MAP REG */
-/** Type of ahb_pdma_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ahb_pdma_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ahb_pdma_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 AHB PDMA IN CH2 INT MAP REG */
-/** Type of ahb_pdma_in_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ahb_pdma_in_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ahb_pdma_in_ch2_int_map_reg_t;
-
-
-/** Group: CORE1 AHB PDMA OUT CH0 INT MAP REG */
-/** Type of ahb_pdma_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ahb_pdma_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ahb_pdma_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 AHB PDMA OUT CH1 INT MAP REG */
-/** Type of ahb_pdma_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ahb_pdma_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ahb_pdma_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 AHB PDMA OUT CH2 INT MAP REG */
-/** Type of ahb_pdma_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ahb_pdma_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ahb_pdma_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE1 AXI PDMA IN CH0 INT MAP REG */
-/** Type of axi_pdma_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_axi_pdma_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_axi_pdma_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 AXI PDMA IN CH1 INT MAP REG */
-/** Type of axi_pdma_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_axi_pdma_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_axi_pdma_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 AXI PDMA IN CH2 INT MAP REG */
-/** Type of axi_pdma_in_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_axi_pdma_in_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_axi_pdma_in_ch2_int_map_reg_t;
-
-
-/** Group: CORE1 AXI PDMA OUT CH0 INT MAP REG */
-/** Type of axi_pdma_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_axi_pdma_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_axi_pdma_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 AXI PDMA OUT CH1 INT MAP REG */
-/** Type of axi_pdma_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_axi_pdma_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_axi_pdma_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 AXI PDMA OUT CH2 INT MAP REG */
-/** Type of axi_pdma_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_axi_pdma_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_axi_pdma_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE1 RSA INT MAP REG */
-/** Type of rsa_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_rsa_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_rsa_int_map_reg_t;
-
-
-/** Group: CORE1 AES INT MAP REG */
-/** Type of aes_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_aes_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_aes_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_aes_int_map_reg_t;
-
-
-/** Group: CORE1 SHA INT MAP REG */
-/** Type of sha_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_sha_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_sha_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_sha_int_map_reg_t;
-
-
-/** Group: CORE1 ECC INT MAP REG */
-/** Type of ecc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ecc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ecc_int_map_reg_t;
-
-
-/** Group: CORE1 ECDSA INT MAP REG */
-/** Type of ecdsa_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ecdsa_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ecdsa_int_map_reg_t;
-
-
-/** Group: CORE1 KM INT MAP REG */
-/** Type of km_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_km_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_km_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_km_int_map_reg_t;
-
-
-/** Group: CORE1 GPIO INT0 MAP REG */
-/** Type of gpio_int0_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_gpio_int0_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_gpio_int0_map_reg_t;
-
-
-/** Group: CORE1 GPIO INT1 MAP REG */
-/** Type of gpio_int1_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_gpio_int1_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_gpio_int1_map_reg_t;
-
-
-/** Group: CORE1 GPIO INT2 MAP REG */
-/** Type of gpio_int2_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_gpio_int2_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_gpio_int2_map_reg_t;
-
-
-/** Group: CORE1 GPIO INT3 MAP REG */
-/** Type of gpio_int3_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_gpio_int3_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_gpio_int3_map_reg_t;
-
-
-/** Group: CORE1 GPIO PAD COMP INT MAP REG */
-/** Type of gpio_pad_comp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_gpio_pad_comp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_gpio_pad_comp_int_map_reg_t;
-
-
-/** Group: CORE1 CPU INT FROM CPU 0 MAP REG */
-/** Type of cpu_int_from_cpu_0_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_cpu_int_from_cpu_0_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_cpu_int_from_cpu_0_map_reg_t;
-
-
-/** Group: CORE1 CPU INT FROM CPU 1 MAP REG */
-/** Type of cpu_int_from_cpu_1_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_cpu_int_from_cpu_1_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_cpu_int_from_cpu_1_map_reg_t;
-
-
-/** Group: CORE1 CPU INT FROM CPU 2 MAP REG */
-/** Type of cpu_int_from_cpu_2_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_cpu_int_from_cpu_2_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_cpu_int_from_cpu_2_map_reg_t;
-
-
-/** Group: CORE1 CPU INT FROM CPU 3 MAP REG */
-/** Type of cpu_int_from_cpu_3_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_cpu_int_from_cpu_3_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_cpu_int_from_cpu_3_map_reg_t;
-
-
-/** Group: CORE1 CACHE INT MAP REG */
-/** Type of cache_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_cache_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_cache_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_cache_int_map_reg_t;
-
-
-/** Group: CORE1 FLASH MSPI INT MAP REG */
-/** Type of flash_mspi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_flash_mspi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_flash_mspi_int_map_reg_t;
-
-
-/** Group: CORE1 CSI BRIDGE INT MAP REG */
-/** Type of csi_bridge_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_csi_bridge_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_csi_bridge_int_map_reg_t;
-
-
-/** Group: CORE1 DSI BRIDGE INT MAP REG */
-/** Type of dsi_bridge_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_dsi_bridge_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_dsi_bridge_int_map_reg_t;
-
-
-/** Group: CORE1 CSI INT MAP REG */
-/** Type of csi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_csi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_csi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_csi_int_map_reg_t;
-
-
-/** Group: CORE1 DSI INT MAP REG */
-/** Type of dsi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_dsi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_dsi_int_map_reg_t;
-
-
-/** Group: CORE1 GMII PHY INT MAP REG */
-/** Type of gmii_phy_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_gmii_phy_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_gmii_phy_int_map_reg_t;
-
-
-/** Group: CORE1 LPI INT MAP REG */
-/** Type of lpi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_lpi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_lpi_int_map_reg_t;
-
-
-/** Group: CORE1 PMT INT MAP REG */
-/** Type of pmt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_pmt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_pmt_int_map_reg_t;
-
-
-/** Group: CORE1 SBD INT MAP REG */
-/** Type of sbd_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_sbd_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_sbd_int_map_reg_t;
-
-
-/** Group: CORE1 USB OTG INT MAP REG */
-/** Type of usb_otg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_usb_otg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_usb_otg_int_map_reg_t;
-
-
-/** Group: CORE1 USB OTG ENDP MULTI PROC INT MAP REG */
-/** Type of usb_otg_endp_multi_proc_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_usb_otg_endp_multi_proc_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_usb_otg_endp_multi_proc_int_map_reg_t;
-
-
-/** Group: CORE1 JPEG INT MAP REG */
-/** Type of jpeg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_jpeg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_jpeg_int_map_reg_t;
-
-
-/** Group: CORE1 PPA INT MAP REG */
-/** Type of ppa_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_ppa_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_ppa_int_map_reg_t;
-
-
-/** Group: CORE1 CORE0 TRACE INT MAP REG */
-/** Type of core0_trace_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_core0_trace_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_core0_trace_int_map_reg_t;
-
-
-/** Group: CORE1 CORE1 TRACE INT MAP REG */
-/** Type of core1_trace_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_core1_trace_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_core1_trace_int_map_reg_t;
-
-
-/** Group: CORE1 HP CORE CTRL INT MAP REG */
-/** Type of hp_core_ctrl_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_hp_core_ctrl_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_hp_core_ctrl_int_map_reg_t;
-
-
-/** Group: CORE1 ISP INT MAP REG */
-/** Type of isp_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_isp_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_isp_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_isp_int_map_reg_t;
-
-
-/** Group: CORE1 I3C MST INT MAP REG */
-/** Type of i3c_mst_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_i3c_mst_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_i3c_mst_int_map_reg_t;
-
-
-/** Group: CORE1 I3C SLV INT MAP REG */
-/** Type of i3c_slv_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_i3c_slv_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_i3c_slv_int_map_reg_t;
-
-
-/** Group: CORE1 USB OTG11 INT MAP REG */
-/** Type of usb_otg11_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_usb_otg11_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_usb_otg11_int_map_reg_t;
-
-
-/** Group: CORE1 DMA2D IN CH0 INT MAP REG */
-/** Type of dma2d_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_dma2d_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_dma2d_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 DMA2D IN CH1 INT MAP REG */
-/** Type of dma2d_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_dma2d_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_dma2d_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 DMA2D OUT CH0 INT MAP REG */
-/** Type of dma2d_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_dma2d_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_dma2d_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 DMA2D OUT CH1 INT MAP REG */
-/** Type of dma2d_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_dma2d_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_dma2d_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 DMA2D OUT CH2 INT MAP REG */
-/** Type of dma2d_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_dma2d_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_dma2d_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE1 PSRAM MSPI INT MAP REG */
-/** Type of psram_mspi_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_psram_mspi_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_psram_mspi_int_map_reg_t;
-
-
-/** Group: CORE1 HP SYSREG INT MAP REG */
-/** Type of hp_sysreg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_hp_sysreg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_hp_sysreg_int_map_reg_t;
-
-
-/** Group: CORE1 PCNT INT MAP REG */
-/** Type of pcnt_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_pcnt_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_pcnt_int_map_reg_t;
-
-
-/** Group: CORE1 HP PAU INT MAP REG */
-/** Type of hp_pau_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_hp_pau_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_hp_pau_int_map_reg_t;
-
-
-/** Group: CORE1 HP PARLIO RX INT MAP REG */
-/** Type of hp_parlio_rx_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_hp_parlio_rx_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_hp_parlio_rx_int_map_reg_t;
-
-
-/** Group: CORE1 HP PARLIO TX INT MAP REG */
-/** Type of hp_parlio_tx_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_hp_parlio_tx_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_hp_parlio_tx_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D OUT CH0 INT MAP REG */
-/** Type of h264_dma2d_out_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_out_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_out_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D OUT CH1 INT MAP REG */
-/** Type of h264_dma2d_out_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_out_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_out_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D OUT CH2 INT MAP REG */
-/** Type of h264_dma2d_out_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_out_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_out_ch2_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D OUT CH3 INT MAP REG */
-/** Type of h264_dma2d_out_ch3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_out_ch3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_out_ch3_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D OUT CH4 INT MAP REG */
-/** Type of h264_dma2d_out_ch4_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_out_ch4_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_out_ch4_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D IN CH0 INT MAP REG */
-/** Type of h264_dma2d_in_ch0_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_in_ch0_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_in_ch0_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D IN CH1 INT MAP REG */
-/** Type of h264_dma2d_in_ch1_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_in_ch1_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_in_ch1_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D IN CH2 INT MAP REG */
-/** Type of h264_dma2d_in_ch2_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_in_ch2_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_in_ch2_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D IN CH3 INT MAP REG */
-/** Type of h264_dma2d_in_ch3_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_in_ch3_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_in_ch3_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D IN CH4 INT MAP REG */
-/** Type of h264_dma2d_in_ch4_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_in_ch4_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_in_ch4_int_map_reg_t;
-
-
-/** Group: CORE1 H264 DMA2D IN CH5 INT MAP REG */
-/** Type of h264_dma2d_in_ch5_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_dma2d_in_ch5_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_dma2d_in_ch5_int_map_reg_t;
-
-
-/** Group: CORE1 H264 REG INT MAP REG */
-/** Type of h264_reg_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_h264_reg_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_h264_reg_int_map_reg_t;
-
-
-/** Group: CORE1 ASSIST DEBUG INT MAP REG */
-/** Type of assist_debug_int_map register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_assist_debug_int_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} core1_assist_debug_int_map_reg_t;
-
-
-/** Group: CORE1 INTR STATUS REG 0 REG */
-/** Type of intr_status_reg_0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_intr_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_intr_status_0:32;
-    };
-    uint32_t val;
-} core1_intr_status_reg_0_reg_t;
-
-
-/** Group: CORE1 INTR STATUS REG 1 REG */
-/** Type of intr_status_reg_1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_intr_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_intr_status_1:32;
-    };
-    uint32_t val;
-} core1_intr_status_reg_1_reg_t;
-
-
-/** Group: CORE1 INTR STATUS REG 2 REG */
-/** Type of intr_status_reg_2 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_intr_status_2 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_intr_status_2:32;
-    };
-    uint32_t val;
-} core1_intr_status_reg_2_reg_t;
-
-
-/** Group: CORE1 INTR STATUS REG 3 REG */
-/** Type of intr_status_reg_3 register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_intr_status_3 : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t core1_intr_status_3:32;
-    };
-    uint32_t val;
-} core1_intr_status_reg_3_reg_t;
-
-
-/** Group: CORE1 CLOCK GATE REG */
-/** Type of clock_gate register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t core1_reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} core1_clock_gate_reg_t;
-
-
-/** Group: CORE1 INTERRUPT REG DATE REG */
-/** Type of interrupt_reg_date register
- *  NA
- */
-typedef union {
-    struct {
-        /** core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752;
-         *  NA
-         */
-        uint32_t core1_interrupt_reg_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} core1_interrupt_reg_date_reg_t;
-
-
-typedef struct {
-    volatile core1_lp_rtc_int_map_reg_t lp_rtc_int_map;
-    volatile core1_lp_wdt_int_map_reg_t lp_wdt_int_map;
-    volatile core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map;
-    volatile core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map;
-    volatile core1_mb_hp_int_map_reg_t mb_hp_int_map;
-    volatile core1_mb_lp_int_map_reg_t mb_lp_int_map;
-    volatile core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map;
-    volatile core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map;
-    volatile core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map;
-    volatile core1_lp_adc_int_map_reg_t lp_adc_int_map;
-    volatile core1_lp_gpio_int_map_reg_t lp_gpio_int_map;
-    volatile core1_lp_i2c_int_map_reg_t lp_i2c_int_map;
-    volatile core1_lp_i2s_int_map_reg_t lp_i2s_int_map;
-    volatile core1_lp_spi_int_map_reg_t lp_spi_int_map;
-    volatile core1_lp_touch_int_map_reg_t lp_touch_int_map;
-    volatile core1_lp_tsens_int_map_reg_t lp_tsens_int_map;
-    volatile core1_lp_uart_int_map_reg_t lp_uart_int_map;
-    volatile core1_lp_efuse_int_map_reg_t lp_efuse_int_map;
-    volatile core1_lp_sw_int_map_reg_t lp_sw_int_map;
-    volatile core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map;
-    volatile core1_lp_huk_int_map_reg_t lp_huk_int_map;
-    volatile core1_sys_icm_int_map_reg_t sys_icm_int_map;
-    volatile core1_usb_device_int_map_reg_t usb_device_int_map;
-    volatile core1_sdio_host_int_map_reg_t sdio_host_int_map;
-    volatile core1_gdma_int_map_reg_t gdma_int_map;
-    volatile core1_spi2_int_map_reg_t spi2_int_map;
-    volatile core1_spi3_int_map_reg_t spi3_int_map;
-    volatile core1_i2s0_int_map_reg_t i2s0_int_map;
-    volatile core1_i2s1_int_map_reg_t i2s1_int_map;
-    volatile core1_i2s2_int_map_reg_t i2s2_int_map;
-    volatile core1_uhci0_int_map_reg_t uhci0_int_map;
-    volatile core1_uart0_int_map_reg_t uart0_int_map;
-    volatile core1_uart1_int_map_reg_t uart1_int_map;
-    volatile core1_uart2_int_map_reg_t uart2_int_map;
-    volatile core1_uart3_int_map_reg_t uart3_int_map;
-    volatile core1_uart4_int_map_reg_t uart4_int_map;
-    volatile core1_lcd_cam_int_map_reg_t lcd_cam_int_map;
-    volatile core1_adc_int_map_reg_t adc_int_map;
-    volatile core1_pwm0_int_map_reg_t pwm0_int_map;
-    volatile core1_pwm1_int_map_reg_t pwm1_int_map;
-    volatile core1_can0_int_map_reg_t can0_int_map;
-    volatile core1_can1_int_map_reg_t can1_int_map;
-    volatile core1_can2_int_map_reg_t can2_int_map;
-    volatile core1_rmt_int_map_reg_t rmt_int_map;
-    volatile core1_i2c0_int_map_reg_t i2c0_int_map;
-    volatile core1_i2c1_int_map_reg_t i2c1_int_map;
-    volatile core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map;
-    volatile core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map;
-    volatile core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map;
-    volatile core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map;
-    volatile core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map;
-    volatile core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map;
-    volatile core1_ledc_int_map_reg_t ledc_int_map;
-    volatile core1_systimer_target0_int_map_reg_t systimer_target0_int_map;
-    volatile core1_systimer_target1_int_map_reg_t systimer_target1_int_map;
-    volatile core1_systimer_target2_int_map_reg_t systimer_target2_int_map;
-    volatile core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map;
-    volatile core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map;
-    volatile core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map;
-    volatile core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map;
-    volatile core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map;
-    volatile core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map;
-    volatile core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map;
-    volatile core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map;
-    volatile core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map;
-    volatile core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map;
-    volatile core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map;
-    volatile core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map;
-    volatile core1_rsa_int_map_reg_t rsa_int_map;
-    volatile core1_aes_int_map_reg_t aes_int_map;
-    volatile core1_sha_int_map_reg_t sha_int_map;
-    volatile core1_ecc_int_map_reg_t ecc_int_map;
-    volatile core1_ecdsa_int_map_reg_t ecdsa_int_map;
-    volatile core1_km_int_map_reg_t km_int_map;
-    volatile core1_gpio_int0_map_reg_t gpio_int0_map;
-    volatile core1_gpio_int1_map_reg_t gpio_int1_map;
-    volatile core1_gpio_int2_map_reg_t gpio_int2_map;
-    volatile core1_gpio_int3_map_reg_t gpio_int3_map;
-    volatile core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map;
-    volatile core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map;
-    volatile core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map;
-    volatile core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map;
-    volatile core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map;
-    volatile core1_cache_int_map_reg_t cache_int_map;
-    volatile core1_flash_mspi_int_map_reg_t flash_mspi_int_map;
-    volatile core1_csi_bridge_int_map_reg_t csi_bridge_int_map;
-    volatile core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map;
-    volatile core1_csi_int_map_reg_t csi_int_map;
-    volatile core1_dsi_int_map_reg_t dsi_int_map;
-    volatile core1_gmii_phy_int_map_reg_t gmii_phy_int_map;
-    volatile core1_lpi_int_map_reg_t lpi_int_map;
-    volatile core1_pmt_int_map_reg_t pmt_int_map;
-    volatile core1_sbd_int_map_reg_t sbd_int_map;
-    volatile core1_usb_otg_int_map_reg_t usb_otg_int_map;
-    volatile core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map;
-    volatile core1_jpeg_int_map_reg_t jpeg_int_map;
-    volatile core1_ppa_int_map_reg_t ppa_int_map;
-    volatile core1_core0_trace_int_map_reg_t core0_trace_int_map;
-    volatile core1_core1_trace_int_map_reg_t core1_trace_int_map;
-    volatile core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map;
-    volatile core1_isp_int_map_reg_t isp_int_map;
-    volatile core1_i3c_mst_int_map_reg_t i3c_mst_int_map;
-    volatile core1_i3c_slv_int_map_reg_t i3c_slv_int_map;
-    volatile core1_usb_otg11_int_map_reg_t usb_otg11_int_map;
-    volatile core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map;
-    volatile core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map;
-    volatile core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map;
-    volatile core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map;
-    volatile core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map;
-    volatile core1_psram_mspi_int_map_reg_t psram_mspi_int_map;
-    volatile core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map;
-    volatile core1_pcnt_int_map_reg_t pcnt_int_map;
-    volatile core1_hp_pau_int_map_reg_t hp_pau_int_map;
-    volatile core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map;
-    volatile core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map;
-    volatile core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map;
-    volatile core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map;
-    volatile core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map;
-    volatile core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map;
-    volatile core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map;
-    volatile core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map;
-    volatile core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map;
-    volatile core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map;
-    volatile core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map;
-    volatile core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map;
-    volatile core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map;
-    volatile core1_h264_reg_int_map_reg_t h264_reg_int_map;
-    volatile core1_assist_debug_int_map_reg_t assist_debug_int_map;
-    volatile core1_intr_status_reg_0_reg_t intr_status_reg_0;
-    volatile core1_intr_status_reg_1_reg_t intr_status_reg_1;
-    volatile core1_intr_status_reg_2_reg_t intr_status_reg_2;
-    volatile core1_intr_status_reg_3_reg_t intr_status_reg_3;
-    volatile core1_clock_gate_reg_t clock_gate;
-    uint32_t reserved_214[122];
-    volatile core1_interrupt_reg_date_reg_t interrupt_reg_date;
-} core1_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(core1_dev_t) == 0x400, "Invalid size of core1_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/extmem_reg.h b/components/soc/esp32p4/include/soc/extmem_reg.h
deleted file mode 100644
index a9cb693586..0000000000
--- a/components/soc/esp32p4/include/soc/extmem_reg.h
+++ /dev/null
@@ -1,871 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define EXTMEM_L1_CACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x4)
-/* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
-#define EXTMEM_L1_CACHE_SHUT_DBUS    (BIT(1))
-#define EXTMEM_L1_CACHE_SHUT_DBUS_M  (BIT(1))
-#define EXTMEM_L1_CACHE_SHUT_DBUS_V  0x1
-#define EXTMEM_L1_CACHE_SHUT_DBUS_S  1
-/* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
-#define EXTMEM_L1_CACHE_SHUT_IBUS    (BIT(0))
-#define EXTMEM_L1_CACHE_SHUT_IBUS_M  (BIT(0))
-#define EXTMEM_L1_CACHE_SHUT_IBUS_V  0x1
-#define EXTMEM_L1_CACHE_SHUT_IBUS_S  0
-
-#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x20)
-/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
-#define EXTMEM_L1_CACHE_WRAP    (BIT(4))
-#define EXTMEM_L1_CACHE_WRAP_M  (BIT(4))
-#define EXTMEM_L1_CACHE_WRAP_V  0x1
-#define EXTMEM_L1_CACHE_WRAP_S  4
-
-#define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x24)
-/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
-/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M  (BIT(18))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S  18
-/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power
-down.*/
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M  (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S  17
-/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating,
-0: open clock gating..*/
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M  (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S  16
-
-#define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x28)
-/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
-/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u
-p.*/
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M  (BIT(18))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S  18
-/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
- down.*/
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M  (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S  17
-/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to close clock gating of  L1-Cache data memory. 1: close gating,
- 0: open clock gating..*/
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M  (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S  16
-
-#define EXTMEM_L1_CACHE_FREEZE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x2C)
-/* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
-/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or
-not. 0: not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_FREEZE_DONE    (BIT(18))
-#define EXTMEM_L1_CACHE_FREEZE_DONE_M  (BIT(18))
-#define EXTMEM_L1_CACHE_FREEZE_DONE_V  0x1
-#define EXTMEM_L1_CACHE_FREEZE_DONE_S  18
-/* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
- will not stuck. 1: a miss-access will stuck..*/
-#define EXTMEM_L1_CACHE_FREEZE_MODE    (BIT(17))
-#define EXTMEM_L1_CACHE_FREEZE_MODE_M  (BIT(17))
-#define EXTMEM_L1_CACHE_FREEZE_MODE_V  0x1
-#define EXTMEM_L1_CACHE_FREEZE_MODE_S  17
-/* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof
-tware..*/
-#define EXTMEM_L1_CACHE_FREEZE_EN    (BIT(16))
-#define EXTMEM_L1_CACHE_FREEZE_EN_M  (BIT(16))
-#define EXTMEM_L1_CACHE_FREEZE_EN_V  0x1
-#define EXTMEM_L1_CACHE_FREEZE_EN_S  16
-
-#define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x30)
-/* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable,
-1: enable..*/
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M  (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S  17
-/* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1
-: enable..*/
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M  (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S  16
-
-#define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x34)
-/* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1
-: enable..*/
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M  (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S  17
-/* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
- enable..*/
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M  (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S  16
-
-#define EXTMEM_L1_CACHE_PRELOCK_CONF_REG          (DR_REG_EXTMEM_BASE + 0x78)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M  (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V  0x1
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S  1
-/* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M  (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V  0x1
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S  0
-
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x7C)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the first section
-of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0
-_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x80)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the second section
- of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT
-1_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x84)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
-/*description: Those bits are used to configure the size of the second section of prelock on L1
--Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x3FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
-/* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
-/*description: Those bits are used to configure the size of the first section of prelock on L1-
-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x3FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x88)
-/* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
- not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_LOCK_DONE    (BIT(2))
-#define EXTMEM_L1_CACHE_LOCK_DONE_M  (BIT(2))
-#define EXTMEM_L1_CACHE_LOCK_DONE_V  0x1
-#define EXTMEM_L1_CACHE_LOCK_DONE_S  2
-/* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
- unlock operation done.*/
-#define EXTMEM_L1_CACHE_UNLOCK_ENA    (BIT(1))
-#define EXTMEM_L1_CACHE_UNLOCK_ENA_M  (BIT(1))
-#define EXTMEM_L1_CACHE_UNLOCK_ENA_V  0x1
-#define EXTMEM_L1_CACHE_UNLOCK_ENA_S  1
-/* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
-ock operation done.*/
-#define EXTMEM_L1_CACHE_LOCK_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_LOCK_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_LOCK_ENA_V  0x1
-#define EXTMEM_L1_CACHE_LOCK_ENA_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_MAP_REG          (DR_REG_EXTMEM_BASE + 0x8C)
-/* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: Those bits are used to indicate which caches in the two-level cache structure wi
-ll apply this lock/unlock operation. [4]: L1-Cache.*/
-#define EXTMEM_L1_CACHE_LOCK_MAP    0x0000003F
-#define EXTMEM_L1_CACHE_LOCK_MAP_M  ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S))
-#define EXTMEM_L1_CACHE_LOCK_MAP_V  0x3F
-#define EXTMEM_L1_CACHE_LOCK_MAP_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x90)
-/* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the lock/unlock op
-eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_LOCK_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_LOCK_ADDR_M  ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S))
-#define EXTMEM_L1_CACHE_LOCK_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_LOCK_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x94)
-/* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
-ould be used together with CACHE_LOCK_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_LOCK_SIZE    0x0000FFFF
-#define EXTMEM_L1_CACHE_LOCK_SIZE_M  ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S))
-#define EXTMEM_L1_CACHE_LOCK_SIZE_V  0xFFFF
-#define EXTMEM_L1_CACHE_LOCK_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x98)
-/* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
-, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE    (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_DONE_M  (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_DONE_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_S  4
-/* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
-/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
-hardware after writeback-invalidate operation done. Note that this bit and the o
-ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
-, that is, those bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V  0x1
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S  3
-/* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
-ter writeback operation done. Note that this bit and the other sync-bits (invali
-date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
-those bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA    (BIT(2))
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA_M  (BIT(2))
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA_V  0x1
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA_S  2
-/* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable clean operation. It will be cleared by hardware after
-clean operation done. Note that this bit and the other sync-bits (invalidate_ena
-, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
-e bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_CLEAN_ENA    (BIT(1))
-#define EXTMEM_L1_CACHE_CLEAN_ENA_M  (BIT(1))
-#define EXTMEM_L1_CACHE_CLEAN_ENA_V  0x1
-#define EXTMEM_L1_CACHE_CLEAN_ENA_S  1
-/* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
-/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done. Note that this bit and the other sync-bits (clea
-n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
- those bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA_V  0x1
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_MAP_REG          (DR_REG_EXTMEM_BASE + 0x9C)
-/* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
-/*description: Those bits are used to indicate which caches in the two-level cache structure wi
-ll apply the sync operation.  [4]: L1-Cache.*/
-#define EXTMEM_L1_CACHE_SYNC_MAP    0x0000003F
-#define EXTMEM_L1_CACHE_SYNC_MAP_M  ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S))
-#define EXTMEM_L1_CACHE_SYNC_MAP_V  0x3F
-#define EXTMEM_L1_CACHE_SYNC_MAP_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xA0)
-/* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the sync operation
-, which should be used together with CACHE_SYNC_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_SYNC_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_SYNC_ADDR_M  ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S))
-#define EXTMEM_L1_CACHE_SYNC_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_SYNC_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xA4)
-/* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Those bits are used to configure the size of the sync operation, which should be
- used together with CACHE_SYNC_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_SYNC_SIZE    0x00FFFFFF
-#define EXTMEM_L1_CACHE_SYNC_SIZE_M  ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S))
-#define EXTMEM_L1_CACHE_SYNC_SIZE_V  0xFFFFFF
-#define EXTMEM_L1_CACHE_SYNC_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xD8)
-/* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
-/*description: The bit is used to set  the gid of l1 cache preload..*/
-#define EXTMEM_L1_CACHE_PRELOAD_RGID    0x0000000F
-#define EXTMEM_L1_CACHE_PRELOAD_RGID_M  ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S))
-#define EXTMEM_L1_CACHE_PRELOAD_RGID_V  0xF
-#define EXTMEM_L1_CACHE_PRELOAD_RGID_S  3
-/* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
-: descending..*/
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER    (BIT(2))
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER_M  (BIT(2))
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER_V  0x1
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER_S  2
-/* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
- finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_PRELOAD_DONE    (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOAD_DONE_M  (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOAD_DONE_V  0x1
-#define EXTMEM_L1_CACHE_PRELOAD_DONE_S  1
-/* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h
-ardware automatically after preload operation is done..*/
-#define EXTMEM_L1_CACHE_PRELOAD_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOAD_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOAD_ENA_V  0x1
-#define EXTMEM_L1_CACHE_PRELOAD_ENA_S  0
-
-#define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xDC)
-/* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of preload on L1-Cach
-e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR_M  ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S))
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR_S  0
-
-#define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xE0)
-/* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: Those bits are used to configure the size of the first section of prelock on L1-
-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE    0x00003FFF
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE_M  ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S))
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE_V  0x3FFF
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x134)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0
-/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x3
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0:
- ascending. 1: descending..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M  (BIT(2))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S  2
-/* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o
-r not. 0: not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M  (BIT(1))
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S  1
-/* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable and disable autoload operation on L1-Cache.  1: enable
-, 0: disable..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x138)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the first section
-for autoload operation on L1-Cache. Note that it should be used together with L1
-_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x13C)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
-/*description: Those bits are used to configure the size of the first section for autoload oper
-ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
-CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x140)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the second section
- for autoload operation on L1-Cache. Note that it should be used together with L
-1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x144)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
-/*description: Those bits are used to configure the size of the second section for autoload ope
-ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
-SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x158)
-/* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
-1-DCache due to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_ENA    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ENA_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ENA_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_ENA_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
-1-DCache due to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_ENA    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ENA_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ENA_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_ENA_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x15C)
-/* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_CLR    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_CLR_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_CLR_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_CLR_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_CLR    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_CLR_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_CLR_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_CLR_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x160)
-/* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
-e due to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_RAW    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_RAW_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_RAW_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_RAW_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
-e due to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_RAW    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_RAW_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_RAW_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_RAW_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x164)
-/* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
-n L1-DCache due to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_ST    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ST_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ST_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_ST_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
-n L1-DCache due to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_ST    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ST_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ST_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_ST_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x168)
-/* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
-to cpu accesses L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x16C)
-/* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
-o cpu accesses L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x170)
-/* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x174)
-/* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
-ue to cpu accesses L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_ST    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_ST_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x178)
-/* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
-#define EXTMEM_L1_DBUS_CNT_CLR    (BIT(21))
-#define EXTMEM_L1_DBUS_CNT_CLR_M  (BIT(21))
-#define EXTMEM_L1_DBUS_CNT_CLR_V  0x1
-#define EXTMEM_L1_DBUS_CNT_CLR_S  21
-/* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
-#define EXTMEM_L1_IBUS_CNT_CLR    (BIT(20))
-#define EXTMEM_L1_IBUS_CNT_CLR_M  (BIT(20))
-#define EXTMEM_L1_IBUS_CNT_CLR_V  0x1
-#define EXTMEM_L1_IBUS_CNT_CLR_S  20
-/* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
-#define EXTMEM_L1_DBUS_CNT_ENA    (BIT(5))
-#define EXTMEM_L1_DBUS_CNT_ENA_M  (BIT(5))
-#define EXTMEM_L1_DBUS_CNT_ENA_V  0x1
-#define EXTMEM_L1_DBUS_CNT_ENA_S  5
-/* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
-#define EXTMEM_L1_IBUS_CNT_ENA    (BIT(4))
-#define EXTMEM_L1_IBUS_CNT_ENA_M  (BIT(4))
-#define EXTMEM_L1_IBUS_CNT_ENA_V  0x1
-#define EXTMEM_L1_IBUS_CNT_ENA_S  4
-
-#define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1BC)
-/* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of hits when bus0 accesses L1-Cache..*/
-#define EXTMEM_L1_IBUS_HIT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_HIT_CNT_M  ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S))
-#define EXTMEM_L1_IBUS_HIT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_HIT_CNT_S  0
-
-#define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C0)
-/* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of missing when bus0 accesses L1-Cache..*/
-#define EXTMEM_L1_IBUS_MISS_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_MISS_CNT_M  ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S))
-#define EXTMEM_L1_IBUS_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_MISS_CNT_S  0
-
-#define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C4)
-/* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/
-#define EXTMEM_L1_IBUS_CONFLICT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_CONFLICT_CNT_M  ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S))
-#define EXTMEM_L1_IBUS_CONFLICT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_CONFLICT_CNT_S  0
-
-#define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C8)
-/* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
-bus0 accessing L1-Cache..*/
-#define EXTMEM_L1_IBUS_NXTLVL_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_NXTLVL_CNT_M  ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S))
-#define EXTMEM_L1_IBUS_NXTLVL_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_NXTLVL_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1CC)
-/* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of hits when bus1 accesses L1-Cache..*/
-#define EXTMEM_L1_DBUS_HIT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_HIT_CNT_M  ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S))
-#define EXTMEM_L1_DBUS_HIT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_HIT_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D0)
-/* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of missing when bus1 accesses L1-Cache..*/
-#define EXTMEM_L1_DBUS_MISS_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_MISS_CNT_M  ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S))
-#define EXTMEM_L1_DBUS_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_MISS_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D4)
-/* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/
-#define EXTMEM_L1_DBUS_CONFLICT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_CONFLICT_CNT_M  ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S))
-#define EXTMEM_L1_DBUS_CONFLICT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_CONFLICT_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D8)
-/* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
-bus1 accessing L1-Cache..*/
-#define EXTMEM_L1_DBUS_NXTLVL_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_NXTLVL_CNT_M  ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S))
-#define EXTMEM_L1_DBUS_NXTLVL_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_NXTLVL_CNT_S  0
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x21C)
-/* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: The register records the attribution of fail-access when cache accesses L1-Cache
-..*/
-#define EXTMEM_L1_CACHE_FAIL_ATTR    0x0000FFFF
-#define EXTMEM_L1_CACHE_FAIL_ATTR_M  ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S))
-#define EXTMEM_L1_CACHE_FAIL_ATTR_V  0xFFFF
-#define EXTMEM_L1_CACHE_FAIL_ATTR_S  16
-/* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/
-#define EXTMEM_L1_CACHE_FAIL_ID    0x0000FFFF
-#define EXTMEM_L1_CACHE_FAIL_ID_M  ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S))
-#define EXTMEM_L1_CACHE_FAIL_ID_V  0xFFFF
-#define EXTMEM_L1_CACHE_FAIL_ID_S  0
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x220)
-/* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the address of fail-access when cache accesses L1-Cache..*/
-#define EXTMEM_L1_CACHE_FAIL_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_FAIL_ADDR_M  ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S))
-#define EXTMEM_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_FAIL_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x224)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op
-eration is done, interrupt occurs..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x228)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
- done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat
-ion is done..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x22C)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
-curs..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er
-ror occurs..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
- done..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x230)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
-r..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
-peration is done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre
-load-operation is done..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG          (DR_REG_EXTMEM_BASE + 0x234)
-/* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: The values 0-2 are available which means sync map, command conflict and size are
- error in Cache System..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE    0x00000003
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M  ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S))
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V  0x3
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S  12
-/* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE    0x00000003
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE_M  ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S))
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE_V  0x3
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE_S  8
-
-#define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x238)
-/* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
-y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
-#define EXTMEM_L1_CACHE_SYNC_RST    (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_RST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_RST_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_RST_S  4
-
-#define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x23C)
-/* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-only be used to initialize preload-logic when some fatal error of preload-logic
-occurs..*/
-#define EXTMEM_L1_CACHE_PLD_RST    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_RST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_RST_V  0x1
-#define EXTMEM_L1_CACHE_PLD_RST_S  4
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x240)
-/* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au
-toload will not work in L1-Cache. This bit should not be active when autoload wo
-rks in L1-Cache..*/
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR_V  0x1
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR_S  4
-
-#define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_EXTMEM_BASE + 0x244)
-/* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
-llocate request is responsed but not completed..*/
-#define EXTMEM_L1_CACHE_UNALLOC_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_UNALLOC_CLR_V  0x1
-#define EXTMEM_L1_CACHE_UNALLOC_CLR_S  4
-
-#define EXTMEM_L1_CACHE_OBJECT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x248)
-/* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi
-th the others fields inside this register..*/
-#define EXTMEM_L1_CACHE_MEM_OBJECT    (BIT(10))
-#define EXTMEM_L1_CACHE_MEM_OBJECT_M  (BIT(10))
-#define EXTMEM_L1_CACHE_MEM_OBJECT_V  0x1
-#define EXTMEM_L1_CACHE_MEM_OBJECT_S  10
-/* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
-h the others fields inside this register..*/
-#define EXTMEM_L1_CACHE_TAG_OBJECT    (BIT(4))
-#define EXTMEM_L1_CACHE_TAG_OBJECT_M  (BIT(4))
-#define EXTMEM_L1_CACHE_TAG_OBJECT_V  0x1
-#define EXTMEM_L1_CACHE_TAG_OBJECT_S  4
-
-#define EXTMEM_L1_CACHE_WAY_OBJECT_REG          (DR_REG_EXTMEM_BASE + 0x24C)
-/* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
-: way1, 2: way2, 3: way3, ?, 7: way7..*/
-#define EXTMEM_L1_CACHE_WAY_OBJECT    0x00000007
-#define EXTMEM_L1_CACHE_WAY_OBJECT_M  ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S))
-#define EXTMEM_L1_CACHE_WAY_OBJECT_V  0x7
-#define EXTMEM_L1_CACHE_WAY_OBJECT_S  0
-
-#define EXTMEM_L1_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x250)
-/* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
-/*description: Those bits stores the virtual address which will decide where inside the specifi
-ed tag memory object will be accessed..*/
-#define EXTMEM_L1_CACHE_VADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_VADDR_M  ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S))
-#define EXTMEM_L1_CACHE_VADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_VADDR_S  0
-
-#define EXTMEM_L1_CACHE_DEBUG_BUS_REG          (DR_REG_EXTMEM_BASE + 0x254)
-/* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
-/*description: This is a constant place where we can write data to or read data from the tag/da
-ta memory on the specified cache..*/
-#define EXTMEM_L1_CACHE_DEBUG_BUS    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_DEBUG_BUS_M  ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S))
-#define EXTMEM_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_DEBUG_BUS_S  0
-
-#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
-/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */
-/*description: version control register. Note that this default value stored is the latest date
- when the hardware logic was updated..*/
-#define EXTMEM_DATE    0x0FFFFFFF
-#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
-#define EXTMEM_DATE_V  0xFFFFFFF
-#define EXTMEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/extmem_struct.h b/components/soc/esp32p4/include/soc/extmem_struct.h
deleted file mode 100644
index dbd90f719a..0000000000
--- a/components/soc/esp32p4/include/soc/extmem_struct.h
+++ /dev/null
@@ -1,5747 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of l1_icache_ctrl register
- *  L1 instruction Cache(L1-ICache) control register
- */
-typedef union {
-    struct {
-        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus0:1;
-        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus1:1;
-        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus2:1;
-        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus3:1;
-        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_undef_op:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_icache_ctrl_reg_t;
-
-/** Type of l1_cache_ctrl register
- *  L1 data Cache(L1-Cache) control register
- */
-typedef union {
-    struct {
-        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus0:1;
-        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus1:1;
-        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus2:1;
-        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus3:1;
-        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_dma:1;
-        uint32_t reserved_5:3;
-        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_undef_op:4;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l1_cache_ctrl_reg_t;
-
-/** Type of l2_cache_ctrl register
- *  L2 Cache(L2-Cache) control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
-         */
-        uint32_t l2_cache_shut_dma:1;
-        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_cache_undef_op:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} extmem_l2_cache_ctrl_reg_t;
-
-
-/** Group: Bypass Cache Control and configuration registers */
-/** Type of l1_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache0_en:1;
-        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache1_en:1;
-        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache2_en:1;
-        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache3_en:1;
-        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_dcache_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_bypass_cache_conf_reg_t;
-
-/** Type of l2_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l2_cache_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_bypass_cache_conf_reg_t;
-
-
-/** Group: Cache Atomic Control and configuration registers */
-/** Type of l1_cache_atomic_conf register
- *  L1 Cache atomic feature configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
-         *  L1-Cache.  1: disable, 1: enable.
-         */
-        uint32_t l1_cache_atomic_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} extmem_l1_cache_atomic_conf_reg_t;
-
-
-/** Group: Cache Mode Control and configuration registers */
-/** Type of l1_icache_cachesize_conf register
- *  L1 instruction Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1k:1;
-        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2k:1;
-        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4k:1;
-        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_8k:1;
-        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_16k:1;
-        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_32k:1;
-        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_64k:1;
-        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_128k:1;
-        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_256k:1;
-        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_512k:1;
-        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1024k:1;
-        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2048k:1;
-        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l1_icache_cachesize_conf_reg_t;
-
-/** Type of l1_icache_blocksize_conf register
- *  L1 instruction Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_8:1;
-        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_16:1;
-        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_32:1;
-        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_64:1;
-        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_128:1;
-        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache_blocksize_conf_reg_t;
-
-/** Type of l1_cache_cachesize_conf register
- *  L1 data Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1k:1;
-        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2k:1;
-        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4k:1;
-        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_8k:1;
-        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_16k:1;
-        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1;
-         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_32k:1;
-        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_64k:1;
-        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_128k:1;
-        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_256k:1;
-        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_512k:1;
-        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1024k:1;
-        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2048k:1;
-        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l1_cache_cachesize_conf_reg_t;
-
-/** Type of l1_cache_blocksize_conf register
- *  L1 data Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_8:1;
-        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_16:1;
-        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
-         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_32:1;
-        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_64:1;
-        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_128:1;
-        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_cache_blocksize_conf_reg_t;
-
-/** Type of l2_cache_cachesize_conf register
- *  L2 Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1k:1;
-        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2k:1;
-        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4k:1;
-        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_8k:1;
-        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_16k:1;
-        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_32k:1;
-        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_64k:1;
-        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_128k:1;
-        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_256k:1;
-        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_512k:1;
-        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1024k:1;
-        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2048k:1;
-        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_cachesize_conf_reg_t;
-
-/** Type of l2_cache_blocksize_conf register
- *  L2 Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_8:1;
-        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_16:1;
-        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_32:1;
-        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_64:1;
-        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_128:1;
-        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_blocksize_conf_reg_t;
-
-
-/** Group: Wrap Mode Control and configuration registers */
-/** Type of l1_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
-         */
-        uint32_t l1_icache0_wrap:1;
-        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
-         */
-        uint32_t l1_icache1_wrap:1;
-        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_wrap:1;
-        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_wrap:1;
-        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
-         *  Set this bit as 1 to enable L1-DCache wrap around mode.
-         */
-        uint32_t l1_cache_wrap:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_wrap_around_ctrl_reg_t;
-
-/** Type of l2_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
-         *  Set this bit as 1 to enable L2-Cache wrap around mode.
-         */
-        uint32_t l2_cache_wrap:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_wrap_around_ctrl_reg_t;
-
-
-/** Group: Cache Tag Memory Power Control registers */
-/** Type of l1_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_tag_mem_force_on:1;
-        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_tag_mem_force_pd:1;
-        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_tag_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_tag_mem_force_on:1;
-        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_tag_mem_force_pd:1;
-        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_tag_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_on:1;
-        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pd:1;
-        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_on:1;
-        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pd:1;
-        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_tag_mem_force_on:1;
-        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l1_cache_tag_mem_force_pd:1;
-        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_tag_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_tag_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_tag_mem_force_on:1;
-        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l2_cache_tag_mem_force_pd:1;
-        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_tag_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_tag_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Power Control registers */
-/** Type of l1_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_data_mem_force_on:1;
-        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_data_mem_force_pd:1;
-        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_data_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_data_mem_force_on:1;
-        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_data_mem_force_pd:1;
-        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_data_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_on:1;
-        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pd:1;
-        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_on:1;
-        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pd:1;
-        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_data_mem_force_on:1;
-        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_cache_data_mem_force_pd:1;
-        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_data_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_data_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_data_mem_force_on:1;
-        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l2_cache_data_mem_force_pd:1;
-        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_data_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_data_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Freeze Control registers */
-/** Type of l1_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache0_freeze_en:1;
-        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache0_freeze_mode:1;
-        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_freeze_done:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache1_freeze_en:1;
-        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache1_freeze_mode:1;
-        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_freeze_done:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_en:1;
-        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_mode:1;
-        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_done:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_en:1;
-        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_mode:1;
-        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_done:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_cache_freeze_en:1;
-        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_cache_freeze_mode:1;
-        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_freeze_done:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_freeze_ctrl_reg_t;
-
-/** Type of l2_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l2_cache_freeze_en:1;
-        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l2_cache_freeze_mode:1;
-        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_freeze_done:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_freeze_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Access Control and Configuration registers */
-/** Type of l1_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_data_mem_rd_en:1;
-        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache0_data_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_data_mem_rd_en:1;
-        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache1_data_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_rd_en:1;
-        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_rd_en:1;
-        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_rd_en:1;
-        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} extmem_l1_cache_data_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_rd_en:1;
-        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} extmem_l2_cache_data_mem_acs_conf_reg_t;
-
-
-/** Group: Cache Tag Memory Access Control and Configuration registers */
-/** Type of l1_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_rd_en:1;
-        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_rd_en:1;
-        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_rd_en:1;
-        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_rd_en:1;
-        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_rd_en:1;
-        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} extmem_l1_cache_tag_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_rd_en:1;
-        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} extmem_l2_cache_tag_mem_acs_conf_reg_t;
-
-
-/** Group: Prelock Control and configuration registers */
-/** Type of l1_icache0_prelock_conf register
- *  L1 instruction Cache 0 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct0_en:1;
-        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct1_en:1;
-        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 prelock.
-         */
-        uint32_t l1_icache0_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_conf_reg_t;
-
-/** Type of l1_icache0_prelock_sct0_addr register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct1_addr register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct_size register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct_size_reg_t;
-
-/** Type of l1_icache1_prelock_conf register
- *  L1 instruction Cache 1 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct0_en:1;
-        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct1_en:1;
-        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 prelock.
-         */
-        uint32_t l1_icache1_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_conf_reg_t;
-
-/** Type of l1_icache1_prelock_sct0_addr register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct1_addr register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct_size register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct_size_reg_t;
-
-/** Type of l1_icache2_prelock_conf register
- *  L1 instruction Cache 2 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct0_en:1;
-        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct1_en:1;
-        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 prelock.
-         */
-        uint32_t l1_icache2_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_conf_reg_t;
-
-/** Type of l1_icache2_prelock_sct0_addr register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct1_addr register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct_size register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct_size_reg_t;
-
-/** Type of l1_icache3_prelock_conf register
- *  L1 instruction Cache 3 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct0_en:1;
-        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct1_en:1;
-        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 prelock.
-         */
-        uint32_t l1_icache3_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_conf_reg_t;
-
-/** Type of l1_icache3_prelock_sct0_addr register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct1_addr register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct_size register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct_size_reg_t;
-
-/** Type of l1_cache_prelock_conf register
- *  L1 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct0_en:1;
-        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct1_en:1;
-        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 cache prelock.
-         */
-        uint32_t l1_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_cache_prelock_conf_reg_t;
-
-/** Type of l1_cache_prelock_sct0_addr register
- *  L1 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct1_addr register
- *  L1 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_prelock_sct1_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct_size register
- *  L1  Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_dcache_prelock_sct_size_reg_t;
-
-/** Type of l2_cache_prelock_conf register
- *  L2 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct0_en:1;
-        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct1_en:1;
-        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l2 cache prelock.
-         */
-        uint32_t l2_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_conf_reg_t;
-
-/** Type of l2_cache_prelock_sct0_addr register
- *  L2 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct1_addr register
- *  L2 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct1_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct_size register
- *  L2 Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct0_size:16;
-        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct1_size:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct_size_reg_t;
-
-
-/** Group: Lock Control and configuration registers */
-/** Type of cache_lock_ctrl register
- *  Lock-class (manual lock) operation control register
- */
-typedef union {
-    struct {
-        /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
-         *  operation done
-         */
-        uint32_t cache_lock_ena:1;
-        /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable unlock operation. It will be cleared by hardware after
-         *  unlock operation done
-         */
-        uint32_t cache_unlock_ena:1;
-        /** cache_lock_done : RO; bitpos: [2]; default: 1;
-         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
-         *  not finished. 1: finished.
-         */
-        uint32_t cache_lock_done:1;
-        /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of cache lock/unlock.
-         */
-        uint32_t cache_lock_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_cache_lock_ctrl_reg_t;
-
-/** Type of cache_lock_map register
- *  Lock (manual lock) map configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_map : R/W; bitpos: [5:0]; default: 0;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply this lock/unlock operation. [4]: L1-Cache
-         */
-        uint32_t cache_lock_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_cache_lock_map_reg_t;
-
-/** Type of cache_lock_addr register
- *  Lock (manual lock) address configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the lock/unlock
-         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
-         */
-        uint32_t cache_lock_addr:32;
-    };
-    uint32_t val;
-} extmem_cache_lock_addr_reg_t;
-
-/** Type of cache_lock_size register
- *  Lock (manual lock) size configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_size : R/W; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the lock/unlock operation, which
-         *  should be used together with CACHE_LOCK_ADDR_REG
-         */
-        uint32_t cache_lock_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_cache_lock_size_reg_t;
-
-
-/** Group: Sync Control and configuration registers */
-/** Type of cache_sync_ctrl register
- *  Sync-class operation control register
- */
-typedef union {
-    struct {
-        /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
-         *  The bit is used to enable invalidate operation. It will be cleared by hardware
-         *  after invalidate operation done. Note that this bit and the other sync-bits
-         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_invalidate_ena:1;
-        /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable clean operation. It will be cleared by hardware after
-         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
-         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
-         *  bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_clean_ena:1;
-        /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0;
-         *  The bit is used to enable writeback operation. It will be cleared by hardware after
-         *  writeback operation done. Note that this bit and the other sync-bits
-         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_writeback_ena:1;
-        /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
-         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
-         *  hardware after writeback-invalidate operation done. Note that this bit and the
-         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
-         *  that is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_writeback_invalidate_ena:1;
-        /** cache_sync_done : RO; bitpos: [4]; default: 0;
-         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
-         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
-         */
-        uint32_t cache_sync_done:1;
-        /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0;
-         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
-         *  writeback, writeback_invalidate)
-         */
-        uint32_t cache_sync_rgid:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} extmem_cache_sync_ctrl_reg_t;
-
-/** Type of cache_sync_map register
- *  Sync map configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_map : R/W; bitpos: [5:0]; default: 63;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply the sync operation.  [4]: L1-Cache
-         */
-        uint32_t cache_sync_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_cache_sync_map_reg_t;
-
-/** Type of cache_sync_addr register
- *  Sync address configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the sync operation,
-         *  which should be used together with CACHE_SYNC_SIZE_REG
-         */
-        uint32_t cache_sync_addr:32;
-    };
-    uint32_t val;
-} extmem_cache_sync_addr_reg_t;
-
-/** Type of cache_sync_size register
- *  Sync size configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the sync operation, which should be
-         *  used together with CACHE_SYNC_ADDR_REG
-         */
-        uint32_t cache_sync_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} extmem_cache_sync_size_reg_t;
-
-
-/** Group: Preload Control and configuration registers */
-/** Type of l1_icache0_preload_ctrl register
- *  L1 instruction Cache 0 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache0_preload_ena:1;
-        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache0_preload_done:1;
-        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache0_preload_order:1;
-        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 preload.
-         */
-        uint32_t l1_icache0_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_ctrl_reg_t;
-
-/** Type of l1_icache0_preload_addr register
- *  L1 instruction Cache 0 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache0_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_addr_reg_t;
-
-/** Type of l1_icache0_preload_size register
- *  L1 instruction Cache 0 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache0_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_size_reg_t;
-
-/** Type of l1_icache1_preload_ctrl register
- *  L1 instruction Cache 1 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache1_preload_ena:1;
-        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache1_preload_done:1;
-        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache1_preload_order:1;
-        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 preload.
-         */
-        uint32_t l1_icache1_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_ctrl_reg_t;
-
-/** Type of l1_icache1_preload_addr register
- *  L1 instruction Cache 1 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache1_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_addr_reg_t;
-
-/** Type of l1_icache1_preload_size register
- *  L1 instruction Cache 1 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache1_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_size_reg_t;
-
-/** Type of l1_icache2_preload_ctrl register
- *  L1 instruction Cache 2 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache2_preload_ena:1;
-        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache2_preload_done:1;
-        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache2_preload_order:1;
-        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 preload.
-         */
-        uint32_t l1_icache2_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_ctrl_reg_t;
-
-/** Type of l1_icache2_preload_addr register
- *  L1 instruction Cache 2 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache2_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_addr_reg_t;
-
-/** Type of l1_icache2_preload_size register
- *  L1 instruction Cache 2 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache2_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_size_reg_t;
-
-/** Type of l1_icache3_preload_ctrl register
- *  L1 instruction Cache 3 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache3_preload_ena:1;
-        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache3_preload_done:1;
-        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache3_preload_order:1;
-        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 preload.
-         */
-        uint32_t l1_icache3_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_ctrl_reg_t;
-
-/** Type of l1_icache3_preload_addr register
- *  L1 instruction Cache 3 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache3_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_addr_reg_t;
-
-/** Type of l1_icache3_preload_size register
- *  L1 instruction Cache 3 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache3_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_size_reg_t;
-
-/** Type of l1_cache_preload_ctrl register
- *  L1 Cache  preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_cache_preload_ena:1;
-        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_cache_preload_done:1;
-        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_cache_preload_order:1;
-        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 cache preload.
-         */
-        uint32_t l1_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_cache_preload_ctrl_reg_t;
-
-/** Type of l1_dcache_preload_addr register
- *  L1 Cache  preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
-         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_cache_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_preload_addr_reg_t;
-
-/** Type of l1_dcache_preload_size register
- *  L1 Cache  preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_cache_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_dcache_preload_size_reg_t;
-
-/** Type of l2_cache_preload_ctrl register
- *  L2 Cache preload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l2_cache_preload_ena:1;
-        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l2_cache_preload_done:1;
-        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l2_cache_preload_order:1;
-        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l2 cache preload.
-         */
-        uint32_t l2_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_ctrl_reg_t;
-
-/** Type of l2_cache_preload_addr register
- *  L2 Cache preload address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
-         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l2_cache_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_addr_reg_t;
-
-/** Type of l2_cache_preload_size register
- *  L2 Cache preload size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l2_cache_preload_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_size_reg_t;
-
-
-/** Group: Autoload Control and configuration registers */
-/** Type of l1_icache0_autoload_ctrl register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache0_autoload_ena:1;
-        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_autoload_done:1;
-        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache0_autoload_order:1;
-        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache0_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct0_ena:1;
-        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct1_ena:1;
-        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 autoload.
-         */
-        uint32_t l1_icache0_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_ctrl_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_addr register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_size register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_addr register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_size register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache1_autoload_ctrl register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache1_autoload_ena:1;
-        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_autoload_done:1;
-        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache1_autoload_order:1;
-        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache1_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct0_ena:1;
-        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct1_ena:1;
-        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 autoload.
-         */
-        uint32_t l1_icache1_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_ctrl_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_addr register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_size register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_addr register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_size register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache2_autoload_ctrl register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache2_autoload_ena:1;
-        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache2_autoload_done:1;
-        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache2_autoload_order:1;
-        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache2_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct0_ena:1;
-        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct1_ena:1;
-        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 autoload.
-         */
-        uint32_t l1_icache2_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_ctrl_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_addr register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_size register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_addr register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_size register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache3_autoload_ctrl register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache3_autoload_ena:1;
-        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache3_autoload_done:1;
-        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache3_autoload_order:1;
-        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache3_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct0_ena:1;
-        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct1_ena:1;
-        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 autoload.
-         */
-        uint32_t l1_icache3_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_ctrl_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_addr register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_size register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_addr register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_size register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_ctrl register
- *  L1 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_cache_autoload_ena:1;
-        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_autoload_done:1;
-        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_cache_autoload_order:1;
-        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct0_ena:1;
-        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct1_ena:1;
-        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct2_ena:1;
-        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct3_ena:1;
-        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l1 cache autoload.
-         */
-        uint32_t l1_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_ctrl_reg_t;
-
-/** Type of l1_cache_autoload_sct0_addr register
- *  L1 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct0_size register
- *  L1 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct0_size_reg_t;
-
-/** Type of l1_cache_autoload_sct1_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct1_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_sct2_addr register
- *  L1 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct2_size register
- *  L1 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct2_size_reg_t;
-
-/** Type of l1_cache_autoload_sct3_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct3_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct3_size_reg_t;
-
-/** Type of l2_cache_autoload_ctrl register
- *  L2 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l2_cache_autoload_ena:1;
-        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_autoload_done:1;
-        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l2_cache_autoload_order:1;
-        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l2_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct0_ena:1;
-        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct1_ena:1;
-        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct2_ena:1;
-        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct3_ena:1;
-        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l2 cache autoload.
-         */
-        uint32_t l2_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_sct0_addr register
- *  L2 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct0_size register
- *  L2 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct0_size_reg_t;
-
-/** Type of l2_cache_autoload_sct1_addr register
- *  L2 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct1_size register
- *  L2 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct1_size_reg_t;
-
-/** Type of l2_cache_autoload_sct2_addr register
- *  L2 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct2_size register
- *  L2 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct2_size_reg_t;
-
-/** Type of l2_cache_autoload_sct3_addr register
- *  L2 Cache autoload section 3 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct3_size register
- *  L2 Cache autoload section 3 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct3_size_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of l1_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_ena:1;
-        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_ena:1;
-        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_ena:1;
-        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_ena:1;
-        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_ena:1;
-        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_ena:1;
-        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_ena:1;
-        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_ena:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
-         *  to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_clr:1;
-        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
-         *  to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_clr:1;
-        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_clr:1;
-        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_clr:1;
-        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_clr:1;
-        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_clr:1;
-        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_clr:1;
-        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_clr:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
-         *  due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_raw:1;
-        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
-         *  due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_raw:1;
-        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
-         *  due to bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_ovf_int_raw:1;
-        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
-         *  due to bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_ovf_int_raw:1;
-        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_raw:1;
-        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_raw:1;
-        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_ovf_int_raw:1;
-        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_ovf_int_raw:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_st:1;
-        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_st:1;
-        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_st:1;
-        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_st:1;
-        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_st:1;
-        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_st:1;
-        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_st:1;
-        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_st:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l1_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_ena:1;
-        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_ena:1;
-        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_ena:1;
-        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_ena:1;
-        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l1_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_clr:1;
-        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_clr:1;
-        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_clr:1;
-        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_clr:1;
-        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l1_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_raw:1;
-        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_raw:1;
-        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
-         */
-        uint32_t l1_icache2_fail_int_raw:1;
-        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
-         */
-        uint32_t l1_icache3_fail_int_raw:1;
-        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l1_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_int_st:1;
-        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_int_st:1;
-        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_st:1;
-        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_st:1;
-        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
-         *  to cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_st_reg_t;
-
-/** Type of l1_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache0_pld_done_int_ena:1;
-        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache1_pld_done_int_ena:1;
-        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_ena:1;
-        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_ena:1;
-        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_cache_pld_done_int_ena:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation done.
-         */
-        uint32_t cache_sync_done_int_ena:1;
-        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_ena:1;
-        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_ena:1;
-        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_ena:1;
-        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_ena:1;
-        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_ena:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_ena:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l1_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_clr:1;
-        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_clr:1;
-        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_clr:1;
-        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_clr:1;
-        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l1_cache_pld_done_int_clr:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
-         *  done.
-         */
-        uint32_t cache_sync_done_int_clr:1;
-        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_clr:1;
-        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_clr:1;
-        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_clr:1;
-        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_clr:1;
-        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
-         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_clr:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0;
-         *  The bit is used to clear interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_clr:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l1_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache0_pld_done_int_raw:1;
-        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache1_pld_done_int_raw:1;
-        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_raw:1;
-        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_raw:1;
-        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l1_cache_pld_done_int_raw:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
-         */
-        uint32_t cache_sync_done_int_raw:1;
-        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache0_pld_err_int_raw:1;
-        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache1_pld_err_int_raw:1;
-        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_raw:1;
-        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_raw:1;
-        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_err_int_raw:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
-         *  occurs.
-         */
-        uint32_t cache_sync_err_int_raw:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l1_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_st:1;
-        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_st:1;
-        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_st:1;
-        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_st:1;
-        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l1_cache_pld_done_int_st:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when Cache
-         *  sync-operation is done.
-         */
-        uint32_t cache_sync_done_int_st:1;
-        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_st:1;
-        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_st:1;
-        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_st:1;
-        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_st:1;
-        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_st:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0;
-         *  The bit indicates the status of the interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_st:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_st_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_ena:1;
-        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_ena:1;
-        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_ena:1;
-        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_ena:1;
-        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_ena:1;
-        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_ena:1;
-        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_ena:1;
-        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_clr:1;
-        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_clr:1;
-        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_clr:1;
-        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_clr:1;
-        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_clr:1;
-        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_clr:1;
-        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_clr:1;
-        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-ICache0.
-         */
-        uint32_t l2_ibus0_ovf_int_raw:1;
-        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-ICache1.
-         */
-        uint32_t l2_ibus1_ovf_int_raw:1;
-        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-ICache2.
-         */
-        uint32_t l2_ibus2_ovf_int_raw:1;
-        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-ICache3.
-         */
-        uint32_t l2_ibus3_ovf_int_raw:1;
-        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-DCache.
-         */
-        uint32_t l2_dbus0_ovf_int_raw:1;
-        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-DCache.
-         */
-        uint32_t l2_dbus1_ovf_int_raw:1;
-        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-DCache.
-         */
-        uint32_t l2_dbus2_ovf_int_raw:1;
-        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-DCache.
-         */
-        uint32_t l2_dbus3_ovf_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_st:1;
-        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_st:1;
-        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_st:1;
-        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_st:1;
-        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_st:1;
-        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_st:1;
-        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_st:1;
-        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l2_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
-         *  l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l2_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
-         *  cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l2_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l2_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
-         *  to l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_st_reg_t;
-
-/** Type of l2_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
-         */
-        uint32_t l2_cache_pld_done_int_ena:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_ena:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l2_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l2_cache_pld_done_int_clr:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_clr:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l2_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l2_cache_pld_done_int_raw:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_err_int_raw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l2_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l2_cache_pld_done_int_st:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_st:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_st_reg_t;
-
-
-/** Group: Access Statistics registers */
-/** Type of l1_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_ena:1;
-        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_ena:1;
-        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_ena:1;
-        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_ena:1;
-        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_ena:1;
-        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_ena:1;
-        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_ena:1;
-        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_ena:1;
-        uint32_t reserved_8:8;
-        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
-         *  The bit is used to clear ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_clr:1;
-        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
-         *  The bit is used to clear ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_clr:1;
-        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_clr:1;
-        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_clr:1;
-        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
-         *  The bit is used to clear dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_clr:1;
-        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
-         *  The bit is used to clear dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_clr:1;
-        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_clr:1;
-        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_clr:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l1_ibus0_acs_hit_cnt register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_miss_cnt register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_conflict_cnt register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_nxtlvl_cnt register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l1_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_hit_cnt register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_miss_cnt register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_conflict_cnt register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_nxtlvl_cnt register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l1_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_hit_cnt register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_miss_cnt register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_conflict_cnt register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_nxtlvl_cnt register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l1_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_hit_cnt register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_miss_cnt register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_conflict_cnt register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_nxtlvl_cnt register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l1_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus0_acs_hit_cnt register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus0_acs_miss_cnt register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus0_acs_conflict_cnt register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus0_acs_nxtlvl_cnt register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus0 accessing L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus1_acs_hit_cnt register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus1_acs_miss_cnt register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus1_acs_conflict_cnt register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus1_acs_nxtlvl_cnt register
- *  L1-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus1 accessing L1-Cache.
-         */
-        uint32_t l1_bus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_hit_cnt register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_miss_cnt register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_conflict_cnt register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_nxtlvl_cnt register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l1_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_hit_cnt register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_miss_cnt register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_conflict_cnt register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_nxtlvl_cnt register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l1_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_ena:1;
-        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_ena:1;
-        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_ena:1;
-        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_ena:1;
-        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_ena:1;
-        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_ena:1;
-        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_ena:1;
-        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_ena:1;
-        uint32_t reserved_16:8;
-        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
-         *  The bit is used to clear ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_clr:1;
-        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
-         *  The bit is used to clear ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_clr:1;
-        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_clr:1;
-        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_clr:1;
-        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
-         *  The bit is used to clear dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_clr:1;
-        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
-         *  The bit is used to clear dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_clr:1;
-        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_clr:1;
-        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_clr:1;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l2_ibus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache0 accesses
-         *  L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache1 accesses
-         *  L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache2 accesses
-         *  L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache3 accesses
-         *  L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t;
-
-
-/** Group: Access Fail Debug registers */
-/** Type of l1_icache0_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_id:16;
-        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache0_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache0_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_acs_fail_addr_reg_t;
-
-/** Type of l1_icache1_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_id:16;
-        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache1_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache1_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_acs_fail_addr_reg_t;
-
-/** Type of l1_icache2_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_id:16;
-        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache2_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache2_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_acs_fail_addr_reg_t;
-
-/** Type of l1_icache3_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_id:16;
-        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache3_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache3_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_acs_fail_addr_reg_t;
-
-/** Type of l1_cache_acs_fail_id_attr register
- *  L1-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_id:16;
-        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l1_dcache_acs_fail_addr register
- *  L1-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_acs_fail_addr_reg_t;
-
-/** Type of l2_cache_acs_fail_id_attr register
- *  L2-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_id:16;
-        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
-         *  due to cache accessing L1-Cache.
-         */
-        uint32_t l2_cache_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l2_cache_acs_fail_addr register
- *  L2-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_addr_reg_t;
-
-
-/** Group: Operation Exception registers */
-/** Type of l1_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache0.
-         */
-        uint32_t l1_icache0_pld_err_code:2;
-        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache1.
-         */
-        uint32_t l1_icache1_pld_err_code:2;
-        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_code:2;
-        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_code:2;
-        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-Cache.
-         */
-        uint32_t l1_cache_pld_err_code:2;
-        uint32_t reserved_10:2;
-        /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0;
-         *  The values 0-2 are available which means sync map, command conflict and size are
-         *  error in Cache System.
-         */
-        uint32_t cache_sync_err_code:2;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_exception_reg_t;
-
-/** Type of l2_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L2-Cache.
-         */
-        uint32_t l2_cache_pld_err_code:2;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_exception_reg_t;
-
-
-/** Group: Sync Reset control and configuration registers */
-/** Type of l1_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache0_sync_rst:1;
-        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache1_sync_rst:1;
-        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_sync_rst:1;
-        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_sync_rst:1;
-        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_cache_sync_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_rst_ctrl_reg_t;
-
-/** Type of l2_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l2_cache_sync_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_rst_ctrl_reg_t;
-
-
-/** Group: Preload Reset control and configuration registers */
-/** Type of l1_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache0_pld_rst:1;
-        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache1_pld_rst:1;
-        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_rst:1;
-        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_rst:1;
-        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_preload_rst_ctrl_reg_t;
-
-/** Type of l2_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_rst_ctrl_reg_t;
-
-
-/** Group: Autoload buffer clear control and configuration registers */
-/** Type of l1_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
-         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
-         *  works in L1-ICache0.
-         */
-        uint32_t l1_icache0_ald_buf_clr:1;
-        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
-         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
-         *  works in L1-ICache1.
-         */
-        uint32_t l1_icache1_ald_buf_clr:1;
-        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_ald_buf_clr:1;
-        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_ald_buf_clr:1;
-        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
-         *  autoload will not work in L1-Cache. This bit should not be active when autoload
-         *  works in L1-Cache.
-         */
-        uint32_t l1_cache_ald_buf_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
-         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
-         *  autoload will not work in L2-Cache. This bit should not be active when autoload
-         *  works in L2-Cache.
-         */
-        uint32_t l2_cache_ald_buf_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t;
-
-
-/** Group: Unallocate request buffer clear registers */
-/** Type of l1_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache0_unalloc_clr:1;
-        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache1_unalloc_clr:1;
-        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_unalloc_clr:1;
-        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_unalloc_clr:1;
-        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_cache_unalloc_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_unallocate_buffer_clear_reg_t;
-
-/** Type of l2_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l2_cache_unalloc_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_unallocate_buffer_clear_reg_t;
-
-
-/** Group: Tag and Data Memory Access Control and configuration register */
-/** Type of l1_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
-         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache0_tag_object:1;
-        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
-         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache1_tag_object:1;
-        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_object:1;
-        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_object:1;
-        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_tag_object:1;
-        uint32_t reserved_5:1;
-        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
-         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache0_mem_object:1;
-        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
-         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache1_mem_object:1;
-        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_mem_object:1;
-        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_mem_object:1;
-        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_mem_object:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} extmem_l1_cache_object_ctrl_reg_t;
-
-/** Type of l1_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l1_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} extmem_l1_cache_way_object_reg_t;
-
-/** Type of l1_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l1_cache_vaddr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_vaddr_reg_t;
-
-/** Type of l1_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l1_cache_debug_bus:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_debug_bus_reg_t;
-
-/** Type of l2_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
-         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_tag_object:1;
-        uint32_t reserved_6:5;
-        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
-         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_mem_object:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l2_cache_object_ctrl_reg_t;
-
-/** Type of l2_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l2_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} extmem_l2_cache_way_object_reg_t;
-
-/** Type of l2_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l2_cache_vaddr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_vaddr_reg_t;
-
-/** Type of l2_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l2_cache_debug_bus:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_debug_bus_reg_t;
-
-
-/** Group: Split L1 and L2 registers */
-/** Type of level_split0 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
-         *  Reserved
-         */
-        uint32_t level_split0:32;
-    };
-    uint32_t val;
-} extmem_level_split0_reg_t;
-
-/** Type of level_split1 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
-         *  Reserved
-         */
-        uint32_t level_split1:32;
-    };
-    uint32_t val;
-} extmem_level_split1_reg_t;
-
-
-/** Group: L2 cache access attribute control register */
-/** Type of l2_cache_access_attr_ctrl register
- *  L1 Cache access Attribute propagation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
-         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
-         *  non-cacheable.
-         */
-        uint32_t l2_cache_access_force_cc:1;
-        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
-         *  write-through.
-         */
-        uint32_t l2_cache_access_force_wb:1;
-        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  write-miss-allocate and write-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_wma:1;
-        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
-         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  read-miss-allocate and read-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_rma:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} extmem_l2_cache_access_attr_ctrl_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} extmem_clock_gate_reg_t;
-
-
-/** Group: Redundancy  register (Prepare for ECO) */
-/** Type of redundancy_sig0 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig0:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig0_reg_t;
-
-/** Type of redundancy_sig1 register
- *  Cache redundancy signal 1 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig1:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig1_reg_t;
-
-/** Type of redundancy_sig2 register
- *  Cache redundancy signal 2 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig2:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig2_reg_t;
-
-/** Type of redundancy_sig3 register
- *  Cache redundancy signal 3 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig3:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig3_reg_t;
-
-/** Type of redundancy_sig4 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig4:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} extmem_redundancy_sig4_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35659904;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_date_reg_t;
-
-
-typedef struct extmem_dev_s {
-    volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl;
-    volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl;
-    volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
-    volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
-    volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
-    volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
-    volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
-    volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
-    volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
-    volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
-    volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
-    volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
-    volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
-    volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
-    volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
-    volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
-    volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
-    volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
-    volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
-    volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
-    volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
-    volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
-    volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
-    volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
-    volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
-    volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
-    volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
-    volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
-    volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
-    volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
-    volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
-    volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
-    volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
-    volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
-    volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl;
-    volatile extmem_cache_lock_map_reg_t cache_lock_map;
-    volatile extmem_cache_lock_addr_reg_t cache_lock_addr;
-    volatile extmem_cache_lock_size_reg_t cache_lock_size;
-    volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl;
-    volatile extmem_cache_sync_map_reg_t cache_sync_map;
-    volatile extmem_cache_sync_addr_reg_t cache_sync_addr;
-    volatile extmem_cache_sync_size_reg_t cache_sync_size;
-    volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
-    volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
-    volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
-    volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
-    volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
-    volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
-    volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
-    volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
-    volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
-    volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
-    volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
-    volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
-    volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
-    volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
-    volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
-    volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
-    volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
-    volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
-    volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
-    volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
-    volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
-    volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
-    volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
-    volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
-    volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
-    volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
-    volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
-    volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
-    volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
-    volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
-    volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
-    volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
-    volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
-    volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
-    volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
-    volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
-    volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
-    volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
-    volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
-    volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
-    volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
-    volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
-    volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
-    volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
-    volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
-    volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
-    volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
-    volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
-    volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
-    volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
-    volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
-    volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
-    volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
-    volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
-    volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
-    volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
-    volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
-    volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
-    volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
-    volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
-    volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
-    volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
-    volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
-    volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
-    volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
-    volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
-    volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
-    volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
-    volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
-    volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
-    volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
-    volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
-    volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
-    volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
-    volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
-    volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
-    volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
-    volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
-    volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
-    volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
-    volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
-    volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
-    volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
-    volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
-    volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
-    volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
-    volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
-    volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
-    volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
-    volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
-    volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
-    volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
-    volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
-    volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
-    volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
-    volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
-    volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
-    volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
-    volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
-    volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
-    volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
-    volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
-    volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object;
-    volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr;
-    volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
-    volatile extmem_level_split0_reg_t level_split0;
-    volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl;
-    volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
-    volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
-    volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
-    volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
-    volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
-    volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
-    volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
-    volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
-    volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
-    volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
-    volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
-    volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
-    volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
-    volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
-    volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
-    volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size;
-    volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
-    volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
-    volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
-    volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
-    volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
-    volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
-    volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
-    volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
-    volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
-    volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
-    volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
-    volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
-    volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
-    volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
-    volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
-    volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
-    volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
-    volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
-    volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
-    volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
-    volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
-    volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
-    volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
-    volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
-    volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
-    volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
-    volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
-    volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
-    volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
-    volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
-    volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
-    volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
-    volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
-    volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
-    volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
-    volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
-    volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
-    volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
-    volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
-    volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
-    volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
-    volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
-    volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
-    volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
-    volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
-    volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
-    volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
-    volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
-    volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
-    volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
-    volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
-    volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
-    volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
-    volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
-    volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
-    volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
-    volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object;
-    volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr;
-    volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
-    volatile extmem_level_split1_reg_t level_split1;
-    volatile extmem_clock_gate_reg_t clock_gate;
-    volatile extmem_redundancy_sig0_reg_t redundancy_sig0;
-    volatile extmem_redundancy_sig1_reg_t redundancy_sig1;
-    volatile extmem_redundancy_sig2_reg_t redundancy_sig2;
-    volatile extmem_redundancy_sig3_reg_t redundancy_sig3;
-    volatile extmem_redundancy_sig4_reg_t redundancy_sig4;
-    uint32_t reserved_3c4[14];
-    volatile extmem_date_reg_t date;
-} extmem_dev_t;
-
-extern extmem_dev_t EXTMEM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/gdma_channel.h b/components/soc/esp32p4/include/soc/gdma_channel.h
index 785d920785..d2aa55b41e 100644
--- a/components/soc/esp32p4/include/soc/gdma_channel.h
+++ b/components/soc/esp32p4/include/soc/gdma_channel.h
@@ -5,13 +5,3 @@
  */
 
 #pragma once
-
-// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
-#define SOC_GDMA_TRIG_PERIPH_M2M0    (-1)
-#define SOC_GDMA_TRIG_PERIPH_SPI2    (0)
-#define SOC_GDMA_TRIG_PERIPH_UHCI0   (2)
-#define SOC_GDMA_TRIG_PERIPH_I2S0    (3)
-#define SOC_GDMA_TRIG_PERIPH_AES0    (6)
-#define SOC_GDMA_TRIG_PERIPH_SHA0    (7)
-#define SOC_GDMA_TRIG_PERIPH_ADC0    (8)
-#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
diff --git a/components/soc/esp32p4/include/soc/gpio_pins.h b/components/soc/esp32p4/include/soc/gpio_pins.h
index 7731c871b0..6238eeffbb 100644
--- a/components/soc/esp32p4/include/soc/gpio_pins.h
+++ b/components/soc/esp32p4/include/soc/gpio_pins.h
@@ -11,8 +11,6 @@
 extern "C" {
 #endif
 
-#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
-#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/gpio_sd_reg.h b/components/soc/esp32p4/include/soc/gpio_sd_reg.h
deleted file mode 100644
index 3173778fda..0000000000
--- a/components/soc/esp32p4/include/soc/gpio_sd_reg.h
+++ /dev/null
@@ -1,1455 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GPIOSD_SIGMADELTA0_REG register
- *  Duty Cycle Configure Register of SDM0
- */
-#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA1_REG register
- *  Duty Cycle Configure Register of SDM1
- */
-#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA2_REG register
- *  Duty Cycle Configure Register of SDM2
- */
-#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA3_REG register
- *  Duty Cycle Configure Register of SDM3
- */
-#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA4_REG register
- *  Duty Cycle Configure Register of SDM4
- */
-#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA5_REG register
- *  Duty Cycle Configure Register of SDM5
- */
-#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA6_REG register
- *  Duty Cycle Configure Register of SDM6
- */
-#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA7_REG register
- *  Duty Cycle Configure Register of SDM7
- */
-#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c)
-/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIOSD_SD0_IN    0x000000FFU
-#define GPIOSD_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
-#define GPIOSD_SD0_IN_V  0x000000FFU
-#define GPIOSD_SD0_IN_S  0
-/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIOSD_SD0_PRESCALE    0x000000FFU
-#define GPIOSD_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
-#define GPIOSD_SD0_PRESCALE_V  0x000000FFU
-#define GPIOSD_SD0_PRESCALE_S  8
-
-/** GPIOSD_SIGMADELTA_MISC_REG register
- *  MISC Register
- */
-#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24)
-/** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
- *  Clock enable bit of sigma delta modulation.
- */
-#define GPIOSD_FUNCTION_CLK_EN    (BIT(30))
-#define GPIOSD_FUNCTION_CLK_EN_M  (GPIOSD_FUNCTION_CLK_EN_V << GPIOSD_FUNCTION_CLK_EN_S)
-#define GPIOSD_FUNCTION_CLK_EN_V  0x00000001U
-#define GPIOSD_FUNCTION_CLK_EN_S  30
-/** GPIOSD_SPI_SWAP : R/W; bitpos: [31]; default: 0;
- *  Reserved.
- */
-#define GPIOSD_SPI_SWAP    (BIT(31))
-#define GPIOSD_SPI_SWAP_M  (GPIOSD_SPI_SWAP_V << GPIOSD_SPI_SWAP_S)
-#define GPIOSD_SPI_SWAP_V  0x00000001U
-#define GPIOSD_SPI_SWAP_S  31
-
-/** GPIOSD_GLITCH_FILTER_CH0_REG register
- *  Glitch Filter Configure Register of Channel0
- */
-#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_GLITCH_FILTER_CH1_REG register
- *  Glitch Filter Configure Register of Channel1
- */
-#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_GLITCH_FILTER_CH2_REG register
- *  Glitch Filter Configure Register of Channel2
- */
-#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_GLITCH_FILTER_CH3_REG register
- *  Glitch Filter Configure Register of Channel3
- */
-#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_GLITCH_FILTER_CH4_REG register
- *  Glitch Filter Configure Register of Channel4
- */
-#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_GLITCH_FILTER_CH5_REG register
- *  Glitch Filter Configure Register of Channel5
- */
-#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_GLITCH_FILTER_CH6_REG register
- *  Glitch Filter Configure Register of Channel6
- */
-#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_GLITCH_FILTER_CH7_REG register
- *  Glitch Filter Configure Register of Channel7
- */
-#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c)
-/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIOSD_FILTER_CH0_EN    (BIT(0))
-#define GPIOSD_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
-#define GPIOSD_FILTER_CH0_EN_V  0x00000001U
-#define GPIOSD_FILTER_CH0_EN_S  0
-/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIOSD_ETM_EVENT_CH0_CFG_REG register
- *  Etm Config register of Channel0
- */
-#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_EVENT_CH1_CFG_REG register
- *  Etm Config register of Channel1
- */
-#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_EVENT_CH2_CFG_REG register
- *  Etm Config register of Channel2
- */
-#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_EVENT_CH3_CFG_REG register
- *  Etm Config register of Channel3
- */
-#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_EVENT_CH4_CFG_REG register
- *  Etm Config register of Channel4
- */
-#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_EVENT_CH5_CFG_REG register
- *  Etm Config register of Channel5
- */
-#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_EVENT_CH6_CFG_REG register
- *  Etm Config register of Channel6
- */
-#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_EVENT_CH7_CFG_REG register
- *  Etm Config register of Channel7
- */
-#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c)
-/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIOSD_ETM_CH0_EVENT_SEL    0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
-#define GPIOSD_ETM_CH0_EVENT_SEL_V  0x0000003FU
-#define GPIOSD_ETM_CH0_EVENT_SEL_S  0
-/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIOSD_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIOSD_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
-#define GPIOSD_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIOSD_ETM_CH0_EVENT_EN_S  7
-
-/** GPIOSD_ETM_TASK_P0_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0)
-/** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO0_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO0_EN_M  (GPIOSD_ETM_TASK_GPIO0_EN_V << GPIOSD_ETM_TASK_GPIO0_EN_S)
-#define GPIOSD_ETM_TASK_GPIO0_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO0_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO0_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO0_SEL_M  (GPIOSD_ETM_TASK_GPIO0_SEL_V << GPIOSD_ETM_TASK_GPIO0_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO0_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO0_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO1_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO1_EN_M  (GPIOSD_ETM_TASK_GPIO1_EN_V << GPIOSD_ETM_TASK_GPIO1_EN_S)
-#define GPIOSD_ETM_TASK_GPIO1_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO1_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO1_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO1_SEL_M  (GPIOSD_ETM_TASK_GPIO1_SEL_V << GPIOSD_ETM_TASK_GPIO1_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO1_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO1_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO2_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO2_EN_M  (GPIOSD_ETM_TASK_GPIO2_EN_V << GPIOSD_ETM_TASK_GPIO2_EN_S)
-#define GPIOSD_ETM_TASK_GPIO2_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO2_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO2_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO2_SEL_M  (GPIOSD_ETM_TASK_GPIO2_SEL_V << GPIOSD_ETM_TASK_GPIO2_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO2_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO2_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO3_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO3_EN_M  (GPIOSD_ETM_TASK_GPIO3_EN_V << GPIOSD_ETM_TASK_GPIO3_EN_S)
-#define GPIOSD_ETM_TASK_GPIO3_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO3_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO3_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO3_SEL_M  (GPIOSD_ETM_TASK_GPIO3_SEL_V << GPIOSD_ETM_TASK_GPIO3_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO3_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO3_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P1_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4)
-/** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO4_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO4_EN_M  (GPIOSD_ETM_TASK_GPIO4_EN_V << GPIOSD_ETM_TASK_GPIO4_EN_S)
-#define GPIOSD_ETM_TASK_GPIO4_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO4_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO4_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO4_SEL_M  (GPIOSD_ETM_TASK_GPIO4_SEL_V << GPIOSD_ETM_TASK_GPIO4_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO4_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO4_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO5_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO5_EN_M  (GPIOSD_ETM_TASK_GPIO5_EN_V << GPIOSD_ETM_TASK_GPIO5_EN_S)
-#define GPIOSD_ETM_TASK_GPIO5_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO5_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO5_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO5_SEL_M  (GPIOSD_ETM_TASK_GPIO5_SEL_V << GPIOSD_ETM_TASK_GPIO5_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO5_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO5_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO6_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO6_EN_M  (GPIOSD_ETM_TASK_GPIO6_EN_V << GPIOSD_ETM_TASK_GPIO6_EN_S)
-#define GPIOSD_ETM_TASK_GPIO6_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO6_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO6_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO6_SEL_M  (GPIOSD_ETM_TASK_GPIO6_SEL_V << GPIOSD_ETM_TASK_GPIO6_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO6_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO6_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO7_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO7_EN_M  (GPIOSD_ETM_TASK_GPIO7_EN_V << GPIOSD_ETM_TASK_GPIO7_EN_S)
-#define GPIOSD_ETM_TASK_GPIO7_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO7_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO7_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO7_SEL_M  (GPIOSD_ETM_TASK_GPIO7_SEL_V << GPIOSD_ETM_TASK_GPIO7_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO7_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO7_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P2_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8)
-/** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO8_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO8_EN_M  (GPIOSD_ETM_TASK_GPIO8_EN_V << GPIOSD_ETM_TASK_GPIO8_EN_S)
-#define GPIOSD_ETM_TASK_GPIO8_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO8_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO8_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO8_SEL_M  (GPIOSD_ETM_TASK_GPIO8_SEL_V << GPIOSD_ETM_TASK_GPIO8_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO8_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO8_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO9_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO9_EN_M  (GPIOSD_ETM_TASK_GPIO9_EN_V << GPIOSD_ETM_TASK_GPIO9_EN_S)
-#define GPIOSD_ETM_TASK_GPIO9_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO9_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO9_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO9_SEL_M  (GPIOSD_ETM_TASK_GPIO9_SEL_V << GPIOSD_ETM_TASK_GPIO9_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO9_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO9_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO10_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO10_EN_M  (GPIOSD_ETM_TASK_GPIO10_EN_V << GPIOSD_ETM_TASK_GPIO10_EN_S)
-#define GPIOSD_ETM_TASK_GPIO10_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO10_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO10_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO10_SEL_M  (GPIOSD_ETM_TASK_GPIO10_SEL_V << GPIOSD_ETM_TASK_GPIO10_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO10_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO10_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO11_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO11_EN_M  (GPIOSD_ETM_TASK_GPIO11_EN_V << GPIOSD_ETM_TASK_GPIO11_EN_S)
-#define GPIOSD_ETM_TASK_GPIO11_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO11_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO11_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO11_SEL_M  (GPIOSD_ETM_TASK_GPIO11_SEL_V << GPIOSD_ETM_TASK_GPIO11_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO11_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO11_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P3_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac)
-/** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO12_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO12_EN_M  (GPIOSD_ETM_TASK_GPIO12_EN_V << GPIOSD_ETM_TASK_GPIO12_EN_S)
-#define GPIOSD_ETM_TASK_GPIO12_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO12_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO12_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO12_SEL_M  (GPIOSD_ETM_TASK_GPIO12_SEL_V << GPIOSD_ETM_TASK_GPIO12_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO12_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO12_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO13_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO13_EN_M  (GPIOSD_ETM_TASK_GPIO13_EN_V << GPIOSD_ETM_TASK_GPIO13_EN_S)
-#define GPIOSD_ETM_TASK_GPIO13_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO13_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO13_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO13_SEL_M  (GPIOSD_ETM_TASK_GPIO13_SEL_V << GPIOSD_ETM_TASK_GPIO13_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO13_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO13_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO14_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO14_EN_M  (GPIOSD_ETM_TASK_GPIO14_EN_V << GPIOSD_ETM_TASK_GPIO14_EN_S)
-#define GPIOSD_ETM_TASK_GPIO14_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO14_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO14_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO14_SEL_M  (GPIOSD_ETM_TASK_GPIO14_SEL_V << GPIOSD_ETM_TASK_GPIO14_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO14_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO14_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO15_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO15_EN_M  (GPIOSD_ETM_TASK_GPIO15_EN_V << GPIOSD_ETM_TASK_GPIO15_EN_S)
-#define GPIOSD_ETM_TASK_GPIO15_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO15_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO15_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO15_SEL_M  (GPIOSD_ETM_TASK_GPIO15_SEL_V << GPIOSD_ETM_TASK_GPIO15_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO15_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO15_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P4_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0)
-/** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO16_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO16_EN_M  (GPIOSD_ETM_TASK_GPIO16_EN_V << GPIOSD_ETM_TASK_GPIO16_EN_S)
-#define GPIOSD_ETM_TASK_GPIO16_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO16_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO16_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO16_SEL_M  (GPIOSD_ETM_TASK_GPIO16_SEL_V << GPIOSD_ETM_TASK_GPIO16_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO16_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO16_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO17_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO17_EN_M  (GPIOSD_ETM_TASK_GPIO17_EN_V << GPIOSD_ETM_TASK_GPIO17_EN_S)
-#define GPIOSD_ETM_TASK_GPIO17_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO17_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO17_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO17_SEL_M  (GPIOSD_ETM_TASK_GPIO17_SEL_V << GPIOSD_ETM_TASK_GPIO17_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO17_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO17_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO18_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO18_EN_M  (GPIOSD_ETM_TASK_GPIO18_EN_V << GPIOSD_ETM_TASK_GPIO18_EN_S)
-#define GPIOSD_ETM_TASK_GPIO18_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO18_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO18_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO18_SEL_M  (GPIOSD_ETM_TASK_GPIO18_SEL_V << GPIOSD_ETM_TASK_GPIO18_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO18_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO18_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO19_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO19_EN_M  (GPIOSD_ETM_TASK_GPIO19_EN_V << GPIOSD_ETM_TASK_GPIO19_EN_S)
-#define GPIOSD_ETM_TASK_GPIO19_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO19_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO19_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO19_SEL_M  (GPIOSD_ETM_TASK_GPIO19_SEL_V << GPIOSD_ETM_TASK_GPIO19_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO19_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO19_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P5_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4)
-/** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO20_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO20_EN_M  (GPIOSD_ETM_TASK_GPIO20_EN_V << GPIOSD_ETM_TASK_GPIO20_EN_S)
-#define GPIOSD_ETM_TASK_GPIO20_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO20_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO20_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO20_SEL_M  (GPIOSD_ETM_TASK_GPIO20_SEL_V << GPIOSD_ETM_TASK_GPIO20_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO20_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO20_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO21_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO21_EN_M  (GPIOSD_ETM_TASK_GPIO21_EN_V << GPIOSD_ETM_TASK_GPIO21_EN_S)
-#define GPIOSD_ETM_TASK_GPIO21_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO21_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO21_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO21_SEL_M  (GPIOSD_ETM_TASK_GPIO21_SEL_V << GPIOSD_ETM_TASK_GPIO21_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO21_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO21_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO22_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO22_EN_M  (GPIOSD_ETM_TASK_GPIO22_EN_V << GPIOSD_ETM_TASK_GPIO22_EN_S)
-#define GPIOSD_ETM_TASK_GPIO22_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO22_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO22_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO22_SEL_M  (GPIOSD_ETM_TASK_GPIO22_SEL_V << GPIOSD_ETM_TASK_GPIO22_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO22_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO22_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO23_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO23_EN_M  (GPIOSD_ETM_TASK_GPIO23_EN_V << GPIOSD_ETM_TASK_GPIO23_EN_S)
-#define GPIOSD_ETM_TASK_GPIO23_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO23_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO23_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO23_SEL_M  (GPIOSD_ETM_TASK_GPIO23_SEL_V << GPIOSD_ETM_TASK_GPIO23_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO23_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO23_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P6_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8)
-/** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO24_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO24_EN_M  (GPIOSD_ETM_TASK_GPIO24_EN_V << GPIOSD_ETM_TASK_GPIO24_EN_S)
-#define GPIOSD_ETM_TASK_GPIO24_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO24_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO24_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO24_SEL_M  (GPIOSD_ETM_TASK_GPIO24_SEL_V << GPIOSD_ETM_TASK_GPIO24_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO24_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO24_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO25_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO25_EN_M  (GPIOSD_ETM_TASK_GPIO25_EN_V << GPIOSD_ETM_TASK_GPIO25_EN_S)
-#define GPIOSD_ETM_TASK_GPIO25_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO25_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO25_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO25_SEL_M  (GPIOSD_ETM_TASK_GPIO25_SEL_V << GPIOSD_ETM_TASK_GPIO25_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO25_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO25_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO26_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO26_EN_M  (GPIOSD_ETM_TASK_GPIO26_EN_V << GPIOSD_ETM_TASK_GPIO26_EN_S)
-#define GPIOSD_ETM_TASK_GPIO26_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO26_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO26_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO26_SEL_M  (GPIOSD_ETM_TASK_GPIO26_SEL_V << GPIOSD_ETM_TASK_GPIO26_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO26_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO26_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO27_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO27_EN_M  (GPIOSD_ETM_TASK_GPIO27_EN_V << GPIOSD_ETM_TASK_GPIO27_EN_S)
-#define GPIOSD_ETM_TASK_GPIO27_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO27_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO27_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO27_SEL_M  (GPIOSD_ETM_TASK_GPIO27_SEL_V << GPIOSD_ETM_TASK_GPIO27_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO27_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO27_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P7_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc)
-/** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO28_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO28_EN_M  (GPIOSD_ETM_TASK_GPIO28_EN_V << GPIOSD_ETM_TASK_GPIO28_EN_S)
-#define GPIOSD_ETM_TASK_GPIO28_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO28_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO28_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO28_SEL_M  (GPIOSD_ETM_TASK_GPIO28_SEL_V << GPIOSD_ETM_TASK_GPIO28_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO28_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO28_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO29_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO29_EN_M  (GPIOSD_ETM_TASK_GPIO29_EN_V << GPIOSD_ETM_TASK_GPIO29_EN_S)
-#define GPIOSD_ETM_TASK_GPIO29_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO29_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO29_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO29_SEL_M  (GPIOSD_ETM_TASK_GPIO29_SEL_V << GPIOSD_ETM_TASK_GPIO29_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO29_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO29_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO30_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO30_EN_M  (GPIOSD_ETM_TASK_GPIO30_EN_V << GPIOSD_ETM_TASK_GPIO30_EN_S)
-#define GPIOSD_ETM_TASK_GPIO30_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO30_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO30_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO30_SEL_M  (GPIOSD_ETM_TASK_GPIO30_SEL_V << GPIOSD_ETM_TASK_GPIO30_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO30_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO30_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO31_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO31_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO31_EN_M  (GPIOSD_ETM_TASK_GPIO31_EN_V << GPIOSD_ETM_TASK_GPIO31_EN_S)
-#define GPIOSD_ETM_TASK_GPIO31_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO31_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO31_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO31_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO31_SEL_M  (GPIOSD_ETM_TASK_GPIO31_SEL_V << GPIOSD_ETM_TASK_GPIO31_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO31_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO31_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P8_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0)
-/** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO32_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO32_EN_M  (GPIOSD_ETM_TASK_GPIO32_EN_V << GPIOSD_ETM_TASK_GPIO32_EN_S)
-#define GPIOSD_ETM_TASK_GPIO32_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO32_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO32_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO32_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO32_SEL_M  (GPIOSD_ETM_TASK_GPIO32_SEL_V << GPIOSD_ETM_TASK_GPIO32_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO32_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO32_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO33_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO33_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO33_EN_M  (GPIOSD_ETM_TASK_GPIO33_EN_V << GPIOSD_ETM_TASK_GPIO33_EN_S)
-#define GPIOSD_ETM_TASK_GPIO33_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO33_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO33_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO33_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO33_SEL_M  (GPIOSD_ETM_TASK_GPIO33_SEL_V << GPIOSD_ETM_TASK_GPIO33_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO33_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO33_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO34_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO34_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO34_EN_M  (GPIOSD_ETM_TASK_GPIO34_EN_V << GPIOSD_ETM_TASK_GPIO34_EN_S)
-#define GPIOSD_ETM_TASK_GPIO34_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO34_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO34_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO34_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO34_SEL_M  (GPIOSD_ETM_TASK_GPIO34_SEL_V << GPIOSD_ETM_TASK_GPIO34_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO34_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO34_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO35_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO35_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO35_EN_M  (GPIOSD_ETM_TASK_GPIO35_EN_V << GPIOSD_ETM_TASK_GPIO35_EN_S)
-#define GPIOSD_ETM_TASK_GPIO35_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO35_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO35_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO35_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO35_SEL_M  (GPIOSD_ETM_TASK_GPIO35_SEL_V << GPIOSD_ETM_TASK_GPIO35_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO35_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO35_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P9_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4)
-/** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO36_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO36_EN_M  (GPIOSD_ETM_TASK_GPIO36_EN_V << GPIOSD_ETM_TASK_GPIO36_EN_S)
-#define GPIOSD_ETM_TASK_GPIO36_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO36_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO36_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO36_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO36_SEL_M  (GPIOSD_ETM_TASK_GPIO36_SEL_V << GPIOSD_ETM_TASK_GPIO36_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO36_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO36_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO37_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO37_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO37_EN_M  (GPIOSD_ETM_TASK_GPIO37_EN_V << GPIOSD_ETM_TASK_GPIO37_EN_S)
-#define GPIOSD_ETM_TASK_GPIO37_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO37_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO37_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO37_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO37_SEL_M  (GPIOSD_ETM_TASK_GPIO37_SEL_V << GPIOSD_ETM_TASK_GPIO37_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO37_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO37_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO38_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO38_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO38_EN_M  (GPIOSD_ETM_TASK_GPIO38_EN_V << GPIOSD_ETM_TASK_GPIO38_EN_S)
-#define GPIOSD_ETM_TASK_GPIO38_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO38_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO38_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO38_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO38_SEL_M  (GPIOSD_ETM_TASK_GPIO38_SEL_V << GPIOSD_ETM_TASK_GPIO38_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO38_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO38_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO39_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO39_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO39_EN_M  (GPIOSD_ETM_TASK_GPIO39_EN_V << GPIOSD_ETM_TASK_GPIO39_EN_S)
-#define GPIOSD_ETM_TASK_GPIO39_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO39_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO39_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO39_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO39_SEL_M  (GPIOSD_ETM_TASK_GPIO39_SEL_V << GPIOSD_ETM_TASK_GPIO39_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO39_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO39_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P10_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8)
-/** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO40_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO40_EN_M  (GPIOSD_ETM_TASK_GPIO40_EN_V << GPIOSD_ETM_TASK_GPIO40_EN_S)
-#define GPIOSD_ETM_TASK_GPIO40_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO40_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO40_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO40_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO40_SEL_M  (GPIOSD_ETM_TASK_GPIO40_SEL_V << GPIOSD_ETM_TASK_GPIO40_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO40_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO40_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO41_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO41_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO41_EN_M  (GPIOSD_ETM_TASK_GPIO41_EN_V << GPIOSD_ETM_TASK_GPIO41_EN_S)
-#define GPIOSD_ETM_TASK_GPIO41_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO41_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO41_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO41_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO41_SEL_M  (GPIOSD_ETM_TASK_GPIO41_SEL_V << GPIOSD_ETM_TASK_GPIO41_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO41_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO41_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO42_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO42_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO42_EN_M  (GPIOSD_ETM_TASK_GPIO42_EN_V << GPIOSD_ETM_TASK_GPIO42_EN_S)
-#define GPIOSD_ETM_TASK_GPIO42_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO42_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO42_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO42_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO42_SEL_M  (GPIOSD_ETM_TASK_GPIO42_SEL_V << GPIOSD_ETM_TASK_GPIO42_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO42_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO42_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO43_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO43_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO43_EN_M  (GPIOSD_ETM_TASK_GPIO43_EN_V << GPIOSD_ETM_TASK_GPIO43_EN_S)
-#define GPIOSD_ETM_TASK_GPIO43_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO43_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO43_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO43_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO43_SEL_M  (GPIOSD_ETM_TASK_GPIO43_SEL_V << GPIOSD_ETM_TASK_GPIO43_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO43_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO43_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P11_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc)
-/** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO44_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO44_EN_M  (GPIOSD_ETM_TASK_GPIO44_EN_V << GPIOSD_ETM_TASK_GPIO44_EN_S)
-#define GPIOSD_ETM_TASK_GPIO44_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO44_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO44_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO44_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO44_SEL_M  (GPIOSD_ETM_TASK_GPIO44_SEL_V << GPIOSD_ETM_TASK_GPIO44_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO44_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO44_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO45_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO45_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO45_EN_M  (GPIOSD_ETM_TASK_GPIO45_EN_V << GPIOSD_ETM_TASK_GPIO45_EN_S)
-#define GPIOSD_ETM_TASK_GPIO45_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO45_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO45_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO45_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO45_SEL_M  (GPIOSD_ETM_TASK_GPIO45_SEL_V << GPIOSD_ETM_TASK_GPIO45_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO45_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO45_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO46_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO46_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO46_EN_M  (GPIOSD_ETM_TASK_GPIO46_EN_V << GPIOSD_ETM_TASK_GPIO46_EN_S)
-#define GPIOSD_ETM_TASK_GPIO46_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO46_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO46_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO46_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO46_SEL_M  (GPIOSD_ETM_TASK_GPIO46_SEL_V << GPIOSD_ETM_TASK_GPIO46_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO46_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO46_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO47_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO47_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO47_EN_M  (GPIOSD_ETM_TASK_GPIO47_EN_V << GPIOSD_ETM_TASK_GPIO47_EN_S)
-#define GPIOSD_ETM_TASK_GPIO47_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO47_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO47_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO47_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO47_SEL_M  (GPIOSD_ETM_TASK_GPIO47_SEL_V << GPIOSD_ETM_TASK_GPIO47_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO47_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO47_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P12_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0)
-/** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO48_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO48_EN_M  (GPIOSD_ETM_TASK_GPIO48_EN_V << GPIOSD_ETM_TASK_GPIO48_EN_S)
-#define GPIOSD_ETM_TASK_GPIO48_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO48_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO48_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO48_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO48_SEL_M  (GPIOSD_ETM_TASK_GPIO48_SEL_V << GPIOSD_ETM_TASK_GPIO48_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO48_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO48_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO49_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO49_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO49_EN_M  (GPIOSD_ETM_TASK_GPIO49_EN_V << GPIOSD_ETM_TASK_GPIO49_EN_S)
-#define GPIOSD_ETM_TASK_GPIO49_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO49_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO49_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO49_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO49_SEL_M  (GPIOSD_ETM_TASK_GPIO49_SEL_V << GPIOSD_ETM_TASK_GPIO49_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO49_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO49_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO50_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO50_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO50_EN_M  (GPIOSD_ETM_TASK_GPIO50_EN_V << GPIOSD_ETM_TASK_GPIO50_EN_S)
-#define GPIOSD_ETM_TASK_GPIO50_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO50_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO50_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO50_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO50_SEL_M  (GPIOSD_ETM_TASK_GPIO50_SEL_V << GPIOSD_ETM_TASK_GPIO50_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO50_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO50_SEL_S  17
-/** GPIOSD_ETM_TASK_GPIO51_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO51_EN    (BIT(24))
-#define GPIOSD_ETM_TASK_GPIO51_EN_M  (GPIOSD_ETM_TASK_GPIO51_EN_V << GPIOSD_ETM_TASK_GPIO51_EN_S)
-#define GPIOSD_ETM_TASK_GPIO51_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO51_EN_S  24
-/** GPIOSD_ETM_TASK_GPIO51_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO51_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO51_SEL_M  (GPIOSD_ETM_TASK_GPIO51_SEL_V << GPIOSD_ETM_TASK_GPIO51_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO51_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO51_SEL_S  25
-
-/** GPIOSD_ETM_TASK_P13_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4)
-/** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO52_EN    (BIT(0))
-#define GPIOSD_ETM_TASK_GPIO52_EN_M  (GPIOSD_ETM_TASK_GPIO52_EN_V << GPIOSD_ETM_TASK_GPIO52_EN_S)
-#define GPIOSD_ETM_TASK_GPIO52_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO52_EN_S  0
-/** GPIOSD_ETM_TASK_GPIO52_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO52_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO52_SEL_M  (GPIOSD_ETM_TASK_GPIO52_SEL_V << GPIOSD_ETM_TASK_GPIO52_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO52_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO52_SEL_S  1
-/** GPIOSD_ETM_TASK_GPIO53_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO53_EN    (BIT(8))
-#define GPIOSD_ETM_TASK_GPIO53_EN_M  (GPIOSD_ETM_TASK_GPIO53_EN_V << GPIOSD_ETM_TASK_GPIO53_EN_S)
-#define GPIOSD_ETM_TASK_GPIO53_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO53_EN_S  8
-/** GPIOSD_ETM_TASK_GPIO53_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO53_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO53_SEL_M  (GPIOSD_ETM_TASK_GPIO53_SEL_V << GPIOSD_ETM_TASK_GPIO53_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO53_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO53_SEL_S  9
-/** GPIOSD_ETM_TASK_GPIO54_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIOSD_ETM_TASK_GPIO54_EN    (BIT(16))
-#define GPIOSD_ETM_TASK_GPIO54_EN_M  (GPIOSD_ETM_TASK_GPIO54_EN_V << GPIOSD_ETM_TASK_GPIO54_EN_S)
-#define GPIOSD_ETM_TASK_GPIO54_EN_V  0x00000001U
-#define GPIOSD_ETM_TASK_GPIO54_EN_S  16
-/** GPIOSD_ETM_TASK_GPIO54_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIOSD_ETM_TASK_GPIO54_SEL    0x00000007U
-#define GPIOSD_ETM_TASK_GPIO54_SEL_M  (GPIOSD_ETM_TASK_GPIO54_SEL_V << GPIOSD_ETM_TASK_GPIO54_SEL_S)
-#define GPIOSD_ETM_TASK_GPIO54_SEL_V  0x00000007U
-#define GPIOSD_ETM_TASK_GPIO54_SEL_S  17
-
-/** GPIOSD_VERSION_REG register
- *  Version Control Register
- */
-#define GPIOSD_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc)
-/** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952;
- *  Version control register.
- */
-#define GPIOSD_GPIO_SD_DATE    0x0FFFFFFFU
-#define GPIOSD_GPIO_SD_DATE_M  (GPIOSD_GPIO_SD_DATE_V << GPIOSD_GPIO_SD_DATE_S)
-#define GPIOSD_GPIO_SD_DATE_V  0x0FFFFFFFU
-#define GPIOSD_GPIO_SD_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/gpio_sd_struct.h b/components/soc/esp32p4/include/soc/gpio_sd_struct.h
deleted file mode 100644
index 54e9030a97..0000000000
--- a/components/soc/esp32p4/include/soc/gpio_sd_struct.h
+++ /dev/null
@@ -1,771 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: SDM Configure Registers */
-/** Type of sigmadeltan register
- *  Duty Cycle Configure Register of SDMn
- */
-typedef union {
-    struct {
-        /** sd0_in : R/W; bitpos: [7:0]; default: 0;
-         *  This field is used to configure the duty cycle of sigma delta modulation output.
-         */
-        uint32_t sd0_in:8;
-        /** sd0_prescale : R/W; bitpos: [15:8]; default: 255;
-         *  This field is used to set a divider value to divide APB clock.
-         */
-        uint32_t sd0_prescale:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} gpiosd_sigmadeltan_reg_t;
-
-/** Type of sigmadelta_misc register
- *  MISC Register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** function_clk_en : R/W; bitpos: [30]; default: 0;
-         *  Clock enable bit of sigma delta modulation.
-         */
-        uint32_t function_clk_en:1;
-        /** spi_swap : R/W; bitpos: [31]; default: 0;
-         *  Reserved.
-         */
-        uint32_t spi_swap:1;
-    };
-    uint32_t val;
-} gpiosd_sigmadelta_misc_reg_t;
-
-
-/** Group: Glitch filter Configure Registers */
-/** Type of glitch_filter_chn register
- *  Glitch Filter Configure Register of Channeln
- */
-typedef union {
-    struct {
-        /** filter_ch0_en : R/W; bitpos: [0]; default: 0;
-         *  Glitch Filter channel enable bit.
-         */
-        uint32_t filter_ch0_en:1;
-        /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
-         *  Glitch Filter input io number.
-         */
-        uint32_t filter_ch0_input_io_num:6;
-        /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
-         *  Glitch Filter window threshold.
-         */
-        uint32_t filter_ch0_window_thres:6;
-        /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
-         *  Glitch Filter window width.
-         */
-        uint32_t filter_ch0_window_width:6;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} gpiosd_glitch_filter_chn_reg_t;
-
-
-/** Group: Etm Configure Registers */
-/** Type of etm_event_chn_cfg register
- *  Etm Config register of Channeln
- */
-typedef union {
-    struct {
-        /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
-         *  Etm event channel select gpio.
-         */
-        uint32_t etm_ch0_event_sel:6;
-        uint32_t reserved_6:1;
-        /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
-         *  Etm event send enable bit.
-         */
-        uint32_t etm_ch0_event_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpiosd_etm_event_chn_cfg_reg_t;
-
-/** Type of etm_task_p0_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio0_en:1;
-        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio0_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio1_en:1;
-        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio1_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio2_en:1;
-        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio2_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio3_en:1;
-        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio3_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p0_cfg_reg_t;
-
-/** Type of etm_task_p1_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio4_en:1;
-        /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio4_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio5_en:1;
-        /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio5_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio6_en:1;
-        /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio6_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio7_en:1;
-        /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio7_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p1_cfg_reg_t;
-
-/** Type of etm_task_p2_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio8_en:1;
-        /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio8_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio9_en:1;
-        /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio9_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio10_en:1;
-        /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio10_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio11_en:1;
-        /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio11_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p2_cfg_reg_t;
-
-/** Type of etm_task_p3_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio12_en:1;
-        /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio12_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio13_en:1;
-        /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio13_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio14_en:1;
-        /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio14_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio15_en:1;
-        /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio15_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p3_cfg_reg_t;
-
-/** Type of etm_task_p4_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio16_en:1;
-        /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio16_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio17_en:1;
-        /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio17_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio18_en:1;
-        /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio18_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio19_en:1;
-        /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio19_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p4_cfg_reg_t;
-
-/** Type of etm_task_p5_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio20_en:1;
-        /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio20_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio21_en:1;
-        /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio21_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio22_en:1;
-        /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio22_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio23_en:1;
-        /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio23_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p5_cfg_reg_t;
-
-/** Type of etm_task_p6_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio24_en:1;
-        /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio24_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio25_en:1;
-        /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio25_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio26_en:1;
-        /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio26_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio27_en:1;
-        /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio27_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p6_cfg_reg_t;
-
-/** Type of etm_task_p7_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio28_en:1;
-        /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio28_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio29_en:1;
-        /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio29_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio30_en:1;
-        /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio30_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio31_en:1;
-        /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio31_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p7_cfg_reg_t;
-
-/** Type of etm_task_p8_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio32_en:1;
-        /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio32_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio33_en:1;
-        /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio33_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio34_en:1;
-        /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio34_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio35_en:1;
-        /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio35_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p8_cfg_reg_t;
-
-/** Type of etm_task_p9_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio36_en:1;
-        /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio36_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio37_en:1;
-        /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio37_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio38_en:1;
-        /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio38_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio39_en:1;
-        /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio39_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p9_cfg_reg_t;
-
-/** Type of etm_task_p10_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio40_en:1;
-        /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio40_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio41_en:1;
-        /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio41_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio42_en:1;
-        /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio42_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio43_en:1;
-        /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio43_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p10_cfg_reg_t;
-
-/** Type of etm_task_p11_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio44_en:1;
-        /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio44_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio45_en:1;
-        /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio45_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio46_en:1;
-        /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio46_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio47_en:1;
-        /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio47_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p11_cfg_reg_t;
-
-/** Type of etm_task_p12_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio48_en:1;
-        /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio48_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio49_en:1;
-        /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio49_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio50_en:1;
-        /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio50_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio51_en:1;
-        /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio51_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p12_cfg_reg_t;
-
-/** Type of etm_task_p13_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio52_en:1;
-        /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio52_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio53_en:1;
-        /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio53_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio54_en:1;
-        /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio54_sel:3;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p13_cfg_reg_t;
-
-
-/** Group: Version Register */
-/** Type of version register
- *  Version Control Register
- */
-typedef union {
-    struct {
-        /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
-         *  Version control register.
-         */
-        uint32_t gpio_sd_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_version_reg_t;
-
-
-typedef struct {
-    volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
-    uint32_t reserved_020;
-    volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
-    uint32_t reserved_028[2];
-    volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
-    uint32_t reserved_050[4];
-    volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
-    uint32_t reserved_080[8];
-    volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
-    volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
-    volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
-    volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
-    volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
-    volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
-    volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
-    volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
-    volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
-    volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
-    volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
-    volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
-    volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
-    volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
-    uint32_t reserved_0d8[9];
-    volatile gpiosd_version_reg_t version;
-} gpiosd_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h
index 92d76b0086..cdb82686cc 100644
--- a/components/soc/esp32p4/include/soc/gpio_sig_map.h
+++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h
@@ -1,10 +1,9 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_GPIO_SIG_MAP_H_
-#define _SOC_GPIO_SIG_MAP_H_
+#pragma once
 
 #define SD_CARD_CCLK_2_PAD_OUT_IDX                         0
 #define SD_CARD_CCMD_2_PAD_IN_IDX                          1
@@ -486,4 +485,3 @@
 #define SIG_IN_FUNC254_IDX                                 254
 #define SIG_IN_FUNC255_IDX                                 255
 #define SIG_IN_FUNC255_IDX                                 255
-#endif  /* _SOC_GPIO_SIG_MAP_H_ */
diff --git a/components/soc/esp32p4/include/soc/hardware_lock_reg.h b/components/soc/esp32p4/include/soc/hardware_lock_reg.h
deleted file mode 100644
index 87faa416d5..0000000000
--- a/components/soc/esp32p4/include/soc/hardware_lock_reg.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ATOMIC_ADDR_LOCK_REG register
- *  hardware lock regsiter
- */
-#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
-/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
- *  read to acquire hardware lock, write to release hardware lock
- */
-#define ATOMIC_LOCK    0x00000003U
-#define ATOMIC_LOCK_M  (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
-#define ATOMIC_LOCK_V  0x00000003U
-#define ATOMIC_LOCK_S  0
-
-/** ATOMIC_LR_ADDR_REG register
- *  gloable lr address regsiter
- */
-#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
-/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  backup gloable address
- */
-#define ATOMIC_GLOABLE_LR_ADDR    0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_ADDR_M  (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
-#define ATOMIC_GLOABLE_LR_ADDR_V  0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_ADDR_S  0
-
-/** ATOMIC_LR_VALUE_REG register
- *  gloable lr value regsiter
- */
-#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
-/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  backup gloable value
- */
-#define ATOMIC_GLOABLE_LR_VALUE    0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_VALUE_M  (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
-#define ATOMIC_GLOABLE_LR_VALUE_V  0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_VALUE_S  0
-
-/** ATOMIC_LOCK_STATUS_REG register
- *  lock status regsiter
- */
-#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
-/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
- *  read hareware lock status for debug
- */
-#define ATOMIC_LOCK_STATUS    0x00000003U
-#define ATOMIC_LOCK_STATUS_M  (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
-#define ATOMIC_LOCK_STATUS_V  0x00000003U
-#define ATOMIC_LOCK_STATUS_S  0
-
-/** ATOMIC_COUNTER_REG register
- *  wait counter register
- */
-#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
-/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
- *  delay counter
- */
-#define ATOMIC_WAIT_COUNTER    0x0000FFFFU
-#define ATOMIC_WAIT_COUNTER_M  (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
-#define ATOMIC_WAIT_COUNTER_V  0x0000FFFFU
-#define ATOMIC_WAIT_COUNTER_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hardware_lock_struct.h b/components/soc/esp32p4/include/soc/hardware_lock_struct.h
deleted file mode 100644
index 4f5f43663c..0000000000
--- a/components/soc/esp32p4/include/soc/hardware_lock_struct.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configuration registers */
-/** Type of addr_lock register
- *  hardware lock regsiter
- */
-typedef union {
-    struct {
-        /** lock : R/W; bitpos: [1:0]; default: 0;
-         *  read to acquire hardware lock, write to release hardware lock
-         */
-        uint32_t lock:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} atomic_addr_lock_reg_t;
-
-/** Type of lr_addr register
- *  gloable lr address regsiter
- */
-typedef union {
-    struct {
-        /** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  backup gloable address
-         */
-        uint32_t gloable_lr_addr:32;
-    };
-    uint32_t val;
-} atomic_lr_addr_reg_t;
-
-/** Type of lr_value register
- *  gloable lr value regsiter
- */
-typedef union {
-    struct {
-        /** gloable_lr_value : R/W; bitpos: [31:0]; default: 0;
-         *  backup gloable value
-         */
-        uint32_t gloable_lr_value:32;
-    };
-    uint32_t val;
-} atomic_lr_value_reg_t;
-
-/** Type of lock_status register
- *  lock status regsiter
- */
-typedef union {
-    struct {
-        /** lock_status : RO; bitpos: [1:0]; default: 0;
-         *  read hareware lock status for debug
-         */
-        uint32_t lock_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} atomic_lock_status_reg_t;
-
-/** Type of counter register
- *  wait counter register
- */
-typedef union {
-    struct {
-        /** wait_counter : R/W; bitpos: [15:0]; default: 0;
-         *  delay counter
-         */
-        uint32_t wait_counter:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} atomic_counter_reg_t;
-
-
-typedef struct atomic_dev_t {
-    volatile atomic_addr_lock_reg_t addr_lock;
-    volatile atomic_lr_addr_reg_t lr_addr;
-    volatile atomic_lr_value_reg_t lr_value;
-    volatile atomic_lock_status_reg_t lock_status;
-    volatile atomic_counter_reg_t counter;
-} atomic_dev_t;
-
-extern atomic_dev_t ATOMIC_LOCKER;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hinf_reg.h b/components/soc/esp32p4/include/soc/hinf_reg.h
deleted file mode 100644
index a5184fc97a..0000000000
--- a/components/soc/esp32p4/include/soc/hinf_reg.h
+++ /dev/null
@@ -1,647 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HINF_CFG_DATA0_REG register
- *  Configure sdio cis content
- */
-#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
-/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
- *  configure device id of function1 in cis
- */
-#define HINF_DEVICE_ID_FN1    0x0000FFFFU
-#define HINF_DEVICE_ID_FN1_M  (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
-#define HINF_DEVICE_ID_FN1_V  0x0000FFFFU
-#define HINF_DEVICE_ID_FN1_S  0
-/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
- *  configure user id of function1 in cis
- */
-#define HINF_USER_ID_FN1    0x0000FFFFU
-#define HINF_USER_ID_FN1_M  (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
-#define HINF_USER_ID_FN1_V  0x0000FFFFU
-#define HINF_USER_ID_FN1_S  16
-
-/** HINF_CFG_DATA1_REG register
- *  SDIO configuration register
- */
-#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
-/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
- *  Sdio clock enable
- */
-#define HINF_SDIO_ENABLE    (BIT(0))
-#define HINF_SDIO_ENABLE_M  (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
-#define HINF_SDIO_ENABLE_V  0x00000001U
-#define HINF_SDIO_ENABLE_S  0
-/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
- *  sdio function1 io ready signal in cis
- */
-#define HINF_SDIO_IOREADY1    (BIT(1))
-#define HINF_SDIO_IOREADY1_M  (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
-#define HINF_SDIO_IOREADY1_V  0x00000001U
-#define HINF_SDIO_IOREADY1_S  1
-/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
- *  Highspeed enable in cccr
- */
-#define HINF_HIGHSPEED_ENABLE    (BIT(2))
-#define HINF_HIGHSPEED_ENABLE_M  (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
-#define HINF_HIGHSPEED_ENABLE_V  0x00000001U
-#define HINF_HIGHSPEED_ENABLE_S  2
-/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
- *  highspeed mode status in cccr
- */
-#define HINF_HIGHSPEED_MODE    (BIT(3))
-#define HINF_HIGHSPEED_MODE_M  (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
-#define HINF_HIGHSPEED_MODE_V  0x00000001U
-#define HINF_HIGHSPEED_MODE_S  3
-/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
- *  sdio card detect enable
- */
-#define HINF_SDIO_CD_ENABLE    (BIT(4))
-#define HINF_SDIO_CD_ENABLE_M  (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
-#define HINF_SDIO_CD_ENABLE_V  0x00000001U
-#define HINF_SDIO_CD_ENABLE_S  4
-/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
- *  sdio function1 io ready signal in cis
- */
-#define HINF_SDIO_IOREADY2    (BIT(5))
-#define HINF_SDIO_IOREADY2_M  (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
-#define HINF_SDIO_IOREADY2_V  0x00000001U
-#define HINF_SDIO_IOREADY2_S  5
-/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
- *  mask sdio interrupt in cccr, high active
- */
-#define HINF_SDIO_INT_MASK    (BIT(6))
-#define HINF_SDIO_INT_MASK_M  (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
-#define HINF_SDIO_INT_MASK_V  0x00000001U
-#define HINF_SDIO_INT_MASK_S  6
-/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
- *  ioe2 status in cccr
- */
-#define HINF_IOENABLE2    (BIT(7))
-#define HINF_IOENABLE2_M  (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
-#define HINF_IOENABLE2_V  0x00000001U
-#define HINF_IOENABLE2_S  7
-/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
- *  card disable status in cccr
- */
-#define HINF_CD_DISABLE    (BIT(8))
-#define HINF_CD_DISABLE_M  (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
-#define HINF_CD_DISABLE_V  0x00000001U
-#define HINF_CD_DISABLE_S  8
-/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
- *  function1 eps status in fbr
- */
-#define HINF_FUNC1_EPS    (BIT(9))
-#define HINF_FUNC1_EPS_M  (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
-#define HINF_FUNC1_EPS_V  0x00000001U
-#define HINF_FUNC1_EPS_S  9
-/** HINF_EMP : RO; bitpos: [10]; default: 0;
- *  empc status in cccr
- */
-#define HINF_EMP    (BIT(10))
-#define HINF_EMP_M  (HINF_EMP_V << HINF_EMP_S)
-#define HINF_EMP_V  0x00000001U
-#define HINF_EMP_S  10
-/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
- *  ioe1 status in cccr
- */
-#define HINF_IOENABLE1    (BIT(11))
-#define HINF_IOENABLE1_M  (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
-#define HINF_IOENABLE1_V  0x00000001U
-#define HINF_IOENABLE1_S  11
-/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
- *  sdio version in cccr
- */
-#define HINF_SDIO_VER    0x00000FFFU
-#define HINF_SDIO_VER_M  (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
-#define HINF_SDIO_VER_V  0x00000FFFU
-#define HINF_SDIO_VER_S  12
-/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
- *  function2 eps status in fbr
- */
-#define HINF_FUNC2_EPS    (BIT(24))
-#define HINF_FUNC2_EPS_M  (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
-#define HINF_FUNC2_EPS_V  0x00000001U
-#define HINF_FUNC2_EPS_S  24
-/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
- *  [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
- *  in delayed cycles control,0:no delay, 1:delay 1 cycle.
- *  [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
- *  mode.
- *  [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
- *  [12]=0,posedge when highspeed mode enable.
- *  [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
- *  [28]: sdio data pad pull up enable
- */
-#define HINF_SDIO20_CONF    0x0000007FU
-#define HINF_SDIO20_CONF_M  (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
-#define HINF_SDIO20_CONF_V  0x0000007FU
-#define HINF_SDIO20_CONF_S  25
-
-/** HINF_CFG_TIMING_REG register
- *  Timing configuration registers
- */
-#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
-/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
- *  configure Ncrc parameter in sdr50/104 mode, no more than 6.
- */
-#define HINF_NCRC    0x00000007U
-#define HINF_NCRC_M  (HINF_NCRC_V << HINF_NCRC_S)
-#define HINF_NCRC_V  0x00000007U
-#define HINF_NCRC_S  0
-/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
- *  configure cycles to lower cmd after voltage is changed to 1.8V.
- */
-#define HINF_PST_END_CMD_LOW_VALUE    0x0000007FU
-#define HINF_PST_END_CMD_LOW_VALUE_M  (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
-#define HINF_PST_END_CMD_LOW_VALUE_V  0x0000007FU
-#define HINF_PST_END_CMD_LOW_VALUE_S  3
-/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
- *  configure cycles to lower data after voltage is changed to 1.8V.
- */
-#define HINF_PST_END_DATA_LOW_VALUE    0x0000003FU
-#define HINF_PST_END_DATA_LOW_VALUE_M  (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
-#define HINF_PST_END_DATA_LOW_VALUE_V  0x0000003FU
-#define HINF_PST_END_DATA_LOW_VALUE_S  10
-/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
- *  Configure the number of cycles of module clk to judge sdclk has stopped
- */
-#define HINF_SDCLK_STOP_THRES    0x000007FFU
-#define HINF_SDCLK_STOP_THRES_M  (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
-#define HINF_SDCLK_STOP_THRES_V  0x000007FFU
-#define HINF_SDCLK_STOP_THRES_S  16
-/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
- *  module clk divider to sample sdclk
- */
-#define HINF_SAMPLE_CLK_DIVIDER    0x0000000FU
-#define HINF_SAMPLE_CLK_DIVIDER_M  (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
-#define HINF_SAMPLE_CLK_DIVIDER_V  0x0000000FU
-#define HINF_SAMPLE_CLK_DIVIDER_S  28
-
-/** HINF_CFG_UPDATE_REG register
- *  update sdio configurations
- */
-#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
-/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
- *  update the timing configurations
- */
-#define HINF_CONF_UPDATE    (BIT(0))
-#define HINF_CONF_UPDATE_M  (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
-#define HINF_CONF_UPDATE_V  0x00000001U
-#define HINF_CONF_UPDATE_S  0
-
-/** HINF_CFG_DATA7_REG register
- *  SDIO configuration register
- */
-#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
-/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
- *  configure cis addr 318 and 574
- */
-#define HINF_PIN_STATE    0x000000FFU
-#define HINF_PIN_STATE_M  (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
-#define HINF_PIN_STATE_V  0x000000FFU
-#define HINF_PIN_STATE_S  0
-/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
- *  configure cis addr 312, 315, 568 and 571
- */
-#define HINF_CHIP_STATE    0x000000FFU
-#define HINF_CHIP_STATE_M  (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
-#define HINF_CHIP_STATE_V  0x000000FFU
-#define HINF_CHIP_STATE_S  8
-/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
- *  soft reset control for sdio module
- */
-#define HINF_SDIO_RST    (BIT(16))
-#define HINF_SDIO_RST_M  (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
-#define HINF_SDIO_RST_V  0x00000001U
-#define HINF_SDIO_RST_S  16
-/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
- *  sdio io ready, high enable
- */
-#define HINF_SDIO_IOREADY0    (BIT(17))
-#define HINF_SDIO_IOREADY0_M  (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
-#define HINF_SDIO_IOREADY0_V  0x00000001U
-#define HINF_SDIO_IOREADY0_S  17
-/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
- *  sdio memory power down, high active
- */
-#define HINF_SDIO_MEM_PD    (BIT(18))
-#define HINF_SDIO_MEM_PD_M  (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
-#define HINF_SDIO_MEM_PD_V  0x00000001U
-#define HINF_SDIO_MEM_PD_S  18
-/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
- *  enable sdio interrupt on data1 line
- */
-#define HINF_ESDIO_DATA1_INT_EN    (BIT(19))
-#define HINF_ESDIO_DATA1_INT_EN_M  (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
-#define HINF_ESDIO_DATA1_INT_EN_V  0x00000001U
-#define HINF_ESDIO_DATA1_INT_EN_S  19
-/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
- *  control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
- */
-#define HINF_SDIO_SWITCH_VOLT_SW    (BIT(20))
-#define HINF_SDIO_SWITCH_VOLT_SW_M  (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
-#define HINF_SDIO_SWITCH_VOLT_SW_V  0x00000001U
-#define HINF_SDIO_SWITCH_VOLT_SW_S  20
-/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
- *  enable block length to be fixed to 512 bytes in ddr50 mode
- */
-#define HINF_DDR50_BLK_LEN_FIX_EN    (BIT(21))
-#define HINF_DDR50_BLK_LEN_FIX_EN_M  (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
-#define HINF_DDR50_BLK_LEN_FIX_EN_V  0x00000001U
-#define HINF_DDR50_BLK_LEN_FIX_EN_S  21
-/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
- *  sdio apb clock for configuration force on control:0-gating,1-force on.
- */
-#define HINF_CLK_EN    (BIT(22))
-#define HINF_CLK_EN_M  (HINF_CLK_EN_V << HINF_CLK_EN_S)
-#define HINF_CLK_EN_V  0x00000001U
-#define HINF_CLK_EN_S  22
-/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
- *  configure if support sdr50 mode in cccr
- */
-#define HINF_SDDR50    (BIT(23))
-#define HINF_SDDR50_M  (HINF_SDDR50_V << HINF_SDDR50_S)
-#define HINF_SDDR50_V  0x00000001U
-#define HINF_SDDR50_S  23
-/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
- *  configure if support sdr104 mode in cccr
- */
-#define HINF_SSDR104    (BIT(24))
-#define HINF_SSDR104_M  (HINF_SSDR104_V << HINF_SSDR104_S)
-#define HINF_SSDR104_V  0x00000001U
-#define HINF_SSDR104_S  24
-/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
- *  configure if support ddr50 mode in cccr
- */
-#define HINF_SSDR50    (BIT(25))
-#define HINF_SSDR50_M  (HINF_SSDR50_V << HINF_SSDR50_S)
-#define HINF_SSDR50_V  0x00000001U
-#define HINF_SSDR50_S  25
-/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
- *  configure if support driver type D in cccr
- */
-#define HINF_SDTD    (BIT(26))
-#define HINF_SDTD_M  (HINF_SDTD_V << HINF_SDTD_S)
-#define HINF_SDTD_V  0x00000001U
-#define HINF_SDTD_S  26
-/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
- *  configure if support driver type A in cccr
- */
-#define HINF_SDTA    (BIT(27))
-#define HINF_SDTA_M  (HINF_SDTA_V << HINF_SDTA_S)
-#define HINF_SDTA_V  0x00000001U
-#define HINF_SDTA_S  27
-/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
- *  configure if support driver type C in cccr
- */
-#define HINF_SDTC    (BIT(28))
-#define HINF_SDTC_M  (HINF_SDTC_V << HINF_SDTC_S)
-#define HINF_SDTC_V  0x00000001U
-#define HINF_SDTC_S  28
-/** HINF_SAI : R/W; bitpos: [29]; default: 1;
- *  configure if support asynchronous interrupt in cccr
- */
-#define HINF_SAI    (BIT(29))
-#define HINF_SAI_M  (HINF_SAI_V << HINF_SAI_S)
-#define HINF_SAI_V  0x00000001U
-#define HINF_SAI_S  29
-/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0;
- *  clear sdio_wake_up signal after the chip wakes up
- */
-#define HINF_SDIO_WAKEUP_CLR    (BIT(30))
-#define HINF_SDIO_WAKEUP_CLR_M  (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
-#define HINF_SDIO_WAKEUP_CLR_V  0x00000001U
-#define HINF_SDIO_WAKEUP_CLR_S  30
-
-/** HINF_CIS_CONF_W0_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
-/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 39~36
- */
-#define HINF_CIS_CONF_W0    0xFFFFFFFFU
-#define HINF_CIS_CONF_W0_M  (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
-#define HINF_CIS_CONF_W0_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W0_S  0
-
-/** HINF_CIS_CONF_W1_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
-/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 43~40
- */
-#define HINF_CIS_CONF_W1    0xFFFFFFFFU
-#define HINF_CIS_CONF_W1_M  (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
-#define HINF_CIS_CONF_W1_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W1_S  0
-
-/** HINF_CIS_CONF_W2_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
-/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 47~44
- */
-#define HINF_CIS_CONF_W2    0xFFFFFFFFU
-#define HINF_CIS_CONF_W2_M  (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
-#define HINF_CIS_CONF_W2_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W2_S  0
-
-/** HINF_CIS_CONF_W3_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
-/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 51~48
- */
-#define HINF_CIS_CONF_W3    0xFFFFFFFFU
-#define HINF_CIS_CONF_W3_M  (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
-#define HINF_CIS_CONF_W3_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W3_S  0
-
-/** HINF_CIS_CONF_W4_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
-/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 55~52
- */
-#define HINF_CIS_CONF_W4    0xFFFFFFFFU
-#define HINF_CIS_CONF_W4_M  (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
-#define HINF_CIS_CONF_W4_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W4_S  0
-
-/** HINF_CIS_CONF_W5_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
-/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 59~56
- */
-#define HINF_CIS_CONF_W5    0xFFFFFFFFU
-#define HINF_CIS_CONF_W5_M  (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
-#define HINF_CIS_CONF_W5_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W5_S  0
-
-/** HINF_CIS_CONF_W6_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
-/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 63~60
- */
-#define HINF_CIS_CONF_W6    0xFFFFFFFFU
-#define HINF_CIS_CONF_W6_M  (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
-#define HINF_CIS_CONF_W6_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W6_S  0
-
-/** HINF_CIS_CONF_W7_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
-/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 67~64
- */
-#define HINF_CIS_CONF_W7    0xFFFFFFFFU
-#define HINF_CIS_CONF_W7_M  (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
-#define HINF_CIS_CONF_W7_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W7_S  0
-
-/** HINF_CFG_DATA16_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
-/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
- *  configure device id of function2 in cis
- */
-#define HINF_DEVICE_ID_FN2    0x0000FFFFU
-#define HINF_DEVICE_ID_FN2_M  (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
-#define HINF_DEVICE_ID_FN2_V  0x0000FFFFU
-#define HINF_DEVICE_ID_FN2_S  0
-/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
- *  configure user id of function2 in cis
- */
-#define HINF_USER_ID_FN2    0x0000FFFFU
-#define HINF_USER_ID_FN2_M  (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
-#define HINF_USER_ID_FN2_V  0x0000FFFFU
-#define HINF_USER_ID_FN2_S  16
-
-/** HINF_CFG_UHS1_INT_MODE_REG register
- *  configure int to start and end ahead of time in uhs1 mode
- */
-#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
-/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
- *  intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INTOE_END_AHEAD_MODE    0x00000003U
-#define HINF_INTOE_END_AHEAD_MODE_M  (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
-#define HINF_INTOE_END_AHEAD_MODE_V  0x00000003U
-#define HINF_INTOE_END_AHEAD_MODE_S  0
-/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
- *  int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INT_END_AHEAD_MODE    0x00000003U
-#define HINF_INT_END_AHEAD_MODE_M  (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
-#define HINF_INT_END_AHEAD_MODE_V  0x00000003U
-#define HINF_INT_END_AHEAD_MODE_S  2
-/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
- *  intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INTOE_ST_AHEAD_MODE    0x00000003U
-#define HINF_INTOE_ST_AHEAD_MODE_M  (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
-#define HINF_INTOE_ST_AHEAD_MODE_V  0x00000003U
-#define HINF_INTOE_ST_AHEAD_MODE_S  4
-/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
- *  int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INT_ST_AHEAD_MODE    0x00000003U
-#define HINF_INT_ST_AHEAD_MODE_M  (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
-#define HINF_INT_ST_AHEAD_MODE_V  0x00000003U
-#define HINF_INT_ST_AHEAD_MODE_S  6
-
-/** HINF_CONF_STATUS_REG register
- *  func0 config0 status
- */
-#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
-/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
- *  func0 config0 (addr: 0x20f0 ) status
- */
-#define HINF_FUNC0_CONFIG0    0x000000FFU
-#define HINF_FUNC0_CONFIG0_M  (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
-#define HINF_FUNC0_CONFIG0_V  0x000000FFU
-#define HINF_FUNC0_CONFIG0_S  0
-/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
- *  sdr25 status
- */
-#define HINF_SDR25_ST    (BIT(8))
-#define HINF_SDR25_ST_M  (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
-#define HINF_SDR25_ST_V  0x00000001U
-#define HINF_SDR25_ST_S  8
-/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
- *  sdr50 status
- */
-#define HINF_SDR50_ST    (BIT(9))
-#define HINF_SDR50_ST_M  (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
-#define HINF_SDR50_ST_V  0x00000001U
-#define HINF_SDR50_ST_S  9
-/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
- *  sdr104 status
- */
-#define HINF_SDR104_ST    (BIT(10))
-#define HINF_SDR104_ST_M  (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
-#define HINF_SDR104_ST_V  0x00000001U
-#define HINF_SDR104_ST_S  10
-/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
- *  ddr50 status
- */
-#define HINF_DDR50_ST    (BIT(11))
-#define HINF_DDR50_ST_M  (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
-#define HINF_DDR50_ST_V  0x00000001U
-#define HINF_DDR50_ST_S  11
-/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
- *  tune_st fsm status
- */
-#define HINF_TUNE_ST    0x00000007U
-#define HINF_TUNE_ST_M  (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
-#define HINF_TUNE_ST_V  0x00000007U
-#define HINF_TUNE_ST_S  12
-/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
- *  sdio switch voltage status:0-3.3V, 1-1.8V.
- */
-#define HINF_SDIO_SWITCH_VOLT_ST    (BIT(15))
-#define HINF_SDIO_SWITCH_VOLT_ST_M  (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
-#define HINF_SDIO_SWITCH_VOLT_ST_V  0x00000001U
-#define HINF_SDIO_SWITCH_VOLT_ST_S  15
-/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
- *  sdio switch voltage ldo ready
- */
-#define HINF_SDIO_SWITCH_END    (BIT(16))
-#define HINF_SDIO_SWITCH_END_M  (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
-#define HINF_SDIO_SWITCH_END_V  0x00000001U
-#define HINF_SDIO_SWITCH_END_S  16
-
-/** HINF_SDIO_SLAVE_ECO_LOW_REG register
- *  sdio_slave redundant control registers
- */
-#define HINF_SDIO_SLAVE_ECO_LOW_REG (DR_REG_HINF_BASE + 0xa4)
-/** HINF_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  redundant registers for sdio_slave
- */
-#define HINF_RDN_ECO_LOW    0xFFFFFFFFU
-#define HINF_RDN_ECO_LOW_M  (HINF_RDN_ECO_LOW_V << HINF_RDN_ECO_LOW_S)
-#define HINF_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define HINF_RDN_ECO_LOW_S  0
-
-/** HINF_SDIO_SLAVE_ECO_HIGH_REG register
- *  sdio_slave redundant control registers
- */
-#define HINF_SDIO_SLAVE_ECO_HIGH_REG (DR_REG_HINF_BASE + 0xa8)
-/** HINF_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  redundant registers for sdio_slave
- */
-#define HINF_RDN_ECO_HIGH    0xFFFFFFFFU
-#define HINF_RDN_ECO_HIGH_M  (HINF_RDN_ECO_HIGH_V << HINF_RDN_ECO_HIGH_S)
-#define HINF_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define HINF_RDN_ECO_HIGH_S  0
-
-/** HINF_SDIO_SLAVE_ECO_CONF_REG register
- *  sdio_slave redundant control registers
- */
-#define HINF_SDIO_SLAVE_ECO_CONF_REG (DR_REG_HINF_BASE + 0xac)
-/** HINF_SDIO_SLAVE_RDN_RESULT : RO; bitpos: [0]; default: 0;
- *  redundant registers for sdio_slave
- */
-#define HINF_SDIO_SLAVE_RDN_RESULT    (BIT(0))
-#define HINF_SDIO_SLAVE_RDN_RESULT_M  (HINF_SDIO_SLAVE_RDN_RESULT_V << HINF_SDIO_SLAVE_RDN_RESULT_S)
-#define HINF_SDIO_SLAVE_RDN_RESULT_V  0x00000001U
-#define HINF_SDIO_SLAVE_RDN_RESULT_S  0
-/** HINF_SDIO_SLAVE_RDN_ENA : R/W; bitpos: [1]; default: 0;
- *  redundant registers for sdio_slave
- */
-#define HINF_SDIO_SLAVE_RDN_ENA    (BIT(1))
-#define HINF_SDIO_SLAVE_RDN_ENA_M  (HINF_SDIO_SLAVE_RDN_ENA_V << HINF_SDIO_SLAVE_RDN_ENA_S)
-#define HINF_SDIO_SLAVE_RDN_ENA_V  0x00000001U
-#define HINF_SDIO_SLAVE_RDN_ENA_S  1
-/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT : RO; bitpos: [2]; default: 0;
- *  redundant registers for sdio_slave
- */
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT    (BIT(2))
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_M  (HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S)
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V  0x00000001U
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S  2
-/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA : R/W; bitpos: [3]; default: 0;
- *  redundant registers for sdio_slave
- */
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA    (BIT(3))
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_M  (HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S)
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V  0x00000001U
-#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S  3
-/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT : RO; bitpos: [4]; default: 0;
- *  redundant registers for sdio_slave
- */
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT    (BIT(4))
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_M  (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S)
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V  0x00000001U
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S  4
-/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA : R/W; bitpos: [5]; default: 0;
- *  redundant registers for sdio_slave
- */
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA    (BIT(5))
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_M  (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S)
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V  0x00000001U
-#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S  5
-
-/** HINF_SDIO_SLAVE_LDO_CONF_REG register
- *  sdio slave ldo control register
- */
-#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
-/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
- *  control ldo ready signal by sdio slave itself
- */
-#define HINF_LDO_READY_CTL_IN_EN    (BIT(0))
-#define HINF_LDO_READY_CTL_IN_EN_M  (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
-#define HINF_LDO_READY_CTL_IN_EN_V  0x00000001U
-#define HINF_LDO_READY_CTL_IN_EN_S  0
-/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
- *  configure ldo ready counting threshold value, the actual counting target is
- *  2^(ldo_ready_thres)-1
- */
-#define HINF_LDO_READY_THRES    0x0000001FU
-#define HINF_LDO_READY_THRES_M  (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
-#define HINF_LDO_READY_THRES_V  0x0000001FU
-#define HINF_LDO_READY_THRES_S  1
-/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
- *  ignore ldo ready signal
- */
-#define HINF_LDO_READY_IGNORE_EN    (BIT(6))
-#define HINF_LDO_READY_IGNORE_EN_M  (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
-#define HINF_LDO_READY_IGNORE_EN_V  0x00000001U
-#define HINF_LDO_READY_IGNORE_EN_S  6
-
-/** HINF_SDIO_DATE_REG register
- *  ******* Description ***********
- */
-#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
-/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208;
- *  sdio version date.
- */
-#define HINF_SDIO_DATE    0xFFFFFFFFU
-#define HINF_SDIO_DATE_M  (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
-#define HINF_SDIO_DATE_V  0xFFFFFFFFU
-#define HINF_SDIO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hinf_struct.h b/components/soc/esp32p4/include/soc/hinf_struct.h
deleted file mode 100644
index 858db7b848..0000000000
--- a/components/soc/esp32p4/include/soc/hinf_struct.h
+++ /dev/null
@@ -1,555 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration registers */
-/** Type of cfg_data0 register
- *  Configure sdio cis content
- */
-typedef union {
-    struct {
-        /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
-         *  configure device id of function1 in cis
-         */
-        uint32_t device_id_fn1:16;
-        /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
-         *  configure user id of function1 in cis
-         */
-        uint32_t user_id_fn1:16;
-    };
-    uint32_t val;
-} hinf_cfg_data0_reg_t;
-
-/** Type of cfg_data1 register
- *  SDIO configuration register
- */
-typedef union {
-    struct {
-        /** sdio_enable : R/W; bitpos: [0]; default: 1;
-         *  Sdio clock enable
-         */
-        uint32_t sdio_enable:1;
-        /** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
-         *  sdio function1 io ready signal in cis
-         */
-        uint32_t sdio_ioready1:1;
-        /** highspeed_enable : R/W; bitpos: [2]; default: 0;
-         *  Highspeed enable in cccr
-         */
-        uint32_t highspeed_enable:1;
-        /** highspeed_mode : RO; bitpos: [3]; default: 0;
-         *  highspeed mode status in cccr
-         */
-        uint32_t highspeed_mode:1;
-        /** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
-         *  sdio card detect enable
-         */
-        uint32_t sdio_cd_enable:1;
-        /** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
-         *  sdio function1 io ready signal in cis
-         */
-        uint32_t sdio_ioready2:1;
-        /** sdio_int_mask : R/W; bitpos: [6]; default: 0;
-         *  mask sdio interrupt in cccr, high active
-         */
-        uint32_t sdio_int_mask:1;
-        /** ioenable2 : RO; bitpos: [7]; default: 0;
-         *  ioe2 status in cccr
-         */
-        uint32_t ioenable2:1;
-        /** cd_disable : RO; bitpos: [8]; default: 0;
-         *  card disable status in cccr
-         */
-        uint32_t cd_disable:1;
-        /** func1_eps : RO; bitpos: [9]; default: 0;
-         *  function1 eps status in fbr
-         */
-        uint32_t func1_eps:1;
-        /** emp : RO; bitpos: [10]; default: 0;
-         *  empc status in cccr
-         */
-        uint32_t emp:1;
-        /** ioenable1 : RO; bitpos: [11]; default: 0;
-         *  ioe1 status in cccr
-         */
-        uint32_t ioenable1:1;
-        /** sdio_ver : R/W; bitpos: [23:12]; default: 562;
-         *  sdio version in cccr
-         */
-        uint32_t sdio_ver:12;
-        /** func2_eps : RO; bitpos: [24]; default: 0;
-         *  function2 eps status in fbr
-         */
-        uint32_t func2_eps:1;
-        /** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
-         *  [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
-         *  in delayed cycles control,0:no delay, 1:delay 1 cycle.
-         *  [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
-         *  mode.
-         *  [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
-         *  [12]=0,posedge when highspeed mode enable.
-         *  [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
-         *  [28]: sdio data pad pull up enable
-         */
-        uint32_t sdio20_conf:7;
-    };
-    uint32_t val;
-} hinf_cfg_data1_reg_t;
-
-/** Type of cfg_timing register
- *  Timing configuration registers
- */
-typedef union {
-    struct {
-        /** ncrc : R/W; bitpos: [2:0]; default: 2;
-         *  configure Ncrc parameter in sdr50/104 mode, no more than 6.
-         */
-        uint32_t ncrc:3;
-        /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
-         *  configure cycles to lower cmd after voltage is changed to 1.8V.
-         */
-        uint32_t pst_end_cmd_low_value:7;
-        /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
-         *  configure cycles to lower data after voltage is changed to 1.8V.
-         */
-        uint32_t pst_end_data_low_value:6;
-        /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
-         *  Configure the number of cycles of module clk to judge sdclk has stopped
-         */
-        uint32_t sdclk_stop_thres:11;
-        uint32_t reserved_27:1;
-        /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
-         *  module clk divider to sample sdclk
-         */
-        uint32_t sample_clk_divider:4;
-    };
-    uint32_t val;
-} hinf_cfg_timing_reg_t;
-
-/** Type of cfg_update register
- *  update sdio configurations
- */
-typedef union {
-    struct {
-        /** conf_update : WT; bitpos: [0]; default: 0;
-         *  update the timing configurations
-         */
-        uint32_t conf_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hinf_cfg_update_reg_t;
-
-/** Type of cfg_data7 register
- *  SDIO configuration register
- */
-typedef union {
-    struct {
-        /** pin_state : R/W; bitpos: [7:0]; default: 0;
-         *  configure cis addr 318 and 574
-         */
-        uint32_t pin_state:8;
-        /** chip_state : R/W; bitpos: [15:8]; default: 0;
-         *  configure cis addr 312, 315, 568 and 571
-         */
-        uint32_t chip_state:8;
-        /** sdio_rst : R/W; bitpos: [16]; default: 0;
-         *  soft reset control for sdio module
-         */
-        uint32_t sdio_rst:1;
-        /** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
-         *  sdio io ready, high enable
-         */
-        uint32_t sdio_ioready0:1;
-        /** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
-         *  sdio memory power down, high active
-         */
-        uint32_t sdio_mem_pd:1;
-        /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
-         *  enable sdio interrupt on data1 line
-         */
-        uint32_t esdio_data1_int_en:1;
-        /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
-         *  control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
-         */
-        uint32_t sdio_switch_volt_sw:1;
-        /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
-         *  enable block length to be fixed to 512 bytes in ddr50 mode
-         */
-        uint32_t ddr50_blk_len_fix_en:1;
-        /** clk_en : R/W; bitpos: [22]; default: 0;
-         *  sdio apb clock for configuration force on control:0-gating,1-force on.
-         */
-        uint32_t clk_en:1;
-        /** sddr50 : R/W; bitpos: [23]; default: 1;
-         *  configure if support sdr50 mode in cccr
-         */
-        uint32_t sddr50:1;
-        /** ssdr104 : R/W; bitpos: [24]; default: 1;
-         *  configure if support sdr104 mode in cccr
-         */
-        uint32_t ssdr104:1;
-        /** ssdr50 : R/W; bitpos: [25]; default: 1;
-         *  configure if support ddr50 mode in cccr
-         */
-        uint32_t ssdr50:1;
-        /** sdtd : R/W; bitpos: [26]; default: 0;
-         *  configure if support driver type D in cccr
-         */
-        uint32_t sdtd:1;
-        /** sdta : R/W; bitpos: [27]; default: 0;
-         *  configure if support driver type A in cccr
-         */
-        uint32_t sdta:1;
-        /** sdtc : R/W; bitpos: [28]; default: 0;
-         *  configure if support driver type C in cccr
-         */
-        uint32_t sdtc:1;
-        /** sai : R/W; bitpos: [29]; default: 1;
-         *  configure if support asynchronous interrupt in cccr
-         */
-        uint32_t sai:1;
-        /** sdio_wakeup_clr : WT; bitpos: [30]; default: 0;
-         *  clear sdio_wake_up signal after the chip wakes up
-         */
-        uint32_t sdio_wakeup_clr:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} hinf_cfg_data7_reg_t;
-
-/** Type of cis_conf_w0 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 39~36
-         */
-        uint32_t cis_conf_w0:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w0_reg_t;
-
-/** Type of cis_conf_w1 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 43~40
-         */
-        uint32_t cis_conf_w1:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w1_reg_t;
-
-/** Type of cis_conf_w2 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 47~44
-         */
-        uint32_t cis_conf_w2:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w2_reg_t;
-
-/** Type of cis_conf_w3 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 51~48
-         */
-        uint32_t cis_conf_w3:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w3_reg_t;
-
-/** Type of cis_conf_w4 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 55~52
-         */
-        uint32_t cis_conf_w4:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w4_reg_t;
-
-/** Type of cis_conf_w5 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 59~56
-         */
-        uint32_t cis_conf_w5:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w5_reg_t;
-
-/** Type of cis_conf_w6 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 63~60
-         */
-        uint32_t cis_conf_w6:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w6_reg_t;
-
-/** Type of cis_conf_w7 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 67~64
-         */
-        uint32_t cis_conf_w7:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w7_reg_t;
-
-/** Type of cfg_data16 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
-         *  configure device id of function2 in cis
-         */
-        uint32_t device_id_fn2:16;
-        /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
-         *  configure user id of function2 in cis
-         */
-        uint32_t user_id_fn2:16;
-    };
-    uint32_t val;
-} hinf_cfg_data16_reg_t;
-
-/** Type of cfg_uhs1_int_mode register
- *  configure int to start and end ahead of time in uhs1 mode
- */
-typedef union {
-    struct {
-        /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
-         *  intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t intoe_end_ahead_mode:2;
-        /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
-         *  int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t int_end_ahead_mode:2;
-        /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
-         *  intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t intoe_st_ahead_mode:2;
-        /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
-         *  int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t int_st_ahead_mode:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hinf_cfg_uhs1_int_mode_reg_t;
-
-/** Type of sdio_slave_eco_low register
- *  sdio_slave redundant control registers
- */
-typedef union {
-    struct {
-        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t rdn_eco_low:32;
-    };
-    uint32_t val;
-} hinf_sdio_slave_eco_low_reg_t;
-
-/** Type of sdio_slave_eco_high register
- *  sdio_slave redundant control registers
- */
-typedef union {
-    struct {
-        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t rdn_eco_high:32;
-    };
-    uint32_t val;
-} hinf_sdio_slave_eco_high_reg_t;
-
-/** Type of sdio_slave_eco_conf register
- *  sdio_slave redundant control registers
- */
-typedef union {
-    struct {
-        /** sdio_slave_rdn_result : RO; bitpos: [0]; default: 0;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t sdio_slave_rdn_result:1;
-        /** sdio_slave_rdn_ena : R/W; bitpos: [1]; default: 0;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t sdio_slave_rdn_ena:1;
-        /** sdio_slave_sdio_clk_rdn_result : RO; bitpos: [2]; default: 0;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t sdio_slave_sdio_clk_rdn_result:1;
-        /** sdio_slave_sdio_clk_rdn_ena : R/W; bitpos: [3]; default: 0;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t sdio_slave_sdio_clk_rdn_ena:1;
-        /** sdio_slave_sdclk_pad_rdn_result : RO; bitpos: [4]; default: 0;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t sdio_slave_sdclk_pad_rdn_result:1;
-        /** sdio_slave_sdclk_pad_rdn_ena : R/W; bitpos: [5]; default: 0;
-         *  redundant registers for sdio_slave
-         */
-        uint32_t sdio_slave_sdclk_pad_rdn_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hinf_sdio_slave_eco_conf_reg_t;
-
-/** Type of sdio_slave_ldo_conf register
- *  sdio slave ldo control register
- */
-typedef union {
-    struct {
-        /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
-         *  control ldo ready signal by sdio slave itself
-         */
-        uint32_t ldo_ready_ctl_in_en:1;
-        /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
-         *  configure ldo ready counting threshold value, the actual counting target is
-         *  2^(ldo_ready_thres)-1
-         */
-        uint32_t ldo_ready_thres:5;
-        /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
-         *  ignore ldo ready signal
-         */
-        uint32_t ldo_ready_ignore_en:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hinf_sdio_slave_ldo_conf_reg_t;
-
-
-/** Group: Status registers */
-/** Type of conf_status register
- *  func0 config0 status
- */
-typedef union {
-    struct {
-        /** func0_config0 : RO; bitpos: [7:0]; default: 0;
-         *  func0 config0 (addr: 0x20f0 ) status
-         */
-        uint32_t func0_config0:8;
-        /** sdr25_st : RO; bitpos: [8]; default: 0;
-         *  sdr25 status
-         */
-        uint32_t sdr25_st:1;
-        /** sdr50_st : RO; bitpos: [9]; default: 0;
-         *  sdr50 status
-         */
-        uint32_t sdr50_st:1;
-        /** sdr104_st : RO; bitpos: [10]; default: 0;
-         *  sdr104 status
-         */
-        uint32_t sdr104_st:1;
-        /** ddr50_st : RO; bitpos: [11]; default: 0;
-         *  ddr50 status
-         */
-        uint32_t ddr50_st:1;
-        /** tune_st : RO; bitpos: [14:12]; default: 0;
-         *  tune_st fsm status
-         */
-        uint32_t tune_st:3;
-        /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
-         *  sdio switch voltage status:0-3.3V, 1-1.8V.
-         */
-        uint32_t sdio_switch_volt_st:1;
-        /** sdio_switch_end : RO; bitpos: [16]; default: 0;
-         *  sdio switch voltage ldo ready
-         */
-        uint32_t sdio_switch_end:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} hinf_conf_status_reg_t;
-
-
-/** Group: Version register */
-/** Type of sdio_date register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** sdio_date : R/W; bitpos: [31:0]; default: 35664208;
-         *  sdio version date.
-         */
-        uint32_t sdio_date:32;
-    };
-    uint32_t val;
-} hinf_sdio_date_reg_t;
-
-
-typedef struct hinf_dev_t {
-    volatile hinf_cfg_data0_reg_t cfg_data0;
-    volatile hinf_cfg_data1_reg_t cfg_data1;
-    volatile hinf_cfg_timing_reg_t cfg_timing;
-    volatile hinf_cfg_update_reg_t cfg_update;
-    uint32_t reserved_010[3];
-    volatile hinf_cfg_data7_reg_t cfg_data7;
-    volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
-    volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
-    volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
-    volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
-    volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
-    volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
-    volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
-    volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
-    volatile hinf_cfg_data16_reg_t cfg_data16;
-    volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
-    uint32_t reserved_048[3];
-    volatile hinf_conf_status_reg_t conf_status;
-    uint32_t reserved_058[19];
-    volatile hinf_sdio_slave_eco_low_reg_t sdio_slave_eco_low;
-    volatile hinf_sdio_slave_eco_high_reg_t sdio_slave_eco_high;
-    volatile hinf_sdio_slave_eco_conf_reg_t sdio_slave_eco_conf;
-    volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
-    uint32_t reserved_0b4[18];
-    volatile hinf_sdio_date_reg_t sdio_date;
-} hinf_dev_t;
-
-extern hinf_dev_t HINF;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/host_reg.h b/components/soc/esp32p4/include/soc/host_reg.h
deleted file mode 100644
index c508e5ab36..0000000000
--- a/components/soc/esp32p4/include/soc/host_reg.h
+++ /dev/null
@@ -1,3883 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SLCHOST_FUNC2_0_REG register
- *  *******Description***********
- */
-#define SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10)
-/** SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_FUNC2_INT    (BIT(24))
-#define SLCHOST_SLC_FUNC2_INT_M  (SLCHOST_SLC_FUNC2_INT_V << SLCHOST_SLC_FUNC2_INT_S)
-#define SLCHOST_SLC_FUNC2_INT_V  0x00000001U
-#define SLCHOST_SLC_FUNC2_INT_S  24
-
-/** SLCHOST_FUNC2_1_REG register
- *  *******Description***********
- */
-#define SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14)
-/** SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_FUNC2_INT_EN    (BIT(0))
-#define SLCHOST_SLC_FUNC2_INT_EN_M  (SLCHOST_SLC_FUNC2_INT_EN_V << SLCHOST_SLC_FUNC2_INT_EN_S)
-#define SLCHOST_SLC_FUNC2_INT_EN_V  0x00000001U
-#define SLCHOST_SLC_FUNC2_INT_EN_S  0
-
-/** SLCHOST_FUNC2_2_REG register
- *  *******Description***********
- */
-#define SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
-/** SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1;
- *  *******Description***********
- */
-#define SLCHOST_SLC_FUNC1_MDSTAT    (BIT(0))
-#define SLCHOST_SLC_FUNC1_MDSTAT_M  (SLCHOST_SLC_FUNC1_MDSTAT_V << SLCHOST_SLC_FUNC1_MDSTAT_S)
-#define SLCHOST_SLC_FUNC1_MDSTAT_V  0x00000001U
-#define SLCHOST_SLC_FUNC1_MDSTAT_S  0
-
-/** SLCHOST_GPIO_STATUS0_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
-/** SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT0    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT0_M  (SLCHOST_GPIO_SDIO_INT0_V << SLCHOST_GPIO_SDIO_INT0_S)
-#define SLCHOST_GPIO_SDIO_INT0_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT0_S  0
-
-/** SLCHOST_GPIO_STATUS1_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
-/** SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT1    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT1_M  (SLCHOST_GPIO_SDIO_INT1_V << SLCHOST_GPIO_SDIO_INT1_S)
-#define SLCHOST_GPIO_SDIO_INT1_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT1_S  0
-
-/** SLCHOST_GPIO_IN0_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3c)
-/** SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_IN0    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN0_M  (SLCHOST_GPIO_SDIO_IN0_V << SLCHOST_GPIO_SDIO_IN0_S)
-#define SLCHOST_GPIO_SDIO_IN0_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN0_S  0
-
-/** SLCHOST_GPIO_IN1_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
-/** SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_IN1    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN1_M  (SLCHOST_GPIO_SDIO_IN1_V << SLCHOST_GPIO_SDIO_IN1_S)
-#define SLCHOST_GPIO_SDIO_IN1_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN1_S  0
-
-/** SLCHOST_SLC0HOST_TOKEN_RDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
-/** SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0    0x00000FFFU
-#define SLCHOST_SLC0_TOKEN0_M  (SLCHOST_SLC0_TOKEN0_V << SLCHOST_SLC0_TOKEN0_S)
-#define SLCHOST_SLC0_TOKEN0_V  0x00000FFFU
-#define SLCHOST_SLC0_TOKEN0_S  0
-/** SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID    (BIT(12))
-#define SLCHOST_SLC0_RX_PF_VALID_M  (SLCHOST_SLC0_RX_PF_VALID_V << SLCHOST_SLC0_RX_PF_VALID_S)
-#define SLCHOST_SLC0_RX_PF_VALID_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_S  12
-/** SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M  (SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S  16
-/** SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_EOF    0x0000000FU
-#define SLCHOST_SLC0_RX_PF_EOF_M  (SLCHOST_SLC0_RX_PF_EOF_V << SLCHOST_SLC0_RX_PF_EOF_S)
-#define SLCHOST_SLC0_RX_PF_EOF_V  0x0000000FU
-#define SLCHOST_SLC0_RX_PF_EOF_S  28
-
-/** SLCHOST_SLC0_HOST_PF_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
-/** SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_PF_DATA    0xFFFFFFFFU
-#define SLCHOST_SLC0_PF_DATA_M  (SLCHOST_SLC0_PF_DATA_V << SLCHOST_SLC0_PF_DATA_S)
-#define SLCHOST_SLC0_PF_DATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC0_PF_DATA_S  0
-
-/** SLCHOST_SLC1_HOST_PF_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4c)
-/** SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_PF_DATA    0xFFFFFFFFU
-#define SLCHOST_SLC1_PF_DATA_M  (SLCHOST_SLC1_PF_DATA_V << SLCHOST_SLC1_PF_DATA_S)
-#define SLCHOST_SLC1_PF_DATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC1_PF_DATA_S  0
-
-/** SLCHOST_SLC0HOST_INT_RAW_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M  (SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M  (SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW_M  (SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SLCHOST_SLC0HOST_RX_START_INT_RAW_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW_M  (SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SLCHOST_SLC0HOST_TX_START_INT_RAW_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_RAW    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_RAW_M  (SLCHOST_SLC0_RX_UDF_INT_RAW_V << SLCHOST_SLC0_RX_UDF_INT_RAW_S)
-#define SLCHOST_SLC0_RX_UDF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_RAW_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_RAW    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_RAW_M  (SLCHOST_SLC0_TX_OVF_INT_RAW_V << SLCHOST_SLC0_TX_OVF_INT_RAW_S)
-#define SLCHOST_SLC0_TX_OVF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_RAW_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M  (SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SLCHOST_SLC0_EXT_BIT0_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SLCHOST_SLC0_EXT_BIT1_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SLCHOST_SLC0_EXT_BIT2_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SLCHOST_SLC0_EXT_BIT3_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S  24
-/** SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_RAW    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_RAW_M  (SLCHOST_GPIO_SDIO_INT_RAW_V << SLCHOST_GPIO_SDIO_INT_RAW_S)
-#define SLCHOST_GPIO_SDIO_INT_RAW_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_RAW_S  25
-
-/** SLCHOST_SLC1HOST_INT_RAW_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M  (SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M  (SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW_M  (SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SLCHOST_SLC1HOST_RX_START_INT_RAW_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW_M  (SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SLCHOST_SLC1HOST_TX_START_INT_RAW_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_RAW    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_RAW_M  (SLCHOST_SLC1_RX_UDF_INT_RAW_V << SLCHOST_SLC1_RX_UDF_INT_RAW_S)
-#define SLCHOST_SLC1_RX_UDF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_RAW_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_RAW    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_RAW_M  (SLCHOST_SLC1_TX_OVF_INT_RAW_V << SLCHOST_SLC1_TX_OVF_INT_RAW_S)
-#define SLCHOST_SLC1_TX_OVF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_RAW_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M  (SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SLCHOST_SLC1_EXT_BIT0_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SLCHOST_SLC1_EXT_BIT1_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SLCHOST_SLC1_EXT_BIT2_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SLCHOST_SLC1_EXT_BIT3_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S  25
-
-/** SLCHOST_SLC0HOST_INT_ST_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SLCHOST_SLC0HOST_RX_SOF_INT_ST_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SLCHOST_SLC0HOST_RX_EOF_INT_ST_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_ST    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_ST_M  (SLCHOST_SLC0HOST_RX_START_INT_ST_V << SLCHOST_SLC0HOST_RX_START_INT_ST_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_ST_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_ST    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_ST_M  (SLCHOST_SLC0HOST_TX_START_INT_ST_V << SLCHOST_SLC0HOST_TX_START_INT_ST_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_ST_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_ST    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_ST_M  (SLCHOST_SLC0_RX_UDF_INT_ST_V << SLCHOST_SLC0_RX_UDF_INT_ST_S)
-#define SLCHOST_SLC0_RX_UDF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_ST_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_ST    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_ST_M  (SLCHOST_SLC0_TX_OVF_INT_ST_V << SLCHOST_SLC0_TX_OVF_INT_ST_S)
-#define SLCHOST_SLC0_TX_OVF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_ST_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SLCHOST_SLC0_RX_PF_VALID_INT_ST_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST_M  (SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SLCHOST_SLC0_EXT_BIT0_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST_M  (SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SLCHOST_SLC0_EXT_BIT1_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST_M  (SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SLCHOST_SLC0_EXT_BIT2_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST_M  (SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SLCHOST_SLC0_EXT_BIT3_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S  24
-/** SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_ST    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_ST_M  (SLCHOST_GPIO_SDIO_INT_ST_V << SLCHOST_GPIO_SDIO_INT_ST_S)
-#define SLCHOST_GPIO_SDIO_INT_ST_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_ST_S  25
-
-/** SLCHOST_SLC1HOST_INT_ST_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5c)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SLCHOST_SLC1HOST_RX_SOF_INT_ST_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SLCHOST_SLC1HOST_RX_EOF_INT_ST_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_ST    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_ST_M  (SLCHOST_SLC1HOST_RX_START_INT_ST_V << SLCHOST_SLC1HOST_RX_START_INT_ST_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_ST_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_ST    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_ST_M  (SLCHOST_SLC1HOST_TX_START_INT_ST_V << SLCHOST_SLC1HOST_TX_START_INT_ST_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_ST_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_ST    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_ST_M  (SLCHOST_SLC1_RX_UDF_INT_ST_V << SLCHOST_SLC1_RX_UDF_INT_ST_S)
-#define SLCHOST_SLC1_RX_UDF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_ST_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_ST    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_ST_M  (SLCHOST_SLC1_TX_OVF_INT_ST_V << SLCHOST_SLC1_TX_OVF_INT_ST_S)
-#define SLCHOST_SLC1_TX_OVF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_ST_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SLCHOST_SLC1_RX_PF_VALID_INT_ST_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST_M  (SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SLCHOST_SLC1_EXT_BIT0_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST_M  (SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SLCHOST_SLC1_EXT_BIT1_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST_M  (SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SLCHOST_SLC1_EXT_BIT2_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST_M  (SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SLCHOST_SLC1_EXT_BIT3_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S  25
-
-/** SLCHOST_PKT_LEN_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S  20
-
-/** SLCHOST_STATE_W0_REG register
- *  *******Description***********
- */
-#define SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64)
-/** SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE0    0x000000FFU
-#define SLCHOST_SLCHOST_STATE0_M  (SLCHOST_SLCHOST_STATE0_V << SLCHOST_SLCHOST_STATE0_S)
-#define SLCHOST_SLCHOST_STATE0_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE0_S  0
-/** SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE1    0x000000FFU
-#define SLCHOST_SLCHOST_STATE1_M  (SLCHOST_SLCHOST_STATE1_V << SLCHOST_SLCHOST_STATE1_S)
-#define SLCHOST_SLCHOST_STATE1_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE1_S  8
-/** SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE2    0x000000FFU
-#define SLCHOST_SLCHOST_STATE2_M  (SLCHOST_SLCHOST_STATE2_V << SLCHOST_SLCHOST_STATE2_S)
-#define SLCHOST_SLCHOST_STATE2_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE2_S  16
-/** SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE3    0x000000FFU
-#define SLCHOST_SLCHOST_STATE3_M  (SLCHOST_SLCHOST_STATE3_V << SLCHOST_SLCHOST_STATE3_S)
-#define SLCHOST_SLCHOST_STATE3_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE3_S  24
-
-/** SLCHOST_STATE_W1_REG register
- *  *******Description***********
- */
-#define SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68)
-/** SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE4    0x000000FFU
-#define SLCHOST_SLCHOST_STATE4_M  (SLCHOST_SLCHOST_STATE4_V << SLCHOST_SLCHOST_STATE4_S)
-#define SLCHOST_SLCHOST_STATE4_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE4_S  0
-/** SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE5    0x000000FFU
-#define SLCHOST_SLCHOST_STATE5_M  (SLCHOST_SLCHOST_STATE5_V << SLCHOST_SLCHOST_STATE5_S)
-#define SLCHOST_SLCHOST_STATE5_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE5_S  8
-/** SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE6    0x000000FFU
-#define SLCHOST_SLCHOST_STATE6_M  (SLCHOST_SLCHOST_STATE6_V << SLCHOST_SLCHOST_STATE6_S)
-#define SLCHOST_SLCHOST_STATE6_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE6_S  16
-/** SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE7    0x000000FFU
-#define SLCHOST_SLCHOST_STATE7_M  (SLCHOST_SLCHOST_STATE7_V << SLCHOST_SLCHOST_STATE7_S)
-#define SLCHOST_SLCHOST_STATE7_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE7_S  24
-
-/** SLCHOST_CONF_W0_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6c)
-/** SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF0    0x000000FFU
-#define SLCHOST_SLCHOST_CONF0_M  (SLCHOST_SLCHOST_CONF0_V << SLCHOST_SLCHOST_CONF0_S)
-#define SLCHOST_SLCHOST_CONF0_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF0_S  0
-/** SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF1    0x000000FFU
-#define SLCHOST_SLCHOST_CONF1_M  (SLCHOST_SLCHOST_CONF1_V << SLCHOST_SLCHOST_CONF1_S)
-#define SLCHOST_SLCHOST_CONF1_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF1_S  8
-/** SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF2    0x000000FFU
-#define SLCHOST_SLCHOST_CONF2_M  (SLCHOST_SLCHOST_CONF2_V << SLCHOST_SLCHOST_CONF2_S)
-#define SLCHOST_SLCHOST_CONF2_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF2_S  16
-/** SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF3    0x000000FFU
-#define SLCHOST_SLCHOST_CONF3_M  (SLCHOST_SLCHOST_CONF3_V << SLCHOST_SLCHOST_CONF3_S)
-#define SLCHOST_SLCHOST_CONF3_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF3_S  24
-
-/** SLCHOST_CONF_W1_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70)
-/** SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF4    0x000000FFU
-#define SLCHOST_SLCHOST_CONF4_M  (SLCHOST_SLCHOST_CONF4_V << SLCHOST_SLCHOST_CONF4_S)
-#define SLCHOST_SLCHOST_CONF4_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF4_S  0
-/** SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF5    0x000000FFU
-#define SLCHOST_SLCHOST_CONF5_M  (SLCHOST_SLCHOST_CONF5_V << SLCHOST_SLCHOST_CONF5_S)
-#define SLCHOST_SLCHOST_CONF5_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF5_S  8
-/** SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF6    0x000000FFU
-#define SLCHOST_SLCHOST_CONF6_M  (SLCHOST_SLCHOST_CONF6_V << SLCHOST_SLCHOST_CONF6_S)
-#define SLCHOST_SLCHOST_CONF6_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF6_S  16
-/** SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF7    0x000000FFU
-#define SLCHOST_SLCHOST_CONF7_M  (SLCHOST_SLCHOST_CONF7_V << SLCHOST_SLCHOST_CONF7_S)
-#define SLCHOST_SLCHOST_CONF7_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF7_S  24
-
-/** SLCHOST_CONF_W2_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74)
-/** SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF8    0x000000FFU
-#define SLCHOST_SLCHOST_CONF8_M  (SLCHOST_SLCHOST_CONF8_V << SLCHOST_SLCHOST_CONF8_S)
-#define SLCHOST_SLCHOST_CONF8_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF8_S  0
-/** SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF9    0x000000FFU
-#define SLCHOST_SLCHOST_CONF9_M  (SLCHOST_SLCHOST_CONF9_V << SLCHOST_SLCHOST_CONF9_S)
-#define SLCHOST_SLCHOST_CONF9_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF9_S  8
-/** SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF10    0x000000FFU
-#define SLCHOST_SLCHOST_CONF10_M  (SLCHOST_SLCHOST_CONF10_V << SLCHOST_SLCHOST_CONF10_S)
-#define SLCHOST_SLCHOST_CONF10_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF10_S  16
-/** SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF11    0x000000FFU
-#define SLCHOST_SLCHOST_CONF11_M  (SLCHOST_SLCHOST_CONF11_V << SLCHOST_SLCHOST_CONF11_S)
-#define SLCHOST_SLCHOST_CONF11_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF11_S  24
-
-/** SLCHOST_CONF_W3_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78)
-/** SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF12    0x000000FFU
-#define SLCHOST_SLCHOST_CONF12_M  (SLCHOST_SLCHOST_CONF12_V << SLCHOST_SLCHOST_CONF12_S)
-#define SLCHOST_SLCHOST_CONF12_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF12_S  0
-/** SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF13    0x000000FFU
-#define SLCHOST_SLCHOST_CONF13_M  (SLCHOST_SLCHOST_CONF13_V << SLCHOST_SLCHOST_CONF13_S)
-#define SLCHOST_SLCHOST_CONF13_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF13_S  8
-/** SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF14    0x000000FFU
-#define SLCHOST_SLCHOST_CONF14_M  (SLCHOST_SLCHOST_CONF14_V << SLCHOST_SLCHOST_CONF14_S)
-#define SLCHOST_SLCHOST_CONF14_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF14_S  16
-/** SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF15    0x000000FFU
-#define SLCHOST_SLCHOST_CONF15_M  (SLCHOST_SLCHOST_CONF15_V << SLCHOST_SLCHOST_CONF15_S)
-#define SLCHOST_SLCHOST_CONF15_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF15_S  24
-
-/** SLCHOST_CONF_W4_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7c)
-/** SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF16    0x000000FFU
-#define SLCHOST_SLCHOST_CONF16_M  (SLCHOST_SLCHOST_CONF16_V << SLCHOST_SLCHOST_CONF16_S)
-#define SLCHOST_SLCHOST_CONF16_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF16_S  0
-/** SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF17    0x000000FFU
-#define SLCHOST_SLCHOST_CONF17_M  (SLCHOST_SLCHOST_CONF17_V << SLCHOST_SLCHOST_CONF17_S)
-#define SLCHOST_SLCHOST_CONF17_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF17_S  8
-/** SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF18    0x000000FFU
-#define SLCHOST_SLCHOST_CONF18_M  (SLCHOST_SLCHOST_CONF18_V << SLCHOST_SLCHOST_CONF18_S)
-#define SLCHOST_SLCHOST_CONF18_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF18_S  16
-/** SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF19    0x000000FFU
-#define SLCHOST_SLCHOST_CONF19_M  (SLCHOST_SLCHOST_CONF19_V << SLCHOST_SLCHOST_CONF19_S)
-#define SLCHOST_SLCHOST_CONF19_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF19_S  24
-
-/** SLCHOST_CONF_W5_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80)
-/** SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF20    0x000000FFU
-#define SLCHOST_SLCHOST_CONF20_M  (SLCHOST_SLCHOST_CONF20_V << SLCHOST_SLCHOST_CONF20_S)
-#define SLCHOST_SLCHOST_CONF20_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF20_S  0
-/** SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF21    0x000000FFU
-#define SLCHOST_SLCHOST_CONF21_M  (SLCHOST_SLCHOST_CONF21_V << SLCHOST_SLCHOST_CONF21_S)
-#define SLCHOST_SLCHOST_CONF21_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF21_S  8
-/** SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF22    0x000000FFU
-#define SLCHOST_SLCHOST_CONF22_M  (SLCHOST_SLCHOST_CONF22_V << SLCHOST_SLCHOST_CONF22_S)
-#define SLCHOST_SLCHOST_CONF22_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF22_S  16
-/** SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF23    0x000000FFU
-#define SLCHOST_SLCHOST_CONF23_M  (SLCHOST_SLCHOST_CONF23_V << SLCHOST_SLCHOST_CONF23_S)
-#define SLCHOST_SLCHOST_CONF23_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF23_S  24
-
-/** SLCHOST_WIN_CMD_REG register
- *  *******Description***********
- */
-#define SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84)
-/** SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_WIN_CMD    0x0000FFFFU
-#define SLCHOST_SLCHOST_WIN_CMD_M  (SLCHOST_SLCHOST_WIN_CMD_V << SLCHOST_SLCHOST_WIN_CMD_S)
-#define SLCHOST_SLCHOST_WIN_CMD_V  0x0000FFFFU
-#define SLCHOST_SLCHOST_WIN_CMD_S  0
-
-/** SLCHOST_CONF_W6_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88)
-/** SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF24    0x000000FFU
-#define SLCHOST_SLCHOST_CONF24_M  (SLCHOST_SLCHOST_CONF24_V << SLCHOST_SLCHOST_CONF24_S)
-#define SLCHOST_SLCHOST_CONF24_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF24_S  0
-/** SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF25    0x000000FFU
-#define SLCHOST_SLCHOST_CONF25_M  (SLCHOST_SLCHOST_CONF25_V << SLCHOST_SLCHOST_CONF25_S)
-#define SLCHOST_SLCHOST_CONF25_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF25_S  8
-/** SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF26    0x000000FFU
-#define SLCHOST_SLCHOST_CONF26_M  (SLCHOST_SLCHOST_CONF26_V << SLCHOST_SLCHOST_CONF26_S)
-#define SLCHOST_SLCHOST_CONF26_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF26_S  16
-/** SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF27    0x000000FFU
-#define SLCHOST_SLCHOST_CONF27_M  (SLCHOST_SLCHOST_CONF27_V << SLCHOST_SLCHOST_CONF27_S)
-#define SLCHOST_SLCHOST_CONF27_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF27_S  24
-
-/** SLCHOST_CONF_W7_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8c)
-/** SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF28    0x000000FFU
-#define SLCHOST_SLCHOST_CONF28_M  (SLCHOST_SLCHOST_CONF28_V << SLCHOST_SLCHOST_CONF28_S)
-#define SLCHOST_SLCHOST_CONF28_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF28_S  0
-/** SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF29    0x000000FFU
-#define SLCHOST_SLCHOST_CONF29_M  (SLCHOST_SLCHOST_CONF29_V << SLCHOST_SLCHOST_CONF29_S)
-#define SLCHOST_SLCHOST_CONF29_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF29_S  8
-/** SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF30    0x000000FFU
-#define SLCHOST_SLCHOST_CONF30_M  (SLCHOST_SLCHOST_CONF30_V << SLCHOST_SLCHOST_CONF30_S)
-#define SLCHOST_SLCHOST_CONF30_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF30_S  16
-/** SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF31    0x000000FFU
-#define SLCHOST_SLCHOST_CONF31_M  (SLCHOST_SLCHOST_CONF31_V << SLCHOST_SLCHOST_CONF31_S)
-#define SLCHOST_SLCHOST_CONF31_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF31_S  24
-
-/** SLCHOST_PKT_LEN0_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S  20
-
-/** SLCHOST_PKT_LEN1_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S  20
-
-/** SLCHOST_PKT_LEN2_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S  20
-
-/** SLCHOST_CONF_W8_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9c)
-/** SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF32    0x000000FFU
-#define SLCHOST_SLCHOST_CONF32_M  (SLCHOST_SLCHOST_CONF32_V << SLCHOST_SLCHOST_CONF32_S)
-#define SLCHOST_SLCHOST_CONF32_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF32_S  0
-/** SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF33    0x000000FFU
-#define SLCHOST_SLCHOST_CONF33_M  (SLCHOST_SLCHOST_CONF33_V << SLCHOST_SLCHOST_CONF33_S)
-#define SLCHOST_SLCHOST_CONF33_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF33_S  8
-/** SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF34    0x000000FFU
-#define SLCHOST_SLCHOST_CONF34_M  (SLCHOST_SLCHOST_CONF34_V << SLCHOST_SLCHOST_CONF34_S)
-#define SLCHOST_SLCHOST_CONF34_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF34_S  16
-/** SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF35    0x000000FFU
-#define SLCHOST_SLCHOST_CONF35_M  (SLCHOST_SLCHOST_CONF35_V << SLCHOST_SLCHOST_CONF35_S)
-#define SLCHOST_SLCHOST_CONF35_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF35_S  24
-
-/** SLCHOST_CONF_W9_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xa0)
-/** SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF36    0x000000FFU
-#define SLCHOST_SLCHOST_CONF36_M  (SLCHOST_SLCHOST_CONF36_V << SLCHOST_SLCHOST_CONF36_S)
-#define SLCHOST_SLCHOST_CONF36_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF36_S  0
-/** SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF37    0x000000FFU
-#define SLCHOST_SLCHOST_CONF37_M  (SLCHOST_SLCHOST_CONF37_V << SLCHOST_SLCHOST_CONF37_S)
-#define SLCHOST_SLCHOST_CONF37_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF37_S  8
-/** SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF38    0x000000FFU
-#define SLCHOST_SLCHOST_CONF38_M  (SLCHOST_SLCHOST_CONF38_V << SLCHOST_SLCHOST_CONF38_S)
-#define SLCHOST_SLCHOST_CONF38_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF38_S  16
-/** SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF39    0x000000FFU
-#define SLCHOST_SLCHOST_CONF39_M  (SLCHOST_SLCHOST_CONF39_V << SLCHOST_SLCHOST_CONF39_S)
-#define SLCHOST_SLCHOST_CONF39_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF39_S  24
-
-/** SLCHOST_CONF_W10_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xa4)
-/** SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF40    0x000000FFU
-#define SLCHOST_SLCHOST_CONF40_M  (SLCHOST_SLCHOST_CONF40_V << SLCHOST_SLCHOST_CONF40_S)
-#define SLCHOST_SLCHOST_CONF40_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF40_S  0
-/** SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF41    0x000000FFU
-#define SLCHOST_SLCHOST_CONF41_M  (SLCHOST_SLCHOST_CONF41_V << SLCHOST_SLCHOST_CONF41_S)
-#define SLCHOST_SLCHOST_CONF41_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF41_S  8
-/** SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF42    0x000000FFU
-#define SLCHOST_SLCHOST_CONF42_M  (SLCHOST_SLCHOST_CONF42_V << SLCHOST_SLCHOST_CONF42_S)
-#define SLCHOST_SLCHOST_CONF42_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF42_S  16
-/** SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF43    0x000000FFU
-#define SLCHOST_SLCHOST_CONF43_M  (SLCHOST_SLCHOST_CONF43_V << SLCHOST_SLCHOST_CONF43_S)
-#define SLCHOST_SLCHOST_CONF43_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF43_S  24
-
-/** SLCHOST_CONF_W11_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xa8)
-/** SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF44    0x000000FFU
-#define SLCHOST_SLCHOST_CONF44_M  (SLCHOST_SLCHOST_CONF44_V << SLCHOST_SLCHOST_CONF44_S)
-#define SLCHOST_SLCHOST_CONF44_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF44_S  0
-/** SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF45    0x000000FFU
-#define SLCHOST_SLCHOST_CONF45_M  (SLCHOST_SLCHOST_CONF45_V << SLCHOST_SLCHOST_CONF45_S)
-#define SLCHOST_SLCHOST_CONF45_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF45_S  8
-/** SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF46    0x000000FFU
-#define SLCHOST_SLCHOST_CONF46_M  (SLCHOST_SLCHOST_CONF46_V << SLCHOST_SLCHOST_CONF46_S)
-#define SLCHOST_SLCHOST_CONF46_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF46_S  16
-/** SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF47    0x000000FFU
-#define SLCHOST_SLCHOST_CONF47_M  (SLCHOST_SLCHOST_CONF47_V << SLCHOST_SLCHOST_CONF47_S)
-#define SLCHOST_SLCHOST_CONF47_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF47_S  24
-
-/** SLCHOST_CONF_W12_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xac)
-/** SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF48    0x000000FFU
-#define SLCHOST_SLCHOST_CONF48_M  (SLCHOST_SLCHOST_CONF48_V << SLCHOST_SLCHOST_CONF48_S)
-#define SLCHOST_SLCHOST_CONF48_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF48_S  0
-/** SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF49    0x000000FFU
-#define SLCHOST_SLCHOST_CONF49_M  (SLCHOST_SLCHOST_CONF49_V << SLCHOST_SLCHOST_CONF49_S)
-#define SLCHOST_SLCHOST_CONF49_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF49_S  8
-/** SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF50    0x000000FFU
-#define SLCHOST_SLCHOST_CONF50_M  (SLCHOST_SLCHOST_CONF50_V << SLCHOST_SLCHOST_CONF50_S)
-#define SLCHOST_SLCHOST_CONF50_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF50_S  16
-/** SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF51    0x000000FFU
-#define SLCHOST_SLCHOST_CONF51_M  (SLCHOST_SLCHOST_CONF51_V << SLCHOST_SLCHOST_CONF51_S)
-#define SLCHOST_SLCHOST_CONF51_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF51_S  24
-
-/** SLCHOST_CONF_W13_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xb0)
-/** SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF52    0x000000FFU
-#define SLCHOST_SLCHOST_CONF52_M  (SLCHOST_SLCHOST_CONF52_V << SLCHOST_SLCHOST_CONF52_S)
-#define SLCHOST_SLCHOST_CONF52_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF52_S  0
-/** SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF53    0x000000FFU
-#define SLCHOST_SLCHOST_CONF53_M  (SLCHOST_SLCHOST_CONF53_V << SLCHOST_SLCHOST_CONF53_S)
-#define SLCHOST_SLCHOST_CONF53_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF53_S  8
-/** SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF54    0x000000FFU
-#define SLCHOST_SLCHOST_CONF54_M  (SLCHOST_SLCHOST_CONF54_V << SLCHOST_SLCHOST_CONF54_S)
-#define SLCHOST_SLCHOST_CONF54_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF54_S  16
-/** SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF55    0x000000FFU
-#define SLCHOST_SLCHOST_CONF55_M  (SLCHOST_SLCHOST_CONF55_V << SLCHOST_SLCHOST_CONF55_S)
-#define SLCHOST_SLCHOST_CONF55_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF55_S  24
-
-/** SLCHOST_CONF_W14_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xb4)
-/** SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF56    0x000000FFU
-#define SLCHOST_SLCHOST_CONF56_M  (SLCHOST_SLCHOST_CONF56_V << SLCHOST_SLCHOST_CONF56_S)
-#define SLCHOST_SLCHOST_CONF56_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF56_S  0
-/** SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF57    0x000000FFU
-#define SLCHOST_SLCHOST_CONF57_M  (SLCHOST_SLCHOST_CONF57_V << SLCHOST_SLCHOST_CONF57_S)
-#define SLCHOST_SLCHOST_CONF57_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF57_S  8
-/** SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF58    0x000000FFU
-#define SLCHOST_SLCHOST_CONF58_M  (SLCHOST_SLCHOST_CONF58_V << SLCHOST_SLCHOST_CONF58_S)
-#define SLCHOST_SLCHOST_CONF58_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF58_S  16
-/** SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF59    0x000000FFU
-#define SLCHOST_SLCHOST_CONF59_M  (SLCHOST_SLCHOST_CONF59_V << SLCHOST_SLCHOST_CONF59_S)
-#define SLCHOST_SLCHOST_CONF59_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF59_S  24
-
-/** SLCHOST_CONF_W15_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xb8)
-/** SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF60    0x000000FFU
-#define SLCHOST_SLCHOST_CONF60_M  (SLCHOST_SLCHOST_CONF60_V << SLCHOST_SLCHOST_CONF60_S)
-#define SLCHOST_SLCHOST_CONF60_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF60_S  0
-/** SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF61    0x000000FFU
-#define SLCHOST_SLCHOST_CONF61_M  (SLCHOST_SLCHOST_CONF61_V << SLCHOST_SLCHOST_CONF61_S)
-#define SLCHOST_SLCHOST_CONF61_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF61_S  8
-/** SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF62    0x000000FFU
-#define SLCHOST_SLCHOST_CONF62_M  (SLCHOST_SLCHOST_CONF62_V << SLCHOST_SLCHOST_CONF62_S)
-#define SLCHOST_SLCHOST_CONF62_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF62_S  16
-/** SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF63    0x000000FFU
-#define SLCHOST_SLCHOST_CONF63_M  (SLCHOST_SLCHOST_CONF63_V << SLCHOST_SLCHOST_CONF63_S)
-#define SLCHOST_SLCHOST_CONF63_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF63_S  24
-
-/** SLCHOST_CHECK_SUM0_REG register
- *  *******Description***********
- */
-#define SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xbc)
-/** SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CHECK_SUM0    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM0_M  (SLCHOST_SLCHOST_CHECK_SUM0_V << SLCHOST_SLCHOST_CHECK_SUM0_S)
-#define SLCHOST_SLCHOST_CHECK_SUM0_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM0_S  0
-
-/** SLCHOST_CHECK_SUM1_REG register
- *  *******Description***********
- */
-#define SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xc0)
-/** SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CHECK_SUM1    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM1_M  (SLCHOST_SLCHOST_CHECK_SUM1_V << SLCHOST_SLCHOST_CHECK_SUM1_S)
-#define SLCHOST_SLCHOST_CHECK_SUM1_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM1_S  0
-
-/** SLCHOST_SLC1HOST_TOKEN_RDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xc4)
-/** SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0    0x00000FFFU
-#define SLCHOST_SLC1_TOKEN0_M  (SLCHOST_SLC1_TOKEN0_V << SLCHOST_SLC1_TOKEN0_S)
-#define SLCHOST_SLC1_TOKEN0_V  0x00000FFFU
-#define SLCHOST_SLC1_TOKEN0_S  0
-/** SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID    (BIT(12))
-#define SLCHOST_SLC1_RX_PF_VALID_M  (SLCHOST_SLC1_RX_PF_VALID_V << SLCHOST_SLC1_RX_PF_VALID_S)
-#define SLCHOST_SLC1_RX_PF_VALID_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_S  12
-/** SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M  (SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S)
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S  16
-/** SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_EOF    0x0000000FU
-#define SLCHOST_SLC1_RX_PF_EOF_M  (SLCHOST_SLC1_RX_PF_EOF_V << SLCHOST_SLC1_RX_PF_EOF_S)
-#define SLCHOST_SLC1_RX_PF_EOF_V  0x0000000FU
-#define SLCHOST_SLC1_RX_PF_EOF_S  28
-
-/** SLCHOST_SLC0HOST_TOKEN_WDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xc8)
-/** SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN0_WD    0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN0_WD_M  (SLCHOST_SLC0HOST_TOKEN0_WD_V << SLCHOST_SLC0HOST_TOKEN0_WD_S)
-#define SLCHOST_SLC0HOST_TOKEN0_WD_V  0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN0_WD_S  0
-/** SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN1_WD    0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN1_WD_M  (SLCHOST_SLC0HOST_TOKEN1_WD_V << SLCHOST_SLC0HOST_TOKEN1_WD_S)
-#define SLCHOST_SLC0HOST_TOKEN1_WD_V  0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN1_WD_S  16
-
-/** SLCHOST_SLC1HOST_TOKEN_WDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xcc)
-/** SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN0_WD    0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN0_WD_M  (SLCHOST_SLC1HOST_TOKEN0_WD_V << SLCHOST_SLC1HOST_TOKEN0_WD_S)
-#define SLCHOST_SLC1HOST_TOKEN0_WD_V  0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN0_WD_S  0
-/** SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN1_WD    0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN1_WD_M  (SLCHOST_SLC1HOST_TOKEN1_WD_V << SLCHOST_SLC1HOST_TOKEN1_WD_S)
-#define SLCHOST_SLC1HOST_TOKEN1_WD_V  0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN1_WD_S  16
-
-/** SLCHOST_TOKEN_CON_REG register
- *  *******Description***********
- */
-#define SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xd0)
-/** SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN0_DEC    (BIT(0))
-#define SLCHOST_SLC0HOST_TOKEN0_DEC_M  (SLCHOST_SLC0HOST_TOKEN0_DEC_V << SLCHOST_SLC0HOST_TOKEN0_DEC_S)
-#define SLCHOST_SLC0HOST_TOKEN0_DEC_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN0_DEC_S  0
-/** SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN1_DEC    (BIT(1))
-#define SLCHOST_SLC0HOST_TOKEN1_DEC_M  (SLCHOST_SLC0HOST_TOKEN1_DEC_V << SLCHOST_SLC0HOST_TOKEN1_DEC_S)
-#define SLCHOST_SLC0HOST_TOKEN1_DEC_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN1_DEC_S  1
-/** SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN0_WR    (BIT(2))
-#define SLCHOST_SLC0HOST_TOKEN0_WR_M  (SLCHOST_SLC0HOST_TOKEN0_WR_V << SLCHOST_SLC0HOST_TOKEN0_WR_S)
-#define SLCHOST_SLC0HOST_TOKEN0_WR_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN0_WR_S  2
-/** SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN1_WR    (BIT(3))
-#define SLCHOST_SLC0HOST_TOKEN1_WR_M  (SLCHOST_SLC0HOST_TOKEN1_WR_V << SLCHOST_SLC0HOST_TOKEN1_WR_S)
-#define SLCHOST_SLC0HOST_TOKEN1_WR_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN1_WR_S  3
-/** SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN0_DEC    (BIT(4))
-#define SLCHOST_SLC1HOST_TOKEN0_DEC_M  (SLCHOST_SLC1HOST_TOKEN0_DEC_V << SLCHOST_SLC1HOST_TOKEN0_DEC_S)
-#define SLCHOST_SLC1HOST_TOKEN0_DEC_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN0_DEC_S  4
-/** SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN1_DEC    (BIT(5))
-#define SLCHOST_SLC1HOST_TOKEN1_DEC_M  (SLCHOST_SLC1HOST_TOKEN1_DEC_V << SLCHOST_SLC1HOST_TOKEN1_DEC_S)
-#define SLCHOST_SLC1HOST_TOKEN1_DEC_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN1_DEC_S  5
-/** SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN0_WR    (BIT(6))
-#define SLCHOST_SLC1HOST_TOKEN0_WR_M  (SLCHOST_SLC1HOST_TOKEN0_WR_V << SLCHOST_SLC1HOST_TOKEN0_WR_S)
-#define SLCHOST_SLC1HOST_TOKEN0_WR_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN0_WR_S  6
-/** SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN1_WR    (BIT(7))
-#define SLCHOST_SLC1HOST_TOKEN1_WR_M  (SLCHOST_SLC1HOST_TOKEN1_WR_V << SLCHOST_SLC1HOST_TOKEN1_WR_S)
-#define SLCHOST_SLC1HOST_TOKEN1_WR_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN1_WR_S  7
-/** SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_LEN_WR    (BIT(8))
-#define SLCHOST_SLC0HOST_LEN_WR_M  (SLCHOST_SLC0HOST_LEN_WR_V << SLCHOST_SLC0HOST_LEN_WR_S)
-#define SLCHOST_SLC0HOST_LEN_WR_V  0x00000001U
-#define SLCHOST_SLC0HOST_LEN_WR_S  8
-
-/** SLCHOST_SLC0HOST_INT_CLR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd4)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M  (SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M  (SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR_M  (SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SLCHOST_SLC0HOST_RX_START_INT_CLR_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR_M  (SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SLCHOST_SLC0HOST_TX_START_INT_CLR_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_CLR    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_CLR_M  (SLCHOST_SLC0_RX_UDF_INT_CLR_V << SLCHOST_SLC0_RX_UDF_INT_CLR_S)
-#define SLCHOST_SLC0_RX_UDF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_CLR_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_CLR    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_CLR_M  (SLCHOST_SLC0_TX_OVF_INT_CLR_V << SLCHOST_SLC0_TX_OVF_INT_CLR_S)
-#define SLCHOST_SLC0_TX_OVF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_CLR_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M  (SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SLCHOST_SLC0_EXT_BIT0_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SLCHOST_SLC0_EXT_BIT1_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SLCHOST_SLC0_EXT_BIT2_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SLCHOST_SLC0_EXT_BIT3_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S  24
-/** SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_CLR    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_CLR_M  (SLCHOST_GPIO_SDIO_INT_CLR_V << SLCHOST_GPIO_SDIO_INT_CLR_S)
-#define SLCHOST_GPIO_SDIO_INT_CLR_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_CLR_S  25
-
-/** SLCHOST_SLC1HOST_INT_CLR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd8)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M  (SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M  (SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR_M  (SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SLCHOST_SLC1HOST_RX_START_INT_CLR_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR_M  (SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SLCHOST_SLC1HOST_TX_START_INT_CLR_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_CLR    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_CLR_M  (SLCHOST_SLC1_RX_UDF_INT_CLR_V << SLCHOST_SLC1_RX_UDF_INT_CLR_S)
-#define SLCHOST_SLC1_RX_UDF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_CLR_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_CLR    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_CLR_M  (SLCHOST_SLC1_TX_OVF_INT_CLR_V << SLCHOST_SLC1_TX_OVF_INT_CLR_S)
-#define SLCHOST_SLC1_TX_OVF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_CLR_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M  (SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SLCHOST_SLC1_EXT_BIT0_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SLCHOST_SLC1_EXT_BIT1_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SLCHOST_SLC1_EXT_BIT2_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SLCHOST_SLC1_EXT_BIT3_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S  25
-
-/** SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xdc)
-/** SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA    (BIT(25))
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_M  (SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SLCHOST_FN1_GPIO_SDIO_INT_ENA_S)
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_S  25
-
-/** SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe0)
-/** SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-
-/** SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe4)
-/** SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA    (BIT(25))
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_M  (SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SLCHOST_FN2_GPIO_SDIO_INT_ENA_S)
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_S  25
-
-/** SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe8)
-/** SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-
-/** SLCHOST_SLC0HOST_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xec)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_SLC0HOST_RX_START_INT_ENA_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_SLC0HOST_TX_START_INT_ENA_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_SLC0_RX_UDF_INT_ENA_V << SLCHOST_SLC0_RX_UDF_INT_ENA_S)
-#define SLCHOST_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_ENA_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_SLC0_TX_OVF_INT_ENA_V << SLCHOST_SLC0_TX_OVF_INT_ENA_S)
-#define SLCHOST_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_ENA_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_ENA    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_ENA_M  (SLCHOST_GPIO_SDIO_INT_ENA_V << SLCHOST_GPIO_SDIO_INT_ENA_S)
-#define SLCHOST_GPIO_SDIO_INT_ENA_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_ENA_S  25
-
-/** SLCHOST_SLC1HOST_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xf0)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_SLC1HOST_RX_START_INT_ENA_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_SLC1HOST_TX_START_INT_ENA_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_SLC1_RX_UDF_INT_ENA_V << SLCHOST_SLC1_RX_UDF_INT_ENA_S)
-#define SLCHOST_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_ENA_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_SLC1_TX_OVF_INT_ENA_V << SLCHOST_SLC1_TX_OVF_INT_ENA_S)
-#define SLCHOST_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_ENA_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-
-/** SLCHOST_SLC0HOST_RX_INFOR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf4)
-/** SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_INFOR    0x000FFFFFU
-#define SLCHOST_SLC0HOST_RX_INFOR_M  (SLCHOST_SLC0HOST_RX_INFOR_V << SLCHOST_SLC0HOST_RX_INFOR_S)
-#define SLCHOST_SLC0HOST_RX_INFOR_V  0x000FFFFFU
-#define SLCHOST_SLC0HOST_RX_INFOR_S  0
-
-/** SLCHOST_SLC1HOST_RX_INFOR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf8)
-/** SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_INFOR    0x000FFFFFU
-#define SLCHOST_SLC1HOST_RX_INFOR_M  (SLCHOST_SLC1HOST_RX_INFOR_V << SLCHOST_SLC1HOST_RX_INFOR_S)
-#define SLCHOST_SLC1HOST_RX_INFOR_V  0x000FFFFFU
-#define SLCHOST_SLC1HOST_RX_INFOR_S  0
-
-/** SLCHOST_SLC0HOST_LEN_WD_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xfc)
-/** SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_LEN_WD    0xFFFFFFFFU
-#define SLCHOST_SLC0HOST_LEN_WD_M  (SLCHOST_SLC0HOST_LEN_WD_V << SLCHOST_SLC0HOST_LEN_WD_S)
-#define SLCHOST_SLC0HOST_LEN_WD_V  0xFFFFFFFFU
-#define SLCHOST_SLC0HOST_LEN_WD_S  0
-
-/** SLCHOST_SLC_APBWIN_WDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100)
-/** SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_WDATA    0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_WDATA_M  (SLCHOST_SLC_APBWIN_WDATA_V << SLCHOST_SLC_APBWIN_WDATA_S)
-#define SLCHOST_SLC_APBWIN_WDATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_WDATA_S  0
-
-/** SLCHOST_SLC_APBWIN_CONF_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104)
-/** SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_ADDR    0x0FFFFFFFU
-#define SLCHOST_SLC_APBWIN_ADDR_M  (SLCHOST_SLC_APBWIN_ADDR_V << SLCHOST_SLC_APBWIN_ADDR_S)
-#define SLCHOST_SLC_APBWIN_ADDR_V  0x0FFFFFFFU
-#define SLCHOST_SLC_APBWIN_ADDR_S  0
-/** SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_WR    (BIT(28))
-#define SLCHOST_SLC_APBWIN_WR_M  (SLCHOST_SLC_APBWIN_WR_V << SLCHOST_SLC_APBWIN_WR_S)
-#define SLCHOST_SLC_APBWIN_WR_V  0x00000001U
-#define SLCHOST_SLC_APBWIN_WR_S  28
-/** SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_START    (BIT(29))
-#define SLCHOST_SLC_APBWIN_START_M  (SLCHOST_SLC_APBWIN_START_V << SLCHOST_SLC_APBWIN_START_S)
-#define SLCHOST_SLC_APBWIN_START_V  0x00000001U
-#define SLCHOST_SLC_APBWIN_START_S  29
-
-/** SLCHOST_SLC_APBWIN_RDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108)
-/** SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_RDATA    0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_RDATA_M  (SLCHOST_SLC_APBWIN_RDATA_V << SLCHOST_SLC_APBWIN_RDATA_S)
-#define SLCHOST_SLC_APBWIN_RDATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_RDATA_S  0
-
-/** SLCHOST_RDCLR0_REG register
- *  *******Description***********
- */
-#define SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10c)
-/** SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M  (SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S  0
-/** SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M  (SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S  9
-
-/** SLCHOST_RDCLR1_REG register
- *  *******Description***********
- */
-#define SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110)
-/** SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M  (SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S  0
-/** SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M  (SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S  9
-
-/** SLCHOST_SLC0HOST_INT_ENA1_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SLCHOST_SLC0HOST_RX_START_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_M  (SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SLCHOST_SLC0HOST_TX_START_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1_M  (SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SLCHOST_SLC0_RX_UDF_INT_ENA1_S)
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1_M  (SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SLCHOST_SLC0_TX_OVF_INT_ENA1_S)
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S  24
-/** SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_ENA1    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_ENA1_M  (SLCHOST_GPIO_SDIO_INT_ENA1_V << SLCHOST_GPIO_SDIO_INT_ENA1_S)
-#define SLCHOST_GPIO_SDIO_INT_ENA1_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_ENA1_S  25
-
-/** SLCHOST_SLC1HOST_INT_ENA1_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SLCHOST_SLC1HOST_RX_START_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_M  (SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SLCHOST_SLC1HOST_TX_START_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1_M  (SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SLCHOST_SLC1_RX_UDF_INT_ENA1_S)
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1_M  (SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SLCHOST_SLC1_TX_OVF_INT_ENA1_S)
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S  25
-
-/** SLCHOST_SLCHOSTDATE_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178)
-/** SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_DATE    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_DATE_M  (SLCHOST_SLCHOST_DATE_V << SLCHOST_SLCHOST_DATE_S)
-#define SLCHOST_SLCHOST_DATE_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_DATE_S  0
-
-/** SLCHOST_SLCHOSTID_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17c)
-/** SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_ID    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_ID_M  (SLCHOST_SLCHOST_ID_V << SLCHOST_SLCHOST_ID_S)
-#define SLCHOST_SLCHOST_ID_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_ID_S  0
-
-/** SLCHOST_CONF_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1f0)
-/** SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_SDIO11    0x0000001FU
-#define SLCHOST_FRC_SDIO11_M  (SLCHOST_FRC_SDIO11_V << SLCHOST_FRC_SDIO11_S)
-#define SLCHOST_FRC_SDIO11_V  0x0000001FU
-#define SLCHOST_FRC_SDIO11_S  0
-/** SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_SDIO20    0x0000001FU
-#define SLCHOST_FRC_SDIO20_M  (SLCHOST_FRC_SDIO20_V << SLCHOST_FRC_SDIO20_S)
-#define SLCHOST_FRC_SDIO20_V  0x0000001FU
-#define SLCHOST_FRC_SDIO20_S  5
-/** SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_NEG_SAMP    0x0000001FU
-#define SLCHOST_FRC_NEG_SAMP_M  (SLCHOST_FRC_NEG_SAMP_V << SLCHOST_FRC_NEG_SAMP_S)
-#define SLCHOST_FRC_NEG_SAMP_V  0x0000001FU
-#define SLCHOST_FRC_NEG_SAMP_S  10
-/** SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_POS_SAMP    0x0000001FU
-#define SLCHOST_FRC_POS_SAMP_M  (SLCHOST_FRC_POS_SAMP_V << SLCHOST_FRC_POS_SAMP_S)
-#define SLCHOST_FRC_POS_SAMP_V  0x0000001FU
-#define SLCHOST_FRC_POS_SAMP_S  15
-/** SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_QUICK_IN    0x0000001FU
-#define SLCHOST_FRC_QUICK_IN_M  (SLCHOST_FRC_QUICK_IN_V << SLCHOST_FRC_QUICK_IN_S)
-#define SLCHOST_FRC_QUICK_IN_V  0x0000001FU
-#define SLCHOST_FRC_QUICK_IN_S  20
-/** SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO20_INT_DELAY    (BIT(25))
-#define SLCHOST_SDIO20_INT_DELAY_M  (SLCHOST_SDIO20_INT_DELAY_V << SLCHOST_SDIO20_INT_DELAY_S)
-#define SLCHOST_SDIO20_INT_DELAY_V  0x00000001U
-#define SLCHOST_SDIO20_INT_DELAY_S  25
-/** SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO_PAD_PULLUP    (BIT(26))
-#define SLCHOST_SDIO_PAD_PULLUP_M  (SLCHOST_SDIO_PAD_PULLUP_V << SLCHOST_SDIO_PAD_PULLUP_S)
-#define SLCHOST_SDIO_PAD_PULLUP_V  0x00000001U
-#define SLCHOST_SDIO_PAD_PULLUP_S  26
-/** SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HSPEED_CON_EN    (BIT(27))
-#define SLCHOST_HSPEED_CON_EN_M  (SLCHOST_HSPEED_CON_EN_V << SLCHOST_HSPEED_CON_EN_S)
-#define SLCHOST_HSPEED_CON_EN_V  0x00000001U
-#define SLCHOST_HSPEED_CON_EN_S  27
-
-/** SLCHOST_INF_ST_REG register
- *  *******Description***********
- */
-#define SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1f4)
-/** SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO20_MODE    0x0000001FU
-#define SLCHOST_SDIO20_MODE_M  (SLCHOST_SDIO20_MODE_V << SLCHOST_SDIO20_MODE_S)
-#define SLCHOST_SDIO20_MODE_V  0x0000001FU
-#define SLCHOST_SDIO20_MODE_S  0
-/** SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO_NEG_SAMP    0x0000001FU
-#define SLCHOST_SDIO_NEG_SAMP_M  (SLCHOST_SDIO_NEG_SAMP_V << SLCHOST_SDIO_NEG_SAMP_S)
-#define SLCHOST_SDIO_NEG_SAMP_V  0x0000001FU
-#define SLCHOST_SDIO_NEG_SAMP_S  5
-/** SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO_QUICK_IN    0x0000001FU
-#define SLCHOST_SDIO_QUICK_IN_M  (SLCHOST_SDIO_QUICK_IN_V << SLCHOST_SDIO_QUICK_IN_S)
-#define SLCHOST_SDIO_QUICK_IN_V  0x0000001FU
-#define SLCHOST_SDIO_QUICK_IN_S  10
-/** SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0;
- *  dll is controlled by software
- */
-#define SLCHOST_DLL_ON_SW    (BIT(15))
-#define SLCHOST_DLL_ON_SW_M  (SLCHOST_DLL_ON_SW_V << SLCHOST_DLL_ON_SW_S)
-#define SLCHOST_DLL_ON_SW_V  0x00000001U
-#define SLCHOST_DLL_ON_SW_S  15
-/** SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0;
- *  Software dll on
- */
-#define SLCHOST_DLL_ON    (BIT(16))
-#define SLCHOST_DLL_ON_M  (SLCHOST_DLL_ON_V << SLCHOST_DLL_ON_S)
-#define SLCHOST_DLL_ON_V  0x00000001U
-#define SLCHOST_DLL_ON_S  16
-/** SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0;
- *  dll clock mode is controlled by software
- */
-#define SLCHOST_CLK_MODE_SW    (BIT(17))
-#define SLCHOST_CLK_MODE_SW_M  (SLCHOST_CLK_MODE_SW_V << SLCHOST_CLK_MODE_SW_S)
-#define SLCHOST_CLK_MODE_SW_V  0x00000001U
-#define SLCHOST_CLK_MODE_SW_S  17
-/** SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0;
- *  Software set clock mode
- */
-#define SLCHOST_CLK_MODE    0x00000003U
-#define SLCHOST_CLK_MODE_M  (SLCHOST_CLK_MODE_V << SLCHOST_CLK_MODE_S)
-#define SLCHOST_CLK_MODE_V  0x00000003U
-#define SLCHOST_CLK_MODE_S  18
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/host_struct.h b/components/soc/esp32p4/include/soc/host_struct.h
deleted file mode 100644
index 275e30e72f..0000000000
--- a/components/soc/esp32p4/include/soc/host_struct.h
+++ /dev/null
@@ -1,2738 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: ********Registers */
-/** Type of func2_0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** slc_func2_int : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_func2_int:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} slchost_func2_0_reg_t;
-
-/** Type of func2_1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_func2_int_en : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_func2_int_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} slchost_func2_1_reg_t;
-
-/** Type of func2_2 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_func1_mdstat : R/W; bitpos: [0]; default: 1;
-         *  *******Description***********
-         */
-        uint32_t slc_func1_mdstat:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} slchost_func2_2_reg_t;
-
-/** Type of gpio_status0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int0:32;
-    };
-    uint32_t val;
-} slchost_gpio_status0_reg_t;
-
-/** Type of gpio_status1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int1:32;
-    };
-    uint32_t val;
-} slchost_gpio_status1_reg_t;
-
-/** Type of gpio_in0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_in0:32;
-    };
-    uint32_t val;
-} slchost_gpio_in0_reg_t;
-
-/** Type of gpio_in1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_in1:32;
-    };
-    uint32_t val;
-} slchost_gpio_in1_reg_t;
-
-/** Type of slc0host_token_rdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_token0 : RO; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0:12;
-        /** slc0_rx_pf_valid : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid:1;
-        uint32_t reserved_13:3;
-        /** hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_token1:12;
-        /** slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_eof:4;
-    };
-    uint32_t val;
-} slchost_slc0host_token_rdata_reg_t;
-
-/** Type of slc0_host_pf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_pf_data : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_pf_data:32;
-    };
-    uint32_t val;
-} slchost_slc0_host_pf_reg_t;
-
-/** Type of slc1_host_pf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_pf_data : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_pf_data:32;
-    };
-    uint32_t val;
-} slchost_slc1_host_pf_reg_t;
-
-/** Type of slc0host_int_raw register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_raw:1;
-        /** slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_raw:1;
-        /** slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_raw:1;
-        /** slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_raw:1;
-        /** slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_raw:1;
-        /** slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_raw:1;
-        /** slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_raw:1;
-        /** slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_raw:1;
-        /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_raw:1;
-        /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_raw:1;
-        /** slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_raw:1;
-        /** slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_raw:1;
-        /** slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_raw:1;
-        /** slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_raw:1;
-        /** slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_raw:1;
-        /** slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_raw:1;
-        /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_raw:1;
-        /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_raw:1;
-        /** slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_raw:1;
-        /** slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_raw:1;
-        /** slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_raw:1;
-        /** slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_raw:1;
-        /** slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_raw:1;
-        /** slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_raw:1;
-        /** slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_raw:1;
-        /** gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_raw:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_raw_reg_t;
-
-/** Type of slc1host_int_raw register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_raw:1;
-        /** slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_raw:1;
-        /** slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_raw:1;
-        /** slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_raw:1;
-        /** slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_raw:1;
-        /** slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_raw:1;
-        /** slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_raw:1;
-        /** slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_raw:1;
-        /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_raw:1;
-        /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_raw:1;
-        /** slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_raw:1;
-        /** slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_raw:1;
-        /** slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_raw:1;
-        /** slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_raw:1;
-        /** slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_raw:1;
-        /** slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_raw:1;
-        /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_raw:1;
-        /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_raw:1;
-        /** slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_raw:1;
-        /** slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_raw:1;
-        /** slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_raw:1;
-        /** slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_raw:1;
-        /** slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_raw:1;
-        /** slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_raw:1;
-        /** slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_raw:1;
-        /** slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_raw:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_raw_reg_t;
-
-/** Type of slc0host_int_st register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_st:1;
-        /** slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_st:1;
-        /** slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_st:1;
-        /** slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_st:1;
-        /** slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_st:1;
-        /** slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_st:1;
-        /** slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_st:1;
-        /** slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_st:1;
-        /** slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_st:1;
-        /** slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_st:1;
-        /** slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_st:1;
-        /** slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_st:1;
-        /** slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_st:1;
-        /** slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_st:1;
-        /** slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_st:1;
-        /** slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_st:1;
-        /** slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_st:1;
-        /** slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_st:1;
-        /** slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_st:1;
-        /** slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_st:1;
-        /** slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_st:1;
-        /** slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_st:1;
-        /** slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_st:1;
-        /** slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_st:1;
-        /** slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_st:1;
-        /** gpio_sdio_int_st : RO; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_st:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_st_reg_t;
-
-/** Type of slc1host_int_st register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_st:1;
-        /** slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_st:1;
-        /** slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_st:1;
-        /** slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_st:1;
-        /** slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_st:1;
-        /** slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_st:1;
-        /** slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_st:1;
-        /** slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_st:1;
-        /** slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_st:1;
-        /** slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_st:1;
-        /** slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_st:1;
-        /** slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_st:1;
-        /** slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_st:1;
-        /** slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_st:1;
-        /** slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_st:1;
-        /** slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_st:1;
-        /** slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_st:1;
-        /** slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_st:1;
-        /** slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_st:1;
-        /** slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_st:1;
-        /** slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_st:1;
-        /** slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_st:1;
-        /** slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_st:1;
-        /** slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_st:1;
-        /** slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_st:1;
-        /** slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_st:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_st_reg_t;
-
-/** Type of pkt_len register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len:20;
-        /** hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len_reg_t;
-
-/** Type of state_w0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_state0 : RO; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state0:8;
-        /** slchost_state1 : RO; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state1:8;
-        /** slchost_state2 : RO; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state2:8;
-        /** slchost_state3 : RO; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state3:8;
-    };
-    uint32_t val;
-} slchost_state_w0_reg_t;
-
-/** Type of state_w1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_state4 : RO; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state4:8;
-        /** slchost_state5 : RO; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state5:8;
-        /** slchost_state6 : RO; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state6:8;
-        /** slchost_state7 : RO; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state7:8;
-    };
-    uint32_t val;
-} slchost_state_w1_reg_t;
-
-/** Type of conf_w0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf0 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf0:8;
-        /** slchost_conf1 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf1:8;
-        /** slchost_conf2 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf2:8;
-        /** slchost_conf3 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf3:8;
-    };
-    uint32_t val;
-} slchost_conf_w0_reg_t;
-
-/** Type of conf_w1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf4 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf4:8;
-        /** slchost_conf5 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf5:8;
-        /** slchost_conf6 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf6:8;
-        /** slchost_conf7 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf7:8;
-    };
-    uint32_t val;
-} slchost_conf_w1_reg_t;
-
-/** Type of conf_w2 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf8 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf8:8;
-        /** slchost_conf9 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf9:8;
-        /** slchost_conf10 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf10:8;
-        /** slchost_conf11 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf11:8;
-    };
-    uint32_t val;
-} slchost_conf_w2_reg_t;
-
-/** Type of conf_w3 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf12 : R/W; bitpos: [7:0]; default: 192;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf12:8;
-        /** slchost_conf13 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf13:8;
-        /** slchost_conf14 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf14:8;
-        /** slchost_conf15 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf15:8;
-    };
-    uint32_t val;
-} slchost_conf_w3_reg_t;
-
-/** Type of conf_w4 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf16 : R/W; bitpos: [7:0]; default: 255;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf16:8;
-        /** slchost_conf17 : R/W; bitpos: [15:8]; default: 1;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf17:8;
-        /** slchost_conf18 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf18:8;
-        /** slchost_conf19 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf19:8;
-    };
-    uint32_t val;
-} slchost_conf_w4_reg_t;
-
-/** Type of conf_w5 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf20 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf20:8;
-        /** slchost_conf21 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf21:8;
-        /** slchost_conf22 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf22:8;
-        /** slchost_conf23 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf23:8;
-    };
-    uint32_t val;
-} slchost_conf_w5_reg_t;
-
-/** Type of win_cmd register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_win_cmd : R/W; bitpos: [15:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_win_cmd:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} slchost_win_cmd_reg_t;
-
-/** Type of conf_w6 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf24 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf24:8;
-        /** slchost_conf25 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf25:8;
-        /** slchost_conf26 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf26:8;
-        /** slchost_conf27 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf27:8;
-    };
-    uint32_t val;
-} slchost_conf_w6_reg_t;
-
-/** Type of conf_w7 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf28 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf28:8;
-        /** slchost_conf29 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf29:8;
-        /** slchost_conf30 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf30:8;
-        /** slchost_conf31 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf31:8;
-    };
-    uint32_t val;
-} slchost_conf_w7_reg_t;
-
-/** Type of pkt_len0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len0:20;
-        /** hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len0_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len0_reg_t;
-
-/** Type of pkt_len1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len1:20;
-        /** hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len1_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len1_reg_t;
-
-/** Type of pkt_len2 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len2:20;
-        /** hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len2_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len2_reg_t;
-
-/** Type of conf_w8 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf32 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf32:8;
-        /** slchost_conf33 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf33:8;
-        /** slchost_conf34 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf34:8;
-        /** slchost_conf35 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf35:8;
-    };
-    uint32_t val;
-} slchost_conf_w8_reg_t;
-
-/** Type of conf_w9 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf36 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf36:8;
-        /** slchost_conf37 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf37:8;
-        /** slchost_conf38 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf38:8;
-        /** slchost_conf39 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf39:8;
-    };
-    uint32_t val;
-} slchost_conf_w9_reg_t;
-
-/** Type of conf_w10 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf40 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf40:8;
-        /** slchost_conf41 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf41:8;
-        /** slchost_conf42 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf42:8;
-        /** slchost_conf43 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf43:8;
-    };
-    uint32_t val;
-} slchost_conf_w10_reg_t;
-
-/** Type of conf_w11 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf44 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf44:8;
-        /** slchost_conf45 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf45:8;
-        /** slchost_conf46 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf46:8;
-        /** slchost_conf47 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf47:8;
-    };
-    uint32_t val;
-} slchost_conf_w11_reg_t;
-
-/** Type of conf_w12 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf48 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf48:8;
-        /** slchost_conf49 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf49:8;
-        /** slchost_conf50 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf50:8;
-        /** slchost_conf51 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf51:8;
-    };
-    uint32_t val;
-} slchost_conf_w12_reg_t;
-
-/** Type of conf_w13 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf52 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf52:8;
-        /** slchost_conf53 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf53:8;
-        /** slchost_conf54 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf54:8;
-        /** slchost_conf55 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf55:8;
-    };
-    uint32_t val;
-} slchost_conf_w13_reg_t;
-
-/** Type of conf_w14 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf56 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf56:8;
-        /** slchost_conf57 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf57:8;
-        /** slchost_conf58 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf58:8;
-        /** slchost_conf59 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf59:8;
-    };
-    uint32_t val;
-} slchost_conf_w14_reg_t;
-
-/** Type of conf_w15 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf60 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf60:8;
-        /** slchost_conf61 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf61:8;
-        /** slchost_conf62 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf62:8;
-        /** slchost_conf63 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf63:8;
-    };
-    uint32_t val;
-} slchost_conf_w15_reg_t;
-
-/** Type of check_sum0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_check_sum0 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_check_sum0:32;
-    };
-    uint32_t val;
-} slchost_check_sum0_reg_t;
-
-/** Type of check_sum1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_check_sum1 : RO; bitpos: [31:0]; default: 319;
-         *  *******Description***********
-         */
-        uint32_t slchost_check_sum1:32;
-    };
-    uint32_t val;
-} slchost_check_sum1_reg_t;
-
-/** Type of slc1host_token_rdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_token0 : RO; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0:12;
-        /** slc1_rx_pf_valid : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid:1;
-        uint32_t reserved_13:3;
-        /** hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc1_token1:12;
-        /** slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_eof:4;
-    };
-    uint32_t val;
-} slchost_slc1host_token_rdata_reg_t;
-
-/** Type of slc0host_token_wdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token0_wd:12;
-        uint32_t reserved_12:4;
-        /** slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token1_wd:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} slchost_slc0host_token_wdata_reg_t;
-
-/** Type of slc1host_token_wdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token0_wd:12;
-        uint32_t reserved_12:4;
-        /** slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token1_wd:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} slchost_slc1host_token_wdata_reg_t;
-
-/** Type of token_con register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_token0_dec : WT; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token0_dec:1;
-        /** slc0host_token1_dec : WT; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token1_dec:1;
-        /** slc0host_token0_wr : WT; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token0_wr:1;
-        /** slc0host_token1_wr : WT; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token1_wr:1;
-        /** slc1host_token0_dec : WT; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token0_dec:1;
-        /** slc1host_token1_dec : WT; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token1_dec:1;
-        /** slc1host_token0_wr : WT; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token0_wr:1;
-        /** slc1host_token1_wr : WT; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token1_wr:1;
-        /** slc0host_len_wr : WT; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_len_wr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} slchost_token_con_reg_t;
-
-/** Type of slc0host_int_clr register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_clr:1;
-        /** slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_clr:1;
-        /** slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_clr:1;
-        /** slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_clr:1;
-        /** slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_clr:1;
-        /** slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_clr:1;
-        /** slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_clr:1;
-        /** slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_clr:1;
-        /** slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_clr:1;
-        /** slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_clr:1;
-        /** slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_clr:1;
-        /** slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_clr:1;
-        /** slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_clr:1;
-        /** slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_clr:1;
-        /** slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_clr:1;
-        /** slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_clr:1;
-        /** slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_clr:1;
-        /** slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_clr:1;
-        /** slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_clr:1;
-        /** slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_clr:1;
-        /** slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_clr:1;
-        /** slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_clr:1;
-        /** slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_clr:1;
-        /** slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_clr:1;
-        /** slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_clr:1;
-        /** gpio_sdio_int_clr : WT; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_clr:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_clr_reg_t;
-
-/** Type of slc1host_int_clr register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_clr:1;
-        /** slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_clr:1;
-        /** slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_clr:1;
-        /** slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_clr:1;
-        /** slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_clr:1;
-        /** slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_clr:1;
-        /** slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_clr:1;
-        /** slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_clr:1;
-        /** slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_clr:1;
-        /** slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_clr:1;
-        /** slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_clr:1;
-        /** slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_clr:1;
-        /** slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_clr:1;
-        /** slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_clr:1;
-        /** slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_clr:1;
-        /** slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_clr:1;
-        /** slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_clr:1;
-        /** slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_clr:1;
-        /** slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_clr:1;
-        /** slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_clr:1;
-        /** slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_clr:1;
-        /** slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_clr:1;
-        /** slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_clr:1;
-        /** slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_clr:1;
-        /** slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_clr:1;
-        /** slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_clr:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_clr_reg_t;
-
-/** Type of slc0host_func1_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit0_int_ena:1;
-        /** fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit1_int_ena:1;
-        /** fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit2_int_ena:1;
-        /** fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit3_int_ena:1;
-        /** fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit4_int_ena:1;
-        /** fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit5_int_ena:1;
-        /** fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit6_int_ena:1;
-        /** fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit7_int_ena:1;
-        /** fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token0_1to0_int_ena:1;
-        /** fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token1_1to0_int_ena:1;
-        /** fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token0_0to1_int_ena:1;
-        /** fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token1_0to1_int_ena:1;
-        /** fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_rx_sof_int_ena:1;
-        /** fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_rx_eof_int_ena:1;
-        /** fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_rx_start_int_ena:1;
-        /** fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_tx_start_int_ena:1;
-        /** fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_rx_udf_int_ena:1;
-        /** fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tx_ovf_int_ena:1;
-        /** fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_rx_pf_valid_int_ena:1;
-        /** fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit0_int_ena:1;
-        /** fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit1_int_ena:1;
-        /** fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit2_int_ena:1;
-        /** fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit3_int_ena:1;
-        /** fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_rx_new_packet_int_ena:1;
-        /** fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_host_rd_retry_int_ena:1;
-        /** fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_gpio_sdio_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_func1_int_ena_reg_t;
-
-/** Type of slc1host_func1_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit0_int_ena:1;
-        /** fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit1_int_ena:1;
-        /** fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit2_int_ena:1;
-        /** fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit3_int_ena:1;
-        /** fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit4_int_ena:1;
-        /** fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit5_int_ena:1;
-        /** fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit6_int_ena:1;
-        /** fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit7_int_ena:1;
-        /** fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token0_1to0_int_ena:1;
-        /** fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token1_1to0_int_ena:1;
-        /** fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token0_0to1_int_ena:1;
-        /** fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token1_0to1_int_ena:1;
-        /** fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_rx_sof_int_ena:1;
-        /** fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_rx_eof_int_ena:1;
-        /** fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_rx_start_int_ena:1;
-        /** fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_tx_start_int_ena:1;
-        /** fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_rx_udf_int_ena:1;
-        /** fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tx_ovf_int_ena:1;
-        /** fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_rx_pf_valid_int_ena:1;
-        /** fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit0_int_ena:1;
-        /** fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit1_int_ena:1;
-        /** fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit2_int_ena:1;
-        /** fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit3_int_ena:1;
-        /** fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_wifi_rx_new_packet_int_ena:1;
-        /** fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_host_rd_retry_int_ena:1;
-        /** fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_bt_rx_new_packet_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_func1_int_ena_reg_t;
-
-/** Type of slc0host_func2_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit0_int_ena:1;
-        /** fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit1_int_ena:1;
-        /** fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit2_int_ena:1;
-        /** fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit3_int_ena:1;
-        /** fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit4_int_ena:1;
-        /** fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit5_int_ena:1;
-        /** fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit6_int_ena:1;
-        /** fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit7_int_ena:1;
-        /** fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token0_1to0_int_ena:1;
-        /** fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token1_1to0_int_ena:1;
-        /** fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token0_0to1_int_ena:1;
-        /** fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token1_0to1_int_ena:1;
-        /** fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_rx_sof_int_ena:1;
-        /** fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_rx_eof_int_ena:1;
-        /** fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_rx_start_int_ena:1;
-        /** fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_tx_start_int_ena:1;
-        /** fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_rx_udf_int_ena:1;
-        /** fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tx_ovf_int_ena:1;
-        /** fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_rx_pf_valid_int_ena:1;
-        /** fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit0_int_ena:1;
-        /** fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit1_int_ena:1;
-        /** fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit2_int_ena:1;
-        /** fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit3_int_ena:1;
-        /** fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_rx_new_packet_int_ena:1;
-        /** fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_host_rd_retry_int_ena:1;
-        /** fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_gpio_sdio_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_func2_int_ena_reg_t;
-
-/** Type of slc1host_func2_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit0_int_ena:1;
-        /** fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit1_int_ena:1;
-        /** fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit2_int_ena:1;
-        /** fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit3_int_ena:1;
-        /** fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit4_int_ena:1;
-        /** fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit5_int_ena:1;
-        /** fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit6_int_ena:1;
-        /** fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit7_int_ena:1;
-        /** fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token0_1to0_int_ena:1;
-        /** fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token1_1to0_int_ena:1;
-        /** fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token0_0to1_int_ena:1;
-        /** fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token1_0to1_int_ena:1;
-        /** fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_rx_sof_int_ena:1;
-        /** fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_rx_eof_int_ena:1;
-        /** fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_rx_start_int_ena:1;
-        /** fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_tx_start_int_ena:1;
-        /** fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_rx_udf_int_ena:1;
-        /** fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tx_ovf_int_ena:1;
-        /** fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_rx_pf_valid_int_ena:1;
-        /** fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit0_int_ena:1;
-        /** fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit1_int_ena:1;
-        /** fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit2_int_ena:1;
-        /** fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit3_int_ena:1;
-        /** fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_wifi_rx_new_packet_int_ena:1;
-        /** fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_host_rd_retry_int_ena:1;
-        /** fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_bt_rx_new_packet_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_func2_int_ena_reg_t;
-
-/** Type of slc0host_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_ena:1;
-        /** slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_ena:1;
-        /** slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_ena:1;
-        /** slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_ena:1;
-        /** slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_ena:1;
-        /** slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_ena:1;
-        /** slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_ena:1;
-        /** slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_ena:1;
-        /** slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_ena:1;
-        /** slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_ena:1;
-        /** slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_ena:1;
-        /** slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_ena:1;
-        /** slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_ena:1;
-        /** slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_ena:1;
-        /** slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_ena:1;
-        /** slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_ena:1;
-        /** slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_ena:1;
-        /** slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_ena:1;
-        /** slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_ena:1;
-        /** slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_ena:1;
-        /** slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_ena:1;
-        /** slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_ena:1;
-        /** slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_ena:1;
-        /** slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_ena:1;
-        /** slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_ena:1;
-        /** gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_ena_reg_t;
-
-/** Type of slc1host_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_ena:1;
-        /** slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_ena:1;
-        /** slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_ena:1;
-        /** slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_ena:1;
-        /** slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_ena:1;
-        /** slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_ena:1;
-        /** slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_ena:1;
-        /** slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_ena:1;
-        /** slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_ena:1;
-        /** slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_ena:1;
-        /** slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_ena:1;
-        /** slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_ena:1;
-        /** slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_ena:1;
-        /** slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_ena:1;
-        /** slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_ena:1;
-        /** slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_ena:1;
-        /** slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_ena:1;
-        /** slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_ena:1;
-        /** slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_ena:1;
-        /** slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_ena:1;
-        /** slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_ena:1;
-        /** slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_ena:1;
-        /** slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_ena:1;
-        /** slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_ena:1;
-        /** slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_ena:1;
-        /** slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_ena_reg_t;
-
-/** Type of slc0host_rx_infor register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_infor:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} slchost_slc0host_rx_infor_reg_t;
-
-/** Type of slc1host_rx_infor register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_infor:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} slchost_slc1host_rx_infor_reg_t;
-
-/** Type of slc0host_len_wd register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_len_wd : R/W; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_len_wd:32;
-    };
-    uint32_t val;
-} slchost_slc0host_len_wd_reg_t;
-
-/** Type of slc_apbwin_wdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_wdata:32;
-    };
-    uint32_t val;
-} slchost_slc_apbwin_wdata_reg_t;
-
-/** Type of slc_apbwin_conf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_addr:28;
-        /** slc_apbwin_wr : R/W; bitpos: [28]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_wr:1;
-        /** slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_start:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} slchost_slc_apbwin_conf_reg_t;
-
-/** Type of slc_apbwin_rdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_rdata:32;
-    };
-    uint32_t val;
-} slchost_slc_apbwin_rdata_reg_t;
-
-/** Type of rdclr0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc0_bit7_clraddr:9;
-        /** slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc0_bit6_clraddr:9;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} slchost_rdclr0_reg_t;
-
-/** Type of rdclr1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc1_bit7_clraddr:9;
-        /** slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc1_bit6_clraddr:9;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} slchost_rdclr1_reg_t;
-
-/** Type of slc0host_int_ena1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_ena1:1;
-        /** slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_ena1:1;
-        /** slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_ena1:1;
-        /** slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_ena1:1;
-        /** slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_ena1:1;
-        /** slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_ena1:1;
-        /** slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_ena1:1;
-        /** slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_ena1:1;
-        /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_ena1:1;
-        /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_ena1:1;
-        /** slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_ena1:1;
-        /** slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_ena1:1;
-        /** slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_ena1:1;
-        /** slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_ena1:1;
-        /** slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_ena1:1;
-        /** slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_ena1:1;
-        /** slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_ena1:1;
-        /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_ena1:1;
-        /** slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_ena1:1;
-        /** slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_ena1:1;
-        /** slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_ena1:1;
-        /** slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_ena1:1;
-        /** slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_ena1:1;
-        /** slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_ena1:1;
-        /** slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_ena1:1;
-        /** gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_ena1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_ena1_reg_t;
-
-/** Type of slc1host_int_ena1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_ena1:1;
-        /** slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_ena1:1;
-        /** slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_ena1:1;
-        /** slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_ena1:1;
-        /** slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_ena1:1;
-        /** slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_ena1:1;
-        /** slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_ena1:1;
-        /** slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_ena1:1;
-        /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_ena1:1;
-        /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_ena1:1;
-        /** slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_ena1:1;
-        /** slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_ena1:1;
-        /** slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_ena1:1;
-        /** slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_ena1:1;
-        /** slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_ena1:1;
-        /** slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_ena1:1;
-        /** slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_ena1:1;
-        /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_ena1:1;
-        /** slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_ena1:1;
-        /** slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_ena1:1;
-        /** slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_ena1:1;
-        /** slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_ena1:1;
-        /** slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_ena1:1;
-        /** slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_ena1:1;
-        /** slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_ena1:1;
-        /** slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_ena1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_ena1_reg_t;
-
-/** Type of slchostdate register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_date : R/W; bitpos: [31:0]; default: 554043136;
-         *  *******Description***********
-         */
-        uint32_t slchost_date:32;
-    };
-    uint32_t val;
-} slchost_slchostdate_reg_t;
-
-/** Type of slchostid register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_id : R/W; bitpos: [31:0]; default: 1536;
-         *  *******Description***********
-         */
-        uint32_t slchost_id:32;
-    };
-    uint32_t val;
-} slchost_slchostid_reg_t;
-
-/** Type of conf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** frc_sdio11 : R/W; bitpos: [4:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_sdio11:5;
-        /** frc_sdio20 : R/W; bitpos: [9:5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_sdio20:5;
-        /** frc_neg_samp : R/W; bitpos: [14:10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_neg_samp:5;
-        /** frc_pos_samp : R/W; bitpos: [19:15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_pos_samp:5;
-        /** frc_quick_in : R/W; bitpos: [24:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_quick_in:5;
-        /** sdio20_int_delay : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio20_int_delay:1;
-        /** sdio_pad_pullup : R/W; bitpos: [26]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio_pad_pullup:1;
-        /** hspeed_con_en : R/W; bitpos: [27]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hspeed_con_en:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} slchost_conf_reg_t;
-
-/** Type of inf_st register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** sdio20_mode : RO; bitpos: [4:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio20_mode:5;
-        /** sdio_neg_samp : RO; bitpos: [9:5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio_neg_samp:5;
-        /** sdio_quick_in : RO; bitpos: [14:10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio_quick_in:5;
-        /** dll_on_sw : R/W; bitpos: [15]; default: 0;
-         *  dll is controlled by software
-         */
-        uint32_t dll_on_sw:1;
-        /** dll_on : R/W; bitpos: [16]; default: 0;
-         *  Software dll on
-         */
-        uint32_t dll_on:1;
-        /** clk_mode_sw : R/W; bitpos: [17]; default: 0;
-         *  dll clock mode is controlled by software
-         */
-        uint32_t clk_mode_sw:1;
-        /** clk_mode : R/W; bitpos: [19:18]; default: 0;
-         *  Software set clock mode
-         */
-        uint32_t clk_mode:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} slchost_inf_st_reg_t;
-
-
-typedef struct host_dev_t {
-    uint32_t reserved_000[4];
-    volatile slchost_func2_0_reg_t func2_0;
-    volatile slchost_func2_1_reg_t func2_1;
-    uint32_t reserved_018[2];
-    volatile slchost_func2_2_reg_t func2_2;
-    uint32_t reserved_024[4];
-    volatile slchost_gpio_status0_reg_t gpio_status0;
-    volatile slchost_gpio_status1_reg_t gpio_status1;
-    volatile slchost_gpio_in0_reg_t gpio_in0;
-    volatile slchost_gpio_in1_reg_t gpio_in1;
-    volatile slchost_slc0host_token_rdata_reg_t slc0host_token_rdata;
-    volatile slchost_slc0_host_pf_reg_t slc0_host_pf;
-    volatile slchost_slc1_host_pf_reg_t slc1_host_pf;
-    volatile slchost_slc0host_int_raw_reg_t slc0host_int_raw;
-    volatile slchost_slc1host_int_raw_reg_t slc1host_int_raw;
-    volatile slchost_slc0host_int_st_reg_t slc0host_int_st;
-    volatile slchost_slc1host_int_st_reg_t slc1host_int_st;
-    volatile slchost_pkt_len_reg_t pkt_len;
-    volatile slchost_state_w0_reg_t state_w0;
-    volatile slchost_state_w1_reg_t state_w1;
-    volatile slchost_conf_w0_reg_t conf_w0;
-    volatile slchost_conf_w1_reg_t conf_w1;
-    volatile slchost_conf_w2_reg_t conf_w2;
-    volatile slchost_conf_w3_reg_t conf_w3;
-    volatile slchost_conf_w4_reg_t conf_w4;
-    volatile slchost_conf_w5_reg_t conf_w5;
-    volatile slchost_win_cmd_reg_t win_cmd;
-    volatile slchost_conf_w6_reg_t conf_w6;
-    volatile slchost_conf_w7_reg_t conf_w7;
-    volatile slchost_pkt_len0_reg_t pkt_len0;
-    volatile slchost_pkt_len1_reg_t pkt_len1;
-    volatile slchost_pkt_len2_reg_t pkt_len2;
-    volatile slchost_conf_w8_reg_t conf_w8;
-    volatile slchost_conf_w9_reg_t conf_w9;
-    volatile slchost_conf_w10_reg_t conf_w10;
-    volatile slchost_conf_w11_reg_t conf_w11;
-    volatile slchost_conf_w12_reg_t conf_w12;
-    volatile slchost_conf_w13_reg_t conf_w13;
-    volatile slchost_conf_w14_reg_t conf_w14;
-    volatile slchost_conf_w15_reg_t conf_w15;
-    volatile slchost_check_sum0_reg_t check_sum0;
-    volatile slchost_check_sum1_reg_t check_sum1;
-    volatile slchost_slc1host_token_rdata_reg_t slc1host_token_rdata;
-    volatile slchost_slc0host_token_wdata_reg_t slc0host_token_wdata;
-    volatile slchost_slc1host_token_wdata_reg_t slc1host_token_wdata;
-    volatile slchost_token_con_reg_t token_con;
-    volatile slchost_slc0host_int_clr_reg_t slc0host_int_clr;
-    volatile slchost_slc1host_int_clr_reg_t slc1host_int_clr;
-    volatile slchost_slc0host_func1_int_ena_reg_t slc0host_func1_int_ena;
-    volatile slchost_slc1host_func1_int_ena_reg_t slc1host_func1_int_ena;
-    volatile slchost_slc0host_func2_int_ena_reg_t slc0host_func2_int_ena;
-    volatile slchost_slc1host_func2_int_ena_reg_t slc1host_func2_int_ena;
-    volatile slchost_slc0host_int_ena_reg_t slc0host_int_ena;
-    volatile slchost_slc1host_int_ena_reg_t slc1host_int_ena;
-    volatile slchost_slc0host_rx_infor_reg_t slc0host_rx_infor;
-    volatile slchost_slc1host_rx_infor_reg_t slc1host_rx_infor;
-    volatile slchost_slc0host_len_wd_reg_t slc0host_len_wd;
-    volatile slchost_slc_apbwin_wdata_reg_t slc_apbwin_wdata;
-    volatile slchost_slc_apbwin_conf_reg_t slc_apbwin_conf;
-    volatile slchost_slc_apbwin_rdata_reg_t slc_apbwin_rdata;
-    volatile slchost_rdclr0_reg_t rdclr0;
-    volatile slchost_rdclr1_reg_t rdclr1;
-    volatile slchost_slc0host_int_ena1_reg_t slc0host_int_ena1;
-    volatile slchost_slc1host_int_ena1_reg_t slc1host_int_ena1;
-    uint32_t reserved_11c[23];
-    volatile slchost_slchostdate_reg_t slchostdate;
-    volatile slchost_slchostid_reg_t slchostid;
-    uint32_t reserved_180[28];
-    volatile slchost_conf_reg_t conf;
-    volatile slchost_inf_st_reg_t inf_st;
-} host_dev_t;
-
-extern host_dev_t HOST;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(host_dev_t) == 0x1f8, "Invalid size of host_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hp_apm_reg.h b/components/soc/esp32p4/include/soc/hp_apm_reg.h
deleted file mode 100644
index 4a9151ab69..0000000000
--- a/components/soc/esp32p4/include/soc/hp_apm_reg.h
+++ /dev/null
@@ -1,1838 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HP_APM_REGION_FILTER_EN_REG register
- *  Region filter enable register
- */
-#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0)
-/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1;
- *  Region filter enable
- */
-#define HP_APM_REGION_FILTER_EN    0x0000FFFFU
-#define HP_APM_REGION_FILTER_EN_M  (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S)
-#define HP_APM_REGION_FILTER_EN_V  0x0000FFFFU
-#define HP_APM_REGION_FILTER_EN_S  0
-
-/** HP_APM_REGION0_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4)
-/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region0
- */
-#define HP_APM_REGION0_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_START_M  (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S)
-#define HP_APM_REGION0_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_START_S  0
-
-/** HP_APM_REGION0_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8)
-/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region0
- */
-#define HP_APM_REGION0_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_END_M  (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S)
-#define HP_APM_REGION0_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_END_S  0
-
-/** HP_APM_REGION0_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc)
-/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION0_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION0_R0_PMS_X_M  (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S)
-#define HP_APM_REGION0_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION0_R0_PMS_X_S  0
-/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION0_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION0_R0_PMS_W_M  (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S)
-#define HP_APM_REGION0_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION0_R0_PMS_W_S  1
-/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION0_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION0_R0_PMS_R_M  (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S)
-#define HP_APM_REGION0_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION0_R0_PMS_R_S  2
-/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION0_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION0_R1_PMS_X_M  (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S)
-#define HP_APM_REGION0_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION0_R1_PMS_X_S  4
-/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION0_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION0_R1_PMS_W_M  (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S)
-#define HP_APM_REGION0_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION0_R1_PMS_W_S  5
-/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION0_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION0_R1_PMS_R_M  (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S)
-#define HP_APM_REGION0_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION0_R1_PMS_R_S  6
-/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION0_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION0_R2_PMS_X_M  (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S)
-#define HP_APM_REGION0_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION0_R2_PMS_X_S  8
-/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION0_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION0_R2_PMS_W_M  (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S)
-#define HP_APM_REGION0_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION0_R2_PMS_W_S  9
-/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION0_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION0_R2_PMS_R_M  (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S)
-#define HP_APM_REGION0_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION0_R2_PMS_R_S  10
-
-/** HP_APM_REGION1_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10)
-/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region1
- */
-#define HP_APM_REGION1_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_START_M  (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S)
-#define HP_APM_REGION1_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_START_S  0
-
-/** HP_APM_REGION1_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14)
-/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region1
- */
-#define HP_APM_REGION1_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_END_M  (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S)
-#define HP_APM_REGION1_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_END_S  0
-
-/** HP_APM_REGION1_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18)
-/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION1_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION1_R0_PMS_X_M  (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S)
-#define HP_APM_REGION1_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION1_R0_PMS_X_S  0
-/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION1_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION1_R0_PMS_W_M  (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S)
-#define HP_APM_REGION1_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION1_R0_PMS_W_S  1
-/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION1_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION1_R0_PMS_R_M  (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S)
-#define HP_APM_REGION1_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION1_R0_PMS_R_S  2
-/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION1_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION1_R1_PMS_X_M  (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S)
-#define HP_APM_REGION1_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION1_R1_PMS_X_S  4
-/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION1_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION1_R1_PMS_W_M  (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S)
-#define HP_APM_REGION1_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION1_R1_PMS_W_S  5
-/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION1_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION1_R1_PMS_R_M  (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S)
-#define HP_APM_REGION1_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION1_R1_PMS_R_S  6
-/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION1_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION1_R2_PMS_X_M  (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S)
-#define HP_APM_REGION1_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION1_R2_PMS_X_S  8
-/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION1_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION1_R2_PMS_W_M  (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S)
-#define HP_APM_REGION1_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION1_R2_PMS_W_S  9
-/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION1_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION1_R2_PMS_R_M  (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S)
-#define HP_APM_REGION1_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION1_R2_PMS_R_S  10
-
-/** HP_APM_REGION2_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c)
-/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region2
- */
-#define HP_APM_REGION2_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_START_M  (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S)
-#define HP_APM_REGION2_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_START_S  0
-
-/** HP_APM_REGION2_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20)
-/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region2
- */
-#define HP_APM_REGION2_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_END_M  (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S)
-#define HP_APM_REGION2_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_END_S  0
-
-/** HP_APM_REGION2_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24)
-/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION2_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION2_R0_PMS_X_M  (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S)
-#define HP_APM_REGION2_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION2_R0_PMS_X_S  0
-/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION2_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION2_R0_PMS_W_M  (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S)
-#define HP_APM_REGION2_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION2_R0_PMS_W_S  1
-/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION2_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION2_R0_PMS_R_M  (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S)
-#define HP_APM_REGION2_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION2_R0_PMS_R_S  2
-/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION2_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION2_R1_PMS_X_M  (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S)
-#define HP_APM_REGION2_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION2_R1_PMS_X_S  4
-/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION2_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION2_R1_PMS_W_M  (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S)
-#define HP_APM_REGION2_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION2_R1_PMS_W_S  5
-/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION2_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION2_R1_PMS_R_M  (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S)
-#define HP_APM_REGION2_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION2_R1_PMS_R_S  6
-/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION2_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION2_R2_PMS_X_M  (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S)
-#define HP_APM_REGION2_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION2_R2_PMS_X_S  8
-/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION2_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION2_R2_PMS_W_M  (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S)
-#define HP_APM_REGION2_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION2_R2_PMS_W_S  9
-/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION2_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION2_R2_PMS_R_M  (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S)
-#define HP_APM_REGION2_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION2_R2_PMS_R_S  10
-
-/** HP_APM_REGION3_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28)
-/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region3
- */
-#define HP_APM_REGION3_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_START_M  (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S)
-#define HP_APM_REGION3_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_START_S  0
-
-/** HP_APM_REGION3_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c)
-/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region3
- */
-#define HP_APM_REGION3_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_END_M  (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S)
-#define HP_APM_REGION3_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_END_S  0
-
-/** HP_APM_REGION3_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30)
-/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION3_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION3_R0_PMS_X_M  (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S)
-#define HP_APM_REGION3_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION3_R0_PMS_X_S  0
-/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION3_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION3_R0_PMS_W_M  (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S)
-#define HP_APM_REGION3_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION3_R0_PMS_W_S  1
-/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION3_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION3_R0_PMS_R_M  (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S)
-#define HP_APM_REGION3_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION3_R0_PMS_R_S  2
-/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION3_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION3_R1_PMS_X_M  (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S)
-#define HP_APM_REGION3_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION3_R1_PMS_X_S  4
-/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION3_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION3_R1_PMS_W_M  (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S)
-#define HP_APM_REGION3_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION3_R1_PMS_W_S  5
-/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION3_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION3_R1_PMS_R_M  (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S)
-#define HP_APM_REGION3_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION3_R1_PMS_R_S  6
-/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION3_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION3_R2_PMS_X_M  (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S)
-#define HP_APM_REGION3_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION3_R2_PMS_X_S  8
-/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION3_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION3_R2_PMS_W_M  (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S)
-#define HP_APM_REGION3_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION3_R2_PMS_W_S  9
-/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION3_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION3_R2_PMS_R_M  (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S)
-#define HP_APM_REGION3_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION3_R2_PMS_R_S  10
-
-/** HP_APM_REGION4_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34)
-/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region4
- */
-#define HP_APM_REGION4_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_START_M  (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S)
-#define HP_APM_REGION4_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_START_S  0
-
-/** HP_APM_REGION4_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38)
-/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region4
- */
-#define HP_APM_REGION4_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_END_M  (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S)
-#define HP_APM_REGION4_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_END_S  0
-
-/** HP_APM_REGION4_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c)
-/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION4_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION4_R0_PMS_X_M  (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S)
-#define HP_APM_REGION4_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION4_R0_PMS_X_S  0
-/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION4_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION4_R0_PMS_W_M  (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S)
-#define HP_APM_REGION4_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION4_R0_PMS_W_S  1
-/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION4_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION4_R0_PMS_R_M  (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S)
-#define HP_APM_REGION4_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION4_R0_PMS_R_S  2
-/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION4_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION4_R1_PMS_X_M  (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S)
-#define HP_APM_REGION4_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION4_R1_PMS_X_S  4
-/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION4_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION4_R1_PMS_W_M  (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S)
-#define HP_APM_REGION4_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION4_R1_PMS_W_S  5
-/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION4_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION4_R1_PMS_R_M  (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S)
-#define HP_APM_REGION4_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION4_R1_PMS_R_S  6
-/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION4_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION4_R2_PMS_X_M  (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S)
-#define HP_APM_REGION4_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION4_R2_PMS_X_S  8
-/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION4_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION4_R2_PMS_W_M  (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S)
-#define HP_APM_REGION4_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION4_R2_PMS_W_S  9
-/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION4_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION4_R2_PMS_R_M  (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S)
-#define HP_APM_REGION4_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION4_R2_PMS_R_S  10
-
-/** HP_APM_REGION5_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40)
-/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region5
- */
-#define HP_APM_REGION5_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_START_M  (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S)
-#define HP_APM_REGION5_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_START_S  0
-
-/** HP_APM_REGION5_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44)
-/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region5
- */
-#define HP_APM_REGION5_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_END_M  (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S)
-#define HP_APM_REGION5_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_END_S  0
-
-/** HP_APM_REGION5_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48)
-/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION5_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION5_R0_PMS_X_M  (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S)
-#define HP_APM_REGION5_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION5_R0_PMS_X_S  0
-/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION5_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION5_R0_PMS_W_M  (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S)
-#define HP_APM_REGION5_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION5_R0_PMS_W_S  1
-/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION5_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION5_R0_PMS_R_M  (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S)
-#define HP_APM_REGION5_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION5_R0_PMS_R_S  2
-/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION5_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION5_R1_PMS_X_M  (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S)
-#define HP_APM_REGION5_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION5_R1_PMS_X_S  4
-/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION5_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION5_R1_PMS_W_M  (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S)
-#define HP_APM_REGION5_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION5_R1_PMS_W_S  5
-/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION5_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION5_R1_PMS_R_M  (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S)
-#define HP_APM_REGION5_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION5_R1_PMS_R_S  6
-/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION5_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION5_R2_PMS_X_M  (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S)
-#define HP_APM_REGION5_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION5_R2_PMS_X_S  8
-/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION5_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION5_R2_PMS_W_M  (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S)
-#define HP_APM_REGION5_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION5_R2_PMS_W_S  9
-/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION5_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION5_R2_PMS_R_M  (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S)
-#define HP_APM_REGION5_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION5_R2_PMS_R_S  10
-
-/** HP_APM_REGION6_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c)
-/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region6
- */
-#define HP_APM_REGION6_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_START_M  (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S)
-#define HP_APM_REGION6_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_START_S  0
-
-/** HP_APM_REGION6_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50)
-/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region6
- */
-#define HP_APM_REGION6_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_END_M  (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S)
-#define HP_APM_REGION6_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_END_S  0
-
-/** HP_APM_REGION6_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54)
-/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION6_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION6_R0_PMS_X_M  (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S)
-#define HP_APM_REGION6_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION6_R0_PMS_X_S  0
-/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION6_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION6_R0_PMS_W_M  (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S)
-#define HP_APM_REGION6_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION6_R0_PMS_W_S  1
-/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION6_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION6_R0_PMS_R_M  (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S)
-#define HP_APM_REGION6_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION6_R0_PMS_R_S  2
-/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION6_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION6_R1_PMS_X_M  (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S)
-#define HP_APM_REGION6_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION6_R1_PMS_X_S  4
-/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION6_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION6_R1_PMS_W_M  (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S)
-#define HP_APM_REGION6_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION6_R1_PMS_W_S  5
-/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION6_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION6_R1_PMS_R_M  (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S)
-#define HP_APM_REGION6_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION6_R1_PMS_R_S  6
-/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION6_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION6_R2_PMS_X_M  (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S)
-#define HP_APM_REGION6_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION6_R2_PMS_X_S  8
-/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION6_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION6_R2_PMS_W_M  (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S)
-#define HP_APM_REGION6_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION6_R2_PMS_W_S  9
-/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION6_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION6_R2_PMS_R_M  (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S)
-#define HP_APM_REGION6_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION6_R2_PMS_R_S  10
-
-/** HP_APM_REGION7_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58)
-/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region7
- */
-#define HP_APM_REGION7_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_START_M  (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S)
-#define HP_APM_REGION7_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_START_S  0
-
-/** HP_APM_REGION7_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c)
-/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region7
- */
-#define HP_APM_REGION7_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_END_M  (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S)
-#define HP_APM_REGION7_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_END_S  0
-
-/** HP_APM_REGION7_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60)
-/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION7_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION7_R0_PMS_X_M  (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S)
-#define HP_APM_REGION7_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION7_R0_PMS_X_S  0
-/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION7_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION7_R0_PMS_W_M  (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S)
-#define HP_APM_REGION7_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION7_R0_PMS_W_S  1
-/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION7_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION7_R0_PMS_R_M  (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S)
-#define HP_APM_REGION7_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION7_R0_PMS_R_S  2
-/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION7_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION7_R1_PMS_X_M  (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S)
-#define HP_APM_REGION7_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION7_R1_PMS_X_S  4
-/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION7_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION7_R1_PMS_W_M  (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S)
-#define HP_APM_REGION7_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION7_R1_PMS_W_S  5
-/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION7_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION7_R1_PMS_R_M  (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S)
-#define HP_APM_REGION7_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION7_R1_PMS_R_S  6
-/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION7_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION7_R2_PMS_X_M  (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S)
-#define HP_APM_REGION7_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION7_R2_PMS_X_S  8
-/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION7_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION7_R2_PMS_W_M  (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S)
-#define HP_APM_REGION7_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION7_R2_PMS_W_S  9
-/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION7_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION7_R2_PMS_R_M  (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S)
-#define HP_APM_REGION7_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION7_R2_PMS_R_S  10
-
-/** HP_APM_REGION8_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64)
-/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region8
- */
-#define HP_APM_REGION8_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_START_M  (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S)
-#define HP_APM_REGION8_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_START_S  0
-
-/** HP_APM_REGION8_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68)
-/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region8
- */
-#define HP_APM_REGION8_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_END_M  (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S)
-#define HP_APM_REGION8_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_END_S  0
-
-/** HP_APM_REGION8_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c)
-/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION8_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION8_R0_PMS_X_M  (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S)
-#define HP_APM_REGION8_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION8_R0_PMS_X_S  0
-/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION8_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION8_R0_PMS_W_M  (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S)
-#define HP_APM_REGION8_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION8_R0_PMS_W_S  1
-/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION8_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION8_R0_PMS_R_M  (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S)
-#define HP_APM_REGION8_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION8_R0_PMS_R_S  2
-/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION8_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION8_R1_PMS_X_M  (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S)
-#define HP_APM_REGION8_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION8_R1_PMS_X_S  4
-/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION8_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION8_R1_PMS_W_M  (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S)
-#define HP_APM_REGION8_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION8_R1_PMS_W_S  5
-/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION8_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION8_R1_PMS_R_M  (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S)
-#define HP_APM_REGION8_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION8_R1_PMS_R_S  6
-/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION8_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION8_R2_PMS_X_M  (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S)
-#define HP_APM_REGION8_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION8_R2_PMS_X_S  8
-/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION8_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION8_R2_PMS_W_M  (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S)
-#define HP_APM_REGION8_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION8_R2_PMS_W_S  9
-/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION8_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION8_R2_PMS_R_M  (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S)
-#define HP_APM_REGION8_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION8_R2_PMS_R_S  10
-
-/** HP_APM_REGION9_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70)
-/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region9
- */
-#define HP_APM_REGION9_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_START_M  (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S)
-#define HP_APM_REGION9_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_START_S  0
-
-/** HP_APM_REGION9_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74)
-/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region9
- */
-#define HP_APM_REGION9_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_END_M  (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S)
-#define HP_APM_REGION9_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_END_S  0
-
-/** HP_APM_REGION9_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78)
-/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION9_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION9_R0_PMS_X_M  (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S)
-#define HP_APM_REGION9_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION9_R0_PMS_X_S  0
-/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION9_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION9_R0_PMS_W_M  (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S)
-#define HP_APM_REGION9_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION9_R0_PMS_W_S  1
-/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION9_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION9_R0_PMS_R_M  (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S)
-#define HP_APM_REGION9_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION9_R0_PMS_R_S  2
-/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION9_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION9_R1_PMS_X_M  (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S)
-#define HP_APM_REGION9_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION9_R1_PMS_X_S  4
-/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION9_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION9_R1_PMS_W_M  (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S)
-#define HP_APM_REGION9_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION9_R1_PMS_W_S  5
-/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION9_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION9_R1_PMS_R_M  (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S)
-#define HP_APM_REGION9_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION9_R1_PMS_R_S  6
-/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION9_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION9_R2_PMS_X_M  (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S)
-#define HP_APM_REGION9_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION9_R2_PMS_X_S  8
-/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION9_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION9_R2_PMS_W_M  (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S)
-#define HP_APM_REGION9_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION9_R2_PMS_W_S  9
-/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION9_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION9_R2_PMS_R_M  (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S)
-#define HP_APM_REGION9_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION9_R2_PMS_R_S  10
-
-/** HP_APM_REGION10_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c)
-/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region10
- */
-#define HP_APM_REGION10_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_START_M  (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S)
-#define HP_APM_REGION10_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_START_S  0
-
-/** HP_APM_REGION10_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80)
-/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region10
- */
-#define HP_APM_REGION10_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_END_M  (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S)
-#define HP_APM_REGION10_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_END_S  0
-
-/** HP_APM_REGION10_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84)
-/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION10_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION10_R0_PMS_X_M  (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S)
-#define HP_APM_REGION10_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION10_R0_PMS_X_S  0
-/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION10_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION10_R0_PMS_W_M  (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S)
-#define HP_APM_REGION10_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION10_R0_PMS_W_S  1
-/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION10_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION10_R0_PMS_R_M  (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S)
-#define HP_APM_REGION10_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION10_R0_PMS_R_S  2
-/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION10_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION10_R1_PMS_X_M  (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S)
-#define HP_APM_REGION10_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION10_R1_PMS_X_S  4
-/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION10_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION10_R1_PMS_W_M  (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S)
-#define HP_APM_REGION10_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION10_R1_PMS_W_S  5
-/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION10_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION10_R1_PMS_R_M  (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S)
-#define HP_APM_REGION10_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION10_R1_PMS_R_S  6
-/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION10_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION10_R2_PMS_X_M  (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S)
-#define HP_APM_REGION10_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION10_R2_PMS_X_S  8
-/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION10_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION10_R2_PMS_W_M  (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S)
-#define HP_APM_REGION10_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION10_R2_PMS_W_S  9
-/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION10_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION10_R2_PMS_R_M  (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S)
-#define HP_APM_REGION10_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION10_R2_PMS_R_S  10
-
-/** HP_APM_REGION11_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88)
-/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region11
- */
-#define HP_APM_REGION11_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_START_M  (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S)
-#define HP_APM_REGION11_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_START_S  0
-
-/** HP_APM_REGION11_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c)
-/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region11
- */
-#define HP_APM_REGION11_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_END_M  (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S)
-#define HP_APM_REGION11_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_END_S  0
-
-/** HP_APM_REGION11_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90)
-/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION11_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION11_R0_PMS_X_M  (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S)
-#define HP_APM_REGION11_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION11_R0_PMS_X_S  0
-/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION11_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION11_R0_PMS_W_M  (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S)
-#define HP_APM_REGION11_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION11_R0_PMS_W_S  1
-/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION11_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION11_R0_PMS_R_M  (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S)
-#define HP_APM_REGION11_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION11_R0_PMS_R_S  2
-/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION11_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION11_R1_PMS_X_M  (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S)
-#define HP_APM_REGION11_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION11_R1_PMS_X_S  4
-/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION11_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION11_R1_PMS_W_M  (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S)
-#define HP_APM_REGION11_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION11_R1_PMS_W_S  5
-/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION11_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION11_R1_PMS_R_M  (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S)
-#define HP_APM_REGION11_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION11_R1_PMS_R_S  6
-/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION11_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION11_R2_PMS_X_M  (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S)
-#define HP_APM_REGION11_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION11_R2_PMS_X_S  8
-/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION11_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION11_R2_PMS_W_M  (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S)
-#define HP_APM_REGION11_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION11_R2_PMS_W_S  9
-/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION11_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION11_R2_PMS_R_M  (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S)
-#define HP_APM_REGION11_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION11_R2_PMS_R_S  10
-
-/** HP_APM_REGION12_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94)
-/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region12
- */
-#define HP_APM_REGION12_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_START_M  (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S)
-#define HP_APM_REGION12_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_START_S  0
-
-/** HP_APM_REGION12_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98)
-/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region12
- */
-#define HP_APM_REGION12_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_END_M  (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S)
-#define HP_APM_REGION12_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_END_S  0
-
-/** HP_APM_REGION12_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c)
-/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION12_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION12_R0_PMS_X_M  (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S)
-#define HP_APM_REGION12_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION12_R0_PMS_X_S  0
-/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION12_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION12_R0_PMS_W_M  (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S)
-#define HP_APM_REGION12_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION12_R0_PMS_W_S  1
-/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION12_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION12_R0_PMS_R_M  (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S)
-#define HP_APM_REGION12_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION12_R0_PMS_R_S  2
-/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION12_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION12_R1_PMS_X_M  (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S)
-#define HP_APM_REGION12_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION12_R1_PMS_X_S  4
-/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION12_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION12_R1_PMS_W_M  (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S)
-#define HP_APM_REGION12_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION12_R1_PMS_W_S  5
-/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION12_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION12_R1_PMS_R_M  (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S)
-#define HP_APM_REGION12_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION12_R1_PMS_R_S  6
-/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION12_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION12_R2_PMS_X_M  (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S)
-#define HP_APM_REGION12_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION12_R2_PMS_X_S  8
-/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION12_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION12_R2_PMS_W_M  (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S)
-#define HP_APM_REGION12_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION12_R2_PMS_W_S  9
-/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION12_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION12_R2_PMS_R_M  (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S)
-#define HP_APM_REGION12_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION12_R2_PMS_R_S  10
-
-/** HP_APM_REGION13_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0)
-/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region13
- */
-#define HP_APM_REGION13_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_START_M  (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S)
-#define HP_APM_REGION13_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_START_S  0
-
-/** HP_APM_REGION13_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4)
-/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region13
- */
-#define HP_APM_REGION13_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_END_M  (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S)
-#define HP_APM_REGION13_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_END_S  0
-
-/** HP_APM_REGION13_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8)
-/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION13_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION13_R0_PMS_X_M  (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S)
-#define HP_APM_REGION13_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION13_R0_PMS_X_S  0
-/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION13_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION13_R0_PMS_W_M  (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S)
-#define HP_APM_REGION13_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION13_R0_PMS_W_S  1
-/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION13_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION13_R0_PMS_R_M  (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S)
-#define HP_APM_REGION13_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION13_R0_PMS_R_S  2
-/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION13_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION13_R1_PMS_X_M  (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S)
-#define HP_APM_REGION13_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION13_R1_PMS_X_S  4
-/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION13_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION13_R1_PMS_W_M  (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S)
-#define HP_APM_REGION13_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION13_R1_PMS_W_S  5
-/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION13_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION13_R1_PMS_R_M  (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S)
-#define HP_APM_REGION13_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION13_R1_PMS_R_S  6
-/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION13_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION13_R2_PMS_X_M  (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S)
-#define HP_APM_REGION13_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION13_R2_PMS_X_S  8
-/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION13_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION13_R2_PMS_W_M  (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S)
-#define HP_APM_REGION13_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION13_R2_PMS_W_S  9
-/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION13_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION13_R2_PMS_R_M  (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S)
-#define HP_APM_REGION13_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION13_R2_PMS_R_S  10
-
-/** HP_APM_REGION14_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac)
-/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region14
- */
-#define HP_APM_REGION14_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_START_M  (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S)
-#define HP_APM_REGION14_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_START_S  0
-
-/** HP_APM_REGION14_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0)
-/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region14
- */
-#define HP_APM_REGION14_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_END_M  (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S)
-#define HP_APM_REGION14_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_END_S  0
-
-/** HP_APM_REGION14_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4)
-/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION14_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION14_R0_PMS_X_M  (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S)
-#define HP_APM_REGION14_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION14_R0_PMS_X_S  0
-/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION14_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION14_R0_PMS_W_M  (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S)
-#define HP_APM_REGION14_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION14_R0_PMS_W_S  1
-/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION14_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION14_R0_PMS_R_M  (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S)
-#define HP_APM_REGION14_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION14_R0_PMS_R_S  2
-/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION14_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION14_R1_PMS_X_M  (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S)
-#define HP_APM_REGION14_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION14_R1_PMS_X_S  4
-/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION14_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION14_R1_PMS_W_M  (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S)
-#define HP_APM_REGION14_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION14_R1_PMS_W_S  5
-/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION14_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION14_R1_PMS_R_M  (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S)
-#define HP_APM_REGION14_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION14_R1_PMS_R_S  6
-/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION14_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION14_R2_PMS_X_M  (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S)
-#define HP_APM_REGION14_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION14_R2_PMS_X_S  8
-/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION14_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION14_R2_PMS_W_M  (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S)
-#define HP_APM_REGION14_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION14_R2_PMS_W_S  9
-/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION14_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION14_R2_PMS_R_M  (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S)
-#define HP_APM_REGION14_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION14_R2_PMS_R_S  10
-
-/** HP_APM_REGION15_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8)
-/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region15
- */
-#define HP_APM_REGION15_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_START_M  (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S)
-#define HP_APM_REGION15_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_START_S  0
-
-/** HP_APM_REGION15_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc)
-/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region15
- */
-#define HP_APM_REGION15_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_END_M  (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S)
-#define HP_APM_REGION15_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_END_S  0
-
-/** HP_APM_REGION15_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0)
-/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION15_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION15_R0_PMS_X_M  (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S)
-#define HP_APM_REGION15_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION15_R0_PMS_X_S  0
-/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION15_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION15_R0_PMS_W_M  (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S)
-#define HP_APM_REGION15_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION15_R0_PMS_W_S  1
-/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION15_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION15_R0_PMS_R_M  (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S)
-#define HP_APM_REGION15_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION15_R0_PMS_R_S  2
-/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION15_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION15_R1_PMS_X_M  (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S)
-#define HP_APM_REGION15_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION15_R1_PMS_X_S  4
-/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION15_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION15_R1_PMS_W_M  (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S)
-#define HP_APM_REGION15_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION15_R1_PMS_W_S  5
-/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION15_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION15_R1_PMS_R_M  (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S)
-#define HP_APM_REGION15_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION15_R1_PMS_R_S  6
-/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION15_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION15_R2_PMS_X_M  (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S)
-#define HP_APM_REGION15_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION15_R2_PMS_X_S  8
-/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION15_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION15_R2_PMS_W_M  (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S)
-#define HP_APM_REGION15_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION15_R2_PMS_W_S  9
-/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION15_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION15_R2_PMS_R_M  (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S)
-#define HP_APM_REGION15_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION15_R2_PMS_R_S  10
-
-/** HP_APM_FUNC_CTRL_REG register
- *  PMS function control register
- */
-#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4)
-/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
- *  PMS M0 function enable
- */
-#define HP_APM_M0_PMS_FUNC_EN    (BIT(0))
-#define HP_APM_M0_PMS_FUNC_EN_M  (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S)
-#define HP_APM_M0_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M0_PMS_FUNC_EN_S  0
-/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
- *  PMS M1 function enable
- */
-#define HP_APM_M1_PMS_FUNC_EN    (BIT(1))
-#define HP_APM_M1_PMS_FUNC_EN_M  (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S)
-#define HP_APM_M1_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M1_PMS_FUNC_EN_S  1
-/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1;
- *  PMS M2 function enable
- */
-#define HP_APM_M2_PMS_FUNC_EN    (BIT(2))
-#define HP_APM_M2_PMS_FUNC_EN_M  (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S)
-#define HP_APM_M2_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M2_PMS_FUNC_EN_S  2
-/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1;
- *  PMS M3 function enable
- */
-#define HP_APM_M3_PMS_FUNC_EN    (BIT(3))
-#define HP_APM_M3_PMS_FUNC_EN_M  (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S)
-#define HP_APM_M3_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M3_PMS_FUNC_EN_S  3
-
-/** HP_APM_M0_STATUS_REG register
- *  M0 status register
- */
-#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8)
-/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M0_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M0_EXCEPTION_STATUS_M  (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S)
-#define HP_APM_M0_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M0_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M0_STATUS_CLR_REG register
- *  M0 status clear register
- */
-#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc)
-/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M0_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M0_REGION_STATUS_CLR_M  (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S)
-#define HP_APM_M0_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M0_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M0_EXCEPTION_INFO0_REG register
- *  M0 exception_info0 register
- */
-#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0)
-/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M0_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M0_EXCEPTION_REGION_M  (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S)
-#define HP_APM_M0_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M0_EXCEPTION_REGION_S  0
-/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M0_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M0_EXCEPTION_MODE_M  (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S)
-#define HP_APM_M0_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M0_EXCEPTION_MODE_S  16
-/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M0_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M0_EXCEPTION_ID_M  (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S)
-#define HP_APM_M0_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M0_EXCEPTION_ID_S  18
-
-/** HP_APM_M0_EXCEPTION_INFO1_REG register
- *  M0 exception_info1 register
- */
-#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4)
-/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M0_EXCEPTION_ADDR_M  (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S)
-#define HP_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M0_EXCEPTION_ADDR_S  0
-
-/** HP_APM_M1_STATUS_REG register
- *  M1 status register
- */
-#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8)
-/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M1_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M1_EXCEPTION_STATUS_M  (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S)
-#define HP_APM_M1_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M1_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M1_STATUS_CLR_REG register
- *  M1 status clear register
- */
-#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc)
-/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M1_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M1_REGION_STATUS_CLR_M  (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S)
-#define HP_APM_M1_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M1_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M1_EXCEPTION_INFO0_REG register
- *  M1 exception_info0 register
- */
-#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0)
-/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M1_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M1_EXCEPTION_REGION_M  (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S)
-#define HP_APM_M1_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M1_EXCEPTION_REGION_S  0
-/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M1_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M1_EXCEPTION_MODE_M  (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S)
-#define HP_APM_M1_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M1_EXCEPTION_MODE_S  16
-/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M1_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M1_EXCEPTION_ID_M  (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S)
-#define HP_APM_M1_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M1_EXCEPTION_ID_S  18
-
-/** HP_APM_M1_EXCEPTION_INFO1_REG register
- *  M1 exception_info1 register
- */
-#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4)
-/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M1_EXCEPTION_ADDR_M  (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S)
-#define HP_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M1_EXCEPTION_ADDR_S  0
-
-/** HP_APM_M2_STATUS_REG register
- *  M2 status register
- */
-#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8)
-/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M2_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M2_EXCEPTION_STATUS_M  (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S)
-#define HP_APM_M2_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M2_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M2_STATUS_CLR_REG register
- *  M2 status clear register
- */
-#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec)
-/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M2_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M2_REGION_STATUS_CLR_M  (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S)
-#define HP_APM_M2_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M2_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M2_EXCEPTION_INFO0_REG register
- *  M2 exception_info0 register
- */
-#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0)
-/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M2_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M2_EXCEPTION_REGION_M  (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S)
-#define HP_APM_M2_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M2_EXCEPTION_REGION_S  0
-/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M2_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M2_EXCEPTION_MODE_M  (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S)
-#define HP_APM_M2_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M2_EXCEPTION_MODE_S  16
-/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M2_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M2_EXCEPTION_ID_M  (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S)
-#define HP_APM_M2_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M2_EXCEPTION_ID_S  18
-
-/** HP_APM_M2_EXCEPTION_INFO1_REG register
- *  M2 exception_info1 register
- */
-#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4)
-/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M2_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M2_EXCEPTION_ADDR_M  (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S)
-#define HP_APM_M2_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M2_EXCEPTION_ADDR_S  0
-
-/** HP_APM_M3_STATUS_REG register
- *  M3 status register
- */
-#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8)
-/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M3_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M3_EXCEPTION_STATUS_M  (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S)
-#define HP_APM_M3_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M3_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M3_STATUS_CLR_REG register
- *  M3 status clear register
- */
-#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc)
-/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M3_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M3_REGION_STATUS_CLR_M  (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S)
-#define HP_APM_M3_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M3_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M3_EXCEPTION_INFO0_REG register
- *  M3 exception_info0 register
- */
-#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100)
-/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M3_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M3_EXCEPTION_REGION_M  (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S)
-#define HP_APM_M3_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M3_EXCEPTION_REGION_S  0
-/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M3_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M3_EXCEPTION_MODE_M  (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S)
-#define HP_APM_M3_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M3_EXCEPTION_MODE_S  16
-/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M3_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M3_EXCEPTION_ID_M  (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S)
-#define HP_APM_M3_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M3_EXCEPTION_ID_S  18
-
-/** HP_APM_M3_EXCEPTION_INFO1_REG register
- *  M3 exception_info1 register
- */
-#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104)
-/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M3_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M3_EXCEPTION_ADDR_M  (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S)
-#define HP_APM_M3_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M3_EXCEPTION_ADDR_S  0
-
-/** HP_APM_INT_EN_REG register
- *  APM interrupt enable register
- */
-#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108)
-/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
- *  APM M0 interrupt enable
- */
-#define HP_APM_M0_APM_INT_EN    (BIT(0))
-#define HP_APM_M0_APM_INT_EN_M  (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S)
-#define HP_APM_M0_APM_INT_EN_V  0x00000001U
-#define HP_APM_M0_APM_INT_EN_S  0
-/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
- *  APM M1 interrupt enable
- */
-#define HP_APM_M1_APM_INT_EN    (BIT(1))
-#define HP_APM_M1_APM_INT_EN_M  (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S)
-#define HP_APM_M1_APM_INT_EN_V  0x00000001U
-#define HP_APM_M1_APM_INT_EN_S  1
-/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0;
- *  APM M2 interrupt enable
- */
-#define HP_APM_M2_APM_INT_EN    (BIT(2))
-#define HP_APM_M2_APM_INT_EN_M  (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S)
-#define HP_APM_M2_APM_INT_EN_V  0x00000001U
-#define HP_APM_M2_APM_INT_EN_S  2
-/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0;
- *  APM M3 interrupt enable
- */
-#define HP_APM_M3_APM_INT_EN    (BIT(3))
-#define HP_APM_M3_APM_INT_EN_M  (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S)
-#define HP_APM_M3_APM_INT_EN_V  0x00000001U
-#define HP_APM_M3_APM_INT_EN_S  3
-
-/** HP_APM_CLOCK_GATE_REG register
- *  clock gating register
- */
-#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c)
-/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define HP_APM_CLK_EN    (BIT(0))
-#define HP_APM_CLK_EN_M  (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S)
-#define HP_APM_CLK_EN_V  0x00000001U
-#define HP_APM_CLK_EN_S  0
-
-/** HP_APM_DATE_REG register
- *  Version register
- */
-#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc)
-/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
- *  reg_date
- */
-#define HP_APM_DATE    0x0FFFFFFFU
-#define HP_APM_DATE_M  (HP_APM_DATE_V << HP_APM_DATE_S)
-#define HP_APM_DATE_V  0x0FFFFFFFU
-#define HP_APM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hp_apm_struct.h b/components/soc/esp32p4/include/soc/hp_apm_struct.h
deleted file mode 100644
index faec6b3372..0000000000
--- a/components/soc/esp32p4/include/soc/hp_apm_struct.h
+++ /dev/null
@@ -1,1670 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Region filter enable register */
-/** Type of region_filter_en register
- *  Region filter enable register
- */
-typedef union {
-    struct {
-        /** region_filter_en : R/W; bitpos: [15:0]; default: 1;
-         *  Region filter enable
-         */
-        uint32_t region_filter_en:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} hp_apm_region_filter_en_reg_t;
-
-
-/** Group: Region address register */
-/** Type of region0_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region0
-         */
-        uint32_t region0_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region0_addr_start_reg_t;
-
-/** Type of region0_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region0
-         */
-        uint32_t region0_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region0_addr_end_reg_t;
-
-/** Type of region1_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region1
-         */
-        uint32_t region1_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region1_addr_start_reg_t;
-
-/** Type of region1_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region1
-         */
-        uint32_t region1_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region1_addr_end_reg_t;
-
-/** Type of region2_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region2
-         */
-        uint32_t region2_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region2_addr_start_reg_t;
-
-/** Type of region2_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region2
-         */
-        uint32_t region2_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region2_addr_end_reg_t;
-
-/** Type of region3_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region3
-         */
-        uint32_t region3_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region3_addr_start_reg_t;
-
-/** Type of region3_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region3
-         */
-        uint32_t region3_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region3_addr_end_reg_t;
-
-/** Type of region4_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region4_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region4
-         */
-        uint32_t region4_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region4_addr_start_reg_t;
-
-/** Type of region4_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region4
-         */
-        uint32_t region4_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region4_addr_end_reg_t;
-
-/** Type of region5_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region5_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region5
-         */
-        uint32_t region5_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region5_addr_start_reg_t;
-
-/** Type of region5_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region5
-         */
-        uint32_t region5_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region5_addr_end_reg_t;
-
-/** Type of region6_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region6_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region6
-         */
-        uint32_t region6_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region6_addr_start_reg_t;
-
-/** Type of region6_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region6
-         */
-        uint32_t region6_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region6_addr_end_reg_t;
-
-/** Type of region7_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region7_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region7
-         */
-        uint32_t region7_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region7_addr_start_reg_t;
-
-/** Type of region7_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region7
-         */
-        uint32_t region7_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region7_addr_end_reg_t;
-
-/** Type of region8_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region8_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region8
-         */
-        uint32_t region8_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region8_addr_start_reg_t;
-
-/** Type of region8_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region8
-         */
-        uint32_t region8_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region8_addr_end_reg_t;
-
-/** Type of region9_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region9_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region9
-         */
-        uint32_t region9_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region9_addr_start_reg_t;
-
-/** Type of region9_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region9
-         */
-        uint32_t region9_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region9_addr_end_reg_t;
-
-/** Type of region10_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region10_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region10
-         */
-        uint32_t region10_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region10_addr_start_reg_t;
-
-/** Type of region10_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region10
-         */
-        uint32_t region10_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region10_addr_end_reg_t;
-
-/** Type of region11_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region11_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region11
-         */
-        uint32_t region11_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region11_addr_start_reg_t;
-
-/** Type of region11_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region11
-         */
-        uint32_t region11_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region11_addr_end_reg_t;
-
-/** Type of region12_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region12_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region12
-         */
-        uint32_t region12_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region12_addr_start_reg_t;
-
-/** Type of region12_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region12
-         */
-        uint32_t region12_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region12_addr_end_reg_t;
-
-/** Type of region13_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region13_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region13
-         */
-        uint32_t region13_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region13_addr_start_reg_t;
-
-/** Type of region13_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region13
-         */
-        uint32_t region13_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region13_addr_end_reg_t;
-
-/** Type of region14_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region14_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region14
-         */
-        uint32_t region14_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region14_addr_start_reg_t;
-
-/** Type of region14_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region14
-         */
-        uint32_t region14_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region14_addr_end_reg_t;
-
-/** Type of region15_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region15_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region15
-         */
-        uint32_t region15_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region15_addr_start_reg_t;
-
-/** Type of region15_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region15
-         */
-        uint32_t region15_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region15_addr_end_reg_t;
-
-
-/** Group: Region access authority attribute register */
-/** Type of region0_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_x:1;
-        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_w:1;
-        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_x:1;
-        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_w:1;
-        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_x:1;
-        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_w:1;
-        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region0_pms_attr_reg_t;
-
-/** Type of region1_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_x:1;
-        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_w:1;
-        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_x:1;
-        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_w:1;
-        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_x:1;
-        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_w:1;
-        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region1_pms_attr_reg_t;
-
-/** Type of region2_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_x:1;
-        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_w:1;
-        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_x:1;
-        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_w:1;
-        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_x:1;
-        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_w:1;
-        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region2_pms_attr_reg_t;
-
-/** Type of region3_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_x:1;
-        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_w:1;
-        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_x:1;
-        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_w:1;
-        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_x:1;
-        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_w:1;
-        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region3_pms_attr_reg_t;
-
-/** Type of region4_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region4_r0_pms_x:1;
-        /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region4_r0_pms_w:1;
-        /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region4_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region4_r1_pms_x:1;
-        /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region4_r1_pms_w:1;
-        /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region4_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region4_r2_pms_x:1;
-        /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region4_r2_pms_w:1;
-        /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region4_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region4_pms_attr_reg_t;
-
-/** Type of region5_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region5_r0_pms_x:1;
-        /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region5_r0_pms_w:1;
-        /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region5_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region5_r1_pms_x:1;
-        /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region5_r1_pms_w:1;
-        /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region5_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region5_r2_pms_x:1;
-        /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region5_r2_pms_w:1;
-        /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region5_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region5_pms_attr_reg_t;
-
-/** Type of region6_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region6_r0_pms_x:1;
-        /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region6_r0_pms_w:1;
-        /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region6_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region6_r1_pms_x:1;
-        /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region6_r1_pms_w:1;
-        /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region6_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region6_r2_pms_x:1;
-        /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region6_r2_pms_w:1;
-        /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region6_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region6_pms_attr_reg_t;
-
-/** Type of region7_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region7_r0_pms_x:1;
-        /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region7_r0_pms_w:1;
-        /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region7_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region7_r1_pms_x:1;
-        /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region7_r1_pms_w:1;
-        /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region7_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region7_r2_pms_x:1;
-        /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region7_r2_pms_w:1;
-        /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region7_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region7_pms_attr_reg_t;
-
-/** Type of region8_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region8_r0_pms_x:1;
-        /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region8_r0_pms_w:1;
-        /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region8_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region8_r1_pms_x:1;
-        /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region8_r1_pms_w:1;
-        /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region8_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region8_r2_pms_x:1;
-        /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region8_r2_pms_w:1;
-        /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region8_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region8_pms_attr_reg_t;
-
-/** Type of region9_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region9_r0_pms_x:1;
-        /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region9_r0_pms_w:1;
-        /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region9_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region9_r1_pms_x:1;
-        /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region9_r1_pms_w:1;
-        /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region9_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region9_r2_pms_x:1;
-        /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region9_r2_pms_w:1;
-        /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region9_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region9_pms_attr_reg_t;
-
-/** Type of region10_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region10_r0_pms_x:1;
-        /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region10_r0_pms_w:1;
-        /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region10_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region10_r1_pms_x:1;
-        /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region10_r1_pms_w:1;
-        /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region10_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region10_r2_pms_x:1;
-        /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region10_r2_pms_w:1;
-        /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region10_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region10_pms_attr_reg_t;
-
-/** Type of region11_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region11_r0_pms_x:1;
-        /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region11_r0_pms_w:1;
-        /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region11_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region11_r1_pms_x:1;
-        /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region11_r1_pms_w:1;
-        /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region11_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region11_r2_pms_x:1;
-        /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region11_r2_pms_w:1;
-        /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region11_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region11_pms_attr_reg_t;
-
-/** Type of region12_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region12_r0_pms_x:1;
-        /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region12_r0_pms_w:1;
-        /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region12_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region12_r1_pms_x:1;
-        /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region12_r1_pms_w:1;
-        /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region12_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region12_r2_pms_x:1;
-        /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region12_r2_pms_w:1;
-        /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region12_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region12_pms_attr_reg_t;
-
-/** Type of region13_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region13_r0_pms_x:1;
-        /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region13_r0_pms_w:1;
-        /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region13_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region13_r1_pms_x:1;
-        /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region13_r1_pms_w:1;
-        /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region13_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region13_r2_pms_x:1;
-        /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region13_r2_pms_w:1;
-        /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region13_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region13_pms_attr_reg_t;
-
-/** Type of region14_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region14_r0_pms_x:1;
-        /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region14_r0_pms_w:1;
-        /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region14_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region14_r1_pms_x:1;
-        /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region14_r1_pms_w:1;
-        /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region14_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region14_r2_pms_x:1;
-        /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region14_r2_pms_w:1;
-        /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region14_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region14_pms_attr_reg_t;
-
-/** Type of region15_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region15_r0_pms_x:1;
-        /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region15_r0_pms_w:1;
-        /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region15_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region15_r1_pms_x:1;
-        /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region15_r1_pms_w:1;
-        /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region15_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region15_r2_pms_x:1;
-        /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region15_r2_pms_w:1;
-        /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region15_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} hp_apm_region15_pms_attr_reg_t;
-
-
-/** Group: PMS function control register */
-/** Type of func_ctrl register
- *  PMS function control register
- */
-typedef union {
-    struct {
-        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
-         *  PMS M0 function enable
-         */
-        uint32_t m0_pms_func_en:1;
-        /** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
-         *  PMS M1 function enable
-         */
-        uint32_t m1_pms_func_en:1;
-        /** m2_pms_func_en : R/W; bitpos: [2]; default: 1;
-         *  PMS M2 function enable
-         */
-        uint32_t m2_pms_func_en:1;
-        /** m3_pms_func_en : R/W; bitpos: [3]; default: 1;
-         *  PMS M3 function enable
-         */
-        uint32_t m3_pms_func_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_apm_func_ctrl_reg_t;
-
-
-/** Group: M0 status register */
-/** Type of m0_status register
- *  M0 status register
- */
-typedef union {
-    struct {
-        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m0_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m0_status_reg_t;
-
-
-/** Group: M0 status clear register */
-/** Type of m0_status_clr register
- *  M0 status clear register
- */
-typedef union {
-    struct {
-        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m0_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m0_status_clr_reg_t;
-
-
-/** Group: M0 exception_info0 register */
-/** Type of m0_exception_info0 register
- *  M0 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m0_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m0_exception_region:16;
-        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m0_exception_mode:2;
-        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m0_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m0_exception_info0_reg_t;
-
-
-/** Group: M0 exception_info1 register */
-/** Type of m0_exception_info1 register
- *  M0 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m0_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m0_exception_info1_reg_t;
-
-
-/** Group: M1 status register */
-/** Type of m1_status register
- *  M1 status register
- */
-typedef union {
-    struct {
-        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m1_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m1_status_reg_t;
-
-
-/** Group: M1 status clear register */
-/** Type of m1_status_clr register
- *  M1 status clear register
- */
-typedef union {
-    struct {
-        /** m1_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m1_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m1_status_clr_reg_t;
-
-
-/** Group: M1 exception_info0 register */
-/** Type of m1_exception_info0 register
- *  M1 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m1_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m1_exception_region:16;
-        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m1_exception_mode:2;
-        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m1_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m1_exception_info0_reg_t;
-
-
-/** Group: M1 exception_info1 register */
-/** Type of m1_exception_info1 register
- *  M1 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m1_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m1_exception_info1_reg_t;
-
-
-/** Group: M2 status register */
-/** Type of m2_status register
- *  M2 status register
- */
-typedef union {
-    struct {
-        /** m2_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m2_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m2_status_reg_t;
-
-
-/** Group: M2 status clear register */
-/** Type of m2_status_clr register
- *  M2 status clear register
- */
-typedef union {
-    struct {
-        /** m2_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m2_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m2_status_clr_reg_t;
-
-
-/** Group: M2 exception_info0 register */
-/** Type of m2_exception_info0 register
- *  M2 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m2_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m2_exception_region:16;
-        /** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m2_exception_mode:2;
-        /** m2_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m2_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m2_exception_info0_reg_t;
-
-
-/** Group: M2 exception_info1 register */
-/** Type of m2_exception_info1 register
- *  M2 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m2_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m2_exception_info1_reg_t;
-
-
-/** Group: M3 status register */
-/** Type of m3_status register
- *  M3 status register
- */
-typedef union {
-    struct {
-        /** m3_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m3_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m3_status_reg_t;
-
-
-/** Group: M3 status clear register */
-/** Type of m3_status_clr register
- *  M3 status clear register
- */
-typedef union {
-    struct {
-        /** m3_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m3_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m3_status_clr_reg_t;
-
-
-/** Group: M3 exception_info0 register */
-/** Type of m3_exception_info0 register
- *  M3 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m3_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m3_exception_region:16;
-        /** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m3_exception_mode:2;
-        /** m3_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m3_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m3_exception_info0_reg_t;
-
-
-/** Group: M3 exception_info1 register */
-/** Type of m3_exception_info1 register
- *  M3 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m3_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m3_exception_info1_reg_t;
-
-
-/** Group: APM interrupt enable register */
-/** Type of int_en register
- *  APM interrupt enable register
- */
-typedef union {
-    struct {
-        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
-         *  APM M0 interrupt enable
-         */
-        uint32_t m0_apm_int_en:1;
-        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
-         *  APM M1 interrupt enable
-         */
-        uint32_t m1_apm_int_en:1;
-        /** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
-         *  APM M2 interrupt enable
-         */
-        uint32_t m2_apm_int_en:1;
-        /** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
-         *  APM M3 interrupt enable
-         */
-        uint32_t m3_apm_int_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_apm_int_en_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35672640;
-         *  reg_date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} hp_apm_date_reg_t;
-
-
-typedef struct hp_apm_dev_t {
-    volatile hp_apm_region_filter_en_reg_t region_filter_en;
-    volatile hp_apm_region0_addr_start_reg_t region0_addr_start;
-    volatile hp_apm_region0_addr_end_reg_t region0_addr_end;
-    volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr;
-    volatile hp_apm_region1_addr_start_reg_t region1_addr_start;
-    volatile hp_apm_region1_addr_end_reg_t region1_addr_end;
-    volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr;
-    volatile hp_apm_region2_addr_start_reg_t region2_addr_start;
-    volatile hp_apm_region2_addr_end_reg_t region2_addr_end;
-    volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr;
-    volatile hp_apm_region3_addr_start_reg_t region3_addr_start;
-    volatile hp_apm_region3_addr_end_reg_t region3_addr_end;
-    volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr;
-    volatile hp_apm_region4_addr_start_reg_t region4_addr_start;
-    volatile hp_apm_region4_addr_end_reg_t region4_addr_end;
-    volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr;
-    volatile hp_apm_region5_addr_start_reg_t region5_addr_start;
-    volatile hp_apm_region5_addr_end_reg_t region5_addr_end;
-    volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr;
-    volatile hp_apm_region6_addr_start_reg_t region6_addr_start;
-    volatile hp_apm_region6_addr_end_reg_t region6_addr_end;
-    volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr;
-    volatile hp_apm_region7_addr_start_reg_t region7_addr_start;
-    volatile hp_apm_region7_addr_end_reg_t region7_addr_end;
-    volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr;
-    volatile hp_apm_region8_addr_start_reg_t region8_addr_start;
-    volatile hp_apm_region8_addr_end_reg_t region8_addr_end;
-    volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr;
-    volatile hp_apm_region9_addr_start_reg_t region9_addr_start;
-    volatile hp_apm_region9_addr_end_reg_t region9_addr_end;
-    volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr;
-    volatile hp_apm_region10_addr_start_reg_t region10_addr_start;
-    volatile hp_apm_region10_addr_end_reg_t region10_addr_end;
-    volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr;
-    volatile hp_apm_region11_addr_start_reg_t region11_addr_start;
-    volatile hp_apm_region11_addr_end_reg_t region11_addr_end;
-    volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr;
-    volatile hp_apm_region12_addr_start_reg_t region12_addr_start;
-    volatile hp_apm_region12_addr_end_reg_t region12_addr_end;
-    volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr;
-    volatile hp_apm_region13_addr_start_reg_t region13_addr_start;
-    volatile hp_apm_region13_addr_end_reg_t region13_addr_end;
-    volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr;
-    volatile hp_apm_region14_addr_start_reg_t region14_addr_start;
-    volatile hp_apm_region14_addr_end_reg_t region14_addr_end;
-    volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr;
-    volatile hp_apm_region15_addr_start_reg_t region15_addr_start;
-    volatile hp_apm_region15_addr_end_reg_t region15_addr_end;
-    volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr;
-    volatile hp_apm_func_ctrl_reg_t func_ctrl;
-    volatile hp_apm_m0_status_reg_t m0_status;
-    volatile hp_apm_m0_status_clr_reg_t m0_status_clr;
-    volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0;
-    volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1;
-    volatile hp_apm_m1_status_reg_t m1_status;
-    volatile hp_apm_m1_status_clr_reg_t m1_status_clr;
-    volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0;
-    volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1;
-    volatile hp_apm_m2_status_reg_t m2_status;
-    volatile hp_apm_m2_status_clr_reg_t m2_status_clr;
-    volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0;
-    volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1;
-    volatile hp_apm_m3_status_reg_t m3_status;
-    volatile hp_apm_m3_status_clr_reg_t m3_status_clr;
-    volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0;
-    volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1;
-    volatile hp_apm_int_en_reg_t int_en;
-    volatile hp_apm_clock_gate_reg_t clock_gate;
-    uint32_t reserved_110[443];
-    volatile hp_apm_date_reg_t date;
-} hp_apm_dev_t;
-
-extern hp_apm_dev_t HP_APM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hp_clkrst_reg.h b/components/soc/esp32p4/include/soc/hp_clkrst_reg.h
deleted file mode 100644
index 661563894f..0000000000
--- a/components/soc/esp32p4/include/soc/hp_clkrst_reg.h
+++ /dev/null
@@ -1,629 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_HP_CLKRST_REG_H_
-#define _SOC_HP_CLKRST_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define HP_CLKRST_VER_DATE_REG          (DR_REG_HP_CLKRST_BASE + 0x0)
-/* HP_CLKRST_VER_DATE : R/W ;bitpos:[31:0] ;default: 32'h20201229 ; */
-/*description: .*/
-#define HP_CLKRST_VER_DATE    0xFFFFFFFF
-#define HP_CLKRST_VER_DATE_M  ((HP_CLKRST_VER_DATE_V)<<(HP_CLKRST_VER_DATE_S))
-#define HP_CLKRST_VER_DATE_V  0xFFFFFFFF
-#define HP_CLKRST_VER_DATE_S  0
-
-#define HP_CLKRST_HP_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x4)
-/* HP_CLKRST_HP_CPU_ROOT_CLK_SEL : R/W ;bitpos:[3:2] ;default: 2'h1 ; */
-/*description: Hp cpu root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP CPU
-PLL clock; 2'h3: HP system PLL clock.*/
-#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL    0x00000003
-#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_M  ((HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S))
-#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V  0x3
-#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S  2
-/* HP_CLKRST_HP_SYS_ROOT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */
-/*description: Hp system root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP s
-ystem PLL clock; 2'h3: HP CPU PLL clock.*/
-#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL    0x00000003
-#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_M  ((HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S))
-#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V  0x3
-#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S  0
-
-#define HP_CLKRST_CPU_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x8)
-/* HP_CLKRST_CPU_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM    0x000000FF
-#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S))
-#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V  0xFF
-#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S  24
-/* HP_CLKRST_CPU_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define HP_CLKRST_CPU_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_CPU_CLK_DIV_NUM_M  ((HP_CLKRST_CPU_CLK_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_DIV_NUM_S))
-#define HP_CLKRST_CPU_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_CPU_CLK_DIV_NUM_S  8
-/* HP_CLKRST_CPU_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define HP_CLKRST_CPU_CLK_EN    (BIT(0))
-#define HP_CLKRST_CPU_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_CPU_CLK_EN_V  0x1
-#define HP_CLKRST_CPU_CLK_EN_S  0
-
-#define HP_CLKRST_SYS_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0xC)
-/* HP_CLKRST_SYS_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM    0x000000FF
-#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S))
-#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V  0xFF
-#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S  24
-/* HP_CLKRST_SYS_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: phase offset compare to clock sync signal.*/
-#define HP_CLKRST_SYS_CLK_PHASE_OFFSET    0x000000FF
-#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_M  ((HP_CLKRST_SYS_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_SYS_CLK_PHASE_OFFSET_S))
-#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_V  0xFF
-#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_S  16
-/* HP_CLKRST_SYS_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define HP_CLKRST_SYS_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_SYS_CLK_DIV_NUM_M  ((HP_CLKRST_SYS_CLK_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_DIV_NUM_S))
-#define HP_CLKRST_SYS_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_SYS_CLK_DIV_NUM_S  8
-/* HP_CLKRST_SYS_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN    (BIT(2))
-#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_V  0x1
-#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_S  2
-/* HP_CLKRST_SYS_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define HP_CLKRST_SYS_CLK_SYNC_EN    (BIT(1))
-#define HP_CLKRST_SYS_CLK_SYNC_EN_M  (BIT(1))
-#define HP_CLKRST_SYS_CLK_SYNC_EN_V  0x1
-#define HP_CLKRST_SYS_CLK_SYNC_EN_S  1
-/* HP_CLKRST_SYS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define HP_CLKRST_SYS_CLK_EN    (BIT(0))
-#define HP_CLKRST_SYS_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_SYS_CLK_EN_V  0x1
-#define HP_CLKRST_SYS_CLK_EN_S  0
-
-#define HP_CLKRST_PERI1_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x10)
-/* HP_CLKRST_PERI1_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM    0x000000FF
-#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S))
-#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V  0xFF
-#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S  24
-/* HP_CLKRST_PERI1_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: phase offset compare to clock sync signal.*/
-#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET    0x000000FF
-#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_M  ((HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S))
-#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V  0xFF
-#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S  16
-/* HP_CLKRST_PERI1_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define HP_CLKRST_PERI1_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_PERI1_CLK_DIV_NUM_M  ((HP_CLKRST_PERI1_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_DIV_NUM_S))
-#define HP_CLKRST_PERI1_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_PERI1_CLK_DIV_NUM_S  8
-/* HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN    (BIT(2))
-#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_V  0x1
-#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_S  2
-/* HP_CLKRST_PERI1_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define HP_CLKRST_PERI1_CLK_SYNC_EN    (BIT(1))
-#define HP_CLKRST_PERI1_CLK_SYNC_EN_M  (BIT(1))
-#define HP_CLKRST_PERI1_CLK_SYNC_EN_V  0x1
-#define HP_CLKRST_PERI1_CLK_SYNC_EN_S  1
-/* HP_CLKRST_PERI1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define HP_CLKRST_PERI1_CLK_EN    (BIT(0))
-#define HP_CLKRST_PERI1_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_PERI1_CLK_EN_V  0x1
-#define HP_CLKRST_PERI1_CLK_EN_S  0
-
-#define HP_CLKRST_PERI2_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x14)
-/* HP_CLKRST_PERI2_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM    0x000000FF
-#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S))
-#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V  0xFF
-#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S  24
-/* HP_CLKRST_PERI2_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: phase offset compare to clock sync signal.*/
-#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET    0x000000FF
-#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_M  ((HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S))
-#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V  0xFF
-#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S  16
-/* HP_CLKRST_PERI2_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define HP_CLKRST_PERI2_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_PERI2_CLK_DIV_NUM_M  ((HP_CLKRST_PERI2_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_DIV_NUM_S))
-#define HP_CLKRST_PERI2_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_PERI2_CLK_DIV_NUM_S  8
-/* HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN    (BIT(2))
-#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_V  0x1
-#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_S  2
-/* HP_CLKRST_PERI2_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define HP_CLKRST_PERI2_CLK_SYNC_EN    (BIT(1))
-#define HP_CLKRST_PERI2_CLK_SYNC_EN_M  (BIT(1))
-#define HP_CLKRST_PERI2_CLK_SYNC_EN_V  0x1
-#define HP_CLKRST_PERI2_CLK_SYNC_EN_S  1
-/* HP_CLKRST_PERI2_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define HP_CLKRST_PERI2_CLK_EN    (BIT(0))
-#define HP_CLKRST_PERI2_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_PERI2_CLK_EN_V  0x1
-#define HP_CLKRST_PERI2_CLK_EN_S  0
-
-#define HP_CLKRST_PSRAM_PHY_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x18)
-/* HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM    0x000000FF
-#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S))
-#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V  0xFF
-#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S  24
-/* HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: .*/
-#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_M  ((HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S))
-#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S  8
-/* HP_CLKRST_PSRAM_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */
-/*description: .*/
-#define HP_CLKRST_PSRAM_PHY_CLK_SEL    0x00000003
-#define HP_CLKRST_PSRAM_PHY_CLK_SEL_M  ((HP_CLKRST_PSRAM_PHY_CLK_SEL_V)<<(HP_CLKRST_PSRAM_PHY_CLK_SEL_S))
-#define HP_CLKRST_PSRAM_PHY_CLK_SEL_V  0x3
-#define HP_CLKRST_PSRAM_PHY_CLK_SEL_S  1
-/* HP_CLKRST_PSRAM_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define HP_CLKRST_PSRAM_PHY_CLK_EN    (BIT(0))
-#define HP_CLKRST_PSRAM_PHY_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_PSRAM_PHY_CLK_EN_V  0x1
-#define HP_CLKRST_PSRAM_PHY_CLK_EN_S  0
-
-#define HP_CLKRST_DDR_PHY_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x1C)
-/* HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM    0x000000FF
-#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_M  ((HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S))
-#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V  0xFF
-#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S  24
-/* HP_CLKRST_DDR_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: .*/
-#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_M  ((HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S))
-#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S  8
-/* HP_CLKRST_DDR_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */
-/*description: .*/
-#define HP_CLKRST_DDR_PHY_CLK_SEL    0x00000003
-#define HP_CLKRST_DDR_PHY_CLK_SEL_M  ((HP_CLKRST_DDR_PHY_CLK_SEL_V)<<(HP_CLKRST_DDR_PHY_CLK_SEL_S))
-#define HP_CLKRST_DDR_PHY_CLK_SEL_V  0x3
-#define HP_CLKRST_DDR_PHY_CLK_SEL_S  1
-/* HP_CLKRST_DDR_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define HP_CLKRST_DDR_PHY_CLK_EN    (BIT(0))
-#define HP_CLKRST_DDR_PHY_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_DDR_PHY_CLK_EN_V  0x1
-#define HP_CLKRST_DDR_PHY_CLK_EN_S  0
-
-#define HP_CLKRST_MSPI_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x20)
-/* HP_CLKRST_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */
-/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/
-#define HP_CLKRST_MSPI_SRC_CLK_SEL    0x00000003
-#define HP_CLKRST_MSPI_SRC_CLK_SEL_M  ((HP_CLKRST_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_MSPI_SRC_CLK_SEL_S))
-#define HP_CLKRST_MSPI_SRC_CLK_SEL_V  0x3
-#define HP_CLKRST_MSPI_SRC_CLK_SEL_S  16
-/* HP_CLKRST_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */
-/*description: clock divider number.*/
-#define HP_CLKRST_MSPI_CLK_DIV_NUM    0x0000000F
-#define HP_CLKRST_MSPI_CLK_DIV_NUM_M  ((HP_CLKRST_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_MSPI_CLK_DIV_NUM_S))
-#define HP_CLKRST_MSPI_CLK_DIV_NUM_V  0xF
-#define HP_CLKRST_MSPI_CLK_DIV_NUM_S  8
-/* HP_CLKRST_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define HP_CLKRST_MSPI_CLK_EN    (BIT(0))
-#define HP_CLKRST_MSPI_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_MSPI_CLK_EN_V  0x1
-#define HP_CLKRST_MSPI_CLK_EN_S  0
-
-#define HP_CLKRST_DUAL_MSPI_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x24)
-/* HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */
-/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/
-#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL    0x00000003
-#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_M  ((HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S))
-#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V  0x3
-#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S  16
-/* HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */
-/*description: clock divider number.*/
-#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM    0x0000000F
-#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_M  ((HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S))
-#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V  0xF
-#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S  8
-/* HP_CLKRST_DUAL_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define HP_CLKRST_DUAL_MSPI_CLK_EN    (BIT(0))
-#define HP_CLKRST_DUAL_MSPI_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_DUAL_MSPI_CLK_EN_V  0x1
-#define HP_CLKRST_DUAL_MSPI_CLK_EN_S  0
-
-#define HP_CLKRST_REF_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x28)
-/* HP_CLKRST_REF_CLK2_DIV_NUM : R/W ;bitpos:[27:24] ;default: 4'h3 ; */
-/*description: 120MHz reference clock divider number, used by i3c master.*/
-#define HP_CLKRST_REF_CLK2_DIV_NUM    0x0000000F
-#define HP_CLKRST_REF_CLK2_DIV_NUM_M  ((HP_CLKRST_REF_CLK2_DIV_NUM_V)<<(HP_CLKRST_REF_CLK2_DIV_NUM_S))
-#define HP_CLKRST_REF_CLK2_DIV_NUM_V  0xF
-#define HP_CLKRST_REF_CLK2_DIV_NUM_S  24
-/* HP_CLKRST_USBPHY_CLK_DIV_NUM : R/W ;bitpos:[23:20] ;default: 4'h9 ; */
-/*description: usbphy clock divider number.*/
-#define HP_CLKRST_USBPHY_CLK_DIV_NUM    0x0000000F
-#define HP_CLKRST_USBPHY_CLK_DIV_NUM_M  ((HP_CLKRST_USBPHY_CLK_DIV_NUM_V)<<(HP_CLKRST_USBPHY_CLK_DIV_NUM_S))
-#define HP_CLKRST_USBPHY_CLK_DIV_NUM_V  0xF
-#define HP_CLKRST_USBPHY_CLK_DIV_NUM_S  20
-/* HP_CLKRST_LEDC_REF_CLK_DIV_NUM : R/W ;bitpos:[19:16] ;default: 4'h1 ; */
-/*description: ledc reference clock divider number.*/
-#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM    0x0000000F
-#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_M  ((HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S))
-#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V  0xF
-#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S  16
-/* HP_CLKRST_USB2_REF_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h27 ; */
-/*description: usb2 phy reference clock divider number.*/
-#define HP_CLKRST_USB2_REF_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_M  ((HP_CLKRST_USB2_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_USB2_REF_CLK_DIV_NUM_S))
-#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_S  8
-/* HP_CLKRST_REF_CLK_DIV_NUM : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
-/*description: reference clock divider number.*/
-#define HP_CLKRST_REF_CLK_DIV_NUM    0x0000000F
-#define HP_CLKRST_REF_CLK_DIV_NUM_M  ((HP_CLKRST_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_REF_CLK_DIV_NUM_S))
-#define HP_CLKRST_REF_CLK_DIV_NUM_V  0xF
-#define HP_CLKRST_REF_CLK_DIV_NUM_S  1
-/* HP_CLKRST_REF_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: reference clock output enable.*/
-#define HP_CLKRST_REF_CLK_EN    (BIT(0))
-#define HP_CLKRST_REF_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_REF_CLK_EN_V  0x1
-#define HP_CLKRST_REF_CLK_EN_S  0
-
-#define HP_CLKRST_TM_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x2C)
-/* HP_CLKRST_TM_240M_CLK_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: 240M test mode clock enable.*/
-#define HP_CLKRST_TM_240M_CLK_EN    (BIT(7))
-#define HP_CLKRST_TM_240M_CLK_EN_M  (BIT(7))
-#define HP_CLKRST_TM_240M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_240M_CLK_EN_S  7
-/* HP_CLKRST_TM_200M_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: 200M test mode clock enable.*/
-#define HP_CLKRST_TM_200M_CLK_EN    (BIT(6))
-#define HP_CLKRST_TM_200M_CLK_EN_M  (BIT(6))
-#define HP_CLKRST_TM_200M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_200M_CLK_EN_S  6
-/* HP_CLKRST_TM_160M_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: 160M test mode clock enable.*/
-#define HP_CLKRST_TM_160M_CLK_EN    (BIT(5))
-#define HP_CLKRST_TM_160M_CLK_EN_M  (BIT(5))
-#define HP_CLKRST_TM_160M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_160M_CLK_EN_S  5
-/* HP_CLKRST_TM_120M_CLK_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: 120M test mode clock enable.*/
-#define HP_CLKRST_TM_120M_CLK_EN    (BIT(4))
-#define HP_CLKRST_TM_120M_CLK_EN_M  (BIT(4))
-#define HP_CLKRST_TM_120M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_120M_CLK_EN_S  4
-/* HP_CLKRST_TM_80M_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: 80M test mode clock enable.*/
-#define HP_CLKRST_TM_80M_CLK_EN    (BIT(3))
-#define HP_CLKRST_TM_80M_CLK_EN_M  (BIT(3))
-#define HP_CLKRST_TM_80M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_80M_CLK_EN_S  3
-/* HP_CLKRST_TM_48M_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: 48M test mode clock enable.*/
-#define HP_CLKRST_TM_48M_CLK_EN    (BIT(2))
-#define HP_CLKRST_TM_48M_CLK_EN_M  (BIT(2))
-#define HP_CLKRST_TM_48M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_48M_CLK_EN_S  2
-/* HP_CLKRST_TM_40M_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: 40M test mode clock enable.*/
-#define HP_CLKRST_TM_40M_CLK_EN    (BIT(1))
-#define HP_CLKRST_TM_40M_CLK_EN_M  (BIT(1))
-#define HP_CLKRST_TM_40M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_40M_CLK_EN_S  1
-/* HP_CLKRST_TM_20M_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: 20M test mode clock enabl.*/
-#define HP_CLKRST_TM_20M_CLK_EN    (BIT(0))
-#define HP_CLKRST_TM_20M_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_TM_20M_CLK_EN_V  0x1
-#define HP_CLKRST_TM_20M_CLK_EN_S  0
-
-#define HP_CLKRST_CORE_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x30)
-/* HP_CLKRST_CORE0_GLOBAL_RSTN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: core0 software global reset.*/
-#define HP_CLKRST_CORE0_GLOBAL_RSTN    (BIT(9))
-#define HP_CLKRST_CORE0_GLOBAL_RSTN_M  (BIT(9))
-#define HP_CLKRST_CORE0_GLOBAL_RSTN_V  0x1
-#define HP_CLKRST_CORE0_GLOBAL_RSTN_S  9
-/* HP_CLKRST_CORE1_GLOBAL_RSTN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: core1 software global reset.*/
-#define HP_CLKRST_CORE1_GLOBAL_RSTN    (BIT(8))
-#define HP_CLKRST_CORE1_GLOBAL_RSTN_M  (BIT(8))
-#define HP_CLKRST_CORE1_GLOBAL_RSTN_V  0x1
-#define HP_CLKRST_CORE1_GLOBAL_RSTN_S  8
-/* HP_CLKRST_CORE0_FORCE_NORST : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define HP_CLKRST_CORE0_FORCE_NORST    (BIT(7))
-#define HP_CLKRST_CORE0_FORCE_NORST_M  (BIT(7))
-#define HP_CLKRST_CORE0_FORCE_NORST_V  0x1
-#define HP_CLKRST_CORE0_FORCE_NORST_S  7
-/* HP_CLKRST_CORE1_FORCE_NORST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define HP_CLKRST_CORE1_FORCE_NORST    (BIT(6))
-#define HP_CLKRST_CORE1_FORCE_NORST_M  (BIT(6))
-#define HP_CLKRST_CORE1_FORCE_NORST_V  0x1
-#define HP_CLKRST_CORE1_FORCE_NORST_S  6
-/* HP_CLKRST_CORE2_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define HP_CLKRST_CORE2_FORCE_NORST    (BIT(5))
-#define HP_CLKRST_CORE2_FORCE_NORST_M  (BIT(5))
-#define HP_CLKRST_CORE2_FORCE_NORST_V  0x1
-#define HP_CLKRST_CORE2_FORCE_NORST_S  5
-/* HP_CLKRST_CORE3_FORCE_NORST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define HP_CLKRST_CORE3_FORCE_NORST    (BIT(4))
-#define HP_CLKRST_CORE3_FORCE_NORST_M  (BIT(4))
-#define HP_CLKRST_CORE3_FORCE_NORST_V  0x1
-#define HP_CLKRST_CORE3_FORCE_NORST_S  4
-/* HP_CLKRST_CORE0_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: hp core0 clock enable.*/
-#define HP_CLKRST_CORE0_CLK_EN    (BIT(3))
-#define HP_CLKRST_CORE0_CLK_EN_M  (BIT(3))
-#define HP_CLKRST_CORE0_CLK_EN_V  0x1
-#define HP_CLKRST_CORE0_CLK_EN_S  3
-/* HP_CLKRST_CORE1_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: hp core1 clock enable.*/
-#define HP_CLKRST_CORE1_CLK_EN    (BIT(2))
-#define HP_CLKRST_CORE1_CLK_EN_M  (BIT(2))
-#define HP_CLKRST_CORE1_CLK_EN_V  0x1
-#define HP_CLKRST_CORE1_CLK_EN_S  2
-/* HP_CLKRST_CORE2_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: hp core2 clock enable.*/
-#define HP_CLKRST_CORE2_CLK_EN    (BIT(1))
-#define HP_CLKRST_CORE2_CLK_EN_M  (BIT(1))
-#define HP_CLKRST_CORE2_CLK_EN_V  0x1
-#define HP_CLKRST_CORE2_CLK_EN_S  1
-/* HP_CLKRST_CORE3_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: hp core3 clock enable.*/
-#define HP_CLKRST_CORE3_CLK_EN    (BIT(0))
-#define HP_CLKRST_CORE3_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_CORE3_CLK_EN_V  0x1
-#define HP_CLKRST_CORE3_CLK_EN_S  0
-
-#define HP_CLKRST_CACHE_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x34)
-/* HP_CLKRST_CACHE_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: L2 cache clock divider number.*/
-#define HP_CLKRST_CACHE_CLK_DIV_NUM    0x000000FF
-#define HP_CLKRST_CACHE_CLK_DIV_NUM_M  ((HP_CLKRST_CACHE_CLK_DIV_NUM_V)<<(HP_CLKRST_CACHE_CLK_DIV_NUM_S))
-#define HP_CLKRST_CACHE_CLK_DIV_NUM_V  0xFF
-#define HP_CLKRST_CACHE_CLK_DIV_NUM_S  8
-/* HP_CLKRST_HP_CACHE_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: cache software reset: low active.*/
-#define HP_CLKRST_HP_CACHE_RSTN    (BIT(2))
-#define HP_CLKRST_HP_CACHE_RSTN_M  (BIT(2))
-#define HP_CLKRST_HP_CACHE_RSTN_V  0x1
-#define HP_CLKRST_HP_CACHE_RSTN_S  2
-/* HP_CLKRST_CACHE_APB_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: cache apb clock enable.*/
-#define HP_CLKRST_CACHE_APB_CLK_EN    (BIT(1))
-#define HP_CLKRST_CACHE_APB_CLK_EN_M  (BIT(1))
-#define HP_CLKRST_CACHE_APB_CLK_EN_V  0x1
-#define HP_CLKRST_CACHE_APB_CLK_EN_S  1
-/* HP_CLKRST_CACHE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: cache clock enable.*/
-#define HP_CLKRST_CACHE_CLK_EN    (BIT(0))
-#define HP_CLKRST_CACHE_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_CACHE_CLK_EN_V  0x1
-#define HP_CLKRST_CACHE_CLK_EN_S  0
-
-#define HP_CLKRST_CPU_PERI_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x38)
-/* HP_CLKRST_L2_MEM_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: l2 memory software reset: low active.*/
-#define HP_CLKRST_L2_MEM_RSTN    (BIT(4))
-#define HP_CLKRST_L2_MEM_RSTN_M  (BIT(4))
-#define HP_CLKRST_L2_MEM_RSTN_V  0x1
-#define HP_CLKRST_L2_MEM_RSTN_S  4
-/* HP_CLKRST_L2_MEM_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: l2 memory clock enable.*/
-#define HP_CLKRST_L2_MEM_CLK_EN    (BIT(3))
-#define HP_CLKRST_L2_MEM_CLK_EN_M  (BIT(3))
-#define HP_CLKRST_L2_MEM_CLK_EN_V  0x1
-#define HP_CLKRST_L2_MEM_CLK_EN_S  3
-/* HP_CLKRST_TCM_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: tcm software reset: low active.*/
-#define HP_CLKRST_TCM_RSTN    (BIT(2))
-#define HP_CLKRST_TCM_RSTN_M  (BIT(2))
-#define HP_CLKRST_TCM_RSTN_V  0x1
-#define HP_CLKRST_TCM_RSTN_S  2
-/* HP_CLKRST_TCM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: tcm clock enable.*/
-#define HP_CLKRST_TCM_CLK_EN    (BIT(1))
-#define HP_CLKRST_TCM_CLK_EN_M  (BIT(1))
-#define HP_CLKRST_TCM_CLK_EN_V  0x1
-#define HP_CLKRST_TCM_CLK_EN_S  1
-/* HP_CLKRST_CPU_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: cpu control logic clock enable.*/
-#define HP_CLKRST_CPU_CTRL_CLK_EN    (BIT(0))
-#define HP_CLKRST_CPU_CTRL_CLK_EN_M  (BIT(0))
-#define HP_CLKRST_CPU_CTRL_CLK_EN_V  0x1
-#define HP_CLKRST_CPU_CTRL_CLK_EN_S  0
-
-#define HP_CLKRST_SYNC_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x3C)
-/* HP_CLKRST_CLK_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */
-/*description: .*/
-#define HP_CLKRST_CLK_EN    (BIT(17))
-#define HP_CLKRST_CLK_EN_M  (BIT(17))
-#define HP_CLKRST_CLK_EN_V  0x1
-#define HP_CLKRST_CLK_EN_S  17
-/* HP_CLKRST_HP_ROOT_CLK_SYNC_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: clock sync signal output enable.*/
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN    (BIT(16))
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_M  (BIT(16))
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_V  0x1
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_S  16
-/* HP_CLKRST_HP_ROOT_CLK_SYNC_PERID : R/W ;bitpos:[15:0] ;default: 16'h347 ; */
-/*description: clock sync signal generation period.*/
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID    0x0000FFFF
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_M  ((HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V)<<(HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S))
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V  0xFFFF
-#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S  0
-
-#define HP_CLKRST_WFI_GATE_CLK_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x40)
-/* HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: force group3(L2 Memory) clock on after WFI.*/
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON    (BIT(18))
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_M  (BIT(18))
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_V  0x1
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_S  18
-/* HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON : R/W ;bitpos:[17] ;default: 1'b1 ; */
-/*description: force group2(HP TCM) clock on after WFI.*/
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON    (BIT(17))
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_M  (BIT(17))
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_V  0x1
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_S  17
-/* HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: force group1(L1/L2 cache & trace & cpu_icm_ibus) clock on after WFI.*/
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON    (BIT(16))
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_M  (BIT(16))
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_V  0x1
-#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_S  16
-/* HP_CLKRST_CPU_WFI_DELAY_NUM : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: This register indicates delayed clock cycles before auto gating HP cache/trace c
-lock once WFI asserted.*/
-#define HP_CLKRST_CPU_WFI_DELAY_NUM    0x0000000F
-#define HP_CLKRST_CPU_WFI_DELAY_NUM_M  ((HP_CLKRST_CPU_WFI_DELAY_NUM_V)<<(HP_CLKRST_CPU_WFI_DELAY_NUM_S))
-#define HP_CLKRST_CPU_WFI_DELAY_NUM_V  0xF
-#define HP_CLKRST_CPU_WFI_DELAY_NUM_S  0
-
-#define HP_CLKRST_PVT_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x44)
-/* HP_CLKRST_PVT_APB_RSTN : R/W ;bitpos:[21] ;default: 1'h1 ; */
-/*description: pvt apb resetn.*/
-#define HP_CLKRST_PVT_APB_RSTN    (BIT(21))
-#define HP_CLKRST_PVT_APB_RSTN_M  (BIT(21))
-#define HP_CLKRST_PVT_APB_RSTN_V  0x1
-#define HP_CLKRST_PVT_APB_RSTN_S  21
-/* HP_CLKRST_PVT_PERI_GROUP2_RSTN : R/W ;bitpos:[20] ;default: 1'h1 ; */
-/*description: pvt peri group2 resetn.*/
-#define HP_CLKRST_PVT_PERI_GROUP2_RSTN    (BIT(20))
-#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_M  (BIT(20))
-#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_V  0x1
-#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_S  20
-/* HP_CLKRST_PVT_PERI_GROUP1_RSTN : R/W ;bitpos:[19] ;default: 1'h1 ; */
-/*description: pvt peri group1 resetn.*/
-#define HP_CLKRST_PVT_PERI_GROUP1_RSTN    (BIT(19))
-#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_M  (BIT(19))
-#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_V  0x1
-#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_S  19
-/* HP_CLKRST_PVT_CPU_GROUP2_RSTN : R/W ;bitpos:[18] ;default: 1'h1 ; */
-/*description: pvt cpu group2 resetn.*/
-#define HP_CLKRST_PVT_CPU_GROUP2_RSTN    (BIT(18))
-#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_M  (BIT(18))
-#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_V  0x1
-#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_S  18
-/* HP_CLKRST_PVT_CPU_GROUP1_RSTN : R/W ;bitpos:[17] ;default: 1'h1 ; */
-/*description: pvt cpu group1 resetn.*/
-#define HP_CLKRST_PVT_CPU_GROUP1_RSTN    (BIT(17))
-#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_M  (BIT(17))
-#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_V  0x1
-#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_S  17
-/* HP_CLKRST_PVT_TOP_RSTN : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: pvt top resetn.*/
-#define HP_CLKRST_PVT_TOP_RSTN    (BIT(16))
-#define HP_CLKRST_PVT_TOP_RSTN_M  (BIT(16))
-#define HP_CLKRST_PVT_TOP_RSTN_V  0x1
-#define HP_CLKRST_PVT_TOP_RSTN_S  16
-/* HP_CLKRST_PVT_APB_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: pvt apb clk en.*/
-#define HP_CLKRST_PVT_APB_CLK_EN    (BIT(13))
-#define HP_CLKRST_PVT_APB_CLK_EN_M  (BIT(13))
-#define HP_CLKRST_PVT_APB_CLK_EN_V  0x1
-#define HP_CLKRST_PVT_APB_CLK_EN_S  13
-/* HP_CLKRST_PVT_PERI_GROUP2_CLK_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: pvt peri group2 clk en.*/
-#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN    (BIT(12))
-#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_M  (BIT(12))
-#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_V  0x1
-#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_S  12
-/* HP_CLKRST_PVT_PERI_GROUP1_CLK_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: pvt peri group1 clk en.*/
-#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN    (BIT(11))
-#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_M  (BIT(11))
-#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_V  0x1
-#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_S  11
-/* HP_CLKRST_PVT_CPU_GROUP2_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: pvt cpu group2 clk en.*/
-#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN    (BIT(10))
-#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_M  (BIT(10))
-#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_V  0x1
-#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_S  10
-/* HP_CLKRST_PVT_CPU_GROUP1_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: pvt cpu group1 clk en.*/
-#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN    (BIT(9))
-#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_M  (BIT(9))
-#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_V  0x1
-#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_S  9
-/* HP_CLKRST_PVT_TOP_CLK_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: pvt top clock en.*/
-#define HP_CLKRST_PVT_TOP_CLK_EN    (BIT(8))
-#define HP_CLKRST_PVT_TOP_CLK_EN_M  (BIT(8))
-#define HP_CLKRST_PVT_TOP_CLK_EN_V  0x1
-#define HP_CLKRST_PVT_TOP_CLK_EN_S  8
-/* HP_CLKRST_PVT_CLK_DIV_NUM : R/W ;bitpos:[7:4] ;default: 4'h1 ; */
-/*description: pvt clock div number.*/
-#define HP_CLKRST_PVT_CLK_DIV_NUM    0x0000000F
-#define HP_CLKRST_PVT_CLK_DIV_NUM_M  ((HP_CLKRST_PVT_CLK_DIV_NUM_V)<<(HP_CLKRST_PVT_CLK_DIV_NUM_S))
-#define HP_CLKRST_PVT_CLK_DIV_NUM_V  0xF
-#define HP_CLKRST_PVT_CLK_DIV_NUM_S  4
-/* HP_CLKRST_PVT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */
-/*description: pvt clock sel.*/
-#define HP_CLKRST_PVT_CLK_SEL    0x00000003
-#define HP_CLKRST_PVT_CLK_SEL_M  ((HP_CLKRST_PVT_CLK_SEL_V)<<(HP_CLKRST_PVT_CLK_SEL_S))
-#define HP_CLKRST_PVT_CLK_SEL_V  0x3
-#define HP_CLKRST_PVT_CLK_SEL_S  0
-
-#define HP_CLKRST_TEST_PLL_CTRL_REG          (DR_REG_HP_CLKRST_BASE + 0x48)
-/* HP_CLKRST_TEST_PLL_DIV_NUM : R/W ;bitpos:[27:16] ;default: 12'h3e7 ; */
-/*description: test pll divider number.*/
-#define HP_CLKRST_TEST_PLL_DIV_NUM    0x00000FFF
-#define HP_CLKRST_TEST_PLL_DIV_NUM_M  ((HP_CLKRST_TEST_PLL_DIV_NUM_V)<<(HP_CLKRST_TEST_PLL_DIV_NUM_S))
-#define HP_CLKRST_TEST_PLL_DIV_NUM_V  0xFFF
-#define HP_CLKRST_TEST_PLL_DIV_NUM_S  16
-/* HP_CLKRST_TEST_PLL_SEL : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: test pll source select; 3'h0: RSVD; 3'h1: system PLL; 3'h2: CPU PLL; 3'h3: MPSI
-DLL; 3'h4: SDIO PLL CK0; 3'h5: SDIO PLL CK1; 3'h6: SDIO PLL CK2; 3'h7: AUDIO APL
-L.*/
-#define HP_CLKRST_TEST_PLL_SEL    0x00000007
-#define HP_CLKRST_TEST_PLL_SEL_M  ((HP_CLKRST_TEST_PLL_SEL_V)<<(HP_CLKRST_TEST_PLL_SEL_S))
-#define HP_CLKRST_TEST_PLL_SEL_V  0x7
-#define HP_CLKRST_TEST_PLL_SEL_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_HP_CLKRST_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/hwcrypto_reg.h b/components/soc/esp32p4/include/soc/hwcrypto_reg.h
deleted file mode 100644
index af608fcd27..0000000000
--- a/components/soc/esp32p4/include/soc/hwcrypto_reg.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef __HWCRYPTO_REG_H__
-#define __HWCRYPTO_REG_H__
-
-#include "soc/soc.h"
-
-/* registers for RSA acceleration via Multiple Precision Integer ops */
-#define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
-/* RB & Z use the same memory block, depending on phase of operation */
-#define RSA_MEM_RB_BLOCK_BASE         ((DR_REG_RSA_BASE)+0x200)
-#define RSA_MEM_Z_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x200)
-#define RSA_MEM_Y_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x400)
-#define RSA_MEM_X_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x600)
-
-/* Configuration registers */
-#define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
-#define RSA_LENGTH_REG                (DR_REG_RSA_BASE + 0x804)
-#define RSA_CONSTANT_TIME_REG         (DR_REG_RSA_BASE + 0x820)
-#define RSA_SEARCH_ENABLE_REG         (DR_REG_RSA_BASE + 0x824)
-#define RSA_SEARCH_POS_REG            (DR_REG_RSA_BASE + 0x828)
-
-/* Initialization registers */
-#define RSA_QUERY_CLEAN_REG           (DR_REG_RSA_BASE + 0x808)
-
-/* Calculation start registers */
-#define RSA_MODEXP_START_REG          (DR_REG_RSA_BASE + 0x80c)
-#define RSA_MOD_MULT_START_REG        (DR_REG_RSA_BASE + 0x810)
-#define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x814)
-
-/* Interrupt registers */
-#define RSA_QUERY_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x818)
-#define RSA_CLEAR_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x81C)
-#define RSA_INTERRUPT_REG             (DR_REG_RSA_BASE + 0x82C)
-#define RSA_DATE_REG                  (DR_REG_RSA_BASE + 0x82C)
-
-#define SHA_MODE_SHA1       0
-#define SHA_MODE_SHA224     1
-#define SHA_MODE_SHA256     2
-
-/* SHA acceleration registers */
-#define SHA_MODE_REG                  ((DR_REG_SHA_BASE) + 0x00)
-#define SHA_BLOCK_NUM_REG             ((DR_REG_SHA_BASE) + 0x0C)
-#define SHA_START_REG                 ((DR_REG_SHA_BASE) + 0x10)
-#define SHA_CONTINUE_REG              ((DR_REG_SHA_BASE) + 0x14)
-#define SHA_BUSY_REG                  ((DR_REG_SHA_BASE) + 0x18)
-#define SHA_DMA_START_REG             ((DR_REG_SHA_BASE) + 0x1C)
-#define SHA_DMA_CONTINUE_REG          ((DR_REG_SHA_BASE) + 0x20)
-#define SHA_CLEAR_IRQ_REG             ((DR_REG_SHA_BASE) + 0x24)
-#define SHA_INT_ENA_REG               ((DR_REG_SHA_BASE) + 0x28)
-#define SHA_DATE_REG                  ((DR_REG_SHA_BASE) + 0x2C)
-
-#define SHA_H_BASE                    ((DR_REG_SHA_BASE) + 0x40)
-#define SHA_TEXT_BASE                 ((DR_REG_SHA_BASE) + 0x80)
-
-/* AES Block operation modes */
-#define AES_BLOCK_MODE_ECB     0
-#define AES_BLOCK_MODE_CBC     1
-#define AES_BLOCK_MODE_OFB     2
-#define AES_BLOCK_MODE_CTR     3
-#define AES_BLOCK_MODE_CFB8    4
-#define AES_BLOCK_MODE_CFB128  5
-
-/* AES Block operation modes (used with DMA) */
-#define AES_BLOCK_MODE_ECB     0
-#define AES_BLOCK_MODE_CBC     1
-#define AES_BLOCK_MODE_OFB     2
-#define AES_BLOCK_MODE_CTR     3
-#define AES_BLOCK_MODE_CFB8    4
-#define AES_BLOCK_MODE_CFB128  5
-
-/* AES acceleration registers */
-#define AES_MODE_REG            ((DR_REG_AES_BASE) + 0x40)
-#define AES_ENDIAN_REG          ((DR_REG_AES_BASE) + 0x44)
-#define AES_TRIGGER_REG         ((DR_REG_AES_BASE) + 0x48)
-#define AES_STATE_REG           ((DR_REG_AES_BASE) + 0x4c)
-#define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
-#define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
-#define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
-#define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
-#define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
-#define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
-#define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
-#define AES_INT_CLEAR_REG       ((DR_REG_AES_BASE) + 0xAC)
-#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
-#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
-#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
-
-#define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
-#define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
-#define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
-#define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
-#define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
-#define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
-#define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
-
-#define AES_KEY_BASE            ((DR_REG_AES_BASE) + 0x00)
-#define AES_TEXT_IN_BASE        ((DR_REG_AES_BASE) + 0x20)
-#define AES_TEXT_OUT_BASE       ((DR_REG_AES_BASE) + 0x30)
-#define AES_IV_BASE             ((DR_REG_AES_BASE) + 0x50)
-#define AES_H_BASE              ((DR_REG_AES_BASE) + 0x60)
-#define AES_J_BASE              ((DR_REG_AES_BASE) + 0x70)
-#define AES_T_BASE              ((DR_REG_AES_BASE) + 0x80)
-
-#define AES_INT_CLR_REG         ((DR_REG_AES_BASE) + 0xAC)
-#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
-#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
-#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
-
-/* AES_STATE_REG values */
-#define AES_STATE_IDLE 0
-#define AES_STATE_BUSY 1
-#define AES_STATE_DONE 2
-
-/* HMAC Module */
-#define HMAC_SET_START_REG             ((DR_REG_HMAC_BASE) + 0x40)
-#define HMAC_SET_PARA_PURPOSE_REG      ((DR_REG_HMAC_BASE) + 0x44)
-#define HMAC_SET_PARA_KEY_REG          ((DR_REG_HMAC_BASE) + 0x48)
-#define HMAC_SET_PARA_FINISH_REG       ((DR_REG_HMAC_BASE) + 0x4c)
-#define HMAC_SET_MESSAGE_ONE_REG       ((DR_REG_HMAC_BASE) + 0x50)
-#define HMAC_SET_MESSAGE_ING_REG       ((DR_REG_HMAC_BASE) + 0x54)
-#define HMAC_SET_MESSAGE_END_REG       ((DR_REG_HMAC_BASE) + 0x58)
-#define HMAC_SET_RESULT_FINISH_REG     ((DR_REG_HMAC_BASE) + 0x5c)
-#define HMAC_SET_INVALIDATE_JTAG_REG   ((DR_REG_HMAC_BASE) + 0x60)
-#define HMAC_SET_INVALIDATE_DS_REG     ((DR_REG_HMAC_BASE) + 0x64)
-#define HMAC_QUERY_ERROR_REG           ((DR_REG_HMAC_BASE) + 0x68)
-#define HMAC_QUERY_BUSY_REG            ((DR_REG_HMAC_BASE) + 0x6c)
-
-#define HMAC_WDATA_BASE                ((DR_REG_HMAC_BASE) + 0x80)
-#define HMAC_RDATA_BASE                ((DR_REG_HMAC_BASE) + 0xC0)
-#define HMAC_SET_MESSAGE_PAD_REG       ((DR_REG_HMAC_BASE) + 0xF0)
-#define HMAC_ONE_BLOCK_REG             ((DR_REG_HMAC_BASE) + 0xF4)
-
-#define HMAC_SOFT_JTAG_CTRL_REG        ((DR_REG_HMAC_BASE) + 0xF8)
-#define HMAC_WR_JTAG_REG               ((DR_REG_HMAC_BASE) + 0xFC)
-
-#define HMAC_DATE_REG                  ((DR_REG_HMAC_BASE) + 0xF8)
-
-
-/* AES-XTS registers */
-#define AES_XTS_PLAIN_BASE        ((DR_REG_AES_XTS_BASE) + 0x00)
-#define AES_XTS_SIZE_REG          ((DR_REG_AES_XTS_BASE) + 0x40)
-#define AES_XTS_DESTINATION_REG   ((DR_REG_AES_XTS_BASE) + 0x44)
-#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
-
-#define AES_XTS_TRIGGER_REG       ((DR_REG_AES_XTS_BASE) + 0x4C)
-#define AES_XTS_RELEASE_REG       ((DR_REG_AES_XTS_BASE) + 0x50)
-#define AES_XTS_DESTROY_REG       ((DR_REG_AES_XTS_BASE) + 0x54)
-#define AES_XTS_STATE_REG         ((DR_REG_AES_XTS_BASE) + 0x58)
-#define AES_XTS_DATE_REG          ((DR_REG_AES_XTS_BASE) + 0x5C)
-
-/* Digital Signature registers and memory blocks */
-#define DS_C_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
-#define DS_C_Y_BASE               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
-#define DS_C_M_BASE               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 )
-#define DS_C_RB_BASE              ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 )
-#define DS_C_BOX_BASE             ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 )
-#define DS_IV_BASE                ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
-#define DS_X_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
-#define DS_Z_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
-
-#define DS_SET_START_REG          ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
-#define DS_SET_ME_REG             ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
-#define DS_SET_FINISH_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
-
-#define DS_QUERY_BUSY_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
-#define DS_QUERY_KEY_WRONG_REG    ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
-#define DS_QUERY_CHECK_REG        ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
-
-#define DS_QUERY_CHECK_INVALID_DIGEST  (1<<0)
-#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
-
-#define DS_DATE_REG               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
-
-#endif
diff --git a/components/soc/esp32p4/include/soc/i2c_ext_reg.h b/components/soc/esp32p4/include/soc/i2c_ext_reg.h
deleted file mode 100644
index 9cdfdcede6..0000000000
--- a/components/soc/esp32p4/include/soc/i2c_ext_reg.h
+++ /dev/null
@@ -1,1521 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2C_SCL_LOW_PERIOD_REG register
- *  Configures the low level width of the SCL Clock.
- */
-#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
-/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  Configures the low level width of the SCL Clock.
- *  Measurement unit: i2c_sclk.
- */
-#define I2C_SCL_LOW_PERIOD    0x000001FFU
-#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
-#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
-#define I2C_SCL_LOW_PERIOD_S  0
-
-/** I2C_CTR_REG register
- *  Transmission setting
- */
-#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
-/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
- *  Configures the SDA output mode
- *  1: Direct output,
- *
- *  0: Open drain output.
- */
-#define I2C_SDA_FORCE_OUT    (BIT(0))
-#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
-#define I2C_SDA_FORCE_OUT_V  0x00000001U
-#define I2C_SDA_FORCE_OUT_S  0
-/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
- *  Configures the SCL output mode
- *  1: Direct output,
- *
- *  0: Open drain output.
- */
-#define I2C_SCL_FORCE_OUT    (BIT(1))
-#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
-#define I2C_SCL_FORCE_OUT_V  0x00000001U
-#define I2C_SCL_FORCE_OUT_S  1
-/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
- *  Configures the sample mode for SDA.
- *  1: Sample SDA data on the SCL low level.
- *
- *  0: Sample SDA data on the SCL high level.
- */
-#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
-#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
-#define I2C_SAMPLE_SCL_LEVEL_S  2
-/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
- *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
- *  reached the threshold.
- */
-#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
-#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
-#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
-#define I2C_RX_FULL_ACK_LEVEL_S  3
-/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
- *  Configures the module as an I2C Master or Slave.
- *  0: Slave
- *
- *  1: Master
- */
-#define I2C_MS_MODE    (BIT(4))
-#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
-#define I2C_MS_MODE_V  0x00000001U
-#define I2C_MS_MODE_S  4
-/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
- *  Configures to start sending the data in txfifo for slave.
- *  0: No effect
- *
- *  1: Start
- */
-#define I2C_TRANS_START    (BIT(5))
-#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
-#define I2C_TRANS_START_V  0x00000001U
-#define I2C_TRANS_START_S  5
-/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
- *  Configures to control the sending order for data needing to be sent.
- *  1: send data from the least significant bit,
- *
- *  0: send data from the most significant bit.
- */
-#define I2C_TX_LSB_FIRST    (BIT(6))
-#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
-#define I2C_TX_LSB_FIRST_V  0x00000001U
-#define I2C_TX_LSB_FIRST_S  6
-/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
- *  Configures to control the storage order for received data.
- *  1: receive data from the least significant bit
- *
- *  0: receive data from the most significant bit.
- */
-#define I2C_RX_LSB_FIRST    (BIT(7))
-#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
-#define I2C_RX_LSB_FIRST_V  0x00000001U
-#define I2C_RX_LSB_FIRST_S  7
-/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether to gate clock signal for registers.
- *
- *  0: Force clock on for registers
- *
- *  1: Support clock only when registers are read or written to by software.
- */
-#define I2C_CLK_EN    (BIT(8))
-#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
-#define I2C_CLK_EN_V  0x00000001U
-#define I2C_CLK_EN_S  8
-/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
- *  Configures to enable I2C bus arbitration detection.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_ARBITRATION_EN    (BIT(9))
-#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
-#define I2C_ARBITRATION_EN_V  0x00000001U
-#define I2C_ARBITRATION_EN_S  9
-/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
- *  Configures to reset the SCL_FSM.
- *  0: No effect
- *
- *  1: Reset
- */
-#define I2C_FSM_RST    (BIT(10))
-#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
-#define I2C_FSM_RST_V  0x00000001U
-#define I2C_FSM_RST_S  10
-/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
- *  Configures this bit for synchronization
- *  0: No effect
- *
- *  1: Synchronize
- */
-#define I2C_CONF_UPGATE    (BIT(11))
-#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
-#define I2C_CONF_UPGATE_V  0x00000001U
-#define I2C_CONF_UPGATE_S  11
-/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
- *  Configures to enable slave to send data automatically
- *  0: Disable
- *
- *  1: Enable
- */
-#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
-#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
-#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
-#define I2C_SLV_TX_AUTO_START_EN_S  12
-/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
- *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
- *  0: Not check
- *
- *  1: Check
- */
-#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
-#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
-#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
-#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
-/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
- *  Configures to support the 7bit general call function.
- *  0: Not support
- *
- *  1: Support
- */
-#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
-#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
-#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
-#define I2C_ADDR_BROADCASTING_EN_S  14
-
-/** I2C_SR_REG register
- *  Describe I2C work status.
- */
-#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
-/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
- *  Represents the received ACK value in master mode or slave mode.
- *  0: ACK,
- *
- *  1: NACK.
- */
-#define I2C_RESP_REC    (BIT(0))
-#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
-#define I2C_RESP_REC_V  0x00000001U
-#define I2C_RESP_REC_S  0
-/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
- *  Represents the transfer direction in slave mode,.
- *  1: Master reads from slave,
- *
- *  0: Master writes to slave.
- */
-#define I2C_SLAVE_RW    (BIT(1))
-#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
-#define I2C_SLAVE_RW_V  0x00000001U
-#define I2C_SLAVE_RW_S  1
-/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
- *  Represents whether the I2C controller loses control of SCL line.
- *  0: No arbitration lost
- *
- *  1: Arbitration lost
- */
-#define I2C_ARB_LOST    (BIT(3))
-#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
-#define I2C_ARB_LOST_V  0x00000001U
-#define I2C_ARB_LOST_S  3
-/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
- *  Represents the I2C bus state.
- *  1: The I2C bus is busy transferring data,
- *
- *  0: The I2C bus is in idle state.
- */
-#define I2C_BUS_BUSY    (BIT(4))
-#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
-#define I2C_BUS_BUSY_V  0x00000001U
-#define I2C_BUS_BUSY_S  4
-/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
- *  Represents whether the address sent by the master is equal to the address of the
- *  slave.
- *  Valid only when the module is configured as an I2C Slave.
- *  0: Not equal
- *
- *  1: Equal
- */
-#define I2C_SLAVE_ADDRESSED    (BIT(5))
-#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
-#define I2C_SLAVE_ADDRESSED_V  0x00000001U
-#define I2C_SLAVE_ADDRESSED_S  5
-/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
- *  Represents the number of data bytes to be sent.
- */
-#define I2C_RXFIFO_CNT    0x0000003FU
-#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
-#define I2C_RXFIFO_CNT_V  0x0000003FU
-#define I2C_RXFIFO_CNT_S  8
-/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
- *  Represents the cause of SCL clocking stretching in slave mode.
- *  0: Stretching SCL low when the master starts to read data.
- *
- *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
- *
- *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
- */
-#define I2C_STRETCH_CAUSE    0x00000003U
-#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
-#define I2C_STRETCH_CAUSE_V  0x00000003U
-#define I2C_STRETCH_CAUSE_S  14
-/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
- *  Represents the number of data bytes received in RAM.
- */
-#define I2C_TXFIFO_CNT    0x0000003FU
-#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
-#define I2C_TXFIFO_CNT_V  0x0000003FU
-#define I2C_TXFIFO_CNT_S  18
-/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
- *  Represents the states of the I2C module state machine.
- *  0: Idle,
- *
- *  1: Address shift,
- *
- *  2: ACK address,
- *
- *  3: Rx data,
- *
- *  4: Tx data,
- *
- *  5: Send ACK,
- *
- *  6: Wait ACK
- */
-#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
-#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
-#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
-#define I2C_SCL_MAIN_STATE_LAST_S  24
-/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
- *  Represents the states of the state machine used to produce SCL.
- *  0: Idle,
- *
- *  1: Start,
- *
- *  2: Negative edge,
- *
- *  3: Low,
- *
- *  4: Positive edge,
- *
- *  5: High,
- *
- *  6: Stop
- */
-#define I2C_SCL_STATE_LAST    0x00000007U
-#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
-#define I2C_SCL_STATE_LAST_V  0x00000007U
-#define I2C_SCL_STATE_LAST_S  28
-
-/** I2C_TO_REG register
- *  Setting time out control for receiving data.
- */
-#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
-/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
- *  Configures the timeout threshold period for SCL stucking at high or low level. The
- *  actual period is 2^(reg_time_out_value).
- *  Measurement unit: i2c_sclk.
- */
-#define I2C_TIME_OUT_VALUE    0x0000001FU
-#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
-#define I2C_TIME_OUT_VALUE_V  0x0000001FU
-#define I2C_TIME_OUT_VALUE_S  0
-/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
- *  Configures to enable time out control.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_TIME_OUT_EN    (BIT(5))
-#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
-#define I2C_TIME_OUT_EN_V  0x00000001U
-#define I2C_TIME_OUT_EN_S  5
-
-/** I2C_SLAVE_ADDR_REG register
- *  Local slave address setting
- */
-#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
-/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
- *  Configure the slave address of I2C Slave.
- */
-#define I2C_SLAVE_ADDR    0x00007FFFU
-#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
-#define I2C_SLAVE_ADDR_V  0x00007FFFU
-#define I2C_SLAVE_ADDR_S  0
-/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
- *  Configures to enable the slave 10-bit addressing mode in master mode.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_ADDR_10BIT_EN    (BIT(31))
-#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
-#define I2C_ADDR_10BIT_EN_V  0x00000001U
-#define I2C_ADDR_10BIT_EN_S  31
-
-/** I2C_FIFO_ST_REG register
- *  FIFO status register.
- */
-#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
-/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
- *  Represents the offset address of the APB reading from RXFIFO
- */
-#define I2C_RXFIFO_RADDR    0x0000001FU
-#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
-#define I2C_RXFIFO_RADDR_V  0x0000001FU
-#define I2C_RXFIFO_RADDR_S  0
-/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
- *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
- */
-#define I2C_RXFIFO_WADDR    0x0000001FU
-#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
-#define I2C_RXFIFO_WADDR_V  0x0000001FU
-#define I2C_RXFIFO_WADDR_S  5
-/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
- *  Represents the offset address of i2c module reading from TXFIFO.
- */
-#define I2C_TXFIFO_RADDR    0x0000001FU
-#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
-#define I2C_TXFIFO_RADDR_V  0x0000001FU
-#define I2C_TXFIFO_RADDR_S  10
-/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
- *  Represents the offset address of APB bus writing to TXFIFO.
- */
-#define I2C_TXFIFO_WADDR    0x0000001FU
-#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
-#define I2C_TXFIFO_WADDR_V  0x0000001FU
-#define I2C_TXFIFO_WADDR_S  15
-/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
- *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
- *  I2C slave mode.
- */
-#define I2C_SLAVE_RW_POINT    0x000000FFU
-#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
-#define I2C_SLAVE_RW_POINT_V  0x000000FFU
-#define I2C_SLAVE_RW_POINT_S  22
-
-/** I2C_FIFO_CONF_REG register
- *  FIFO configuration register.
- */
-#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
-/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
- *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
- *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
- */
-#define I2C_RXFIFO_WM_THRHD    0x0000001FU
-#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
-#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
-#define I2C_RXFIFO_WM_THRHD_S  0
-/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
- *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
- *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
- */
-#define I2C_TXFIFO_WM_THRHD    0x0000001FU
-#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
-#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
-#define I2C_TXFIFO_WM_THRHD_S  5
-/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
- *  Configures to enable APB nonfifo access.
- */
-#define I2C_NONFIFO_EN    (BIT(10))
-#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
-#define I2C_NONFIFO_EN_V  0x00000001U
-#define I2C_NONFIFO_EN_S  10
-/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
- *  Configures to enable double addressing mode. When this mode is enabled, the byte
- *  received after the I2C address byte represents the offset address in the I2C Slave
- *  RAM.
- *  0: Disable
- *
- *  1: Enable
- */
-#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
-#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
-#define I2C_FIFO_ADDR_CFG_EN_S  11
-/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
- *  Configures to reset RXFIFO.
- *  0: No effect
- *
- *  1: Reset
- */
-#define I2C_RX_FIFO_RST    (BIT(12))
-#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
-#define I2C_RX_FIFO_RST_V  0x00000001U
-#define I2C_RX_FIFO_RST_S  12
-/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
- *  Configures to reset TXFIFO.
- *  0: No effect
- *
- *  1: Reset
- */
-#define I2C_TX_FIFO_RST    (BIT(13))
-#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
-#define I2C_TX_FIFO_RST_V  0x00000001U
-#define I2C_TX_FIFO_RST_S  13
-/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
- *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
- *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_FIFO_PRT_EN    (BIT(14))
-#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
-#define I2C_FIFO_PRT_EN_V  0x00000001U
-#define I2C_FIFO_PRT_EN_S  14
-
-/** I2C_DATA_REG register
- *  Rx FIFO read data.
- */
-#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
-/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
- *  Represents the value of RXFIFO read data.
- */
-#define I2C_FIFO_RDATA    0x000000FFU
-#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
-#define I2C_FIFO_RDATA_V  0x000000FFU
-#define I2C_FIFO_RDATA_S  0
-
-/** I2C_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
-/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
-#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
-#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_RAW_S  0
-/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
- *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
-#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
-#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_RAW_S  1
-/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
-#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_RAW_S  2
-/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
- *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_RAW    (BIT(3))
-#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
-#define I2C_END_DETECT_INT_RAW_V  0x00000001U
-#define I2C_END_DETECT_INT_RAW_S  3
-/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
- *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
-#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
-/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
- *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
-#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_RAW_S  5
-/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
- *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
-#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
-/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
- *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
-#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_RAW_S  7
-/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
- *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_RAW    (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
-#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
-#define I2C_TIME_OUT_INT_RAW_S  8
-/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
- *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_RAW    (BIT(9))
-#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
-#define I2C_TRANS_START_INT_RAW_V  0x00000001U
-#define I2C_TRANS_START_INT_RAW_S  9
-/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
- *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_RAW    (BIT(10))
-#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
-#define I2C_NACK_INT_RAW_V  0x00000001U
-#define I2C_NACK_INT_RAW_S  10
-/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
- *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
-#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_RAW_S  11
-/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
-#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_RAW_S  12
-/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
- *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
-#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
-#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_RAW_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
- *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
-/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
- *  The raw interrupt status of I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_RAW    (BIT(15))
-#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
-#define I2C_DET_START_INT_RAW_V  0x00000001U
-#define I2C_DET_START_INT_RAW_S  15
-/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
- *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
-#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_RAW_S  16
-/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
- *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
-#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
-#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_RAW_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0;
- *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M  (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S  18
-
-/** I2C_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
-/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
-#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
-#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_CLR_S  0
-/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
-#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
-#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_CLR_S  1
-/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
-#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_CLR_S  2
-/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_CLR    (BIT(3))
-#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
-#define I2C_END_DETECT_INT_CLR_V  0x00000001U
-#define I2C_END_DETECT_INT_CLR_S  3
-/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
-#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
-/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
-#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_CLR_S  5
-/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
-#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
-/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
-#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_CLR_S  7
-/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_CLR    (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
-#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
-#define I2C_TIME_OUT_INT_CLR_S  8
-/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_CLR    (BIT(9))
-#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
-#define I2C_TRANS_START_INT_CLR_V  0x00000001U
-#define I2C_TRANS_START_INT_CLR_S  9
-/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_CLR    (BIT(10))
-#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
-#define I2C_NACK_INT_CLR_V  0x00000001U
-#define I2C_NACK_INT_CLR_S  10
-/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
-#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_CLR_S  11
-/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
-#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_CLR_S  12
-/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
-#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
-#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_CLR_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
-/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Write 1 to clear I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_CLR    (BIT(15))
-#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
-#define I2C_DET_START_INT_CLR_V  0x00000001U
-#define I2C_DET_START_INT_CLR_S  15
-/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
-#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_CLR_S  16
-/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
-#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
-#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_CLR_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M  (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S  18
-
-/** I2C_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
-/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
-#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_ENA_S  0
-/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
-#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_ENA_S  1
-/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
-#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_ENA_S  2
-/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_ENA    (BIT(3))
-#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
-#define I2C_END_DETECT_INT_ENA_V  0x00000001U
-#define I2C_END_DETECT_INT_ENA_S  3
-/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
-#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
-/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
-#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_ENA_S  5
-/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
-#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
-/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
-#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_ENA_S  7
-/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_ENA    (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
-#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
-#define I2C_TIME_OUT_INT_ENA_S  8
-/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_ENA    (BIT(9))
-#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
-#define I2C_TRANS_START_INT_ENA_V  0x00000001U
-#define I2C_TRANS_START_INT_ENA_S  9
-/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_ENA    (BIT(10))
-#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
-#define I2C_NACK_INT_ENA_V  0x00000001U
-#define I2C_NACK_INT_ENA_S  10
-/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
-#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_ENA_S  11
-/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
-#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_ENA_S  12
-/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
-#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_ENA_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
-/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  Write 1 to enable I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_ENA    (BIT(15))
-#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
-#define I2C_DET_START_INT_ENA_V  0x00000001U
-#define I2C_DET_START_INT_ENA_S  15
-/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
-#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_ENA_S  16
-/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
-#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_ENA_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S  18
-
-/** I2C_INT_STATUS_REG register
- *  Status of captured I2C communication events
- */
-#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
-/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
-#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_ST_S  0
-/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
-#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_ST_S  1
-/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
-#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_ST_S  2
-/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_ST    (BIT(3))
-#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
-#define I2C_END_DETECT_INT_ST_V  0x00000001U
-#define I2C_END_DETECT_INT_ST_S  3
-/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
-#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
-/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
-#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_ST_S  5
-/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
-#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
-/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
-#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_ST_S  7
-/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_ST    (BIT(8))
-#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
-#define I2C_TIME_OUT_INT_ST_V  0x00000001U
-#define I2C_TIME_OUT_INT_ST_S  8
-/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_ST    (BIT(9))
-#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
-#define I2C_TRANS_START_INT_ST_V  0x00000001U
-#define I2C_TRANS_START_INT_ST_S  9
-/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_ST    (BIT(10))
-#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
-#define I2C_NACK_INT_ST_V  0x00000001U
-#define I2C_NACK_INT_ST_S  10
-/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
-#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_ST_S  11
-/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
-#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_ST_S  12
-/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
-#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_ST_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
- *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
-#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
-/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  The masked interrupt status status of I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_ST    (BIT(15))
-#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
-#define I2C_DET_START_INT_ST_V  0x00000001U
-#define I2C_DET_START_INT_ST_S  15
-/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
- *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
-#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_ST_S  16
-/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
- *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
-#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_ST_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0;
- *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S  18
-
-/** I2C_SDA_HOLD_REG register
- *  Configures the hold time after a negative SCL edge.
- */
-#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
-/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
- *  Configures the time to hold the data after the falling edge of SCL.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SDA_HOLD_TIME    0x000001FFU
-#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
-#define I2C_SDA_HOLD_TIME_V  0x000001FFU
-#define I2C_SDA_HOLD_TIME_S  0
-
-/** I2C_SDA_SAMPLE_REG register
- *  Configures the sample time after a positive SCL edge.
- */
-#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
-/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
- *  Configures the sample time after a positive SCL edge.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SDA_SAMPLE_TIME    0x000001FFU
-#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
-#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
-#define I2C_SDA_SAMPLE_TIME_S  0
-
-/** I2C_SCL_HIGH_PERIOD_REG register
- *  Configures the high level width of SCL
- */
-#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
-/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  Configures for how long SCL remains high in master mode.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_HIGH_PERIOD    0x000001FFU
-#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
-#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
-#define I2C_SCL_HIGH_PERIOD_S  0
-/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
- *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
-#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
-#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
-#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
-
-/** I2C_SCL_START_HOLD_REG register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
-/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the falling edge of SDA and the falling edge of SCL for
- *  a START condition.
- *  Measurement unit: i2c_sclk.
- */
-#define I2C_SCL_START_HOLD_TIME    0x000001FFU
-#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
-#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
-#define I2C_SCL_START_HOLD_TIME_S  0
-
-/** I2C_SCL_RSTART_SETUP_REG register
- *  Configures the delay between the positive edge of SCL and the negative edge of SDA
- */
-#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
-/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the positive edge of SCL and the negative edge of SDA
- *  for a RESTART condition.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
-#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
-#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
-#define I2C_SCL_RSTART_SETUP_TIME_S  0
-
-/** I2C_SCL_STOP_HOLD_REG register
- *  Configures the delay after the SCL clock edge for a stop condition
- */
-#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
-/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the delay after the STOP condition.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
-#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
-#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
-#define I2C_SCL_STOP_HOLD_TIME_S  0
-
-/** I2C_SCL_STOP_SETUP_REG register
- *  Configures the delay between the SDA and SCL rising edge for a stop condition.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
-/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the rising edge of SCL and the rising edge of SDA.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
-#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
-#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
-#define I2C_SCL_STOP_SETUP_TIME_S  0
-
-/** I2C_FILTER_CFG_REG register
- *  SCL and SDA filter configuration register
- */
-#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
-/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
- *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
- *  input has smaller width than this register value, the I2C controller will ignore
- *  that pulse.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_FILTER_THRES    0x0000000FU
-#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
-#define I2C_SCL_FILTER_THRES_V  0x0000000FU
-#define I2C_SCL_FILTER_THRES_S  0
-/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
- *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
- *  input has smaller width than this register value, the I2C controller will ignore
- *  that pulse.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SDA_FILTER_THRES    0x0000000FU
-#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
-#define I2C_SDA_FILTER_THRES_V  0x0000000FU
-#define I2C_SDA_FILTER_THRES_S  4
-/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
- *  Configures to enable the filter function for SCL.
- */
-#define I2C_SCL_FILTER_EN    (BIT(8))
-#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
-#define I2C_SCL_FILTER_EN_V  0x00000001U
-#define I2C_SCL_FILTER_EN_S  8
-/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
- *  Configures to enable the filter function for SDA.
- */
-#define I2C_SDA_FILTER_EN    (BIT(9))
-#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
-#define I2C_SDA_FILTER_EN_V  0x00000001U
-#define I2C_SDA_FILTER_EN_S  9
-
-/** I2C_COMD0_REG register
- *  I2C command register 0
- */
-#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
-/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 0. It consists of three parts:
- *  op_code is the command,
- *  0: RSTART,
- *  1: WRITE,
- *  2: READ,
- *  3: STOP,
- *  4: END.
- *
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more information.
- */
-#define I2C_COMMAND0    0x00003FFFU
-#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
-#define I2C_COMMAND0_V  0x00003FFFU
-#define I2C_COMMAND0_S  0
-/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 0 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND0_DONE    (BIT(31))
-#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
-#define I2C_COMMAND0_DONE_V  0x00000001U
-#define I2C_COMMAND0_DONE_S  31
-
-/** I2C_COMD1_REG register
- *  I2C command register 1
- */
-#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
-/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 1. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND1    0x00003FFFU
-#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
-#define I2C_COMMAND1_V  0x00003FFFU
-#define I2C_COMMAND1_S  0
-/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 1 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND1_DONE    (BIT(31))
-#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
-#define I2C_COMMAND1_DONE_V  0x00000001U
-#define I2C_COMMAND1_DONE_S  31
-
-/** I2C_COMD2_REG register
- *  I2C command register 2
- */
-#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
-/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 2. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND2    0x00003FFFU
-#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
-#define I2C_COMMAND2_V  0x00003FFFU
-#define I2C_COMMAND2_S  0
-/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 2 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND2_DONE    (BIT(31))
-#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
-#define I2C_COMMAND2_DONE_V  0x00000001U
-#define I2C_COMMAND2_DONE_S  31
-
-/** I2C_COMD3_REG register
- *  I2C command register 3
- */
-#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
-/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 3. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND3    0x00003FFFU
-#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
-#define I2C_COMMAND3_V  0x00003FFFU
-#define I2C_COMMAND3_S  0
-/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 3 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND3_DONE    (BIT(31))
-#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
-#define I2C_COMMAND3_DONE_V  0x00000001U
-#define I2C_COMMAND3_DONE_S  31
-
-/** I2C_COMD4_REG register
- *  I2C command register 4
- */
-#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
-/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 4. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND4    0x00003FFFU
-#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
-#define I2C_COMMAND4_V  0x00003FFFU
-#define I2C_COMMAND4_S  0
-/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 4 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND4_DONE    (BIT(31))
-#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
-#define I2C_COMMAND4_DONE_V  0x00000001U
-#define I2C_COMMAND4_DONE_S  31
-
-/** I2C_COMD5_REG register
- *  I2C command register 5
- */
-#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
-/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 5. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND5    0x00003FFFU
-#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
-#define I2C_COMMAND5_V  0x00003FFFU
-#define I2C_COMMAND5_S  0
-/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 5 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND5_DONE    (BIT(31))
-#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
-#define I2C_COMMAND5_DONE_V  0x00000001U
-#define I2C_COMMAND5_DONE_S  31
-
-/** I2C_COMD6_REG register
- *  I2C command register 6
- */
-#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
-/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 6. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND6    0x00003FFFU
-#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
-#define I2C_COMMAND6_V  0x00003FFFU
-#define I2C_COMMAND6_S  0
-/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 6 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND6_DONE    (BIT(31))
-#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
-#define I2C_COMMAND6_DONE_V  0x00000001U
-#define I2C_COMMAND6_DONE_S  31
-
-/** I2C_COMD7_REG register
- *  I2C command register 7
- */
-#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
-/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 7. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND7    0x00003FFFU
-#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
-#define I2C_COMMAND7_V  0x00003FFFU
-#define I2C_COMMAND7_S  0
-/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 7 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND7_DONE    (BIT(31))
-#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
-#define I2C_COMMAND7_DONE_V  0x00000001U
-#define I2C_COMMAND7_DONE_S  31
-
-/** I2C_SCL_ST_TIME_OUT_REG register
- *  SCL status time out register
- */
-#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
-/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
- *  more than 23.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_ST_TO_I2C    0x0000001FU
-#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
-#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
-#define I2C_SCL_ST_TO_I2C_S  0
-
-/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
- *  SCL main status time out register
- */
-#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
-/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
- *  no more than 23.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
-#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
-#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
-#define I2C_SCL_MAIN_ST_TO_I2C_S  0
-
-/** I2C_SCL_SP_CONF_REG register
- *  Power configuration register
- */
-#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
-/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
- *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
- *  equals to reg_scl_rst_slv_num[4:0].
- */
-#define I2C_SCL_RST_SLV_EN    (BIT(0))
-#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
-#define I2C_SCL_RST_SLV_EN_V  0x00000001U
-#define I2C_SCL_RST_SLV_EN_S  0
-/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
- *  Configure the pulses of SCL generated in I2C master mode.
- *  Valid when reg_scl_rst_slv_en is 1.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_RST_SLV_NUM    0x0000001FU
-#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
-#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
-#define I2C_SCL_RST_SLV_NUM_S  1
-/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
- *  Configures to power down the I2C output SCL line.
- *  0: Not power down.
- *
- *  1: Power down.
- *  Valid only when reg_scl_force_out is 1.
- */
-#define I2C_SCL_PD_EN    (BIT(6))
-#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
-#define I2C_SCL_PD_EN_V  0x00000001U
-#define I2C_SCL_PD_EN_S  6
-/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
- *  Configures to power down the I2C output SDA line.
- *  0: Not power down.
- *
- *  1: Power down.
- *  Valid only when reg_sda_force_out is 1.
- */
-#define I2C_SDA_PD_EN    (BIT(7))
-#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
-#define I2C_SDA_PD_EN_V  0x00000001U
-#define I2C_SDA_PD_EN_S  7
-
-/** I2C_SCL_STRETCH_CONF_REG register
- *  Set SCL stretch of I2C slave
- */
-#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
-/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
- *  Configures the time period to release the SCL line from stretching to avoid timing
- *  violation. Usually it should be larger than the SDA setup time.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
-#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
-#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
-#define I2C_STRETCH_PROTECT_NUM_S  0
-/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
- *  Configures to enable slave SCL stretch function.
- *  0: Disable
- *
- *  1: Enable
- *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
- *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
- */
-#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
-#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
-#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
-#define I2C_SLAVE_SCL_STRETCH_EN_S  10
-/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
- *  Configures to clear the I2C slave SCL stretch function.
- *  0: No effect
- *
- *  1: Clear
- */
-#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
-#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
-#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
-#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
-/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
- *  Configures to enable the function for slave to control ACK level.
- *  0: Disable
- *
- *  1: Enable
- */
-#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
-/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
- *  Set the ACK level when slave controlling ACK level function enables.
- *  0: Low level
- *
- *  1: High level
- */
-#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
-#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
-#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
-#define I2C_SLAVE_BYTE_ACK_LVL_S  13
-
-/** I2C_DATE_REG register
- *  Version register
- */
-#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
-/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050;
- *  Version control register.
- */
-#define I2C_DATE    0xFFFFFFFFU
-#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
-#define I2C_DATE_V  0xFFFFFFFFU
-#define I2C_DATE_S  0
-
-/** I2C_TXFIFO_START_ADDR_REG register
- *  I2C TXFIFO base address register
- */
-#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
-/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Represents the I2C txfifo first address.
- */
-#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
-#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
-#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define I2C_TXFIFO_START_ADDR_S  0
-
-/** I2C_RXFIFO_START_ADDR_REG register
- *  I2C RXFIFO base address register
- */
-#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
-/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Represents the I2C rxfifo first address.
- */
-#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
-#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
-#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define I2C_RXFIFO_START_ADDR_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/i2c_ext_struct.h b/components/soc/esp32p4/include/soc/i2c_ext_struct.h
deleted file mode 100644
index eb8069be9c..0000000000
--- a/components/soc/esp32p4/include/soc/i2c_ext_struct.h
+++ /dev/null
@@ -1,1276 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Timing registers */
-/** Type of scl_low_period register
- *  Configures the low level width of the SCL Clock.
- */
-typedef union {
-    struct {
-        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the low level width of the SCL Clock.
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t scl_low_period:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_low_period_reg_t;
-
-/** Type of sda_hold register
- *  Configures the hold time after a negative SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the time to hold the data after the falling edge of SCL.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_sda_hold_reg_t;
-
-/** Type of sda_sample register
- *  Configures the sample time after a positive SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the sample time after a positive SCL edge.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_sample_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_sda_sample_reg_t;
-
-/** Type of scl_high_period register
- *  Configures the high level width of SCL
- */
-typedef union {
-    struct {
-        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
-         *  Configures for how long SCL remains high in master mode.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_high_period:9;
-        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
-         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_wait_high_period:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} i2c_scl_high_period_reg_t;
-
-/** Type of scl_start_hold register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-typedef union {
-    struct {
-        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
-         *  a START condition.
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t scl_start_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_start_hold_reg_t;
-
-/** Type of scl_rstart_setup register
- *  Configures the delay between the positive edge of SCL and the negative edge of SDA
- */
-typedef union {
-    struct {
-        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the positive edge of SCL and the negative edge of SDA
-         *  for a RESTART condition.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_rstart_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_rstart_setup_reg_t;
-
-/** Type of scl_stop_hold register
- *  Configures the delay after the SCL clock edge for a stop condition
- */
-typedef union {
-    struct {
-        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the delay after the STOP condition.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_stop_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_stop_hold_reg_t;
-
-/** Type of scl_stop_setup register
- *  Configures the delay between the SDA and SCL rising edge for a stop condition.
- *  Measurement unit: i2c_sclk
- */
-typedef union {
-    struct {
-        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the rising edge of SCL and the rising edge of SDA.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_stop_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_stop_setup_reg_t;
-
-/** Type of scl_st_time_out register
- *  SCL status time out register
- */
-typedef union {
-    struct {
-        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
-         *  more than 23.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} i2c_scl_st_time_out_reg_t;
-
-/** Type of scl_main_st_time_out register
- *  SCL main status time out register
- */
-typedef union {
-    struct {
-        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
-         *  no more than 23.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_main_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} i2c_scl_main_st_time_out_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of ctr register
- *  Transmission setting
- */
-typedef union {
-    struct {
-        /** sda_force_out : R/W; bitpos: [0]; default: 0;
-         *  Configures the SDA output mode
-         *  1: Direct output,
-         *
-         *  0: Open drain output.
-         */
-        uint32_t sda_force_out:1;
-        /** scl_force_out : R/W; bitpos: [1]; default: 0;
-         *  Configures the SCL output mode
-         *  1: Direct output,
-         *
-         *  0: Open drain output.
-         */
-        uint32_t scl_force_out:1;
-        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
-         *  Configures the sample mode for SDA.
-         *  1: Sample SDA data on the SCL low level.
-         *
-         *  0: Sample SDA data on the SCL high level.
-         */
-        uint32_t sample_scl_level:1;
-        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
-         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
-         *  reached the threshold.
-         */
-        uint32_t rx_full_ack_level:1;
-        /** ms_mode : R/W; bitpos: [4]; default: 0;
-         *  Configures the module as an I2C Master or Slave.
-         *  0: Slave
-         *
-         *  1: Master
-         */
-        uint32_t ms_mode:1;
-        /** trans_start : WT; bitpos: [5]; default: 0;
-         *  Configures to start sending the data in txfifo for slave.
-         *  0: No effect
-         *
-         *  1: Start
-         */
-        uint32_t trans_start:1;
-        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
-         *  Configures to control the sending order for data needing to be sent.
-         *  1: send data from the least significant bit,
-         *
-         *  0: send data from the most significant bit.
-         */
-        uint32_t tx_lsb_first:1;
-        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
-         *  Configures to control the storage order for received data.
-         *  1: receive data from the least significant bit
-         *
-         *  0: receive data from the most significant bit.
-         */
-        uint32_t rx_lsb_first:1;
-        /** clk_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether to gate clock signal for registers.
-         *
-         *  0: Force clock on for registers
-         *
-         *  1: Support clock only when registers are read or written to by software.
-         */
-        uint32_t clk_en:1;
-        /** arbitration_en : R/W; bitpos: [9]; default: 1;
-         *  Configures to enable I2C bus arbitration detection.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t arbitration_en:1;
-        /** fsm_rst : WT; bitpos: [10]; default: 0;
-         *  Configures to reset the SCL_FSM.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t fsm_rst:1;
-        /** conf_upgate : WT; bitpos: [11]; default: 0;
-         *  Configures this bit for synchronization
-         *  0: No effect
-         *
-         *  1: Synchronize
-         */
-        uint32_t conf_upgate:1;
-        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
-         *  Configures to enable slave to send data automatically
-         *  0: Disable
-         *
-         *  1: Enable
-         */
-        uint32_t slv_tx_auto_start_en:1;
-        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
-         *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
-         *  0: Not check
-         *
-         *  1: Check
-         */
-        uint32_t addr_10bit_rw_check_en:1;
-        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
-         *  Configures to support the 7bit general call function.
-         *  0: Not support
-         *
-         *  1: Support
-         */
-        uint32_t addr_broadcasting_en:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} i2c_ctr_reg_t;
-
-/** Type of to register
- *  Setting time out control for receiving data.
- */
-typedef union {
-    struct {
-        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the timeout threshold period for SCL stucking at high or low level. The
-         *  actual period is 2^(reg_time_out_value).
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t time_out_value:5;
-        /** time_out_en : R/W; bitpos: [5]; default: 0;
-         *  Configures to enable time out control.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t time_out_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} i2c_to_reg_t;
-
-/** Type of slave_addr register
- *  Local slave address setting
- */
-typedef union {
-    struct {
-        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
-         *  Configure the slave address of I2C Slave.
-         */
-        uint32_t slave_addr:15;
-        uint32_t reserved_15:16;
-        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
-         *  Configures to enable the slave 10-bit addressing mode in master mode.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t addr_10bit_en:1;
-    };
-    uint32_t val;
-} i2c_slave_addr_reg_t;
-
-/** Type of fifo_conf register
- *  FIFO configuration register.
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
-         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
-         *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t rxfifo_wm_thrhd:5;
-        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
-         *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
-         *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t txfifo_wm_thrhd:5;
-        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
-         *  Configures to enable APB nonfifo access.
-         */
-        uint32_t nonfifo_en:1;
-        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
-         *  Configures to enable double addressing mode. When this mode is enabled, the byte
-         *  received after the I2C address byte represents the offset address in the I2C Slave
-         *  RAM.
-         *  0: Disable
-         *
-         *  1: Enable
-         */
-        uint32_t fifo_addr_cfg_en:1;
-        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
-         *  Configures to reset RXFIFO.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t rx_fifo_rst:1;
-        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
-         *  Configures to reset TXFIFO.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t tx_fifo_rst:1;
-        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
-         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
-         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t fifo_prt_en:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} i2c_fifo_conf_reg_t;
-
-/** Type of filter_cfg register
- *  SCL and SDA filter configuration register
- */
-typedef union {
-    struct {
-        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
-         *  input has smaller width than this register value, the I2C controller will ignore
-         *  that pulse.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_filter_thres:4;
-        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
-         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
-         *  input has smaller width than this register value, the I2C controller will ignore
-         *  that pulse.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_filter_thres:4;
-        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
-         *  Configures to enable the filter function for SCL.
-         */
-        uint32_t scl_filter_en:1;
-        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
-         *  Configures to enable the filter function for SDA.
-         */
-        uint32_t sda_filter_en:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} i2c_filter_cfg_reg_t;
-
-/** Type of scl_sp_conf register
- *  Power configuration register
- */
-typedef union {
-    struct {
-        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
-         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
-         *  equals to reg_scl_rst_slv_num[4:0].
-         */
-        uint32_t scl_rst_slv_en:1;
-        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
-         *  Configure the pulses of SCL generated in I2C master mode.
-         *  Valid when reg_scl_rst_slv_en is 1.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_rst_slv_num:5;
-        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
-         *  Configures to power down the I2C output SCL line.
-         *  0: Not power down.
-         *
-         *  1: Power down.
-         *  Valid only when reg_scl_force_out is 1.
-         */
-        uint32_t scl_pd_en:1;
-        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
-         *  Configures to power down the I2C output SDA line.
-         *  0: Not power down.
-         *
-         *  1: Power down.
-         *  Valid only when reg_sda_force_out is 1.
-         */
-        uint32_t sda_pd_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} i2c_scl_sp_conf_reg_t;
-
-/** Type of scl_stretch_conf register
- *  Set SCL stretch of I2C slave
- */
-typedef union {
-    struct {
-        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
-         *  Configures the time period to release the SCL line from stretching to avoid timing
-         *  violation. Usually it should be larger than the SDA setup time.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t stretch_protect_num:10;
-        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
-         *  Configures to enable slave SCL stretch function.
-         *  0: Disable
-         *
-         *  1: Enable
-         *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
-         *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
-         */
-        uint32_t slave_scl_stretch_en:1;
-        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
-         *  Configures to clear the I2C slave SCL stretch function.
-         *  0: No effect
-         *
-         *  1: Clear
-         */
-        uint32_t slave_scl_stretch_clr:1;
-        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
-         *  Configures to enable the function for slave to control ACK level.
-         *  0: Disable
-         *
-         *  1: Enable
-         */
-        uint32_t slave_byte_ack_ctl_en:1;
-        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
-         *  Set the ACK level when slave controlling ACK level function enables.
-         *  0: Low level
-         *
-         *  1: High level
-         */
-        uint32_t slave_byte_ack_lvl:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} i2c_scl_stretch_conf_reg_t;
-
-
-/** Group: Status registers */
-/** Type of sr register
- *  Describe I2C work status.
- */
-typedef union {
-    struct {
-        /** resp_rec : RO; bitpos: [0]; default: 0;
-         *  Represents the received ACK value in master mode or slave mode.
-         *  0: ACK,
-         *
-         *  1: NACK.
-         */
-        uint32_t resp_rec:1;
-        /** slave_rw : RO; bitpos: [1]; default: 0;
-         *  Represents the transfer direction in slave mode,.
-         *  1: Master reads from slave,
-         *
-         *  0: Master writes to slave.
-         */
-        uint32_t slave_rw:1;
-        uint32_t reserved_2:1;
-        /** arb_lost : RO; bitpos: [3]; default: 0;
-         *  Represents whether the I2C controller loses control of SCL line.
-         *  0: No arbitration lost
-         *
-         *  1: Arbitration lost
-         */
-        uint32_t arb_lost:1;
-        /** bus_busy : RO; bitpos: [4]; default: 0;
-         *  Represents the I2C bus state.
-         *  1: The I2C bus is busy transferring data,
-         *
-         *  0: The I2C bus is in idle state.
-         */
-        uint32_t bus_busy:1;
-        /** slave_addressed : RO; bitpos: [5]; default: 0;
-         *  Represents whether the address sent by the master is equal to the address of the
-         *  slave.
-         *  Valid only when the module is configured as an I2C Slave.
-         *  0: Not equal
-         *
-         *  1: Equal
-         */
-        uint32_t slave_addressed:1;
-        uint32_t reserved_6:2;
-        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
-         *  Represents the number of data bytes to be sent.
-         */
-        uint32_t rxfifo_cnt:6;
-        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
-         *  Represents the cause of SCL clocking stretching in slave mode.
-         *  0: Stretching SCL low when the master starts to read data.
-         *
-         *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
-         *
-         *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
-         */
-        uint32_t stretch_cause:2;
-        uint32_t reserved_16:2;
-        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
-         *  Represents the number of data bytes received in RAM.
-         */
-        uint32_t txfifo_cnt:6;
-        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
-         *  Represents the states of the I2C module state machine.
-         *  0: Idle,
-         *
-         *  1: Address shift,
-         *
-         *  2: ACK address,
-         *
-         *  3: Rx data,
-         *
-         *  4: Tx data,
-         *
-         *  5: Send ACK,
-         *
-         *  6: Wait ACK
-         */
-        uint32_t scl_main_state_last:3;
-        uint32_t reserved_27:1;
-        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
-         *  Represents the states of the state machine used to produce SCL.
-         *  0: Idle,
-         *
-         *  1: Start,
-         *
-         *  2: Negative edge,
-         *
-         *  3: Low,
-         *
-         *  4: Positive edge,
-         *
-         *  5: High,
-         *
-         *  6: Stop
-         */
-        uint32_t scl_state_last:3;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2c_sr_reg_t;
-
-/** Type of fifo_st register
- *  FIFO status register.
- */
-typedef union {
-    struct {
-        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
-         *  Represents the offset address of the APB reading from RXFIFO
-         */
-        uint32_t rxfifo_raddr:5;
-        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
-         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
-         */
-        uint32_t rxfifo_waddr:5;
-        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
-         *  Represents the offset address of i2c module reading from TXFIFO.
-         */
-        uint32_t txfifo_raddr:5;
-        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
-         *  Represents the offset address of APB bus writing to TXFIFO.
-         */
-        uint32_t txfifo_waddr:5;
-        uint32_t reserved_20:2;
-        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
-         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
-         *  I2C slave mode.
-         */
-        uint32_t slave_rw_point:8;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2c_fifo_st_reg_t;
-
-/** Type of data register
- *  Rx FIFO read data.
- */
-typedef union {
-    struct {
-        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
-         *  Represents the value of RXFIFO read data.
-         */
-        uint32_t fifo_rdata:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} i2c_data_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_raw:1;
-        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
-         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
-         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_raw:1;
-        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
-         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_raw:1;
-        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
-         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_raw:1;
-        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
-         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_raw:1;
-        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
-         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_raw:1;
-        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
-         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_raw:1;
-        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
-         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_raw:1;
-        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
-         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_raw:1;
-        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
-         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_raw:1;
-        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_raw:1;
-        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
-         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_raw:1;
-        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
-         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_raw:1;
-        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
-         *  The raw interrupt status of I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_raw:1;
-        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
-         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_raw:1;
-        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
-         *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_raw:1;
-        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
-         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_raw:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_raw_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_clr:1;
-        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_clr:1;
-        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_clr:1;
-        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_clr:1;
-        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_clr:1;
-        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_clr:1;
-        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_clr:1;
-        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_clr:1;
-        /** nack_int_clr : WT; bitpos: [10]; default: 0;
-         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_clr:1;
-        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_clr:1;
-        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_clr:1;
-        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
-         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_clr:1;
-        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
-         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_clr:1;
-        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  Write 1 to clear I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_clr:1;
-        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
-         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_clr:1;
-        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
-         *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_clr:1;
-        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
-         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_clr:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_clr_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_ena:1;
-        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_ena:1;
-        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_ena:1;
-        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_ena:1;
-        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_ena:1;
-        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_ena:1;
-        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_ena:1;
-        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_ena:1;
-        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_ena:1;
-        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_ena:1;
-        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_ena:1;
-        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_ena:1;
-        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_ena:1;
-        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Write 1 to enable I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_ena:1;
-        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_ena:1;
-        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_ena:1;
-        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
-         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_ena:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_ena_reg_t;
-
-/** Type of int_status register
- *  Status of captured I2C communication events
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_st:1;
-        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_st:1;
-        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_st:1;
-        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_st:1;
-        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_st:1;
-        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_st:1;
-        /** time_out_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_st:1;
-        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_st:1;
-        /** nack_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_st:1;
-        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_st:1;
-        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_st:1;
-        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_st:1;
-        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_st:1;
-        /** det_start_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_st:1;
-        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_st:1;
-        /** general_call_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_st:1;
-        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
-         *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_st:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_status_reg_t;
-
-
-/** Group: Command registers */
-/** Type of comd0 register
- *  I2C command register 0
- */
-typedef union {
-    struct {
-        /** command0 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 0. It consists of three parts:
-         *  op_code is the command,
-         *  0: RSTART,
-         *  1: WRITE,
-         *  2: READ,
-         *  3: STOP,
-         *  4: END.
-         *
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more information.
-         */
-        uint32_t command0:14;
-        uint32_t reserved_14:17;
-        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 0 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command0_done:1;
-    };
-    uint32_t val;
-} i2c_comd0_reg_t;
-
-/** Type of comd1 register
- *  I2C command register 1
- */
-typedef union {
-    struct {
-        /** command1 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 1. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command1:14;
-        uint32_t reserved_14:17;
-        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 1 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command1_done:1;
-    };
-    uint32_t val;
-} i2c_comd1_reg_t;
-
-/** Type of comd2 register
- *  I2C command register 2
- */
-typedef union {
-    struct {
-        /** command2 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 2. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command2:14;
-        uint32_t reserved_14:17;
-        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 2 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command2_done:1;
-    };
-    uint32_t val;
-} i2c_comd2_reg_t;
-
-/** Type of comd3 register
- *  I2C command register 3
- */
-typedef union {
-    struct {
-        /** command3 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 3. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command3:14;
-        uint32_t reserved_14:17;
-        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 3 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command3_done:1;
-    };
-    uint32_t val;
-} i2c_comd3_reg_t;
-
-/** Type of comd4 register
- *  I2C command register 4
- */
-typedef union {
-    struct {
-        /** command4 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 4. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command4:14;
-        uint32_t reserved_14:17;
-        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 4 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command4_done:1;
-    };
-    uint32_t val;
-} i2c_comd4_reg_t;
-
-/** Type of comd5 register
- *  I2C command register 5
- */
-typedef union {
-    struct {
-        /** command5 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 5. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command5:14;
-        uint32_t reserved_14:17;
-        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 5 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command5_done:1;
-    };
-    uint32_t val;
-} i2c_comd5_reg_t;
-
-/** Type of comd6 register
- *  I2C command register 6
- */
-typedef union {
-    struct {
-        /** command6 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 6. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command6:14;
-        uint32_t reserved_14:17;
-        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 6 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command6_done:1;
-    };
-    uint32_t val;
-} i2c_comd6_reg_t;
-
-/** Type of comd7 register
- *  I2C command register 7
- */
-typedef union {
-    struct {
-        /** command7 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 7. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command7:14;
-        uint32_t reserved_14:17;
-        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 7 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command7_done:1;
-    };
-    uint32_t val;
-} i2c_comd7_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35656050;
-         *  Version control register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} i2c_date_reg_t;
-
-
-/** Group: Address register */
-/** Type of txfifo_start_addr register
- *  I2C TXFIFO base address register
- */
-typedef union {
-    struct {
-        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Represents the I2C txfifo first address.
-         */
-        uint32_t txfifo_start_addr:32;
-    };
-    uint32_t val;
-} i2c_txfifo_start_addr_reg_t;
-
-/** Type of rxfifo_start_addr register
- *  I2C RXFIFO base address register
- */
-typedef union {
-    struct {
-        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Represents the I2C rxfifo first address.
-         */
-        uint32_t rxfifo_start_addr:32;
-    };
-    uint32_t val;
-} i2c_rxfifo_start_addr_reg_t;
-
-
-typedef struct {
-    volatile i2c_scl_low_period_reg_t scl_low_period;
-    volatile i2c_ctr_reg_t ctr;
-    volatile i2c_sr_reg_t sr;
-    volatile i2c_to_reg_t to;
-    volatile i2c_slave_addr_reg_t slave_addr;
-    volatile i2c_fifo_st_reg_t fifo_st;
-    volatile i2c_fifo_conf_reg_t fifo_conf;
-    volatile i2c_data_reg_t data;
-    volatile i2c_int_raw_reg_t int_raw;
-    volatile i2c_int_clr_reg_t int_clr;
-    volatile i2c_int_ena_reg_t int_ena;
-    volatile i2c_int_status_reg_t int_status;
-    volatile i2c_sda_hold_reg_t sda_hold;
-    volatile i2c_sda_sample_reg_t sda_sample;
-    volatile i2c_scl_high_period_reg_t scl_high_period;
-    uint32_t reserved_03c;
-    volatile i2c_scl_start_hold_reg_t scl_start_hold;
-    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
-    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
-    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
-    volatile i2c_filter_cfg_reg_t filter_cfg;
-    uint32_t reserved_054;
-    volatile i2c_comd0_reg_t comd0;
-    volatile i2c_comd1_reg_t comd1;
-    volatile i2c_comd2_reg_t comd2;
-    volatile i2c_comd3_reg_t comd3;
-    volatile i2c_comd4_reg_t comd4;
-    volatile i2c_comd5_reg_t comd5;
-    volatile i2c_comd6_reg_t comd6;
-    volatile i2c_comd7_reg_t comd7;
-    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
-    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
-    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
-    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
-    uint32_t reserved_088[28];
-    volatile i2c_date_reg_t date;
-    uint32_t reserved_0fc;
-    volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
-    uint32_t reserved_104[31];
-    volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
-} i2c_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h
index 98a17b234a..ac0b5a9ad3 100644
--- a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h
+++ b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h
@@ -1,1094 +1,1624 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_INTERRUPT_CORE0_REG_H_
-#define _SOC_INTERRUPT_CORE0_REG_H_
-
+#pragma once
 
+#include <stdint.h>
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
-#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
-/* INTERRUPT_CORE0_LP_RTC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_RTC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_RTC_INT_MAP_M  ((INTERRUPT_CORE0_LP_RTC_INT_MAP_V)<<(INTERRUPT_CORE0_LP_RTC_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_RTC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_RTC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
+/** INTERRUPT_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_M  (CORE0_LP_RTC_INT_MAP_V << CORE0_LP_RTC_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_RTC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
-/* INTERRUPT_CORE0_LP_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_WDT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_WDT_INT_MAP_M  ((INTERRUPT_CORE0_LP_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_LP_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_WDT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
+/** INTERRUPT_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_M  (CORE0_LP_WDT_INT_MAP_V << CORE0_LP_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
-/* INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_M  ((INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
+/** INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_M  (CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_LP_TIMER_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC)
-/* INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_M  ((INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
+/** INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_M  (CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_LP_TIMER_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
-/* INTERRUPT_CORE0_MB_HP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_MB_HP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_MB_HP_INT_MAP_M  ((INTERRUPT_CORE0_MB_HP_INT_MAP_V)<<(INTERRUPT_CORE0_MB_HP_INT_MAP_S))
-#define INTERRUPT_CORE0_MB_HP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_MB_HP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
+/** INTERRUPT_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_HP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_M  (CORE0_MB_HP_INT_MAP_V << CORE0_MB_HP_INT_MAP_S)
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_MB_HP_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
-/* INTERRUPT_CORE0_MB_LP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_MB_LP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_MB_LP_INT_MAP_M  ((INTERRUPT_CORE0_MB_LP_INT_MAP_V)<<(INTERRUPT_CORE0_MB_LP_INT_MAP_S))
-#define INTERRUPT_CORE0_MB_LP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_MB_LP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
+/** INTERRUPT_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_LP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_M  (CORE0_MB_LP_INT_MAP_V << CORE0_MB_LP_INT_MAP_S)
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_MB_LP_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
-/* INTERRUPT_CORE0_PMU_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_M  ((INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V)<<(INTERRUPT_CORE0_PMU_REG_0_INT_MAP_S))
-#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
+/** INTERRUPT_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_M  (CORE0_PMU_REG_0_INT_MAP_V << CORE0_PMU_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C)
-/* INTERRUPT_CORE0_PMU_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_M  ((INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V)<<(INTERRUPT_CORE0_PMU_REG_1_INT_MAP_S))
-#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
+/** INTERRUPT_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_M  (CORE0_PMU_REG_1_INT_MAP_V << CORE0_PMU_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
-/* INTERRUPT_CORE0_LP_ANAPERI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_M  ((INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V)<<(INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
+/** INTERRUPT_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_M  (CORE0_LP_ANAPERI_INT_MAP_V << CORE0_LP_ANAPERI_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
-/* INTERRUPT_CORE0_LP_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_ADC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_ADC_INT_MAP_M  ((INTERRUPT_CORE0_LP_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_LP_ADC_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_ADC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
+/** INTERRUPT_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_M  (CORE0_LP_ADC_INT_MAP_V << CORE0_LP_ADC_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_ADC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
-/* INTERRUPT_CORE0_LP_GPIO_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_GPIO_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_M  ((INTERRUPT_CORE0_LP_GPIO_INT_MAP_V)<<(INTERRUPT_CORE0_LP_GPIO_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
+/** INTERRUPT_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_M  (CORE0_LP_GPIO_INT_MAP_V << CORE0_LP_GPIO_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_GPIO_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x2C)
-/* INTERRUPT_CORE0_LP_I2C_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_I2C_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_I2C_INT_MAP_M  ((INTERRUPT_CORE0_LP_I2C_INT_MAP_V)<<(INTERRUPT_CORE0_LP_I2C_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_I2C_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_I2C_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
+/** INTERRUPT_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_M  (CORE0_LP_I2C_INT_MAP_V << CORE0_LP_I2C_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_I2C_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
-/* INTERRUPT_CORE0_LP_I2S_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_I2S_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_I2S_INT_MAP_M  ((INTERRUPT_CORE0_LP_I2S_INT_MAP_V)<<(INTERRUPT_CORE0_LP_I2S_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_I2S_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_I2S_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
+/** INTERRUPT_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_M  (CORE0_LP_I2S_INT_MAP_V << CORE0_LP_I2S_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_I2S_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
-/* INTERRUPT_CORE0_LP_SPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_SPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_SPI_INT_MAP_M  ((INTERRUPT_CORE0_LP_SPI_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SPI_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_SPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_SPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
+/** INTERRUPT_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_M  (CORE0_LP_SPI_INT_MAP_V << CORE0_LP_SPI_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_SPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
-/* INTERRUPT_CORE0_LP_TOUCH_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_M  ((INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TOUCH_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
+/** INTERRUPT_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_M  (CORE0_LP_TOUCH_INT_MAP_V << CORE0_LP_TOUCH_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x3C)
-/* INTERRUPT_CORE0_LP_TSENS_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_TSENS_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_M  ((INTERRUPT_CORE0_LP_TSENS_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TSENS_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
+/** INTERRUPT_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_M  (CORE0_LP_TSENS_INT_MAP_V << CORE0_LP_TSENS_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_TSENS_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
-/* INTERRUPT_CORE0_LP_UART_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_UART_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_UART_INT_MAP_M  ((INTERRUPT_CORE0_LP_UART_INT_MAP_V)<<(INTERRUPT_CORE0_LP_UART_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_UART_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_UART_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
+/** INTERRUPT_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_UART_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_M  (CORE0_LP_UART_INT_MAP_V << CORE0_LP_UART_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_UART_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
-/* INTERRUPT_CORE0_LP_EFUSE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_LP_EFUSE_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
+/** INTERRUPT_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_M  (CORE0_LP_EFUSE_INT_MAP_V << CORE0_LP_EFUSE_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
-/* INTERRUPT_CORE0_LP_SW_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_SW_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_SW_INT_MAP_M  ((INTERRUPT_CORE0_LP_SW_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SW_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_SW_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_SW_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
+/** INTERRUPT_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SW_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_M  (CORE0_LP_SW_INT_MAP_V << CORE0_LP_SW_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_SW_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x4C)
-/* INTERRUPT_CORE0_LP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SYSREG_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
+/** INTERRUPT_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_M  (CORE0_LP_SYSREG_INT_MAP_V << CORE0_LP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
-/* INTERRUPT_CORE0_LP_HUK_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LP_HUK_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LP_HUK_INT_MAP_M  ((INTERRUPT_CORE0_LP_HUK_INT_MAP_V)<<(INTERRUPT_CORE0_LP_HUK_INT_MAP_S))
-#define INTERRUPT_CORE0_LP_HUK_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LP_HUK_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
+/** INTERRUPT_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_M  (CORE0_LP_HUK_INT_MAP_V << CORE0_LP_HUK_INT_MAP_S)
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LP_HUK_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
-/* INTERRUPT_CORE0_SYS_ICM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SYS_ICM_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_M  ((INTERRUPT_CORE0_SYS_ICM_INT_MAP_V)<<(INTERRUPT_CORE0_SYS_ICM_INT_MAP_S))
-#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
+/** INTERRUPT_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_M  (CORE0_SYS_ICM_INT_MAP_V << CORE0_SYS_ICM_INT_MAP_S)
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SYS_ICM_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
-/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M  ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S))
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
+/** INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M  (CORE0_USB_DEVICE_INT_MAP_V << CORE0_USB_DEVICE_INT_MAP_S)
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x5C)
-/* INTERRUPT_CORE0_SDIO_HOST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_M  ((INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V)<<(INTERRUPT_CORE0_SDIO_HOST_INT_MAP_S))
-#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
+/** INTERRUPT_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_M  (CORE0_SDIO_HOST_INT_MAP_V << CORE0_SDIO_HOST_INT_MAP_S)
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_GDMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
-/* INTERRUPT_CORE0_GDMA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_GDMA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_GDMA_INT_MAP_M  ((INTERRUPT_CORE0_GDMA_INT_MAP_V)<<(INTERRUPT_CORE0_GDMA_INT_MAP_S))
-#define INTERRUPT_CORE0_GDMA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_GDMA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
+/** INTERRUPT_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_GDMA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GDMA_INT_MAP_M  (CORE0_GDMA_INT_MAP_V << CORE0_GDMA_INT_MAP_S)
+#define INTERRUPT_CORE0_GDMA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_GDMA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SPI2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
-/* INTERRUPT_CORE0_SPI2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SPI2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SPI2_INT_MAP_M  ((INTERRUPT_CORE0_SPI2_INT_MAP_V)<<(INTERRUPT_CORE0_SPI2_INT_MAP_S))
-#define INTERRUPT_CORE0_SPI2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SPI2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
+/** INTERRUPT_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SPI2_INT_MAP_M  (CORE0_SPI2_INT_MAP_V << CORE0_SPI2_INT_MAP_S)
+#define INTERRUPT_CORE0_SPI2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SPI2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SPI3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
-/* INTERRUPT_CORE0_SPI3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SPI3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SPI3_INT_MAP_M  ((INTERRUPT_CORE0_SPI3_INT_MAP_V)<<(INTERRUPT_CORE0_SPI3_INT_MAP_S))
-#define INTERRUPT_CORE0_SPI3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SPI3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
+/** INTERRUPT_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SPI3_INT_MAP_M  (CORE0_SPI3_INT_MAP_V << CORE0_SPI3_INT_MAP_S)
+#define INTERRUPT_CORE0_SPI3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SPI3_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_I2S0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x6C)
-/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_I2S0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_I2S0_INT_MAP_M  ((INTERRUPT_CORE0_I2S0_INT_MAP_V)<<(INTERRUPT_CORE0_I2S0_INT_MAP_S))
-#define INTERRUPT_CORE0_I2S0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_I2S0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
+/** INTERRUPT_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2S0_INT_MAP_M  (CORE0_I2S0_INT_MAP_V << CORE0_I2S0_INT_MAP_S)
+#define INTERRUPT_CORE0_I2S0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_I2S0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
-/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_I2S1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_I2S1_INT_MAP_M  ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
-#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_I2S1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
+/** INTERRUPT_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2S1_INT_MAP_M  (CORE0_I2S1_INT_MAP_V << CORE0_I2S1_INT_MAP_S)
+#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_I2S1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_I2S2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
-/* INTERRUPT_CORE0_I2S2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_I2S2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_I2S2_INT_MAP_M  ((INTERRUPT_CORE0_I2S2_INT_MAP_V)<<(INTERRUPT_CORE0_I2S2_INT_MAP_S))
-#define INTERRUPT_CORE0_I2S2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_I2S2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
+/** INTERRUPT_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2S2_INT_MAP_M  (CORE0_I2S2_INT_MAP_V << CORE0_I2S2_INT_MAP_S)
+#define INTERRUPT_CORE0_I2S2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_I2S2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
-/* INTERRUPT_CORE0_UHCI0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_UHCI0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_UHCI0_INT_MAP_M  ((INTERRUPT_CORE0_UHCI0_INT_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INT_MAP_S))
-#define INTERRUPT_CORE0_UHCI0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_UHCI0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
+/** INTERRUPT_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_UHCI0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_M  (CORE0_UHCI0_INT_MAP_V << CORE0_UHCI0_INT_MAP_S)
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_UHCI0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_UART0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7C)
-/* INTERRUPT_CORE0_UART0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_UART0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_UART0_INT_MAP_M  ((INTERRUPT_CORE0_UART0_INT_MAP_V)<<(INTERRUPT_CORE0_UART0_INT_MAP_S))
-#define INTERRUPT_CORE0_UART0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_UART0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
+/** INTERRUPT_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART0_INT_MAP_M  (CORE0_UART0_INT_MAP_V << CORE0_UART0_INT_MAP_S)
+#define INTERRUPT_CORE0_UART0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_UART0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_UART1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
-/* INTERRUPT_CORE0_UART1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_UART1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_UART1_INT_MAP_M  ((INTERRUPT_CORE0_UART1_INT_MAP_V)<<(INTERRUPT_CORE0_UART1_INT_MAP_S))
-#define INTERRUPT_CORE0_UART1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_UART1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
+/** INTERRUPT_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART1_INT_MAP_M  (CORE0_UART1_INT_MAP_V << CORE0_UART1_INT_MAP_S)
+#define INTERRUPT_CORE0_UART1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_UART1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_UART2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
-/* INTERRUPT_CORE0_UART2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_UART2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_UART2_INT_MAP_M  ((INTERRUPT_CORE0_UART2_INT_MAP_V)<<(INTERRUPT_CORE0_UART2_INT_MAP_S))
-#define INTERRUPT_CORE0_UART2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_UART2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
+/** INTERRUPT_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART2_INT_MAP_M  (CORE0_UART2_INT_MAP_V << CORE0_UART2_INT_MAP_S)
+#define INTERRUPT_CORE0_UART2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_UART2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_UART3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
-/* INTERRUPT_CORE0_UART3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_UART3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_UART3_INT_MAP_M  ((INTERRUPT_CORE0_UART3_INT_MAP_V)<<(INTERRUPT_CORE0_UART3_INT_MAP_S))
-#define INTERRUPT_CORE0_UART3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_UART3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
+/** INTERRUPT_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART3_INT_MAP_M  (CORE0_UART3_INT_MAP_V << CORE0_UART3_INT_MAP_S)
+#define INTERRUPT_CORE0_UART3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_UART3_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_UART4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x8C)
-/* INTERRUPT_CORE0_UART4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_UART4_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_UART4_INT_MAP_M  ((INTERRUPT_CORE0_UART4_INT_MAP_V)<<(INTERRUPT_CORE0_UART4_INT_MAP_S))
-#define INTERRUPT_CORE0_UART4_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_UART4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
+/** INTERRUPT_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART4_INT_MAP_M  (CORE0_UART4_INT_MAP_V << CORE0_UART4_INT_MAP_S)
+#define INTERRUPT_CORE0_UART4_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_UART4_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
-/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M  ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE0_LCD_CAM_INT_MAP_S))
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
+/** INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M  (CORE0_LCD_CAM_INT_MAP_V << CORE0_LCD_CAM_INT_MAP_S)
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
-/* INTERRUPT_CORE0_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_ADC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_ADC_INT_MAP_M  ((INTERRUPT_CORE0_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_ADC_INT_MAP_S))
-#define INTERRUPT_CORE0_ADC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
+/** INTERRUPT_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ADC_INT_MAP_M  (CORE0_ADC_INT_MAP_V << CORE0_ADC_INT_MAP_S)
+#define INTERRUPT_CORE0_ADC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_ADC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PWM0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
-/* INTERRUPT_CORE0_PWM0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PWM0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PWM0_INT_MAP_M  ((INTERRUPT_CORE0_PWM0_INT_MAP_V)<<(INTERRUPT_CORE0_PWM0_INT_MAP_S))
-#define INTERRUPT_CORE0_PWM0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PWM0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
+/** INTERRUPT_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PWM0_INT_MAP_M  (CORE0_PWM0_INT_MAP_V << CORE0_PWM0_INT_MAP_S)
+#define INTERRUPT_CORE0_PWM0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PWM0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PWM1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x9C)
-/* INTERRUPT_CORE0_PWM1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PWM1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PWM1_INT_MAP_M  ((INTERRUPT_CORE0_PWM1_INT_MAP_V)<<(INTERRUPT_CORE0_PWM1_INT_MAP_S))
-#define INTERRUPT_CORE0_PWM1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PWM1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
+/** INTERRUPT_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PWM1_INT_MAP_M  (CORE0_PWM1_INT_MAP_V << CORE0_PWM1_INT_MAP_S)
+#define INTERRUPT_CORE0_PWM1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PWM1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CAN0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA0)
-/* INTERRUPT_CORE0_CAN0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CAN0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_CAN0_INT_MAP_M  ((INTERRUPT_CORE0_CAN0_INT_MAP_V)<<(INTERRUPT_CORE0_CAN0_INT_MAP_S))
-#define INTERRUPT_CORE0_CAN0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_CAN0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
+/** INTERRUPT_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CAN0_INT_MAP_M  (CORE0_CAN0_INT_MAP_V << CORE0_CAN0_INT_MAP_S)
+#define INTERRUPT_CORE0_CAN0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CAN0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CAN1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA4)
-/* INTERRUPT_CORE0_CAN1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CAN1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_CAN1_INT_MAP_M  ((INTERRUPT_CORE0_CAN1_INT_MAP_V)<<(INTERRUPT_CORE0_CAN1_INT_MAP_S))
-#define INTERRUPT_CORE0_CAN1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_CAN1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
+/** INTERRUPT_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CAN1_INT_MAP_M  (CORE0_CAN1_INT_MAP_V << CORE0_CAN1_INT_MAP_S)
+#define INTERRUPT_CORE0_CAN1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CAN1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CAN2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA8)
-/* INTERRUPT_CORE0_CAN2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CAN2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_CAN2_INT_MAP_M  ((INTERRUPT_CORE0_CAN2_INT_MAP_V)<<(INTERRUPT_CORE0_CAN2_INT_MAP_S))
-#define INTERRUPT_CORE0_CAN2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_CAN2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
+/** INTERRUPT_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CAN2_INT_MAP_M  (CORE0_CAN2_INT_MAP_V << CORE0_CAN2_INT_MAP_S)
+#define INTERRUPT_CORE0_CAN2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CAN2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_RMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xAC)
-/* INTERRUPT_CORE0_RMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_RMT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_RMT_INT_MAP_M  ((INTERRUPT_CORE0_RMT_INT_MAP_V)<<(INTERRUPT_CORE0_RMT_INT_MAP_S))
-#define INTERRUPT_CORE0_RMT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_RMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
+/** INTERRUPT_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_RMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_RMT_INT_MAP_M  (CORE0_RMT_INT_MAP_V << CORE0_RMT_INT_MAP_S)
+#define INTERRUPT_CORE0_RMT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_RMT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_I2C0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB0)
-/* INTERRUPT_CORE0_I2C0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_I2C0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_I2C0_INT_MAP_M  ((INTERRUPT_CORE0_I2C0_INT_MAP_V)<<(INTERRUPT_CORE0_I2C0_INT_MAP_S))
-#define INTERRUPT_CORE0_I2C0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_I2C0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
+/** INTERRUPT_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2C0_INT_MAP_M  (CORE0_I2C0_INT_MAP_V << CORE0_I2C0_INT_MAP_S)
+#define INTERRUPT_CORE0_I2C0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_I2C0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_I2C1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB4)
-/* INTERRUPT_CORE0_I2C1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_I2C1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_I2C1_INT_MAP_M  ((INTERRUPT_CORE0_I2C1_INT_MAP_V)<<(INTERRUPT_CORE0_I2C1_INT_MAP_S))
-#define INTERRUPT_CORE0_I2C1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_I2C1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
+/** INTERRUPT_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2C1_INT_MAP_M  (CORE0_I2C1_INT_MAP_V << CORE0_I2C1_INT_MAP_S)
+#define INTERRUPT_CORE0_I2C1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_I2C1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB8)
-/* INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
+/** INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_M  (CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_TIMERGRP0_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xBC)
-/* INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_S))
-#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
+/** INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_M  (CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_TIMERGRP0_T1_INT_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC0)
-/* INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
+/** INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_M  (CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_TIMERGRP0_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC4)
-/* INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
+/** INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_M  (CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_TIMERGRP1_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC8)
-/* INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_S))
-#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
+/** INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_M  (CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_TIMERGRP1_T1_INT_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xCC)
-/* INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
+/** INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_M  (CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_TIMERGRP1_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD0)
-/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LEDC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
-#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LEDC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
+/** INTERRUPT_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LEDC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LEDC_INT_MAP_M  (CORE0_LEDC_INT_MAP_V << CORE0_LEDC_INT_MAP_S)
+#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD4)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  (CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_SYSTIMER_TARGET0_INT_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD8)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  (CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_SYSTIMER_TARGET1_INT_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xDC)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  (CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_SYSTIMER_TARGET2_INT_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE0)
-/* INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M  (CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_AHB_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE4)
-/* INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M  (CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_AHB_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE8)
-/* INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M  (CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_AHB_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xEC)
-/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M  (CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF0)
-/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M  (CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF4)
-/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M  (CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF8)
-/* INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M  (CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_AXI_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xFC)
-/* INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M  (CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_AXI_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
-/* INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M  (CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_AXI_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
-/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M  (CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
-/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M  (CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
-/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M  (CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
-/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_RSA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
-#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_RSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/** INTERRUPT_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_RSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_RSA_INT_MAP_M  (CORE0_RSA_INT_MAP_V << CORE0_RSA_INT_MAP_S)
+#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_RSA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
-/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_AES_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
-#define INTERRUPT_CORE0_AES_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_AES_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/** INTERRUPT_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_AES_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AES_INT_MAP_M  (CORE0_AES_INT_MAP_V << CORE0_AES_INT_MAP_S)
+#define INTERRUPT_CORE0_AES_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_AES_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
-/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SHA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
-#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SHA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/** INTERRUPT_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SHA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SHA_INT_MAP_M  (CORE0_SHA_INT_MAP_V << CORE0_SHA_INT_MAP_S)
+#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SHA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ECC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
-/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_ECC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_ECC_INT_MAP_M  ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S))
-#define INTERRUPT_CORE0_ECC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_ECC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
+/** INTERRUPT_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ECC_INT_MAP_M  (CORE0_ECC_INT_MAP_V << CORE0_ECC_INT_MAP_S)
+#define INTERRUPT_CORE0_ECC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_ECC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
-/* INTERRUPT_CORE0_ECDSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_ECDSA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_ECDSA_INT_MAP_M  ((INTERRUPT_CORE0_ECDSA_INT_MAP_V)<<(INTERRUPT_CORE0_ECDSA_INT_MAP_S))
-#define INTERRUPT_CORE0_ECDSA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_ECDSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/** INTERRUPT_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECDSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_M  (CORE0_ECDSA_INT_MAP_V << CORE0_ECDSA_INT_MAP_S)
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_ECDSA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_KM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
-/* INTERRUPT_CORE0_KM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_KM_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_KM_INT_MAP_M  ((INTERRUPT_CORE0_KM_INT_MAP_V)<<(INTERRUPT_CORE0_KM_INT_MAP_S))
-#define INTERRUPT_CORE0_KM_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_KM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/** INTERRUPT_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_KM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_KM_INT_MAP_M  (CORE0_KM_INT_MAP_V << CORE0_KM_INT_MAP_S)
+#define INTERRUPT_CORE0_KM_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_KM_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
-/* INTERRUPT_CORE0_GPIO_INT0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_GPIO_INT0_MAP    0x0000003F
-#define INTERRUPT_CORE0_GPIO_INT0_MAP_M  ((INTERRUPT_CORE0_GPIO_INT0_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT0_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INT0_MAP_V  0x3F
+/** INTERRUPT_CORE0_GPIO_INT0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/** INTERRUPT_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_M  (CORE0_GPIO_INT0_MAP_V << CORE0_GPIO_INT0_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_GPIO_INT0_MAP_S  0
 
-#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
-/* INTERRUPT_CORE0_GPIO_INT1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_GPIO_INT1_MAP    0x0000003F
-#define INTERRUPT_CORE0_GPIO_INT1_MAP_M  ((INTERRUPT_CORE0_GPIO_INT1_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT1_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INT1_MAP_V  0x3F
+/** INTERRUPT_CORE0_GPIO_INT1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
+/** INTERRUPT_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_M  (CORE0_GPIO_INT1_MAP_V << CORE0_GPIO_INT1_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_GPIO_INT1_MAP_S  0
 
-#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
-/* INTERRUPT_CORE0_GPIO_INT2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_GPIO_INT2_MAP    0x0000003F
-#define INTERRUPT_CORE0_GPIO_INT2_MAP_M  ((INTERRUPT_CORE0_GPIO_INT2_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT2_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INT2_MAP_V  0x3F
+/** INTERRUPT_CORE0_GPIO_INT2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/** INTERRUPT_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_M  (CORE0_GPIO_INT2_MAP_V << CORE0_GPIO_INT2_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_GPIO_INT2_MAP_S  0
 
-#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
-/* INTERRUPT_CORE0_GPIO_INT3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_GPIO_INT3_MAP    0x0000003F
-#define INTERRUPT_CORE0_GPIO_INT3_MAP_M  ((INTERRUPT_CORE0_GPIO_INT3_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT3_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INT3_MAP_V  0x3F
+/** INTERRUPT_CORE0_GPIO_INT3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/** INTERRUPT_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_M  (CORE0_GPIO_INT3_MAP_V << CORE0_GPIO_INT3_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_GPIO_INT3_MAP_S  0
 
-#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
-/* INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_M  ((INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V)<<(INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_S))
-#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/** INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_M  (CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_GPIO_PAD_COMP_INT_MAP_S)
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
-/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP    0x0000003F
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_S))
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V  0x3F
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_M  (CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CPU_INT_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
-/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP    0x0000003F
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_S))
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V  0x3F
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_M  (CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CPU_INT_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
-/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP    0x0000003F
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_S))
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V  0x3F
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_M  (CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CPU_INT_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
-/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP    0x0000003F
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_S))
-#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V  0x3F
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_M  (CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CPU_INT_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_S  0
 
-#define INTERRUPT_CORE0_CACHE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
-/* INTERRUPT_CORE0_CACHE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CACHE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_CACHE_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_CACHE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
+/** INTERRUPT_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CACHE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CACHE_INT_MAP_M  (CORE0_CACHE_INT_MAP_V << CORE0_CACHE_INT_MAP_S)
+#define INTERRUPT_CORE0_CACHE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CACHE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
-/* INTERRUPT_CORE0_FLASH_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_M  ((INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V)<<(INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_S))
-#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/** INTERRUPT_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_M  (CORE0_FLASH_MSPI_INT_MAP_V << CORE0_FLASH_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
-/* INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_S))
-#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/** INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_M  (CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
-/* INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_S))
-#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/** INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_M  (CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_DSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
-/* INTERRUPT_CORE0_CSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CSI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_CSI_INT_MAP_M  ((INTERRUPT_CORE0_CSI_INT_MAP_V)<<(INTERRUPT_CORE0_CSI_INT_MAP_S))
-#define INTERRUPT_CORE0_CSI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_CSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c)
+/** INTERRUPT_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CSI_INT_MAP_M  (CORE0_CSI_INT_MAP_V << CORE0_CSI_INT_MAP_S)
+#define INTERRUPT_CORE0_CSI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CSI_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
-/* INTERRUPT_CORE0_DSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_DSI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_DSI_INT_MAP_M  ((INTERRUPT_CORE0_DSI_INT_MAP_V)<<(INTERRUPT_CORE0_DSI_INT_MAP_S))
-#define INTERRUPT_CORE0_DSI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_DSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/** INTERRUPT_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DSI_INT_MAP_M  (CORE0_DSI_INT_MAP_V << CORE0_DSI_INT_MAP_S)
+#define INTERRUPT_CORE0_DSI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_DSI_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
-/* INTERRUPT_CORE0_GMII_PHY_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_GMII_PHY_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_M  ((INTERRUPT_CORE0_GMII_PHY_INT_MAP_V)<<(INTERRUPT_CORE0_GMII_PHY_INT_MAP_S))
-#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/** INTERRUPT_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_M  (CORE0_GMII_PHY_INT_MAP_V << CORE0_GMII_PHY_INT_MAP_S)
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_GMII_PHY_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_LPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
-/* INTERRUPT_CORE0_LPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_LPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_LPI_INT_MAP_M  ((INTERRUPT_CORE0_LPI_INT_MAP_V)<<(INTERRUPT_CORE0_LPI_INT_MAP_S))
-#define INTERRUPT_CORE0_LPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_LPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/** INTERRUPT_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_LPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LPI_INT_MAP_M  (CORE0_LPI_INT_MAP_V << CORE0_LPI_INT_MAP_S)
+#define INTERRUPT_CORE0_LPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_LPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
-/* INTERRUPT_CORE0_PMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PMT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PMT_INT_MAP_M  ((INTERRUPT_CORE0_PMT_INT_MAP_V)<<(INTERRUPT_CORE0_PMT_INT_MAP_S))
-#define INTERRUPT_CORE0_PMT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c)
+/** INTERRUPT_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PMT_INT_MAP_M  (CORE0_PMT_INT_MAP_V << CORE0_PMT_INT_MAP_S)
+#define INTERRUPT_CORE0_PMT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PMT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SBD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
-/* INTERRUPT_CORE0_SBD_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_SBD_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_SBD_INT_MAP_M  ((INTERRUPT_CORE0_SBD_INT_MAP_V)<<(INTERRUPT_CORE0_SBD_INT_MAP_S))
-#define INTERRUPT_CORE0_SBD_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_SBD_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/** INTERRUPT_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_SBD_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SBD_INT_MAP_M  (CORE0_SBD_INT_MAP_V << CORE0_SBD_INT_MAP_S)
+#define INTERRUPT_CORE0_SBD_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_SBD_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
-/* INTERRUPT_CORE0_USB_OTG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_USB_OTG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_USB_OTG_INT_MAP_M  ((INTERRUPT_CORE0_USB_OTG_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG_INT_MAP_S))
-#define INTERRUPT_CORE0_USB_OTG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_USB_OTG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/** INTERRUPT_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_M  (CORE0_USB_OTG_INT_MAP_V << CORE0_USB_OTG_INT_MAP_S)
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_USB_OTG_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
-/* INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  ((INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S))
-#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/** INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  (CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_JPEG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
-/* INTERRUPT_CORE0_JPEG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_JPEG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_JPEG_INT_MAP_M  ((INTERRUPT_CORE0_JPEG_INT_MAP_V)<<(INTERRUPT_CORE0_JPEG_INT_MAP_S))
-#define INTERRUPT_CORE0_JPEG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_JPEG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c)
+/** INTERRUPT_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_JPEG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_JPEG_INT_MAP_M  (CORE0_JPEG_INT_MAP_V << CORE0_JPEG_INT_MAP_S)
+#define INTERRUPT_CORE0_JPEG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_JPEG_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PPA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
-/* INTERRUPT_CORE0_PPA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PPA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PPA_INT_MAP_M  ((INTERRUPT_CORE0_PPA_INT_MAP_V)<<(INTERRUPT_CORE0_PPA_INT_MAP_S))
-#define INTERRUPT_CORE0_PPA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PPA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/** INTERRUPT_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PPA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PPA_INT_MAP_M  (CORE0_PPA_INT_MAP_V << CORE0_PPA_INT_MAP_S)
+#define INTERRUPT_CORE0_PPA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PPA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
-/* INTERRUPT_CORE0_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_TRACE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_TRACE_INT_MAP_M  ((INTERRUPT_CORE0_TRACE_INT_MAP_V)<<(INTERRUPT_CORE0_TRACE_INT_MAP_S))
-#define INTERRUPT_CORE0_TRACE_INT_MAP_V  0x3F
-#define INTERRUPT_CORE0_TRACE_INT_MAP_S  0
+/** INTERRUPT_CORE0_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/** INTERRUPT_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_M  (CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
-/* INTERRUPT_CORE0_CORE1_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_M  ((INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V)<<(INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_S))
-#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/** INTERRUPT_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_M  (CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE1_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
-/* INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_M  ((INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V)<<(INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_S))
-#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c)
+/** INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_M  (CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_HP_CORE_CTRL_INT_MAP_S)
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ISP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
-/* INTERRUPT_CORE0_ISP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_ISP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_ISP_INT_MAP_M  ((INTERRUPT_CORE0_ISP_INT_MAP_V)<<(INTERRUPT_CORE0_ISP_INT_MAP_S))
-#define INTERRUPT_CORE0_ISP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_ISP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/** INTERRUPT_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_ISP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ISP_INT_MAP_M  (CORE0_ISP_INT_MAP_V << CORE0_ISP_INT_MAP_S)
+#define INTERRUPT_CORE0_ISP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_ISP_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
-/* INTERRUPT_CORE0_I3C_MST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_I3C_MST_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_I3C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I3C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I3C_MST_INT_MAP_S))
-#define INTERRUPT_CORE0_I3C_MST_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_I3C_MST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/** INTERRUPT_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_M  (CORE0_I3C_MST_INT_MAP_V << CORE0_I3C_MST_INT_MAP_S)
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_I3C_MST_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
-/* INTERRUPT_CORE0_I3C_SLV_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_I3C_SLV_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_M  ((INTERRUPT_CORE0_I3C_SLV_INT_MAP_V)<<(INTERRUPT_CORE0_I3C_SLV_INT_MAP_S))
-#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
+/** INTERRUPT_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_M  (CORE0_I3C_SLV_INT_MAP_V << CORE0_I3C_SLV_INT_MAP_S)
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_I3C_SLV_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x19C)
-/* INTERRUPT_CORE0_USB_OTG11_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_USB_OTG11_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_M  ((INTERRUPT_CORE0_USB_OTG11_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG11_INT_MAP_S))
-#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
+/** INTERRUPT_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_M  (CORE0_USB_OTG11_INT_MAP_V << CORE0_USB_OTG11_INT_MAP_S)
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_USB_OTG11_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0)
-/* INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0)
+/** INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_M  (CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4)
-/* INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4)
+/** INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_M  (CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8)
-/* INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8)
+/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC)
-/* INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac)
+/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0)
-/* INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0)
+/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4)
-/* INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_M  ((INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V)<<(INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_S))
-#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b4)
+/** INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_M  (CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_PSRAM_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B8)
-/* INTERRUPT_CORE0_HP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE0_HP_SYSREG_INT_MAP_S))
-#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b8)
+/** INTERRUPT_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_M  (CORE0_HP_SYSREG_INT_MAP_V << CORE0_HP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_PCNT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1BC)
-/* INTERRUPT_CORE0_PCNT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_PCNT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_PCNT_INT_MAP_M  ((INTERRUPT_CORE0_PCNT_INT_MAP_V)<<(INTERRUPT_CORE0_PCNT_INT_MAP_S))
-#define INTERRUPT_CORE0_PCNT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_PCNT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1bc)
+/** INTERRUPT_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_PCNT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PCNT_INT_MAP_M  (CORE0_PCNT_INT_MAP_V << CORE0_PCNT_INT_MAP_S)
+#define INTERRUPT_CORE0_PCNT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_PCNT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C0)
-/* INTERRUPT_CORE0_HP_PAU_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_HP_PAU_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_HP_PAU_INT_MAP_M  ((INTERRUPT_CORE0_HP_PAU_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PAU_INT_MAP_S))
-#define INTERRUPT_CORE0_HP_PAU_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_HP_PAU_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c0)
+/** INTERRUPT_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_M  (CORE0_HP_PAU_INT_MAP_V << CORE0_HP_PAU_INT_MAP_S)
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_HP_PAU_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C4)
-/* INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_M  ((INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_S))
-#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c4)
+/** INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_M  (CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_HP_PARLIO_RX_INT_MAP_S)
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C8)
-/* INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_M  ((INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_S))
-#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c8)
+/** INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_M  (CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_HP_PARLIO_TX_INT_MAP_S)
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1CC)
-/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1cc)
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1D0)
-/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d0)
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1D4)
-/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d4)
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1D8)
-/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d8)
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M  (CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1DC)
-/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1dc)
+/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M  (CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1E0)
-/* INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e0)
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M  (CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_H264_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1E4)
-/* INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e4)
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M  (CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_H264_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1E8)
-/* INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e8)
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M  (CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_H264_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1EC)
-/* INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ec)
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M  (CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_H264_DMA2D_IN_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1F0)
-/* INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f0)
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M  (CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_H264_DMA2D_IN_CH4_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1F4)
-/* INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M  ((INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f4)
+/** INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M  (CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_H264_DMA2D_IN_CH5_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1F8)
-/* INTERRUPT_CORE0_H264_REG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_H264_REG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_H264_REG_INT_MAP_M  ((INTERRUPT_CORE0_H264_REG_INT_MAP_V)<<(INTERRUPT_CORE0_H264_REG_INT_MAP_S))
-#define INTERRUPT_CORE0_H264_REG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_H264_REG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f8)
+/** INTERRUPT_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_REG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_M  (CORE0_H264_REG_INT_MAP_V << CORE0_H264_REG_INT_MAP_S)
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_H264_REG_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1FC)
-/* INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_S))
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1fc)
+/** INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_M  (CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_ASSIST_DEBUG_INT_MAP_S)
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x200)
-/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_INTR_STATUS_0    0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
-#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_INTR_STATUS_REG_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200)
+/** INTERRUPT_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INTR_STATUS_0_M  (CORE0_INTR_STATUS_0_V << CORE0_INTR_STATUS_0_S)
+#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_INTR_STATUS_0_S  0
 
-#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x204)
-/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_INTR_STATUS_1    0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
-#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_INTR_STATUS_REG_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204)
+/** INTERRUPT_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INTR_STATUS_1_M  (CORE0_INTR_STATUS_1_V << CORE0_INTR_STATUS_1_S)
+#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_INTR_STATUS_1_S  0
 
-#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x208)
-/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_INTR_STATUS_2    0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_2_M  ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
-#define INTERRUPT_CORE0_INTR_STATUS_2_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_INTR_STATUS_REG_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208)
+/** INTERRUPT_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INTR_STATUS_2_M  (CORE0_INTR_STATUS_2_V << CORE0_INTR_STATUS_2_S)
+#define INTERRUPT_CORE0_INTR_STATUS_2_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_INTR_STATUS_2_S  0
 
-#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x20C)
-/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_INTR_STATUS_3    0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_3_M  ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S))
-#define INTERRUPT_CORE0_INTR_STATUS_3_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_INTR_STATUS_REG_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20c)
+/** INTERRUPT_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INTR_STATUS_3_M  (CORE0_INTR_STATUS_3_V << CORE0_INTR_STATUS_3_S)
+#define INTERRUPT_CORE0_INTR_STATUS_3_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_INTR_STATUS_3_S  0
 
-#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x210)
-/* INTERRUPT_CORE0_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
+/** INTERRUPT_CORE0_CLOCK_GATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210)
+/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
 #define INTERRUPT_CORE0_REG_CLK_EN    (BIT(0))
-#define INTERRUPT_CORE0_REG_CLK_EN_M  (BIT(0))
-#define INTERRUPT_CORE0_REG_CLK_EN_V  0x1
+#define INTERRUPT_CORE0_REG_CLK_EN_M  (CORE0_REG_CLK_EN_V << CORE0_REG_CLK_EN_S)
+#define INTERRUPT_CORE0_REG_CLK_EN_V  0x00000001U
 #define INTERRUPT_CORE0_REG_CLK_EN_S  0
 
-#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x3FC)
-/* INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
-/*description: .*/
-#define INTERRUPT_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFF
-#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_REG_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_REG_DATE_S))
-#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V  0xFFFFFFF
+/** INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3fc)
+/** INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752;
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M  (CORE0_INTERRUPT_REG_DATE_V << CORE0_INTERRUPT_REG_DATE_S)
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
 #define INTERRUPT_CORE0_INTERRUPT_REG_DATE_S  0
 
-
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_struct.h b/components/soc/esp32p4/include/soc/interrupt_core0_struct.h
new file mode 100644
index 0000000000..2b5ba97fb8
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/interrupt_core0_struct.h
@@ -0,0 +1,2298 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: INTERRUPT_CORE0_LP RTC INT MAP REG */
+/** Type of lp_rtc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_rtc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_rtc_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP WDT INT MAP REG */
+/** Type of lp_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_wdt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_wdt_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP TIMER REG 0 INT MAP REG */
+/** Type of lp_timer_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_timer_reg_0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_timer_reg_0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP TIMER REG 1 INT MAP REG */
+/** Type of lp_timer_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_timer_reg_1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_timer_reg_1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_MB HP INT MAP REG */
+/** Type of mb_hp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_mb_hp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_mb_hp_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_MB LP INT MAP REG */
+/** Type of mb_lp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_mb_lp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_mb_lp_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PMU REG 0 INT MAP REG */
+/** Type of pmu_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_pmu_reg_0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_pmu_reg_0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PMU REG 1 INT MAP REG */
+/** Type of pmu_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_pmu_reg_1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_pmu_reg_1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP ANAPERI INT MAP REG */
+/** Type of lp_anaperi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_anaperi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_anaperi_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP ADC INT MAP REG */
+/** Type of lp_adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_adc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_adc_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP GPIO INT MAP REG */
+/** Type of lp_gpio_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_gpio_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_gpio_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP I2C INT MAP REG */
+/** Type of lp_i2c_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_i2c_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_i2c_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP I2S INT MAP REG */
+/** Type of lp_i2s_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_i2s_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_i2s_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP SPI INT MAP REG */
+/** Type of lp_spi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_spi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_spi_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP TOUCH INT MAP REG */
+/** Type of lp_touch_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_touch_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_touch_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP TSENS INT MAP REG */
+/** Type of lp_tsens_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_tsens_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_tsens_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP UART INT MAP REG */
+/** Type of lp_uart_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_uart_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_uart_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP EFUSE INT MAP REG */
+/** Type of lp_efuse_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_efuse_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_efuse_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP SW INT MAP REG */
+/** Type of lp_sw_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_sw_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_sw_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP SYSREG INT MAP REG */
+/** Type of lp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_sysreg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_sysreg_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LP HUK INT MAP REG */
+/** Type of lp_huk_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lp_huk_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lp_huk_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SYS ICM INT MAP REG */
+/** Type of sys_icm_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_sys_icm_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_sys_icm_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_USB DEVICE INT MAP REG */
+/** Type of usb_device_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_usb_device_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_usb_device_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SDIO HOST INT MAP REG */
+/** Type of sdio_host_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_sdio_host_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_sdio_host_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_GDMA INT MAP REG */
+/** Type of gdma_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_gdma_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_gdma_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SPI2 INT MAP REG */
+/** Type of spi2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_spi2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_spi2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SPI3 INT MAP REG */
+/** Type of spi3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_spi3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_spi3_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_I2S0 INT MAP REG */
+/** Type of i2s0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_i2s0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_i2s0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_I2S1 INT MAP REG */
+/** Type of i2s1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_i2s1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_i2s1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_I2S2 INT MAP REG */
+/** Type of i2s2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_i2s2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_i2s2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_UHCI0 INT MAP REG */
+/** Type of uhci0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_uhci0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_uhci0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_UART0 INT MAP REG */
+/** Type of uart0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_uart0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_uart0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_UART1 INT MAP REG */
+/** Type of uart1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_uart1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_uart1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_UART2 INT MAP REG */
+/** Type of uart2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_uart2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_uart2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_UART3 INT MAP REG */
+/** Type of uart3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_uart3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_uart3_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_UART4 INT MAP REG */
+/** Type of uart4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_uart4_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_uart4_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LCD CAM INT MAP REG */
+/** Type of lcd_cam_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lcd_cam_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lcd_cam_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_ADC INT MAP REG */
+/** Type of adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_adc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_adc_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PWM0 INT MAP REG */
+/** Type of pwm0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_pwm0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_pwm0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PWM1 INT MAP REG */
+/** Type of pwm1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_pwm1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_pwm1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CAN0 INT MAP REG */
+/** Type of can0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_can0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_can0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_can0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CAN1 INT MAP REG */
+/** Type of can1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_can1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_can1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_can1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CAN2 INT MAP REG */
+/** Type of can2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_can2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_can2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_can2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_RMT INT MAP REG */
+/** Type of rmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_rmt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_rmt_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_I2C0 INT MAP REG */
+/** Type of i2c0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_i2c0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_i2c0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_I2C1 INT MAP REG */
+/** Type of i2c1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_i2c1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_i2c1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_TIMERGRP0 T0 INT MAP REG */
+/** Type of timergrp0_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_timergrp0_t0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp0_t0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_TIMERGRP0 T1 INT MAP REG */
+/** Type of timergrp0_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_timergrp0_t1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp0_t1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_TIMERGRP0 WDT INT MAP REG */
+/** Type of timergrp0_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_timergrp0_wdt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp0_wdt_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_TIMERGRP1 T0 INT MAP REG */
+/** Type of timergrp1_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_timergrp1_t0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp1_t0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_TIMERGRP1 T1 INT MAP REG */
+/** Type of timergrp1_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_timergrp1_t1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp1_t1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_TIMERGRP1 WDT INT MAP REG */
+/** Type of timergrp1_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_timergrp1_wdt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp1_wdt_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LEDC INT MAP REG */
+/** Type of ledc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ledc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ledc_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SYSTIMER TARGET0 INT MAP REG */
+/** Type of systimer_target0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_systimer_target0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_systimer_target0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SYSTIMER TARGET1 INT MAP REG */
+/** Type of systimer_target1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_systimer_target1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_systimer_target1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SYSTIMER TARGET2 INT MAP REG */
+/** Type of systimer_target2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_systimer_target2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_systimer_target2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AHB PDMA IN CH0 INT MAP REG */
+/** Type of ahb_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ahb_pdma_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AHB PDMA IN CH1 INT MAP REG */
+/** Type of ahb_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ahb_pdma_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AHB PDMA IN CH2 INT MAP REG */
+/** Type of ahb_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ahb_pdma_in_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH0 INT MAP REG */
+/** Type of ahb_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ahb_pdma_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH1 INT MAP REG */
+/** Type of ahb_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ahb_pdma_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH2 INT MAP REG */
+/** Type of ahb_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ahb_pdma_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AXI PDMA IN CH0 INT MAP REG */
+/** Type of axi_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_axi_pdma_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AXI PDMA IN CH1 INT MAP REG */
+/** Type of axi_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_axi_pdma_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AXI PDMA IN CH2 INT MAP REG */
+/** Type of axi_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_axi_pdma_in_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH0 INT MAP REG */
+/** Type of axi_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_axi_pdma_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH1 INT MAP REG */
+/** Type of axi_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_axi_pdma_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH2 INT MAP REG */
+/** Type of axi_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_axi_pdma_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_RSA INT MAP REG */
+/** Type of rsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_rsa_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_rsa_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_AES INT MAP REG */
+/** Type of aes_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_aes_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_aes_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_aes_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SHA INT MAP REG */
+/** Type of sha_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_sha_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_sha_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_sha_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_ECC INT MAP REG */
+/** Type of ecc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ecc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ecc_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_ECDSA INT MAP REG */
+/** Type of ecdsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ecdsa_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ecdsa_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_KM INT MAP REG */
+/** Type of km_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_km_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_km_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_km_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_GPIO INT0 MAP REG */
+/** Type of gpio_int0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_gpio_int0_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_int0_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_GPIO INT1 MAP REG */
+/** Type of gpio_int1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_gpio_int1_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_int1_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_GPIO INT2 MAP REG */
+/** Type of gpio_int2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_gpio_int2_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_int2_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_GPIO INT3 MAP REG */
+/** Type of gpio_int3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_gpio_int3_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_int3_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_GPIO PAD COMP INT MAP REG */
+/** Type of gpio_pad_comp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_gpio_pad_comp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_pad_comp_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 0 MAP REG */
+/** Type of cpu_int_from_cpu_0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_cpu_int_from_cpu_0_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_int_from_cpu_0_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 1 MAP REG */
+/** Type of cpu_int_from_cpu_1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_cpu_int_from_cpu_1_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_int_from_cpu_1_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 2 MAP REG */
+/** Type of cpu_int_from_cpu_2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_cpu_int_from_cpu_2_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_int_from_cpu_2_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 3 MAP REG */
+/** Type of cpu_int_from_cpu_3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_cpu_int_from_cpu_3_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_int_from_cpu_3_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CACHE INT MAP REG */
+/** Type of cache_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_cache_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_cache_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_cache_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_FLASH MSPI INT MAP REG */
+/** Type of flash_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_flash_mspi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_flash_mspi_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CSI BRIDGE INT MAP REG */
+/** Type of csi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_csi_bridge_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_csi_bridge_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_DSI BRIDGE INT MAP REG */
+/** Type of dsi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_dsi_bridge_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_dsi_bridge_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CSI INT MAP REG */
+/** Type of csi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_csi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_csi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_csi_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_DSI INT MAP REG */
+/** Type of dsi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_dsi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_dsi_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_GMII PHY INT MAP REG */
+/** Type of gmii_phy_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_gmii_phy_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_gmii_phy_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_LPI INT MAP REG */
+/** Type of lpi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_lpi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_lpi_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PMT INT MAP REG */
+/** Type of pmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_pmt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_pmt_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_SBD INT MAP REG */
+/** Type of sbd_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_sbd_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_sbd_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_USB OTG INT MAP REG */
+/** Type of usb_otg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_usb_otg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_usb_otg_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_USB OTG ENDP MULTI PROC INT MAP REG */
+/** Type of usb_otg_endp_multi_proc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_usb_otg_endp_multi_proc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_usb_otg_endp_multi_proc_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_JPEG INT MAP REG */
+/** Type of jpeg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_jpeg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_jpeg_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PPA INT MAP REG */
+/** Type of ppa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_ppa_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_ppa_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_INTERRUPT_CORE0_TRACE INT MAP REG */
+/** Type of interrupt_core0_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_trace_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_trace_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CORE1 TRACE INT MAP REG */
+/** Type of core1_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_core1_trace_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_core1_trace_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_HP CORE CTRL INT MAP REG */
+/** Type of hp_core_ctrl_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_hp_core_ctrl_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_hp_core_ctrl_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_ISP INT MAP REG */
+/** Type of isp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_isp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_isp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_isp_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_I3C MST INT MAP REG */
+/** Type of i3c_mst_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_i3c_mst_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_i3c_mst_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_I3C SLV INT MAP REG */
+/** Type of i3c_slv_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_i3c_slv_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_i3c_slv_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_USB OTG11 INT MAP REG */
+/** Type of usb_otg11_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_usb_otg11_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_usb_otg11_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_DMA2D IN CH0 INT MAP REG */
+/** Type of dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_dma2d_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_DMA2D IN CH1 INT MAP REG */
+/** Type of dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_dma2d_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_DMA2D OUT CH0 INT MAP REG */
+/** Type of dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_dma2d_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_DMA2D OUT CH1 INT MAP REG */
+/** Type of dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_dma2d_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_DMA2D OUT CH2 INT MAP REG */
+/** Type of dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_dma2d_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PSRAM MSPI INT MAP REG */
+/** Type of psram_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_psram_mspi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_psram_mspi_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_HP SYSREG INT MAP REG */
+/** Type of hp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_hp_sysreg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_hp_sysreg_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_PCNT INT MAP REG */
+/** Type of pcnt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_pcnt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_pcnt_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_HP PAU INT MAP REG */
+/** Type of hp_pau_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_hp_pau_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_hp_pau_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_HP PARLIO RX INT MAP REG */
+/** Type of hp_parlio_rx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_hp_parlio_rx_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_hp_parlio_rx_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_HP PARLIO TX INT MAP REG */
+/** Type of hp_parlio_tx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_hp_parlio_tx_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_hp_parlio_tx_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH0 INT MAP REG */
+/** Type of h264_dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH1 INT MAP REG */
+/** Type of h264_dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH2 INT MAP REG */
+/** Type of h264_dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH3 INT MAP REG */
+/** Type of h264_dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_out_ch3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH4 INT MAP REG */
+/** Type of h264_dma2d_out_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_out_ch4_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_out_ch4_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH0 INT MAP REG */
+/** Type of h264_dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH1 INT MAP REG */
+/** Type of h264_dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH2 INT MAP REG */
+/** Type of h264_dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_in_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH3 INT MAP REG */
+/** Type of h264_dma2d_in_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_in_ch3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_in_ch3_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH4 INT MAP REG */
+/** Type of h264_dma2d_in_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_in_ch4_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_in_ch4_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH5 INT MAP REG */
+/** Type of h264_dma2d_in_ch5_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_dma2d_in_ch5_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_dma2d_in_ch5_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_H264 REG INT MAP REG */
+/** Type of h264_reg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_h264_reg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_h264_reg_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_ASSIST DEBUG INT MAP REG */
+/** Type of assist_debug_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_assist_debug_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core0_assist_debug_int_map_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_INTR STATUS REG 0 REG */
+/** Type of intr_status_reg_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_intr_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_intr_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core0_intr_status_reg_0_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_INTR STATUS REG 1 REG */
+/** Type of intr_status_reg_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_intr_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_intr_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core0_intr_status_reg_1_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_INTR STATUS REG 2 REG */
+/** Type of intr_status_reg_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_intr_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_intr_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core0_intr_status_reg_2_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_INTR STATUS REG 3 REG */
+/** Type of intr_status_reg_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_intr_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core0_intr_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core0_intr_status_reg_3_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_CLOCK GATE REG */
+/** Type of clock_gate register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t interrupt_core0_reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} interrupt_core0_clock_gate_reg_t;
+
+
+/** Group: INTERRUPT_CORE0_INTERRUPT REG DATE REG */
+/** Type of interrupt_reg_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752;
+         *  NA
+         */
+        uint32_t interrupt_core0_interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} interrupt_core0_interrupt_reg_date_reg_t;
+
+
+typedef struct {
+    volatile interrupt_core0_lp_rtc_int_map_reg_t lp_rtc_int_map;
+    volatile interrupt_core0_lp_wdt_int_map_reg_t lp_wdt_int_map;
+    volatile interrupt_core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map;
+    volatile interrupt_core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map;
+    volatile interrupt_core0_mb_hp_int_map_reg_t mb_hp_int_map;
+    volatile interrupt_core0_mb_lp_int_map_reg_t mb_lp_int_map;
+    volatile interrupt_core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map;
+    volatile interrupt_core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map;
+    volatile interrupt_core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map;
+    volatile interrupt_core0_lp_adc_int_map_reg_t lp_adc_int_map;
+    volatile interrupt_core0_lp_gpio_int_map_reg_t lp_gpio_int_map;
+    volatile interrupt_core0_lp_i2c_int_map_reg_t lp_i2c_int_map;
+    volatile interrupt_core0_lp_i2s_int_map_reg_t lp_i2s_int_map;
+    volatile interrupt_core0_lp_spi_int_map_reg_t lp_spi_int_map;
+    volatile interrupt_core0_lp_touch_int_map_reg_t lp_touch_int_map;
+    volatile interrupt_core0_lp_tsens_int_map_reg_t lp_tsens_int_map;
+    volatile interrupt_core0_lp_uart_int_map_reg_t lp_uart_int_map;
+    volatile interrupt_core0_lp_efuse_int_map_reg_t lp_efuse_int_map;
+    volatile interrupt_core0_lp_sw_int_map_reg_t lp_sw_int_map;
+    volatile interrupt_core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map;
+    volatile interrupt_core0_lp_huk_int_map_reg_t lp_huk_int_map;
+    volatile interrupt_core0_sys_icm_int_map_reg_t sys_icm_int_map;
+    volatile interrupt_core0_usb_device_int_map_reg_t usb_device_int_map;
+    volatile interrupt_core0_sdio_host_int_map_reg_t sdio_host_int_map;
+    volatile interrupt_core0_gdma_int_map_reg_t gdma_int_map;
+    volatile interrupt_core0_spi2_int_map_reg_t spi2_int_map;
+    volatile interrupt_core0_spi3_int_map_reg_t spi3_int_map;
+    volatile interrupt_core0_i2s0_int_map_reg_t i2s0_int_map;
+    volatile interrupt_core0_i2s1_int_map_reg_t i2s1_int_map;
+    volatile interrupt_core0_i2s2_int_map_reg_t i2s2_int_map;
+    volatile interrupt_core0_uhci0_int_map_reg_t uhci0_int_map;
+    volatile interrupt_core0_uart0_int_map_reg_t uart0_int_map;
+    volatile interrupt_core0_uart1_int_map_reg_t uart1_int_map;
+    volatile interrupt_core0_uart2_int_map_reg_t uart2_int_map;
+    volatile interrupt_core0_uart3_int_map_reg_t uart3_int_map;
+    volatile interrupt_core0_uart4_int_map_reg_t uart4_int_map;
+    volatile interrupt_core0_lcd_cam_int_map_reg_t lcd_cam_int_map;
+    volatile interrupt_core0_adc_int_map_reg_t adc_int_map;
+    volatile interrupt_core0_pwm0_int_map_reg_t pwm0_int_map;
+    volatile interrupt_core0_pwm1_int_map_reg_t pwm1_int_map;
+    volatile interrupt_core0_can0_int_map_reg_t can0_int_map;
+    volatile interrupt_core0_can1_int_map_reg_t can1_int_map;
+    volatile interrupt_core0_can2_int_map_reg_t can2_int_map;
+    volatile interrupt_core0_rmt_int_map_reg_t rmt_int_map;
+    volatile interrupt_core0_i2c0_int_map_reg_t i2c0_int_map;
+    volatile interrupt_core0_i2c1_int_map_reg_t i2c1_int_map;
+    volatile interrupt_core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map;
+    volatile interrupt_core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map;
+    volatile interrupt_core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map;
+    volatile interrupt_core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map;
+    volatile interrupt_core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map;
+    volatile interrupt_core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map;
+    volatile interrupt_core0_ledc_int_map_reg_t ledc_int_map;
+    volatile interrupt_core0_systimer_target0_int_map_reg_t systimer_target0_int_map;
+    volatile interrupt_core0_systimer_target1_int_map_reg_t systimer_target1_int_map;
+    volatile interrupt_core0_systimer_target2_int_map_reg_t systimer_target2_int_map;
+    volatile interrupt_core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map;
+    volatile interrupt_core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map;
+    volatile interrupt_core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map;
+    volatile interrupt_core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map;
+    volatile interrupt_core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map;
+    volatile interrupt_core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map;
+    volatile interrupt_core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map;
+    volatile interrupt_core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map;
+    volatile interrupt_core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map;
+    volatile interrupt_core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map;
+    volatile interrupt_core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map;
+    volatile interrupt_core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map;
+    volatile interrupt_core0_rsa_int_map_reg_t rsa_int_map;
+    volatile interrupt_core0_aes_int_map_reg_t aes_int_map;
+    volatile interrupt_core0_sha_int_map_reg_t sha_int_map;
+    volatile interrupt_core0_ecc_int_map_reg_t ecc_int_map;
+    volatile interrupt_core0_ecdsa_int_map_reg_t ecdsa_int_map;
+    volatile interrupt_core0_km_int_map_reg_t km_int_map;
+    volatile interrupt_core0_gpio_int0_map_reg_t gpio_int0_map;
+    volatile interrupt_core0_gpio_int1_map_reg_t gpio_int1_map;
+    volatile interrupt_core0_gpio_int2_map_reg_t gpio_int2_map;
+    volatile interrupt_core0_gpio_int3_map_reg_t gpio_int3_map;
+    volatile interrupt_core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map;
+    volatile interrupt_core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map;
+    volatile interrupt_core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map;
+    volatile interrupt_core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map;
+    volatile interrupt_core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map;
+    volatile interrupt_core0_cache_int_map_reg_t cache_int_map;
+    volatile interrupt_core0_flash_mspi_int_map_reg_t flash_mspi_int_map;
+    volatile interrupt_core0_csi_bridge_int_map_reg_t csi_bridge_int_map;
+    volatile interrupt_core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map;
+    volatile interrupt_core0_csi_int_map_reg_t csi_int_map;
+    volatile interrupt_core0_dsi_int_map_reg_t dsi_int_map;
+    volatile interrupt_core0_gmii_phy_int_map_reg_t gmii_phy_int_map;
+    volatile interrupt_core0_lpi_int_map_reg_t lpi_int_map;
+    volatile interrupt_core0_pmt_int_map_reg_t pmt_int_map;
+    volatile interrupt_core0_sbd_int_map_reg_t sbd_int_map;
+    volatile interrupt_core0_usb_otg_int_map_reg_t usb_otg_int_map;
+    volatile interrupt_core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map;
+    volatile interrupt_core0_jpeg_int_map_reg_t jpeg_int_map;
+    volatile interrupt_core0_ppa_int_map_reg_t ppa_int_map;
+    volatile interrupt_core0_trace_int_map_reg_t interrupt_core0_trace_int_map;
+    volatile interrupt_core0_core1_trace_int_map_reg_t core1_trace_int_map;
+    volatile interrupt_core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map;
+    volatile interrupt_core0_isp_int_map_reg_t isp_int_map;
+    volatile interrupt_core0_i3c_mst_int_map_reg_t i3c_mst_int_map;
+    volatile interrupt_core0_i3c_slv_int_map_reg_t i3c_slv_int_map;
+    volatile interrupt_core0_usb_otg11_int_map_reg_t usb_otg11_int_map;
+    volatile interrupt_core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map;
+    volatile interrupt_core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map;
+    volatile interrupt_core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map;
+    volatile interrupt_core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map;
+    volatile interrupt_core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map;
+    volatile interrupt_core0_psram_mspi_int_map_reg_t psram_mspi_int_map;
+    volatile interrupt_core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map;
+    volatile interrupt_core0_pcnt_int_map_reg_t pcnt_int_map;
+    volatile interrupt_core0_hp_pau_int_map_reg_t hp_pau_int_map;
+    volatile interrupt_core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map;
+    volatile interrupt_core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map;
+    volatile interrupt_core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map;
+    volatile interrupt_core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map;
+    volatile interrupt_core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map;
+    volatile interrupt_core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map;
+    volatile interrupt_core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map;
+    volatile interrupt_core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map;
+    volatile interrupt_core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map;
+    volatile interrupt_core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map;
+    volatile interrupt_core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map;
+    volatile interrupt_core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map;
+    volatile interrupt_core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map;
+    volatile interrupt_core0_h264_reg_int_map_reg_t h264_reg_int_map;
+    volatile interrupt_core0_assist_debug_int_map_reg_t assist_debug_int_map;
+    volatile interrupt_core0_intr_status_reg_0_reg_t intr_status_reg_0;
+    volatile interrupt_core0_intr_status_reg_1_reg_t intr_status_reg_1;
+    volatile interrupt_core0_intr_status_reg_2_reg_t intr_status_reg_2;
+    volatile interrupt_core0_intr_status_reg_3_reg_t intr_status_reg_3;
+    volatile interrupt_core0_clock_gate_reg_t clock_gate;
+    uint32_t reserved_214[122];
+    volatile interrupt_core0_interrupt_reg_date_reg_t interrupt_reg_date;
+} interrupt_core0_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(interrupt_core0_dev_t) == 0x400, "Invalid size of interrupt_core0_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h
index 7ba04340b6..d4afbcfbe1 100644
--- a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h
+++ b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h
@@ -1,1094 +1,1624 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_INTERRUPT_CORE1_REG_H_
-#define _SOC_INTERRUPT_CORE1_REG_H_
-
+#pragma once
 
+#include <stdint.h>
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
-#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x0)
-/* INTERRUPT_CORE1_LP_RTC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_RTC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_RTC_INT_MAP_M  ((INTERRUPT_CORE1_LP_RTC_INT_MAP_V)<<(INTERRUPT_CORE1_LP_RTC_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_RTC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_RTC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x0)
+/** INTERRUPT_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_M  (INTERRUPT_CORE1_LP_RTC_INT_MAP_V << INTERRUPT_CORE1_LP_RTC_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_RTC_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x4)
-/* INTERRUPT_CORE1_LP_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_WDT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_WDT_INT_MAP_M  ((INTERRUPT_CORE1_LP_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_LP_WDT_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_WDT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4)
+/** INTERRUPT_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_M  (INTERRUPT_CORE1_LP_WDT_INT_MAP_V << INTERRUPT_CORE1_LP_WDT_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x8)
-/* INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_M  ((INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8)
+/** INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_M  (INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC)
-/* INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_M  ((INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc)
+/** INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_M  (INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x10)
-/* INTERRUPT_CORE1_MB_HP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_MB_HP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_MB_HP_INT_MAP_M  ((INTERRUPT_CORE1_MB_HP_INT_MAP_V)<<(INTERRUPT_CORE1_MB_HP_INT_MAP_S))
-#define INTERRUPT_CORE1_MB_HP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_MB_HP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10)
+/** INTERRUPT_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_MB_HP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_M  (INTERRUPT_CORE1_MB_HP_INT_MAP_V << INTERRUPT_CORE1_MB_HP_INT_MAP_S)
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_MB_HP_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x14)
-/* INTERRUPT_CORE1_MB_LP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_MB_LP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_MB_LP_INT_MAP_M  ((INTERRUPT_CORE1_MB_LP_INT_MAP_V)<<(INTERRUPT_CORE1_MB_LP_INT_MAP_S))
-#define INTERRUPT_CORE1_MB_LP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_MB_LP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14)
+/** INTERRUPT_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_MB_LP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_M  (INTERRUPT_CORE1_MB_LP_INT_MAP_V << INTERRUPT_CORE1_MB_LP_INT_MAP_S)
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_MB_LP_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x18)
-/* INTERRUPT_CORE1_PMU_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_M  ((INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V)<<(INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S))
-#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18)
+/** INTERRUPT_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_M  (INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V << INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C)
-/* INTERRUPT_CORE1_PMU_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_M  ((INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V)<<(INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S))
-#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c)
+/** INTERRUPT_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_M  (INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V << INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x20)
-/* INTERRUPT_CORE1_LP_ANAPERI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_M  ((INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V)<<(INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20)
+/** INTERRUPT_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_M  (INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V << INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x24)
-/* INTERRUPT_CORE1_LP_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_ADC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_ADC_INT_MAP_M  ((INTERRUPT_CORE1_LP_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_LP_ADC_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_ADC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24)
+/** INTERRUPT_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_M  (INTERRUPT_CORE1_LP_ADC_INT_MAP_V << INTERRUPT_CORE1_LP_ADC_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_ADC_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x28)
-/* INTERRUPT_CORE1_LP_GPIO_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_GPIO_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_M  ((INTERRUPT_CORE1_LP_GPIO_INT_MAP_V)<<(INTERRUPT_CORE1_LP_GPIO_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28)
+/** INTERRUPT_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_M  (INTERRUPT_CORE1_LP_GPIO_INT_MAP_V << INTERRUPT_CORE1_LP_GPIO_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_GPIO_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x2C)
-/* INTERRUPT_CORE1_LP_I2C_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_I2C_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_I2C_INT_MAP_M  ((INTERRUPT_CORE1_LP_I2C_INT_MAP_V)<<(INTERRUPT_CORE1_LP_I2C_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_I2C_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_I2C_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c)
+/** INTERRUPT_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_M  (INTERRUPT_CORE1_LP_I2C_INT_MAP_V << INTERRUPT_CORE1_LP_I2C_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_I2C_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x30)
-/* INTERRUPT_CORE1_LP_I2S_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_I2S_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_I2S_INT_MAP_M  ((INTERRUPT_CORE1_LP_I2S_INT_MAP_V)<<(INTERRUPT_CORE1_LP_I2S_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_I2S_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_I2S_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x30)
+/** INTERRUPT_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_M  (INTERRUPT_CORE1_LP_I2S_INT_MAP_V << INTERRUPT_CORE1_LP_I2S_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_I2S_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x34)
-/* INTERRUPT_CORE1_LP_SPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_SPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_SPI_INT_MAP_M  ((INTERRUPT_CORE1_LP_SPI_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SPI_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_SPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_SPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x34)
+/** INTERRUPT_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_M  (INTERRUPT_CORE1_LP_SPI_INT_MAP_V << INTERRUPT_CORE1_LP_SPI_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_SPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x38)
-/* INTERRUPT_CORE1_LP_TOUCH_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_M  ((INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x38)
+/** INTERRUPT_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_M  (INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V << INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x3C)
-/* INTERRUPT_CORE1_LP_TSENS_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_TSENS_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_M  ((INTERRUPT_CORE1_LP_TSENS_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TSENS_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3c)
+/** INTERRUPT_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_M  (INTERRUPT_CORE1_LP_TSENS_INT_MAP_V << INTERRUPT_CORE1_LP_TSENS_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_TSENS_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x40)
-/* INTERRUPT_CORE1_LP_UART_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_UART_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_UART_INT_MAP_M  ((INTERRUPT_CORE1_LP_UART_INT_MAP_V)<<(INTERRUPT_CORE1_LP_UART_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_UART_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_UART_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x40)
+/** INTERRUPT_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_UART_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_M  (INTERRUPT_CORE1_LP_UART_INT_MAP_V << INTERRUPT_CORE1_LP_UART_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_UART_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x44)
-/* INTERRUPT_CORE1_LP_EFUSE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_M  ((INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x44)
+/** INTERRUPT_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_M  (INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V << INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x48)
-/* INTERRUPT_CORE1_LP_SW_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_SW_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_SW_INT_MAP_M  ((INTERRUPT_CORE1_LP_SW_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SW_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_SW_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_SW_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x48)
+/** INTERRUPT_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SW_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_M  (INTERRUPT_CORE1_LP_SW_INT_MAP_V << INTERRUPT_CORE1_LP_SW_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_SW_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x4C)
-/* INTERRUPT_CORE1_LP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4c)
+/** INTERRUPT_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_M  (INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V << INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x50)
-/* INTERRUPT_CORE1_LP_HUK_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LP_HUK_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LP_HUK_INT_MAP_M  ((INTERRUPT_CORE1_LP_HUK_INT_MAP_V)<<(INTERRUPT_CORE1_LP_HUK_INT_MAP_S))
-#define INTERRUPT_CORE1_LP_HUK_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LP_HUK_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x50)
+/** INTERRUPT_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_M  (INTERRUPT_CORE1_LP_HUK_INT_MAP_V << INTERRUPT_CORE1_LP_HUK_INT_MAP_S)
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LP_HUK_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x54)
-/* INTERRUPT_CORE1_SYS_ICM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SYS_ICM_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_M  ((INTERRUPT_CORE1_SYS_ICM_INT_MAP_V)<<(INTERRUPT_CORE1_SYS_ICM_INT_MAP_S))
-#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x54)
+/** INTERRUPT_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_M  (INTERRUPT_CORE1_SYS_ICM_INT_MAP_V << INTERRUPT_CORE1_SYS_ICM_INT_MAP_S)
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SYS_ICM_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x58)
-/* INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M  ((INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S))
-#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x58)
+/** INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M  (INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V << INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S)
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x5C)
-/* INTERRUPT_CORE1_SDIO_HOST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_M  ((INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V)<<(INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S))
-#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x5c)
+/** INTERRUPT_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_M  (INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V << INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S)
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_GDMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x60)
-/* INTERRUPT_CORE1_GDMA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_GDMA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_GDMA_INT_MAP_M  ((INTERRUPT_CORE1_GDMA_INT_MAP_V)<<(INTERRUPT_CORE1_GDMA_INT_MAP_S))
-#define INTERRUPT_CORE1_GDMA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_GDMA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x60)
+/** INTERRUPT_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_GDMA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GDMA_INT_MAP_M  (INTERRUPT_CORE1_GDMA_INT_MAP_V << INTERRUPT_CORE1_GDMA_INT_MAP_S)
+#define INTERRUPT_CORE1_GDMA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_GDMA_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SPI2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x64)
-/* INTERRUPT_CORE1_SPI2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SPI2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SPI2_INT_MAP_M  ((INTERRUPT_CORE1_SPI2_INT_MAP_V)<<(INTERRUPT_CORE1_SPI2_INT_MAP_S))
-#define INTERRUPT_CORE1_SPI2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SPI2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x64)
+/** INTERRUPT_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SPI2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SPI2_INT_MAP_M  (INTERRUPT_CORE1_SPI2_INT_MAP_V << INTERRUPT_CORE1_SPI2_INT_MAP_S)
+#define INTERRUPT_CORE1_SPI2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SPI2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SPI3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x68)
-/* INTERRUPT_CORE1_SPI3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SPI3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SPI3_INT_MAP_M  ((INTERRUPT_CORE1_SPI3_INT_MAP_V)<<(INTERRUPT_CORE1_SPI3_INT_MAP_S))
-#define INTERRUPT_CORE1_SPI3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SPI3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x68)
+/** INTERRUPT_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SPI3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SPI3_INT_MAP_M  (INTERRUPT_CORE1_SPI3_INT_MAP_V << INTERRUPT_CORE1_SPI3_INT_MAP_S)
+#define INTERRUPT_CORE1_SPI3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SPI3_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_I2S0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x6C)
-/* INTERRUPT_CORE1_I2S0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_I2S0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_I2S0_INT_MAP_M  ((INTERRUPT_CORE1_I2S0_INT_MAP_V)<<(INTERRUPT_CORE1_I2S0_INT_MAP_S))
-#define INTERRUPT_CORE1_I2S0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_I2S0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x6c)
+/** INTERRUPT_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2S0_INT_MAP_M  (INTERRUPT_CORE1_I2S0_INT_MAP_V << INTERRUPT_CORE1_I2S0_INT_MAP_S)
+#define INTERRUPT_CORE1_I2S0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_I2S0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x70)
-/* INTERRUPT_CORE1_I2S1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_I2S1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_I2S1_INT_MAP_M  ((INTERRUPT_CORE1_I2S1_INT_MAP_V)<<(INTERRUPT_CORE1_I2S1_INT_MAP_S))
-#define INTERRUPT_CORE1_I2S1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_I2S1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x70)
+/** INTERRUPT_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2S1_INT_MAP_M  (INTERRUPT_CORE1_I2S1_INT_MAP_V << INTERRUPT_CORE1_I2S1_INT_MAP_S)
+#define INTERRUPT_CORE1_I2S1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_I2S1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_I2S2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x74)
-/* INTERRUPT_CORE1_I2S2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_I2S2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_I2S2_INT_MAP_M  ((INTERRUPT_CORE1_I2S2_INT_MAP_V)<<(INTERRUPT_CORE1_I2S2_INT_MAP_S))
-#define INTERRUPT_CORE1_I2S2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_I2S2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x74)
+/** INTERRUPT_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2S2_INT_MAP_M  (INTERRUPT_CORE1_I2S2_INT_MAP_V << INTERRUPT_CORE1_I2S2_INT_MAP_S)
+#define INTERRUPT_CORE1_I2S2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_I2S2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x78)
-/* INTERRUPT_CORE1_UHCI0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_UHCI0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_UHCI0_INT_MAP_M  ((INTERRUPT_CORE1_UHCI0_INT_MAP_V)<<(INTERRUPT_CORE1_UHCI0_INT_MAP_S))
-#define INTERRUPT_CORE1_UHCI0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_UHCI0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x78)
+/** INTERRUPT_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_UHCI0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_M  (INTERRUPT_CORE1_UHCI0_INT_MAP_V << INTERRUPT_CORE1_UHCI0_INT_MAP_S)
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_UHCI0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_UART0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x7C)
-/* INTERRUPT_CORE1_UART0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_UART0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_UART0_INT_MAP_M  ((INTERRUPT_CORE1_UART0_INT_MAP_V)<<(INTERRUPT_CORE1_UART0_INT_MAP_S))
-#define INTERRUPT_CORE1_UART0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_UART0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7c)
+/** INTERRUPT_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART0_INT_MAP_M  (INTERRUPT_CORE1_UART0_INT_MAP_V << INTERRUPT_CORE1_UART0_INT_MAP_S)
+#define INTERRUPT_CORE1_UART0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_UART0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_UART1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x80)
-/* INTERRUPT_CORE1_UART1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_UART1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_UART1_INT_MAP_M  ((INTERRUPT_CORE1_UART1_INT_MAP_V)<<(INTERRUPT_CORE1_UART1_INT_MAP_S))
-#define INTERRUPT_CORE1_UART1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_UART1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80)
+/** INTERRUPT_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART1_INT_MAP_M  (INTERRUPT_CORE1_UART1_INT_MAP_V << INTERRUPT_CORE1_UART1_INT_MAP_S)
+#define INTERRUPT_CORE1_UART1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_UART1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_UART2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x84)
-/* INTERRUPT_CORE1_UART2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_UART2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_UART2_INT_MAP_M  ((INTERRUPT_CORE1_UART2_INT_MAP_V)<<(INTERRUPT_CORE1_UART2_INT_MAP_S))
-#define INTERRUPT_CORE1_UART2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_UART2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84)
+/** INTERRUPT_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART2_INT_MAP_M  (INTERRUPT_CORE1_UART2_INT_MAP_V << INTERRUPT_CORE1_UART2_INT_MAP_S)
+#define INTERRUPT_CORE1_UART2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_UART2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_UART3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x88)
-/* INTERRUPT_CORE1_UART3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_UART3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_UART3_INT_MAP_M  ((INTERRUPT_CORE1_UART3_INT_MAP_V)<<(INTERRUPT_CORE1_UART3_INT_MAP_S))
-#define INTERRUPT_CORE1_UART3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_UART3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88)
+/** INTERRUPT_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART3_INT_MAP_M  (INTERRUPT_CORE1_UART3_INT_MAP_V << INTERRUPT_CORE1_UART3_INT_MAP_S)
+#define INTERRUPT_CORE1_UART3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_UART3_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_UART4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x8C)
-/* INTERRUPT_CORE1_UART4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_UART4_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_UART4_INT_MAP_M  ((INTERRUPT_CORE1_UART4_INT_MAP_V)<<(INTERRUPT_CORE1_UART4_INT_MAP_S))
-#define INTERRUPT_CORE1_UART4_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_UART4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8c)
+/** INTERRUPT_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART4_INT_MAP_M  (INTERRUPT_CORE1_UART4_INT_MAP_V << INTERRUPT_CORE1_UART4_INT_MAP_S)
+#define INTERRUPT_CORE1_UART4_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_UART4_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x90)
-/* INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LCD_CAM_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M  ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE1_LCD_CAM_INT_MAP_S))
-#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90)
+/** INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M  (INTERRUPT_CORE1_LCD_CAM_INT_MAP_V << INTERRUPT_CORE1_LCD_CAM_INT_MAP_S)
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x94)
-/* INTERRUPT_CORE1_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_ADC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_ADC_INT_MAP_M  ((INTERRUPT_CORE1_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_ADC_INT_MAP_S))
-#define INTERRUPT_CORE1_ADC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94)
+/** INTERRUPT_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ADC_INT_MAP_M  (INTERRUPT_CORE1_ADC_INT_MAP_V << INTERRUPT_CORE1_ADC_INT_MAP_S)
+#define INTERRUPT_CORE1_ADC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_ADC_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PWM0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x98)
-/* INTERRUPT_CORE1_PWM0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PWM0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PWM0_INT_MAP_M  ((INTERRUPT_CORE1_PWM0_INT_MAP_V)<<(INTERRUPT_CORE1_PWM0_INT_MAP_S))
-#define INTERRUPT_CORE1_PWM0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PWM0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98)
+/** INTERRUPT_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PWM0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PWM0_INT_MAP_M  (INTERRUPT_CORE1_PWM0_INT_MAP_V << INTERRUPT_CORE1_PWM0_INT_MAP_S)
+#define INTERRUPT_CORE1_PWM0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PWM0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PWM1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x9C)
-/* INTERRUPT_CORE1_PWM1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PWM1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PWM1_INT_MAP_M  ((INTERRUPT_CORE1_PWM1_INT_MAP_V)<<(INTERRUPT_CORE1_PWM1_INT_MAP_S))
-#define INTERRUPT_CORE1_PWM1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PWM1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x9c)
+/** INTERRUPT_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PWM1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PWM1_INT_MAP_M  (INTERRUPT_CORE1_PWM1_INT_MAP_V << INTERRUPT_CORE1_PWM1_INT_MAP_S)
+#define INTERRUPT_CORE1_PWM1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PWM1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_CAN0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xA0)
-/* INTERRUPT_CORE1_CAN0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CAN0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_CAN0_INT_MAP_M  ((INTERRUPT_CORE1_CAN0_INT_MAP_V)<<(INTERRUPT_CORE1_CAN0_INT_MAP_S))
-#define INTERRUPT_CORE1_CAN0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_CAN0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa0)
+/** INTERRUPT_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CAN0_INT_MAP_M  (INTERRUPT_CORE1_CAN0_INT_MAP_V << INTERRUPT_CORE1_CAN0_INT_MAP_S)
+#define INTERRUPT_CORE1_CAN0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CAN0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_CAN1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xA4)
-/* INTERRUPT_CORE1_CAN1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CAN1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_CAN1_INT_MAP_M  ((INTERRUPT_CORE1_CAN1_INT_MAP_V)<<(INTERRUPT_CORE1_CAN1_INT_MAP_S))
-#define INTERRUPT_CORE1_CAN1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_CAN1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa4)
+/** INTERRUPT_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CAN1_INT_MAP_M  (INTERRUPT_CORE1_CAN1_INT_MAP_V << INTERRUPT_CORE1_CAN1_INT_MAP_S)
+#define INTERRUPT_CORE1_CAN1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CAN1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_CAN2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xA8)
-/* INTERRUPT_CORE1_CAN2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CAN2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_CAN2_INT_MAP_M  ((INTERRUPT_CORE1_CAN2_INT_MAP_V)<<(INTERRUPT_CORE1_CAN2_INT_MAP_S))
-#define INTERRUPT_CORE1_CAN2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_CAN2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa8)
+/** INTERRUPT_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CAN2_INT_MAP_M  (INTERRUPT_CORE1_CAN2_INT_MAP_V << INTERRUPT_CORE1_CAN2_INT_MAP_S)
+#define INTERRUPT_CORE1_CAN2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CAN2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_RMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xAC)
-/* INTERRUPT_CORE1_RMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_RMT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_RMT_INT_MAP_M  ((INTERRUPT_CORE1_RMT_INT_MAP_V)<<(INTERRUPT_CORE1_RMT_INT_MAP_S))
-#define INTERRUPT_CORE1_RMT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_RMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xac)
+/** INTERRUPT_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_RMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_RMT_INT_MAP_M  (INTERRUPT_CORE1_RMT_INT_MAP_V << INTERRUPT_CORE1_RMT_INT_MAP_S)
+#define INTERRUPT_CORE1_RMT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_RMT_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_I2C0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xB0)
-/* INTERRUPT_CORE1_I2C0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_I2C0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_I2C0_INT_MAP_M  ((INTERRUPT_CORE1_I2C0_INT_MAP_V)<<(INTERRUPT_CORE1_I2C0_INT_MAP_S))
-#define INTERRUPT_CORE1_I2C0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_I2C0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb0)
+/** INTERRUPT_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2C0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2C0_INT_MAP_M  (INTERRUPT_CORE1_I2C0_INT_MAP_V << INTERRUPT_CORE1_I2C0_INT_MAP_S)
+#define INTERRUPT_CORE1_I2C0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_I2C0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_I2C1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xB4)
-/* INTERRUPT_CORE1_I2C1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_I2C1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_I2C1_INT_MAP_M  ((INTERRUPT_CORE1_I2C1_INT_MAP_V)<<(INTERRUPT_CORE1_I2C1_INT_MAP_S))
-#define INTERRUPT_CORE1_I2C1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_I2C1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb4)
+/** INTERRUPT_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2C1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2C1_INT_MAP_M  (INTERRUPT_CORE1_I2C1_INT_MAP_V << INTERRUPT_CORE1_I2C1_INT_MAP_S)
+#define INTERRUPT_CORE1_I2C1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_I2C1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xB8)
-/* INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S))
-#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb8)
+/** INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_M  (INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xBC)
-/* INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S))
-#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xbc)
+/** INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_M  (INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC0)
-/* INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S))
-#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc0)
+/** INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_M  (INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC4)
-/* INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S))
-#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc4)
+/** INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_M  (INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xC8)
-/* INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S))
-#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc8)
+/** INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_M  (INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xCC)
-/* INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_M  ((INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S))
-#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xcc)
+/** INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_M  (INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xD0)
-/* INTERRUPT_CORE1_LEDC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LEDC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LEDC_INT_MAP_M  ((INTERRUPT_CORE1_LEDC_INT_MAP_V)<<(INTERRUPT_CORE1_LEDC_INT_MAP_S))
-#define INTERRUPT_CORE1_LEDC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LEDC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd0)
+/** INTERRUPT_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LEDC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LEDC_INT_MAP_M  (INTERRUPT_CORE1_LEDC_INT_MAP_V << INTERRUPT_CORE1_LEDC_INT_MAP_S)
+#define INTERRUPT_CORE1_LEDC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LEDC_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xD4)
-/* INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S))
-#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd4)
+/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M  (INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xD8)
-/* INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S))
-#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd8)
+/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M  (INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xDC)
-/* INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S))
-#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xdc)
+/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M  (INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xE0)
-/* INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe0)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xE4)
-/* INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe4)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xE8)
-/* INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S))
-#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe8)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xEC)
-/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xec)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xF0)
-/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf0)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xF4)
-/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf4)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xF8)
-/* INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf8)
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0xFC)
-/* INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xfc)
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x100)
-/* INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S))
-#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x100)
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x104)
-/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x104)
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x108)
-/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x108)
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x10C)
-/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10c)
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x110)
-/* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_RSA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_RSA_INT_MAP_M  ((INTERRUPT_CORE1_RSA_INT_MAP_V)<<(INTERRUPT_CORE1_RSA_INT_MAP_S))
-#define INTERRUPT_CORE1_RSA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_RSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x110)
+/** INTERRUPT_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_RSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_RSA_INT_MAP_M  (INTERRUPT_CORE1_RSA_INT_MAP_V << INTERRUPT_CORE1_RSA_INT_MAP_S)
+#define INTERRUPT_CORE1_RSA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_RSA_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x114)
-/* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_AES_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_AES_INT_MAP_M  ((INTERRUPT_CORE1_AES_INT_MAP_V)<<(INTERRUPT_CORE1_AES_INT_MAP_S))
-#define INTERRUPT_CORE1_AES_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_AES_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x114)
+/** INTERRUPT_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_AES_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AES_INT_MAP_M  (INTERRUPT_CORE1_AES_INT_MAP_V << INTERRUPT_CORE1_AES_INT_MAP_S)
+#define INTERRUPT_CORE1_AES_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_AES_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x118)
-/* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SHA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SHA_INT_MAP_M  ((INTERRUPT_CORE1_SHA_INT_MAP_V)<<(INTERRUPT_CORE1_SHA_INT_MAP_S))
-#define INTERRUPT_CORE1_SHA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SHA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x118)
+/** INTERRUPT_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SHA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SHA_INT_MAP_M  (INTERRUPT_CORE1_SHA_INT_MAP_V << INTERRUPT_CORE1_SHA_INT_MAP_S)
+#define INTERRUPT_CORE1_SHA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SHA_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_ECC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x11C)
-/* INTERRUPT_CORE1_ECC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_ECC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_ECC_INT_MAP_M  ((INTERRUPT_CORE1_ECC_INT_MAP_V)<<(INTERRUPT_CORE1_ECC_INT_MAP_S))
-#define INTERRUPT_CORE1_ECC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_ECC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x11c)
+/** INTERRUPT_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_ECC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ECC_INT_MAP_M  (INTERRUPT_CORE1_ECC_INT_MAP_V << INTERRUPT_CORE1_ECC_INT_MAP_S)
+#define INTERRUPT_CORE1_ECC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_ECC_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x120)
-/* INTERRUPT_CORE1_ECDSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_ECDSA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_ECDSA_INT_MAP_M  ((INTERRUPT_CORE1_ECDSA_INT_MAP_V)<<(INTERRUPT_CORE1_ECDSA_INT_MAP_S))
-#define INTERRUPT_CORE1_ECDSA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_ECDSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x120)
+/** INTERRUPT_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_ECDSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_M  (INTERRUPT_CORE1_ECDSA_INT_MAP_V << INTERRUPT_CORE1_ECDSA_INT_MAP_S)
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_ECDSA_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_KM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x124)
-/* INTERRUPT_CORE1_KM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_KM_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_KM_INT_MAP_M  ((INTERRUPT_CORE1_KM_INT_MAP_V)<<(INTERRUPT_CORE1_KM_INT_MAP_S))
-#define INTERRUPT_CORE1_KM_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_KM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x124)
+/** INTERRUPT_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_KM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_KM_INT_MAP_M  (INTERRUPT_CORE1_KM_INT_MAP_V << INTERRUPT_CORE1_KM_INT_MAP_S)
+#define INTERRUPT_CORE1_KM_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_KM_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x128)
-/* INTERRUPT_CORE1_GPIO_INT0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_GPIO_INT0_MAP    0x0000003F
-#define INTERRUPT_CORE1_GPIO_INT0_MAP_M  ((INTERRUPT_CORE1_GPIO_INT0_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT0_MAP_S))
-#define INTERRUPT_CORE1_GPIO_INT0_MAP_V  0x3F
+/** INTERRUPT_CORE1_GPIO_INT0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x128)
+/** INTERRUPT_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT0_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_M  (INTERRUPT_CORE1_GPIO_INT0_MAP_V << INTERRUPT_CORE1_GPIO_INT0_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_GPIO_INT0_MAP_S  0
 
-#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x12C)
-/* INTERRUPT_CORE1_GPIO_INT1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_GPIO_INT1_MAP    0x0000003F
-#define INTERRUPT_CORE1_GPIO_INT1_MAP_M  ((INTERRUPT_CORE1_GPIO_INT1_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT1_MAP_S))
-#define INTERRUPT_CORE1_GPIO_INT1_MAP_V  0x3F
+/** INTERRUPT_CORE1_GPIO_INT1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x12c)
+/** INTERRUPT_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT1_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_M  (INTERRUPT_CORE1_GPIO_INT1_MAP_V << INTERRUPT_CORE1_GPIO_INT1_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_GPIO_INT1_MAP_S  0
 
-#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x130)
-/* INTERRUPT_CORE1_GPIO_INT2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_GPIO_INT2_MAP    0x0000003F
-#define INTERRUPT_CORE1_GPIO_INT2_MAP_M  ((INTERRUPT_CORE1_GPIO_INT2_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT2_MAP_S))
-#define INTERRUPT_CORE1_GPIO_INT2_MAP_V  0x3F
+/** INTERRUPT_CORE1_GPIO_INT2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x130)
+/** INTERRUPT_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT2_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_M  (INTERRUPT_CORE1_GPIO_INT2_MAP_V << INTERRUPT_CORE1_GPIO_INT2_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_GPIO_INT2_MAP_S  0
 
-#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x134)
-/* INTERRUPT_CORE1_GPIO_INT3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_GPIO_INT3_MAP    0x0000003F
-#define INTERRUPT_CORE1_GPIO_INT3_MAP_M  ((INTERRUPT_CORE1_GPIO_INT3_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT3_MAP_S))
-#define INTERRUPT_CORE1_GPIO_INT3_MAP_V  0x3F
+/** INTERRUPT_CORE1_GPIO_INT3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x134)
+/** INTERRUPT_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT3_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_M  (INTERRUPT_CORE1_GPIO_INT3_MAP_V << INTERRUPT_CORE1_GPIO_INT3_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_GPIO_INT3_MAP_S  0
 
-#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x138)
-/* INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_M  ((INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V)<<(INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S))
-#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x138)
+/** INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_M  (INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V << INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S)
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x13C)
-/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP    0x0000003F
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S))
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V  0x3F
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x13c)
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_M  (INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S  0
 
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x140)
-/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP    0x0000003F
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S))
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V  0x3F
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x140)
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_M  (INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S  0
 
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x144)
-/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP    0x0000003F
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S))
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V  0x3F
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x144)
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_M  (INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S  0
 
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x148)
-/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP    0x0000003F
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S))
-#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V  0x3F
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x148)
+/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_M  (INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S  0
 
-#define INTERRUPT_CORE1_CACHE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x14C)
-/* INTERRUPT_CORE1_CACHE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CACHE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_CACHE_INT_MAP_M  ((INTERRUPT_CORE1_CACHE_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_INT_MAP_S))
-#define INTERRUPT_CORE1_CACHE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_CACHE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14c)
+/** INTERRUPT_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CACHE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CACHE_INT_MAP_M  (INTERRUPT_CORE1_CACHE_INT_MAP_V << INTERRUPT_CORE1_CACHE_INT_MAP_S)
+#define INTERRUPT_CORE1_CACHE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CACHE_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x150)
-/* INTERRUPT_CORE1_FLASH_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_M  ((INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V)<<(INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S))
-#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x150)
+/** INTERRUPT_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_M  (INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V << INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x154)
-/* INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S))
-#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x154)
+/** INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_M  (INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V << INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x158)
-/* INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_M  ((INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S))
-#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x158)
+/** INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_M  (INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V << INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_CSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x15C)
-/* INTERRUPT_CORE1_CSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CSI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_CSI_INT_MAP_M  ((INTERRUPT_CORE1_CSI_INT_MAP_V)<<(INTERRUPT_CORE1_CSI_INT_MAP_S))
-#define INTERRUPT_CORE1_CSI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_CSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x15c)
+/** INTERRUPT_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CSI_INT_MAP_M  (INTERRUPT_CORE1_CSI_INT_MAP_V << INTERRUPT_CORE1_CSI_INT_MAP_S)
+#define INTERRUPT_CORE1_CSI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CSI_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_DSI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x160)
-/* INTERRUPT_CORE1_DSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_DSI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_DSI_INT_MAP_M  ((INTERRUPT_CORE1_DSI_INT_MAP_V)<<(INTERRUPT_CORE1_DSI_INT_MAP_S))
-#define INTERRUPT_CORE1_DSI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_DSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x160)
+/** INTERRUPT_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_DSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DSI_INT_MAP_M  (INTERRUPT_CORE1_DSI_INT_MAP_V << INTERRUPT_CORE1_DSI_INT_MAP_S)
+#define INTERRUPT_CORE1_DSI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_DSI_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x164)
-/* INTERRUPT_CORE1_GMII_PHY_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_GMII_PHY_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_M  ((INTERRUPT_CORE1_GMII_PHY_INT_MAP_V)<<(INTERRUPT_CORE1_GMII_PHY_INT_MAP_S))
-#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x164)
+/** INTERRUPT_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_M  (INTERRUPT_CORE1_GMII_PHY_INT_MAP_V << INTERRUPT_CORE1_GMII_PHY_INT_MAP_S)
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_GMII_PHY_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_LPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x168)
-/* INTERRUPT_CORE1_LPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_LPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_LPI_INT_MAP_M  ((INTERRUPT_CORE1_LPI_INT_MAP_V)<<(INTERRUPT_CORE1_LPI_INT_MAP_S))
-#define INTERRUPT_CORE1_LPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_LPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x168)
+/** INTERRUPT_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_LPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LPI_INT_MAP_M  (INTERRUPT_CORE1_LPI_INT_MAP_V << INTERRUPT_CORE1_LPI_INT_MAP_S)
+#define INTERRUPT_CORE1_LPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_LPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PMT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x16C)
-/* INTERRUPT_CORE1_PMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PMT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PMT_INT_MAP_M  ((INTERRUPT_CORE1_PMT_INT_MAP_V)<<(INTERRUPT_CORE1_PMT_INT_MAP_S))
-#define INTERRUPT_CORE1_PMT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x16c)
+/** INTERRUPT_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PMT_INT_MAP_M  (INTERRUPT_CORE1_PMT_INT_MAP_V << INTERRUPT_CORE1_PMT_INT_MAP_S)
+#define INTERRUPT_CORE1_PMT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PMT_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_SBD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x170)
-/* INTERRUPT_CORE1_SBD_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_SBD_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_SBD_INT_MAP_M  ((INTERRUPT_CORE1_SBD_INT_MAP_V)<<(INTERRUPT_CORE1_SBD_INT_MAP_S))
-#define INTERRUPT_CORE1_SBD_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_SBD_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x170)
+/** INTERRUPT_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_SBD_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SBD_INT_MAP_M  (INTERRUPT_CORE1_SBD_INT_MAP_V << INTERRUPT_CORE1_SBD_INT_MAP_S)
+#define INTERRUPT_CORE1_SBD_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_SBD_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x174)
-/* INTERRUPT_CORE1_USB_OTG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_USB_OTG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_USB_OTG_INT_MAP_M  ((INTERRUPT_CORE1_USB_OTG_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG_INT_MAP_S))
-#define INTERRUPT_CORE1_USB_OTG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_USB_OTG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x174)
+/** INTERRUPT_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_M  (INTERRUPT_CORE1_USB_OTG_INT_MAP_V << INTERRUPT_CORE1_USB_OTG_INT_MAP_S)
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_USB_OTG_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x178)
-/* INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  ((INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S))
-#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x178)
+/** INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  (INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_JPEG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x17C)
-/* INTERRUPT_CORE1_JPEG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_JPEG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_JPEG_INT_MAP_M  ((INTERRUPT_CORE1_JPEG_INT_MAP_V)<<(INTERRUPT_CORE1_JPEG_INT_MAP_S))
-#define INTERRUPT_CORE1_JPEG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_JPEG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x17c)
+/** INTERRUPT_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_JPEG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_JPEG_INT_MAP_M  (INTERRUPT_CORE1_JPEG_INT_MAP_V << INTERRUPT_CORE1_JPEG_INT_MAP_S)
+#define INTERRUPT_CORE1_JPEG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_JPEG_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PPA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x180)
-/* INTERRUPT_CORE1_PPA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PPA_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PPA_INT_MAP_M  ((INTERRUPT_CORE1_PPA_INT_MAP_V)<<(INTERRUPT_CORE1_PPA_INT_MAP_S))
-#define INTERRUPT_CORE1_PPA_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PPA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x180)
+/** INTERRUPT_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PPA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PPA_INT_MAP_M  (INTERRUPT_CORE1_PPA_INT_MAP_V << INTERRUPT_CORE1_PPA_INT_MAP_S)
+#define INTERRUPT_CORE1_PPA_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PPA_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x184)
-/* INTERRUPT_CORE1_CORE0_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_M  ((INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V)<<(INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S))
-#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x184)
+/** INTERRUPT_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_M  (INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V << INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_TRACE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x188)
-/* INTERRUPT_CORE1_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_TRACE_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_TRACE_INT_MAP_M  ((INTERRUPT_CORE1_TRACE_INT_MAP_V)<<(INTERRUPT_CORE1_TRACE_INT_MAP_S))
-#define INTERRUPT_CORE1_TRACE_INT_MAP_V  0x3F
-#define INTERRUPT_CORE1_TRACE_INT_MAP_S  0
+/** INTERRUPT_CORE1_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x188)
+/** INTERRUPT_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_M  (INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_V << INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x18C)
-/* INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_M  ((INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V)<<(INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S))
-#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18c)
+/** INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_M  (INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V << INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S)
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_ISP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x190)
-/* INTERRUPT_CORE1_ISP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_ISP_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_ISP_INT_MAP_M  ((INTERRUPT_CORE1_ISP_INT_MAP_V)<<(INTERRUPT_CORE1_ISP_INT_MAP_S))
-#define INTERRUPT_CORE1_ISP_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_ISP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x190)
+/** INTERRUPT_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_ISP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ISP_INT_MAP_M  (INTERRUPT_CORE1_ISP_INT_MAP_V << INTERRUPT_CORE1_ISP_INT_MAP_S)
+#define INTERRUPT_CORE1_ISP_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_ISP_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x194)
-/* INTERRUPT_CORE1_I3C_MST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_I3C_MST_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_I3C_MST_INT_MAP_M  ((INTERRUPT_CORE1_I3C_MST_INT_MAP_V)<<(INTERRUPT_CORE1_I3C_MST_INT_MAP_S))
-#define INTERRUPT_CORE1_I3C_MST_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_I3C_MST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x194)
+/** INTERRUPT_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_M  (INTERRUPT_CORE1_I3C_MST_INT_MAP_V << INTERRUPT_CORE1_I3C_MST_INT_MAP_S)
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_I3C_MST_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x198)
-/* INTERRUPT_CORE1_I3C_SLV_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_I3C_SLV_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_M  ((INTERRUPT_CORE1_I3C_SLV_INT_MAP_V)<<(INTERRUPT_CORE1_I3C_SLV_INT_MAP_S))
-#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x198)
+/** INTERRUPT_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_M  (INTERRUPT_CORE1_I3C_SLV_INT_MAP_V << INTERRUPT_CORE1_I3C_SLV_INT_MAP_S)
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_I3C_SLV_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x19C)
-/* INTERRUPT_CORE1_USB_OTG11_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_USB_OTG11_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_M  ((INTERRUPT_CORE1_USB_OTG11_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG11_INT_MAP_S))
-#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19c)
+/** INTERRUPT_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_M  (INTERRUPT_CORE1_USB_OTG11_INT_MAP_V << INTERRUPT_CORE1_USB_OTG11_INT_MAP_S)
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_USB_OTG11_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1A0)
-/* INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a0)
+/** INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_M  (INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1A4)
-/* INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a4)
+/** INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_M  (INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1A8)
-/* INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a8)
+/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_M  (INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1AC)
-/* INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ac)
+/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_M  (INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1B0)
-/* INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b0)
+/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_M  (INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1B4)
-/* INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_M  ((INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V)<<(INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S))
-#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b4)
+/** INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_M  (INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V << INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1B8)
-/* INTERRUPT_CORE1_HP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_M  ((INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S))
-#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b8)
+/** INTERRUPT_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_M  (INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V << INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_PCNT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1BC)
-/* INTERRUPT_CORE1_PCNT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_PCNT_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_PCNT_INT_MAP_M  ((INTERRUPT_CORE1_PCNT_INT_MAP_V)<<(INTERRUPT_CORE1_PCNT_INT_MAP_S))
-#define INTERRUPT_CORE1_PCNT_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_PCNT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1bc)
+/** INTERRUPT_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_PCNT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PCNT_INT_MAP_M  (INTERRUPT_CORE1_PCNT_INT_MAP_V << INTERRUPT_CORE1_PCNT_INT_MAP_S)
+#define INTERRUPT_CORE1_PCNT_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_PCNT_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C0)
-/* INTERRUPT_CORE1_HP_PAU_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_HP_PAU_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_HP_PAU_INT_MAP_M  ((INTERRUPT_CORE1_HP_PAU_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PAU_INT_MAP_S))
-#define INTERRUPT_CORE1_HP_PAU_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_HP_PAU_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c0)
+/** INTERRUPT_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_M  (INTERRUPT_CORE1_HP_PAU_INT_MAP_V << INTERRUPT_CORE1_HP_PAU_INT_MAP_S)
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_HP_PAU_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C4)
-/* INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_M  ((INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S))
-#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c4)
+/** INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_M  (INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V << INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S)
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1C8)
-/* INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_M  ((INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S))
-#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c8)
+/** INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_M  (INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V << INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S)
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1CC)
-/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1cc)
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1D0)
-/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d0)
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1D4)
-/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d4)
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1D8)
-/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d8)
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1DC)
-/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1dc)
+/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1E0)
-/* INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e0)
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1E4)
-/* INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e4)
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1E8)
-/* INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e8)
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1EC)
-/* INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ec)
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1F0)
-/* INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f0)
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1F4)
-/* INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M  ((INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f4)
+/** INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M  (INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1F8)
-/* INTERRUPT_CORE1_H264_REG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_H264_REG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_H264_REG_INT_MAP_M  ((INTERRUPT_CORE1_H264_REG_INT_MAP_V)<<(INTERRUPT_CORE1_H264_REG_INT_MAP_S))
-#define INTERRUPT_CORE1_H264_REG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_H264_REG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f8)
+/** INTERRUPT_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_REG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_M  (INTERRUPT_CORE1_H264_REG_INT_MAP_V << INTERRUPT_CORE1_H264_REG_INT_MAP_S)
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_H264_REG_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x1FC)
-/* INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP    0x0000003F
-#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_M  ((INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V)<<(INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S))
-#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V  0x3F
+/** INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1fc)
+/** INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_M  (INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V << INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S)
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V  0x0000003FU
 #define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S  0
 
-#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x200)
-/* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_INTR_STATUS_0    0xFFFFFFFF
-#define INTERRUPT_CORE1_INTR_STATUS_0_M  ((INTERRUPT_CORE1_INTR_STATUS_0_V)<<(INTERRUPT_CORE1_INTR_STATUS_0_S))
-#define INTERRUPT_CORE1_INTR_STATUS_0_V  0xFFFFFFFF
+/** INTERRUPT_CORE1_INTR_STATUS_REG_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x200)
+/** INTERRUPT_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INTR_STATUS_0_M  (INTERRUPT_CORE1_INTR_STATUS_0_V << INTERRUPT_CORE1_INTR_STATUS_0_S)
+#define INTERRUPT_CORE1_INTR_STATUS_0_V  0xFFFFFFFFU
 #define INTERRUPT_CORE1_INTR_STATUS_0_S  0
 
-#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x204)
-/* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_INTR_STATUS_1    0xFFFFFFFF
-#define INTERRUPT_CORE1_INTR_STATUS_1_M  ((INTERRUPT_CORE1_INTR_STATUS_1_V)<<(INTERRUPT_CORE1_INTR_STATUS_1_S))
-#define INTERRUPT_CORE1_INTR_STATUS_1_V  0xFFFFFFFF
+/** INTERRUPT_CORE1_INTR_STATUS_REG_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x204)
+/** INTERRUPT_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INTR_STATUS_1_M  (INTERRUPT_CORE1_INTR_STATUS_1_V << INTERRUPT_CORE1_INTR_STATUS_1_S)
+#define INTERRUPT_CORE1_INTR_STATUS_1_V  0xFFFFFFFFU
 #define INTERRUPT_CORE1_INTR_STATUS_1_S  0
 
-#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x208)
-/* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_INTR_STATUS_2    0xFFFFFFFF
-#define INTERRUPT_CORE1_INTR_STATUS_2_M  ((INTERRUPT_CORE1_INTR_STATUS_2_V)<<(INTERRUPT_CORE1_INTR_STATUS_2_S))
-#define INTERRUPT_CORE1_INTR_STATUS_2_V  0xFFFFFFFF
+/** INTERRUPT_CORE1_INTR_STATUS_REG_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x208)
+/** INTERRUPT_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INTR_STATUS_2_M  (INTERRUPT_CORE1_INTR_STATUS_2_V << INTERRUPT_CORE1_INTR_STATUS_2_S)
+#define INTERRUPT_CORE1_INTR_STATUS_2_V  0xFFFFFFFFU
 #define INTERRUPT_CORE1_INTR_STATUS_2_S  0
 
-#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x20C)
-/* INTERRUPT_CORE1_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_INTR_STATUS_3    0xFFFFFFFF
-#define INTERRUPT_CORE1_INTR_STATUS_3_M  ((INTERRUPT_CORE1_INTR_STATUS_3_V)<<(INTERRUPT_CORE1_INTR_STATUS_3_S))
-#define INTERRUPT_CORE1_INTR_STATUS_3_V  0xFFFFFFFF
+/** INTERRUPT_CORE1_INTR_STATUS_REG_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20c)
+/** INTERRUPT_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INTR_STATUS_3_M  (INTERRUPT_CORE1_INTR_STATUS_3_V << INTERRUPT_CORE1_INTR_STATUS_3_S)
+#define INTERRUPT_CORE1_INTR_STATUS_3_V  0xFFFFFFFFU
 #define INTERRUPT_CORE1_INTR_STATUS_3_S  0
 
-#define INTERRUPT_CORE1_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x210)
-/* INTERRUPT_CORE1_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
+/** INTERRUPT_CORE1_CLOCK_GATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x210)
+/** INTERRUPT_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
 #define INTERRUPT_CORE1_REG_CLK_EN    (BIT(0))
-#define INTERRUPT_CORE1_REG_CLK_EN_M  (BIT(0))
-#define INTERRUPT_CORE1_REG_CLK_EN_V  0x1
+#define INTERRUPT_CORE1_REG_CLK_EN_M  (INTERRUPT_CORE1_REG_CLK_EN_V << INTERRUPT_CORE1_REG_CLK_EN_S)
+#define INTERRUPT_CORE1_REG_CLK_EN_V  0x00000001U
 #define INTERRUPT_CORE1_REG_CLK_EN_S  0
 
-#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG          (DR_REG_INTERRUPT_CORE1_BASE + 0x3FC)
-/* INTERRUPT_CORE1_INTERRUPT_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
-/*description: .*/
-#define INTERRUPT_CORE1_INTERRUPT_REG_DATE    0x0FFFFFFF
-#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_M  ((INTERRUPT_CORE1_INTERRUPT_REG_DATE_V)<<(INTERRUPT_CORE1_INTERRUPT_REG_DATE_S))
-#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_V  0xFFFFFFF
+/** INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3fc)
+/** INTERRUPT_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752;
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_M  (INTERRUPT_CORE1_INTERRUPT_REG_DATE_V << INTERRUPT_CORE1_INTERRUPT_REG_DATE_S)
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
 #define INTERRUPT_CORE1_INTERRUPT_REG_DATE_S  0
 
-
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_INTERRUPT_CORE1_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_struct.h b/components/soc/esp32p4/include/soc/interrupt_core1_struct.h
new file mode 100644
index 0000000000..8ded5f7582
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/interrupt_core1_struct.h
@@ -0,0 +1,2298 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: INTERRUPT CORE1LP RTC INT MAP REG */
+/** Type of lp_rtc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_rtc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_rtc_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP WDT INT MAP REG */
+/** Type of lp_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_wdt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_wdt_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP TIMER REG 0 INT MAP REG */
+/** Type of lp_timer_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_timer_reg_0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_timer_reg_0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP TIMER REG 1 INT MAP REG */
+/** Type of lp_timer_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_timer_reg_1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_timer_reg_1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1MB HP INT MAP REG */
+/** Type of mb_hp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_mb_hp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_mb_hp_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1MB LP INT MAP REG */
+/** Type of mb_lp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_mb_lp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_mb_lp_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PMU REG 0 INT MAP REG */
+/** Type of pmu_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_pmu_reg_0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_pmu_reg_0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PMU REG 1 INT MAP REG */
+/** Type of pmu_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_pmu_reg_1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_pmu_reg_1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP ANAPERI INT MAP REG */
+/** Type of lp_anaperi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_anaperi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_anaperi_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP ADC INT MAP REG */
+/** Type of lp_adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_adc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_adc_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP GPIO INT MAP REG */
+/** Type of lp_gpio_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_gpio_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_gpio_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP I2C INT MAP REG */
+/** Type of lp_i2c_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_i2c_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_i2c_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP I2S INT MAP REG */
+/** Type of lp_i2s_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_i2s_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_i2s_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP SPI INT MAP REG */
+/** Type of lp_spi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_spi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_spi_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP TOUCH INT MAP REG */
+/** Type of lp_touch_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_touch_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_touch_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP TSENS INT MAP REG */
+/** Type of lp_tsens_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_tsens_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_tsens_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP UART INT MAP REG */
+/** Type of lp_uart_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_uart_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_uart_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP EFUSE INT MAP REG */
+/** Type of lp_efuse_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_efuse_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_efuse_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP SW INT MAP REG */
+/** Type of lp_sw_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_sw_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_sw_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP SYSREG INT MAP REG */
+/** Type of lp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_sysreg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_sysreg_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LP HUK INT MAP REG */
+/** Type of lp_huk_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lp_huk_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lp_huk_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SYS ICM INT MAP REG */
+/** Type of sys_icm_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_sys_icm_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_sys_icm_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1USB DEVICE INT MAP REG */
+/** Type of usb_device_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_usb_device_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_usb_device_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SDIO HOST INT MAP REG */
+/** Type of sdio_host_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_sdio_host_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_sdio_host_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1GDMA INT MAP REG */
+/** Type of gdma_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_gdma_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_gdma_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SPI2 INT MAP REG */
+/** Type of spi2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_spi2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_spi2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SPI3 INT MAP REG */
+/** Type of spi3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_spi3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_spi3_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1I2S0 INT MAP REG */
+/** Type of i2s0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_i2s0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_i2s0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1I2S1 INT MAP REG */
+/** Type of i2s1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_i2s1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_i2s1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1I2S2 INT MAP REG */
+/** Type of i2s2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_i2s2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_i2s2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1UHCI0 INT MAP REG */
+/** Type of uhci0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_uhci0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_uhci0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1UART0 INT MAP REG */
+/** Type of uart0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_uart0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_uart0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1UART1 INT MAP REG */
+/** Type of uart1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_uart1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_uart1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1UART2 INT MAP REG */
+/** Type of uart2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_uart2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_uart2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1UART3 INT MAP REG */
+/** Type of uart3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_uart3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_uart3_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1UART4 INT MAP REG */
+/** Type of uart4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_uart4_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_uart4_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LCD CAM INT MAP REG */
+/** Type of lcd_cam_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lcd_cam_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lcd_cam_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1ADC INT MAP REG */
+/** Type of adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_adc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_adc_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PWM0 INT MAP REG */
+/** Type of pwm0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_pwm0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_pwm0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PWM1 INT MAP REG */
+/** Type of pwm1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_pwm1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_pwm1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CAN0 INT MAP REG */
+/** Type of can0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_can0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_can0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_can0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CAN1 INT MAP REG */
+/** Type of can1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_can1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_can1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_can1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CAN2 INT MAP REG */
+/** Type of can2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_can2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_can2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_can2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1RMT INT MAP REG */
+/** Type of rmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_rmt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_rmt_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1I2C0 INT MAP REG */
+/** Type of i2c0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_i2c0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_i2c0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1I2C1 INT MAP REG */
+/** Type of i2c1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_i2c1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_i2c1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1TIMERGRP0 T0 INT MAP REG */
+/** Type of timergrp0_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_timergrp0_t0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp0_t0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1TIMERGRP0 T1 INT MAP REG */
+/** Type of timergrp0_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_timergrp0_t1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp0_t1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1TIMERGRP0 WDT INT MAP REG */
+/** Type of timergrp0_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_timergrp0_wdt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp0_wdt_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1TIMERGRP1 T0 INT MAP REG */
+/** Type of timergrp1_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_timergrp1_t0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp1_t0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1TIMERGRP1 T1 INT MAP REG */
+/** Type of timergrp1_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_timergrp1_t1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp1_t1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1TIMERGRP1 WDT INT MAP REG */
+/** Type of timergrp1_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_timergrp1_wdt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp1_wdt_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LEDC INT MAP REG */
+/** Type of ledc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ledc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ledc_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SYSTIMER TARGET0 INT MAP REG */
+/** Type of systimer_target0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_systimer_target0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_systimer_target0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SYSTIMER TARGET1 INT MAP REG */
+/** Type of systimer_target1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_systimer_target1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_systimer_target1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SYSTIMER TARGET2 INT MAP REG */
+/** Type of systimer_target2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_systimer_target2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_systimer_target2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AHB PDMA IN CH0 INT MAP REG */
+/** Type of ahb_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ahb_pdma_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AHB PDMA IN CH1 INT MAP REG */
+/** Type of ahb_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ahb_pdma_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AHB PDMA IN CH2 INT MAP REG */
+/** Type of ahb_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ahb_pdma_in_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AHB PDMA OUT CH0 INT MAP REG */
+/** Type of ahb_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ahb_pdma_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AHB PDMA OUT CH1 INT MAP REG */
+/** Type of ahb_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ahb_pdma_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AHB PDMA OUT CH2 INT MAP REG */
+/** Type of ahb_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ahb_pdma_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AXI PDMA IN CH0 INT MAP REG */
+/** Type of axi_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_axi_pdma_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AXI PDMA IN CH1 INT MAP REG */
+/** Type of axi_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_axi_pdma_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AXI PDMA IN CH2 INT MAP REG */
+/** Type of axi_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_axi_pdma_in_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AXI PDMA OUT CH0 INT MAP REG */
+/** Type of axi_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_axi_pdma_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AXI PDMA OUT CH1 INT MAP REG */
+/** Type of axi_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_axi_pdma_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AXI PDMA OUT CH2 INT MAP REG */
+/** Type of axi_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_axi_pdma_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1RSA INT MAP REG */
+/** Type of rsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_rsa_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_rsa_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1AES INT MAP REG */
+/** Type of aes_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_aes_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_aes_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_aes_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SHA INT MAP REG */
+/** Type of sha_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_sha_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_sha_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_sha_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1ECC INT MAP REG */
+/** Type of ecc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ecc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ecc_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1ECDSA INT MAP REG */
+/** Type of ecdsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ecdsa_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ecdsa_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1KM INT MAP REG */
+/** Type of km_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_km_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_km_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_km_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1GPIO INT0 MAP REG */
+/** Type of gpio_int0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_gpio_int0_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_int0_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1GPIO INT1 MAP REG */
+/** Type of gpio_int1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_gpio_int1_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_int1_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1GPIO INT2 MAP REG */
+/** Type of gpio_int2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_gpio_int2_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_int2_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1GPIO INT3 MAP REG */
+/** Type of gpio_int3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_gpio_int3_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_int3_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1GPIO PAD COMP INT MAP REG */
+/** Type of gpio_pad_comp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_gpio_pad_comp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_pad_comp_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CPU INT FROM CPU 0 MAP REG */
+/** Type of cpu_int_from_cpu_0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_cpu_int_from_cpu_0_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_int_from_cpu_0_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CPU INT FROM CPU 1 MAP REG */
+/** Type of cpu_int_from_cpu_1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_cpu_int_from_cpu_1_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_int_from_cpu_1_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CPU INT FROM CPU 2 MAP REG */
+/** Type of cpu_int_from_cpu_2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_cpu_int_from_cpu_2_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_int_from_cpu_2_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CPU INT FROM CPU 3 MAP REG */
+/** Type of cpu_int_from_cpu_3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_cpu_int_from_cpu_3_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_int_from_cpu_3_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CACHE INT MAP REG */
+/** Type of cache_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_cache_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_cache_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_cache_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1FLASH MSPI INT MAP REG */
+/** Type of flash_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_flash_mspi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_flash_mspi_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CSI BRIDGE INT MAP REG */
+/** Type of csi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_csi_bridge_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_csi_bridge_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1DSI BRIDGE INT MAP REG */
+/** Type of dsi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_dsi_bridge_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_dsi_bridge_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CSI INT MAP REG */
+/** Type of csi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_csi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_csi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_csi_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1DSI INT MAP REG */
+/** Type of dsi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_dsi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_dsi_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1GMII PHY INT MAP REG */
+/** Type of gmii_phy_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_gmii_phy_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_gmii_phy_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1LPI INT MAP REG */
+/** Type of lpi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_lpi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_lpi_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PMT INT MAP REG */
+/** Type of pmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_pmt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_pmt_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1SBD INT MAP REG */
+/** Type of sbd_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_sbd_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_sbd_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1USB OTG INT MAP REG */
+/** Type of usb_otg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_usb_otg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_usb_otg_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1USB OTG ENDP MULTI PROC INT MAP REG */
+/** Type of usb_otg_endp_multi_proc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_usb_otg_endp_multi_proc_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_usb_otg_endp_multi_proc_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1JPEG INT MAP REG */
+/** Type of jpeg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_jpeg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_jpeg_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PPA INT MAP REG */
+/** Type of ppa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_ppa_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_ppa_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1CORE0 TRACE INT MAP REG */
+/** Type of core0_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_core0_trace_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_core0_trace_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1TRACE INT MAP REG */
+/** Type of interrupt_core1_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_trace_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_trace_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1HP CORE CTRL INT MAP REG */
+/** Type of hp_core_ctrl_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_hp_core_ctrl_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_hp_core_ctrl_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1ISP INT MAP REG */
+/** Type of isp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_isp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_isp_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_isp_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1I3C MST INT MAP REG */
+/** Type of i3c_mst_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_i3c_mst_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_i3c_mst_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1I3C SLV INT MAP REG */
+/** Type of i3c_slv_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_i3c_slv_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_i3c_slv_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1USB OTG11 INT MAP REG */
+/** Type of usb_otg11_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_usb_otg11_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_usb_otg11_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1DMA2D IN CH0 INT MAP REG */
+/** Type of dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_dma2d_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1DMA2D IN CH1 INT MAP REG */
+/** Type of dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_dma2d_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1DMA2D OUT CH0 INT MAP REG */
+/** Type of dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_dma2d_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1DMA2D OUT CH1 INT MAP REG */
+/** Type of dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_dma2d_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1DMA2D OUT CH2 INT MAP REG */
+/** Type of dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_dma2d_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PSRAM MSPI INT MAP REG */
+/** Type of psram_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_psram_mspi_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_psram_mspi_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1HP SYSREG INT MAP REG */
+/** Type of hp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_hp_sysreg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_hp_sysreg_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1PCNT INT MAP REG */
+/** Type of pcnt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_pcnt_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_pcnt_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1HP PAU INT MAP REG */
+/** Type of hp_pau_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_hp_pau_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_hp_pau_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1HP PARLIO RX INT MAP REG */
+/** Type of hp_parlio_rx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_hp_parlio_rx_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_hp_parlio_rx_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1HP PARLIO TX INT MAP REG */
+/** Type of hp_parlio_tx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_hp_parlio_tx_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_hp_parlio_tx_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D OUT CH0 INT MAP REG */
+/** Type of h264_dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_out_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D OUT CH1 INT MAP REG */
+/** Type of h264_dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_out_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D OUT CH2 INT MAP REG */
+/** Type of h264_dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_out_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D OUT CH3 INT MAP REG */
+/** Type of h264_dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_out_ch3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D OUT CH4 INT MAP REG */
+/** Type of h264_dma2d_out_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_out_ch4_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_out_ch4_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D IN CH0 INT MAP REG */
+/** Type of h264_dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_in_ch0_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D IN CH1 INT MAP REG */
+/** Type of h264_dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_in_ch1_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D IN CH2 INT MAP REG */
+/** Type of h264_dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_in_ch2_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D IN CH3 INT MAP REG */
+/** Type of h264_dma2d_in_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_in_ch3_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_in_ch3_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D IN CH4 INT MAP REG */
+/** Type of h264_dma2d_in_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_in_ch4_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_in_ch4_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 DMA2D IN CH5 INT MAP REG */
+/** Type of h264_dma2d_in_ch5_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_dma2d_in_ch5_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_dma2d_in_ch5_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1H264 REG INT MAP REG */
+/** Type of h264_reg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_h264_reg_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_h264_reg_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1ASSIST DEBUG INT MAP REG */
+/** Type of assist_debug_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_assist_debug_int_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} interrupt_core1_assist_debug_int_map_reg_t;
+
+
+/** Group: INTERRUPT CORE1INTR STATUS REG 0 REG */
+/** Type of intr_status_reg_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_intr_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_intr_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core1_intr_status_reg_0_reg_t;
+
+
+/** Group: INTERRUPT CORE1INTR STATUS REG 1 REG */
+/** Type of intr_status_reg_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_intr_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_intr_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core1_intr_status_reg_1_reg_t;
+
+
+/** Group: INTERRUPT CORE1INTR STATUS REG 2 REG */
+/** Type of intr_status_reg_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_intr_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_intr_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core1_intr_status_reg_2_reg_t;
+
+
+/** Group: INTERRUPT CORE1INTR STATUS REG 3 REG */
+/** Type of intr_status_reg_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_intr_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t interrupt_core1_intr_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core1_intr_status_reg_3_reg_t;
+
+
+/** Group: INTERRUPT CORE1CLOCK GATE REG */
+/** Type of clock_gate register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t interrupt_core1_reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} interrupt_core1_clock_gate_reg_t;
+
+
+/** Group: INTERRUPT CORE1INTERRUPT REG DATE REG */
+/** Type of interrupt_reg_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** interrupt_core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752;
+         *  NA
+         */
+        uint32_t interrupt_core1_interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} interrupt_core1_interrupt_reg_date_reg_t;
+
+
+typedef struct {
+    volatile interrupt_core1_lp_rtc_int_map_reg_t lp_rtc_int_map;
+    volatile interrupt_core1_lp_wdt_int_map_reg_t lp_wdt_int_map;
+    volatile interrupt_core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map;
+    volatile interrupt_core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map;
+    volatile interrupt_core1_mb_hp_int_map_reg_t mb_hp_int_map;
+    volatile interrupt_core1_mb_lp_int_map_reg_t mb_lp_int_map;
+    volatile interrupt_core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map;
+    volatile interrupt_core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map;
+    volatile interrupt_core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map;
+    volatile interrupt_core1_lp_adc_int_map_reg_t lp_adc_int_map;
+    volatile interrupt_core1_lp_gpio_int_map_reg_t lp_gpio_int_map;
+    volatile interrupt_core1_lp_i2c_int_map_reg_t lp_i2c_int_map;
+    volatile interrupt_core1_lp_i2s_int_map_reg_t lp_i2s_int_map;
+    volatile interrupt_core1_lp_spi_int_map_reg_t lp_spi_int_map;
+    volatile interrupt_core1_lp_touch_int_map_reg_t lp_touch_int_map;
+    volatile interrupt_core1_lp_tsens_int_map_reg_t lp_tsens_int_map;
+    volatile interrupt_core1_lp_uart_int_map_reg_t lp_uart_int_map;
+    volatile interrupt_core1_lp_efuse_int_map_reg_t lp_efuse_int_map;
+    volatile interrupt_core1_lp_sw_int_map_reg_t lp_sw_int_map;
+    volatile interrupt_core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map;
+    volatile interrupt_core1_lp_huk_int_map_reg_t lp_huk_int_map;
+    volatile interrupt_core1_sys_icm_int_map_reg_t sys_icm_int_map;
+    volatile interrupt_core1_usb_device_int_map_reg_t usb_device_int_map;
+    volatile interrupt_core1_sdio_host_int_map_reg_t sdio_host_int_map;
+    volatile interrupt_core1_gdma_int_map_reg_t gdma_int_map;
+    volatile interrupt_core1_spi2_int_map_reg_t spi2_int_map;
+    volatile interrupt_core1_spi3_int_map_reg_t spi3_int_map;
+    volatile interrupt_core1_i2s0_int_map_reg_t i2s0_int_map;
+    volatile interrupt_core1_i2s1_int_map_reg_t i2s1_int_map;
+    volatile interrupt_core1_i2s2_int_map_reg_t i2s2_int_map;
+    volatile interrupt_core1_uhci0_int_map_reg_t uhci0_int_map;
+    volatile interrupt_core1_uart0_int_map_reg_t uart0_int_map;
+    volatile interrupt_core1_uart1_int_map_reg_t uart1_int_map;
+    volatile interrupt_core1_uart2_int_map_reg_t uart2_int_map;
+    volatile interrupt_core1_uart3_int_map_reg_t uart3_int_map;
+    volatile interrupt_core1_uart4_int_map_reg_t uart4_int_map;
+    volatile interrupt_core1_lcd_cam_int_map_reg_t lcd_cam_int_map;
+    volatile interrupt_core1_adc_int_map_reg_t adc_int_map;
+    volatile interrupt_core1_pwm0_int_map_reg_t pwm0_int_map;
+    volatile interrupt_core1_pwm1_int_map_reg_t pwm1_int_map;
+    volatile interrupt_core1_can0_int_map_reg_t can0_int_map;
+    volatile interrupt_core1_can1_int_map_reg_t can1_int_map;
+    volatile interrupt_core1_can2_int_map_reg_t can2_int_map;
+    volatile interrupt_core1_rmt_int_map_reg_t rmt_int_map;
+    volatile interrupt_core1_i2c0_int_map_reg_t i2c0_int_map;
+    volatile interrupt_core1_i2c1_int_map_reg_t i2c1_int_map;
+    volatile interrupt_core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map;
+    volatile interrupt_core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map;
+    volatile interrupt_core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map;
+    volatile interrupt_core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map;
+    volatile interrupt_core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map;
+    volatile interrupt_core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map;
+    volatile interrupt_core1_ledc_int_map_reg_t ledc_int_map;
+    volatile interrupt_core1_systimer_target0_int_map_reg_t systimer_target0_int_map;
+    volatile interrupt_core1_systimer_target1_int_map_reg_t systimer_target1_int_map;
+    volatile interrupt_core1_systimer_target2_int_map_reg_t systimer_target2_int_map;
+    volatile interrupt_core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map;
+    volatile interrupt_core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map;
+    volatile interrupt_core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map;
+    volatile interrupt_core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map;
+    volatile interrupt_core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map;
+    volatile interrupt_core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map;
+    volatile interrupt_core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map;
+    volatile interrupt_core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map;
+    volatile interrupt_core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map;
+    volatile interrupt_core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map;
+    volatile interrupt_core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map;
+    volatile interrupt_core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map;
+    volatile interrupt_core1_rsa_int_map_reg_t rsa_int_map;
+    volatile interrupt_core1_aes_int_map_reg_t aes_int_map;
+    volatile interrupt_core1_sha_int_map_reg_t sha_int_map;
+    volatile interrupt_core1_ecc_int_map_reg_t ecc_int_map;
+    volatile interrupt_core1_ecdsa_int_map_reg_t ecdsa_int_map;
+    volatile interrupt_core1_km_int_map_reg_t km_int_map;
+    volatile interrupt_core1_gpio_int0_map_reg_t gpio_int0_map;
+    volatile interrupt_core1_gpio_int1_map_reg_t gpio_int1_map;
+    volatile interrupt_core1_gpio_int2_map_reg_t gpio_int2_map;
+    volatile interrupt_core1_gpio_int3_map_reg_t gpio_int3_map;
+    volatile interrupt_core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map;
+    volatile interrupt_core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map;
+    volatile interrupt_core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map;
+    volatile interrupt_core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map;
+    volatile interrupt_core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map;
+    volatile interrupt_core1_cache_int_map_reg_t cache_int_map;
+    volatile interrupt_core1_flash_mspi_int_map_reg_t flash_mspi_int_map;
+    volatile interrupt_core1_csi_bridge_int_map_reg_t csi_bridge_int_map;
+    volatile interrupt_core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map;
+    volatile interrupt_core1_csi_int_map_reg_t csi_int_map;
+    volatile interrupt_core1_dsi_int_map_reg_t dsi_int_map;
+    volatile interrupt_core1_gmii_phy_int_map_reg_t gmii_phy_int_map;
+    volatile interrupt_core1_lpi_int_map_reg_t lpi_int_map;
+    volatile interrupt_core1_pmt_int_map_reg_t pmt_int_map;
+    volatile interrupt_core1_sbd_int_map_reg_t sbd_int_map;
+    volatile interrupt_core1_usb_otg_int_map_reg_t usb_otg_int_map;
+    volatile interrupt_core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map;
+    volatile interrupt_core1_jpeg_int_map_reg_t jpeg_int_map;
+    volatile interrupt_core1_ppa_int_map_reg_t ppa_int_map;
+    volatile interrupt_core1_core0_trace_int_map_reg_t core0_trace_int_map;
+    volatile interrupt_core1_trace_int_map_reg_t interrupt_core1_trace_int_map;
+    volatile interrupt_core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map;
+    volatile interrupt_core1_isp_int_map_reg_t isp_int_map;
+    volatile interrupt_core1_i3c_mst_int_map_reg_t i3c_mst_int_map;
+    volatile interrupt_core1_i3c_slv_int_map_reg_t i3c_slv_int_map;
+    volatile interrupt_core1_usb_otg11_int_map_reg_t usb_otg11_int_map;
+    volatile interrupt_core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map;
+    volatile interrupt_core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map;
+    volatile interrupt_core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map;
+    volatile interrupt_core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map;
+    volatile interrupt_core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map;
+    volatile interrupt_core1_psram_mspi_int_map_reg_t psram_mspi_int_map;
+    volatile interrupt_core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map;
+    volatile interrupt_core1_pcnt_int_map_reg_t pcnt_int_map;
+    volatile interrupt_core1_hp_pau_int_map_reg_t hp_pau_int_map;
+    volatile interrupt_core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map;
+    volatile interrupt_core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map;
+    volatile interrupt_core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map;
+    volatile interrupt_core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map;
+    volatile interrupt_core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map;
+    volatile interrupt_core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map;
+    volatile interrupt_core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map;
+    volatile interrupt_core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map;
+    volatile interrupt_core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map;
+    volatile interrupt_core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map;
+    volatile interrupt_core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map;
+    volatile interrupt_core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map;
+    volatile interrupt_core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map;
+    volatile interrupt_core1_h264_reg_int_map_reg_t h264_reg_int_map;
+    volatile interrupt_core1_assist_debug_int_map_reg_t assist_debug_int_map;
+    volatile interrupt_core1_intr_status_reg_0_reg_t intr_status_reg_0;
+    volatile interrupt_core1_intr_status_reg_1_reg_t intr_status_reg_1;
+    volatile interrupt_core1_intr_status_reg_2_reg_t intr_status_reg_2;
+    volatile interrupt_core1_intr_status_reg_3_reg_t intr_status_reg_3;
+    volatile interrupt_core1_clock_gate_reg_t clock_gate;
+    uint32_t reserved_214[122];
+    volatile interrupt_core1_interrupt_reg_date_reg_t interrupt_reg_date;
+} interrupt_core1_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(interrupt_core1_dev_t) == 0x400, "Invalid size of interrupt_core1_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h b/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h
deleted file mode 100644
index 1c41e19b79..0000000000
--- a/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h
+++ /dev/null
@@ -1,999 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
-/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M  (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
-/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M  (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S)
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S  0
-
-/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
-/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M  (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S)
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S  0
-
-/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
-/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M  (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S)
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
-/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BT_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_M  (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
-/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BT_BB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_BB_INTR_MAP_M  (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
-#define INTMTX_CORE0_BT_BB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_BB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
-/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BT_BB_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_BB_NMI_MAP_M  (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
-#define INTMTX_CORE0_BT_BB_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_BB_NMI_MAP_S  0
-
-/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
-/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_COEX_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
-/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_COEX_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_COEX_INTR_MAP_M  (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
-#define INTMTX_CORE0_COEX_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_COEX_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
-/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
-/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M  (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
-/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_I2C_MST_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_M  (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S)
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_S  0
-
-/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
-/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M  (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PMU_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
-/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PMU_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PMU_INTR_MAP_M  (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
-#define INTMTX_CORE0_PMU_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PMU_INTR_MAP_S  0
-
-/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
-/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_EFUSE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_EFUSE_INTR_MAP_M  (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
-#define INTMTX_CORE0_EFUSE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_EFUSE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
-/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
-/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_UART_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_UART_INTR_MAP_M  (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S)
-#define INTMTX_CORE0_LP_UART_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_UART_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
-/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_I2C_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_M  (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S)
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
-/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_M  (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
-/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
-/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
-/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S)
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
-/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
-/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TRACE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TRACE_INTR_MAP_M  (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
-#define INTMTX_CORE0_TRACE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TRACE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
-/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CACHE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CACHE_INTR_MAP_M  (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
-#define INTMTX_CORE0_CACHE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CACHE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
-/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
-
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
-
-/** INTMTX_CORE0_PAU_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
-/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PAU_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PAU_INTR_MAP_M  (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
-#define INTMTX_CORE0_PAU_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PAU_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
-/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
-/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
-/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
-/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
-/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
-/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
-/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_APM0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_M  (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S)
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
-/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_MSPI_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_MSPI_INTR_MAP_M  (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
-#define INTMTX_CORE0_MSPI_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_MSPI_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
-/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_I2S1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2S1_INTR_MAP_M  (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
-#define INTMTX_CORE0_I2S1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2S1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
-/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_UHCI0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UHCI0_INTR_MAP_M  (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
-#define INTMTX_CORE0_UHCI0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UHCI0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UART0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
-/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_UART0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UART0_INTR_MAP_M  (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
-#define INTMTX_CORE0_UART0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UART0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UART1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
-/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_UART1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UART1_INTR_MAP_M  (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
-#define INTMTX_CORE0_UART1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UART1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
-/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LEDC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LEDC_INTR_MAP_M  (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
-#define INTMTX_CORE0_LEDC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LEDC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
-/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CAN0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CAN0_INTR_MAP_M  (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
-#define INTMTX_CORE0_CAN0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CAN0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CAN1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
-/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CAN1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CAN1_INTR_MAP_M  (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S)
-#define INTMTX_CORE0_CAN1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CAN1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_USB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
-/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_USB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_USB_INTR_MAP_M  (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
-#define INTMTX_CORE0_USB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_USB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_RMT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
-/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_RMT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_RMT_INTR_MAP_M  (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
-#define INTMTX_CORE0_RMT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_RMT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
-/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
-/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG0_T0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_M  (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
-/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG0_T1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_M  (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
-/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M  (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
-/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG1_T0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_M  (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
-/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG1_T1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_M  (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
-/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M  (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
-/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
-/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
-/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
-/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_APB_ADC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_M  (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PWM_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
-/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PWM_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PWM_INTR_MAP_M  (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
-#define INTMTX_CORE0_PWM_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PWM_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
-/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PCNT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PCNT_INTR_MAP_M  (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
-#define INTMTX_CORE0_PCNT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PCNT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
-/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PARL_IO_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S)
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SLC0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
-/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SLC0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SLC0_INTR_MAP_M  (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S)
-#define INTMTX_CORE0_SLC0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SLC0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SLC1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
-/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SLC1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SLC1_INTR_MAP_M  (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S)
-#define INTMTX_CORE0_SLC1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SLC1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
-/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
-/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
-/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114)
-/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118)
-/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c)
-/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120)
-/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_GPSPI2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_M  (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_AES_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124)
-/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_AES_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_AES_INTR_MAP_M  (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
-#define INTMTX_CORE0_AES_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_AES_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SHA_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128)
-/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SHA_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SHA_INTR_MAP_M  (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
-#define INTMTX_CORE0_SHA_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SHA_INTR_MAP_S  0
-
-/** INTMTX_CORE0_RSA_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c)
-/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_RSA_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_RSA_INTR_MAP_M  (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
-#define INTMTX_CORE0_RSA_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_RSA_INTR_MAP_S  0
-
-/** INTMTX_CORE0_ECC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130)
-/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_ECC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ECC_INTR_MAP_M  (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
-#define INTMTX_CORE0_ECC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ECC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134)
-/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_INT_STATUS_0    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_0_M  (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
-#define INTMTX_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_0_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138)
-/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_INT_STATUS_1    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_1_M  (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
-#define INTMTX_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_1_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c)
-/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_INT_STATUS_2    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_2_M  (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
-#define INTMTX_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_2_S  0
-
-/** INTMTX_CORE0_CLOCK_GATE_REG register
- *  register description
- */
-#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140)
-/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Need add description
- */
-#define INTMTX_CORE0_REG_CLK_EN    (BIT(0))
-#define INTMTX_CORE0_REG_CLK_EN_M  (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
-#define INTMTX_CORE0_REG_CLK_EN_V  0x00000001U
-#define INTMTX_CORE0_REG_CLK_EN_S  0
-
-/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
- *  register description
- */
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
-/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144;
- *  Need add description
- */
-#define INTMTX_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_M  (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h b/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h
deleted file mode 100644
index 95dff43fc6..0000000000
--- a/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h
+++ /dev/null
@@ -1,1254 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of wifi_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_mac_intr_map_reg_t;
-
-/** Type of wifi_mac_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_mac_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_mac_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_mac_nmi_map_reg_t;
-
-/** Type of wifi_pwr_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_pwr_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_pwr_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_pwr_intr_map_reg_t;
-
-/** Type of wifi_bb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_bb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_bb_intr_map_reg_t;
-
-/** Type of bt_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t bt_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_bt_mac_intr_map_reg_t;
-
-/** Type of bt_bb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t bt_bb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_bt_bb_intr_map_reg_t;
-
-/** Type of bt_bb_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t bt_bb_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_bt_bb_nmi_map_reg_t;
-
-/** Type of lp_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_timer_intr_map_reg_t;
-
-/** Type of coex_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** coex_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t coex_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_coex_intr_map_reg_t;
-
-/** Type of ble_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ble_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ble_timer_intr_map_reg_t;
-
-/** Type of ble_sec_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ble_sec_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ble_sec_intr_map_reg_t;
-
-/** Type of i2c_mst_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2c_mst_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t i2c_mst_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_i2c_mst_intr_map_reg_t;
-
-/** Type of zb_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t zb_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_zb_mac_intr_map_reg_t;
-
-/** Type of pmu_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pmu_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pmu_intr_map_reg_t;
-
-/** Type of efuse_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t efuse_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_efuse_intr_map_reg_t;
-
-/** Type of lp_rtc_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_rtc_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_rtc_timer_intr_map_reg_t;
-
-/** Type of lp_uart_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_uart_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_uart_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_uart_intr_map_reg_t;
-
-/** Type of lp_i2c_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_i2c_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_i2c_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_i2c_intr_map_reg_t;
-
-/** Type of lp_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_wdt_intr_map_reg_t;
-
-/** Type of lp_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_peri_timeout_intr_map_reg_t;
-
-/** Type of lp_apm_m0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_apm_m0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_apm_m0_intr_map_reg_t;
-
-/** Type of lp_apm_m1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_apm_m1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_apm_m1_intr_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_0_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_0_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_1_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_1_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_2_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_2_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_3_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_3_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t;
-
-/** Type of assist_debug_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t assist_debug_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_assist_debug_intr_map_reg_t;
-
-/** Type of trace_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** trace_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t trace_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_trace_intr_map_reg_t;
-
-/** Type of cache_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cache_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cache_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cache_intr_map_reg_t;
-
-/** Type of cpu_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t;
-
-/** Type of gpio_interrupt_pro_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t gpio_interrupt_pro_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_gpio_interrupt_pro_map_reg_t;
-
-/** Type of gpio_interrupt_pro_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t gpio_interrupt_pro_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t;
-
-/** Type of pau_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pau_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pau_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pau_intr_map_reg_t;
-
-/** Type of hp_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_peri_timeout_intr_map_reg_t;
-
-/** Type of modem_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t modem_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_modem_peri_timeout_intr_map_reg_t;
-
-/** Type of hp_apm_m0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m0_intr_map_reg_t;
-
-/** Type of hp_apm_m1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m1_intr_map_reg_t;
-
-/** Type of hp_apm_m2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m2_intr_map_reg_t;
-
-/** Type of hp_apm_m3_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m3_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m3_intr_map_reg_t;
-
-/** Type of lp_apm0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_apm0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_apm0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_apm0_intr_map_reg_t;
-
-/** Type of mspi_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t mspi_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_mspi_intr_map_reg_t;
-
-/** Type of i2s1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t i2s1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_i2s1_intr_map_reg_t;
-
-/** Type of uhci0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t uhci0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_uhci0_intr_map_reg_t;
-
-/** Type of uart0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t uart0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_uart0_intr_map_reg_t;
-
-/** Type of uart1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t uart1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_uart1_intr_map_reg_t;
-
-/** Type of ledc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ledc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ledc_intr_map_reg_t;
-
-/** Type of can0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** can0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t can0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_can0_intr_map_reg_t;
-
-/** Type of can1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** can1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t can1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_can1_intr_map_reg_t;
-
-/** Type of usb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** usb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t usb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_usb_intr_map_reg_t;
-
-/** Type of rmt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t rmt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_rmt_intr_map_reg_t;
-
-/** Type of i2c_ext0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t i2c_ext0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_i2c_ext0_intr_map_reg_t;
-
-/** Type of tg0_t0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg0_t0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg0_t0_intr_map_reg_t;
-
-/** Type of tg0_t1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg0_t1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg0_t1_intr_map_reg_t;
-
-/** Type of tg0_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg0_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg0_wdt_intr_map_reg_t;
-
-/** Type of tg1_t0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg1_t0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg1_t0_intr_map_reg_t;
-
-/** Type of tg1_t1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg1_t1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg1_t1_intr_map_reg_t;
-
-/** Type of tg1_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg1_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg1_wdt_intr_map_reg_t;
-
-/** Type of systimer_target0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t systimer_target0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_systimer_target0_intr_map_reg_t;
-
-/** Type of systimer_target1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t systimer_target1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_systimer_target1_intr_map_reg_t;
-
-/** Type of systimer_target2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t systimer_target2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_systimer_target2_intr_map_reg_t;
-
-/** Type of apb_adc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t apb_adc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_apb_adc_intr_map_reg_t;
-
-/** Type of pwm_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pwm_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pwm_intr_map_reg_t;
-
-/** Type of pcnt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pcnt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pcnt_intr_map_reg_t;
-
-/** Type of parl_io_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** parl_io_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t parl_io_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_parl_io_intr_map_reg_t;
-
-/** Type of slc0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** slc0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t slc0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_slc0_intr_map_reg_t;
-
-/** Type of slc1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** slc1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t slc1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_slc1_intr_map_reg_t;
-
-/** Type of dma_in_ch0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_in_ch0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_in_ch0_intr_map_reg_t;
-
-/** Type of dma_in_ch1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_in_ch1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_in_ch1_intr_map_reg_t;
-
-/** Type of dma_in_ch2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_in_ch2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_in_ch2_intr_map_reg_t;
-
-/** Type of dma_out_ch0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_out_ch0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_out_ch0_intr_map_reg_t;
-
-/** Type of dma_out_ch1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_out_ch1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_out_ch1_intr_map_reg_t;
-
-/** Type of dma_out_ch2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_out_ch2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_out_ch2_intr_map_reg_t;
-
-/** Type of gpspi2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t gpspi2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_gpspi2_intr_map_reg_t;
-
-/** Type of aes_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** aes_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t aes_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_aes_intr_map_reg_t;
-
-/** Type of sha_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** sha_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t sha_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_sha_intr_map_reg_t;
-
-/** Type of rsa_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t rsa_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_rsa_intr_map_reg_t;
-
-/** Type of ecc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ecc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ecc_intr_map_reg_t;
-
-/** Type of int_status_reg_0 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t int_status_0:32;
-    };
-    uint32_t val;
-} interrupt_matrix_int_status_reg_0_reg_t;
-
-/** Type of int_status_reg_1 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t int_status_1:32;
-    };
-    uint32_t val;
-} interrupt_matrix_int_status_reg_1_reg_t;
-
-/** Type of int_status_reg_2 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t int_status_2:32;
-    };
-    uint32_t val;
-} interrupt_matrix_int_status_reg_2_reg_t;
-
-/** Type of clock_gate register
- *  register description
- */
-typedef union {
-    struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Need add description
-         */
-        uint32_t reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} interrupt_matrix_clock_gate_reg_t;
-
-/** Type of interrupt_reg_date register
- *  register description
- */
-typedef union {
-    struct {
-        /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35664144;
-         *  Need add description
-         */
-        uint32_t interrupt_reg_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} interrupt_matrix_interrupt_reg_date_reg_t;
-
-
-typedef struct interrupt_matrix_dev_t {
-    volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map;
-    volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map;
-    volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map;
-    volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map;
-    volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map;
-    volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map;
-    volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map;
-    volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map;
-    volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map;
-    volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map;
-    volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map;
-    volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map;
-    volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map;
-    volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map;
-    volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map;
-    volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
-    volatile interrupt_matrix_lp_uart_intr_map_reg_t lp_uart_intr_map;
-    volatile interrupt_matrix_lp_i2c_intr_map_reg_t lp_i2c_intr_map;
-    volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
-    volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
-    volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
-    volatile interrupt_matrix_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
-    volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map;
-    volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map;
-    volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map;
-    volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map;
-    volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map;
-    volatile interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map;
-    volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map;
-    volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map;
-    volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map;
-    volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
-    volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
-    volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
-    volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
-    volatile interrupt_matrix_lp_apm0_intr_map_reg_t lp_apm0_intr_map;
-    volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map;
-    volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map;
-    volatile interrupt_matrix_uhci0_intr_map_reg_t uhci0_intr_map;
-    volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map;
-    volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map;
-    volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map;
-    volatile interrupt_matrix_can0_intr_map_reg_t can0_intr_map;
-    volatile interrupt_matrix_can1_intr_map_reg_t can1_intr_map;
-    volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map;
-    volatile interrupt_matrix_rmt_intr_map_reg_t rmt_intr_map;
-    volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map;
-    volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map;
-    volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map;
-    volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map;
-    volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map;
-    volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map;
-    volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map;
-    volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
-    volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
-    volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
-    volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map;
-    volatile interrupt_matrix_pwm_intr_map_reg_t pwm_intr_map;
-    volatile interrupt_matrix_pcnt_intr_map_reg_t pcnt_intr_map;
-    volatile interrupt_matrix_parl_io_intr_map_reg_t parl_io_intr_map;
-    volatile interrupt_matrix_slc0_intr_map_reg_t slc0_intr_map;
-    volatile interrupt_matrix_slc1_intr_map_reg_t slc1_intr_map;
-    volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map;
-    volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map;
-    volatile interrupt_matrix_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map;
-    volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map;
-    volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map;
-    volatile interrupt_matrix_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map;
-    volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map;
-    volatile interrupt_matrix_aes_intr_map_reg_t aes_intr_map;
-    volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map;
-    volatile interrupt_matrix_rsa_intr_map_reg_t rsa_intr_map;
-    volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map;
-    volatile interrupt_matrix_int_status_reg_0_reg_t int_status_reg_0;
-    volatile interrupt_matrix_int_status_reg_1_reg_t int_status_reg_1;
-    volatile interrupt_matrix_int_status_reg_2_reg_t int_status_reg_2;
-    volatile interrupt_matrix_clock_gate_reg_t clock_gate;
-    uint32_t reserved_144[430];
-    volatile interrupt_matrix_interrupt_reg_date_reg_t interrupt_reg_date;
-} interrupt_matrix_dev_t;
-
-extern interrupt_matrix_dev_t INTMTX;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/interrupt_reg.h b/components/soc/esp32p4/include/soc/interrupt_reg.h
index 4290233051..b799b19144 100644
--- a/components/soc/esp32p4/include/soc/interrupt_reg.h
+++ b/components/soc/esp32p4/include/soc/interrupt_reg.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,6 @@
 #include "soc/clic_reg.h"
 #include "soc/soc_caps.h"
 
-// ESP32P4 should use the CLIC controller as the interrupt controller instead of INTC (SOC_INT_CLIC_SUPPORTED = y)
+// ESP32P4 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
 #define INTERRUPT_CORE0_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG
 #define INTERRUPT_CORE1_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG
diff --git a/components/soc/esp32p4/include/soc/intpri_reg.h b/components/soc/esp32p4/include/soc/intpri_reg.h
deleted file mode 100644
index 25c3acccaa..0000000000
--- a/components/soc/esp32p4/include/soc/intpri_reg.h
+++ /dev/null
@@ -1,574 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** INTPRI_CORE0_CPU_INT_ENABLE_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0)
-/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_INT_ENABLE    0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_ENABLE_M  (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S)
-#define INTPRI_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_ENABLE_S  0
-
-/** INTPRI_CORE0_CPU_INT_TYPE_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4)
-/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_INT_TYPE    0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_TYPE_M  (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S)
-#define INTPRI_CORE0_CPU_INT_TYPE_V  0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_TYPE_S  0
-
-/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8)
-/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_INT_EIP_STATUS    0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M  (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S)
-#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_0_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc)
-/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_0_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_0_MAP_M  (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_0_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_0_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_1_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10)
-/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_1_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_1_MAP_M  (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_1_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_1_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_2_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14)
-/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_2_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_2_MAP_M  (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_2_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_2_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_3_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18)
-/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_3_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_3_MAP_M  (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_3_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_3_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_4_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c)
-/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_4_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_4_MAP_M  (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_4_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_4_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_5_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20)
-/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_5_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_5_MAP_M  (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_5_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_5_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_6_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24)
-/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_6_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_6_MAP_M  (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_6_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_6_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_7_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28)
-/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_7_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_7_MAP_M  (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_7_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_7_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_8_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c)
-/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_8_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_8_MAP_M  (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_8_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_8_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_9_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30)
-/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_9_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_9_MAP_M  (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_9_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_9_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_10_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34)
-/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_10_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_10_MAP_M  (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_10_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_10_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_11_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38)
-/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_11_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_11_MAP_M  (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_11_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_11_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_12_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c)
-/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_12_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_12_MAP_M  (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_12_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_12_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_13_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40)
-/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_13_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_13_MAP_M  (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_13_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_13_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_14_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44)
-/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_14_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_14_MAP_M  (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_14_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_14_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_15_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48)
-/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_15_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_15_MAP_M  (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_15_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_15_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_16_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c)
-/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_16_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_16_MAP_M  (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_16_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_16_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_17_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50)
-/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_17_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_17_MAP_M  (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_17_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_17_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_18_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54)
-/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_18_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_18_MAP_M  (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_18_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_18_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_19_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58)
-/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_19_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_19_MAP_M  (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_19_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_19_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_20_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c)
-/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_20_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_20_MAP_M  (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_20_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_20_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_21_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60)
-/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_21_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_21_MAP_M  (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_21_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_21_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_22_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64)
-/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_22_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_22_MAP_M  (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_22_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_22_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_23_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68)
-/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_23_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_23_MAP_M  (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_23_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_23_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_24_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c)
-/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_24_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_24_MAP_M  (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_24_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_24_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_25_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70)
-/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_25_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_25_MAP_M  (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_25_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_25_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_26_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74)
-/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_26_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_26_MAP_M  (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_26_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_26_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_27_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78)
-/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_27_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_27_MAP_M  (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_27_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_27_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_28_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c)
-/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_28_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_28_MAP_M  (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_28_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_28_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_29_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80)
-/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_29_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_29_MAP_M  (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_29_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_29_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_30_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84)
-/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_30_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_30_MAP_M  (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_30_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_30_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_PRI_31_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88)
-/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_PRI_31_MAP    0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_31_MAP_M  (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S)
-#define INTPRI_CORE0_CPU_PRI_31_MAP_V  0x0000000FU
-#define INTPRI_CORE0_CPU_PRI_31_MAP_S  0
-
-/** INTPRI_CORE0_CPU_INT_THRESH_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c)
-/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_INT_THRESH    0x000000FFU
-#define INTPRI_CORE0_CPU_INT_THRESH_M  (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S)
-#define INTPRI_CORE0_CPU_INT_THRESH_V  0x000000FFU
-#define INTPRI_CORE0_CPU_INT_THRESH_S  0
-
-/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
-/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_0    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_0_M  (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
-#define INTPRI_CPU_INTR_FROM_CPU_0_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_0_S  0
-
-/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
-/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_1    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_1_M  (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
-#define INTPRI_CPU_INTR_FROM_CPU_1_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_1_S  0
-
-/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
-/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_2    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_2_M  (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
-#define INTPRI_CPU_INTR_FROM_CPU_2_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_2_S  0
-
-/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
-/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_3    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_3_M  (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
-#define INTPRI_CPU_INTR_FROM_CPU_3_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_3_S  0
-
-/** INTPRI_DATE_REG register
- *  register description
- */
-#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
-/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35655824;
- *  Need add description
- */
-#define INTPRI_DATE    0x0FFFFFFFU
-#define INTPRI_DATE_M  (INTPRI_DATE_V << INTPRI_DATE_S)
-#define INTPRI_DATE_V  0x0FFFFFFFU
-#define INTPRI_DATE_S  0
-
-/** INTPRI_CLOCK_GATE_REG register
- *  register description
- */
-#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
-/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Need add description
- */
-#define INTPRI_CLK_EN    (BIT(0))
-#define INTPRI_CLK_EN_M  (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
-#define INTPRI_CLK_EN_V  0x00000001U
-#define INTPRI_CLK_EN_S  0
-
-/** INTPRI_CORE0_CPU_INT_CLEAR_REG register
- *  register description
- */
-#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8)
-/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CORE0_CPU_INT_CLEAR    0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_CLEAR_M  (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S)
-#define INTPRI_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFFU
-#define INTPRI_CORE0_CPU_INT_CLEAR_S  0
-
-/** INTPRI_RND_ECO_REG register
- *  redcy eco register.
- */
-#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac)
-/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0;
- *  Only reserved for ECO.
- */
-#define INTPRI_REDCY_ENA    (BIT(0))
-#define INTPRI_REDCY_ENA_M  (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S)
-#define INTPRI_REDCY_ENA_V  0x00000001U
-#define INTPRI_REDCY_ENA_S  0
-/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0;
- *  Only reserved for ECO.
- */
-#define INTPRI_REDCY_RESULT    (BIT(1))
-#define INTPRI_REDCY_RESULT_M  (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S)
-#define INTPRI_REDCY_RESULT_V  0x00000001U
-#define INTPRI_REDCY_RESULT_S  1
-
-/** INTPRI_RND_ECO_LOW_REG register
- *  redcy eco low register.
- */
-#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0)
-/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
- *  Only reserved for ECO.
- */
-#define INTPRI_REDCY_LOW    0xFFFFFFFFU
-#define INTPRI_REDCY_LOW_M  (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S)
-#define INTPRI_REDCY_LOW_V  0xFFFFFFFFU
-#define INTPRI_REDCY_LOW_S  0
-
-/** INTPRI_RND_ECO_HIGH_REG register
- *  redcy eco high register.
- */
-#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc)
-/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
- *  Only reserved for ECO.
- */
-#define INTPRI_REDCY_HIGH    0xFFFFFFFFU
-#define INTPRI_REDCY_HIGH_M  (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S)
-#define INTPRI_REDCY_HIGH_V  0xFFFFFFFFU
-#define INTPRI_REDCY_HIGH_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/intpri_struct.h b/components/soc/esp32p4/include/soc/intpri_struct.h
deleted file mode 100644
index 622f00818b..0000000000
--- a/components/soc/esp32p4/include/soc/intpri_struct.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of core0_cpu_int_enable register
- *  register description
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t core0_cpu_int_enable:32;
-    };
-    uint32_t val;
-} intpri_core0_cpu_int_enable_reg_t;
-
-/** Type of core0_cpu_int_type register
- *  register description
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t core0_cpu_int_type:32;
-    };
-    uint32_t val;
-} intpri_core0_cpu_int_type_reg_t;
-
-/** Type of core0_cpu_int_eip_status register
- *  register description
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t core0_cpu_int_eip_status:32;
-    };
-    uint32_t val;
-} intpri_core0_cpu_int_eip_status_reg_t;
-
-/** Type of core0_cpu_int_pri_n register
- *  register description
- */
-typedef union {
-    struct {
-        /** map : R/W; bitpos: [3:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t map:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} intpri_core0_cpu_int_pri_n_reg_t;
-
-/** Type of core0_cpu_int_thresh register
- *  register description
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t core0_cpu_int_thresh:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} intpri_core0_cpu_int_thresh_reg_t;
-
-/** Type of clock_gate register
- *  register description
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Need add description
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_clock_gate_reg_t;
-
-/** Type of core0_cpu_int_clear register
- *  register description
- */
-typedef union {
-    struct {
-        /** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t core0_cpu_int_clear:32;
-    };
-    uint32_t val;
-} intpri_core0_cpu_int_clear_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of cpu_intr_from_cpu_0 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_0:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_0_reg_t;
-
-/** Type of cpu_intr_from_cpu_1 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_1:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_1_reg_t;
-
-/** Type of cpu_intr_from_cpu_2 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_2:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_2_reg_t;
-
-/** Type of cpu_intr_from_cpu_3 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_3:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_3_reg_t;
-
-
-/** Group: Version Registers */
-/** Type of date register
- *  register description
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35655824;
-         *  Need add description
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} intpri_date_reg_t;
-
-
-/** Group: Redcy ECO Registers */
-/** Type of rnd_eco register
- *  redcy eco register.
- */
-typedef union {
-    struct {
-        /** redcy_ena : W/R; bitpos: [0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_ena:1;
-        /** redcy_result : RO; bitpos: [1]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} intpri_rnd_eco_reg_t;
-
-/** Type of rnd_eco_low register
- *  redcy eco low register.
- */
-typedef union {
-    struct {
-        /** redcy_low : W/R; bitpos: [31:0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_low:32;
-    };
-    uint32_t val;
-} intpri_rnd_eco_low_reg_t;
-
-/** Type of rnd_eco_high register
- *  redcy eco high register.
- */
-typedef union {
-    struct {
-        /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_high:32;
-    };
-    uint32_t val;
-} intpri_rnd_eco_high_reg_t;
-
-
-typedef struct intpri_dev_t {
-    volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable;
-    volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type;
-    volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status;
-    volatile intpri_core0_cpu_int_pri_n_reg_t core0_cpu_int_pri[32];
-    volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh;
-    volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
-    volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
-    volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
-    volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
-    volatile intpri_date_reg_t date;
-    volatile intpri_clock_gate_reg_t clock_gate;
-    volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear;
-    volatile intpri_rnd_eco_reg_t rnd_eco;
-    volatile intpri_rnd_eco_low_reg_t rnd_eco_low;
-    uint32_t reserved_0b4[210];
-    volatile intpri_rnd_eco_high_reg_t rnd_eco_high;
-} intpri_dev_t;
-
-extern intpri_dev_t INTPRI;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/iomux_reg.h b/components/soc/esp32p4/include/soc/iomux_reg.h
deleted file mode 100644
index 7e2b0b221e..0000000000
--- a/components/soc/esp32p4/include/soc/iomux_reg.h
+++ /dev/null
@@ -1,5143 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** IO_MUX_gpio0_REG register
- *  iomux control register for gpio0
- */
-#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4)
-/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO0_MCU_OE_M  (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S)
-#define IO_MUX_GPIO0_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_OE_S  0
-/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO0_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO0_SLP_SEL_M  (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S)
-#define IO_MUX_GPIO0_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO0_SLP_SEL_S  1
-/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO0_MCU_WPD_M  (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S)
-#define IO_MUX_GPIO0_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_WPD_S  2
-/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO0_MCU_WPU_M  (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S)
-#define IO_MUX_GPIO0_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_WPU_S  3
-/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO0_MCU_IE_M  (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S)
-#define IO_MUX_GPIO0_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_IE_S  4
-/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO0_MCU_DRV_M  (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S)
-#define IO_MUX_GPIO0_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO0_MCU_DRV_S  5
-/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO0_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO0_FUN_WPD_M  (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S)
-#define IO_MUX_GPIO0_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_WPD_S  7
-/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO0_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO0_FUN_WPU_M  (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S)
-#define IO_MUX_GPIO0_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_WPU_S  8
-/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO0_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO0_FUN_IE_M  (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S)
-#define IO_MUX_GPIO0_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_IE_S  9
-/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO0_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO0_FUN_DRV_M  (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S)
-#define IO_MUX_GPIO0_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO0_FUN_DRV_S  10
-/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO0_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO0_MCU_SEL_M  (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S)
-#define IO_MUX_GPIO0_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO0_MCU_SEL_S  12
-/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO0_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO0_FILTER_EN_M  (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S)
-#define IO_MUX_GPIO0_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO0_FILTER_EN_S  15
-
-/** IO_MUX_gpio1_REG register
- *  iomux control register for gpio1
- */
-#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8)
-/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO1_MCU_OE_M  (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S)
-#define IO_MUX_GPIO1_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_OE_S  0
-/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO1_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO1_SLP_SEL_M  (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S)
-#define IO_MUX_GPIO1_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO1_SLP_SEL_S  1
-/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO1_MCU_WPD_M  (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S)
-#define IO_MUX_GPIO1_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_WPD_S  2
-/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO1_MCU_WPU_M  (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S)
-#define IO_MUX_GPIO1_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_WPU_S  3
-/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO1_MCU_IE_M  (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S)
-#define IO_MUX_GPIO1_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_IE_S  4
-/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO1_MCU_DRV_M  (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S)
-#define IO_MUX_GPIO1_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO1_MCU_DRV_S  5
-/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO1_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO1_FUN_WPD_M  (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S)
-#define IO_MUX_GPIO1_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_WPD_S  7
-/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO1_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO1_FUN_WPU_M  (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S)
-#define IO_MUX_GPIO1_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_WPU_S  8
-/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO1_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO1_FUN_IE_M  (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S)
-#define IO_MUX_GPIO1_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_IE_S  9
-/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO1_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO1_FUN_DRV_M  (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S)
-#define IO_MUX_GPIO1_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO1_FUN_DRV_S  10
-/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO1_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO1_MCU_SEL_M  (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S)
-#define IO_MUX_GPIO1_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO1_MCU_SEL_S  12
-/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO1_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO1_FILTER_EN_M  (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S)
-#define IO_MUX_GPIO1_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO1_FILTER_EN_S  15
-
-/** IO_MUX_gpio2_REG register
- *  iomux control register for gpio2
- */
-#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc)
-/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO2_MCU_OE_M  (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S)
-#define IO_MUX_GPIO2_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_OE_S  0
-/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO2_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO2_SLP_SEL_M  (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S)
-#define IO_MUX_GPIO2_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO2_SLP_SEL_S  1
-/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO2_MCU_WPD_M  (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S)
-#define IO_MUX_GPIO2_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_WPD_S  2
-/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO2_MCU_WPU_M  (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S)
-#define IO_MUX_GPIO2_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_WPU_S  3
-/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO2_MCU_IE_M  (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S)
-#define IO_MUX_GPIO2_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_IE_S  4
-/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO2_MCU_DRV_M  (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S)
-#define IO_MUX_GPIO2_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO2_MCU_DRV_S  5
-/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO2_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO2_FUN_WPD_M  (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S)
-#define IO_MUX_GPIO2_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_WPD_S  7
-/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO2_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO2_FUN_WPU_M  (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S)
-#define IO_MUX_GPIO2_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_WPU_S  8
-/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO2_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO2_FUN_IE_M  (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S)
-#define IO_MUX_GPIO2_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_IE_S  9
-/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO2_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO2_FUN_DRV_M  (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S)
-#define IO_MUX_GPIO2_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO2_FUN_DRV_S  10
-/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO2_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO2_MCU_SEL_M  (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S)
-#define IO_MUX_GPIO2_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO2_MCU_SEL_S  12
-/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO2_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO2_FILTER_EN_M  (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S)
-#define IO_MUX_GPIO2_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO2_FILTER_EN_S  15
-
-/** IO_MUX_gpio3_REG register
- *  iomux control register for gpio3
- */
-#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10)
-/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO3_MCU_OE_M  (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S)
-#define IO_MUX_GPIO3_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_OE_S  0
-/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO3_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO3_SLP_SEL_M  (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S)
-#define IO_MUX_GPIO3_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO3_SLP_SEL_S  1
-/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO3_MCU_WPD_M  (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S)
-#define IO_MUX_GPIO3_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_WPD_S  2
-/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO3_MCU_WPU_M  (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S)
-#define IO_MUX_GPIO3_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_WPU_S  3
-/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO3_MCU_IE_M  (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S)
-#define IO_MUX_GPIO3_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_IE_S  4
-/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO3_MCU_DRV_M  (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S)
-#define IO_MUX_GPIO3_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO3_MCU_DRV_S  5
-/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO3_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO3_FUN_WPD_M  (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S)
-#define IO_MUX_GPIO3_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_WPD_S  7
-/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO3_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO3_FUN_WPU_M  (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S)
-#define IO_MUX_GPIO3_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_WPU_S  8
-/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO3_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO3_FUN_IE_M  (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S)
-#define IO_MUX_GPIO3_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_IE_S  9
-/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO3_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO3_FUN_DRV_M  (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S)
-#define IO_MUX_GPIO3_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO3_FUN_DRV_S  10
-/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO3_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO3_MCU_SEL_M  (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S)
-#define IO_MUX_GPIO3_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO3_MCU_SEL_S  12
-/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO3_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO3_FILTER_EN_M  (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S)
-#define IO_MUX_GPIO3_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO3_FILTER_EN_S  15
-
-/** IO_MUX_gpio4_REG register
- *  iomux control register for gpio4
- */
-#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14)
-/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO4_MCU_OE_M  (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S)
-#define IO_MUX_GPIO4_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_OE_S  0
-/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO4_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO4_SLP_SEL_M  (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S)
-#define IO_MUX_GPIO4_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO4_SLP_SEL_S  1
-/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO4_MCU_WPD_M  (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S)
-#define IO_MUX_GPIO4_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_WPD_S  2
-/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO4_MCU_WPU_M  (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S)
-#define IO_MUX_GPIO4_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_WPU_S  3
-/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO4_MCU_IE_M  (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S)
-#define IO_MUX_GPIO4_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_IE_S  4
-/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO4_MCU_DRV_M  (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S)
-#define IO_MUX_GPIO4_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO4_MCU_DRV_S  5
-/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO4_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO4_FUN_WPD_M  (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S)
-#define IO_MUX_GPIO4_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_WPD_S  7
-/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO4_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO4_FUN_WPU_M  (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S)
-#define IO_MUX_GPIO4_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_WPU_S  8
-/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO4_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO4_FUN_IE_M  (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S)
-#define IO_MUX_GPIO4_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_IE_S  9
-/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO4_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO4_FUN_DRV_M  (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S)
-#define IO_MUX_GPIO4_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO4_FUN_DRV_S  10
-/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO4_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO4_MCU_SEL_M  (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S)
-#define IO_MUX_GPIO4_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO4_MCU_SEL_S  12
-/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO4_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO4_FILTER_EN_M  (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S)
-#define IO_MUX_GPIO4_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO4_FILTER_EN_S  15
-
-/** IO_MUX_gpio5_REG register
- *  iomux control register for gpio5
- */
-#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18)
-/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO5_MCU_OE_M  (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S)
-#define IO_MUX_GPIO5_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_OE_S  0
-/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO5_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO5_SLP_SEL_M  (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S)
-#define IO_MUX_GPIO5_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO5_SLP_SEL_S  1
-/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO5_MCU_WPD_M  (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S)
-#define IO_MUX_GPIO5_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_WPD_S  2
-/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO5_MCU_WPU_M  (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S)
-#define IO_MUX_GPIO5_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_WPU_S  3
-/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO5_MCU_IE_M  (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S)
-#define IO_MUX_GPIO5_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_IE_S  4
-/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO5_MCU_DRV_M  (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S)
-#define IO_MUX_GPIO5_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO5_MCU_DRV_S  5
-/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO5_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO5_FUN_WPD_M  (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S)
-#define IO_MUX_GPIO5_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_WPD_S  7
-/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO5_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO5_FUN_WPU_M  (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S)
-#define IO_MUX_GPIO5_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_WPU_S  8
-/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO5_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO5_FUN_IE_M  (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S)
-#define IO_MUX_GPIO5_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_IE_S  9
-/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO5_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO5_FUN_DRV_M  (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S)
-#define IO_MUX_GPIO5_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO5_FUN_DRV_S  10
-/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO5_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO5_MCU_SEL_M  (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S)
-#define IO_MUX_GPIO5_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO5_MCU_SEL_S  12
-/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO5_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO5_FILTER_EN_M  (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S)
-#define IO_MUX_GPIO5_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO5_FILTER_EN_S  15
-
-/** IO_MUX_gpio6_REG register
- *  iomux control register for gpio6
- */
-#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c)
-/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO6_MCU_OE_M  (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S)
-#define IO_MUX_GPIO6_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_OE_S  0
-/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO6_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO6_SLP_SEL_M  (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S)
-#define IO_MUX_GPIO6_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO6_SLP_SEL_S  1
-/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO6_MCU_WPD_M  (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S)
-#define IO_MUX_GPIO6_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_WPD_S  2
-/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO6_MCU_WPU_M  (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S)
-#define IO_MUX_GPIO6_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_WPU_S  3
-/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO6_MCU_IE_M  (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S)
-#define IO_MUX_GPIO6_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_IE_S  4
-/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO6_MCU_DRV_M  (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S)
-#define IO_MUX_GPIO6_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO6_MCU_DRV_S  5
-/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO6_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO6_FUN_WPD_M  (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S)
-#define IO_MUX_GPIO6_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_WPD_S  7
-/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO6_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO6_FUN_WPU_M  (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S)
-#define IO_MUX_GPIO6_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_WPU_S  8
-/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO6_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO6_FUN_IE_M  (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S)
-#define IO_MUX_GPIO6_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_IE_S  9
-/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO6_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO6_FUN_DRV_M  (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S)
-#define IO_MUX_GPIO6_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO6_FUN_DRV_S  10
-/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO6_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO6_MCU_SEL_M  (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S)
-#define IO_MUX_GPIO6_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO6_MCU_SEL_S  12
-/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO6_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO6_FILTER_EN_M  (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S)
-#define IO_MUX_GPIO6_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO6_FILTER_EN_S  15
-
-/** IO_MUX_gpio7_REG register
- *  iomux control register for gpio7
- */
-#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20)
-/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO7_MCU_OE_M  (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S)
-#define IO_MUX_GPIO7_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_OE_S  0
-/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO7_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO7_SLP_SEL_M  (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S)
-#define IO_MUX_GPIO7_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO7_SLP_SEL_S  1
-/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO7_MCU_WPD_M  (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S)
-#define IO_MUX_GPIO7_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_WPD_S  2
-/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO7_MCU_WPU_M  (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S)
-#define IO_MUX_GPIO7_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_WPU_S  3
-/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO7_MCU_IE_M  (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S)
-#define IO_MUX_GPIO7_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_IE_S  4
-/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO7_MCU_DRV_M  (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S)
-#define IO_MUX_GPIO7_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO7_MCU_DRV_S  5
-/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO7_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO7_FUN_WPD_M  (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S)
-#define IO_MUX_GPIO7_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_WPD_S  7
-/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO7_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO7_FUN_WPU_M  (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S)
-#define IO_MUX_GPIO7_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_WPU_S  8
-/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO7_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO7_FUN_IE_M  (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S)
-#define IO_MUX_GPIO7_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_IE_S  9
-/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO7_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO7_FUN_DRV_M  (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S)
-#define IO_MUX_GPIO7_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO7_FUN_DRV_S  10
-/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO7_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO7_MCU_SEL_M  (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S)
-#define IO_MUX_GPIO7_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO7_MCU_SEL_S  12
-/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO7_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO7_FILTER_EN_M  (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S)
-#define IO_MUX_GPIO7_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO7_FILTER_EN_S  15
-
-/** IO_MUX_gpio8_REG register
- *  iomux control register for gpio8
- */
-#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24)
-/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO8_MCU_OE_M  (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S)
-#define IO_MUX_GPIO8_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_OE_S  0
-/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO8_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO8_SLP_SEL_M  (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S)
-#define IO_MUX_GPIO8_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO8_SLP_SEL_S  1
-/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO8_MCU_WPD_M  (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S)
-#define IO_MUX_GPIO8_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_WPD_S  2
-/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO8_MCU_WPU_M  (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S)
-#define IO_MUX_GPIO8_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_WPU_S  3
-/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO8_MCU_IE_M  (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S)
-#define IO_MUX_GPIO8_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_IE_S  4
-/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO8_MCU_DRV_M  (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S)
-#define IO_MUX_GPIO8_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO8_MCU_DRV_S  5
-/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO8_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO8_FUN_WPD_M  (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S)
-#define IO_MUX_GPIO8_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_WPD_S  7
-/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO8_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO8_FUN_WPU_M  (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S)
-#define IO_MUX_GPIO8_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_WPU_S  8
-/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO8_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO8_FUN_IE_M  (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S)
-#define IO_MUX_GPIO8_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_IE_S  9
-/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO8_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO8_FUN_DRV_M  (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S)
-#define IO_MUX_GPIO8_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO8_FUN_DRV_S  10
-/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO8_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO8_MCU_SEL_M  (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S)
-#define IO_MUX_GPIO8_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO8_MCU_SEL_S  12
-/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO8_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO8_FILTER_EN_M  (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S)
-#define IO_MUX_GPIO8_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO8_FILTER_EN_S  15
-
-/** IO_MUX_gpio9_REG register
- *  iomux control register for gpio9
- */
-#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28)
-/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO9_MCU_OE_M  (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S)
-#define IO_MUX_GPIO9_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_OE_S  0
-/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO9_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO9_SLP_SEL_M  (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S)
-#define IO_MUX_GPIO9_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO9_SLP_SEL_S  1
-/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO9_MCU_WPD_M  (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S)
-#define IO_MUX_GPIO9_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_WPD_S  2
-/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO9_MCU_WPU_M  (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S)
-#define IO_MUX_GPIO9_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_WPU_S  3
-/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO9_MCU_IE_M  (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S)
-#define IO_MUX_GPIO9_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_IE_S  4
-/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO9_MCU_DRV_M  (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S)
-#define IO_MUX_GPIO9_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO9_MCU_DRV_S  5
-/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO9_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO9_FUN_WPD_M  (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S)
-#define IO_MUX_GPIO9_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_WPD_S  7
-/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO9_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO9_FUN_WPU_M  (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S)
-#define IO_MUX_GPIO9_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_WPU_S  8
-/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO9_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO9_FUN_IE_M  (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S)
-#define IO_MUX_GPIO9_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_IE_S  9
-/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO9_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO9_FUN_DRV_M  (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S)
-#define IO_MUX_GPIO9_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO9_FUN_DRV_S  10
-/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO9_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO9_MCU_SEL_M  (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S)
-#define IO_MUX_GPIO9_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO9_MCU_SEL_S  12
-/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO9_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO9_FILTER_EN_M  (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S)
-#define IO_MUX_GPIO9_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO9_FILTER_EN_S  15
-
-/** IO_MUX_gpio10_REG register
- *  iomux control register for gpio10
- */
-#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c)
-/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO10_MCU_OE_M  (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S)
-#define IO_MUX_GPIO10_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_OE_S  0
-/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO10_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO10_SLP_SEL_M  (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S)
-#define IO_MUX_GPIO10_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO10_SLP_SEL_S  1
-/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO10_MCU_WPD_M  (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S)
-#define IO_MUX_GPIO10_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_WPD_S  2
-/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO10_MCU_WPU_M  (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S)
-#define IO_MUX_GPIO10_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_WPU_S  3
-/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO10_MCU_IE_M  (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S)
-#define IO_MUX_GPIO10_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_IE_S  4
-/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO10_MCU_DRV_M  (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S)
-#define IO_MUX_GPIO10_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO10_MCU_DRV_S  5
-/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO10_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO10_FUN_WPD_M  (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S)
-#define IO_MUX_GPIO10_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_WPD_S  7
-/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO10_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO10_FUN_WPU_M  (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S)
-#define IO_MUX_GPIO10_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_WPU_S  8
-/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO10_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO10_FUN_IE_M  (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S)
-#define IO_MUX_GPIO10_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_IE_S  9
-/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO10_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO10_FUN_DRV_M  (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S)
-#define IO_MUX_GPIO10_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO10_FUN_DRV_S  10
-/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO10_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO10_MCU_SEL_M  (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S)
-#define IO_MUX_GPIO10_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO10_MCU_SEL_S  12
-/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO10_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO10_FILTER_EN_M  (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S)
-#define IO_MUX_GPIO10_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO10_FILTER_EN_S  15
-
-/** IO_MUX_gpio11_REG register
- *  iomux control register for gpio11
- */
-#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30)
-/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO11_MCU_OE_M  (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S)
-#define IO_MUX_GPIO11_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_OE_S  0
-/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO11_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO11_SLP_SEL_M  (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S)
-#define IO_MUX_GPIO11_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO11_SLP_SEL_S  1
-/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO11_MCU_WPD_M  (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S)
-#define IO_MUX_GPIO11_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_WPD_S  2
-/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO11_MCU_WPU_M  (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S)
-#define IO_MUX_GPIO11_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_WPU_S  3
-/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO11_MCU_IE_M  (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S)
-#define IO_MUX_GPIO11_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_IE_S  4
-/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO11_MCU_DRV_M  (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S)
-#define IO_MUX_GPIO11_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO11_MCU_DRV_S  5
-/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO11_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO11_FUN_WPD_M  (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S)
-#define IO_MUX_GPIO11_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_WPD_S  7
-/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO11_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO11_FUN_WPU_M  (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S)
-#define IO_MUX_GPIO11_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_WPU_S  8
-/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO11_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO11_FUN_IE_M  (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S)
-#define IO_MUX_GPIO11_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_IE_S  9
-/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO11_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO11_FUN_DRV_M  (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S)
-#define IO_MUX_GPIO11_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO11_FUN_DRV_S  10
-/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO11_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO11_MCU_SEL_M  (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S)
-#define IO_MUX_GPIO11_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO11_MCU_SEL_S  12
-/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO11_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO11_FILTER_EN_M  (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S)
-#define IO_MUX_GPIO11_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO11_FILTER_EN_S  15
-
-/** IO_MUX_gpio12_REG register
- *  iomux control register for gpio12
- */
-#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34)
-/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO12_MCU_OE_M  (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S)
-#define IO_MUX_GPIO12_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_OE_S  0
-/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO12_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO12_SLP_SEL_M  (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S)
-#define IO_MUX_GPIO12_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO12_SLP_SEL_S  1
-/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO12_MCU_WPD_M  (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S)
-#define IO_MUX_GPIO12_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_WPD_S  2
-/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO12_MCU_WPU_M  (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S)
-#define IO_MUX_GPIO12_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_WPU_S  3
-/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO12_MCU_IE_M  (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S)
-#define IO_MUX_GPIO12_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_IE_S  4
-/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO12_MCU_DRV_M  (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S)
-#define IO_MUX_GPIO12_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO12_MCU_DRV_S  5
-/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO12_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO12_FUN_WPD_M  (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S)
-#define IO_MUX_GPIO12_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_WPD_S  7
-/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO12_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO12_FUN_WPU_M  (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S)
-#define IO_MUX_GPIO12_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_WPU_S  8
-/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO12_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO12_FUN_IE_M  (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S)
-#define IO_MUX_GPIO12_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_IE_S  9
-/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO12_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO12_FUN_DRV_M  (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S)
-#define IO_MUX_GPIO12_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO12_FUN_DRV_S  10
-/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO12_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO12_MCU_SEL_M  (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S)
-#define IO_MUX_GPIO12_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO12_MCU_SEL_S  12
-/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO12_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO12_FILTER_EN_M  (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S)
-#define IO_MUX_GPIO12_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO12_FILTER_EN_S  15
-
-/** IO_MUX_gpio13_REG register
- *  iomux control register for gpio13
- */
-#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38)
-/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO13_MCU_OE_M  (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S)
-#define IO_MUX_GPIO13_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_OE_S  0
-/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO13_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO13_SLP_SEL_M  (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S)
-#define IO_MUX_GPIO13_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO13_SLP_SEL_S  1
-/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO13_MCU_WPD_M  (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S)
-#define IO_MUX_GPIO13_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_WPD_S  2
-/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO13_MCU_WPU_M  (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S)
-#define IO_MUX_GPIO13_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_WPU_S  3
-/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO13_MCU_IE_M  (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S)
-#define IO_MUX_GPIO13_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_IE_S  4
-/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO13_MCU_DRV_M  (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S)
-#define IO_MUX_GPIO13_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO13_MCU_DRV_S  5
-/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO13_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO13_FUN_WPD_M  (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S)
-#define IO_MUX_GPIO13_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_WPD_S  7
-/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO13_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO13_FUN_WPU_M  (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S)
-#define IO_MUX_GPIO13_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_WPU_S  8
-/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO13_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO13_FUN_IE_M  (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S)
-#define IO_MUX_GPIO13_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_IE_S  9
-/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO13_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO13_FUN_DRV_M  (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S)
-#define IO_MUX_GPIO13_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO13_FUN_DRV_S  10
-/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO13_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO13_MCU_SEL_M  (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S)
-#define IO_MUX_GPIO13_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO13_MCU_SEL_S  12
-/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO13_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO13_FILTER_EN_M  (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S)
-#define IO_MUX_GPIO13_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO13_FILTER_EN_S  15
-
-/** IO_MUX_gpio14_REG register
- *  iomux control register for gpio14
- */
-#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c)
-/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO14_MCU_OE_M  (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S)
-#define IO_MUX_GPIO14_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_OE_S  0
-/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO14_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO14_SLP_SEL_M  (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S)
-#define IO_MUX_GPIO14_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO14_SLP_SEL_S  1
-/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO14_MCU_WPD_M  (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S)
-#define IO_MUX_GPIO14_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_WPD_S  2
-/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO14_MCU_WPU_M  (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S)
-#define IO_MUX_GPIO14_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_WPU_S  3
-/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO14_MCU_IE_M  (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S)
-#define IO_MUX_GPIO14_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_IE_S  4
-/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO14_MCU_DRV_M  (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S)
-#define IO_MUX_GPIO14_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO14_MCU_DRV_S  5
-/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO14_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO14_FUN_WPD_M  (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S)
-#define IO_MUX_GPIO14_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_WPD_S  7
-/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO14_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO14_FUN_WPU_M  (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S)
-#define IO_MUX_GPIO14_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_WPU_S  8
-/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO14_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO14_FUN_IE_M  (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S)
-#define IO_MUX_GPIO14_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_IE_S  9
-/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO14_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO14_FUN_DRV_M  (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S)
-#define IO_MUX_GPIO14_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO14_FUN_DRV_S  10
-/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO14_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO14_MCU_SEL_M  (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S)
-#define IO_MUX_GPIO14_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO14_MCU_SEL_S  12
-/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO14_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO14_FILTER_EN_M  (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S)
-#define IO_MUX_GPIO14_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO14_FILTER_EN_S  15
-
-/** IO_MUX_gpio15_REG register
- *  iomux control register for gpio15
- */
-#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40)
-/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO15_MCU_OE_M  (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S)
-#define IO_MUX_GPIO15_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_OE_S  0
-/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO15_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO15_SLP_SEL_M  (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S)
-#define IO_MUX_GPIO15_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO15_SLP_SEL_S  1
-/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO15_MCU_WPD_M  (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S)
-#define IO_MUX_GPIO15_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_WPD_S  2
-/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO15_MCU_WPU_M  (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S)
-#define IO_MUX_GPIO15_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_WPU_S  3
-/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO15_MCU_IE_M  (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S)
-#define IO_MUX_GPIO15_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_IE_S  4
-/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO15_MCU_DRV_M  (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S)
-#define IO_MUX_GPIO15_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO15_MCU_DRV_S  5
-/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO15_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO15_FUN_WPD_M  (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S)
-#define IO_MUX_GPIO15_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_WPD_S  7
-/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO15_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO15_FUN_WPU_M  (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S)
-#define IO_MUX_GPIO15_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_WPU_S  8
-/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO15_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO15_FUN_IE_M  (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S)
-#define IO_MUX_GPIO15_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_IE_S  9
-/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO15_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO15_FUN_DRV_M  (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S)
-#define IO_MUX_GPIO15_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO15_FUN_DRV_S  10
-/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO15_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO15_MCU_SEL_M  (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S)
-#define IO_MUX_GPIO15_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO15_MCU_SEL_S  12
-/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO15_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO15_FILTER_EN_M  (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S)
-#define IO_MUX_GPIO15_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO15_FILTER_EN_S  15
-
-/** IO_MUX_gpio16_REG register
- *  iomux control register for gpio16
- */
-#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44)
-/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO16_MCU_OE_M  (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S)
-#define IO_MUX_GPIO16_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_OE_S  0
-/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO16_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO16_SLP_SEL_M  (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S)
-#define IO_MUX_GPIO16_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO16_SLP_SEL_S  1
-/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO16_MCU_WPD_M  (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S)
-#define IO_MUX_GPIO16_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_WPD_S  2
-/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO16_MCU_WPU_M  (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S)
-#define IO_MUX_GPIO16_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_WPU_S  3
-/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO16_MCU_IE_M  (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S)
-#define IO_MUX_GPIO16_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_IE_S  4
-/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO16_MCU_DRV_M  (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S)
-#define IO_MUX_GPIO16_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO16_MCU_DRV_S  5
-/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO16_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO16_FUN_WPD_M  (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S)
-#define IO_MUX_GPIO16_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_WPD_S  7
-/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO16_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO16_FUN_WPU_M  (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S)
-#define IO_MUX_GPIO16_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_WPU_S  8
-/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO16_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO16_FUN_IE_M  (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S)
-#define IO_MUX_GPIO16_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_IE_S  9
-/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO16_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO16_FUN_DRV_M  (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S)
-#define IO_MUX_GPIO16_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO16_FUN_DRV_S  10
-/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO16_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO16_MCU_SEL_M  (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S)
-#define IO_MUX_GPIO16_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO16_MCU_SEL_S  12
-/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO16_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO16_FILTER_EN_M  (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S)
-#define IO_MUX_GPIO16_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO16_FILTER_EN_S  15
-
-/** IO_MUX_gpio17_REG register
- *  iomux control register for gpio17
- */
-#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48)
-/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO17_MCU_OE_M  (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S)
-#define IO_MUX_GPIO17_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_OE_S  0
-/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO17_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO17_SLP_SEL_M  (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S)
-#define IO_MUX_GPIO17_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO17_SLP_SEL_S  1
-/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO17_MCU_WPD_M  (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S)
-#define IO_MUX_GPIO17_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_WPD_S  2
-/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO17_MCU_WPU_M  (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S)
-#define IO_MUX_GPIO17_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_WPU_S  3
-/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO17_MCU_IE_M  (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S)
-#define IO_MUX_GPIO17_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_IE_S  4
-/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO17_MCU_DRV_M  (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S)
-#define IO_MUX_GPIO17_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO17_MCU_DRV_S  5
-/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO17_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO17_FUN_WPD_M  (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S)
-#define IO_MUX_GPIO17_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_WPD_S  7
-/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO17_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO17_FUN_WPU_M  (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S)
-#define IO_MUX_GPIO17_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_WPU_S  8
-/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO17_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO17_FUN_IE_M  (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S)
-#define IO_MUX_GPIO17_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_IE_S  9
-/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO17_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO17_FUN_DRV_M  (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S)
-#define IO_MUX_GPIO17_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO17_FUN_DRV_S  10
-/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO17_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO17_MCU_SEL_M  (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S)
-#define IO_MUX_GPIO17_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO17_MCU_SEL_S  12
-/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO17_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO17_FILTER_EN_M  (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S)
-#define IO_MUX_GPIO17_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO17_FILTER_EN_S  15
-
-/** IO_MUX_gpio18_REG register
- *  iomux control register for gpio18
- */
-#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c)
-/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO18_MCU_OE_M  (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S)
-#define IO_MUX_GPIO18_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_OE_S  0
-/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO18_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO18_SLP_SEL_M  (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S)
-#define IO_MUX_GPIO18_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO18_SLP_SEL_S  1
-/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO18_MCU_WPD_M  (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S)
-#define IO_MUX_GPIO18_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_WPD_S  2
-/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO18_MCU_WPU_M  (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S)
-#define IO_MUX_GPIO18_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_WPU_S  3
-/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO18_MCU_IE_M  (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S)
-#define IO_MUX_GPIO18_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_IE_S  4
-/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO18_MCU_DRV_M  (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S)
-#define IO_MUX_GPIO18_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO18_MCU_DRV_S  5
-/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO18_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO18_FUN_WPD_M  (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S)
-#define IO_MUX_GPIO18_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_WPD_S  7
-/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO18_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO18_FUN_WPU_M  (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S)
-#define IO_MUX_GPIO18_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_WPU_S  8
-/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO18_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO18_FUN_IE_M  (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S)
-#define IO_MUX_GPIO18_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_IE_S  9
-/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO18_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO18_FUN_DRV_M  (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S)
-#define IO_MUX_GPIO18_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO18_FUN_DRV_S  10
-/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO18_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO18_MCU_SEL_M  (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S)
-#define IO_MUX_GPIO18_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO18_MCU_SEL_S  12
-/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO18_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO18_FILTER_EN_M  (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S)
-#define IO_MUX_GPIO18_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO18_FILTER_EN_S  15
-
-/** IO_MUX_gpio19_REG register
- *  iomux control register for gpio19
- */
-#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50)
-/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO19_MCU_OE_M  (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S)
-#define IO_MUX_GPIO19_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_OE_S  0
-/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO19_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO19_SLP_SEL_M  (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S)
-#define IO_MUX_GPIO19_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO19_SLP_SEL_S  1
-/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO19_MCU_WPD_M  (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S)
-#define IO_MUX_GPIO19_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_WPD_S  2
-/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO19_MCU_WPU_M  (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S)
-#define IO_MUX_GPIO19_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_WPU_S  3
-/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO19_MCU_IE_M  (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S)
-#define IO_MUX_GPIO19_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_IE_S  4
-/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO19_MCU_DRV_M  (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S)
-#define IO_MUX_GPIO19_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO19_MCU_DRV_S  5
-/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO19_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO19_FUN_WPD_M  (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S)
-#define IO_MUX_GPIO19_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_WPD_S  7
-/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO19_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO19_FUN_WPU_M  (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S)
-#define IO_MUX_GPIO19_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_WPU_S  8
-/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO19_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO19_FUN_IE_M  (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S)
-#define IO_MUX_GPIO19_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_IE_S  9
-/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO19_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO19_FUN_DRV_M  (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S)
-#define IO_MUX_GPIO19_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO19_FUN_DRV_S  10
-/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO19_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO19_MCU_SEL_M  (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S)
-#define IO_MUX_GPIO19_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO19_MCU_SEL_S  12
-/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO19_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO19_FILTER_EN_M  (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S)
-#define IO_MUX_GPIO19_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO19_FILTER_EN_S  15
-
-/** IO_MUX_gpio20_REG register
- *  iomux control register for gpio20
- */
-#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54)
-/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO20_MCU_OE_M  (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S)
-#define IO_MUX_GPIO20_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_OE_S  0
-/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO20_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO20_SLP_SEL_M  (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S)
-#define IO_MUX_GPIO20_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO20_SLP_SEL_S  1
-/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO20_MCU_WPD_M  (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S)
-#define IO_MUX_GPIO20_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_WPD_S  2
-/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO20_MCU_WPU_M  (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S)
-#define IO_MUX_GPIO20_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_WPU_S  3
-/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO20_MCU_IE_M  (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S)
-#define IO_MUX_GPIO20_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_IE_S  4
-/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO20_MCU_DRV_M  (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S)
-#define IO_MUX_GPIO20_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO20_MCU_DRV_S  5
-/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO20_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO20_FUN_WPD_M  (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S)
-#define IO_MUX_GPIO20_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_WPD_S  7
-/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO20_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO20_FUN_WPU_M  (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S)
-#define IO_MUX_GPIO20_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_WPU_S  8
-/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO20_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO20_FUN_IE_M  (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S)
-#define IO_MUX_GPIO20_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_IE_S  9
-/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO20_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO20_FUN_DRV_M  (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S)
-#define IO_MUX_GPIO20_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO20_FUN_DRV_S  10
-/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO20_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO20_MCU_SEL_M  (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S)
-#define IO_MUX_GPIO20_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO20_MCU_SEL_S  12
-/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO20_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO20_FILTER_EN_M  (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S)
-#define IO_MUX_GPIO20_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO20_FILTER_EN_S  15
-
-/** IO_MUX_gpio21_REG register
- *  iomux control register for gpio21
- */
-#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58)
-/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO21_MCU_OE_M  (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S)
-#define IO_MUX_GPIO21_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_OE_S  0
-/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO21_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO21_SLP_SEL_M  (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S)
-#define IO_MUX_GPIO21_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO21_SLP_SEL_S  1
-/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO21_MCU_WPD_M  (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S)
-#define IO_MUX_GPIO21_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_WPD_S  2
-/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO21_MCU_WPU_M  (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S)
-#define IO_MUX_GPIO21_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_WPU_S  3
-/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO21_MCU_IE_M  (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S)
-#define IO_MUX_GPIO21_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_IE_S  4
-/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO21_MCU_DRV_M  (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S)
-#define IO_MUX_GPIO21_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO21_MCU_DRV_S  5
-/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO21_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO21_FUN_WPD_M  (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S)
-#define IO_MUX_GPIO21_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_WPD_S  7
-/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO21_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO21_FUN_WPU_M  (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S)
-#define IO_MUX_GPIO21_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_WPU_S  8
-/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO21_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO21_FUN_IE_M  (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S)
-#define IO_MUX_GPIO21_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_IE_S  9
-/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO21_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO21_FUN_DRV_M  (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S)
-#define IO_MUX_GPIO21_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO21_FUN_DRV_S  10
-/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO21_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO21_MCU_SEL_M  (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S)
-#define IO_MUX_GPIO21_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO21_MCU_SEL_S  12
-/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO21_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO21_FILTER_EN_M  (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S)
-#define IO_MUX_GPIO21_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO21_FILTER_EN_S  15
-
-/** IO_MUX_gpio22_REG register
- *  iomux control register for gpio22
- */
-#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c)
-/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO22_MCU_OE_M  (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S)
-#define IO_MUX_GPIO22_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_OE_S  0
-/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO22_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO22_SLP_SEL_M  (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S)
-#define IO_MUX_GPIO22_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO22_SLP_SEL_S  1
-/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO22_MCU_WPD_M  (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S)
-#define IO_MUX_GPIO22_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_WPD_S  2
-/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO22_MCU_WPU_M  (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S)
-#define IO_MUX_GPIO22_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_WPU_S  3
-/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO22_MCU_IE_M  (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S)
-#define IO_MUX_GPIO22_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_IE_S  4
-/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO22_MCU_DRV_M  (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S)
-#define IO_MUX_GPIO22_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO22_MCU_DRV_S  5
-/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO22_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO22_FUN_WPD_M  (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S)
-#define IO_MUX_GPIO22_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_WPD_S  7
-/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO22_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO22_FUN_WPU_M  (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S)
-#define IO_MUX_GPIO22_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_WPU_S  8
-/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO22_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO22_FUN_IE_M  (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S)
-#define IO_MUX_GPIO22_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_IE_S  9
-/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO22_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO22_FUN_DRV_M  (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S)
-#define IO_MUX_GPIO22_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO22_FUN_DRV_S  10
-/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO22_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO22_MCU_SEL_M  (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S)
-#define IO_MUX_GPIO22_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO22_MCU_SEL_S  12
-/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO22_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO22_FILTER_EN_M  (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S)
-#define IO_MUX_GPIO22_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO22_FILTER_EN_S  15
-
-/** IO_MUX_gpio23_REG register
- *  iomux control register for gpio23
- */
-#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60)
-/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO23_MCU_OE_M  (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S)
-#define IO_MUX_GPIO23_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_OE_S  0
-/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO23_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO23_SLP_SEL_M  (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S)
-#define IO_MUX_GPIO23_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO23_SLP_SEL_S  1
-/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO23_MCU_WPD_M  (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S)
-#define IO_MUX_GPIO23_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_WPD_S  2
-/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO23_MCU_WPU_M  (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S)
-#define IO_MUX_GPIO23_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_WPU_S  3
-/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO23_MCU_IE_M  (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S)
-#define IO_MUX_GPIO23_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_IE_S  4
-/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO23_MCU_DRV_M  (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S)
-#define IO_MUX_GPIO23_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO23_MCU_DRV_S  5
-/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO23_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO23_FUN_WPD_M  (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S)
-#define IO_MUX_GPIO23_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_WPD_S  7
-/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO23_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO23_FUN_WPU_M  (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S)
-#define IO_MUX_GPIO23_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_WPU_S  8
-/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO23_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO23_FUN_IE_M  (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S)
-#define IO_MUX_GPIO23_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_IE_S  9
-/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO23_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO23_FUN_DRV_M  (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S)
-#define IO_MUX_GPIO23_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO23_FUN_DRV_S  10
-/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO23_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO23_MCU_SEL_M  (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S)
-#define IO_MUX_GPIO23_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO23_MCU_SEL_S  12
-/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO23_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO23_FILTER_EN_M  (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S)
-#define IO_MUX_GPIO23_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO23_FILTER_EN_S  15
-
-/** IO_MUX_gpio24_REG register
- *  iomux control register for gpio24
- */
-#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64)
-/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO24_MCU_OE_M  (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S)
-#define IO_MUX_GPIO24_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_OE_S  0
-/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO24_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO24_SLP_SEL_M  (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S)
-#define IO_MUX_GPIO24_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO24_SLP_SEL_S  1
-/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO24_MCU_WPD_M  (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S)
-#define IO_MUX_GPIO24_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_WPD_S  2
-/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO24_MCU_WPU_M  (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S)
-#define IO_MUX_GPIO24_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_WPU_S  3
-/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO24_MCU_IE_M  (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S)
-#define IO_MUX_GPIO24_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_IE_S  4
-/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO24_MCU_DRV_M  (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S)
-#define IO_MUX_GPIO24_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO24_MCU_DRV_S  5
-/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO24_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO24_FUN_WPD_M  (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S)
-#define IO_MUX_GPIO24_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_WPD_S  7
-/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO24_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO24_FUN_WPU_M  (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S)
-#define IO_MUX_GPIO24_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_WPU_S  8
-/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO24_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO24_FUN_IE_M  (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S)
-#define IO_MUX_GPIO24_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_IE_S  9
-/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO24_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO24_FUN_DRV_M  (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S)
-#define IO_MUX_GPIO24_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO24_FUN_DRV_S  10
-/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO24_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO24_MCU_SEL_M  (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S)
-#define IO_MUX_GPIO24_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO24_MCU_SEL_S  12
-/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO24_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO24_FILTER_EN_M  (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S)
-#define IO_MUX_GPIO24_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO24_FILTER_EN_S  15
-
-/** IO_MUX_gpio25_REG register
- *  iomux control register for gpio25
- */
-#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68)
-/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO25_MCU_OE_M  (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S)
-#define IO_MUX_GPIO25_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_OE_S  0
-/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO25_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO25_SLP_SEL_M  (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S)
-#define IO_MUX_GPIO25_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO25_SLP_SEL_S  1
-/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO25_MCU_WPD_M  (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S)
-#define IO_MUX_GPIO25_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_WPD_S  2
-/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO25_MCU_WPU_M  (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S)
-#define IO_MUX_GPIO25_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_WPU_S  3
-/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO25_MCU_IE_M  (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S)
-#define IO_MUX_GPIO25_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_IE_S  4
-/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO25_MCU_DRV_M  (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S)
-#define IO_MUX_GPIO25_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO25_MCU_DRV_S  5
-/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO25_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO25_FUN_WPD_M  (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S)
-#define IO_MUX_GPIO25_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_WPD_S  7
-/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO25_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO25_FUN_WPU_M  (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S)
-#define IO_MUX_GPIO25_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_WPU_S  8
-/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO25_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO25_FUN_IE_M  (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S)
-#define IO_MUX_GPIO25_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_IE_S  9
-/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO25_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO25_FUN_DRV_M  (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S)
-#define IO_MUX_GPIO25_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO25_FUN_DRV_S  10
-/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO25_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO25_MCU_SEL_M  (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S)
-#define IO_MUX_GPIO25_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO25_MCU_SEL_S  12
-/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO25_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO25_FILTER_EN_M  (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S)
-#define IO_MUX_GPIO25_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO25_FILTER_EN_S  15
-
-/** IO_MUX_gpio26_REG register
- *  iomux control register for gpio26
- */
-#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c)
-/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO26_MCU_OE_M  (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S)
-#define IO_MUX_GPIO26_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_OE_S  0
-/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO26_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO26_SLP_SEL_M  (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S)
-#define IO_MUX_GPIO26_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO26_SLP_SEL_S  1
-/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO26_MCU_WPD_M  (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S)
-#define IO_MUX_GPIO26_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_WPD_S  2
-/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO26_MCU_WPU_M  (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S)
-#define IO_MUX_GPIO26_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_WPU_S  3
-/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO26_MCU_IE_M  (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S)
-#define IO_MUX_GPIO26_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_IE_S  4
-/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO26_MCU_DRV_M  (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S)
-#define IO_MUX_GPIO26_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO26_MCU_DRV_S  5
-/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO26_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO26_FUN_WPD_M  (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S)
-#define IO_MUX_GPIO26_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_WPD_S  7
-/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO26_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO26_FUN_WPU_M  (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S)
-#define IO_MUX_GPIO26_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_WPU_S  8
-/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO26_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO26_FUN_IE_M  (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S)
-#define IO_MUX_GPIO26_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_IE_S  9
-/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO26_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO26_FUN_DRV_M  (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S)
-#define IO_MUX_GPIO26_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO26_FUN_DRV_S  10
-/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO26_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO26_MCU_SEL_M  (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S)
-#define IO_MUX_GPIO26_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO26_MCU_SEL_S  12
-/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO26_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO26_FILTER_EN_M  (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S)
-#define IO_MUX_GPIO26_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO26_FILTER_EN_S  15
-
-/** IO_MUX_gpio27_REG register
- *  iomux control register for gpio27
- */
-#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70)
-/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO27_MCU_OE_M  (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S)
-#define IO_MUX_GPIO27_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_OE_S  0
-/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO27_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO27_SLP_SEL_M  (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S)
-#define IO_MUX_GPIO27_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO27_SLP_SEL_S  1
-/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO27_MCU_WPD_M  (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S)
-#define IO_MUX_GPIO27_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_WPD_S  2
-/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO27_MCU_WPU_M  (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S)
-#define IO_MUX_GPIO27_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_WPU_S  3
-/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO27_MCU_IE_M  (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S)
-#define IO_MUX_GPIO27_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_IE_S  4
-/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO27_MCU_DRV_M  (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S)
-#define IO_MUX_GPIO27_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO27_MCU_DRV_S  5
-/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO27_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO27_FUN_WPD_M  (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S)
-#define IO_MUX_GPIO27_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_WPD_S  7
-/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO27_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO27_FUN_WPU_M  (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S)
-#define IO_MUX_GPIO27_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_WPU_S  8
-/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO27_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO27_FUN_IE_M  (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S)
-#define IO_MUX_GPIO27_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_IE_S  9
-/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO27_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO27_FUN_DRV_M  (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S)
-#define IO_MUX_GPIO27_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO27_FUN_DRV_S  10
-/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO27_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO27_MCU_SEL_M  (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S)
-#define IO_MUX_GPIO27_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO27_MCU_SEL_S  12
-/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO27_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO27_FILTER_EN_M  (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S)
-#define IO_MUX_GPIO27_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO27_FILTER_EN_S  15
-
-/** IO_MUX_gpio28_REG register
- *  iomux control register for gpio28
- */
-#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74)
-/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO28_MCU_OE_M  (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S)
-#define IO_MUX_GPIO28_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_OE_S  0
-/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO28_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO28_SLP_SEL_M  (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S)
-#define IO_MUX_GPIO28_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO28_SLP_SEL_S  1
-/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO28_MCU_WPD_M  (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S)
-#define IO_MUX_GPIO28_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_WPD_S  2
-/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO28_MCU_WPU_M  (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S)
-#define IO_MUX_GPIO28_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_WPU_S  3
-/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO28_MCU_IE_M  (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S)
-#define IO_MUX_GPIO28_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_IE_S  4
-/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO28_MCU_DRV_M  (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S)
-#define IO_MUX_GPIO28_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO28_MCU_DRV_S  5
-/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO28_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO28_FUN_WPD_M  (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S)
-#define IO_MUX_GPIO28_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_WPD_S  7
-/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO28_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO28_FUN_WPU_M  (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S)
-#define IO_MUX_GPIO28_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_WPU_S  8
-/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO28_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO28_FUN_IE_M  (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S)
-#define IO_MUX_GPIO28_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_IE_S  9
-/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO28_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO28_FUN_DRV_M  (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S)
-#define IO_MUX_GPIO28_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO28_FUN_DRV_S  10
-/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO28_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO28_MCU_SEL_M  (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S)
-#define IO_MUX_GPIO28_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO28_MCU_SEL_S  12
-/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO28_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO28_FILTER_EN_M  (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S)
-#define IO_MUX_GPIO28_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO28_FILTER_EN_S  15
-
-/** IO_MUX_gpio29_REG register
- *  iomux control register for gpio29
- */
-#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78)
-/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO29_MCU_OE_M  (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S)
-#define IO_MUX_GPIO29_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_OE_S  0
-/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO29_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO29_SLP_SEL_M  (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S)
-#define IO_MUX_GPIO29_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO29_SLP_SEL_S  1
-/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO29_MCU_WPD_M  (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S)
-#define IO_MUX_GPIO29_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_WPD_S  2
-/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO29_MCU_WPU_M  (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S)
-#define IO_MUX_GPIO29_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_WPU_S  3
-/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO29_MCU_IE_M  (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S)
-#define IO_MUX_GPIO29_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_IE_S  4
-/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO29_MCU_DRV_M  (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S)
-#define IO_MUX_GPIO29_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO29_MCU_DRV_S  5
-/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO29_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO29_FUN_WPD_M  (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S)
-#define IO_MUX_GPIO29_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO29_FUN_WPD_S  7
-/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO29_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO29_FUN_WPU_M  (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S)
-#define IO_MUX_GPIO29_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO29_FUN_WPU_S  8
-/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO29_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO29_FUN_IE_M  (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S)
-#define IO_MUX_GPIO29_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO29_FUN_IE_S  9
-/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO29_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO29_FUN_DRV_M  (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S)
-#define IO_MUX_GPIO29_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO29_FUN_DRV_S  10
-/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO29_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO29_MCU_SEL_M  (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S)
-#define IO_MUX_GPIO29_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO29_MCU_SEL_S  12
-/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO29_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO29_FILTER_EN_M  (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S)
-#define IO_MUX_GPIO29_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO29_FILTER_EN_S  15
-
-/** IO_MUX_gpio30_REG register
- *  iomux control register for gpio30
- */
-#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c)
-/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO30_MCU_OE_M  (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S)
-#define IO_MUX_GPIO30_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_OE_S  0
-/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO30_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO30_SLP_SEL_M  (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S)
-#define IO_MUX_GPIO30_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO30_SLP_SEL_S  1
-/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO30_MCU_WPD_M  (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S)
-#define IO_MUX_GPIO30_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_WPD_S  2
-/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO30_MCU_WPU_M  (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S)
-#define IO_MUX_GPIO30_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_WPU_S  3
-/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO30_MCU_IE_M  (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S)
-#define IO_MUX_GPIO30_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_IE_S  4
-/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO30_MCU_DRV_M  (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S)
-#define IO_MUX_GPIO30_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO30_MCU_DRV_S  5
-/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO30_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO30_FUN_WPD_M  (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S)
-#define IO_MUX_GPIO30_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO30_FUN_WPD_S  7
-/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO30_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO30_FUN_WPU_M  (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S)
-#define IO_MUX_GPIO30_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO30_FUN_WPU_S  8
-/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO30_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO30_FUN_IE_M  (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S)
-#define IO_MUX_GPIO30_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO30_FUN_IE_S  9
-/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO30_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO30_FUN_DRV_M  (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S)
-#define IO_MUX_GPIO30_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO30_FUN_DRV_S  10
-/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO30_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO30_MCU_SEL_M  (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S)
-#define IO_MUX_GPIO30_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO30_MCU_SEL_S  12
-/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO30_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO30_FILTER_EN_M  (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S)
-#define IO_MUX_GPIO30_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO30_FILTER_EN_S  15
-
-/** IO_MUX_gpio31_REG register
- *  iomux control register for gpio31
- */
-#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80)
-/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO31_MCU_OE_M  (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S)
-#define IO_MUX_GPIO31_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_OE_S  0
-/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO31_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO31_SLP_SEL_M  (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S)
-#define IO_MUX_GPIO31_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO31_SLP_SEL_S  1
-/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO31_MCU_WPD_M  (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S)
-#define IO_MUX_GPIO31_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_WPD_S  2
-/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO31_MCU_WPU_M  (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S)
-#define IO_MUX_GPIO31_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_WPU_S  3
-/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO31_MCU_IE_M  (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S)
-#define IO_MUX_GPIO31_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_IE_S  4
-/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO31_MCU_DRV_M  (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S)
-#define IO_MUX_GPIO31_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO31_MCU_DRV_S  5
-/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO31_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO31_FUN_WPD_M  (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S)
-#define IO_MUX_GPIO31_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO31_FUN_WPD_S  7
-/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO31_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO31_FUN_WPU_M  (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S)
-#define IO_MUX_GPIO31_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO31_FUN_WPU_S  8
-/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO31_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO31_FUN_IE_M  (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S)
-#define IO_MUX_GPIO31_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO31_FUN_IE_S  9
-/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO31_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO31_FUN_DRV_M  (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S)
-#define IO_MUX_GPIO31_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO31_FUN_DRV_S  10
-/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO31_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO31_MCU_SEL_M  (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S)
-#define IO_MUX_GPIO31_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO31_MCU_SEL_S  12
-/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO31_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO31_FILTER_EN_M  (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S)
-#define IO_MUX_GPIO31_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO31_FILTER_EN_S  15
-
-/** IO_MUX_gpio32_REG register
- *  iomux control register for gpio32
- */
-#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84)
-/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO32_MCU_OE_M  (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S)
-#define IO_MUX_GPIO32_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_OE_S  0
-/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO32_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO32_SLP_SEL_M  (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S)
-#define IO_MUX_GPIO32_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO32_SLP_SEL_S  1
-/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO32_MCU_WPD_M  (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S)
-#define IO_MUX_GPIO32_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_WPD_S  2
-/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO32_MCU_WPU_M  (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S)
-#define IO_MUX_GPIO32_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_WPU_S  3
-/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO32_MCU_IE_M  (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S)
-#define IO_MUX_GPIO32_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_IE_S  4
-/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO32_MCU_DRV_M  (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S)
-#define IO_MUX_GPIO32_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO32_MCU_DRV_S  5
-/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO32_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO32_FUN_WPD_M  (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S)
-#define IO_MUX_GPIO32_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO32_FUN_WPD_S  7
-/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO32_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO32_FUN_WPU_M  (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S)
-#define IO_MUX_GPIO32_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO32_FUN_WPU_S  8
-/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO32_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO32_FUN_IE_M  (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S)
-#define IO_MUX_GPIO32_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO32_FUN_IE_S  9
-/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO32_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO32_FUN_DRV_M  (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S)
-#define IO_MUX_GPIO32_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO32_FUN_DRV_S  10
-/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO32_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO32_MCU_SEL_M  (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S)
-#define IO_MUX_GPIO32_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO32_MCU_SEL_S  12
-/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO32_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO32_FILTER_EN_M  (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S)
-#define IO_MUX_GPIO32_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO32_FILTER_EN_S  15
-/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO32_RUE_I3C    (BIT(16))
-#define IO_MUX_GPIO32_RUE_I3C_M  (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S)
-#define IO_MUX_GPIO32_RUE_I3C_V  0x00000001U
-#define IO_MUX_GPIO32_RUE_I3C_S  16
-/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO32_RU_I3C    0x00000003U
-#define IO_MUX_GPIO32_RU_I3C_M  (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S)
-#define IO_MUX_GPIO32_RU_I3C_V  0x00000003U
-#define IO_MUX_GPIO32_RU_I3C_S  17
-/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO32_RUE_SEL_I3C    (BIT(19))
-#define IO_MUX_GPIO32_RUE_SEL_I3C_M  (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S)
-#define IO_MUX_GPIO32_RUE_SEL_I3C_V  0x00000001U
-#define IO_MUX_GPIO32_RUE_SEL_I3C_S  19
-
-/** IO_MUX_gpio33_REG register
- *  iomux control register for gpio33
- */
-#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88)
-/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO33_MCU_OE_M  (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S)
-#define IO_MUX_GPIO33_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_OE_S  0
-/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO33_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO33_SLP_SEL_M  (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S)
-#define IO_MUX_GPIO33_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO33_SLP_SEL_S  1
-/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO33_MCU_WPD_M  (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S)
-#define IO_MUX_GPIO33_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_WPD_S  2
-/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO33_MCU_WPU_M  (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S)
-#define IO_MUX_GPIO33_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_WPU_S  3
-/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO33_MCU_IE_M  (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S)
-#define IO_MUX_GPIO33_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_IE_S  4
-/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO33_MCU_DRV_M  (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S)
-#define IO_MUX_GPIO33_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO33_MCU_DRV_S  5
-/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO33_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO33_FUN_WPD_M  (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S)
-#define IO_MUX_GPIO33_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO33_FUN_WPD_S  7
-/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO33_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO33_FUN_WPU_M  (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S)
-#define IO_MUX_GPIO33_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO33_FUN_WPU_S  8
-/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO33_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO33_FUN_IE_M  (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S)
-#define IO_MUX_GPIO33_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO33_FUN_IE_S  9
-/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO33_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO33_FUN_DRV_M  (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S)
-#define IO_MUX_GPIO33_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO33_FUN_DRV_S  10
-/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO33_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO33_MCU_SEL_M  (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S)
-#define IO_MUX_GPIO33_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO33_MCU_SEL_S  12
-/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO33_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO33_FILTER_EN_M  (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S)
-#define IO_MUX_GPIO33_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO33_FILTER_EN_S  15
-/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO33_RUE_I3C    (BIT(16))
-#define IO_MUX_GPIO33_RUE_I3C_M  (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S)
-#define IO_MUX_GPIO33_RUE_I3C_V  0x00000001U
-#define IO_MUX_GPIO33_RUE_I3C_S  16
-/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO33_RU_I3C    0x00000003U
-#define IO_MUX_GPIO33_RU_I3C_M  (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S)
-#define IO_MUX_GPIO33_RU_I3C_V  0x00000003U
-#define IO_MUX_GPIO33_RU_I3C_S  17
-/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO33_RUE_SEL_I3C    (BIT(19))
-#define IO_MUX_GPIO33_RUE_SEL_I3C_M  (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S)
-#define IO_MUX_GPIO33_RUE_SEL_I3C_V  0x00000001U
-#define IO_MUX_GPIO33_RUE_SEL_I3C_S  19
-
-/** IO_MUX_gpio34_REG register
- *  iomux control register for gpio34
- */
-#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c)
-/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO34_MCU_OE_M  (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S)
-#define IO_MUX_GPIO34_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_OE_S  0
-/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO34_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO34_SLP_SEL_M  (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S)
-#define IO_MUX_GPIO34_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO34_SLP_SEL_S  1
-/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO34_MCU_WPD_M  (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S)
-#define IO_MUX_GPIO34_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_WPD_S  2
-/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO34_MCU_WPU_M  (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S)
-#define IO_MUX_GPIO34_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_WPU_S  3
-/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO34_MCU_IE_M  (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S)
-#define IO_MUX_GPIO34_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_IE_S  4
-/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO34_MCU_DRV_M  (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S)
-#define IO_MUX_GPIO34_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO34_MCU_DRV_S  5
-/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO34_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO34_FUN_WPD_M  (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S)
-#define IO_MUX_GPIO34_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO34_FUN_WPD_S  7
-/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO34_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO34_FUN_WPU_M  (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S)
-#define IO_MUX_GPIO34_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO34_FUN_WPU_S  8
-/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO34_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO34_FUN_IE_M  (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S)
-#define IO_MUX_GPIO34_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO34_FUN_IE_S  9
-/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO34_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO34_FUN_DRV_M  (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S)
-#define IO_MUX_GPIO34_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO34_FUN_DRV_S  10
-/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO34_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO34_MCU_SEL_M  (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S)
-#define IO_MUX_GPIO34_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO34_MCU_SEL_S  12
-/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO34_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO34_FILTER_EN_M  (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S)
-#define IO_MUX_GPIO34_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO34_FILTER_EN_S  15
-
-/** IO_MUX_gpio35_REG register
- *  iomux control register for gpio35
- */
-#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90)
-/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO35_MCU_OE_M  (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S)
-#define IO_MUX_GPIO35_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_OE_S  0
-/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO35_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO35_SLP_SEL_M  (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S)
-#define IO_MUX_GPIO35_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO35_SLP_SEL_S  1
-/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO35_MCU_WPD_M  (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S)
-#define IO_MUX_GPIO35_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_WPD_S  2
-/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO35_MCU_WPU_M  (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S)
-#define IO_MUX_GPIO35_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_WPU_S  3
-/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO35_MCU_IE_M  (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S)
-#define IO_MUX_GPIO35_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_IE_S  4
-/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO35_MCU_DRV_M  (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S)
-#define IO_MUX_GPIO35_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO35_MCU_DRV_S  5
-/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO35_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO35_FUN_WPD_M  (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S)
-#define IO_MUX_GPIO35_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO35_FUN_WPD_S  7
-/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO35_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO35_FUN_WPU_M  (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S)
-#define IO_MUX_GPIO35_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO35_FUN_WPU_S  8
-/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO35_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO35_FUN_IE_M  (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S)
-#define IO_MUX_GPIO35_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO35_FUN_IE_S  9
-/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO35_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO35_FUN_DRV_M  (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S)
-#define IO_MUX_GPIO35_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO35_FUN_DRV_S  10
-/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO35_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO35_MCU_SEL_M  (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S)
-#define IO_MUX_GPIO35_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO35_MCU_SEL_S  12
-/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO35_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO35_FILTER_EN_M  (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S)
-#define IO_MUX_GPIO35_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO35_FILTER_EN_S  15
-
-/** IO_MUX_gpio36_REG register
- *  iomux control register for gpio36
- */
-#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94)
-/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO36_MCU_OE_M  (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S)
-#define IO_MUX_GPIO36_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_OE_S  0
-/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO36_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO36_SLP_SEL_M  (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S)
-#define IO_MUX_GPIO36_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO36_SLP_SEL_S  1
-/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO36_MCU_WPD_M  (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S)
-#define IO_MUX_GPIO36_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_WPD_S  2
-/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO36_MCU_WPU_M  (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S)
-#define IO_MUX_GPIO36_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_WPU_S  3
-/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO36_MCU_IE_M  (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S)
-#define IO_MUX_GPIO36_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_IE_S  4
-/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO36_MCU_DRV_M  (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S)
-#define IO_MUX_GPIO36_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO36_MCU_DRV_S  5
-/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO36_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO36_FUN_WPD_M  (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S)
-#define IO_MUX_GPIO36_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO36_FUN_WPD_S  7
-/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO36_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO36_FUN_WPU_M  (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S)
-#define IO_MUX_GPIO36_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO36_FUN_WPU_S  8
-/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO36_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO36_FUN_IE_M  (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S)
-#define IO_MUX_GPIO36_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO36_FUN_IE_S  9
-/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO36_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO36_FUN_DRV_M  (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S)
-#define IO_MUX_GPIO36_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO36_FUN_DRV_S  10
-/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO36_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO36_MCU_SEL_M  (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S)
-#define IO_MUX_GPIO36_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO36_MCU_SEL_S  12
-/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO36_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO36_FILTER_EN_M  (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S)
-#define IO_MUX_GPIO36_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO36_FILTER_EN_S  15
-
-/** IO_MUX_gpio37_REG register
- *  iomux control register for gpio37
- */
-#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98)
-/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO37_MCU_OE_M  (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S)
-#define IO_MUX_GPIO37_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_OE_S  0
-/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO37_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO37_SLP_SEL_M  (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S)
-#define IO_MUX_GPIO37_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO37_SLP_SEL_S  1
-/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO37_MCU_WPD_M  (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S)
-#define IO_MUX_GPIO37_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_WPD_S  2
-/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO37_MCU_WPU_M  (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S)
-#define IO_MUX_GPIO37_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_WPU_S  3
-/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO37_MCU_IE_M  (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S)
-#define IO_MUX_GPIO37_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_IE_S  4
-/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO37_MCU_DRV_M  (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S)
-#define IO_MUX_GPIO37_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO37_MCU_DRV_S  5
-/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO37_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO37_FUN_WPD_M  (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S)
-#define IO_MUX_GPIO37_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO37_FUN_WPD_S  7
-/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO37_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO37_FUN_WPU_M  (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S)
-#define IO_MUX_GPIO37_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO37_FUN_WPU_S  8
-/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO37_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO37_FUN_IE_M  (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S)
-#define IO_MUX_GPIO37_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO37_FUN_IE_S  9
-/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO37_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO37_FUN_DRV_M  (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S)
-#define IO_MUX_GPIO37_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO37_FUN_DRV_S  10
-/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO37_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO37_MCU_SEL_M  (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S)
-#define IO_MUX_GPIO37_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO37_MCU_SEL_S  12
-/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO37_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO37_FILTER_EN_M  (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S)
-#define IO_MUX_GPIO37_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO37_FILTER_EN_S  15
-
-/** IO_MUX_gpio38_REG register
- *  iomux control register for gpio38
- */
-#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c)
-/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO38_MCU_OE_M  (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S)
-#define IO_MUX_GPIO38_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_OE_S  0
-/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO38_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO38_SLP_SEL_M  (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S)
-#define IO_MUX_GPIO38_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO38_SLP_SEL_S  1
-/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO38_MCU_WPD_M  (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S)
-#define IO_MUX_GPIO38_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_WPD_S  2
-/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO38_MCU_WPU_M  (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S)
-#define IO_MUX_GPIO38_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_WPU_S  3
-/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO38_MCU_IE_M  (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S)
-#define IO_MUX_GPIO38_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_IE_S  4
-/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO38_MCU_DRV_M  (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S)
-#define IO_MUX_GPIO38_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO38_MCU_DRV_S  5
-/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO38_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO38_FUN_WPD_M  (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S)
-#define IO_MUX_GPIO38_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO38_FUN_WPD_S  7
-/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO38_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO38_FUN_WPU_M  (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S)
-#define IO_MUX_GPIO38_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO38_FUN_WPU_S  8
-/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO38_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO38_FUN_IE_M  (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S)
-#define IO_MUX_GPIO38_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO38_FUN_IE_S  9
-/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO38_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO38_FUN_DRV_M  (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S)
-#define IO_MUX_GPIO38_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO38_FUN_DRV_S  10
-/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO38_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO38_MCU_SEL_M  (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S)
-#define IO_MUX_GPIO38_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO38_MCU_SEL_S  12
-/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO38_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO38_FILTER_EN_M  (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S)
-#define IO_MUX_GPIO38_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO38_FILTER_EN_S  15
-
-/** IO_MUX_gpio39_REG register
- *  iomux control register for gpio39
- */
-#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0)
-/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO39_MCU_OE_M  (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S)
-#define IO_MUX_GPIO39_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_OE_S  0
-/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO39_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO39_SLP_SEL_M  (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S)
-#define IO_MUX_GPIO39_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO39_SLP_SEL_S  1
-/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO39_MCU_WPD_M  (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S)
-#define IO_MUX_GPIO39_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_WPD_S  2
-/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO39_MCU_WPU_M  (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S)
-#define IO_MUX_GPIO39_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_WPU_S  3
-/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO39_MCU_IE_M  (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S)
-#define IO_MUX_GPIO39_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_IE_S  4
-/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO39_MCU_DRV_M  (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S)
-#define IO_MUX_GPIO39_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO39_MCU_DRV_S  5
-/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO39_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO39_FUN_WPD_M  (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S)
-#define IO_MUX_GPIO39_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO39_FUN_WPD_S  7
-/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO39_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO39_FUN_WPU_M  (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S)
-#define IO_MUX_GPIO39_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO39_FUN_WPU_S  8
-/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO39_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO39_FUN_IE_M  (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S)
-#define IO_MUX_GPIO39_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO39_FUN_IE_S  9
-/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO39_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO39_FUN_DRV_M  (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S)
-#define IO_MUX_GPIO39_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO39_FUN_DRV_S  10
-/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO39_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO39_MCU_SEL_M  (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S)
-#define IO_MUX_GPIO39_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO39_MCU_SEL_S  12
-/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO39_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO39_FILTER_EN_M  (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S)
-#define IO_MUX_GPIO39_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO39_FILTER_EN_S  15
-
-/** IO_MUX_gpio40_REG register
- *  iomux control register for gpio40
- */
-#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4)
-/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO40_MCU_OE_M  (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S)
-#define IO_MUX_GPIO40_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_OE_S  0
-/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO40_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO40_SLP_SEL_M  (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S)
-#define IO_MUX_GPIO40_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO40_SLP_SEL_S  1
-/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO40_MCU_WPD_M  (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S)
-#define IO_MUX_GPIO40_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_WPD_S  2
-/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO40_MCU_WPU_M  (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S)
-#define IO_MUX_GPIO40_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_WPU_S  3
-/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO40_MCU_IE_M  (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S)
-#define IO_MUX_GPIO40_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_IE_S  4
-/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO40_MCU_DRV_M  (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S)
-#define IO_MUX_GPIO40_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO40_MCU_DRV_S  5
-/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO40_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO40_FUN_WPD_M  (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S)
-#define IO_MUX_GPIO40_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO40_FUN_WPD_S  7
-/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO40_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO40_FUN_WPU_M  (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S)
-#define IO_MUX_GPIO40_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO40_FUN_WPU_S  8
-/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO40_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO40_FUN_IE_M  (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S)
-#define IO_MUX_GPIO40_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO40_FUN_IE_S  9
-/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO40_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO40_FUN_DRV_M  (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S)
-#define IO_MUX_GPIO40_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO40_FUN_DRV_S  10
-/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO40_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO40_MCU_SEL_M  (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S)
-#define IO_MUX_GPIO40_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO40_MCU_SEL_S  12
-/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO40_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO40_FILTER_EN_M  (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S)
-#define IO_MUX_GPIO40_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO40_FILTER_EN_S  15
-
-/** IO_MUX_gpio41_REG register
- *  iomux control register for gpio41
- */
-#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8)
-/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO41_MCU_OE_M  (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S)
-#define IO_MUX_GPIO41_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_OE_S  0
-/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO41_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO41_SLP_SEL_M  (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S)
-#define IO_MUX_GPIO41_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO41_SLP_SEL_S  1
-/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO41_MCU_WPD_M  (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S)
-#define IO_MUX_GPIO41_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_WPD_S  2
-/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO41_MCU_WPU_M  (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S)
-#define IO_MUX_GPIO41_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_WPU_S  3
-/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO41_MCU_IE_M  (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S)
-#define IO_MUX_GPIO41_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_IE_S  4
-/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO41_MCU_DRV_M  (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S)
-#define IO_MUX_GPIO41_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO41_MCU_DRV_S  5
-/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO41_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO41_FUN_WPD_M  (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S)
-#define IO_MUX_GPIO41_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO41_FUN_WPD_S  7
-/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO41_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO41_FUN_WPU_M  (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S)
-#define IO_MUX_GPIO41_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO41_FUN_WPU_S  8
-/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO41_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO41_FUN_IE_M  (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S)
-#define IO_MUX_GPIO41_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO41_FUN_IE_S  9
-/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO41_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO41_FUN_DRV_M  (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S)
-#define IO_MUX_GPIO41_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO41_FUN_DRV_S  10
-/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO41_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO41_MCU_SEL_M  (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S)
-#define IO_MUX_GPIO41_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO41_MCU_SEL_S  12
-/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO41_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO41_FILTER_EN_M  (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S)
-#define IO_MUX_GPIO41_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO41_FILTER_EN_S  15
-
-/** IO_MUX_gpio42_REG register
- *  iomux control register for gpio42
- */
-#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac)
-/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO42_MCU_OE_M  (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S)
-#define IO_MUX_GPIO42_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_OE_S  0
-/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO42_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO42_SLP_SEL_M  (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S)
-#define IO_MUX_GPIO42_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO42_SLP_SEL_S  1
-/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO42_MCU_WPD_M  (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S)
-#define IO_MUX_GPIO42_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_WPD_S  2
-/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO42_MCU_WPU_M  (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S)
-#define IO_MUX_GPIO42_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_WPU_S  3
-/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO42_MCU_IE_M  (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S)
-#define IO_MUX_GPIO42_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_IE_S  4
-/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO42_MCU_DRV_M  (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S)
-#define IO_MUX_GPIO42_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO42_MCU_DRV_S  5
-/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO42_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO42_FUN_WPD_M  (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S)
-#define IO_MUX_GPIO42_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO42_FUN_WPD_S  7
-/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO42_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO42_FUN_WPU_M  (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S)
-#define IO_MUX_GPIO42_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO42_FUN_WPU_S  8
-/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO42_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO42_FUN_IE_M  (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S)
-#define IO_MUX_GPIO42_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO42_FUN_IE_S  9
-/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO42_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO42_FUN_DRV_M  (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S)
-#define IO_MUX_GPIO42_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO42_FUN_DRV_S  10
-/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO42_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO42_MCU_SEL_M  (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S)
-#define IO_MUX_GPIO42_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO42_MCU_SEL_S  12
-/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO42_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO42_FILTER_EN_M  (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S)
-#define IO_MUX_GPIO42_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO42_FILTER_EN_S  15
-
-/** IO_MUX_gpio43_REG register
- *  iomux control register for gpio43
- */
-#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0)
-/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO43_MCU_OE_M  (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S)
-#define IO_MUX_GPIO43_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_OE_S  0
-/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO43_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO43_SLP_SEL_M  (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S)
-#define IO_MUX_GPIO43_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO43_SLP_SEL_S  1
-/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO43_MCU_WPD_M  (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S)
-#define IO_MUX_GPIO43_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_WPD_S  2
-/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO43_MCU_WPU_M  (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S)
-#define IO_MUX_GPIO43_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_WPU_S  3
-/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO43_MCU_IE_M  (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S)
-#define IO_MUX_GPIO43_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_IE_S  4
-/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO43_MCU_DRV_M  (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S)
-#define IO_MUX_GPIO43_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO43_MCU_DRV_S  5
-/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO43_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO43_FUN_WPD_M  (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S)
-#define IO_MUX_GPIO43_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO43_FUN_WPD_S  7
-/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO43_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO43_FUN_WPU_M  (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S)
-#define IO_MUX_GPIO43_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO43_FUN_WPU_S  8
-/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO43_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO43_FUN_IE_M  (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S)
-#define IO_MUX_GPIO43_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO43_FUN_IE_S  9
-/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO43_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO43_FUN_DRV_M  (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S)
-#define IO_MUX_GPIO43_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO43_FUN_DRV_S  10
-/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO43_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO43_MCU_SEL_M  (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S)
-#define IO_MUX_GPIO43_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO43_MCU_SEL_S  12
-/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO43_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO43_FILTER_EN_M  (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S)
-#define IO_MUX_GPIO43_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO43_FILTER_EN_S  15
-
-/** IO_MUX_gpio44_REG register
- *  iomux control register for gpio44
- */
-#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4)
-/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO44_MCU_OE_M  (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S)
-#define IO_MUX_GPIO44_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_OE_S  0
-/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO44_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO44_SLP_SEL_M  (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S)
-#define IO_MUX_GPIO44_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO44_SLP_SEL_S  1
-/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO44_MCU_WPD_M  (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S)
-#define IO_MUX_GPIO44_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_WPD_S  2
-/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO44_MCU_WPU_M  (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S)
-#define IO_MUX_GPIO44_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_WPU_S  3
-/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO44_MCU_IE_M  (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S)
-#define IO_MUX_GPIO44_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_IE_S  4
-/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO44_MCU_DRV_M  (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S)
-#define IO_MUX_GPIO44_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO44_MCU_DRV_S  5
-/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO44_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO44_FUN_WPD_M  (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S)
-#define IO_MUX_GPIO44_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO44_FUN_WPD_S  7
-/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO44_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO44_FUN_WPU_M  (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S)
-#define IO_MUX_GPIO44_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO44_FUN_WPU_S  8
-/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO44_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO44_FUN_IE_M  (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S)
-#define IO_MUX_GPIO44_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO44_FUN_IE_S  9
-/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO44_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO44_FUN_DRV_M  (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S)
-#define IO_MUX_GPIO44_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO44_FUN_DRV_S  10
-/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO44_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO44_MCU_SEL_M  (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S)
-#define IO_MUX_GPIO44_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO44_MCU_SEL_S  12
-/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO44_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO44_FILTER_EN_M  (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S)
-#define IO_MUX_GPIO44_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO44_FILTER_EN_S  15
-
-/** IO_MUX_gpio45_REG register
- *  iomux control register for gpio45
- */
-#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8)
-/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO45_MCU_OE_M  (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S)
-#define IO_MUX_GPIO45_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_OE_S  0
-/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO45_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO45_SLP_SEL_M  (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S)
-#define IO_MUX_GPIO45_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO45_SLP_SEL_S  1
-/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO45_MCU_WPD_M  (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S)
-#define IO_MUX_GPIO45_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_WPD_S  2
-/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO45_MCU_WPU_M  (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S)
-#define IO_MUX_GPIO45_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_WPU_S  3
-/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO45_MCU_IE_M  (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S)
-#define IO_MUX_GPIO45_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_IE_S  4
-/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO45_MCU_DRV_M  (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S)
-#define IO_MUX_GPIO45_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO45_MCU_DRV_S  5
-/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO45_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO45_FUN_WPD_M  (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S)
-#define IO_MUX_GPIO45_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO45_FUN_WPD_S  7
-/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO45_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO45_FUN_WPU_M  (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S)
-#define IO_MUX_GPIO45_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO45_FUN_WPU_S  8
-/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO45_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO45_FUN_IE_M  (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S)
-#define IO_MUX_GPIO45_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO45_FUN_IE_S  9
-/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO45_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO45_FUN_DRV_M  (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S)
-#define IO_MUX_GPIO45_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO45_FUN_DRV_S  10
-/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO45_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO45_MCU_SEL_M  (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S)
-#define IO_MUX_GPIO45_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO45_MCU_SEL_S  12
-/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO45_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO45_FILTER_EN_M  (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S)
-#define IO_MUX_GPIO45_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO45_FILTER_EN_S  15
-
-/** IO_MUX_gpio46_REG register
- *  iomux control register for gpio46
- */
-#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc)
-/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO46_MCU_OE_M  (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S)
-#define IO_MUX_GPIO46_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_OE_S  0
-/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO46_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO46_SLP_SEL_M  (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S)
-#define IO_MUX_GPIO46_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO46_SLP_SEL_S  1
-/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO46_MCU_WPD_M  (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S)
-#define IO_MUX_GPIO46_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_WPD_S  2
-/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO46_MCU_WPU_M  (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S)
-#define IO_MUX_GPIO46_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_WPU_S  3
-/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO46_MCU_IE_M  (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S)
-#define IO_MUX_GPIO46_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_IE_S  4
-/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO46_MCU_DRV_M  (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S)
-#define IO_MUX_GPIO46_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO46_MCU_DRV_S  5
-/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO46_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO46_FUN_WPD_M  (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S)
-#define IO_MUX_GPIO46_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO46_FUN_WPD_S  7
-/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO46_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO46_FUN_WPU_M  (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S)
-#define IO_MUX_GPIO46_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO46_FUN_WPU_S  8
-/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO46_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO46_FUN_IE_M  (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S)
-#define IO_MUX_GPIO46_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO46_FUN_IE_S  9
-/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO46_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO46_FUN_DRV_M  (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S)
-#define IO_MUX_GPIO46_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO46_FUN_DRV_S  10
-/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO46_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO46_MCU_SEL_M  (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S)
-#define IO_MUX_GPIO46_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO46_MCU_SEL_S  12
-/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO46_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO46_FILTER_EN_M  (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S)
-#define IO_MUX_GPIO46_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO46_FILTER_EN_S  15
-
-/** IO_MUX_gpio47_REG register
- *  iomux control register for gpio47
- */
-#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0)
-/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO47_MCU_OE_M  (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S)
-#define IO_MUX_GPIO47_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_OE_S  0
-/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO47_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO47_SLP_SEL_M  (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S)
-#define IO_MUX_GPIO47_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO47_SLP_SEL_S  1
-/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO47_MCU_WPD_M  (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S)
-#define IO_MUX_GPIO47_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_WPD_S  2
-/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO47_MCU_WPU_M  (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S)
-#define IO_MUX_GPIO47_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_WPU_S  3
-/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO47_MCU_IE_M  (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S)
-#define IO_MUX_GPIO47_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_IE_S  4
-/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO47_MCU_DRV_M  (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S)
-#define IO_MUX_GPIO47_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO47_MCU_DRV_S  5
-/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO47_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO47_FUN_WPD_M  (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S)
-#define IO_MUX_GPIO47_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO47_FUN_WPD_S  7
-/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO47_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO47_FUN_WPU_M  (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S)
-#define IO_MUX_GPIO47_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO47_FUN_WPU_S  8
-/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO47_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO47_FUN_IE_M  (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S)
-#define IO_MUX_GPIO47_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO47_FUN_IE_S  9
-/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO47_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO47_FUN_DRV_M  (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S)
-#define IO_MUX_GPIO47_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO47_FUN_DRV_S  10
-/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO47_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO47_MCU_SEL_M  (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S)
-#define IO_MUX_GPIO47_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO47_MCU_SEL_S  12
-/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO47_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO47_FILTER_EN_M  (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S)
-#define IO_MUX_GPIO47_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO47_FILTER_EN_S  15
-
-/** IO_MUX_gpio48_REG register
- *  iomux control register for gpio48
- */
-#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4)
-/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO48_MCU_OE_M  (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S)
-#define IO_MUX_GPIO48_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_OE_S  0
-/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO48_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO48_SLP_SEL_M  (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S)
-#define IO_MUX_GPIO48_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO48_SLP_SEL_S  1
-/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO48_MCU_WPD_M  (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S)
-#define IO_MUX_GPIO48_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_WPD_S  2
-/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO48_MCU_WPU_M  (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S)
-#define IO_MUX_GPIO48_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_WPU_S  3
-/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO48_MCU_IE_M  (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S)
-#define IO_MUX_GPIO48_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_IE_S  4
-/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO48_MCU_DRV_M  (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S)
-#define IO_MUX_GPIO48_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO48_MCU_DRV_S  5
-/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO48_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO48_FUN_WPD_M  (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S)
-#define IO_MUX_GPIO48_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO48_FUN_WPD_S  7
-/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO48_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO48_FUN_WPU_M  (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S)
-#define IO_MUX_GPIO48_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO48_FUN_WPU_S  8
-/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO48_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO48_FUN_IE_M  (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S)
-#define IO_MUX_GPIO48_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO48_FUN_IE_S  9
-/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO48_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO48_FUN_DRV_M  (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S)
-#define IO_MUX_GPIO48_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO48_FUN_DRV_S  10
-/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO48_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO48_MCU_SEL_M  (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S)
-#define IO_MUX_GPIO48_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO48_MCU_SEL_S  12
-/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO48_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO48_FILTER_EN_M  (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S)
-#define IO_MUX_GPIO48_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO48_FILTER_EN_S  15
-
-/** IO_MUX_gpio49_REG register
- *  iomux control register for gpio49
- */
-#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8)
-/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO49_MCU_OE_M  (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S)
-#define IO_MUX_GPIO49_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_OE_S  0
-/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO49_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO49_SLP_SEL_M  (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S)
-#define IO_MUX_GPIO49_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO49_SLP_SEL_S  1
-/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO49_MCU_WPD_M  (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S)
-#define IO_MUX_GPIO49_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_WPD_S  2
-/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO49_MCU_WPU_M  (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S)
-#define IO_MUX_GPIO49_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_WPU_S  3
-/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO49_MCU_IE_M  (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S)
-#define IO_MUX_GPIO49_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_IE_S  4
-/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO49_MCU_DRV_M  (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S)
-#define IO_MUX_GPIO49_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO49_MCU_DRV_S  5
-/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO49_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO49_FUN_WPD_M  (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S)
-#define IO_MUX_GPIO49_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO49_FUN_WPD_S  7
-/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO49_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO49_FUN_WPU_M  (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S)
-#define IO_MUX_GPIO49_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO49_FUN_WPU_S  8
-/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO49_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO49_FUN_IE_M  (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S)
-#define IO_MUX_GPIO49_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO49_FUN_IE_S  9
-/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO49_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO49_FUN_DRV_M  (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S)
-#define IO_MUX_GPIO49_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO49_FUN_DRV_S  10
-/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO49_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO49_MCU_SEL_M  (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S)
-#define IO_MUX_GPIO49_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO49_MCU_SEL_S  12
-/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO49_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO49_FILTER_EN_M  (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S)
-#define IO_MUX_GPIO49_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO49_FILTER_EN_S  15
-
-/** IO_MUX_gpio50_REG register
- *  iomux control register for gpio50
- */
-#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc)
-/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO50_MCU_OE_M  (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S)
-#define IO_MUX_GPIO50_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_OE_S  0
-/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO50_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO50_SLP_SEL_M  (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S)
-#define IO_MUX_GPIO50_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO50_SLP_SEL_S  1
-/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO50_MCU_WPD_M  (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S)
-#define IO_MUX_GPIO50_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_WPD_S  2
-/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO50_MCU_WPU_M  (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S)
-#define IO_MUX_GPIO50_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_WPU_S  3
-/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO50_MCU_IE_M  (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S)
-#define IO_MUX_GPIO50_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_IE_S  4
-/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO50_MCU_DRV_M  (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S)
-#define IO_MUX_GPIO50_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO50_MCU_DRV_S  5
-/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO50_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO50_FUN_WPD_M  (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S)
-#define IO_MUX_GPIO50_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO50_FUN_WPD_S  7
-/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO50_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO50_FUN_WPU_M  (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S)
-#define IO_MUX_GPIO50_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO50_FUN_WPU_S  8
-/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO50_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO50_FUN_IE_M  (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S)
-#define IO_MUX_GPIO50_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO50_FUN_IE_S  9
-/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO50_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO50_FUN_DRV_M  (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S)
-#define IO_MUX_GPIO50_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO50_FUN_DRV_S  10
-/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO50_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO50_MCU_SEL_M  (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S)
-#define IO_MUX_GPIO50_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO50_MCU_SEL_S  12
-/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO50_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO50_FILTER_EN_M  (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S)
-#define IO_MUX_GPIO50_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO50_FILTER_EN_S  15
-
-/** IO_MUX_gpio51_REG register
- *  iomux control register for gpio51
- */
-#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0)
-/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO51_MCU_OE_M  (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S)
-#define IO_MUX_GPIO51_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_OE_S  0
-/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO51_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO51_SLP_SEL_M  (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S)
-#define IO_MUX_GPIO51_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO51_SLP_SEL_S  1
-/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO51_MCU_WPD_M  (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S)
-#define IO_MUX_GPIO51_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_WPD_S  2
-/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO51_MCU_WPU_M  (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S)
-#define IO_MUX_GPIO51_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_WPU_S  3
-/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO51_MCU_IE_M  (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S)
-#define IO_MUX_GPIO51_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_IE_S  4
-/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO51_MCU_DRV_M  (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S)
-#define IO_MUX_GPIO51_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO51_MCU_DRV_S  5
-/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO51_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO51_FUN_WPD_M  (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S)
-#define IO_MUX_GPIO51_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO51_FUN_WPD_S  7
-/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO51_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO51_FUN_WPU_M  (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S)
-#define IO_MUX_GPIO51_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO51_FUN_WPU_S  8
-/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO51_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO51_FUN_IE_M  (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S)
-#define IO_MUX_GPIO51_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO51_FUN_IE_S  9
-/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO51_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO51_FUN_DRV_M  (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S)
-#define IO_MUX_GPIO51_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO51_FUN_DRV_S  10
-/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO51_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO51_MCU_SEL_M  (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S)
-#define IO_MUX_GPIO51_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO51_MCU_SEL_S  12
-/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO51_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO51_FILTER_EN_M  (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S)
-#define IO_MUX_GPIO51_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO51_FILTER_EN_S  15
-
-/** IO_MUX_gpio52_REG register
- *  iomux control register for gpio52
- */
-#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4)
-/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO52_MCU_OE_M  (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S)
-#define IO_MUX_GPIO52_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_OE_S  0
-/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO52_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO52_SLP_SEL_M  (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S)
-#define IO_MUX_GPIO52_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO52_SLP_SEL_S  1
-/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO52_MCU_WPD_M  (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S)
-#define IO_MUX_GPIO52_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_WPD_S  2
-/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO52_MCU_WPU_M  (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S)
-#define IO_MUX_GPIO52_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_WPU_S  3
-/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO52_MCU_IE_M  (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S)
-#define IO_MUX_GPIO52_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_IE_S  4
-/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO52_MCU_DRV_M  (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S)
-#define IO_MUX_GPIO52_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO52_MCU_DRV_S  5
-/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO52_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO52_FUN_WPD_M  (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S)
-#define IO_MUX_GPIO52_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO52_FUN_WPD_S  7
-/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO52_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO52_FUN_WPU_M  (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S)
-#define IO_MUX_GPIO52_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO52_FUN_WPU_S  8
-/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO52_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO52_FUN_IE_M  (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S)
-#define IO_MUX_GPIO52_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO52_FUN_IE_S  9
-/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO52_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO52_FUN_DRV_M  (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S)
-#define IO_MUX_GPIO52_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO52_FUN_DRV_S  10
-/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO52_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO52_MCU_SEL_M  (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S)
-#define IO_MUX_GPIO52_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO52_MCU_SEL_S  12
-/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO52_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO52_FILTER_EN_M  (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S)
-#define IO_MUX_GPIO52_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO52_FILTER_EN_S  15
-
-/** IO_MUX_gpio53_REG register
- *  iomux control register for gpio53
- */
-#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8)
-/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO53_MCU_OE_M  (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S)
-#define IO_MUX_GPIO53_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_OE_S  0
-/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO53_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO53_SLP_SEL_M  (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S)
-#define IO_MUX_GPIO53_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO53_SLP_SEL_S  1
-/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO53_MCU_WPD_M  (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S)
-#define IO_MUX_GPIO53_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_WPD_S  2
-/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO53_MCU_WPU_M  (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S)
-#define IO_MUX_GPIO53_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_WPU_S  3
-/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO53_MCU_IE_M  (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S)
-#define IO_MUX_GPIO53_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_IE_S  4
-/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO53_MCU_DRV_M  (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S)
-#define IO_MUX_GPIO53_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO53_MCU_DRV_S  5
-/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO53_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO53_FUN_WPD_M  (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S)
-#define IO_MUX_GPIO53_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO53_FUN_WPD_S  7
-/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO53_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO53_FUN_WPU_M  (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S)
-#define IO_MUX_GPIO53_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO53_FUN_WPU_S  8
-/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO53_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO53_FUN_IE_M  (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S)
-#define IO_MUX_GPIO53_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO53_FUN_IE_S  9
-/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO53_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO53_FUN_DRV_M  (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S)
-#define IO_MUX_GPIO53_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO53_FUN_DRV_S  10
-/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO53_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO53_MCU_SEL_M  (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S)
-#define IO_MUX_GPIO53_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO53_MCU_SEL_S  12
-/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO53_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO53_FILTER_EN_M  (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S)
-#define IO_MUX_GPIO53_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO53_FILTER_EN_S  15
-
-/** IO_MUX_gpio54_REG register
- *  iomux control register for gpio54
- */
-#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc)
-/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO54_MCU_OE_M  (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S)
-#define IO_MUX_GPIO54_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_OE_S  0
-/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO54_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO54_SLP_SEL_M  (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S)
-#define IO_MUX_GPIO54_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO54_SLP_SEL_S  1
-/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO54_MCU_WPD_M  (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S)
-#define IO_MUX_GPIO54_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_WPD_S  2
-/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO54_MCU_WPU_M  (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S)
-#define IO_MUX_GPIO54_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_WPU_S  3
-/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO54_MCU_IE_M  (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S)
-#define IO_MUX_GPIO54_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_IE_S  4
-/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO54_MCU_DRV_M  (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S)
-#define IO_MUX_GPIO54_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO54_MCU_DRV_S  5
-/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO54_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO54_FUN_WPD_M  (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S)
-#define IO_MUX_GPIO54_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO54_FUN_WPD_S  7
-/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO54_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO54_FUN_WPU_M  (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S)
-#define IO_MUX_GPIO54_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO54_FUN_WPU_S  8
-/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO54_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO54_FUN_IE_M  (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S)
-#define IO_MUX_GPIO54_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO54_FUN_IE_S  9
-/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO54_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO54_FUN_DRV_M  (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S)
-#define IO_MUX_GPIO54_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO54_FUN_DRV_S  10
-/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO54_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO54_MCU_SEL_M  (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S)
-#define IO_MUX_GPIO54_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO54_MCU_SEL_S  12
-/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO54_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO54_FILTER_EN_M  (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S)
-#define IO_MUX_GPIO54_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO54_FILTER_EN_S  15
-
-/** IO_MUX_gpio55_REG register
- *  iomux control register for gpio55
- */
-#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0)
-/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO55_MCU_OE_M  (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S)
-#define IO_MUX_GPIO55_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_OE_S  0
-/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO55_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO55_SLP_SEL_M  (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S)
-#define IO_MUX_GPIO55_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO55_SLP_SEL_S  1
-/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO55_MCU_WPD_M  (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S)
-#define IO_MUX_GPIO55_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_WPD_S  2
-/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO55_MCU_WPU_M  (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S)
-#define IO_MUX_GPIO55_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_WPU_S  3
-/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO55_MCU_IE_M  (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S)
-#define IO_MUX_GPIO55_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_IE_S  4
-/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO55_MCU_DRV_M  (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S)
-#define IO_MUX_GPIO55_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO55_MCU_DRV_S  5
-/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO55_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO55_FUN_WPD_M  (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S)
-#define IO_MUX_GPIO55_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO55_FUN_WPD_S  7
-/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO55_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO55_FUN_WPU_M  (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S)
-#define IO_MUX_GPIO55_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO55_FUN_WPU_S  8
-/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO55_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO55_FUN_IE_M  (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S)
-#define IO_MUX_GPIO55_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO55_FUN_IE_S  9
-/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO55_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO55_FUN_DRV_M  (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S)
-#define IO_MUX_GPIO55_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO55_FUN_DRV_S  10
-/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO55_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO55_MCU_SEL_M  (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S)
-#define IO_MUX_GPIO55_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO55_MCU_SEL_S  12
-/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO55_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO55_FILTER_EN_M  (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S)
-#define IO_MUX_GPIO55_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO55_FILTER_EN_S  15
-
-/** IO_MUX_gpio56_REG register
- *  iomux control register for gpio56
- */
-#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4)
-/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO56_MCU_OE_M  (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S)
-#define IO_MUX_GPIO56_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_OE_S  0
-/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO56_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO56_SLP_SEL_M  (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S)
-#define IO_MUX_GPIO56_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO56_SLP_SEL_S  1
-/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO56_MCU_WPD_M  (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S)
-#define IO_MUX_GPIO56_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_WPD_S  2
-/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO56_MCU_WPU_M  (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S)
-#define IO_MUX_GPIO56_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_WPU_S  3
-/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO56_MCU_IE_M  (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S)
-#define IO_MUX_GPIO56_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_IE_S  4
-/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strenth on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO56_MCU_DRV_M  (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S)
-#define IO_MUX_GPIO56_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO56_MCU_DRV_S  5
-/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO56_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO56_FUN_WPD_M  (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S)
-#define IO_MUX_GPIO56_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO56_FUN_WPD_S  7
-/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO56_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO56_FUN_WPU_M  (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S)
-#define IO_MUX_GPIO56_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO56_FUN_WPU_S  8
-/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO56_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO56_FUN_IE_M  (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S)
-#define IO_MUX_GPIO56_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO56_FUN_IE_S  9
-/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO56_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO56_FUN_DRV_M  (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S)
-#define IO_MUX_GPIO56_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO56_FUN_DRV_S  10
-/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO56_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO56_MCU_SEL_M  (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S)
-#define IO_MUX_GPIO56_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO56_MCU_SEL_S  12
-/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO56_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO56_FILTER_EN_M  (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S)
-#define IO_MUX_GPIO56_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO56_FILTER_EN_S  15
-
-/** IO_MUX_DATE_REG register
- *  iomux version
- */
-#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104)
-/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794;
- *  csv date
- */
-#define IO_MUX_DATE    0x0FFFFFFFU
-#define IO_MUX_DATE_M  (IO_MUX_DATE_V << IO_MUX_DATE_S)
-#define IO_MUX_DATE_V  0x0FFFFFFFU
-#define IO_MUX_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/iomux_struct.h b/components/soc/esp32p4/include/soc/iomux_struct.h
deleted file mode 100644
index 583b6dec07..0000000000
--- a/components/soc/esp32p4/include/soc/iomux_struct.h
+++ /dev/null
@@ -1,3429 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: IOMUX Register */
-/** Type of gpio0 register
- *  iomux control register for gpio0
- */
-typedef union {
-    struct {
-        /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio0_mcu_oe:1;
-        /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio0_slp_sel:1;
-        /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio0_mcu_wpd:1;
-        /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio0_mcu_wpu:1;
-        /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio0_mcu_ie:1;
-        /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio0_mcu_drv:2;
-        /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio0_fun_wpd:1;
-        /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio0_fun_wpu:1;
-        /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio0_fun_ie:1;
-        /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio0_fun_drv:2;
-        /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio0_mcu_sel:3;
-        /** gpio0_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio0_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio0_reg_t;
-
-/** Type of gpio1 register
- *  iomux control register for gpio1
- */
-typedef union {
-    struct {
-        /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio1_mcu_oe:1;
-        /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio1_slp_sel:1;
-        /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio1_mcu_wpd:1;
-        /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio1_mcu_wpu:1;
-        /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio1_mcu_ie:1;
-        /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio1_mcu_drv:2;
-        /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio1_fun_wpd:1;
-        /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio1_fun_wpu:1;
-        /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio1_fun_ie:1;
-        /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio1_fun_drv:2;
-        /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio1_mcu_sel:3;
-        /** gpio1_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio1_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio1_reg_t;
-
-/** Type of gpio2 register
- *  iomux control register for gpio2
- */
-typedef union {
-    struct {
-        /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio2_mcu_oe:1;
-        /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio2_slp_sel:1;
-        /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio2_mcu_wpd:1;
-        /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio2_mcu_wpu:1;
-        /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio2_mcu_ie:1;
-        /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio2_mcu_drv:2;
-        /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio2_fun_wpd:1;
-        /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio2_fun_wpu:1;
-        /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio2_fun_ie:1;
-        /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio2_fun_drv:2;
-        /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio2_mcu_sel:3;
-        /** gpio2_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio2_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio2_reg_t;
-
-/** Type of gpio3 register
- *  iomux control register for gpio3
- */
-typedef union {
-    struct {
-        /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio3_mcu_oe:1;
-        /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio3_slp_sel:1;
-        /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio3_mcu_wpd:1;
-        /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio3_mcu_wpu:1;
-        /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio3_mcu_ie:1;
-        /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio3_mcu_drv:2;
-        /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio3_fun_wpd:1;
-        /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio3_fun_wpu:1;
-        /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio3_fun_ie:1;
-        /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio3_fun_drv:2;
-        /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio3_mcu_sel:3;
-        /** gpio3_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio3_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio3_reg_t;
-
-/** Type of gpio4 register
- *  iomux control register for gpio4
- */
-typedef union {
-    struct {
-        /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio4_mcu_oe:1;
-        /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio4_slp_sel:1;
-        /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio4_mcu_wpd:1;
-        /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio4_mcu_wpu:1;
-        /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio4_mcu_ie:1;
-        /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio4_mcu_drv:2;
-        /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio4_fun_wpd:1;
-        /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio4_fun_wpu:1;
-        /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio4_fun_ie:1;
-        /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio4_fun_drv:2;
-        /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio4_mcu_sel:3;
-        /** gpio4_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio4_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio4_reg_t;
-
-/** Type of gpio5 register
- *  iomux control register for gpio5
- */
-typedef union {
-    struct {
-        /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio5_mcu_oe:1;
-        /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio5_slp_sel:1;
-        /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio5_mcu_wpd:1;
-        /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio5_mcu_wpu:1;
-        /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio5_mcu_ie:1;
-        /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio5_mcu_drv:2;
-        /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio5_fun_wpd:1;
-        /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio5_fun_wpu:1;
-        /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio5_fun_ie:1;
-        /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio5_fun_drv:2;
-        /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio5_mcu_sel:3;
-        /** gpio5_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio5_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio5_reg_t;
-
-/** Type of gpio6 register
- *  iomux control register for gpio6
- */
-typedef union {
-    struct {
-        /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio6_mcu_oe:1;
-        /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio6_slp_sel:1;
-        /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio6_mcu_wpd:1;
-        /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio6_mcu_wpu:1;
-        /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio6_mcu_ie:1;
-        /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio6_mcu_drv:2;
-        /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio6_fun_wpd:1;
-        /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio6_fun_wpu:1;
-        /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio6_fun_ie:1;
-        /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio6_fun_drv:2;
-        /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio6_mcu_sel:3;
-        /** gpio6_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio6_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio6_reg_t;
-
-/** Type of gpio7 register
- *  iomux control register for gpio7
- */
-typedef union {
-    struct {
-        /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio7_mcu_oe:1;
-        /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio7_slp_sel:1;
-        /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio7_mcu_wpd:1;
-        /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio7_mcu_wpu:1;
-        /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio7_mcu_ie:1;
-        /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio7_mcu_drv:2;
-        /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio7_fun_wpd:1;
-        /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio7_fun_wpu:1;
-        /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio7_fun_ie:1;
-        /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio7_fun_drv:2;
-        /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio7_mcu_sel:3;
-        /** gpio7_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio7_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio7_reg_t;
-
-/** Type of gpio8 register
- *  iomux control register for gpio8
- */
-typedef union {
-    struct {
-        /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio8_mcu_oe:1;
-        /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio8_slp_sel:1;
-        /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio8_mcu_wpd:1;
-        /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio8_mcu_wpu:1;
-        /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio8_mcu_ie:1;
-        /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio8_mcu_drv:2;
-        /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio8_fun_wpd:1;
-        /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio8_fun_wpu:1;
-        /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio8_fun_ie:1;
-        /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio8_fun_drv:2;
-        /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio8_mcu_sel:3;
-        /** gpio8_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio8_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio8_reg_t;
-
-/** Type of gpio9 register
- *  iomux control register for gpio9
- */
-typedef union {
-    struct {
-        /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio9_mcu_oe:1;
-        /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio9_slp_sel:1;
-        /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio9_mcu_wpd:1;
-        /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio9_mcu_wpu:1;
-        /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio9_mcu_ie:1;
-        /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio9_mcu_drv:2;
-        /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio9_fun_wpd:1;
-        /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio9_fun_wpu:1;
-        /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio9_fun_ie:1;
-        /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio9_fun_drv:2;
-        /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio9_mcu_sel:3;
-        /** gpio9_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio9_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio9_reg_t;
-
-/** Type of gpio10 register
- *  iomux control register for gpio10
- */
-typedef union {
-    struct {
-        /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio10_mcu_oe:1;
-        /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio10_slp_sel:1;
-        /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio10_mcu_wpd:1;
-        /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio10_mcu_wpu:1;
-        /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio10_mcu_ie:1;
-        /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio10_mcu_drv:2;
-        /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio10_fun_wpd:1;
-        /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio10_fun_wpu:1;
-        /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio10_fun_ie:1;
-        /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio10_fun_drv:2;
-        /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio10_mcu_sel:3;
-        /** gpio10_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio10_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio10_reg_t;
-
-/** Type of gpio11 register
- *  iomux control register for gpio11
- */
-typedef union {
-    struct {
-        /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio11_mcu_oe:1;
-        /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio11_slp_sel:1;
-        /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio11_mcu_wpd:1;
-        /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio11_mcu_wpu:1;
-        /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio11_mcu_ie:1;
-        /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio11_mcu_drv:2;
-        /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio11_fun_wpd:1;
-        /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio11_fun_wpu:1;
-        /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio11_fun_ie:1;
-        /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio11_fun_drv:2;
-        /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio11_mcu_sel:3;
-        /** gpio11_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio11_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio11_reg_t;
-
-/** Type of gpio12 register
- *  iomux control register for gpio12
- */
-typedef union {
-    struct {
-        /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio12_mcu_oe:1;
-        /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio12_slp_sel:1;
-        /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio12_mcu_wpd:1;
-        /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio12_mcu_wpu:1;
-        /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio12_mcu_ie:1;
-        /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio12_mcu_drv:2;
-        /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio12_fun_wpd:1;
-        /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio12_fun_wpu:1;
-        /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio12_fun_ie:1;
-        /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio12_fun_drv:2;
-        /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio12_mcu_sel:3;
-        /** gpio12_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio12_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio12_reg_t;
-
-/** Type of gpio13 register
- *  iomux control register for gpio13
- */
-typedef union {
-    struct {
-        /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio13_mcu_oe:1;
-        /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio13_slp_sel:1;
-        /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio13_mcu_wpd:1;
-        /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio13_mcu_wpu:1;
-        /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio13_mcu_ie:1;
-        /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio13_mcu_drv:2;
-        /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio13_fun_wpd:1;
-        /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio13_fun_wpu:1;
-        /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio13_fun_ie:1;
-        /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio13_fun_drv:2;
-        /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio13_mcu_sel:3;
-        /** gpio13_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio13_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio13_reg_t;
-
-/** Type of gpio14 register
- *  iomux control register for gpio14
- */
-typedef union {
-    struct {
-        /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio14_mcu_oe:1;
-        /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio14_slp_sel:1;
-        /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio14_mcu_wpd:1;
-        /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio14_mcu_wpu:1;
-        /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio14_mcu_ie:1;
-        /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio14_mcu_drv:2;
-        /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio14_fun_wpd:1;
-        /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio14_fun_wpu:1;
-        /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio14_fun_ie:1;
-        /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio14_fun_drv:2;
-        /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio14_mcu_sel:3;
-        /** gpio14_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio14_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio14_reg_t;
-
-/** Type of gpio15 register
- *  iomux control register for gpio15
- */
-typedef union {
-    struct {
-        /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio15_mcu_oe:1;
-        /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio15_slp_sel:1;
-        /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio15_mcu_wpd:1;
-        /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio15_mcu_wpu:1;
-        /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio15_mcu_ie:1;
-        /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio15_mcu_drv:2;
-        /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio15_fun_wpd:1;
-        /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio15_fun_wpu:1;
-        /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio15_fun_ie:1;
-        /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio15_fun_drv:2;
-        /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio15_mcu_sel:3;
-        /** gpio15_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio15_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio15_reg_t;
-
-/** Type of gpio16 register
- *  iomux control register for gpio16
- */
-typedef union {
-    struct {
-        /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio16_mcu_oe:1;
-        /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio16_slp_sel:1;
-        /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio16_mcu_wpd:1;
-        /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio16_mcu_wpu:1;
-        /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio16_mcu_ie:1;
-        /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio16_mcu_drv:2;
-        /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio16_fun_wpd:1;
-        /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio16_fun_wpu:1;
-        /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio16_fun_ie:1;
-        /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio16_fun_drv:2;
-        /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio16_mcu_sel:3;
-        /** gpio16_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio16_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio16_reg_t;
-
-/** Type of gpio17 register
- *  iomux control register for gpio17
- */
-typedef union {
-    struct {
-        /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio17_mcu_oe:1;
-        /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio17_slp_sel:1;
-        /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio17_mcu_wpd:1;
-        /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio17_mcu_wpu:1;
-        /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio17_mcu_ie:1;
-        /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio17_mcu_drv:2;
-        /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio17_fun_wpd:1;
-        /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio17_fun_wpu:1;
-        /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio17_fun_ie:1;
-        /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio17_fun_drv:2;
-        /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio17_mcu_sel:3;
-        /** gpio17_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio17_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio17_reg_t;
-
-/** Type of gpio18 register
- *  iomux control register for gpio18
- */
-typedef union {
-    struct {
-        /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio18_mcu_oe:1;
-        /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio18_slp_sel:1;
-        /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio18_mcu_wpd:1;
-        /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio18_mcu_wpu:1;
-        /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio18_mcu_ie:1;
-        /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio18_mcu_drv:2;
-        /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio18_fun_wpd:1;
-        /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio18_fun_wpu:1;
-        /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio18_fun_ie:1;
-        /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio18_fun_drv:2;
-        /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio18_mcu_sel:3;
-        /** gpio18_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio18_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio18_reg_t;
-
-/** Type of gpio19 register
- *  iomux control register for gpio19
- */
-typedef union {
-    struct {
-        /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio19_mcu_oe:1;
-        /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio19_slp_sel:1;
-        /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio19_mcu_wpd:1;
-        /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio19_mcu_wpu:1;
-        /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio19_mcu_ie:1;
-        /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio19_mcu_drv:2;
-        /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio19_fun_wpd:1;
-        /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio19_fun_wpu:1;
-        /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio19_fun_ie:1;
-        /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio19_fun_drv:2;
-        /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio19_mcu_sel:3;
-        /** gpio19_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio19_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio19_reg_t;
-
-/** Type of gpio20 register
- *  iomux control register for gpio20
- */
-typedef union {
-    struct {
-        /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio20_mcu_oe:1;
-        /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio20_slp_sel:1;
-        /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio20_mcu_wpd:1;
-        /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio20_mcu_wpu:1;
-        /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio20_mcu_ie:1;
-        /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio20_mcu_drv:2;
-        /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio20_fun_wpd:1;
-        /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio20_fun_wpu:1;
-        /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio20_fun_ie:1;
-        /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio20_fun_drv:2;
-        /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio20_mcu_sel:3;
-        /** gpio20_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio20_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio20_reg_t;
-
-/** Type of gpio21 register
- *  iomux control register for gpio21
- */
-typedef union {
-    struct {
-        /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio21_mcu_oe:1;
-        /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio21_slp_sel:1;
-        /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio21_mcu_wpd:1;
-        /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio21_mcu_wpu:1;
-        /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio21_mcu_ie:1;
-        /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio21_mcu_drv:2;
-        /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio21_fun_wpd:1;
-        /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio21_fun_wpu:1;
-        /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio21_fun_ie:1;
-        /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio21_fun_drv:2;
-        /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio21_mcu_sel:3;
-        /** gpio21_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio21_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio21_reg_t;
-
-/** Type of gpio22 register
- *  iomux control register for gpio22
- */
-typedef union {
-    struct {
-        /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio22_mcu_oe:1;
-        /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio22_slp_sel:1;
-        /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio22_mcu_wpd:1;
-        /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio22_mcu_wpu:1;
-        /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio22_mcu_ie:1;
-        /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio22_mcu_drv:2;
-        /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio22_fun_wpd:1;
-        /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio22_fun_wpu:1;
-        /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio22_fun_ie:1;
-        /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio22_fun_drv:2;
-        /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio22_mcu_sel:3;
-        /** gpio22_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio22_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio22_reg_t;
-
-/** Type of gpio23 register
- *  iomux control register for gpio23
- */
-typedef union {
-    struct {
-        /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio23_mcu_oe:1;
-        /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio23_slp_sel:1;
-        /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio23_mcu_wpd:1;
-        /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio23_mcu_wpu:1;
-        /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio23_mcu_ie:1;
-        /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio23_mcu_drv:2;
-        /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio23_fun_wpd:1;
-        /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio23_fun_wpu:1;
-        /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio23_fun_ie:1;
-        /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio23_fun_drv:2;
-        /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio23_mcu_sel:3;
-        /** gpio23_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio23_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio23_reg_t;
-
-/** Type of gpio24 register
- *  iomux control register for gpio24
- */
-typedef union {
-    struct {
-        /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio24_mcu_oe:1;
-        /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio24_slp_sel:1;
-        /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio24_mcu_wpd:1;
-        /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio24_mcu_wpu:1;
-        /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio24_mcu_ie:1;
-        /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio24_mcu_drv:2;
-        /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio24_fun_wpd:1;
-        /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio24_fun_wpu:1;
-        /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio24_fun_ie:1;
-        /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio24_fun_drv:2;
-        /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio24_mcu_sel:3;
-        /** gpio24_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio24_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio24_reg_t;
-
-/** Type of gpio25 register
- *  iomux control register for gpio25
- */
-typedef union {
-    struct {
-        /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio25_mcu_oe:1;
-        /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio25_slp_sel:1;
-        /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio25_mcu_wpd:1;
-        /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio25_mcu_wpu:1;
-        /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio25_mcu_ie:1;
-        /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio25_mcu_drv:2;
-        /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio25_fun_wpd:1;
-        /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio25_fun_wpu:1;
-        /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio25_fun_ie:1;
-        /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio25_fun_drv:2;
-        /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio25_mcu_sel:3;
-        /** gpio25_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio25_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio25_reg_t;
-
-/** Type of gpio26 register
- *  iomux control register for gpio26
- */
-typedef union {
-    struct {
-        /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio26_mcu_oe:1;
-        /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio26_slp_sel:1;
-        /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio26_mcu_wpd:1;
-        /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio26_mcu_wpu:1;
-        /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio26_mcu_ie:1;
-        /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio26_mcu_drv:2;
-        /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio26_fun_wpd:1;
-        /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio26_fun_wpu:1;
-        /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio26_fun_ie:1;
-        /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio26_fun_drv:2;
-        /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio26_mcu_sel:3;
-        /** gpio26_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio26_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio26_reg_t;
-
-/** Type of gpio27 register
- *  iomux control register for gpio27
- */
-typedef union {
-    struct {
-        /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio27_mcu_oe:1;
-        /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio27_slp_sel:1;
-        /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio27_mcu_wpd:1;
-        /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio27_mcu_wpu:1;
-        /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio27_mcu_ie:1;
-        /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio27_mcu_drv:2;
-        /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio27_fun_wpd:1;
-        /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio27_fun_wpu:1;
-        /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio27_fun_ie:1;
-        /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio27_fun_drv:2;
-        /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio27_mcu_sel:3;
-        /** gpio27_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio27_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio27_reg_t;
-
-/** Type of gpio28 register
- *  iomux control register for gpio28
- */
-typedef union {
-    struct {
-        /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio28_mcu_oe:1;
-        /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio28_slp_sel:1;
-        /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio28_mcu_wpd:1;
-        /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio28_mcu_wpu:1;
-        /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio28_mcu_ie:1;
-        /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio28_mcu_drv:2;
-        /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio28_fun_wpd:1;
-        /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio28_fun_wpu:1;
-        /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio28_fun_ie:1;
-        /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio28_fun_drv:2;
-        /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio28_mcu_sel:3;
-        /** gpio28_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio28_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio28_reg_t;
-
-/** Type of gpio29 register
- *  iomux control register for gpio29
- */
-typedef union {
-    struct {
-        /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio29_mcu_oe:1;
-        /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio29_slp_sel:1;
-        /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio29_mcu_wpd:1;
-        /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio29_mcu_wpu:1;
-        /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio29_mcu_ie:1;
-        /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio29_mcu_drv:2;
-        /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio29_fun_wpd:1;
-        /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio29_fun_wpu:1;
-        /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio29_fun_ie:1;
-        /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio29_fun_drv:2;
-        /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio29_mcu_sel:3;
-        /** gpio29_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio29_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio29_reg_t;
-
-/** Type of gpio30 register
- *  iomux control register for gpio30
- */
-typedef union {
-    struct {
-        /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio30_mcu_oe:1;
-        /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio30_slp_sel:1;
-        /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio30_mcu_wpd:1;
-        /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio30_mcu_wpu:1;
-        /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio30_mcu_ie:1;
-        /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio30_mcu_drv:2;
-        /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio30_fun_wpd:1;
-        /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio30_fun_wpu:1;
-        /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio30_fun_ie:1;
-        /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio30_fun_drv:2;
-        /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio30_mcu_sel:3;
-        /** gpio30_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio30_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio30_reg_t;
-
-/** Type of gpio31 register
- *  iomux control register for gpio31
- */
-typedef union {
-    struct {
-        /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio31_mcu_oe:1;
-        /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio31_slp_sel:1;
-        /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio31_mcu_wpd:1;
-        /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio31_mcu_wpu:1;
-        /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio31_mcu_ie:1;
-        /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio31_mcu_drv:2;
-        /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio31_fun_wpd:1;
-        /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio31_fun_wpu:1;
-        /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio31_fun_ie:1;
-        /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio31_fun_drv:2;
-        /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio31_mcu_sel:3;
-        /** gpio31_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio31_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio31_reg_t;
-
-/** Type of gpio32 register
- *  iomux control register for gpio32
- */
-typedef union {
-    struct {
-        /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio32_mcu_oe:1;
-        /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio32_slp_sel:1;
-        /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio32_mcu_wpd:1;
-        /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio32_mcu_wpu:1;
-        /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio32_mcu_ie:1;
-        /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio32_mcu_drv:2;
-        /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio32_fun_wpd:1;
-        /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio32_fun_wpu:1;
-        /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio32_fun_ie:1;
-        /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio32_fun_drv:2;
-        /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio32_mcu_sel:3;
-        /** gpio32_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio32_filter_en:1;
-        /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t gpio32_rue_i3c:1;
-        /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0;
-         *  NA
-         */
-        uint32_t gpio32_ru_i3c:2;
-        /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t gpio32_rue_sel_i3c:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} io_mux_gpio32_reg_t;
-
-/** Type of gpio33 register
- *  iomux control register for gpio33
- */
-typedef union {
-    struct {
-        /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio33_mcu_oe:1;
-        /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio33_slp_sel:1;
-        /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio33_mcu_wpd:1;
-        /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio33_mcu_wpu:1;
-        /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio33_mcu_ie:1;
-        /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio33_mcu_drv:2;
-        /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio33_fun_wpd:1;
-        /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio33_fun_wpu:1;
-        /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio33_fun_ie:1;
-        /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio33_fun_drv:2;
-        /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio33_mcu_sel:3;
-        /** gpio33_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio33_filter_en:1;
-        /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t gpio33_rue_i3c:1;
-        /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0;
-         *  NA
-         */
-        uint32_t gpio33_ru_i3c:2;
-        /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t gpio33_rue_sel_i3c:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} io_mux_gpio33_reg_t;
-
-/** Type of gpio34 register
- *  iomux control register for gpio34
- */
-typedef union {
-    struct {
-        /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio34_mcu_oe:1;
-        /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio34_slp_sel:1;
-        /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio34_mcu_wpd:1;
-        /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio34_mcu_wpu:1;
-        /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio34_mcu_ie:1;
-        /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio34_mcu_drv:2;
-        /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio34_fun_wpd:1;
-        /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio34_fun_wpu:1;
-        /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio34_fun_ie:1;
-        /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio34_fun_drv:2;
-        /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio34_mcu_sel:3;
-        /** gpio34_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio34_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio34_reg_t;
-
-/** Type of gpio35 register
- *  iomux control register for gpio35
- */
-typedef union {
-    struct {
-        /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio35_mcu_oe:1;
-        /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio35_slp_sel:1;
-        /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio35_mcu_wpd:1;
-        /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio35_mcu_wpu:1;
-        /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio35_mcu_ie:1;
-        /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio35_mcu_drv:2;
-        /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio35_fun_wpd:1;
-        /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio35_fun_wpu:1;
-        /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio35_fun_ie:1;
-        /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio35_fun_drv:2;
-        /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio35_mcu_sel:3;
-        /** gpio35_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio35_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio35_reg_t;
-
-/** Type of gpio36 register
- *  iomux control register for gpio36
- */
-typedef union {
-    struct {
-        /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio36_mcu_oe:1;
-        /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio36_slp_sel:1;
-        /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio36_mcu_wpd:1;
-        /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio36_mcu_wpu:1;
-        /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio36_mcu_ie:1;
-        /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio36_mcu_drv:2;
-        /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio36_fun_wpd:1;
-        /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio36_fun_wpu:1;
-        /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio36_fun_ie:1;
-        /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio36_fun_drv:2;
-        /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio36_mcu_sel:3;
-        /** gpio36_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio36_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio36_reg_t;
-
-/** Type of gpio37 register
- *  iomux control register for gpio37
- */
-typedef union {
-    struct {
-        /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio37_mcu_oe:1;
-        /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio37_slp_sel:1;
-        /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio37_mcu_wpd:1;
-        /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio37_mcu_wpu:1;
-        /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio37_mcu_ie:1;
-        /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio37_mcu_drv:2;
-        /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio37_fun_wpd:1;
-        /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio37_fun_wpu:1;
-        /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio37_fun_ie:1;
-        /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio37_fun_drv:2;
-        /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio37_mcu_sel:3;
-        /** gpio37_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio37_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio37_reg_t;
-
-/** Type of gpio38 register
- *  iomux control register for gpio38
- */
-typedef union {
-    struct {
-        /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio38_mcu_oe:1;
-        /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio38_slp_sel:1;
-        /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio38_mcu_wpd:1;
-        /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio38_mcu_wpu:1;
-        /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio38_mcu_ie:1;
-        /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio38_mcu_drv:2;
-        /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio38_fun_wpd:1;
-        /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio38_fun_wpu:1;
-        /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio38_fun_ie:1;
-        /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio38_fun_drv:2;
-        /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio38_mcu_sel:3;
-        /** gpio38_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio38_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio38_reg_t;
-
-/** Type of gpio39 register
- *  iomux control register for gpio39
- */
-typedef union {
-    struct {
-        /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio39_mcu_oe:1;
-        /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio39_slp_sel:1;
-        /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio39_mcu_wpd:1;
-        /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio39_mcu_wpu:1;
-        /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio39_mcu_ie:1;
-        /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio39_mcu_drv:2;
-        /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio39_fun_wpd:1;
-        /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio39_fun_wpu:1;
-        /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio39_fun_ie:1;
-        /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio39_fun_drv:2;
-        /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio39_mcu_sel:3;
-        /** gpio39_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio39_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio39_reg_t;
-
-/** Type of gpio40 register
- *  iomux control register for gpio40
- */
-typedef union {
-    struct {
-        /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio40_mcu_oe:1;
-        /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio40_slp_sel:1;
-        /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio40_mcu_wpd:1;
-        /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio40_mcu_wpu:1;
-        /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio40_mcu_ie:1;
-        /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio40_mcu_drv:2;
-        /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio40_fun_wpd:1;
-        /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio40_fun_wpu:1;
-        /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio40_fun_ie:1;
-        /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio40_fun_drv:2;
-        /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio40_mcu_sel:3;
-        /** gpio40_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio40_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio40_reg_t;
-
-/** Type of gpio41 register
- *  iomux control register for gpio41
- */
-typedef union {
-    struct {
-        /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio41_mcu_oe:1;
-        /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio41_slp_sel:1;
-        /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio41_mcu_wpd:1;
-        /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio41_mcu_wpu:1;
-        /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio41_mcu_ie:1;
-        /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio41_mcu_drv:2;
-        /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio41_fun_wpd:1;
-        /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio41_fun_wpu:1;
-        /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio41_fun_ie:1;
-        /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio41_fun_drv:2;
-        /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio41_mcu_sel:3;
-        /** gpio41_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio41_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio41_reg_t;
-
-/** Type of gpio42 register
- *  iomux control register for gpio42
- */
-typedef union {
-    struct {
-        /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio42_mcu_oe:1;
-        /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio42_slp_sel:1;
-        /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio42_mcu_wpd:1;
-        /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio42_mcu_wpu:1;
-        /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio42_mcu_ie:1;
-        /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio42_mcu_drv:2;
-        /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio42_fun_wpd:1;
-        /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio42_fun_wpu:1;
-        /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio42_fun_ie:1;
-        /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio42_fun_drv:2;
-        /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio42_mcu_sel:3;
-        /** gpio42_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio42_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio42_reg_t;
-
-/** Type of gpio43 register
- *  iomux control register for gpio43
- */
-typedef union {
-    struct {
-        /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio43_mcu_oe:1;
-        /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio43_slp_sel:1;
-        /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio43_mcu_wpd:1;
-        /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio43_mcu_wpu:1;
-        /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio43_mcu_ie:1;
-        /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio43_mcu_drv:2;
-        /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio43_fun_wpd:1;
-        /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio43_fun_wpu:1;
-        /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio43_fun_ie:1;
-        /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio43_fun_drv:2;
-        /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio43_mcu_sel:3;
-        /** gpio43_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio43_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio43_reg_t;
-
-/** Type of gpio44 register
- *  iomux control register for gpio44
- */
-typedef union {
-    struct {
-        /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio44_mcu_oe:1;
-        /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio44_slp_sel:1;
-        /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio44_mcu_wpd:1;
-        /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio44_mcu_wpu:1;
-        /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio44_mcu_ie:1;
-        /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio44_mcu_drv:2;
-        /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio44_fun_wpd:1;
-        /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio44_fun_wpu:1;
-        /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio44_fun_ie:1;
-        /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio44_fun_drv:2;
-        /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio44_mcu_sel:3;
-        /** gpio44_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio44_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio44_reg_t;
-
-/** Type of gpio45 register
- *  iomux control register for gpio45
- */
-typedef union {
-    struct {
-        /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio45_mcu_oe:1;
-        /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio45_slp_sel:1;
-        /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio45_mcu_wpd:1;
-        /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio45_mcu_wpu:1;
-        /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio45_mcu_ie:1;
-        /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio45_mcu_drv:2;
-        /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio45_fun_wpd:1;
-        /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio45_fun_wpu:1;
-        /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio45_fun_ie:1;
-        /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio45_fun_drv:2;
-        /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio45_mcu_sel:3;
-        /** gpio45_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio45_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio45_reg_t;
-
-/** Type of gpio46 register
- *  iomux control register for gpio46
- */
-typedef union {
-    struct {
-        /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio46_mcu_oe:1;
-        /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio46_slp_sel:1;
-        /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio46_mcu_wpd:1;
-        /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio46_mcu_wpu:1;
-        /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio46_mcu_ie:1;
-        /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio46_mcu_drv:2;
-        /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio46_fun_wpd:1;
-        /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio46_fun_wpu:1;
-        /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio46_fun_ie:1;
-        /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio46_fun_drv:2;
-        /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio46_mcu_sel:3;
-        /** gpio46_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio46_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio46_reg_t;
-
-/** Type of gpio47 register
- *  iomux control register for gpio47
- */
-typedef union {
-    struct {
-        /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio47_mcu_oe:1;
-        /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio47_slp_sel:1;
-        /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio47_mcu_wpd:1;
-        /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio47_mcu_wpu:1;
-        /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio47_mcu_ie:1;
-        /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio47_mcu_drv:2;
-        /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio47_fun_wpd:1;
-        /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio47_fun_wpu:1;
-        /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio47_fun_ie:1;
-        /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio47_fun_drv:2;
-        /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio47_mcu_sel:3;
-        /** gpio47_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio47_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio47_reg_t;
-
-/** Type of gpio48 register
- *  iomux control register for gpio48
- */
-typedef union {
-    struct {
-        /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio48_mcu_oe:1;
-        /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio48_slp_sel:1;
-        /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio48_mcu_wpd:1;
-        /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio48_mcu_wpu:1;
-        /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio48_mcu_ie:1;
-        /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio48_mcu_drv:2;
-        /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio48_fun_wpd:1;
-        /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio48_fun_wpu:1;
-        /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio48_fun_ie:1;
-        /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio48_fun_drv:2;
-        /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio48_mcu_sel:3;
-        /** gpio48_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio48_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio48_reg_t;
-
-/** Type of gpio49 register
- *  iomux control register for gpio49
- */
-typedef union {
-    struct {
-        /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio49_mcu_oe:1;
-        /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio49_slp_sel:1;
-        /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio49_mcu_wpd:1;
-        /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio49_mcu_wpu:1;
-        /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio49_mcu_ie:1;
-        /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio49_mcu_drv:2;
-        /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio49_fun_wpd:1;
-        /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio49_fun_wpu:1;
-        /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio49_fun_ie:1;
-        /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio49_fun_drv:2;
-        /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio49_mcu_sel:3;
-        /** gpio49_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio49_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio49_reg_t;
-
-/** Type of gpio50 register
- *  iomux control register for gpio50
- */
-typedef union {
-    struct {
-        /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio50_mcu_oe:1;
-        /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio50_slp_sel:1;
-        /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio50_mcu_wpd:1;
-        /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio50_mcu_wpu:1;
-        /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio50_mcu_ie:1;
-        /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio50_mcu_drv:2;
-        /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio50_fun_wpd:1;
-        /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio50_fun_wpu:1;
-        /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio50_fun_ie:1;
-        /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio50_fun_drv:2;
-        /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio50_mcu_sel:3;
-        /** gpio50_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio50_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio50_reg_t;
-
-/** Type of gpio51 register
- *  iomux control register for gpio51
- */
-typedef union {
-    struct {
-        /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio51_mcu_oe:1;
-        /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio51_slp_sel:1;
-        /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio51_mcu_wpd:1;
-        /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio51_mcu_wpu:1;
-        /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio51_mcu_ie:1;
-        /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio51_mcu_drv:2;
-        /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio51_fun_wpd:1;
-        /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio51_fun_wpu:1;
-        /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio51_fun_ie:1;
-        /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio51_fun_drv:2;
-        /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio51_mcu_sel:3;
-        /** gpio51_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio51_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio51_reg_t;
-
-/** Type of gpio52 register
- *  iomux control register for gpio52
- */
-typedef union {
-    struct {
-        /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio52_mcu_oe:1;
-        /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio52_slp_sel:1;
-        /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio52_mcu_wpd:1;
-        /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio52_mcu_wpu:1;
-        /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio52_mcu_ie:1;
-        /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio52_mcu_drv:2;
-        /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio52_fun_wpd:1;
-        /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio52_fun_wpu:1;
-        /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio52_fun_ie:1;
-        /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio52_fun_drv:2;
-        /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio52_mcu_sel:3;
-        /** gpio52_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio52_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio52_reg_t;
-
-/** Type of gpio53 register
- *  iomux control register for gpio53
- */
-typedef union {
-    struct {
-        /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio53_mcu_oe:1;
-        /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio53_slp_sel:1;
-        /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio53_mcu_wpd:1;
-        /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio53_mcu_wpu:1;
-        /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio53_mcu_ie:1;
-        /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio53_mcu_drv:2;
-        /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio53_fun_wpd:1;
-        /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio53_fun_wpu:1;
-        /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio53_fun_ie:1;
-        /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio53_fun_drv:2;
-        /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio53_mcu_sel:3;
-        /** gpio53_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio53_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio53_reg_t;
-
-/** Type of gpio54 register
- *  iomux control register for gpio54
- */
-typedef union {
-    struct {
-        /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio54_mcu_oe:1;
-        /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio54_slp_sel:1;
-        /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio54_mcu_wpd:1;
-        /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio54_mcu_wpu:1;
-        /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio54_mcu_ie:1;
-        /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio54_mcu_drv:2;
-        /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio54_fun_wpd:1;
-        /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio54_fun_wpu:1;
-        /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio54_fun_ie:1;
-        /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio54_fun_drv:2;
-        /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio54_mcu_sel:3;
-        /** gpio54_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio54_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio54_reg_t;
-
-/** Type of gpio55 register
- *  iomux control register for gpio55
- */
-typedef union {
-    struct {
-        /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio55_mcu_oe:1;
-        /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio55_slp_sel:1;
-        /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio55_mcu_wpd:1;
-        /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio55_mcu_wpu:1;
-        /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio55_mcu_ie:1;
-        /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio55_mcu_drv:2;
-        /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio55_fun_wpd:1;
-        /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio55_fun_wpu:1;
-        /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio55_fun_ie:1;
-        /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio55_fun_drv:2;
-        /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio55_mcu_sel:3;
-        /** gpio55_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio55_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio55_reg_t;
-
-/** Type of gpio56 register
- *  iomux control register for gpio56
- */
-typedef union {
-    struct {
-        /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio56_mcu_oe:1;
-        /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio56_slp_sel:1;
-        /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio56_mcu_wpd:1;
-        /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio56_mcu_wpu:1;
-        /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio56_mcu_ie:1;
-        /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strenth on sleep mode
-         */
-        uint32_t gpio56_mcu_drv:2;
-        /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio56_fun_wpd:1;
-        /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio56_fun_wpu:1;
-        /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio56_fun_ie:1;
-        /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio56_fun_drv:2;
-        /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio56_mcu_sel:3;
-        /** gpio56_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio56_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio56_reg_t;
-
-/** Type of date register
- *  iomux version
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 2101794;
-         *  csv date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} io_mux_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000;
-    volatile io_mux_gpio0_reg_t gpio0;
-    volatile io_mux_gpio1_reg_t gpio1;
-    volatile io_mux_gpio2_reg_t gpio2;
-    volatile io_mux_gpio3_reg_t gpio3;
-    volatile io_mux_gpio4_reg_t gpio4;
-    volatile io_mux_gpio5_reg_t gpio5;
-    volatile io_mux_gpio6_reg_t gpio6;
-    volatile io_mux_gpio7_reg_t gpio7;
-    volatile io_mux_gpio8_reg_t gpio8;
-    volatile io_mux_gpio9_reg_t gpio9;
-    volatile io_mux_gpio10_reg_t gpio10;
-    volatile io_mux_gpio11_reg_t gpio11;
-    volatile io_mux_gpio12_reg_t gpio12;
-    volatile io_mux_gpio13_reg_t gpio13;
-    volatile io_mux_gpio14_reg_t gpio14;
-    volatile io_mux_gpio15_reg_t gpio15;
-    volatile io_mux_gpio16_reg_t gpio16;
-    volatile io_mux_gpio17_reg_t gpio17;
-    volatile io_mux_gpio18_reg_t gpio18;
-    volatile io_mux_gpio19_reg_t gpio19;
-    volatile io_mux_gpio20_reg_t gpio20;
-    volatile io_mux_gpio21_reg_t gpio21;
-    volatile io_mux_gpio22_reg_t gpio22;
-    volatile io_mux_gpio23_reg_t gpio23;
-    volatile io_mux_gpio24_reg_t gpio24;
-    volatile io_mux_gpio25_reg_t gpio25;
-    volatile io_mux_gpio26_reg_t gpio26;
-    volatile io_mux_gpio27_reg_t gpio27;
-    volatile io_mux_gpio28_reg_t gpio28;
-    volatile io_mux_gpio29_reg_t gpio29;
-    volatile io_mux_gpio30_reg_t gpio30;
-    volatile io_mux_gpio31_reg_t gpio31;
-    volatile io_mux_gpio32_reg_t gpio32;
-    volatile io_mux_gpio33_reg_t gpio33;
-    volatile io_mux_gpio34_reg_t gpio34;
-    volatile io_mux_gpio35_reg_t gpio35;
-    volatile io_mux_gpio36_reg_t gpio36;
-    volatile io_mux_gpio37_reg_t gpio37;
-    volatile io_mux_gpio38_reg_t gpio38;
-    volatile io_mux_gpio39_reg_t gpio39;
-    volatile io_mux_gpio40_reg_t gpio40;
-    volatile io_mux_gpio41_reg_t gpio41;
-    volatile io_mux_gpio42_reg_t gpio42;
-    volatile io_mux_gpio43_reg_t gpio43;
-    volatile io_mux_gpio44_reg_t gpio44;
-    volatile io_mux_gpio45_reg_t gpio45;
-    volatile io_mux_gpio46_reg_t gpio46;
-    volatile io_mux_gpio47_reg_t gpio47;
-    volatile io_mux_gpio48_reg_t gpio48;
-    volatile io_mux_gpio49_reg_t gpio49;
-    volatile io_mux_gpio50_reg_t gpio50;
-    volatile io_mux_gpio51_reg_t gpio51;
-    volatile io_mux_gpio52_reg_t gpio52;
-    volatile io_mux_gpio53_reg_t gpio53;
-    volatile io_mux_gpio54_reg_t gpio54;
-    volatile io_mux_gpio55_reg_t gpio55;
-    volatile io_mux_gpio56_reg_t gpio56;
-    uint32_t reserved_0e8[7];
-    volatile io_mux_date_reg_t date;
-} io_mux_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lcd_cam_reg.h b/components/soc/esp32p4/include/soc/lcd_cam_reg.h
index 715dc51396..7a2f8ed19a 100644
--- a/components/soc/esp32p4/include/soc/lcd_cam_reg.h
+++ b/components/soc/esp32p4/include/soc/lcd_cam_reg.h
@@ -1,962 +1,1145 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_LCD_CAM_REG_H_
-#define _SOC_LCD_CAM_REG_H_
-
+#pragma once
 
+#include <stdint.h>
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
-#define LCD_CAM_LCD_CLOCK_REG          (DR_REG_LCD_CAM_BASE + 0x0)
-/* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit to enable clk gate.*/
-#define LCD_CAM_CLK_EN    (BIT(31))
-#define LCD_CAM_CLK_EN_M  (BIT(31))
-#define LCD_CAM_CLK_EN_V  0x1
-#define LCD_CAM_CLK_EN_S  31
-/* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
-/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
-#define LCD_CAM_LCD_CLK_SEL    0x00000003
-#define LCD_CAM_LCD_CLK_SEL_M  ((LCD_CAM_LCD_CLK_SEL_V)<<(LCD_CAM_LCD_CLK_SEL_S))
-#define LCD_CAM_LCD_CLK_SEL_V  0x3
-#define LCD_CAM_LCD_CLK_SEL_S  29
-/* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
-/*description: Fractional clock divider denominator value.*/
-#define LCD_CAM_LCD_CLKM_DIV_A    0x0000003F
-#define LCD_CAM_LCD_CLKM_DIV_A_M  ((LCD_CAM_LCD_CLKM_DIV_A_V)<<(LCD_CAM_LCD_CLKM_DIV_A_S))
-#define LCD_CAM_LCD_CLKM_DIV_A_V  0x3F
-#define LCD_CAM_LCD_CLKM_DIV_A_S  23
-/* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
-/*description: Fractional clock divider numerator value.*/
-#define LCD_CAM_LCD_CLKM_DIV_B    0x0000003F
-#define LCD_CAM_LCD_CLKM_DIV_B_M  ((LCD_CAM_LCD_CLKM_DIV_B_V)<<(LCD_CAM_LCD_CLKM_DIV_B_S))
-#define LCD_CAM_LCD_CLKM_DIV_B_V  0x3F
-#define LCD_CAM_LCD_CLKM_DIV_B_S  17
-/* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
-/*description: Integral LCD clock divider value.*/
-#define LCD_CAM_LCD_CLKM_DIV_NUM    0x000000FF
-#define LCD_CAM_LCD_CLKM_DIV_NUM_M  ((LCD_CAM_LCD_CLKM_DIV_NUM_V)<<(LCD_CAM_LCD_CLKM_DIV_NUM_S))
-#define LCD_CAM_LCD_CLKM_DIV_NUM_V  0xFF
-#define LCD_CAM_LCD_CLKM_DIV_NUM_S  9
-/* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: 1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is l
-ow in the second half data cycle..*/
-#define LCD_CAM_LCD_CK_OUT_EDGE    (BIT(8))
-#define LCD_CAM_LCD_CK_OUT_EDGE_M  (BIT(8))
-#define LCD_CAM_LCD_CK_OUT_EDGE_V  0x1
-#define LCD_CAM_LCD_CK_OUT_EDGE_S  8
-/* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle..*/
-#define LCD_CAM_LCD_CK_IDLE_EDGE    (BIT(7))
-#define LCD_CAM_LCD_CK_IDLE_EDGE_M  (BIT(7))
-#define LCD_CAM_LCD_CK_IDLE_EDGE_V  0x1
-#define LCD_CAM_LCD_CK_IDLE_EDGE_S  7
-/* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */
-/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)..*/
-#define LCD_CAM_LCD_CLK_EQU_SYSCLK    (BIT(6))
-#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M  (BIT(6))
-#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V  0x1
-#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S  6
-/* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
-/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0..*/
-#define LCD_CAM_LCD_CLKCNT_N    0x0000003F
-#define LCD_CAM_LCD_CLKCNT_N_M  ((LCD_CAM_LCD_CLKCNT_N_V)<<(LCD_CAM_LCD_CLKCNT_N_S))
-#define LCD_CAM_LCD_CLKCNT_N_V  0x3F
-#define LCD_CAM_LCD_CLKCNT_N_S  0
+/** LCDCAM_LCD_CLOCK_REG register
+ *  LCD clock config register.
+ */
+#define LCDCAM_LCD_CLOCK_REG (DR_REG_LCDCAM_BASE + 0x0)
+/** LCDCAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3;
+ *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+ */
+#define LCDCAM_LCD_CLKCNT_N    0x0000003FU
+#define LCDCAM_LCD_CLKCNT_N_M  (LCDCAM_LCD_CLKCNT_N_V << LCDCAM_LCD_CLKCNT_N_S)
+#define LCDCAM_LCD_CLKCNT_N_V  0x0000003FU
+#define LCDCAM_LCD_CLKCNT_N_S  0
+/** LCDCAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1;
+ *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+ */
+#define LCDCAM_LCD_CLK_EQU_SYSCLK    (BIT(6))
+#define LCDCAM_LCD_CLK_EQU_SYSCLK_M  (LCDCAM_LCD_CLK_EQU_SYSCLK_V << LCDCAM_LCD_CLK_EQU_SYSCLK_S)
+#define LCDCAM_LCD_CLK_EQU_SYSCLK_V  0x00000001U
+#define LCDCAM_LCD_CLK_EQU_SYSCLK_S  6
+/** LCDCAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0;
+ *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+ */
+#define LCDCAM_LCD_CK_IDLE_EDGE    (BIT(7))
+#define LCDCAM_LCD_CK_IDLE_EDGE_M  (LCDCAM_LCD_CK_IDLE_EDGE_V << LCDCAM_LCD_CK_IDLE_EDGE_S)
+#define LCDCAM_LCD_CK_IDLE_EDGE_V  0x00000001U
+#define LCDCAM_LCD_CK_IDLE_EDGE_S  7
+/** LCDCAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0;
+ *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
+ *  in the second half data cycle.
+ */
+#define LCDCAM_LCD_CK_OUT_EDGE    (BIT(8))
+#define LCDCAM_LCD_CK_OUT_EDGE_M  (LCDCAM_LCD_CK_OUT_EDGE_V << LCDCAM_LCD_CK_OUT_EDGE_S)
+#define LCDCAM_LCD_CK_OUT_EDGE_V  0x00000001U
+#define LCDCAM_LCD_CK_OUT_EDGE_S  8
+/** LCDCAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
+ *  Integral LCD clock divider value
+ */
+#define LCDCAM_LCD_CLKM_DIV_NUM    0x000000FFU
+#define LCDCAM_LCD_CLKM_DIV_NUM_M  (LCDCAM_LCD_CLKM_DIV_NUM_V << LCDCAM_LCD_CLKM_DIV_NUM_S)
+#define LCDCAM_LCD_CLKM_DIV_NUM_V  0x000000FFU
+#define LCDCAM_LCD_CLKM_DIV_NUM_S  9
+/** LCDCAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
+ *  Fractional clock divider numerator value
+ */
+#define LCDCAM_LCD_CLKM_DIV_B    0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_B_M  (LCDCAM_LCD_CLKM_DIV_B_V << LCDCAM_LCD_CLKM_DIV_B_S)
+#define LCDCAM_LCD_CLKM_DIV_B_V  0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_B_S  17
+/** LCDCAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
+ *  Fractional clock divider denominator value
+ */
+#define LCDCAM_LCD_CLKM_DIV_A    0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_A_M  (LCDCAM_LCD_CLKM_DIV_A_V << LCDCAM_LCD_CLKM_DIV_A_S)
+#define LCDCAM_LCD_CLKM_DIV_A_V  0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_A_S  23
+/** LCDCAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+ */
+#define LCDCAM_LCD_CLK_SEL    0x00000003U
+#define LCDCAM_LCD_CLK_SEL_M  (LCDCAM_LCD_CLK_SEL_V << LCDCAM_LCD_CLK_SEL_S)
+#define LCDCAM_LCD_CLK_SEL_V  0x00000003U
+#define LCDCAM_LCD_CLK_SEL_S  29
+/** LCDCAM_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define LCDCAM_CLK_EN    (BIT(31))
+#define LCDCAM_CLK_EN_M  (LCDCAM_CLK_EN_V << LCDCAM_CLK_EN_S)
+#define LCDCAM_CLK_EN_V  0x00000001U
+#define LCDCAM_CLK_EN_S  31
 
-#define LCD_CAM_CAM_CTRL_REG          (DR_REG_LCD_CAM_BASE + 0x4)
-/* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
-/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
-#define LCD_CAM_CAM_CLK_SEL    0x00000003
-#define LCD_CAM_CAM_CLK_SEL_M  ((LCD_CAM_CAM_CLK_SEL_V)<<(LCD_CAM_CAM_CLK_SEL_S))
-#define LCD_CAM_CAM_CLK_SEL_V  0x3
-#define LCD_CAM_CAM_CLK_SEL_S  29
-/* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
-/*description: Fractional clock divider denominator value.*/
-#define LCD_CAM_CAM_CLKM_DIV_A    0x0000003F
-#define LCD_CAM_CAM_CLKM_DIV_A_M  ((LCD_CAM_CAM_CLKM_DIV_A_V)<<(LCD_CAM_CAM_CLKM_DIV_A_S))
-#define LCD_CAM_CAM_CLKM_DIV_A_V  0x3F
-#define LCD_CAM_CAM_CLKM_DIV_A_S  23
-/* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
-/*description: Fractional clock divider numerator value.*/
-#define LCD_CAM_CAM_CLKM_DIV_B    0x0000003F
-#define LCD_CAM_CAM_CLKM_DIV_B_M  ((LCD_CAM_CAM_CLKM_DIV_B_V)<<(LCD_CAM_CAM_CLKM_DIV_B_S))
-#define LCD_CAM_CAM_CLKM_DIV_B_V  0x3F
-#define LCD_CAM_CAM_CLKM_DIV_B_S  17
-/* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
-/*description: Integral Camera clock divider value.*/
-#define LCD_CAM_CAM_CLKM_DIV_NUM    0x000000FF
-#define LCD_CAM_CAM_CLKM_DIV_NUM_M  ((LCD_CAM_CAM_CLKM_DIV_NUM_V)<<(LCD_CAM_CAM_CLKM_DIV_NUM_S))
-#define LCD_CAM_CAM_CLKM_DIV_NUM_V  0xFF
-#define LCD_CAM_CAM_CLKM_DIV_NUM_S  9
-/* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_
-data_cyclelen..*/
-#define LCD_CAM_CAM_VS_EOF_EN    (BIT(8))
-#define LCD_CAM_CAM_VS_EOF_EN_M  (BIT(8))
-#define LCD_CAM_CAM_VS_EOF_EN_V  0x1
-#define LCD_CAM_CAM_VS_EOF_EN_S  8
-/* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: 1: Enable to generate CAM_HS_INT. 0: Disable..*/
-#define LCD_CAM_CAM_LINE_INT_EN    (BIT(7))
-#define LCD_CAM_CAM_LINE_INT_EN_M  (BIT(7))
-#define LCD_CAM_CAM_LINE_INT_EN_V  0x1
-#define LCD_CAM_CAM_LINE_INT_EN_S  7
-/* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
-#define LCD_CAM_CAM_BIT_ORDER    (BIT(6))
-#define LCD_CAM_CAM_BIT_ORDER_M  (BIT(6))
-#define LCD_CAM_CAM_BIT_ORDER_V  0x1
-#define LCD_CAM_CAM_BIT_ORDER_S  6
-/* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byt
-e mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change..*/
-#define LCD_CAM_CAM_BYTE_ORDER    (BIT(5))
-#define LCD_CAM_CAM_BYTE_ORDER_M  (BIT(5))
-#define LCD_CAM_CAM_BYTE_ORDER_V  0x1
-#define LCD_CAM_CAM_BYTE_ORDER_S  5
-/* LCD_CAM_CAM_UPDATE_REG : R/W/SC ;bitpos:[4] ;default: 1'h0 ; */
-/*description: 1: Update Camera registers, will be cleared by hardware. 0 : Not care..*/
-#define LCD_CAM_CAM_UPDATE_REG    (BIT(4))
-#define LCD_CAM_CAM_UPDATE_REG_M  (BIT(4))
-#define LCD_CAM_CAM_UPDATE_REG_V  0x1
-#define LCD_CAM_CAM_UPDATE_REG_S  4
-/* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */
-/*description: Filter threshold value for CAM_VSYNC signal..*/
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES    0x00000007
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M  ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V)<<(LCD_CAM_CAM_VSYNC_FILTER_THRES_S))
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V  0x7
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S  1
-/* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop
-..*/
-#define LCD_CAM_CAM_STOP_EN    (BIT(0))
-#define LCD_CAM_CAM_STOP_EN_M  (BIT(0))
-#define LCD_CAM_CAM_STOP_EN_V  0x1
-#define LCD_CAM_CAM_STOP_EN_S  0
+/** LCDCAM_CAM_CTRL_REG register
+ *  CAM config register.
+ */
+#define LCDCAM_CAM_CTRL_REG (DR_REG_LCDCAM_BASE + 0x4)
+/** LCDCAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+ */
+#define LCDCAM_CAM_STOP_EN    (BIT(0))
+#define LCDCAM_CAM_STOP_EN_M  (LCDCAM_CAM_STOP_EN_V << LCDCAM_CAM_STOP_EN_S)
+#define LCDCAM_CAM_STOP_EN_V  0x00000001U
+#define LCDCAM_CAM_STOP_EN_S  0
+/** LCDCAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0;
+ *  Filter threshold value for CAM_VSYNC signal.
+ */
+#define LCDCAM_CAM_VSYNC_FILTER_THRES    0x00000007U
+#define LCDCAM_CAM_VSYNC_FILTER_THRES_M  (LCDCAM_CAM_VSYNC_FILTER_THRES_V << LCDCAM_CAM_VSYNC_FILTER_THRES_S)
+#define LCDCAM_CAM_VSYNC_FILTER_THRES_V  0x00000007U
+#define LCDCAM_CAM_VSYNC_FILTER_THRES_S  1
+/** LCDCAM_CAM_UPDATE_REG : R/W/SC; bitpos: [4]; default: 0;
+ *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+ */
+#define LCDCAM_CAM_UPDATE_REG    (BIT(4))
+#define LCDCAM_CAM_UPDATE_REG_M  (LCDCAM_CAM_UPDATE_REG_V << LCDCAM_CAM_UPDATE_REG_S)
+#define LCDCAM_CAM_UPDATE_REG_V  0x00000001U
+#define LCDCAM_CAM_UPDATE_REG_S  4
+/** LCDCAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0;
+ *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+ *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+ */
+#define LCDCAM_CAM_BYTE_ORDER    (BIT(5))
+#define LCDCAM_CAM_BYTE_ORDER_M  (LCDCAM_CAM_BYTE_ORDER_V << LCDCAM_CAM_BYTE_ORDER_S)
+#define LCDCAM_CAM_BYTE_ORDER_V  0x00000001U
+#define LCDCAM_CAM_BYTE_ORDER_S  5
+/** LCDCAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0;
+ *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+ */
+#define LCDCAM_CAM_BIT_ORDER    (BIT(6))
+#define LCDCAM_CAM_BIT_ORDER_M  (LCDCAM_CAM_BIT_ORDER_V << LCDCAM_CAM_BIT_ORDER_S)
+#define LCDCAM_CAM_BIT_ORDER_V  0x00000001U
+#define LCDCAM_CAM_BIT_ORDER_S  6
+/** LCDCAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0;
+ *  1: Enable to generate CAM_HS_INT. 0: Disable.
+ */
+#define LCDCAM_CAM_LINE_INT_EN    (BIT(7))
+#define LCDCAM_CAM_LINE_INT_EN_M  (LCDCAM_CAM_LINE_INT_EN_V << LCDCAM_CAM_LINE_INT_EN_S)
+#define LCDCAM_CAM_LINE_INT_EN_V  0x00000001U
+#define LCDCAM_CAM_LINE_INT_EN_S  7
+/** LCDCAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0;
+ *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+ *  reg_cam_rec_data_cyclelen.
+ */
+#define LCDCAM_CAM_VS_EOF_EN    (BIT(8))
+#define LCDCAM_CAM_VS_EOF_EN_M  (LCDCAM_CAM_VS_EOF_EN_V << LCDCAM_CAM_VS_EOF_EN_S)
+#define LCDCAM_CAM_VS_EOF_EN_V  0x00000001U
+#define LCDCAM_CAM_VS_EOF_EN_S  8
+/** LCDCAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
+ *  Integral Camera clock divider value
+ */
+#define LCDCAM_CAM_CLKM_DIV_NUM    0x000000FFU
+#define LCDCAM_CAM_CLKM_DIV_NUM_M  (LCDCAM_CAM_CLKM_DIV_NUM_V << LCDCAM_CAM_CLKM_DIV_NUM_S)
+#define LCDCAM_CAM_CLKM_DIV_NUM_V  0x000000FFU
+#define LCDCAM_CAM_CLKM_DIV_NUM_S  9
+/** LCDCAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
+ *  Fractional clock divider numerator value
+ */
+#define LCDCAM_CAM_CLKM_DIV_B    0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_B_M  (LCDCAM_CAM_CLKM_DIV_B_V << LCDCAM_CAM_CLKM_DIV_B_S)
+#define LCDCAM_CAM_CLKM_DIV_B_V  0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_B_S  17
+/** LCDCAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
+ *  Fractional clock divider denominator value
+ */
+#define LCDCAM_CAM_CLKM_DIV_A    0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_A_M  (LCDCAM_CAM_CLKM_DIV_A_V << LCDCAM_CAM_CLKM_DIV_A_S)
+#define LCDCAM_CAM_CLKM_DIV_A_V  0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_A_S  23
+/** LCDCAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+ */
+#define LCDCAM_CAM_CLK_SEL    0x00000003U
+#define LCDCAM_CAM_CLK_SEL_M  (LCDCAM_CAM_CLK_SEL_V << LCDCAM_CAM_CLK_SEL_S)
+#define LCDCAM_CAM_CLK_SEL_V  0x00000003U
+#define LCDCAM_CAM_CLK_SEL_S  29
 
-#define LCD_CAM_CAM_CTRL1_REG          (DR_REG_LCD_CAM_BASE + 0x8)
-/* LCD_CAM_CAM_AFIFO_RESET : WT ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Camera AFIFO reset signal..*/
-#define LCD_CAM_CAM_AFIFO_RESET    (BIT(31))
-#define LCD_CAM_CAM_AFIFO_RESET_M  (BIT(31))
-#define LCD_CAM_CAM_AFIFO_RESET_V  0x1
-#define LCD_CAM_CAM_AFIFO_RESET_S  31
-/* LCD_CAM_CAM_RESET : WT ;bitpos:[30] ;default: 1'h0 ; */
-/*description: Camera module reset signal..*/
-#define LCD_CAM_CAM_RESET    (BIT(30))
-#define LCD_CAM_CAM_RESET_M  (BIT(30))
-#define LCD_CAM_CAM_RESET_V  0x1
-#define LCD_CAM_CAM_RESET_S  30
-/* LCD_CAM_CAM_START : R/W/SC ;bitpos:[29] ;default: 1'h0 ; */
-/*description: Camera module start signal..*/
-#define LCD_CAM_CAM_START    (BIT(29))
-#define LCD_CAM_CAM_START_M  (BIT(29))
-#define LCD_CAM_CAM_START_V  0x1
-#define LCD_CAM_CAM_START_S  29
-/* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
-/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control si
-gnals are CAM_DE and CAM_VSYNC..*/
-#define LCD_CAM_CAM_VH_DE_MODE_EN    (BIT(28))
-#define LCD_CAM_CAM_VH_DE_MODE_EN_M  (BIT(28))
-#define LCD_CAM_CAM_VH_DE_MODE_EN_V  0x1
-#define LCD_CAM_CAM_VH_DE_MODE_EN_S  28
-/* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */
-/*description: CAM_VSYNC invert enable signal, valid in high level..*/
-#define LCD_CAM_CAM_VSYNC_INV    (BIT(27))
-#define LCD_CAM_CAM_VSYNC_INV_M  (BIT(27))
-#define LCD_CAM_CAM_VSYNC_INV_V  0x1
-#define LCD_CAM_CAM_VSYNC_INV_S  27
-/* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: CAM_HSYNC invert enable signal, valid in high level..*/
-#define LCD_CAM_CAM_HSYNC_INV    (BIT(26))
-#define LCD_CAM_CAM_HSYNC_INV_M  (BIT(26))
-#define LCD_CAM_CAM_HSYNC_INV_V  0x1
-#define LCD_CAM_CAM_HSYNC_INV_S  26
-/* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: CAM_DE invert enable signal, valid in high level..*/
-#define LCD_CAM_CAM_DE_INV    (BIT(25))
-#define LCD_CAM_CAM_DE_INV_M  (BIT(25))
-#define LCD_CAM_CAM_DE_INV_V  0x1
-#define LCD_CAM_CAM_DE_INV_S  25
-/* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: 1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8
-..*/
-#define LCD_CAM_CAM_2BYTE_EN    (BIT(24))
-#define LCD_CAM_CAM_2BYTE_EN_M  (BIT(24))
-#define LCD_CAM_CAM_2BYTE_EN_V  0x1
-#define LCD_CAM_CAM_2BYTE_EN_S  24
-/* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: 1: Enable CAM_VSYNC filter function. 0: bypass..*/
-#define LCD_CAM_CAM_VSYNC_FILTER_EN    (BIT(23))
-#define LCD_CAM_CAM_VSYNC_FILTER_EN_M  (BIT(23))
-#define LCD_CAM_CAM_VSYNC_FILTER_EN_V  0x1
-#define LCD_CAM_CAM_VSYNC_FILTER_EN_S  23
-/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: Invert  the input signal CAM_PCLK. 0: Not invert..*/
-#define LCD_CAM_CAM_CLK_INV    (BIT(22))
-#define LCD_CAM_CAM_CLK_INV_M  (BIT(22))
-#define LCD_CAM_CAM_CLK_INV_V  0x1
-#define LCD_CAM_CAM_CLK_INV_S  22
-/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[21:16] ;default: 6'h0 ; */
-/*description: The line number minus 1 to generate cam_hs_int..*/
-#define LCD_CAM_CAM_LINE_INT_NUM    0x0000003F
-#define LCD_CAM_CAM_LINE_INT_NUM_M  ((LCD_CAM_CAM_LINE_INT_NUM_V)<<(LCD_CAM_CAM_LINE_INT_NUM_S))
-#define LCD_CAM_CAM_LINE_INT_NUM_V  0x3F
-#define LCD_CAM_CAM_LINE_INT_NUM_S  16
-/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int..*/
-#define LCD_CAM_CAM_REC_DATA_BYTELEN    0x0000FFFF
-#define LCD_CAM_CAM_REC_DATA_BYTELEN_M  ((LCD_CAM_CAM_REC_DATA_BYTELEN_V)<<(LCD_CAM_CAM_REC_DATA_BYTELEN_S))
-#define LCD_CAM_CAM_REC_DATA_BYTELEN_V  0xFFFF
-#define LCD_CAM_CAM_REC_DATA_BYTELEN_S  0
+/** LCDCAM_CAM_CTRL1_REG register
+ *  CAM config register.
+ */
+#define LCDCAM_CAM_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x8)
+/** LCDCAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0;
+ *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+ */
+#define LCDCAM_CAM_REC_DATA_BYTELEN    0x0000FFFFU
+#define LCDCAM_CAM_REC_DATA_BYTELEN_M  (LCDCAM_CAM_REC_DATA_BYTELEN_V << LCDCAM_CAM_REC_DATA_BYTELEN_S)
+#define LCDCAM_CAM_REC_DATA_BYTELEN_V  0x0000FFFFU
+#define LCDCAM_CAM_REC_DATA_BYTELEN_S  0
+/** LCDCAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0;
+ *  The line number minus 1 to generate cam_hs_int.
+ */
+#define LCDCAM_CAM_LINE_INT_NUM    0x0000003FU
+#define LCDCAM_CAM_LINE_INT_NUM_M  (LCDCAM_CAM_LINE_INT_NUM_V << LCDCAM_CAM_LINE_INT_NUM_S)
+#define LCDCAM_CAM_LINE_INT_NUM_V  0x0000003FU
+#define LCDCAM_CAM_LINE_INT_NUM_S  16
+/** LCDCAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0;
+ *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+ */
+#define LCDCAM_CAM_CLK_INV    (BIT(22))
+#define LCDCAM_CAM_CLK_INV_M  (LCDCAM_CAM_CLK_INV_V << LCDCAM_CAM_CLK_INV_S)
+#define LCDCAM_CAM_CLK_INV_V  0x00000001U
+#define LCDCAM_CAM_CLK_INV_S  22
+/** LCDCAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0;
+ *  1: Enable CAM_VSYNC filter function. 0: bypass.
+ */
+#define LCDCAM_CAM_VSYNC_FILTER_EN    (BIT(23))
+#define LCDCAM_CAM_VSYNC_FILTER_EN_M  (LCDCAM_CAM_VSYNC_FILTER_EN_V << LCDCAM_CAM_VSYNC_FILTER_EN_S)
+#define LCDCAM_CAM_VSYNC_FILTER_EN_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_FILTER_EN_S  23
+/** LCDCAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0;
+ *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+ */
+#define LCDCAM_CAM_2BYTE_EN    (BIT(24))
+#define LCDCAM_CAM_2BYTE_EN_M  (LCDCAM_CAM_2BYTE_EN_V << LCDCAM_CAM_2BYTE_EN_S)
+#define LCDCAM_CAM_2BYTE_EN_V  0x00000001U
+#define LCDCAM_CAM_2BYTE_EN_S  24
+/** LCDCAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0;
+ *  CAM_DE invert enable signal, valid in high level.
+ */
+#define LCDCAM_CAM_DE_INV    (BIT(25))
+#define LCDCAM_CAM_DE_INV_M  (LCDCAM_CAM_DE_INV_V << LCDCAM_CAM_DE_INV_S)
+#define LCDCAM_CAM_DE_INV_V  0x00000001U
+#define LCDCAM_CAM_DE_INV_S  25
+/** LCDCAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0;
+ *  CAM_HSYNC invert enable signal, valid in high level.
+ */
+#define LCDCAM_CAM_HSYNC_INV    (BIT(26))
+#define LCDCAM_CAM_HSYNC_INV_M  (LCDCAM_CAM_HSYNC_INV_V << LCDCAM_CAM_HSYNC_INV_S)
+#define LCDCAM_CAM_HSYNC_INV_V  0x00000001U
+#define LCDCAM_CAM_HSYNC_INV_S  26
+/** LCDCAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0;
+ *  CAM_VSYNC invert enable signal, valid in high level.
+ */
+#define LCDCAM_CAM_VSYNC_INV    (BIT(27))
+#define LCDCAM_CAM_VSYNC_INV_M  (LCDCAM_CAM_VSYNC_INV_V << LCDCAM_CAM_VSYNC_INV_S)
+#define LCDCAM_CAM_VSYNC_INV_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INV_S  27
+/** LCDCAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0;
+ *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
+ *  signals are CAM_DE and CAM_VSYNC.
+ */
+#define LCDCAM_CAM_VH_DE_MODE_EN    (BIT(28))
+#define LCDCAM_CAM_VH_DE_MODE_EN_M  (LCDCAM_CAM_VH_DE_MODE_EN_V << LCDCAM_CAM_VH_DE_MODE_EN_S)
+#define LCDCAM_CAM_VH_DE_MODE_EN_V  0x00000001U
+#define LCDCAM_CAM_VH_DE_MODE_EN_S  28
+/** LCDCAM_CAM_START : R/W/SC; bitpos: [29]; default: 0;
+ *  Camera module start signal.
+ */
+#define LCDCAM_CAM_START    (BIT(29))
+#define LCDCAM_CAM_START_M  (LCDCAM_CAM_START_V << LCDCAM_CAM_START_S)
+#define LCDCAM_CAM_START_V  0x00000001U
+#define LCDCAM_CAM_START_S  29
+/** LCDCAM_CAM_RESET : WT; bitpos: [30]; default: 0;
+ *  Camera module reset signal.
+ */
+#define LCDCAM_CAM_RESET    (BIT(30))
+#define LCDCAM_CAM_RESET_M  (LCDCAM_CAM_RESET_V << LCDCAM_CAM_RESET_S)
+#define LCDCAM_CAM_RESET_V  0x00000001U
+#define LCDCAM_CAM_RESET_S  30
+/** LCDCAM_CAM_AFIFO_RESET : WT; bitpos: [31]; default: 0;
+ *  Camera AFIFO reset signal.
+ */
+#define LCDCAM_CAM_AFIFO_RESET    (BIT(31))
+#define LCDCAM_CAM_AFIFO_RESET_M  (LCDCAM_CAM_AFIFO_RESET_V << LCDCAM_CAM_AFIFO_RESET_S)
+#define LCDCAM_CAM_AFIFO_RESET_V  0x00000001U
+#define LCDCAM_CAM_AFIFO_RESET_S  31
 
-#define LCD_CAM_CAM_RGB_YUV_REG          (DR_REG_LCD_CAM_BASE + 0xC)
-/* LCD_CAM_CAM_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 0: Bypass converter. 1: Enable converter..*/
-#define LCD_CAM_CAM_CONV_ENABLE    (BIT(31))
-#define LCD_CAM_CAM_CONV_ENABLE_M  (BIT(31))
-#define LCD_CAM_CAM_CONV_ENABLE_V  0x1
-#define LCD_CAM_CAM_CONV_ENABLE_S  31
-/* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: YUV to RGB. 1: RGB to YUV..*/
-#define LCD_CAM_CAM_CONV_TRANS_MODE    (BIT(30))
-#define LCD_CAM_CAM_CONV_TRANS_MODE_M  (BIT(30))
-#define LCD_CAM_CAM_CONV_TRANS_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_TRANS_MODE_S  30
-/* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 0: 16bits mode. 1: 8bits mode..*/
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON    (BIT(29))
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M  (BIT(29))
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V  0x1
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S  29
-/* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE    (BIT(28))
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M  (BIT(28))
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S  28
-/* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE    (BIT(27))
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M  (BIT(27))
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S  27
-/* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 0:BT601. 1:BT709..*/
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE    (BIT(26))
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M  (BIT(26))
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S  26
-/* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
-/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-mode of Data_in.*/
-#define LCD_CAM_CAM_CONV_YUV_MODE    0x00000003
-#define LCD_CAM_CAM_CONV_YUV_MODE_M  ((LCD_CAM_CAM_CONV_YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV_MODE_S))
-#define LCD_CAM_CAM_CONV_YUV_MODE_V  0x3
-#define LCD_CAM_CAM_CONV_YUV_MODE_S  24
-/* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
-/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-trans_mode must be set to 1..*/
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE    0x00000003
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M  ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV2YUV_MODE_S))
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V  0x3
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S  22
-/* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1:invert every two 8bits input data. 2. disabled..*/
-#define LCD_CAM_CAM_CONV_8BITS_DATA_INV    (BIT(21))
-#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M  (BIT(21))
-#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V  0x1
-#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S  21
+/** LCDCAM_CAM_RGB_YUV_REG register
+ *  CAM YUV/RGB converter configuration register.
+ */
+#define LCDCAM_CAM_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0xc)
+/** LCDCAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0;
+ *  1:invert every two 8bits input data. 2. disabled.
+ */
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV    (BIT(21))
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV_M  (LCDCAM_CAM_CONV_8BITS_DATA_INV_V << LCDCAM_CAM_CONV_8BITS_DATA_INV_S)
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV_V  0x00000001U
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV_S  21
+/** LCDCAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
+ *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+ *  trans_mode must be set to 1.
+ */
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE    0x00000003U
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE_M  (LCDCAM_CAM_CONV_YUV2YUV_MODE_V << LCDCAM_CAM_CONV_YUV2YUV_MODE_S)
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE_V  0x00000003U
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE_S  22
+/** LCDCAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+ *  mode of Data_in
+ */
+#define LCDCAM_CAM_CONV_YUV_MODE    0x00000003U
+#define LCDCAM_CAM_CONV_YUV_MODE_M  (LCDCAM_CAM_CONV_YUV_MODE_V << LCDCAM_CAM_CONV_YUV_MODE_S)
+#define LCDCAM_CAM_CONV_YUV_MODE_V  0x00000003U
+#define LCDCAM_CAM_CONV_YUV_MODE_S  24
+/** LCDCAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
+ *  0:BT601. 1:BT709.
+ */
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE_M  (LCDCAM_CAM_CONV_PROTOCOL_MODE_V << LCDCAM_CAM_CONV_PROTOCOL_MODE_S)
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE_S  26
+/** LCDCAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
+ *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+ */
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE_M  (LCDCAM_CAM_CONV_DATA_OUT_MODE_V << LCDCAM_CAM_CONV_DATA_OUT_MODE_S)
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE_S  27
+/** LCDCAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
+ *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+ */
+#define LCDCAM_CAM_CONV_DATA_IN_MODE    (BIT(28))
+#define LCDCAM_CAM_CONV_DATA_IN_MODE_M  (LCDCAM_CAM_CONV_DATA_IN_MODE_V << LCDCAM_CAM_CONV_DATA_IN_MODE_S)
+#define LCDCAM_CAM_CONV_DATA_IN_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_DATA_IN_MODE_S  28
+/** LCDCAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
+ *  0: 16bits mode. 1: 8bits mode.
+ */
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON_M  (LCDCAM_CAM_CONV_MODE_8BITS_ON_V << LCDCAM_CAM_CONV_MODE_8BITS_ON_S)
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON_V  0x00000001U
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON_S  29
+/** LCDCAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
+ *  0: YUV to RGB. 1: RGB to YUV.
+ */
+#define LCDCAM_CAM_CONV_TRANS_MODE    (BIT(30))
+#define LCDCAM_CAM_CONV_TRANS_MODE_M  (LCDCAM_CAM_CONV_TRANS_MODE_V << LCDCAM_CAM_CONV_TRANS_MODE_S)
+#define LCDCAM_CAM_CONV_TRANS_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_TRANS_MODE_S  30
+/** LCDCAM_CAM_CONV_ENABLE : R/W; bitpos: [31]; default: 0;
+ *  0: Bypass converter. 1: Enable converter.
+ */
+#define LCDCAM_CAM_CONV_ENABLE    (BIT(31))
+#define LCDCAM_CAM_CONV_ENABLE_M  (LCDCAM_CAM_CONV_ENABLE_V << LCDCAM_CAM_CONV_ENABLE_S)
+#define LCDCAM_CAM_CONV_ENABLE_V  0x00000001U
+#define LCDCAM_CAM_CONV_ENABLE_S  31
 
-#define LCD_CAM_LCD_RGB_YUV_REG          (DR_REG_LCD_CAM_BASE + 0x10)
-/* LCD_CAM_LCD_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 0: Bypass converter. 1: Enable converter..*/
-#define LCD_CAM_LCD_CONV_ENABLE    (BIT(31))
-#define LCD_CAM_LCD_CONV_ENABLE_M  (BIT(31))
-#define LCD_CAM_LCD_CONV_ENABLE_V  0x1
-#define LCD_CAM_LCD_CONV_ENABLE_S  31
-/* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: YUV to RGB. 1: RGB to YUV..*/
-#define LCD_CAM_LCD_CONV_TRANS_MODE    (BIT(30))
-#define LCD_CAM_LCD_CONV_TRANS_MODE_M  (BIT(30))
-#define LCD_CAM_LCD_CONV_TRANS_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_TRANS_MODE_S  30
-/* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 0: 16bits mode. 1: 8bits mode..*/
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON    (BIT(29))
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M  (BIT(29))
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V  0x1
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S  29
-/* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE    (BIT(28))
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M  (BIT(28))
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S  28
-/* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE    (BIT(27))
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M  (BIT(27))
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S  27
-/* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 0:BT601. 1:BT709..*/
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE    (BIT(26))
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M  (BIT(26))
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S  26
-/* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
-/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-mode of Data_in.*/
-#define LCD_CAM_LCD_CONV_YUV_MODE    0x00000003
-#define LCD_CAM_LCD_CONV_YUV_MODE_M  ((LCD_CAM_LCD_CONV_YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV_MODE_S))
-#define LCD_CAM_LCD_CONV_YUV_MODE_V  0x3
-#define LCD_CAM_LCD_CONV_YUV_MODE_S  24
-/* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
-/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-trans_mode must be set to 1..*/
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE    0x00000003
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M  ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV2YUV_MODE_S))
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V  0x3
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S  22
-/* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 0: txtorx mode off. 1: txtorx mode on..*/
-#define LCD_CAM_LCD_CONV_TXTORX    (BIT(21))
-#define LCD_CAM_LCD_CONV_TXTORX_M  (BIT(21))
-#define LCD_CAM_LCD_CONV_TXTORX_V  0x1
-#define LCD_CAM_LCD_CONV_TXTORX_S  21
-/* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: 1:invert every two 8bits input data. 2. disabled..*/
-#define LCD_CAM_LCD_CONV_8BITS_DATA_INV    (BIT(20))
-#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M  (BIT(20))
-#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V  0x1
-#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S  20
+/** LCDCAM_LCD_RGB_YUV_REG register
+ *  LCD YUV/RGB converter configuration register.
+ */
+#define LCDCAM_LCD_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0x10)
+/** LCDCAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0;
+ *  1:invert every two 8bits input data. 2. disabled.
+ */
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV    (BIT(20))
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV_M  (LCDCAM_LCD_CONV_8BITS_DATA_INV_V << LCDCAM_LCD_CONV_8BITS_DATA_INV_S)
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV_V  0x00000001U
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV_S  20
+/** LCDCAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0;
+ *  0: txtorx mode off. 1: txtorx mode on.
+ */
+#define LCDCAM_LCD_CONV_TXTORX    (BIT(21))
+#define LCDCAM_LCD_CONV_TXTORX_M  (LCDCAM_LCD_CONV_TXTORX_V << LCDCAM_LCD_CONV_TXTORX_S)
+#define LCDCAM_LCD_CONV_TXTORX_V  0x00000001U
+#define LCDCAM_LCD_CONV_TXTORX_S  21
+/** LCDCAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
+ *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+ *  trans_mode must be set to 1.
+ */
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE    0x00000003U
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE_M  (LCDCAM_LCD_CONV_YUV2YUV_MODE_V << LCDCAM_LCD_CONV_YUV2YUV_MODE_S)
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE_V  0x00000003U
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE_S  22
+/** LCDCAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+ *  mode of Data_in
+ */
+#define LCDCAM_LCD_CONV_YUV_MODE    0x00000003U
+#define LCDCAM_LCD_CONV_YUV_MODE_M  (LCDCAM_LCD_CONV_YUV_MODE_V << LCDCAM_LCD_CONV_YUV_MODE_S)
+#define LCDCAM_LCD_CONV_YUV_MODE_V  0x00000003U
+#define LCDCAM_LCD_CONV_YUV_MODE_S  24
+/** LCDCAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
+ *  0:BT601. 1:BT709.
+ */
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE_M  (LCDCAM_LCD_CONV_PROTOCOL_MODE_V << LCDCAM_LCD_CONV_PROTOCOL_MODE_S)
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE_S  26
+/** LCDCAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
+ *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+ */
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE_M  (LCDCAM_LCD_CONV_DATA_OUT_MODE_V << LCDCAM_LCD_CONV_DATA_OUT_MODE_S)
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE_S  27
+/** LCDCAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
+ *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+ */
+#define LCDCAM_LCD_CONV_DATA_IN_MODE    (BIT(28))
+#define LCDCAM_LCD_CONV_DATA_IN_MODE_M  (LCDCAM_LCD_CONV_DATA_IN_MODE_V << LCDCAM_LCD_CONV_DATA_IN_MODE_S)
+#define LCDCAM_LCD_CONV_DATA_IN_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_DATA_IN_MODE_S  28
+/** LCDCAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
+ *  0: 16bits mode. 1: 8bits mode.
+ */
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON_M  (LCDCAM_LCD_CONV_MODE_8BITS_ON_V << LCDCAM_LCD_CONV_MODE_8BITS_ON_S)
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON_V  0x00000001U
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON_S  29
+/** LCDCAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
+ *  0: YUV to RGB. 1: RGB to YUV.
+ */
+#define LCDCAM_LCD_CONV_TRANS_MODE    (BIT(30))
+#define LCDCAM_LCD_CONV_TRANS_MODE_M  (LCDCAM_LCD_CONV_TRANS_MODE_V << LCDCAM_LCD_CONV_TRANS_MODE_S)
+#define LCDCAM_LCD_CONV_TRANS_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_TRANS_MODE_S  30
+/** LCDCAM_LCD_CONV_ENABLE : R/W; bitpos: [31]; default: 0;
+ *  0: Bypass converter. 1: Enable converter.
+ */
+#define LCDCAM_LCD_CONV_ENABLE    (BIT(31))
+#define LCDCAM_LCD_CONV_ENABLE_M  (LCDCAM_LCD_CONV_ENABLE_V << LCDCAM_LCD_CONV_ENABLE_S)
+#define LCDCAM_LCD_CONV_ENABLE_V  0x00000001U
+#define LCDCAM_LCD_CONV_ENABLE_S  31
 
-#define LCD_CAM_LCD_USER_REG          (DR_REG_LCD_CAM_BASE + 0x14)
-/* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: The cycle length of command phase. 1: 2 cycles. 0: 1 cycle..*/
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN    (BIT(31))
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M  (BIT(31))
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V  0x1
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S  31
-/* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
-/*description: The dummy cycle length minus 1..*/
-#define LCD_CAM_LCD_DUMMY_CYCLELEN    0x00000003
-#define LCD_CAM_LCD_DUMMY_CYCLELEN_M  ((LCD_CAM_LCD_DUMMY_CYCLELEN_V)<<(LCD_CAM_LCD_DUMMY_CYCLELEN_S))
-#define LCD_CAM_LCD_DUMMY_CYCLELEN_V  0x3
-#define LCD_CAM_LCD_DUMMY_CYCLELEN_S  29
-/* LCD_CAM_LCD_RESET : WT ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The value of  command..*/
-#define LCD_CAM_LCD_RESET    (BIT(28))
-#define LCD_CAM_LCD_RESET_M  (BIT(28))
-#define LCD_CAM_LCD_RESET_V  0x1
-#define LCD_CAM_LCD_RESET_S  28
-/* LCD_CAM_LCD_START : R/W/SC ;bitpos:[27] ;default: 1'h0 ; */
-/*description: LCD start sending data enable signal, valid in high level..*/
-#define LCD_CAM_LCD_START    (BIT(27))
-#define LCD_CAM_LCD_START_M  (BIT(27))
-#define LCD_CAM_LCD_START_V  0x1
-#define LCD_CAM_LCD_START_S  27
-/* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable..*/
-#define LCD_CAM_LCD_CMD    (BIT(26))
-#define LCD_CAM_LCD_CMD_M  (BIT(26))
-#define LCD_CAM_LCD_CMD_V  0x1
-#define LCD_CAM_LCD_CMD_S  26
-/* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable..*/
-#define LCD_CAM_LCD_DUMMY    (BIT(25))
-#define LCD_CAM_LCD_DUMMY_M  (BIT(25))
-#define LCD_CAM_LCD_DUMMY_V  0x1
-#define LCD_CAM_LCD_DUMMY_S  25
-/* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable..*/
-#define LCD_CAM_LCD_DOUT    (BIT(24))
-#define LCD_CAM_LCD_DOUT_M  (BIT(24))
-#define LCD_CAM_LCD_DOUT_V  0x1
-#define LCD_CAM_LCD_DOUT_S  24
-/* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
-#define LCD_CAM_LCD_BYTE_ORDER    (BIT(23))
-#define LCD_CAM_LCD_BYTE_ORDER_M  (BIT(23))
-#define LCD_CAM_LCD_BYTE_ORDER_V  0x1
-#define LCD_CAM_LCD_BYTE_ORDER_S  23
-/* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one b
-yte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change..*/
-#define LCD_CAM_LCD_BIT_ORDER    (BIT(22))
-#define LCD_CAM_LCD_BIT_ORDER_M  (BIT(22))
-#define LCD_CAM_LCD_BIT_ORDER_V  0x1
-#define LCD_CAM_LCD_BIT_ORDER_S  22
-/* LCD_CAM_LCD_UPDATE_REG : R/W/SC ;bitpos:[21] ;default: 1'h0 ; */
-/*description: 1: Update LCD registers, will be cleared by hardware. 0 : Not care..*/
-#define LCD_CAM_LCD_UPDATE_REG    (BIT(21))
-#define LCD_CAM_LCD_UPDATE_REG_M  (BIT(21))
-#define LCD_CAM_LCD_UPDATE_REG_V  0x1
-#define LCD_CAM_LCD_UPDATE_REG_S  21
-/* LCD_CAM_LCD_BYTE_MODE : R/W ;bitpos:[20:19] ;default: 2'h0 ; */
-/*description: 2: 24bit mode. 1: 16bit mode. 0: 8bit mode.*/
-#define LCD_CAM_LCD_BYTE_MODE    0x00000003
-#define LCD_CAM_LCD_BYTE_MODE_M  ((LCD_CAM_LCD_BYTE_MODE_V)<<(LCD_CAM_LCD_BYTE_MODE_S))
-#define LCD_CAM_LCD_BYTE_MODE_V  0x3
-#define LCD_CAM_LCD_BYTE_MODE_S  19
-/* LCD_CAM_LCD_DOUT_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: 1: change bit order in every byte. 0: Not change..*/
-#define LCD_CAM_LCD_DOUT_BIT_ORDER    (BIT(18))
-#define LCD_CAM_LCD_DOUT_BIT_ORDER_M  (BIT(18))
-#define LCD_CAM_LCD_DOUT_BIT_ORDER_V  0x1
-#define LCD_CAM_LCD_DOUT_BIT_ORDER_S  18
-/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: 1: enable byte swizzle 0: disable.*/
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE    (BIT(17))
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M  (BIT(17))
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V  0x1
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S  17
-/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W ;bitpos:[16:14] ;default: 3'h0 ; */
-/*description: 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA.*/
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE    0x00000007
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M  ((LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V)<<(LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S))
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V  0x7
-#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S  14
-/* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */
-/*description: LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared
- or reg_lcd_reset is set..*/
-#define LCD_CAM_LCD_ALWAYS_OUT_EN    (BIT(13))
-#define LCD_CAM_LCD_ALWAYS_OUT_EN_M  (BIT(13))
-#define LCD_CAM_LCD_ALWAYS_OUT_EN_V  0x1
-#define LCD_CAM_LCD_ALWAYS_OUT_EN_S  13
-/* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
-/*description: The output data cycles minus 1 of LCD module..*/
-#define LCD_CAM_LCD_DOUT_CYCLELEN    0x00001FFF
-#define LCD_CAM_LCD_DOUT_CYCLELEN_M  ((LCD_CAM_LCD_DOUT_CYCLELEN_V)<<(LCD_CAM_LCD_DOUT_CYCLELEN_S))
-#define LCD_CAM_LCD_DOUT_CYCLELEN_V  0x1FFF
-#define LCD_CAM_LCD_DOUT_CYCLELEN_S  0
+/** LCDCAM_LCD_USER_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_USER_REG (DR_REG_LCDCAM_BASE + 0x14)
+/** LCDCAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1;
+ *  The output data cycles minus 1 of LCD module.
+ */
+#define LCDCAM_LCD_DOUT_CYCLELEN    0x00001FFFU
+#define LCDCAM_LCD_DOUT_CYCLELEN_M  (LCDCAM_LCD_DOUT_CYCLELEN_V << LCDCAM_LCD_DOUT_CYCLELEN_S)
+#define LCDCAM_LCD_DOUT_CYCLELEN_V  0x00001FFFU
+#define LCDCAM_LCD_DOUT_CYCLELEN_S  0
+/** LCDCAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0;
+ *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+ *  reg_lcd_reset is set.
+ */
+#define LCDCAM_LCD_ALWAYS_OUT_EN    (BIT(13))
+#define LCDCAM_LCD_ALWAYS_OUT_EN_M  (LCDCAM_LCD_ALWAYS_OUT_EN_V << LCDCAM_LCD_ALWAYS_OUT_EN_S)
+#define LCDCAM_LCD_ALWAYS_OUT_EN_V  0x00000001U
+#define LCDCAM_LCD_ALWAYS_OUT_EN_S  13
+/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W; bitpos: [16:14]; default: 0;
+ *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
+ */
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE    0x00000007U
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M  (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S)
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V  0x00000007U
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S  14
+/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W; bitpos: [17]; default: 0;
+ *  1: enable byte swizzle 0: disable
+ */
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE    (BIT(17))
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M  (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S)
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V  0x00000001U
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S  17
+/** LCDCAM_LCD_DOUT_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  1: change bit order in every byte. 0: Not change.
+ */
+#define LCDCAM_LCD_DOUT_BIT_ORDER    (BIT(18))
+#define LCDCAM_LCD_DOUT_BIT_ORDER_M  (LCDCAM_LCD_DOUT_BIT_ORDER_V << LCDCAM_LCD_DOUT_BIT_ORDER_S)
+#define LCDCAM_LCD_DOUT_BIT_ORDER_V  0x00000001U
+#define LCDCAM_LCD_DOUT_BIT_ORDER_S  18
+/** LCDCAM_LCD_BYTE_MODE : R/W; bitpos: [20:19]; default: 0;
+ *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
+ */
+#define LCDCAM_LCD_BYTE_MODE    0x00000003U
+#define LCDCAM_LCD_BYTE_MODE_M  (LCDCAM_LCD_BYTE_MODE_V << LCDCAM_LCD_BYTE_MODE_S)
+#define LCDCAM_LCD_BYTE_MODE_V  0x00000003U
+#define LCDCAM_LCD_BYTE_MODE_S  19
+/** LCDCAM_LCD_UPDATE_REG : R/W/SC; bitpos: [21]; default: 0;
+ *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+ */
+#define LCDCAM_LCD_UPDATE_REG    (BIT(21))
+#define LCDCAM_LCD_UPDATE_REG_M  (LCDCAM_LCD_UPDATE_REG_V << LCDCAM_LCD_UPDATE_REG_S)
+#define LCDCAM_LCD_UPDATE_REG_V  0x00000001U
+#define LCDCAM_LCD_UPDATE_REG_S  21
+/** LCDCAM_LCD_BIT_ORDER : R/W; bitpos: [22]; default: 0;
+ *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+ *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+ */
+#define LCDCAM_LCD_BIT_ORDER    (BIT(22))
+#define LCDCAM_LCD_BIT_ORDER_M  (LCDCAM_LCD_BIT_ORDER_V << LCDCAM_LCD_BIT_ORDER_S)
+#define LCDCAM_LCD_BIT_ORDER_V  0x00000001U
+#define LCDCAM_LCD_BIT_ORDER_S  22
+/** LCDCAM_LCD_BYTE_ORDER : R/W; bitpos: [23]; default: 0;
+ *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+ */
+#define LCDCAM_LCD_BYTE_ORDER    (BIT(23))
+#define LCDCAM_LCD_BYTE_ORDER_M  (LCDCAM_LCD_BYTE_ORDER_V << LCDCAM_LCD_BYTE_ORDER_S)
+#define LCDCAM_LCD_BYTE_ORDER_V  0x00000001U
+#define LCDCAM_LCD_BYTE_ORDER_S  23
+/** LCDCAM_LCD_DOUT : R/W; bitpos: [24]; default: 0;
+ *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCDCAM_LCD_DOUT    (BIT(24))
+#define LCDCAM_LCD_DOUT_M  (LCDCAM_LCD_DOUT_V << LCDCAM_LCD_DOUT_S)
+#define LCDCAM_LCD_DOUT_V  0x00000001U
+#define LCDCAM_LCD_DOUT_S  24
+/** LCDCAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0;
+ *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCDCAM_LCD_DUMMY    (BIT(25))
+#define LCDCAM_LCD_DUMMY_M  (LCDCAM_LCD_DUMMY_V << LCDCAM_LCD_DUMMY_S)
+#define LCDCAM_LCD_DUMMY_V  0x00000001U
+#define LCDCAM_LCD_DUMMY_S  25
+/** LCDCAM_LCD_CMD : R/W; bitpos: [26]; default: 0;
+ *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCDCAM_LCD_CMD    (BIT(26))
+#define LCDCAM_LCD_CMD_M  (LCDCAM_LCD_CMD_V << LCDCAM_LCD_CMD_S)
+#define LCDCAM_LCD_CMD_V  0x00000001U
+#define LCDCAM_LCD_CMD_S  26
+/** LCDCAM_LCD_START : R/W/SC; bitpos: [27]; default: 0;
+ *  LCD start sending data enable signal, valid in high level.
+ */
+#define LCDCAM_LCD_START    (BIT(27))
+#define LCDCAM_LCD_START_M  (LCDCAM_LCD_START_V << LCDCAM_LCD_START_S)
+#define LCDCAM_LCD_START_V  0x00000001U
+#define LCDCAM_LCD_START_S  27
+/** LCDCAM_LCD_RESET : WT; bitpos: [28]; default: 0;
+ *  The value of  command.
+ */
+#define LCDCAM_LCD_RESET    (BIT(28))
+#define LCDCAM_LCD_RESET_M  (LCDCAM_LCD_RESET_V << LCDCAM_LCD_RESET_S)
+#define LCDCAM_LCD_RESET_V  0x00000001U
+#define LCDCAM_LCD_RESET_S  28
+/** LCDCAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0;
+ *  The dummy cycle length minus 1.
+ */
+#define LCDCAM_LCD_DUMMY_CYCLELEN    0x00000003U
+#define LCDCAM_LCD_DUMMY_CYCLELEN_M  (LCDCAM_LCD_DUMMY_CYCLELEN_V << LCDCAM_LCD_DUMMY_CYCLELEN_S)
+#define LCDCAM_LCD_DUMMY_CYCLELEN_V  0x00000003U
+#define LCDCAM_LCD_DUMMY_CYCLELEN_S  29
+/** LCDCAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0;
+ *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
+ */
+#define LCDCAM_LCD_CMD_2_CYCLE_EN    (BIT(31))
+#define LCDCAM_LCD_CMD_2_CYCLE_EN_M  (LCDCAM_LCD_CMD_2_CYCLE_EN_V << LCDCAM_LCD_CMD_2_CYCLE_EN_S)
+#define LCDCAM_LCD_CMD_2_CYCLE_EN_V  0x00000001U
+#define LCDCAM_LCD_CMD_2_CYCLE_EN_S  31
 
-#define LCD_CAM_LCD_MISC_REG          (DR_REG_LCD_CAM_BASE + 0x18)
-/* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: The default value of LCD_CD..*/
-#define LCD_CAM_LCD_CD_IDLE_EDGE    (BIT(31))
-#define LCD_CAM_LCD_CD_IDLE_EDGE_M  (BIT(31))
-#define LCD_CAM_LCD_CD_IDLE_EDGE_V  0x1
-#define LCD_CAM_LCD_CD_IDLE_EDGE_S  31
-/* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
- reg_cd_idle_edge..*/
-#define LCD_CAM_LCD_CD_CMD_SET    (BIT(30))
-#define LCD_CAM_LCD_CD_CMD_SET_M  (BIT(30))
-#define LCD_CAM_LCD_CD_CMD_SET_V  0x1
-#define LCD_CAM_LCD_CD_CMD_SET_S  30
-/* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */
-/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD
- = reg_cd_idle_edge..*/
-#define LCD_CAM_LCD_CD_DUMMY_SET    (BIT(29))
-#define LCD_CAM_LCD_CD_DUMMY_SET_M  (BIT(29))
-#define LCD_CAM_LCD_CD_DUMMY_SET_V  0x1
-#define LCD_CAM_LCD_CD_DUMMY_SET_S  29
-/* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD
-= reg_cd_idle_edge..*/
-#define LCD_CAM_LCD_CD_DATA_SET    (BIT(28))
-#define LCD_CAM_LCD_CD_DATA_SET_M  (BIT(28))
-#define LCD_CAM_LCD_CD_DATA_SET_V  0x1
-#define LCD_CAM_LCD_CD_DATA_SET_S  28
-/* LCD_CAM_LCD_AFIFO_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
-/*description: LCD AFIFO reset signal..*/
-#define LCD_CAM_LCD_AFIFO_RESET    (BIT(27))
-#define LCD_CAM_LCD_AFIFO_RESET_M  (BIT(27))
-#define LCD_CAM_LCD_AFIFO_RESET_V  0x1
-#define LCD_CAM_LCD_AFIFO_RESET_S  27
-/* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: Enable blank region when LCD sends data out. 0: No blank region..*/
-#define LCD_CAM_LCD_BK_EN    (BIT(26))
-#define LCD_CAM_LCD_BK_EN_M  (BIT(26))
-#define LCD_CAM_LCD_BK_EN_V  0x1
-#define LCD_CAM_LCD_BK_EN_S  26
-/* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: 1: Send the next frame data when the current frame is sent out. 0: LCD stops whe
-n the current frame is sent out..*/
-#define LCD_CAM_LCD_NEXT_FRAME_EN    (BIT(25))
-#define LCD_CAM_LCD_NEXT_FRAME_EN_M  (BIT(25))
-#define LCD_CAM_LCD_NEXT_FRAME_EN_V  0x1
-#define LCD_CAM_LCD_NEXT_FRAME_EN_S  25
-/* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */
-/*description: The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
- time cycle length in LCD non-RGB mode..*/
-#define LCD_CAM_LCD_VBK_CYCLELEN    0x00001FFF
-#define LCD_CAM_LCD_VBK_CYCLELEN_M  ((LCD_CAM_LCD_VBK_CYCLELEN_V)<<(LCD_CAM_LCD_VBK_CYCLELEN_S))
-#define LCD_CAM_LCD_VBK_CYCLELEN_V  0x1FFF
-#define LCD_CAM_LCD_VBK_CYCLELEN_S  12
-/* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */
-/*description: The setup cycle length minus 1 in LCD non-RGB mode..*/
-#define LCD_CAM_LCD_VFK_CYCLELEN    0x0000003F
-#define LCD_CAM_LCD_VFK_CYCLELEN_M  ((LCD_CAM_LCD_VFK_CYCLELEN_V)<<(LCD_CAM_LCD_VFK_CYCLELEN_S))
-#define LCD_CAM_LCD_VFK_CYCLELEN_V  0x3F
-#define LCD_CAM_LCD_VFK_CYCLELEN_S  6
-/* LCD_CAM_LCD_WIRE_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit.*/
-#define LCD_CAM_LCD_WIRE_MODE    0x00000003
-#define LCD_CAM_LCD_WIRE_MODE_M  ((LCD_CAM_LCD_WIRE_MODE_V)<<(LCD_CAM_LCD_WIRE_MODE_S))
-#define LCD_CAM_LCD_WIRE_MODE_V  0x3
-#define LCD_CAM_LCD_WIRE_MODE_S  4
+/** LCDCAM_LCD_MISC_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_MISC_REG (DR_REG_LCDCAM_BASE + 0x18)
+/** LCDCAM_LCD_WIRE_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
+ */
+#define LCDCAM_LCD_WIRE_MODE    0x00000003U
+#define LCDCAM_LCD_WIRE_MODE_M  (LCDCAM_LCD_WIRE_MODE_V << LCDCAM_LCD_WIRE_MODE_S)
+#define LCDCAM_LCD_WIRE_MODE_V  0x00000003U
+#define LCDCAM_LCD_WIRE_MODE_S  4
+/** LCDCAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3;
+ *  The setup cycle length minus 1 in LCD non-RGB mode.
+ */
+#define LCDCAM_LCD_VFK_CYCLELEN    0x0000003FU
+#define LCDCAM_LCD_VFK_CYCLELEN_M  (LCDCAM_LCD_VFK_CYCLELEN_V << LCDCAM_LCD_VFK_CYCLELEN_S)
+#define LCDCAM_LCD_VFK_CYCLELEN_V  0x0000003FU
+#define LCDCAM_LCD_VFK_CYCLELEN_S  6
+/** LCDCAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0;
+ *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+ *  time cycle length in LCD non-RGB mode.
+ */
+#define LCDCAM_LCD_VBK_CYCLELEN    0x00001FFFU
+#define LCDCAM_LCD_VBK_CYCLELEN_M  (LCDCAM_LCD_VBK_CYCLELEN_V << LCDCAM_LCD_VBK_CYCLELEN_S)
+#define LCDCAM_LCD_VBK_CYCLELEN_V  0x00001FFFU
+#define LCDCAM_LCD_VBK_CYCLELEN_S  12
+/** LCDCAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0;
+ *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+ *  the current frame is sent out.
+ */
+#define LCDCAM_LCD_NEXT_FRAME_EN    (BIT(25))
+#define LCDCAM_LCD_NEXT_FRAME_EN_M  (LCDCAM_LCD_NEXT_FRAME_EN_V << LCDCAM_LCD_NEXT_FRAME_EN_S)
+#define LCDCAM_LCD_NEXT_FRAME_EN_V  0x00000001U
+#define LCDCAM_LCD_NEXT_FRAME_EN_S  25
+/** LCDCAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0;
+ *  1: Enable blank region when LCD sends data out. 0: No blank region.
+ */
+#define LCDCAM_LCD_BK_EN    (BIT(26))
+#define LCDCAM_LCD_BK_EN_M  (LCDCAM_LCD_BK_EN_V << LCDCAM_LCD_BK_EN_S)
+#define LCDCAM_LCD_BK_EN_V  0x00000001U
+#define LCDCAM_LCD_BK_EN_S  26
+/** LCDCAM_LCD_AFIFO_RESET : WT; bitpos: [27]; default: 0;
+ *  LCD AFIFO reset signal.
+ */
+#define LCDCAM_LCD_AFIFO_RESET    (BIT(27))
+#define LCDCAM_LCD_AFIFO_RESET_M  (LCDCAM_LCD_AFIFO_RESET_V << LCDCAM_LCD_AFIFO_RESET_S)
+#define LCDCAM_LCD_AFIFO_RESET_V  0x00000001U
+#define LCDCAM_LCD_AFIFO_RESET_S  27
+/** LCDCAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCDCAM_LCD_CD_DATA_SET    (BIT(28))
+#define LCDCAM_LCD_CD_DATA_SET_M  (LCDCAM_LCD_CD_DATA_SET_V << LCDCAM_LCD_CD_DATA_SET_S)
+#define LCDCAM_LCD_CD_DATA_SET_V  0x00000001U
+#define LCDCAM_LCD_CD_DATA_SET_S  28
+/** LCDCAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCDCAM_LCD_CD_DUMMY_SET    (BIT(29))
+#define LCDCAM_LCD_CD_DUMMY_SET_M  (LCDCAM_LCD_CD_DUMMY_SET_V << LCDCAM_LCD_CD_DUMMY_SET_S)
+#define LCDCAM_LCD_CD_DUMMY_SET_V  0x00000001U
+#define LCDCAM_LCD_CD_DUMMY_SET_S  29
+/** LCDCAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCDCAM_LCD_CD_CMD_SET    (BIT(30))
+#define LCDCAM_LCD_CD_CMD_SET_M  (LCDCAM_LCD_CD_CMD_SET_V << LCDCAM_LCD_CD_CMD_SET_S)
+#define LCDCAM_LCD_CD_CMD_SET_V  0x00000001U
+#define LCDCAM_LCD_CD_CMD_SET_S  30
+/** LCDCAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0;
+ *  The default value of LCD_CD.
+ */
+#define LCDCAM_LCD_CD_IDLE_EDGE    (BIT(31))
+#define LCDCAM_LCD_CD_IDLE_EDGE_M  (LCDCAM_LCD_CD_IDLE_EDGE_V << LCDCAM_LCD_CD_IDLE_EDGE_S)
+#define LCDCAM_LCD_CD_IDLE_EDGE_V  0x00000001U
+#define LCDCAM_LCD_CD_IDLE_EDGE_S  31
 
-#define LCD_CAM_LCD_CTRL_REG          (DR_REG_LCD_CAM_BASE + 0x1C)
-/* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: Enable LCD RGB mode. 0: Disable LCD RGB mode..*/
-#define LCD_CAM_LCD_RGB_MODE_EN    (BIT(31))
-#define LCD_CAM_LCD_RGB_MODE_EN_M  (BIT(31))
-#define LCD_CAM_LCD_RGB_MODE_EN_V  0x1
-#define LCD_CAM_LCD_RGB_MODE_EN_S  31
-/* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */
-/*description: It is the vertical total height of a frame..*/
-#define LCD_CAM_LCD_VT_HEIGHT    0x000003FF
-#define LCD_CAM_LCD_VT_HEIGHT_M  ((LCD_CAM_LCD_VT_HEIGHT_V)<<(LCD_CAM_LCD_VT_HEIGHT_S))
-#define LCD_CAM_LCD_VT_HEIGHT_V  0x3FF
-#define LCD_CAM_LCD_VT_HEIGHT_S  21
-/* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */
-/*description: It is the vertical active height of a frame..*/
-#define LCD_CAM_LCD_VA_HEIGHT    0x000003FF
-#define LCD_CAM_LCD_VA_HEIGHT_M  ((LCD_CAM_LCD_VA_HEIGHT_V)<<(LCD_CAM_LCD_VA_HEIGHT_S))
-#define LCD_CAM_LCD_VA_HEIGHT_V  0x3FF
-#define LCD_CAM_LCD_VA_HEIGHT_S  11
-/* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */
-/*description: It is the horizontal blank front porch of a frame..*/
-#define LCD_CAM_LCD_HB_FRONT    0x000007FF
-#define LCD_CAM_LCD_HB_FRONT_M  ((LCD_CAM_LCD_HB_FRONT_V)<<(LCD_CAM_LCD_HB_FRONT_S))
-#define LCD_CAM_LCD_HB_FRONT_V  0x7FF
-#define LCD_CAM_LCD_HB_FRONT_S  0
+/** LCDCAM_LCD_CTRL_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_CTRL_REG (DR_REG_LCDCAM_BASE + 0x1c)
+/** LCDCAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0;
+ *  It is the horizontal blank front porch of a frame.
+ */
+#define LCDCAM_LCD_HB_FRONT    0x000007FFU
+#define LCDCAM_LCD_HB_FRONT_M  (LCDCAM_LCD_HB_FRONT_V << LCDCAM_LCD_HB_FRONT_S)
+#define LCDCAM_LCD_HB_FRONT_V  0x000007FFU
+#define LCDCAM_LCD_HB_FRONT_S  0
+/** LCDCAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0;
+ *  It is the vertical active height of a frame.
+ */
+#define LCDCAM_LCD_VA_HEIGHT    0x000003FFU
+#define LCDCAM_LCD_VA_HEIGHT_M  (LCDCAM_LCD_VA_HEIGHT_V << LCDCAM_LCD_VA_HEIGHT_S)
+#define LCDCAM_LCD_VA_HEIGHT_V  0x000003FFU
+#define LCDCAM_LCD_VA_HEIGHT_S  11
+/** LCDCAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0;
+ *  It is the vertical total height of a frame.
+ */
+#define LCDCAM_LCD_VT_HEIGHT    0x000003FFU
+#define LCDCAM_LCD_VT_HEIGHT_M  (LCDCAM_LCD_VT_HEIGHT_V << LCDCAM_LCD_VT_HEIGHT_S)
+#define LCDCAM_LCD_VT_HEIGHT_V  0x000003FFU
+#define LCDCAM_LCD_VT_HEIGHT_S  21
+/** LCDCAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0;
+ *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
+ */
+#define LCDCAM_LCD_RGB_MODE_EN    (BIT(31))
+#define LCDCAM_LCD_RGB_MODE_EN_M  (LCDCAM_LCD_RGB_MODE_EN_V << LCDCAM_LCD_RGB_MODE_EN_S)
+#define LCDCAM_LCD_RGB_MODE_EN_V  0x00000001U
+#define LCDCAM_LCD_RGB_MODE_EN_S  31
 
-#define LCD_CAM_LCD_CTRL1_REG          (DR_REG_LCD_CAM_BASE + 0x20)
-/* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */
-/*description: It is the horizontal total width of a frame..*/
-#define LCD_CAM_LCD_HT_WIDTH    0x00000FFF
-#define LCD_CAM_LCD_HT_WIDTH_M  ((LCD_CAM_LCD_HT_WIDTH_V)<<(LCD_CAM_LCD_HT_WIDTH_S))
-#define LCD_CAM_LCD_HT_WIDTH_V  0xFFF
-#define LCD_CAM_LCD_HT_WIDTH_S  20
-/* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */
-/*description: It is the horizontal active width of a frame..*/
-#define LCD_CAM_LCD_HA_WIDTH    0x00000FFF
-#define LCD_CAM_LCD_HA_WIDTH_M  ((LCD_CAM_LCD_HA_WIDTH_V)<<(LCD_CAM_LCD_HA_WIDTH_S))
-#define LCD_CAM_LCD_HA_WIDTH_V  0xFFF
-#define LCD_CAM_LCD_HA_WIDTH_S  8
-/* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
-/*description: It is the vertical blank front porch of a frame..*/
-#define LCD_CAM_LCD_VB_FRONT    0x000000FF
-#define LCD_CAM_LCD_VB_FRONT_M  ((LCD_CAM_LCD_VB_FRONT_V)<<(LCD_CAM_LCD_VB_FRONT_S))
-#define LCD_CAM_LCD_VB_FRONT_V  0xFF
-#define LCD_CAM_LCD_VB_FRONT_S  0
+/** LCDCAM_LCD_CTRL1_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x20)
+/** LCDCAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0;
+ *  It is the vertical blank front porch of a frame.
+ */
+#define LCDCAM_LCD_VB_FRONT    0x000000FFU
+#define LCDCAM_LCD_VB_FRONT_M  (LCDCAM_LCD_VB_FRONT_V << LCDCAM_LCD_VB_FRONT_S)
+#define LCDCAM_LCD_VB_FRONT_V  0x000000FFU
+#define LCDCAM_LCD_VB_FRONT_S  0
+/** LCDCAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0;
+ *  It is the horizontal active width of a frame.
+ */
+#define LCDCAM_LCD_HA_WIDTH    0x00000FFFU
+#define LCDCAM_LCD_HA_WIDTH_M  (LCDCAM_LCD_HA_WIDTH_V << LCDCAM_LCD_HA_WIDTH_S)
+#define LCDCAM_LCD_HA_WIDTH_V  0x00000FFFU
+#define LCDCAM_LCD_HA_WIDTH_S  8
+/** LCDCAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0;
+ *  It is the horizontal total width of a frame.
+ */
+#define LCDCAM_LCD_HT_WIDTH    0x00000FFFU
+#define LCDCAM_LCD_HT_WIDTH_M  (LCDCAM_LCD_HT_WIDTH_V << LCDCAM_LCD_HT_WIDTH_S)
+#define LCDCAM_LCD_HT_WIDTH_V  0x00000FFFU
+#define LCDCAM_LCD_HT_WIDTH_S  20
 
-#define LCD_CAM_LCD_CTRL2_REG          (DR_REG_LCD_CAM_BASE + 0x24)
-/* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
-/*description: It is the position of LCD_HSYNC active pulse in a line..*/
-#define LCD_CAM_LCD_HSYNC_POSITION    0x000000FF
-#define LCD_CAM_LCD_HSYNC_POSITION_M  ((LCD_CAM_LCD_HSYNC_POSITION_V)<<(LCD_CAM_LCD_HSYNC_POSITION_S))
-#define LCD_CAM_LCD_HSYNC_POSITION_V  0xFF
-#define LCD_CAM_LCD_HSYNC_POSITION_S  24
-/* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: It is the idle value of LCD_HSYNC..*/
-#define LCD_CAM_LCD_HSYNC_IDLE_POL    (BIT(23))
-#define LCD_CAM_LCD_HSYNC_IDLE_POL_M  (BIT(23))
-#define LCD_CAM_LCD_HSYNC_IDLE_POL_V  0x1
-#define LCD_CAM_LCD_HSYNC_IDLE_POL_S  23
-/* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */
-/*description: It is the position of LCD_HSYNC active pulse in a line..*/
-#define LCD_CAM_LCD_HSYNC_WIDTH    0x0000007F
-#define LCD_CAM_LCD_HSYNC_WIDTH_M  ((LCD_CAM_LCD_HSYNC_WIDTH_V)<<(LCD_CAM_LCD_HSYNC_WIDTH_S))
-#define LCD_CAM_LCD_HSYNC_WIDTH_V  0x7F
-#define LCD_CAM_LCD_HSYNC_WIDTH_S  16
-/* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSY
-NC pulse is valid only in active region lines in RGB mode..*/
-#define LCD_CAM_LCD_HS_BLANK_EN    (BIT(9))
-#define LCD_CAM_LCD_HS_BLANK_EN_M  (BIT(9))
-#define LCD_CAM_LCD_HS_BLANK_EN_V  0x1
-#define LCD_CAM_LCD_HS_BLANK_EN_S  9
-/* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: It is the idle value of LCD_DE..*/
-#define LCD_CAM_LCD_DE_IDLE_POL    (BIT(8))
-#define LCD_CAM_LCD_DE_IDLE_POL_M  (BIT(8))
-#define LCD_CAM_LCD_DE_IDLE_POL_V  0x1
-#define LCD_CAM_LCD_DE_IDLE_POL_S  8
-/* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: It is the idle value of LCD_VSYNC..*/
-#define LCD_CAM_LCD_VSYNC_IDLE_POL    (BIT(7))
-#define LCD_CAM_LCD_VSYNC_IDLE_POL_M  (BIT(7))
-#define LCD_CAM_LCD_VSYNC_IDLE_POL_V  0x1
-#define LCD_CAM_LCD_VSYNC_IDLE_POL_S  7
-/* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
-/*description: It is the position of LCD_VSYNC active pulse in a line..*/
-#define LCD_CAM_LCD_VSYNC_WIDTH    0x0000007F
-#define LCD_CAM_LCD_VSYNC_WIDTH_M  ((LCD_CAM_LCD_VSYNC_WIDTH_V)<<(LCD_CAM_LCD_VSYNC_WIDTH_S))
-#define LCD_CAM_LCD_VSYNC_WIDTH_V  0x7F
-#define LCD_CAM_LCD_VSYNC_WIDTH_S  0
+/** LCDCAM_LCD_CTRL2_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_CTRL2_REG (DR_REG_LCDCAM_BASE + 0x24)
+/** LCDCAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1;
+ *  It is the position of LCD_VSYNC active pulse in a line.
+ */
+#define LCDCAM_LCD_VSYNC_WIDTH    0x0000007FU
+#define LCDCAM_LCD_VSYNC_WIDTH_M  (LCDCAM_LCD_VSYNC_WIDTH_V << LCDCAM_LCD_VSYNC_WIDTH_S)
+#define LCDCAM_LCD_VSYNC_WIDTH_V  0x0000007FU
+#define LCDCAM_LCD_VSYNC_WIDTH_S  0
+/** LCDCAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0;
+ *  It is the idle value of LCD_VSYNC.
+ */
+#define LCDCAM_LCD_VSYNC_IDLE_POL    (BIT(7))
+#define LCDCAM_LCD_VSYNC_IDLE_POL_M  (LCDCAM_LCD_VSYNC_IDLE_POL_V << LCDCAM_LCD_VSYNC_IDLE_POL_S)
+#define LCDCAM_LCD_VSYNC_IDLE_POL_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_IDLE_POL_S  7
+/** LCDCAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0;
+ *  It is the idle value of LCD_DE.
+ */
+#define LCDCAM_LCD_DE_IDLE_POL    (BIT(8))
+#define LCDCAM_LCD_DE_IDLE_POL_M  (LCDCAM_LCD_DE_IDLE_POL_V << LCDCAM_LCD_DE_IDLE_POL_S)
+#define LCDCAM_LCD_DE_IDLE_POL_V  0x00000001U
+#define LCDCAM_LCD_DE_IDLE_POL_S  8
+/** LCDCAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0;
+ *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+ *  pulse is valid only in active region lines in RGB mode.
+ */
+#define LCDCAM_LCD_HS_BLANK_EN    (BIT(9))
+#define LCDCAM_LCD_HS_BLANK_EN_M  (LCDCAM_LCD_HS_BLANK_EN_V << LCDCAM_LCD_HS_BLANK_EN_S)
+#define LCDCAM_LCD_HS_BLANK_EN_V  0x00000001U
+#define LCDCAM_LCD_HS_BLANK_EN_S  9
+/** LCDCAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1;
+ *  It is the position of LCD_HSYNC active pulse in a line.
+ */
+#define LCDCAM_LCD_HSYNC_WIDTH    0x0000007FU
+#define LCDCAM_LCD_HSYNC_WIDTH_M  (LCDCAM_LCD_HSYNC_WIDTH_V << LCDCAM_LCD_HSYNC_WIDTH_S)
+#define LCDCAM_LCD_HSYNC_WIDTH_V  0x0000007FU
+#define LCDCAM_LCD_HSYNC_WIDTH_S  16
+/** LCDCAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0;
+ *  It is the idle value of LCD_HSYNC.
+ */
+#define LCDCAM_LCD_HSYNC_IDLE_POL    (BIT(23))
+#define LCDCAM_LCD_HSYNC_IDLE_POL_M  (LCDCAM_LCD_HSYNC_IDLE_POL_V << LCDCAM_LCD_HSYNC_IDLE_POL_S)
+#define LCDCAM_LCD_HSYNC_IDLE_POL_V  0x00000001U
+#define LCDCAM_LCD_HSYNC_IDLE_POL_S  23
+/** LCDCAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0;
+ *  It is the position of LCD_HSYNC active pulse in a line.
+ */
+#define LCDCAM_LCD_HSYNC_POSITION    0x000000FFU
+#define LCDCAM_LCD_HSYNC_POSITION_M  (LCDCAM_LCD_HSYNC_POSITION_V << LCDCAM_LCD_HSYNC_POSITION_S)
+#define LCDCAM_LCD_HSYNC_POSITION_V  0x000000FFU
+#define LCDCAM_LCD_HSYNC_POSITION_S  24
 
-#define LCD_CAM_LCD_FIRST_CMD_VAL_REG          (DR_REG_LCD_CAM_BASE + 0x28)
-/* LCD_CAM_LCD_FIRST_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The LCD write command value of first cmd cycle..*/
-#define LCD_CAM_LCD_FIRST_CMD_VALUE    0xFFFFFFFF
-#define LCD_CAM_LCD_FIRST_CMD_VALUE_M  ((LCD_CAM_LCD_FIRST_CMD_VALUE_V)<<(LCD_CAM_LCD_FIRST_CMD_VALUE_S))
-#define LCD_CAM_LCD_FIRST_CMD_VALUE_V  0xFFFFFFFF
-#define LCD_CAM_LCD_FIRST_CMD_VALUE_S  0
+/** LCDCAM_LCD_FIRST_CMD_VAL_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x28)
+/** LCDCAM_LCD_FIRST_CMD_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  The LCD write command value of first cmd cycle.
+ */
+#define LCDCAM_LCD_FIRST_CMD_VALUE    0xFFFFFFFFU
+#define LCDCAM_LCD_FIRST_CMD_VALUE_M  (LCDCAM_LCD_FIRST_CMD_VALUE_V << LCDCAM_LCD_FIRST_CMD_VALUE_S)
+#define LCDCAM_LCD_FIRST_CMD_VALUE_V  0xFFFFFFFFU
+#define LCDCAM_LCD_FIRST_CMD_VALUE_S  0
 
-#define LCD_CAM_LCD_LATTER_CMD_VAL_REG          (DR_REG_LCD_CAM_BASE + 0x2C)
-/* LCD_CAM_LCD_LATTER_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The LCD write command value of latter cmd cycle..*/
-#define LCD_CAM_LCD_LATTER_CMD_VALUE    0xFFFFFFFF
-#define LCD_CAM_LCD_LATTER_CMD_VALUE_M  ((LCD_CAM_LCD_LATTER_CMD_VALUE_V)<<(LCD_CAM_LCD_LATTER_CMD_VALUE_S))
-#define LCD_CAM_LCD_LATTER_CMD_VALUE_V  0xFFFFFFFF
-#define LCD_CAM_LCD_LATTER_CMD_VALUE_S  0
+/** LCDCAM_LCD_LATTER_CMD_VAL_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x2c)
+/** LCDCAM_LCD_LATTER_CMD_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  The LCD write command value of latter cmd cycle.
+ */
+#define LCDCAM_LCD_LATTER_CMD_VALUE    0xFFFFFFFFU
+#define LCDCAM_LCD_LATTER_CMD_VALUE_M  (LCDCAM_LCD_LATTER_CMD_VALUE_V << LCDCAM_LCD_LATTER_CMD_VALUE_S)
+#define LCDCAM_LCD_LATTER_CMD_VALUE_V  0xFFFFFFFFU
+#define LCDCAM_LCD_LATTER_CMD_VALUE_S  0
 
-#define LCD_CAM_LCD_DLY_MODE_CFG1_REG          (DR_REG_LCD_CAM_BASE + 0x30)
-/* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
-/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay
-ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L
-CD_CLK..*/
-#define LCD_CAM_LCD_VSYNC_MODE    0x00000003
-#define LCD_CAM_LCD_VSYNC_MODE_M  ((LCD_CAM_LCD_VSYNC_MODE_V)<<(LCD_CAM_LCD_VSYNC_MODE_S))
-#define LCD_CAM_LCD_VSYNC_MODE_V  0x3
-#define LCD_CAM_LCD_VSYNC_MODE_S  22
-/* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay
-ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L
-CD_CLK..*/
-#define LCD_CAM_LCD_HSYNC_MODE    0x00000003
-#define LCD_CAM_LCD_HSYNC_MODE_M  ((LCD_CAM_LCD_HSYNC_MODE_V)<<(LCD_CAM_LCD_HSYNC_MODE_S))
-#define LCD_CAM_LCD_HSYNC_MODE_V  0x3
-#define LCD_CAM_LCD_HSYNC_MODE_S  20
-/* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
-/*description: The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed.
- 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_
-CLK..*/
-#define LCD_CAM_LCD_DE_MODE    0x00000003
-#define LCD_CAM_LCD_DE_MODE_M  ((LCD_CAM_LCD_DE_MODE_V)<<(LCD_CAM_LCD_DE_MODE_S))
-#define LCD_CAM_LCD_DE_MODE_V  0x3
-#define LCD_CAM_LCD_DE_MODE_S  18
-/* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed.
- 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_
-CLK..*/
-#define LCD_CAM_LCD_CD_MODE    0x00000003
-#define LCD_CAM_LCD_CD_MODE_M  ((LCD_CAM_LCD_CD_MODE_V)<<(LCD_CAM_LCD_CD_MODE_S))
-#define LCD_CAM_LCD_CD_MODE_V  0x3
-#define LCD_CAM_LCD_CD_MODE_S  16
-/* LCD_CAM_DOUT23_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT23_MODE    0x00000003
-#define LCD_CAM_DOUT23_MODE_M  ((LCD_CAM_DOUT23_MODE_V)<<(LCD_CAM_DOUT23_MODE_S))
-#define LCD_CAM_DOUT23_MODE_V  0x3
-#define LCD_CAM_DOUT23_MODE_S  14
-/* LCD_CAM_DOUT22_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT22_MODE    0x00000003
-#define LCD_CAM_DOUT22_MODE_M  ((LCD_CAM_DOUT22_MODE_V)<<(LCD_CAM_DOUT22_MODE_S))
-#define LCD_CAM_DOUT22_MODE_V  0x3
-#define LCD_CAM_DOUT22_MODE_S  12
-/* LCD_CAM_DOUT21_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT21_MODE    0x00000003
-#define LCD_CAM_DOUT21_MODE_M  ((LCD_CAM_DOUT21_MODE_V)<<(LCD_CAM_DOUT21_MODE_S))
-#define LCD_CAM_DOUT21_MODE_V  0x3
-#define LCD_CAM_DOUT21_MODE_S  10
-/* LCD_CAM_DOUT20_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT20_MODE    0x00000003
-#define LCD_CAM_DOUT20_MODE_M  ((LCD_CAM_DOUT20_MODE_V)<<(LCD_CAM_DOUT20_MODE_S))
-#define LCD_CAM_DOUT20_MODE_V  0x3
-#define LCD_CAM_DOUT20_MODE_S  8
-/* LCD_CAM_DOUT19_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT19_MODE    0x00000003
-#define LCD_CAM_DOUT19_MODE_M  ((LCD_CAM_DOUT19_MODE_V)<<(LCD_CAM_DOUT19_MODE_S))
-#define LCD_CAM_DOUT19_MODE_V  0x3
-#define LCD_CAM_DOUT19_MODE_S  6
-/* LCD_CAM_DOUT18_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT18_MODE    0x00000003
-#define LCD_CAM_DOUT18_MODE_M  ((LCD_CAM_DOUT18_MODE_V)<<(LCD_CAM_DOUT18_MODE_S))
-#define LCD_CAM_DOUT18_MODE_V  0x3
-#define LCD_CAM_DOUT18_MODE_S  4
-/* LCD_CAM_DOUT17_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT17_MODE    0x00000003
-#define LCD_CAM_DOUT17_MODE_M  ((LCD_CAM_DOUT17_MODE_V)<<(LCD_CAM_DOUT17_MODE_S))
-#define LCD_CAM_DOUT17_MODE_V  0x3
-#define LCD_CAM_DOUT17_MODE_S  2
-/* LCD_CAM_DOUT16_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT16_MODE    0x00000003
-#define LCD_CAM_DOUT16_MODE_M  ((LCD_CAM_DOUT16_MODE_V)<<(LCD_CAM_DOUT16_MODE_S))
-#define LCD_CAM_DOUT16_MODE_V  0x3
-#define LCD_CAM_DOUT16_MODE_S  0
+/** LCDCAM_LCD_DLY_MODE_CFG1_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCDCAM_BASE + 0x30)
+/** LCDCAM_DOUT16_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT16_MODE    0x00000003U
+#define LCDCAM_DOUT16_MODE_M  (LCDCAM_DOUT16_MODE_V << LCDCAM_DOUT16_MODE_S)
+#define LCDCAM_DOUT16_MODE_V  0x00000003U
+#define LCDCAM_DOUT16_MODE_S  0
+/** LCDCAM_DOUT17_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT17_MODE    0x00000003U
+#define LCDCAM_DOUT17_MODE_M  (LCDCAM_DOUT17_MODE_V << LCDCAM_DOUT17_MODE_S)
+#define LCDCAM_DOUT17_MODE_V  0x00000003U
+#define LCDCAM_DOUT17_MODE_S  2
+/** LCDCAM_DOUT18_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT18_MODE    0x00000003U
+#define LCDCAM_DOUT18_MODE_M  (LCDCAM_DOUT18_MODE_V << LCDCAM_DOUT18_MODE_S)
+#define LCDCAM_DOUT18_MODE_V  0x00000003U
+#define LCDCAM_DOUT18_MODE_S  4
+/** LCDCAM_DOUT19_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT19_MODE    0x00000003U
+#define LCDCAM_DOUT19_MODE_M  (LCDCAM_DOUT19_MODE_V << LCDCAM_DOUT19_MODE_S)
+#define LCDCAM_DOUT19_MODE_V  0x00000003U
+#define LCDCAM_DOUT19_MODE_S  6
+/** LCDCAM_DOUT20_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT20_MODE    0x00000003U
+#define LCDCAM_DOUT20_MODE_M  (LCDCAM_DOUT20_MODE_V << LCDCAM_DOUT20_MODE_S)
+#define LCDCAM_DOUT20_MODE_V  0x00000003U
+#define LCDCAM_DOUT20_MODE_S  8
+/** LCDCAM_DOUT21_MODE : R/W; bitpos: [11:10]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT21_MODE    0x00000003U
+#define LCDCAM_DOUT21_MODE_M  (LCDCAM_DOUT21_MODE_V << LCDCAM_DOUT21_MODE_S)
+#define LCDCAM_DOUT21_MODE_V  0x00000003U
+#define LCDCAM_DOUT21_MODE_S  10
+/** LCDCAM_DOUT22_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT22_MODE    0x00000003U
+#define LCDCAM_DOUT22_MODE_M  (LCDCAM_DOUT22_MODE_V << LCDCAM_DOUT22_MODE_S)
+#define LCDCAM_DOUT22_MODE_V  0x00000003U
+#define LCDCAM_DOUT22_MODE_S  12
+/** LCDCAM_DOUT23_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT23_MODE    0x00000003U
+#define LCDCAM_DOUT23_MODE_M  (LCDCAM_DOUT23_MODE_V << LCDCAM_DOUT23_MODE_S)
+#define LCDCAM_DOUT23_MODE_V  0x00000003U
+#define LCDCAM_DOUT23_MODE_S  14
+/** LCDCAM_LCD_CD_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+ *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_CD_MODE    0x00000003U
+#define LCDCAM_LCD_CD_MODE_M  (LCDCAM_LCD_CD_MODE_V << LCDCAM_LCD_CD_MODE_S)
+#define LCDCAM_LCD_CD_MODE_V  0x00000003U
+#define LCDCAM_LCD_CD_MODE_S  16
+/** LCDCAM_LCD_DE_MODE : R/W; bitpos: [19:18]; default: 0;
+ *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+ *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_DE_MODE    0x00000003U
+#define LCDCAM_LCD_DE_MODE_M  (LCDCAM_LCD_DE_MODE_V << LCDCAM_LCD_DE_MODE_S)
+#define LCDCAM_LCD_DE_MODE_V  0x00000003U
+#define LCDCAM_LCD_DE_MODE_S  18
+/** LCDCAM_LCD_HSYNC_MODE : R/W; bitpos: [21:20]; default: 0;
+ *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+ *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_HSYNC_MODE    0x00000003U
+#define LCDCAM_LCD_HSYNC_MODE_M  (LCDCAM_LCD_HSYNC_MODE_V << LCDCAM_LCD_HSYNC_MODE_S)
+#define LCDCAM_LCD_HSYNC_MODE_V  0x00000003U
+#define LCDCAM_LCD_HSYNC_MODE_S  20
+/** LCDCAM_LCD_VSYNC_MODE : R/W; bitpos: [23:22]; default: 0;
+ *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+ *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_VSYNC_MODE    0x00000003U
+#define LCDCAM_LCD_VSYNC_MODE_M  (LCDCAM_LCD_VSYNC_MODE_V << LCDCAM_LCD_VSYNC_MODE_S)
+#define LCDCAM_LCD_VSYNC_MODE_V  0x00000003U
+#define LCDCAM_LCD_VSYNC_MODE_S  22
 
-#define LCD_CAM_LCD_DLY_MODE_CFG2_REG          (DR_REG_LCD_CAM_BASE + 0x38)
-/* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT15_MODE    0x00000003
-#define LCD_CAM_DOUT15_MODE_M  ((LCD_CAM_DOUT15_MODE_V)<<(LCD_CAM_DOUT15_MODE_S))
-#define LCD_CAM_DOUT15_MODE_V  0x3
-#define LCD_CAM_DOUT15_MODE_S  30
-/* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT14_MODE    0x00000003
-#define LCD_CAM_DOUT14_MODE_M  ((LCD_CAM_DOUT14_MODE_V)<<(LCD_CAM_DOUT14_MODE_S))
-#define LCD_CAM_DOUT14_MODE_V  0x3
-#define LCD_CAM_DOUT14_MODE_S  28
-/* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT13_MODE    0x00000003
-#define LCD_CAM_DOUT13_MODE_M  ((LCD_CAM_DOUT13_MODE_V)<<(LCD_CAM_DOUT13_MODE_S))
-#define LCD_CAM_DOUT13_MODE_V  0x3
-#define LCD_CAM_DOUT13_MODE_S  26
-/* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT12_MODE    0x00000003
-#define LCD_CAM_DOUT12_MODE_M  ((LCD_CAM_DOUT12_MODE_V)<<(LCD_CAM_DOUT12_MODE_S))
-#define LCD_CAM_DOUT12_MODE_V  0x3
-#define LCD_CAM_DOUT12_MODE_S  24
-/* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT11_MODE    0x00000003
-#define LCD_CAM_DOUT11_MODE_M  ((LCD_CAM_DOUT11_MODE_V)<<(LCD_CAM_DOUT11_MODE_S))
-#define LCD_CAM_DOUT11_MODE_V  0x3
-#define LCD_CAM_DOUT11_MODE_S  22
-/* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT10_MODE    0x00000003
-#define LCD_CAM_DOUT10_MODE_M  ((LCD_CAM_DOUT10_MODE_V)<<(LCD_CAM_DOUT10_MODE_S))
-#define LCD_CAM_DOUT10_MODE_V  0x3
-#define LCD_CAM_DOUT10_MODE_S  20
-/* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT9_MODE    0x00000003
-#define LCD_CAM_DOUT9_MODE_M  ((LCD_CAM_DOUT9_MODE_V)<<(LCD_CAM_DOUT9_MODE_S))
-#define LCD_CAM_DOUT9_MODE_V  0x3
-#define LCD_CAM_DOUT9_MODE_S  18
-/* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT8_MODE    0x00000003
-#define LCD_CAM_DOUT8_MODE_M  ((LCD_CAM_DOUT8_MODE_V)<<(LCD_CAM_DOUT8_MODE_S))
-#define LCD_CAM_DOUT8_MODE_V  0x3
-#define LCD_CAM_DOUT8_MODE_S  16
-/* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT7_MODE    0x00000003
-#define LCD_CAM_DOUT7_MODE_M  ((LCD_CAM_DOUT7_MODE_V)<<(LCD_CAM_DOUT7_MODE_S))
-#define LCD_CAM_DOUT7_MODE_V  0x3
-#define LCD_CAM_DOUT7_MODE_S  14
-/* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT6_MODE    0x00000003
-#define LCD_CAM_DOUT6_MODE_M  ((LCD_CAM_DOUT6_MODE_V)<<(LCD_CAM_DOUT6_MODE_S))
-#define LCD_CAM_DOUT6_MODE_V  0x3
-#define LCD_CAM_DOUT6_MODE_S  12
-/* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT5_MODE    0x00000003
-#define LCD_CAM_DOUT5_MODE_M  ((LCD_CAM_DOUT5_MODE_V)<<(LCD_CAM_DOUT5_MODE_S))
-#define LCD_CAM_DOUT5_MODE_V  0x3
-#define LCD_CAM_DOUT5_MODE_S  10
-/* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT4_MODE    0x00000003
-#define LCD_CAM_DOUT4_MODE_M  ((LCD_CAM_DOUT4_MODE_V)<<(LCD_CAM_DOUT4_MODE_S))
-#define LCD_CAM_DOUT4_MODE_V  0x3
-#define LCD_CAM_DOUT4_MODE_S  8
-/* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT3_MODE    0x00000003
-#define LCD_CAM_DOUT3_MODE_M  ((LCD_CAM_DOUT3_MODE_V)<<(LCD_CAM_DOUT3_MODE_S))
-#define LCD_CAM_DOUT3_MODE_V  0x3
-#define LCD_CAM_DOUT3_MODE_S  6
-/* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT2_MODE    0x00000003
-#define LCD_CAM_DOUT2_MODE_M  ((LCD_CAM_DOUT2_MODE_V)<<(LCD_CAM_DOUT2_MODE_S))
-#define LCD_CAM_DOUT2_MODE_V  0x3
-#define LCD_CAM_DOUT2_MODE_S  4
-/* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT1_MODE    0x00000003
-#define LCD_CAM_DOUT1_MODE_M  ((LCD_CAM_DOUT1_MODE_V)<<(LCD_CAM_DOUT1_MODE_S))
-#define LCD_CAM_DOUT1_MODE_V  0x3
-#define LCD_CAM_DOUT1_MODE_S  2
-/* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
-ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- LCD_CLK..*/
-#define LCD_CAM_DOUT0_MODE    0x00000003
-#define LCD_CAM_DOUT0_MODE_M  ((LCD_CAM_DOUT0_MODE_V)<<(LCD_CAM_DOUT0_MODE_S))
-#define LCD_CAM_DOUT0_MODE_V  0x3
-#define LCD_CAM_DOUT0_MODE_S  0
+/** LCDCAM_LCD_DLY_MODE_CFG2_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCDCAM_BASE + 0x38)
+/** LCDCAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT0_MODE    0x00000003U
+#define LCDCAM_DOUT0_MODE_M  (LCDCAM_DOUT0_MODE_V << LCDCAM_DOUT0_MODE_S)
+#define LCDCAM_DOUT0_MODE_V  0x00000003U
+#define LCDCAM_DOUT0_MODE_S  0
+/** LCDCAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT1_MODE    0x00000003U
+#define LCDCAM_DOUT1_MODE_M  (LCDCAM_DOUT1_MODE_V << LCDCAM_DOUT1_MODE_S)
+#define LCDCAM_DOUT1_MODE_V  0x00000003U
+#define LCDCAM_DOUT1_MODE_S  2
+/** LCDCAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT2_MODE    0x00000003U
+#define LCDCAM_DOUT2_MODE_M  (LCDCAM_DOUT2_MODE_V << LCDCAM_DOUT2_MODE_S)
+#define LCDCAM_DOUT2_MODE_V  0x00000003U
+#define LCDCAM_DOUT2_MODE_S  4
+/** LCDCAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT3_MODE    0x00000003U
+#define LCDCAM_DOUT3_MODE_M  (LCDCAM_DOUT3_MODE_V << LCDCAM_DOUT3_MODE_S)
+#define LCDCAM_DOUT3_MODE_V  0x00000003U
+#define LCDCAM_DOUT3_MODE_S  6
+/** LCDCAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT4_MODE    0x00000003U
+#define LCDCAM_DOUT4_MODE_M  (LCDCAM_DOUT4_MODE_V << LCDCAM_DOUT4_MODE_S)
+#define LCDCAM_DOUT4_MODE_V  0x00000003U
+#define LCDCAM_DOUT4_MODE_S  8
+/** LCDCAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT5_MODE    0x00000003U
+#define LCDCAM_DOUT5_MODE_M  (LCDCAM_DOUT5_MODE_V << LCDCAM_DOUT5_MODE_S)
+#define LCDCAM_DOUT5_MODE_V  0x00000003U
+#define LCDCAM_DOUT5_MODE_S  10
+/** LCDCAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT6_MODE    0x00000003U
+#define LCDCAM_DOUT6_MODE_M  (LCDCAM_DOUT6_MODE_V << LCDCAM_DOUT6_MODE_S)
+#define LCDCAM_DOUT6_MODE_V  0x00000003U
+#define LCDCAM_DOUT6_MODE_S  12
+/** LCDCAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT7_MODE    0x00000003U
+#define LCDCAM_DOUT7_MODE_M  (LCDCAM_DOUT7_MODE_V << LCDCAM_DOUT7_MODE_S)
+#define LCDCAM_DOUT7_MODE_V  0x00000003U
+#define LCDCAM_DOUT7_MODE_S  14
+/** LCDCAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT8_MODE    0x00000003U
+#define LCDCAM_DOUT8_MODE_M  (LCDCAM_DOUT8_MODE_V << LCDCAM_DOUT8_MODE_S)
+#define LCDCAM_DOUT8_MODE_V  0x00000003U
+#define LCDCAM_DOUT8_MODE_S  16
+/** LCDCAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT9_MODE    0x00000003U
+#define LCDCAM_DOUT9_MODE_M  (LCDCAM_DOUT9_MODE_V << LCDCAM_DOUT9_MODE_S)
+#define LCDCAM_DOUT9_MODE_V  0x00000003U
+#define LCDCAM_DOUT9_MODE_S  18
+/** LCDCAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT10_MODE    0x00000003U
+#define LCDCAM_DOUT10_MODE_M  (LCDCAM_DOUT10_MODE_V << LCDCAM_DOUT10_MODE_S)
+#define LCDCAM_DOUT10_MODE_V  0x00000003U
+#define LCDCAM_DOUT10_MODE_S  20
+/** LCDCAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT11_MODE    0x00000003U
+#define LCDCAM_DOUT11_MODE_M  (LCDCAM_DOUT11_MODE_V << LCDCAM_DOUT11_MODE_S)
+#define LCDCAM_DOUT11_MODE_V  0x00000003U
+#define LCDCAM_DOUT11_MODE_S  22
+/** LCDCAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT12_MODE    0x00000003U
+#define LCDCAM_DOUT12_MODE_M  (LCDCAM_DOUT12_MODE_V << LCDCAM_DOUT12_MODE_S)
+#define LCDCAM_DOUT12_MODE_V  0x00000003U
+#define LCDCAM_DOUT12_MODE_S  24
+/** LCDCAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT13_MODE    0x00000003U
+#define LCDCAM_DOUT13_MODE_M  (LCDCAM_DOUT13_MODE_V << LCDCAM_DOUT13_MODE_S)
+#define LCDCAM_DOUT13_MODE_V  0x00000003U
+#define LCDCAM_DOUT13_MODE_S  26
+/** LCDCAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT14_MODE    0x00000003U
+#define LCDCAM_DOUT14_MODE_M  (LCDCAM_DOUT14_MODE_V << LCDCAM_DOUT14_MODE_S)
+#define LCDCAM_DOUT14_MODE_V  0x00000003U
+#define LCDCAM_DOUT14_MODE_S  28
+/** LCDCAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT15_MODE    0x00000003U
+#define LCDCAM_DOUT15_MODE_M  (LCDCAM_DOUT15_MODE_V << LCDCAM_DOUT15_MODE_S)
+#define LCDCAM_DOUT15_MODE_V  0x00000003U
+#define LCDCAM_DOUT15_MODE_S  30
 
-#define LCD_CAM_LC_DMA_INT_ENA_REG          (DR_REG_LCD_CAM_BASE + 0x64)
-/* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for Camera line interrupt..*/
-#define LCD_CAM_CAM_HS_INT_ENA    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ENA_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ENA_V  0x1
-#define LCD_CAM_CAM_HS_INT_ENA_S  3
-/* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_ENA    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ENA_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ENA_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_ENA_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S  1
-/* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for LCD frame end interrupt..*/
-#define LCD_CAM_LCD_VSYNC_INT_ENA    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ENA_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ENA_V  0x1
-#define LCD_CAM_LCD_VSYNC_INT_ENA_S  0
+/** LCDCAM_LC_DMA_INT_ENA_REG register
+ *  LCDCAM interrupt enable register.
+ */
+#define LCDCAM_LC_DMA_INT_ENA_REG (DR_REG_LCDCAM_BASE + 0x64)
+/** LCDCAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_ENA    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_ENA_M  (LCDCAM_LCD_VSYNC_INT_ENA_V << LCDCAM_LCD_VSYNC_INT_ENA_S)
+#define LCDCAM_LCD_VSYNC_INT_ENA_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_ENA_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA_M  (LCDCAM_LCD_TRANS_DONE_INT_ENA_V << LCDCAM_LCD_TRANS_DONE_INT_ENA_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA_S  1
+/** LCDCAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_ENA    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_ENA_M  (LCDCAM_CAM_VSYNC_INT_ENA_V << LCDCAM_CAM_VSYNC_INT_ENA_S)
+#define LCDCAM_CAM_VSYNC_INT_ENA_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_ENA_S  2
+/** LCDCAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for Camera line interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_ENA    (BIT(3))
+#define LCDCAM_CAM_HS_INT_ENA_M  (LCDCAM_CAM_HS_INT_ENA_V << LCDCAM_CAM_HS_INT_ENA_S)
+#define LCDCAM_CAM_HS_INT_ENA_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_ENA_S  3
 
-#define LCD_CAM_LC_DMA_INT_RAW_REG          (DR_REG_LCD_CAM_BASE + 0x68)
-/* LCD_CAM_CAM_HS_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for Camera line interrupt..*/
-#define LCD_CAM_CAM_HS_INT_RAW    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_RAW_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_RAW_V  0x1
-#define LCD_CAM_CAM_HS_INT_RAW_S  3
-/* LCD_CAM_CAM_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_RAW    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_RAW_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_RAW_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_RAW_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S  1
-/* LCD_CAM_LCD_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for LCD frame end interrupt..*/
-#define LCD_CAM_LCD_VSYNC_INT_RAW    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_RAW_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_RAW_V  0x1
-#define LCD_CAM_LCD_VSYNC_INT_RAW_S  0
+/** LCDCAM_LC_DMA_INT_RAW_REG register
+ *  LCDCAM interrupt raw register, valid in level.
+ */
+#define LCDCAM_LC_DMA_INT_RAW_REG (DR_REG_LCDCAM_BASE + 0x68)
+/** LCDCAM_LCD_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_RAW    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_RAW_M  (LCDCAM_LCD_VSYNC_INT_RAW_V << LCDCAM_LCD_VSYNC_INT_RAW_S)
+#define LCDCAM_LCD_VSYNC_INT_RAW_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_RAW_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW_M  (LCDCAM_LCD_TRANS_DONE_INT_RAW_V << LCDCAM_LCD_TRANS_DONE_INT_RAW_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW_S  1
+/** LCDCAM_CAM_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_RAW    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_RAW_M  (LCDCAM_CAM_VSYNC_INT_RAW_V << LCDCAM_CAM_VSYNC_INT_RAW_S)
+#define LCDCAM_CAM_VSYNC_INT_RAW_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_RAW_S  2
+/** LCDCAM_CAM_HS_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for Camera line interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_RAW    (BIT(3))
+#define LCDCAM_CAM_HS_INT_RAW_M  (LCDCAM_CAM_HS_INT_RAW_V << LCDCAM_CAM_HS_INT_RAW_S)
+#define LCDCAM_CAM_HS_INT_RAW_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_RAW_S  3
 
-#define LCD_CAM_LC_DMA_INT_ST_REG          (DR_REG_LCD_CAM_BASE + 0x6C)
-/* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for Camera transfer end interrupt..*/
-#define LCD_CAM_CAM_HS_INT_ST    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ST_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ST_V  0x1
-#define LCD_CAM_CAM_HS_INT_ST_S  3
-/* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_ST    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ST_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ST_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_ST_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S  1
-/* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for LCD frame end interrupt..*/
-#define LCD_CAM_LCD_VSYNC_INT_ST    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ST_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ST_V  0x1
-#define LCD_CAM_LCD_VSYNC_INT_ST_S  0
+/** LCDCAM_LC_DMA_INT_ST_REG register
+ *  LCDCAM interrupt status register.
+ */
+#define LCDCAM_LC_DMA_INT_ST_REG (DR_REG_LCDCAM_BASE + 0x6c)
+/** LCDCAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_ST    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_ST_M  (LCDCAM_LCD_VSYNC_INT_ST_V << LCDCAM_LCD_VSYNC_INT_ST_S)
+#define LCDCAM_LCD_VSYNC_INT_ST_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_ST_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_ST    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_ST_M  (LCDCAM_LCD_TRANS_DONE_INT_ST_V << LCDCAM_LCD_TRANS_DONE_INT_ST_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_ST_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_ST_S  1
+/** LCDCAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_ST    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_ST_M  (LCDCAM_CAM_VSYNC_INT_ST_V << LCDCAM_CAM_VSYNC_INT_ST_S)
+#define LCDCAM_CAM_VSYNC_INT_ST_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_ST_S  2
+/** LCDCAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for Camera transfer end interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_ST    (BIT(3))
+#define LCDCAM_CAM_HS_INT_ST_M  (LCDCAM_CAM_HS_INT_ST_V << LCDCAM_CAM_HS_INT_ST_S)
+#define LCDCAM_CAM_HS_INT_ST_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_ST_S  3
 
-#define LCD_CAM_LC_DMA_INT_CLR_REG          (DR_REG_LCD_CAM_BASE + 0x70)
-/* LCD_CAM_CAM_HS_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for Camera line interrupt..*/
-#define LCD_CAM_CAM_HS_INT_CLR    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_CLR_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_CLR_V  0x1
-#define LCD_CAM_CAM_HS_INT_CLR_S  3
-/* LCD_CAM_CAM_VSYNC_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_CLR    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_CLR_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_CLR_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_CLR_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S  1
-/* LCD_CAM_LCD_VSYNC_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for LCD frame end interrupt..*/
-#define LCD_CAM_LCD_VSYNC_INT_CLR    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_CLR_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_CLR_V  0x1
-#define LCD_CAM_LCD_VSYNC_INT_CLR_S  0
-
-#define LCD_CAM_LC_REG_DATE_REG          (DR_REG_LCD_CAM_BASE + 0xFC)
-/* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2303090 ; */
-/*description: LCD_CAM version control register.*/
-#define LCD_CAM_LC_DATE    0x0FFFFFFF
-#define LCD_CAM_LC_DATE_M  ((LCD_CAM_LC_DATE_V)<<(LCD_CAM_LC_DATE_S))
-#define LCD_CAM_LC_DATE_V  0xFFFFFFF
-#define LCD_CAM_LC_DATE_S  0
+/** LCDCAM_LC_DMA_INT_CLR_REG register
+ *  LCDCAM interrupt clear register.
+ */
+#define LCDCAM_LC_DMA_INT_CLR_REG (DR_REG_LCDCAM_BASE + 0x70)
+/** LCDCAM_LCD_VSYNC_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_CLR    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_CLR_M  (LCDCAM_LCD_VSYNC_INT_CLR_V << LCDCAM_LCD_VSYNC_INT_CLR_S)
+#define LCDCAM_LCD_VSYNC_INT_CLR_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_CLR_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR_M  (LCDCAM_LCD_TRANS_DONE_INT_CLR_V << LCDCAM_LCD_TRANS_DONE_INT_CLR_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR_S  1
+/** LCDCAM_CAM_VSYNC_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_CLR    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_CLR_M  (LCDCAM_CAM_VSYNC_INT_CLR_V << LCDCAM_CAM_VSYNC_INT_CLR_S)
+#define LCDCAM_CAM_VSYNC_INT_CLR_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_CLR_S  2
+/** LCDCAM_CAM_HS_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for Camera line interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_CLR    (BIT(3))
+#define LCDCAM_CAM_HS_INT_CLR_M  (LCDCAM_CAM_HS_INT_CLR_V << LCDCAM_CAM_HS_INT_CLR_S)
+#define LCDCAM_CAM_HS_INT_CLR_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_CLR_S  3
 
+/** LCDCAM_LC_REG_DATE_REG register
+ *  Version register
+ */
+#define LCDCAM_LC_REG_DATE_REG (DR_REG_LCDCAM_BASE + 0xfc)
+/** LCDCAM_LC_DATE : R/W; bitpos: [27:0]; default: 36712592;
+ *  LCD_CAM version control register
+ */
+#define LCDCAM_LC_DATE    0x0FFFFFFFU
+#define LCDCAM_LC_DATE_M  (LCDCAM_LC_DATE_V << LCDCAM_LC_DATE_S)
+#define LCDCAM_LC_DATE_V  0x0FFFFFFFU
+#define LCDCAM_LC_DATE_S  0
 
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_LCD_CAM_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/lcd_cam_struct.h b/components/soc/esp32p4/include/soc/lcd_cam_struct.h
index ed787f0761..2ce7658d43 100644
--- a/components/soc/esp32p4/include/soc/lcd_cam_struct.h
+++ b/components/soc/esp32p4/include/soc/lcd_cam_struct.h
@@ -1,303 +1,855 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_LCD_CAM_STRUCT_H_
-#define _SOC_LCD_CAM_STRUCT_H_
-
+#pragma once
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t lcd_clkcnt_n                  :    6;  /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
-            uint32_t lcd_clk_equ_sysclk            :    1;  /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
-            uint32_t lcd_ck_idle_edge              :    1;  /*1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle. */
-            uint32_t lcd_ck_out_edge               :    1;  /*1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low in the second half data cycle. */
-            uint32_t lcd_clkm_div_num              :    8;  /*Integral LCD clock divider value*/
-            uint32_t lcd_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
-            uint32_t lcd_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
-            uint32_t lcd_clk_sel                   :    2;  /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
-            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
-        };
-        uint32_t val;
-    } lcd_clock;
-    union {
-        struct {
-            uint32_t cam_stop_en                   :    1;  /*Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/
-            uint32_t cam_vsync_filter_thres        :    3;  /*Filter threshold value for CAM_VSYNC signal.*/
-            uint32_t cam_update                    :    1;  /*1: Update Camera registers, will be cleared by hardware. 0 : Not care.*/
-            uint32_t cam_byte_order                :    1;  /*1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
-            uint32_t cam_bit_order                 :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
-            uint32_t cam_line_int_en               :    1;  /*1: Enable to generate CAM_HS_INT. 0: Disable.*/
-            uint32_t cam_vs_eof_en                 :    1;  /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/
-            uint32_t cam_clkm_div_num              :    8;  /*Integral Camera clock divider value*/
-            uint32_t cam_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
-            uint32_t cam_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
-            uint32_t cam_clk_sel                   :    2;  /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } cam_ctrl;
-    union {
-        struct {
-            uint32_t cam_rec_data_bytelen          :    16;  /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
-            uint32_t cam_line_int_num              :    6;  /*The line number minus 1 to generate cam_hs_int.*/
-            uint32_t cam_clk_inv                   :    1;  /*1: Invert  the input signal CAM_PCLK. 0: Not invert.*/
-            uint32_t cam_vsync_filter_en           :    1;  /*1: Enable CAM_VSYNC filter function. 0: bypass.*/
-            uint32_t cam_2byte_en                  :    1;  /*1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8. */
-            uint32_t cam_de_inv                    :    1;  /*CAM_DE invert enable signal, valid in high level.*/
-            uint32_t cam_hsync_inv                 :    1;  /*CAM_HSYNC invert enable signal, valid in high level.*/
-            uint32_t cam_vsync_inv                 :    1;  /*CAM_VSYNC invert enable signal, valid in high level.*/
-            uint32_t cam_vh_de_mode_en             :    1;  /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC.*/
-            uint32_t cam_start                     :    1;  /*Camera module start signal.*/
-            uint32_t cam_reset                     :    1;  /*Camera module reset signal.*/
-            uint32_t cam_afifo_reset               :    1;  /*Camera AFIFO reset signal.*/
-        };
-        uint32_t val;
-    } cam_ctrl1;
-    union {
-        struct {
-            uint32_t reserved0                     :    21;  /*reserved*/
-            uint32_t cam_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
-            uint32_t cam_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
-            uint32_t cam_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
-            uint32_t cam_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
-            uint32_t cam_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
-            uint32_t cam_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
-            uint32_t cam_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
-            uint32_t cam_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
-            uint32_t cam_conv_enable               :    1;  /*0: Bypass converter. 1: Enable converter.*/
-        };
-        uint32_t val;
-    } cam_rgb_yuv;
-    union {
-        struct {
-            uint32_t reserved0                     :    20;  /*reserved*/
-            uint32_t lcd_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
-            uint32_t lcd_conv_txtorx               :    1;  /*0: txtorx mode off. 1: txtorx mode on.*/
-            uint32_t lcd_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
-            uint32_t lcd_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
-            uint32_t lcd_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
-            uint32_t lcd_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
-            uint32_t lcd_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
-            uint32_t lcd_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
-            uint32_t lcd_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
-            uint32_t lcd_conv_enable               :    1;  /*0: Bypass converter. 1: Enable converter.*/
-        };
-        uint32_t val;
-    } lcd_rgb_yuv;
-    union {
-        struct {
-            uint32_t lcd_dout_cyclelen             :    13;  /*The output data cycles minus 1 of LCD module.*/
-            uint32_t lcd_always_out_en             :    1;  /*LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set.*/
-            uint32_t lcd_dout_byte_swizzle_mode    :    3;  /*0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA*/
-            uint32_t lcd_dout_byte_swizzle_enable  :    1;  /*1: enable byte swizzle 0: disable*/
-            uint32_t lcd_dout_bit_order            :    1;  /*1: change bit order in every byte. 0: Not change.*/
-            uint32_t lcd_byte_mode                 :    2;  /*2: 24bit mode. 1: 16bit mode. 0: 8bit mode*/
-            uint32_t lcd_update                    :    1;  /*1: Update LCD registers, will be cleared by hardware. 0 : Not care.*/
-            uint32_t lcd_bit_order                 :    1;  /*1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
-            uint32_t lcd_byte_order                :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
-            uint32_t lcd_dout                      :    1;  /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_dummy                     :    1;  /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_cmd                       :    1;  /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_start                     :    1;  /*LCD start sending data enable signal, valid in high level.*/
-            uint32_t lcd_reset                     :    1;  /*The value of  command. */
-            uint32_t lcd_dummy_cyclelen            :    2;  /*The dummy cycle length minus 1.*/
-            uint32_t lcd_cmd_2_cycle_en            :    1;  /*The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */
-        };
-        uint32_t val;
-    } lcd_user;
-    union {
-        struct {
-            uint32_t reserved0                     :    4;  /*reserved*/
-            uint32_t lcd_wire_mode                 :    2;  /*The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit*/
-            uint32_t lcd_vfk_cyclelen              :    6;  /*The setup cycle length minus 1 in LCD non-RGB mode.*/
-            uint32_t lcd_vbk_cyclelen              :    13;  /*The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode.*/
-            uint32_t lcd_next_frame_en             :    1;  /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/
-            uint32_t lcd_bk_en                     :    1;  /*1: Enable blank region when LCD sends data out. 0: No blank region.*/
-            uint32_t lcd_afifo_reset               :    1;  /*LCD AFIFO reset signal.*/
-            uint32_t lcd_cd_data_set               :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD = reg_cd_idle_edge. */
-            uint32_t lcd_cd_dummy_set              :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD = reg_cd_idle_edge. */
-            uint32_t lcd_cd_cmd_set                :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD = reg_cd_idle_edge. */
-            uint32_t lcd_cd_idle_edge              :    1;  /*The default value of LCD_CD. */
-        };
-        uint32_t val;
-    } lcd_misc;
-    union {
-        struct {
-            uint32_t lcd_hb_front                  :    11;  /*It is the horizontal blank front porch of a frame. */
-            uint32_t lcd_va_height                 :    10;  /*It is the vertical active height of a frame. */
-            uint32_t lcd_vt_height                 :    10;  /*It is the vertical total height of a frame. */
-            uint32_t lcd_rgb_mode_en               :    1;  /*1: Enable LCD RGB mode. 0: Disable LCD RGB mode.*/
-        };
-        uint32_t val;
-    } lcd_ctrl;
-    union {
-        struct {
-            uint32_t lcd_vb_front                  :    8;  /*It is the vertical blank front porch of a frame. */
-            uint32_t lcd_ha_width                  :    12;  /*It is the horizontal active width of a frame. */
-            uint32_t lcd_ht_width                  :    12;  /*It is the horizontal total width of a frame. */
-        };
-        uint32_t val;
-    } lcd_ctrl1;
-    union {
-        struct {
-            uint32_t lcd_vsync_width               :    7;  /*It is the position of LCD_VSYNC active pulse in a line. */
-            uint32_t lcd_vsync_idle_pol            :    1;  /*It is the idle value of LCD_VSYNC. */
-            uint32_t lcd_de_idle_pol               :    1;  /*It is the idle value of LCD_DE. */
-            uint32_t lcd_hs_blank_en               :    1;  /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. */
-            uint32_t reserved10                    :    6;  /*reserved*/
-            uint32_t lcd_hsync_width               :    7;  /*It is the position of LCD_HSYNC active pulse in a line. */
-            uint32_t lcd_hsync_idle_pol            :    1;  /*It is the idle value of LCD_HSYNC. */
-            uint32_t lcd_hsync_position            :    8;  /*It is the position of LCD_HSYNC active pulse in a line. */
-        };
-        uint32_t val;
-    } lcd_ctrl2;
-    uint32_t lcd_first_cmd_val;
-    uint32_t lcd_latter_cmd_val;
-    union {
-        struct {
-            uint32_t dout16_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout17_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout18_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout19_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout20_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout21_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout22_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout23_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t lcd_cd_mode                   :    2;  /*The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t lcd_de_mode                   :    2;  /*The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t lcd_hsync_mode                :    2;  /*The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t lcd_vsync_mode                :    2;  /*The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } lcd_dly_mode_cfg1;
-    uint32_t reserved_34;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout1_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout2_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout3_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout4_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout5_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout6_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout7_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout8_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout9_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout10_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout11_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout12_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout13_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout14_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-            uint32_t dout15_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
-        };
-        uint32_t val;
-    } lcd_dly_mode_cfg2;
-    uint32_t reserved_3c;
-    uint32_t reserved_40;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The enable bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The enable bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The enable bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The enable bit for Camera line interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_ena;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The raw bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The raw bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The raw bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The raw bit for Camera line interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_raw;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The status bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The status bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The status bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The status bit for Camera transfer end interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_st;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The clear bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The clear bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The clear bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The clear bit for Camera line interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_clr;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*LCD_CAM version control register*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} lcd_cam_dev_t;
-extern lcd_cam_dev_t LCD_CAM;
+/** Group: lcd configuration registers */
+/** Type of lcd_clock register
+ *  LCD clock config register.
+ */
+typedef union {
+    struct {
+        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
+         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+         */
+        uint32_t lcd_clkcnt_n:6;
+        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
+         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+         */
+        uint32_t lcd_clk_equ_sysclk:1;
+        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
+         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+         */
+        uint32_t lcd_ck_idle_edge:1;
+        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
+         *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
+         *  in the second half data cycle.
+         */
+        uint32_t lcd_ck_out_edge:1;
+        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral LCD clock divider value
+         */
+        uint32_t lcd_clkm_div_num:8;
+        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t lcd_clkm_div_b:6;
+        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t lcd_clkm_div_a:6;
+        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t lcd_clk_sel:2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_clock_reg_t;
+
+/** Type of lcd_rgb_yuv register
+ *  LCD YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t lcd_conv_8bits_data_inv:1;
+        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
+         *  0: txtorx mode off. 1: txtorx mode on.
+         */
+        uint32_t lcd_conv_txtorx:1;
+        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t lcd_conv_yuv2yuv_mode:2;
+        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t lcd_conv_yuv_mode:2;
+        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t lcd_conv_protocol_mode:1;
+        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_out_mode:1;
+        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_in_mode:1;
+        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t lcd_conv_mode_8bits_on:1;
+        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t lcd_conv_trans_mode:1;
+        /** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t lcd_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_rgb_yuv_reg_t;
+
+/** Type of lcd_user register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
+         *  The output data cycles minus 1 of LCD module.
+         */
+        uint32_t lcd_dout_cyclelen:13;
+        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
+         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+         *  reg_lcd_reset is set.
+         */
+        uint32_t lcd_always_out_en:1;
+        /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
+         *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
+         */
+        uint32_t lcd_dout_byte_swizzle_mode:3;
+        /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
+         *  1: enable byte swizzle 0: disable
+         */
+        uint32_t lcd_dout_byte_swizzle_enable:1;
+        /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
+         *  1: change bit order in every byte. 0: Not change.
+         */
+        uint32_t lcd_dout_bit_order:1;
+        /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
+         *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
+         */
+        uint32_t lcd_byte_mode:2;
+        /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
+         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t lcd_update_reg:1;
+        /** lcd_bit_order : R/W; bitpos: [22]; default: 0;
+         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t lcd_bit_order:1;
+        /** lcd_byte_order : R/W; bitpos: [23]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t lcd_byte_order:1;
+        /** lcd_dout : R/W; bitpos: [24]; default: 0;
+         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dout:1;
+        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
+         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dummy:1;
+        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
+         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_cmd:1;
+        /** lcd_start : R/W/SC; bitpos: [27]; default: 0;
+         *  LCD start sending data enable signal, valid in high level.
+         */
+        uint32_t lcd_start:1;
+        /** lcd_reset : WT; bitpos: [28]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t lcd_reset:1;
+        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
+         *  The dummy cycle length minus 1.
+         */
+        uint32_t lcd_dummy_cyclelen:2;
+        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
+         *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
+         */
+        uint32_t lcd_cmd_2_cycle_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_user_reg_t;
+
+/** Type of lcd_misc register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
+         */
+        uint32_t lcd_wire_mode:2;
+        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
+         *  The setup cycle length minus 1 in LCD non-RGB mode.
+         */
+        uint32_t lcd_vfk_cyclelen:6;
+        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
+         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+         *  time cycle length in LCD non-RGB mode.
+         */
+        uint32_t lcd_vbk_cyclelen:13;
+        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
+         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+         *  the current frame is sent out.
+         */
+        uint32_t lcd_next_frame_en:1;
+        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
+         *  1: Enable blank region when LCD sends data out. 0: No blank region.
+         */
+        uint32_t lcd_bk_en:1;
+        /** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
+         *  LCD AFIFO reset signal.
+         */
+        uint32_t lcd_afifo_reset:1;
+        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_data_set:1;
+        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_dummy_set:1;
+        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_cmd_set:1;
+        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
+         *  The default value of LCD_CD.
+         */
+        uint32_t lcd_cd_idle_edge:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_misc_reg_t;
+
+/** Type of lcd_ctrl register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
+         *  It is the horizontal blank front porch of a frame.
+         */
+        uint32_t lcd_hb_front:11;
+        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
+         *  It is the vertical active height of a frame.
+         */
+        uint32_t lcd_va_height:10;
+        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
+         *  It is the vertical total height of a frame.
+         */
+        uint32_t lcd_vt_height:10;
+        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
+         *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
+         */
+        uint32_t lcd_rgb_mode_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl_reg_t;
+
+/** Type of lcd_ctrl1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
+         *  It is the vertical blank front porch of a frame.
+         */
+        uint32_t lcd_vb_front:8;
+        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
+         *  It is the horizontal active width of a frame.
+         */
+        uint32_t lcd_ha_width:12;
+        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
+         *  It is the horizontal total width of a frame.
+         */
+        uint32_t lcd_ht_width:12;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl1_reg_t;
+
+/** Type of lcd_ctrl2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
+         *  It is the position of LCD_VSYNC active pulse in a line.
+         */
+        uint32_t lcd_vsync_width:7;
+        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
+         *  It is the idle value of LCD_VSYNC.
+         */
+        uint32_t lcd_vsync_idle_pol:1;
+        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
+         *  It is the idle value of LCD_DE.
+         */
+        uint32_t lcd_de_idle_pol:1;
+        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
+         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+         *  pulse is valid only in active region lines in RGB mode.
+         */
+        uint32_t lcd_hs_blank_en:1;
+        uint32_t reserved_10:6;
+        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_width:7;
+        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
+         *  It is the idle value of LCD_HSYNC.
+         */
+        uint32_t lcd_hsync_idle_pol:1;
+        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_position:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl2_reg_t;
+
+/** Type of lcd_first_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of first cmd cycle.
+         */
+        uint32_t lcd_first_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_first_cmd_val_reg_t;
+
+/** Type of lcd_latter_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of latter cmd cycle.
+         */
+        uint32_t lcd_latter_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_latter_cmd_val_reg_t;
+
+/** Type of lcd_dly_mode_cfg1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout16_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout16_mode:2;
+        /** dout17_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout17_mode:2;
+        /** dout18_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout18_mode:2;
+        /** dout19_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout19_mode:2;
+        /** dout20_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout20_mode:2;
+        /** dout21_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout21_mode:2;
+        /** dout22_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout22_mode:2;
+        /** dout23_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout23_mode:2;
+        /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_cd_mode:2;
+        /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_de_mode:2;
+        /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_hsync_mode:2;
+        /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_vsync_mode:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg1_reg_t;
+
+/** Type of lcd_dly_mode_cfg2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout0_mode:2;
+        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout1_mode:2;
+        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout2_mode:2;
+        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout3_mode:2;
+        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout4_mode:2;
+        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout5_mode:2;
+        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout6_mode:2;
+        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout7_mode:2;
+        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout8_mode:2;
+        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout9_mode:2;
+        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout10_mode:2;
+        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout11_mode:2;
+        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout12_mode:2;
+        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout13_mode:2;
+        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout14_mode:2;
+        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout15_mode:2;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg2_reg_t;
+
+
+/** Group: cam configuration registers */
+/** Type of cam_ctrl register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+         */
+        uint32_t cam_stop_en:1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
+         *  Filter threshold value for CAM_VSYNC signal.
+         */
+        uint32_t cam_vsync_filter_thres:3;
+        /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
+         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t cam_update_reg:1;
+        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
+         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t cam_byte_order:1;
+        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t cam_bit_order:1;
+        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable to generate CAM_HS_INT. 0: Disable.
+         */
+        uint32_t cam_line_int_en:1;
+        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
+         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+         *  reg_cam_rec_data_cyclelen.
+         */
+        uint32_t cam_vs_eof_en:1;
+        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral Camera clock divider value
+         */
+        uint32_t cam_clkm_div_num:8;
+        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t cam_clkm_div_b:6;
+        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t cam_clkm_div_a:6;
+        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t cam_clk_sel:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl_reg_t;
+
+/** Type of cam_ctrl1 register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
+         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+         */
+        uint32_t cam_rec_data_bytelen:16;
+        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
+         *  The line number minus 1 to generate cam_hs_int.
+         */
+        uint32_t cam_line_int_num:6;
+        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
+         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+         */
+        uint32_t cam_clk_inv:1;
+        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
+         *  1: Enable CAM_VSYNC filter function. 0: bypass.
+         */
+        uint32_t cam_vsync_filter_en:1;
+        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
+         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+         */
+        uint32_t cam_2byte_en:1;
+        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
+         *  CAM_DE invert enable signal, valid in high level.
+         */
+        uint32_t cam_de_inv:1;
+        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
+         *  CAM_HSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_hsync_inv:1;
+        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
+         *  CAM_VSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_vsync_inv:1;
+        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
+         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
+         *  signals are CAM_DE and CAM_VSYNC.
+         */
+        uint32_t cam_vh_de_mode_en:1;
+        /** cam_start : R/W/SC; bitpos: [29]; default: 0;
+         *  Camera module start signal.
+         */
+        uint32_t cam_start:1;
+        /** cam_reset : WT; bitpos: [30]; default: 0;
+         *  Camera module reset signal.
+         */
+        uint32_t cam_reset:1;
+        /** cam_afifo_reset : WT; bitpos: [31]; default: 0;
+         *  Camera AFIFO reset signal.
+         */
+        uint32_t cam_afifo_reset:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl1_reg_t;
+
+/** Type of cam_rgb_yuv register
+ *  CAM YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t cam_conv_8bits_data_inv:1;
+        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t cam_conv_yuv2yuv_mode:2;
+        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t cam_conv_yuv_mode:2;
+        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t cam_conv_protocol_mode:1;
+        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_out_mode:1;
+        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_in_mode:1;
+        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t cam_conv_mode_8bits_on:1;
+        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t cam_conv_trans_mode:1;
+        /** cam_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t cam_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_cam_rgb_yuv_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of lc_dma_int_ena register
+ *  LCDCAM interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_ena:1;
+        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_ena:1;
+        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_ena:1;
+        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_ena_reg_t;
+
+/** Type of lc_dma_int_raw register
+ *  LCDCAM interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_raw:1;
+        /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_raw:1;
+        /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_raw:1;
+        /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_raw_reg_t;
+
+/** Type of lc_dma_int_st register
+ *  LCDCAM interrupt status register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_st:1;
+        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_st:1;
+        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_st:1;
+        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for Camera transfer end interrupt.
+         */
+        uint32_t cam_hs_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_st_reg_t;
+
+/** Type of lc_dma_int_clr register
+ *  LCDCAM interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_clr:1;
+        /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_clr:1;
+        /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_clr:1;
+        /** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_clr_reg_t;
+
+
+/** Group: Version register */
+/** Type of lc_reg_date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** lc_date : R/W; bitpos: [27:0]; default: 36712592;
+         *  LCD_CAM version control register
+         */
+        uint32_t lc_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lcdcam_lc_reg_date_reg_t;
+
+
+typedef struct lcdcam_dev_t {
+    volatile lcdcam_lcd_clock_reg_t lcd_clock;
+    volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
+    volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
+    volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
+    volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
+    volatile lcdcam_lcd_user_reg_t lcd_user;
+    volatile lcdcam_lcd_misc_reg_t lcd_misc;
+    volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
+    volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
+    volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
+    volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
+    volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
+    volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
+    uint32_t reserved_034;
+    volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
+    uint32_t reserved_03c[10];
+    volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
+    volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
+    volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
+    volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
+    uint32_t reserved_074[34];
+    volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
+} lcdcam_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
+#endif
+
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_LCD_CAM_STRUCT_H_ */
diff --git a/components/soc/esp32p4/include/soc/lcdcam_reg.h b/components/soc/esp32p4/include/soc/lcdcam_reg.h
deleted file mode 100644
index 7a2f8ed19a..0000000000
--- a/components/soc/esp32p4/include/soc/lcdcam_reg.h
+++ /dev/null
@@ -1,1145 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LCDCAM_LCD_CLOCK_REG register
- *  LCD clock config register.
- */
-#define LCDCAM_LCD_CLOCK_REG (DR_REG_LCDCAM_BASE + 0x0)
-/** LCDCAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3;
- *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
- */
-#define LCDCAM_LCD_CLKCNT_N    0x0000003FU
-#define LCDCAM_LCD_CLKCNT_N_M  (LCDCAM_LCD_CLKCNT_N_V << LCDCAM_LCD_CLKCNT_N_S)
-#define LCDCAM_LCD_CLKCNT_N_V  0x0000003FU
-#define LCDCAM_LCD_CLKCNT_N_S  0
-/** LCDCAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1;
- *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
- */
-#define LCDCAM_LCD_CLK_EQU_SYSCLK    (BIT(6))
-#define LCDCAM_LCD_CLK_EQU_SYSCLK_M  (LCDCAM_LCD_CLK_EQU_SYSCLK_V << LCDCAM_LCD_CLK_EQU_SYSCLK_S)
-#define LCDCAM_LCD_CLK_EQU_SYSCLK_V  0x00000001U
-#define LCDCAM_LCD_CLK_EQU_SYSCLK_S  6
-/** LCDCAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0;
- *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
- */
-#define LCDCAM_LCD_CK_IDLE_EDGE    (BIT(7))
-#define LCDCAM_LCD_CK_IDLE_EDGE_M  (LCDCAM_LCD_CK_IDLE_EDGE_V << LCDCAM_LCD_CK_IDLE_EDGE_S)
-#define LCDCAM_LCD_CK_IDLE_EDGE_V  0x00000001U
-#define LCDCAM_LCD_CK_IDLE_EDGE_S  7
-/** LCDCAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0;
- *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
- *  in the second half data cycle.
- */
-#define LCDCAM_LCD_CK_OUT_EDGE    (BIT(8))
-#define LCDCAM_LCD_CK_OUT_EDGE_M  (LCDCAM_LCD_CK_OUT_EDGE_V << LCDCAM_LCD_CK_OUT_EDGE_S)
-#define LCDCAM_LCD_CK_OUT_EDGE_V  0x00000001U
-#define LCDCAM_LCD_CK_OUT_EDGE_S  8
-/** LCDCAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
- *  Integral LCD clock divider value
- */
-#define LCDCAM_LCD_CLKM_DIV_NUM    0x000000FFU
-#define LCDCAM_LCD_CLKM_DIV_NUM_M  (LCDCAM_LCD_CLKM_DIV_NUM_V << LCDCAM_LCD_CLKM_DIV_NUM_S)
-#define LCDCAM_LCD_CLKM_DIV_NUM_V  0x000000FFU
-#define LCDCAM_LCD_CLKM_DIV_NUM_S  9
-/** LCDCAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
- *  Fractional clock divider numerator value
- */
-#define LCDCAM_LCD_CLKM_DIV_B    0x0000003FU
-#define LCDCAM_LCD_CLKM_DIV_B_M  (LCDCAM_LCD_CLKM_DIV_B_V << LCDCAM_LCD_CLKM_DIV_B_S)
-#define LCDCAM_LCD_CLKM_DIV_B_V  0x0000003FU
-#define LCDCAM_LCD_CLKM_DIV_B_S  17
-/** LCDCAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
- *  Fractional clock divider denominator value
- */
-#define LCDCAM_LCD_CLKM_DIV_A    0x0000003FU
-#define LCDCAM_LCD_CLKM_DIV_A_M  (LCDCAM_LCD_CLKM_DIV_A_V << LCDCAM_LCD_CLKM_DIV_A_S)
-#define LCDCAM_LCD_CLKM_DIV_A_V  0x0000003FU
-#define LCDCAM_LCD_CLKM_DIV_A_S  23
-/** LCDCAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
- *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
- */
-#define LCDCAM_LCD_CLK_SEL    0x00000003U
-#define LCDCAM_LCD_CLK_SEL_M  (LCDCAM_LCD_CLK_SEL_V << LCDCAM_LCD_CLK_SEL_S)
-#define LCDCAM_LCD_CLK_SEL_V  0x00000003U
-#define LCDCAM_LCD_CLK_SEL_S  29
-/** LCDCAM_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Set this bit to enable clk gate
- */
-#define LCDCAM_CLK_EN    (BIT(31))
-#define LCDCAM_CLK_EN_M  (LCDCAM_CLK_EN_V << LCDCAM_CLK_EN_S)
-#define LCDCAM_CLK_EN_V  0x00000001U
-#define LCDCAM_CLK_EN_S  31
-
-/** LCDCAM_CAM_CTRL_REG register
- *  CAM config register.
- */
-#define LCDCAM_CAM_CTRL_REG (DR_REG_LCDCAM_BASE + 0x4)
-/** LCDCAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0;
- *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
- */
-#define LCDCAM_CAM_STOP_EN    (BIT(0))
-#define LCDCAM_CAM_STOP_EN_M  (LCDCAM_CAM_STOP_EN_V << LCDCAM_CAM_STOP_EN_S)
-#define LCDCAM_CAM_STOP_EN_V  0x00000001U
-#define LCDCAM_CAM_STOP_EN_S  0
-/** LCDCAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0;
- *  Filter threshold value for CAM_VSYNC signal.
- */
-#define LCDCAM_CAM_VSYNC_FILTER_THRES    0x00000007U
-#define LCDCAM_CAM_VSYNC_FILTER_THRES_M  (LCDCAM_CAM_VSYNC_FILTER_THRES_V << LCDCAM_CAM_VSYNC_FILTER_THRES_S)
-#define LCDCAM_CAM_VSYNC_FILTER_THRES_V  0x00000007U
-#define LCDCAM_CAM_VSYNC_FILTER_THRES_S  1
-/** LCDCAM_CAM_UPDATE_REG : R/W/SC; bitpos: [4]; default: 0;
- *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
- */
-#define LCDCAM_CAM_UPDATE_REG    (BIT(4))
-#define LCDCAM_CAM_UPDATE_REG_M  (LCDCAM_CAM_UPDATE_REG_V << LCDCAM_CAM_UPDATE_REG_S)
-#define LCDCAM_CAM_UPDATE_REG_V  0x00000001U
-#define LCDCAM_CAM_UPDATE_REG_S  4
-/** LCDCAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0;
- *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
- *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
- */
-#define LCDCAM_CAM_BYTE_ORDER    (BIT(5))
-#define LCDCAM_CAM_BYTE_ORDER_M  (LCDCAM_CAM_BYTE_ORDER_V << LCDCAM_CAM_BYTE_ORDER_S)
-#define LCDCAM_CAM_BYTE_ORDER_V  0x00000001U
-#define LCDCAM_CAM_BYTE_ORDER_S  5
-/** LCDCAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0;
- *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
- */
-#define LCDCAM_CAM_BIT_ORDER    (BIT(6))
-#define LCDCAM_CAM_BIT_ORDER_M  (LCDCAM_CAM_BIT_ORDER_V << LCDCAM_CAM_BIT_ORDER_S)
-#define LCDCAM_CAM_BIT_ORDER_V  0x00000001U
-#define LCDCAM_CAM_BIT_ORDER_S  6
-/** LCDCAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0;
- *  1: Enable to generate CAM_HS_INT. 0: Disable.
- */
-#define LCDCAM_CAM_LINE_INT_EN    (BIT(7))
-#define LCDCAM_CAM_LINE_INT_EN_M  (LCDCAM_CAM_LINE_INT_EN_V << LCDCAM_CAM_LINE_INT_EN_S)
-#define LCDCAM_CAM_LINE_INT_EN_V  0x00000001U
-#define LCDCAM_CAM_LINE_INT_EN_S  7
-/** LCDCAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0;
- *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
- *  reg_cam_rec_data_cyclelen.
- */
-#define LCDCAM_CAM_VS_EOF_EN    (BIT(8))
-#define LCDCAM_CAM_VS_EOF_EN_M  (LCDCAM_CAM_VS_EOF_EN_V << LCDCAM_CAM_VS_EOF_EN_S)
-#define LCDCAM_CAM_VS_EOF_EN_V  0x00000001U
-#define LCDCAM_CAM_VS_EOF_EN_S  8
-/** LCDCAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
- *  Integral Camera clock divider value
- */
-#define LCDCAM_CAM_CLKM_DIV_NUM    0x000000FFU
-#define LCDCAM_CAM_CLKM_DIV_NUM_M  (LCDCAM_CAM_CLKM_DIV_NUM_V << LCDCAM_CAM_CLKM_DIV_NUM_S)
-#define LCDCAM_CAM_CLKM_DIV_NUM_V  0x000000FFU
-#define LCDCAM_CAM_CLKM_DIV_NUM_S  9
-/** LCDCAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
- *  Fractional clock divider numerator value
- */
-#define LCDCAM_CAM_CLKM_DIV_B    0x0000003FU
-#define LCDCAM_CAM_CLKM_DIV_B_M  (LCDCAM_CAM_CLKM_DIV_B_V << LCDCAM_CAM_CLKM_DIV_B_S)
-#define LCDCAM_CAM_CLKM_DIV_B_V  0x0000003FU
-#define LCDCAM_CAM_CLKM_DIV_B_S  17
-/** LCDCAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
- *  Fractional clock divider denominator value
- */
-#define LCDCAM_CAM_CLKM_DIV_A    0x0000003FU
-#define LCDCAM_CAM_CLKM_DIV_A_M  (LCDCAM_CAM_CLKM_DIV_A_V << LCDCAM_CAM_CLKM_DIV_A_S)
-#define LCDCAM_CAM_CLKM_DIV_A_V  0x0000003FU
-#define LCDCAM_CAM_CLKM_DIV_A_S  23
-/** LCDCAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
- *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
- */
-#define LCDCAM_CAM_CLK_SEL    0x00000003U
-#define LCDCAM_CAM_CLK_SEL_M  (LCDCAM_CAM_CLK_SEL_V << LCDCAM_CAM_CLK_SEL_S)
-#define LCDCAM_CAM_CLK_SEL_V  0x00000003U
-#define LCDCAM_CAM_CLK_SEL_S  29
-
-/** LCDCAM_CAM_CTRL1_REG register
- *  CAM config register.
- */
-#define LCDCAM_CAM_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x8)
-/** LCDCAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0;
- *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
- */
-#define LCDCAM_CAM_REC_DATA_BYTELEN    0x0000FFFFU
-#define LCDCAM_CAM_REC_DATA_BYTELEN_M  (LCDCAM_CAM_REC_DATA_BYTELEN_V << LCDCAM_CAM_REC_DATA_BYTELEN_S)
-#define LCDCAM_CAM_REC_DATA_BYTELEN_V  0x0000FFFFU
-#define LCDCAM_CAM_REC_DATA_BYTELEN_S  0
-/** LCDCAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0;
- *  The line number minus 1 to generate cam_hs_int.
- */
-#define LCDCAM_CAM_LINE_INT_NUM    0x0000003FU
-#define LCDCAM_CAM_LINE_INT_NUM_M  (LCDCAM_CAM_LINE_INT_NUM_V << LCDCAM_CAM_LINE_INT_NUM_S)
-#define LCDCAM_CAM_LINE_INT_NUM_V  0x0000003FU
-#define LCDCAM_CAM_LINE_INT_NUM_S  16
-/** LCDCAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0;
- *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
- */
-#define LCDCAM_CAM_CLK_INV    (BIT(22))
-#define LCDCAM_CAM_CLK_INV_M  (LCDCAM_CAM_CLK_INV_V << LCDCAM_CAM_CLK_INV_S)
-#define LCDCAM_CAM_CLK_INV_V  0x00000001U
-#define LCDCAM_CAM_CLK_INV_S  22
-/** LCDCAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0;
- *  1: Enable CAM_VSYNC filter function. 0: bypass.
- */
-#define LCDCAM_CAM_VSYNC_FILTER_EN    (BIT(23))
-#define LCDCAM_CAM_VSYNC_FILTER_EN_M  (LCDCAM_CAM_VSYNC_FILTER_EN_V << LCDCAM_CAM_VSYNC_FILTER_EN_S)
-#define LCDCAM_CAM_VSYNC_FILTER_EN_V  0x00000001U
-#define LCDCAM_CAM_VSYNC_FILTER_EN_S  23
-/** LCDCAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0;
- *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
- */
-#define LCDCAM_CAM_2BYTE_EN    (BIT(24))
-#define LCDCAM_CAM_2BYTE_EN_M  (LCDCAM_CAM_2BYTE_EN_V << LCDCAM_CAM_2BYTE_EN_S)
-#define LCDCAM_CAM_2BYTE_EN_V  0x00000001U
-#define LCDCAM_CAM_2BYTE_EN_S  24
-/** LCDCAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0;
- *  CAM_DE invert enable signal, valid in high level.
- */
-#define LCDCAM_CAM_DE_INV    (BIT(25))
-#define LCDCAM_CAM_DE_INV_M  (LCDCAM_CAM_DE_INV_V << LCDCAM_CAM_DE_INV_S)
-#define LCDCAM_CAM_DE_INV_V  0x00000001U
-#define LCDCAM_CAM_DE_INV_S  25
-/** LCDCAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0;
- *  CAM_HSYNC invert enable signal, valid in high level.
- */
-#define LCDCAM_CAM_HSYNC_INV    (BIT(26))
-#define LCDCAM_CAM_HSYNC_INV_M  (LCDCAM_CAM_HSYNC_INV_V << LCDCAM_CAM_HSYNC_INV_S)
-#define LCDCAM_CAM_HSYNC_INV_V  0x00000001U
-#define LCDCAM_CAM_HSYNC_INV_S  26
-/** LCDCAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0;
- *  CAM_VSYNC invert enable signal, valid in high level.
- */
-#define LCDCAM_CAM_VSYNC_INV    (BIT(27))
-#define LCDCAM_CAM_VSYNC_INV_M  (LCDCAM_CAM_VSYNC_INV_V << LCDCAM_CAM_VSYNC_INV_S)
-#define LCDCAM_CAM_VSYNC_INV_V  0x00000001U
-#define LCDCAM_CAM_VSYNC_INV_S  27
-/** LCDCAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0;
- *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
- *  signals are CAM_DE and CAM_VSYNC.
- */
-#define LCDCAM_CAM_VH_DE_MODE_EN    (BIT(28))
-#define LCDCAM_CAM_VH_DE_MODE_EN_M  (LCDCAM_CAM_VH_DE_MODE_EN_V << LCDCAM_CAM_VH_DE_MODE_EN_S)
-#define LCDCAM_CAM_VH_DE_MODE_EN_V  0x00000001U
-#define LCDCAM_CAM_VH_DE_MODE_EN_S  28
-/** LCDCAM_CAM_START : R/W/SC; bitpos: [29]; default: 0;
- *  Camera module start signal.
- */
-#define LCDCAM_CAM_START    (BIT(29))
-#define LCDCAM_CAM_START_M  (LCDCAM_CAM_START_V << LCDCAM_CAM_START_S)
-#define LCDCAM_CAM_START_V  0x00000001U
-#define LCDCAM_CAM_START_S  29
-/** LCDCAM_CAM_RESET : WT; bitpos: [30]; default: 0;
- *  Camera module reset signal.
- */
-#define LCDCAM_CAM_RESET    (BIT(30))
-#define LCDCAM_CAM_RESET_M  (LCDCAM_CAM_RESET_V << LCDCAM_CAM_RESET_S)
-#define LCDCAM_CAM_RESET_V  0x00000001U
-#define LCDCAM_CAM_RESET_S  30
-/** LCDCAM_CAM_AFIFO_RESET : WT; bitpos: [31]; default: 0;
- *  Camera AFIFO reset signal.
- */
-#define LCDCAM_CAM_AFIFO_RESET    (BIT(31))
-#define LCDCAM_CAM_AFIFO_RESET_M  (LCDCAM_CAM_AFIFO_RESET_V << LCDCAM_CAM_AFIFO_RESET_S)
-#define LCDCAM_CAM_AFIFO_RESET_V  0x00000001U
-#define LCDCAM_CAM_AFIFO_RESET_S  31
-
-/** LCDCAM_CAM_RGB_YUV_REG register
- *  CAM YUV/RGB converter configuration register.
- */
-#define LCDCAM_CAM_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0xc)
-/** LCDCAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0;
- *  1:invert every two 8bits input data. 2. disabled.
- */
-#define LCDCAM_CAM_CONV_8BITS_DATA_INV    (BIT(21))
-#define LCDCAM_CAM_CONV_8BITS_DATA_INV_M  (LCDCAM_CAM_CONV_8BITS_DATA_INV_V << LCDCAM_CAM_CONV_8BITS_DATA_INV_S)
-#define LCDCAM_CAM_CONV_8BITS_DATA_INV_V  0x00000001U
-#define LCDCAM_CAM_CONV_8BITS_DATA_INV_S  21
-/** LCDCAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
- *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
- *  trans_mode must be set to 1.
- */
-#define LCDCAM_CAM_CONV_YUV2YUV_MODE    0x00000003U
-#define LCDCAM_CAM_CONV_YUV2YUV_MODE_M  (LCDCAM_CAM_CONV_YUV2YUV_MODE_V << LCDCAM_CAM_CONV_YUV2YUV_MODE_S)
-#define LCDCAM_CAM_CONV_YUV2YUV_MODE_V  0x00000003U
-#define LCDCAM_CAM_CONV_YUV2YUV_MODE_S  22
-/** LCDCAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
- *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
- *  mode of Data_in
- */
-#define LCDCAM_CAM_CONV_YUV_MODE    0x00000003U
-#define LCDCAM_CAM_CONV_YUV_MODE_M  (LCDCAM_CAM_CONV_YUV_MODE_V << LCDCAM_CAM_CONV_YUV_MODE_S)
-#define LCDCAM_CAM_CONV_YUV_MODE_V  0x00000003U
-#define LCDCAM_CAM_CONV_YUV_MODE_S  24
-/** LCDCAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
- *  0:BT601. 1:BT709.
- */
-#define LCDCAM_CAM_CONV_PROTOCOL_MODE    (BIT(26))
-#define LCDCAM_CAM_CONV_PROTOCOL_MODE_M  (LCDCAM_CAM_CONV_PROTOCOL_MODE_V << LCDCAM_CAM_CONV_PROTOCOL_MODE_S)
-#define LCDCAM_CAM_CONV_PROTOCOL_MODE_V  0x00000001U
-#define LCDCAM_CAM_CONV_PROTOCOL_MODE_S  26
-/** LCDCAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
- *  LIMIT or FULL mode of Data out. 0: limit. 1: full
- */
-#define LCDCAM_CAM_CONV_DATA_OUT_MODE    (BIT(27))
-#define LCDCAM_CAM_CONV_DATA_OUT_MODE_M  (LCDCAM_CAM_CONV_DATA_OUT_MODE_V << LCDCAM_CAM_CONV_DATA_OUT_MODE_S)
-#define LCDCAM_CAM_CONV_DATA_OUT_MODE_V  0x00000001U
-#define LCDCAM_CAM_CONV_DATA_OUT_MODE_S  27
-/** LCDCAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
- *  LIMIT or FULL mode of Data in. 0: limit. 1: full
- */
-#define LCDCAM_CAM_CONV_DATA_IN_MODE    (BIT(28))
-#define LCDCAM_CAM_CONV_DATA_IN_MODE_M  (LCDCAM_CAM_CONV_DATA_IN_MODE_V << LCDCAM_CAM_CONV_DATA_IN_MODE_S)
-#define LCDCAM_CAM_CONV_DATA_IN_MODE_V  0x00000001U
-#define LCDCAM_CAM_CONV_DATA_IN_MODE_S  28
-/** LCDCAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
- *  0: 16bits mode. 1: 8bits mode.
- */
-#define LCDCAM_CAM_CONV_MODE_8BITS_ON    (BIT(29))
-#define LCDCAM_CAM_CONV_MODE_8BITS_ON_M  (LCDCAM_CAM_CONV_MODE_8BITS_ON_V << LCDCAM_CAM_CONV_MODE_8BITS_ON_S)
-#define LCDCAM_CAM_CONV_MODE_8BITS_ON_V  0x00000001U
-#define LCDCAM_CAM_CONV_MODE_8BITS_ON_S  29
-/** LCDCAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
- *  0: YUV to RGB. 1: RGB to YUV.
- */
-#define LCDCAM_CAM_CONV_TRANS_MODE    (BIT(30))
-#define LCDCAM_CAM_CONV_TRANS_MODE_M  (LCDCAM_CAM_CONV_TRANS_MODE_V << LCDCAM_CAM_CONV_TRANS_MODE_S)
-#define LCDCAM_CAM_CONV_TRANS_MODE_V  0x00000001U
-#define LCDCAM_CAM_CONV_TRANS_MODE_S  30
-/** LCDCAM_CAM_CONV_ENABLE : R/W; bitpos: [31]; default: 0;
- *  0: Bypass converter. 1: Enable converter.
- */
-#define LCDCAM_CAM_CONV_ENABLE    (BIT(31))
-#define LCDCAM_CAM_CONV_ENABLE_M  (LCDCAM_CAM_CONV_ENABLE_V << LCDCAM_CAM_CONV_ENABLE_S)
-#define LCDCAM_CAM_CONV_ENABLE_V  0x00000001U
-#define LCDCAM_CAM_CONV_ENABLE_S  31
-
-/** LCDCAM_LCD_RGB_YUV_REG register
- *  LCD YUV/RGB converter configuration register.
- */
-#define LCDCAM_LCD_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0x10)
-/** LCDCAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0;
- *  1:invert every two 8bits input data. 2. disabled.
- */
-#define LCDCAM_LCD_CONV_8BITS_DATA_INV    (BIT(20))
-#define LCDCAM_LCD_CONV_8BITS_DATA_INV_M  (LCDCAM_LCD_CONV_8BITS_DATA_INV_V << LCDCAM_LCD_CONV_8BITS_DATA_INV_S)
-#define LCDCAM_LCD_CONV_8BITS_DATA_INV_V  0x00000001U
-#define LCDCAM_LCD_CONV_8BITS_DATA_INV_S  20
-/** LCDCAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0;
- *  0: txtorx mode off. 1: txtorx mode on.
- */
-#define LCDCAM_LCD_CONV_TXTORX    (BIT(21))
-#define LCDCAM_LCD_CONV_TXTORX_M  (LCDCAM_LCD_CONV_TXTORX_V << LCDCAM_LCD_CONV_TXTORX_S)
-#define LCDCAM_LCD_CONV_TXTORX_V  0x00000001U
-#define LCDCAM_LCD_CONV_TXTORX_S  21
-/** LCDCAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
- *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
- *  trans_mode must be set to 1.
- */
-#define LCDCAM_LCD_CONV_YUV2YUV_MODE    0x00000003U
-#define LCDCAM_LCD_CONV_YUV2YUV_MODE_M  (LCDCAM_LCD_CONV_YUV2YUV_MODE_V << LCDCAM_LCD_CONV_YUV2YUV_MODE_S)
-#define LCDCAM_LCD_CONV_YUV2YUV_MODE_V  0x00000003U
-#define LCDCAM_LCD_CONV_YUV2YUV_MODE_S  22
-/** LCDCAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
- *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
- *  mode of Data_in
- */
-#define LCDCAM_LCD_CONV_YUV_MODE    0x00000003U
-#define LCDCAM_LCD_CONV_YUV_MODE_M  (LCDCAM_LCD_CONV_YUV_MODE_V << LCDCAM_LCD_CONV_YUV_MODE_S)
-#define LCDCAM_LCD_CONV_YUV_MODE_V  0x00000003U
-#define LCDCAM_LCD_CONV_YUV_MODE_S  24
-/** LCDCAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
- *  0:BT601. 1:BT709.
- */
-#define LCDCAM_LCD_CONV_PROTOCOL_MODE    (BIT(26))
-#define LCDCAM_LCD_CONV_PROTOCOL_MODE_M  (LCDCAM_LCD_CONV_PROTOCOL_MODE_V << LCDCAM_LCD_CONV_PROTOCOL_MODE_S)
-#define LCDCAM_LCD_CONV_PROTOCOL_MODE_V  0x00000001U
-#define LCDCAM_LCD_CONV_PROTOCOL_MODE_S  26
-/** LCDCAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
- *  LIMIT or FULL mode of Data out. 0: limit. 1: full
- */
-#define LCDCAM_LCD_CONV_DATA_OUT_MODE    (BIT(27))
-#define LCDCAM_LCD_CONV_DATA_OUT_MODE_M  (LCDCAM_LCD_CONV_DATA_OUT_MODE_V << LCDCAM_LCD_CONV_DATA_OUT_MODE_S)
-#define LCDCAM_LCD_CONV_DATA_OUT_MODE_V  0x00000001U
-#define LCDCAM_LCD_CONV_DATA_OUT_MODE_S  27
-/** LCDCAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
- *  LIMIT or FULL mode of Data in. 0: limit. 1: full
- */
-#define LCDCAM_LCD_CONV_DATA_IN_MODE    (BIT(28))
-#define LCDCAM_LCD_CONV_DATA_IN_MODE_M  (LCDCAM_LCD_CONV_DATA_IN_MODE_V << LCDCAM_LCD_CONV_DATA_IN_MODE_S)
-#define LCDCAM_LCD_CONV_DATA_IN_MODE_V  0x00000001U
-#define LCDCAM_LCD_CONV_DATA_IN_MODE_S  28
-/** LCDCAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
- *  0: 16bits mode. 1: 8bits mode.
- */
-#define LCDCAM_LCD_CONV_MODE_8BITS_ON    (BIT(29))
-#define LCDCAM_LCD_CONV_MODE_8BITS_ON_M  (LCDCAM_LCD_CONV_MODE_8BITS_ON_V << LCDCAM_LCD_CONV_MODE_8BITS_ON_S)
-#define LCDCAM_LCD_CONV_MODE_8BITS_ON_V  0x00000001U
-#define LCDCAM_LCD_CONV_MODE_8BITS_ON_S  29
-/** LCDCAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
- *  0: YUV to RGB. 1: RGB to YUV.
- */
-#define LCDCAM_LCD_CONV_TRANS_MODE    (BIT(30))
-#define LCDCAM_LCD_CONV_TRANS_MODE_M  (LCDCAM_LCD_CONV_TRANS_MODE_V << LCDCAM_LCD_CONV_TRANS_MODE_S)
-#define LCDCAM_LCD_CONV_TRANS_MODE_V  0x00000001U
-#define LCDCAM_LCD_CONV_TRANS_MODE_S  30
-/** LCDCAM_LCD_CONV_ENABLE : R/W; bitpos: [31]; default: 0;
- *  0: Bypass converter. 1: Enable converter.
- */
-#define LCDCAM_LCD_CONV_ENABLE    (BIT(31))
-#define LCDCAM_LCD_CONV_ENABLE_M  (LCDCAM_LCD_CONV_ENABLE_V << LCDCAM_LCD_CONV_ENABLE_S)
-#define LCDCAM_LCD_CONV_ENABLE_V  0x00000001U
-#define LCDCAM_LCD_CONV_ENABLE_S  31
-
-/** LCDCAM_LCD_USER_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_USER_REG (DR_REG_LCDCAM_BASE + 0x14)
-/** LCDCAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1;
- *  The output data cycles minus 1 of LCD module.
- */
-#define LCDCAM_LCD_DOUT_CYCLELEN    0x00001FFFU
-#define LCDCAM_LCD_DOUT_CYCLELEN_M  (LCDCAM_LCD_DOUT_CYCLELEN_V << LCDCAM_LCD_DOUT_CYCLELEN_S)
-#define LCDCAM_LCD_DOUT_CYCLELEN_V  0x00001FFFU
-#define LCDCAM_LCD_DOUT_CYCLELEN_S  0
-/** LCDCAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0;
- *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
- *  reg_lcd_reset is set.
- */
-#define LCDCAM_LCD_ALWAYS_OUT_EN    (BIT(13))
-#define LCDCAM_LCD_ALWAYS_OUT_EN_M  (LCDCAM_LCD_ALWAYS_OUT_EN_V << LCDCAM_LCD_ALWAYS_OUT_EN_S)
-#define LCDCAM_LCD_ALWAYS_OUT_EN_V  0x00000001U
-#define LCDCAM_LCD_ALWAYS_OUT_EN_S  13
-/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W; bitpos: [16:14]; default: 0;
- *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
- */
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE    0x00000007U
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M  (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S)
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V  0x00000007U
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S  14
-/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W; bitpos: [17]; default: 0;
- *  1: enable byte swizzle 0: disable
- */
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE    (BIT(17))
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M  (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S)
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V  0x00000001U
-#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S  17
-/** LCDCAM_LCD_DOUT_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  1: change bit order in every byte. 0: Not change.
- */
-#define LCDCAM_LCD_DOUT_BIT_ORDER    (BIT(18))
-#define LCDCAM_LCD_DOUT_BIT_ORDER_M  (LCDCAM_LCD_DOUT_BIT_ORDER_V << LCDCAM_LCD_DOUT_BIT_ORDER_S)
-#define LCDCAM_LCD_DOUT_BIT_ORDER_V  0x00000001U
-#define LCDCAM_LCD_DOUT_BIT_ORDER_S  18
-/** LCDCAM_LCD_BYTE_MODE : R/W; bitpos: [20:19]; default: 0;
- *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
- */
-#define LCDCAM_LCD_BYTE_MODE    0x00000003U
-#define LCDCAM_LCD_BYTE_MODE_M  (LCDCAM_LCD_BYTE_MODE_V << LCDCAM_LCD_BYTE_MODE_S)
-#define LCDCAM_LCD_BYTE_MODE_V  0x00000003U
-#define LCDCAM_LCD_BYTE_MODE_S  19
-/** LCDCAM_LCD_UPDATE_REG : R/W/SC; bitpos: [21]; default: 0;
- *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
- */
-#define LCDCAM_LCD_UPDATE_REG    (BIT(21))
-#define LCDCAM_LCD_UPDATE_REG_M  (LCDCAM_LCD_UPDATE_REG_V << LCDCAM_LCD_UPDATE_REG_S)
-#define LCDCAM_LCD_UPDATE_REG_V  0x00000001U
-#define LCDCAM_LCD_UPDATE_REG_S  21
-/** LCDCAM_LCD_BIT_ORDER : R/W; bitpos: [22]; default: 0;
- *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
- *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
- */
-#define LCDCAM_LCD_BIT_ORDER    (BIT(22))
-#define LCDCAM_LCD_BIT_ORDER_M  (LCDCAM_LCD_BIT_ORDER_V << LCDCAM_LCD_BIT_ORDER_S)
-#define LCDCAM_LCD_BIT_ORDER_V  0x00000001U
-#define LCDCAM_LCD_BIT_ORDER_S  22
-/** LCDCAM_LCD_BYTE_ORDER : R/W; bitpos: [23]; default: 0;
- *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
- */
-#define LCDCAM_LCD_BYTE_ORDER    (BIT(23))
-#define LCDCAM_LCD_BYTE_ORDER_M  (LCDCAM_LCD_BYTE_ORDER_V << LCDCAM_LCD_BYTE_ORDER_S)
-#define LCDCAM_LCD_BYTE_ORDER_V  0x00000001U
-#define LCDCAM_LCD_BYTE_ORDER_S  23
-/** LCDCAM_LCD_DOUT : R/W; bitpos: [24]; default: 0;
- *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
- */
-#define LCDCAM_LCD_DOUT    (BIT(24))
-#define LCDCAM_LCD_DOUT_M  (LCDCAM_LCD_DOUT_V << LCDCAM_LCD_DOUT_S)
-#define LCDCAM_LCD_DOUT_V  0x00000001U
-#define LCDCAM_LCD_DOUT_S  24
-/** LCDCAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0;
- *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
- */
-#define LCDCAM_LCD_DUMMY    (BIT(25))
-#define LCDCAM_LCD_DUMMY_M  (LCDCAM_LCD_DUMMY_V << LCDCAM_LCD_DUMMY_S)
-#define LCDCAM_LCD_DUMMY_V  0x00000001U
-#define LCDCAM_LCD_DUMMY_S  25
-/** LCDCAM_LCD_CMD : R/W; bitpos: [26]; default: 0;
- *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
- */
-#define LCDCAM_LCD_CMD    (BIT(26))
-#define LCDCAM_LCD_CMD_M  (LCDCAM_LCD_CMD_V << LCDCAM_LCD_CMD_S)
-#define LCDCAM_LCD_CMD_V  0x00000001U
-#define LCDCAM_LCD_CMD_S  26
-/** LCDCAM_LCD_START : R/W/SC; bitpos: [27]; default: 0;
- *  LCD start sending data enable signal, valid in high level.
- */
-#define LCDCAM_LCD_START    (BIT(27))
-#define LCDCAM_LCD_START_M  (LCDCAM_LCD_START_V << LCDCAM_LCD_START_S)
-#define LCDCAM_LCD_START_V  0x00000001U
-#define LCDCAM_LCD_START_S  27
-/** LCDCAM_LCD_RESET : WT; bitpos: [28]; default: 0;
- *  The value of  command.
- */
-#define LCDCAM_LCD_RESET    (BIT(28))
-#define LCDCAM_LCD_RESET_M  (LCDCAM_LCD_RESET_V << LCDCAM_LCD_RESET_S)
-#define LCDCAM_LCD_RESET_V  0x00000001U
-#define LCDCAM_LCD_RESET_S  28
-/** LCDCAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0;
- *  The dummy cycle length minus 1.
- */
-#define LCDCAM_LCD_DUMMY_CYCLELEN    0x00000003U
-#define LCDCAM_LCD_DUMMY_CYCLELEN_M  (LCDCAM_LCD_DUMMY_CYCLELEN_V << LCDCAM_LCD_DUMMY_CYCLELEN_S)
-#define LCDCAM_LCD_DUMMY_CYCLELEN_V  0x00000003U
-#define LCDCAM_LCD_DUMMY_CYCLELEN_S  29
-/** LCDCAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0;
- *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
- */
-#define LCDCAM_LCD_CMD_2_CYCLE_EN    (BIT(31))
-#define LCDCAM_LCD_CMD_2_CYCLE_EN_M  (LCDCAM_LCD_CMD_2_CYCLE_EN_V << LCDCAM_LCD_CMD_2_CYCLE_EN_S)
-#define LCDCAM_LCD_CMD_2_CYCLE_EN_V  0x00000001U
-#define LCDCAM_LCD_CMD_2_CYCLE_EN_S  31
-
-/** LCDCAM_LCD_MISC_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_MISC_REG (DR_REG_LCDCAM_BASE + 0x18)
-/** LCDCAM_LCD_WIRE_MODE : R/W; bitpos: [5:4]; default: 0;
- *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
- */
-#define LCDCAM_LCD_WIRE_MODE    0x00000003U
-#define LCDCAM_LCD_WIRE_MODE_M  (LCDCAM_LCD_WIRE_MODE_V << LCDCAM_LCD_WIRE_MODE_S)
-#define LCDCAM_LCD_WIRE_MODE_V  0x00000003U
-#define LCDCAM_LCD_WIRE_MODE_S  4
-/** LCDCAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3;
- *  The setup cycle length minus 1 in LCD non-RGB mode.
- */
-#define LCDCAM_LCD_VFK_CYCLELEN    0x0000003FU
-#define LCDCAM_LCD_VFK_CYCLELEN_M  (LCDCAM_LCD_VFK_CYCLELEN_V << LCDCAM_LCD_VFK_CYCLELEN_S)
-#define LCDCAM_LCD_VFK_CYCLELEN_V  0x0000003FU
-#define LCDCAM_LCD_VFK_CYCLELEN_S  6
-/** LCDCAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0;
- *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
- *  time cycle length in LCD non-RGB mode.
- */
-#define LCDCAM_LCD_VBK_CYCLELEN    0x00001FFFU
-#define LCDCAM_LCD_VBK_CYCLELEN_M  (LCDCAM_LCD_VBK_CYCLELEN_V << LCDCAM_LCD_VBK_CYCLELEN_S)
-#define LCDCAM_LCD_VBK_CYCLELEN_V  0x00001FFFU
-#define LCDCAM_LCD_VBK_CYCLELEN_S  12
-/** LCDCAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0;
- *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
- *  the current frame is sent out.
- */
-#define LCDCAM_LCD_NEXT_FRAME_EN    (BIT(25))
-#define LCDCAM_LCD_NEXT_FRAME_EN_M  (LCDCAM_LCD_NEXT_FRAME_EN_V << LCDCAM_LCD_NEXT_FRAME_EN_S)
-#define LCDCAM_LCD_NEXT_FRAME_EN_V  0x00000001U
-#define LCDCAM_LCD_NEXT_FRAME_EN_S  25
-/** LCDCAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0;
- *  1: Enable blank region when LCD sends data out. 0: No blank region.
- */
-#define LCDCAM_LCD_BK_EN    (BIT(26))
-#define LCDCAM_LCD_BK_EN_M  (LCDCAM_LCD_BK_EN_V << LCDCAM_LCD_BK_EN_S)
-#define LCDCAM_LCD_BK_EN_V  0x00000001U
-#define LCDCAM_LCD_BK_EN_S  26
-/** LCDCAM_LCD_AFIFO_RESET : WT; bitpos: [27]; default: 0;
- *  LCD AFIFO reset signal.
- */
-#define LCDCAM_LCD_AFIFO_RESET    (BIT(27))
-#define LCDCAM_LCD_AFIFO_RESET_M  (LCDCAM_LCD_AFIFO_RESET_V << LCDCAM_LCD_AFIFO_RESET_S)
-#define LCDCAM_LCD_AFIFO_RESET_V  0x00000001U
-#define LCDCAM_LCD_AFIFO_RESET_S  27
-/** LCDCAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0;
- *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
- *  reg_cd_idle_edge.
- */
-#define LCDCAM_LCD_CD_DATA_SET    (BIT(28))
-#define LCDCAM_LCD_CD_DATA_SET_M  (LCDCAM_LCD_CD_DATA_SET_V << LCDCAM_LCD_CD_DATA_SET_S)
-#define LCDCAM_LCD_CD_DATA_SET_V  0x00000001U
-#define LCDCAM_LCD_CD_DATA_SET_S  28
-/** LCDCAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0;
- *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
- *  reg_cd_idle_edge.
- */
-#define LCDCAM_LCD_CD_DUMMY_SET    (BIT(29))
-#define LCDCAM_LCD_CD_DUMMY_SET_M  (LCDCAM_LCD_CD_DUMMY_SET_V << LCDCAM_LCD_CD_DUMMY_SET_S)
-#define LCDCAM_LCD_CD_DUMMY_SET_V  0x00000001U
-#define LCDCAM_LCD_CD_DUMMY_SET_S  29
-/** LCDCAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0;
- *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
- *  reg_cd_idle_edge.
- */
-#define LCDCAM_LCD_CD_CMD_SET    (BIT(30))
-#define LCDCAM_LCD_CD_CMD_SET_M  (LCDCAM_LCD_CD_CMD_SET_V << LCDCAM_LCD_CD_CMD_SET_S)
-#define LCDCAM_LCD_CD_CMD_SET_V  0x00000001U
-#define LCDCAM_LCD_CD_CMD_SET_S  30
-/** LCDCAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0;
- *  The default value of LCD_CD.
- */
-#define LCDCAM_LCD_CD_IDLE_EDGE    (BIT(31))
-#define LCDCAM_LCD_CD_IDLE_EDGE_M  (LCDCAM_LCD_CD_IDLE_EDGE_V << LCDCAM_LCD_CD_IDLE_EDGE_S)
-#define LCDCAM_LCD_CD_IDLE_EDGE_V  0x00000001U
-#define LCDCAM_LCD_CD_IDLE_EDGE_S  31
-
-/** LCDCAM_LCD_CTRL_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_CTRL_REG (DR_REG_LCDCAM_BASE + 0x1c)
-/** LCDCAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0;
- *  It is the horizontal blank front porch of a frame.
- */
-#define LCDCAM_LCD_HB_FRONT    0x000007FFU
-#define LCDCAM_LCD_HB_FRONT_M  (LCDCAM_LCD_HB_FRONT_V << LCDCAM_LCD_HB_FRONT_S)
-#define LCDCAM_LCD_HB_FRONT_V  0x000007FFU
-#define LCDCAM_LCD_HB_FRONT_S  0
-/** LCDCAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0;
- *  It is the vertical active height of a frame.
- */
-#define LCDCAM_LCD_VA_HEIGHT    0x000003FFU
-#define LCDCAM_LCD_VA_HEIGHT_M  (LCDCAM_LCD_VA_HEIGHT_V << LCDCAM_LCD_VA_HEIGHT_S)
-#define LCDCAM_LCD_VA_HEIGHT_V  0x000003FFU
-#define LCDCAM_LCD_VA_HEIGHT_S  11
-/** LCDCAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0;
- *  It is the vertical total height of a frame.
- */
-#define LCDCAM_LCD_VT_HEIGHT    0x000003FFU
-#define LCDCAM_LCD_VT_HEIGHT_M  (LCDCAM_LCD_VT_HEIGHT_V << LCDCAM_LCD_VT_HEIGHT_S)
-#define LCDCAM_LCD_VT_HEIGHT_V  0x000003FFU
-#define LCDCAM_LCD_VT_HEIGHT_S  21
-/** LCDCAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0;
- *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
- */
-#define LCDCAM_LCD_RGB_MODE_EN    (BIT(31))
-#define LCDCAM_LCD_RGB_MODE_EN_M  (LCDCAM_LCD_RGB_MODE_EN_V << LCDCAM_LCD_RGB_MODE_EN_S)
-#define LCDCAM_LCD_RGB_MODE_EN_V  0x00000001U
-#define LCDCAM_LCD_RGB_MODE_EN_S  31
-
-/** LCDCAM_LCD_CTRL1_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x20)
-/** LCDCAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0;
- *  It is the vertical blank front porch of a frame.
- */
-#define LCDCAM_LCD_VB_FRONT    0x000000FFU
-#define LCDCAM_LCD_VB_FRONT_M  (LCDCAM_LCD_VB_FRONT_V << LCDCAM_LCD_VB_FRONT_S)
-#define LCDCAM_LCD_VB_FRONT_V  0x000000FFU
-#define LCDCAM_LCD_VB_FRONT_S  0
-/** LCDCAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0;
- *  It is the horizontal active width of a frame.
- */
-#define LCDCAM_LCD_HA_WIDTH    0x00000FFFU
-#define LCDCAM_LCD_HA_WIDTH_M  (LCDCAM_LCD_HA_WIDTH_V << LCDCAM_LCD_HA_WIDTH_S)
-#define LCDCAM_LCD_HA_WIDTH_V  0x00000FFFU
-#define LCDCAM_LCD_HA_WIDTH_S  8
-/** LCDCAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0;
- *  It is the horizontal total width of a frame.
- */
-#define LCDCAM_LCD_HT_WIDTH    0x00000FFFU
-#define LCDCAM_LCD_HT_WIDTH_M  (LCDCAM_LCD_HT_WIDTH_V << LCDCAM_LCD_HT_WIDTH_S)
-#define LCDCAM_LCD_HT_WIDTH_V  0x00000FFFU
-#define LCDCAM_LCD_HT_WIDTH_S  20
-
-/** LCDCAM_LCD_CTRL2_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_CTRL2_REG (DR_REG_LCDCAM_BASE + 0x24)
-/** LCDCAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1;
- *  It is the position of LCD_VSYNC active pulse in a line.
- */
-#define LCDCAM_LCD_VSYNC_WIDTH    0x0000007FU
-#define LCDCAM_LCD_VSYNC_WIDTH_M  (LCDCAM_LCD_VSYNC_WIDTH_V << LCDCAM_LCD_VSYNC_WIDTH_S)
-#define LCDCAM_LCD_VSYNC_WIDTH_V  0x0000007FU
-#define LCDCAM_LCD_VSYNC_WIDTH_S  0
-/** LCDCAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0;
- *  It is the idle value of LCD_VSYNC.
- */
-#define LCDCAM_LCD_VSYNC_IDLE_POL    (BIT(7))
-#define LCDCAM_LCD_VSYNC_IDLE_POL_M  (LCDCAM_LCD_VSYNC_IDLE_POL_V << LCDCAM_LCD_VSYNC_IDLE_POL_S)
-#define LCDCAM_LCD_VSYNC_IDLE_POL_V  0x00000001U
-#define LCDCAM_LCD_VSYNC_IDLE_POL_S  7
-/** LCDCAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0;
- *  It is the idle value of LCD_DE.
- */
-#define LCDCAM_LCD_DE_IDLE_POL    (BIT(8))
-#define LCDCAM_LCD_DE_IDLE_POL_M  (LCDCAM_LCD_DE_IDLE_POL_V << LCDCAM_LCD_DE_IDLE_POL_S)
-#define LCDCAM_LCD_DE_IDLE_POL_V  0x00000001U
-#define LCDCAM_LCD_DE_IDLE_POL_S  8
-/** LCDCAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0;
- *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
- *  pulse is valid only in active region lines in RGB mode.
- */
-#define LCDCAM_LCD_HS_BLANK_EN    (BIT(9))
-#define LCDCAM_LCD_HS_BLANK_EN_M  (LCDCAM_LCD_HS_BLANK_EN_V << LCDCAM_LCD_HS_BLANK_EN_S)
-#define LCDCAM_LCD_HS_BLANK_EN_V  0x00000001U
-#define LCDCAM_LCD_HS_BLANK_EN_S  9
-/** LCDCAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1;
- *  It is the position of LCD_HSYNC active pulse in a line.
- */
-#define LCDCAM_LCD_HSYNC_WIDTH    0x0000007FU
-#define LCDCAM_LCD_HSYNC_WIDTH_M  (LCDCAM_LCD_HSYNC_WIDTH_V << LCDCAM_LCD_HSYNC_WIDTH_S)
-#define LCDCAM_LCD_HSYNC_WIDTH_V  0x0000007FU
-#define LCDCAM_LCD_HSYNC_WIDTH_S  16
-/** LCDCAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0;
- *  It is the idle value of LCD_HSYNC.
- */
-#define LCDCAM_LCD_HSYNC_IDLE_POL    (BIT(23))
-#define LCDCAM_LCD_HSYNC_IDLE_POL_M  (LCDCAM_LCD_HSYNC_IDLE_POL_V << LCDCAM_LCD_HSYNC_IDLE_POL_S)
-#define LCDCAM_LCD_HSYNC_IDLE_POL_V  0x00000001U
-#define LCDCAM_LCD_HSYNC_IDLE_POL_S  23
-/** LCDCAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0;
- *  It is the position of LCD_HSYNC active pulse in a line.
- */
-#define LCDCAM_LCD_HSYNC_POSITION    0x000000FFU
-#define LCDCAM_LCD_HSYNC_POSITION_M  (LCDCAM_LCD_HSYNC_POSITION_V << LCDCAM_LCD_HSYNC_POSITION_S)
-#define LCDCAM_LCD_HSYNC_POSITION_V  0x000000FFU
-#define LCDCAM_LCD_HSYNC_POSITION_S  24
-
-/** LCDCAM_LCD_FIRST_CMD_VAL_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x28)
-/** LCDCAM_LCD_FIRST_CMD_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  The LCD write command value of first cmd cycle.
- */
-#define LCDCAM_LCD_FIRST_CMD_VALUE    0xFFFFFFFFU
-#define LCDCAM_LCD_FIRST_CMD_VALUE_M  (LCDCAM_LCD_FIRST_CMD_VALUE_V << LCDCAM_LCD_FIRST_CMD_VALUE_S)
-#define LCDCAM_LCD_FIRST_CMD_VALUE_V  0xFFFFFFFFU
-#define LCDCAM_LCD_FIRST_CMD_VALUE_S  0
-
-/** LCDCAM_LCD_LATTER_CMD_VAL_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x2c)
-/** LCDCAM_LCD_LATTER_CMD_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  The LCD write command value of latter cmd cycle.
- */
-#define LCDCAM_LCD_LATTER_CMD_VALUE    0xFFFFFFFFU
-#define LCDCAM_LCD_LATTER_CMD_VALUE_M  (LCDCAM_LCD_LATTER_CMD_VALUE_V << LCDCAM_LCD_LATTER_CMD_VALUE_S)
-#define LCDCAM_LCD_LATTER_CMD_VALUE_V  0xFFFFFFFFU
-#define LCDCAM_LCD_LATTER_CMD_VALUE_S  0
-
-/** LCDCAM_LCD_DLY_MODE_CFG1_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCDCAM_BASE + 0x30)
-/** LCDCAM_DOUT16_MODE : R/W; bitpos: [1:0]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT16_MODE    0x00000003U
-#define LCDCAM_DOUT16_MODE_M  (LCDCAM_DOUT16_MODE_V << LCDCAM_DOUT16_MODE_S)
-#define LCDCAM_DOUT16_MODE_V  0x00000003U
-#define LCDCAM_DOUT16_MODE_S  0
-/** LCDCAM_DOUT17_MODE : R/W; bitpos: [3:2]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT17_MODE    0x00000003U
-#define LCDCAM_DOUT17_MODE_M  (LCDCAM_DOUT17_MODE_V << LCDCAM_DOUT17_MODE_S)
-#define LCDCAM_DOUT17_MODE_V  0x00000003U
-#define LCDCAM_DOUT17_MODE_S  2
-/** LCDCAM_DOUT18_MODE : R/W; bitpos: [5:4]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT18_MODE    0x00000003U
-#define LCDCAM_DOUT18_MODE_M  (LCDCAM_DOUT18_MODE_V << LCDCAM_DOUT18_MODE_S)
-#define LCDCAM_DOUT18_MODE_V  0x00000003U
-#define LCDCAM_DOUT18_MODE_S  4
-/** LCDCAM_DOUT19_MODE : R/W; bitpos: [7:6]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT19_MODE    0x00000003U
-#define LCDCAM_DOUT19_MODE_M  (LCDCAM_DOUT19_MODE_V << LCDCAM_DOUT19_MODE_S)
-#define LCDCAM_DOUT19_MODE_V  0x00000003U
-#define LCDCAM_DOUT19_MODE_S  6
-/** LCDCAM_DOUT20_MODE : R/W; bitpos: [9:8]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT20_MODE    0x00000003U
-#define LCDCAM_DOUT20_MODE_M  (LCDCAM_DOUT20_MODE_V << LCDCAM_DOUT20_MODE_S)
-#define LCDCAM_DOUT20_MODE_V  0x00000003U
-#define LCDCAM_DOUT20_MODE_S  8
-/** LCDCAM_DOUT21_MODE : R/W; bitpos: [11:10]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT21_MODE    0x00000003U
-#define LCDCAM_DOUT21_MODE_M  (LCDCAM_DOUT21_MODE_V << LCDCAM_DOUT21_MODE_S)
-#define LCDCAM_DOUT21_MODE_V  0x00000003U
-#define LCDCAM_DOUT21_MODE_S  10
-/** LCDCAM_DOUT22_MODE : R/W; bitpos: [13:12]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT22_MODE    0x00000003U
-#define LCDCAM_DOUT22_MODE_M  (LCDCAM_DOUT22_MODE_V << LCDCAM_DOUT22_MODE_S)
-#define LCDCAM_DOUT22_MODE_V  0x00000003U
-#define LCDCAM_DOUT22_MODE_S  12
-/** LCDCAM_DOUT23_MODE : R/W; bitpos: [15:14]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT23_MODE    0x00000003U
-#define LCDCAM_DOUT23_MODE_M  (LCDCAM_DOUT23_MODE_V << LCDCAM_DOUT23_MODE_S)
-#define LCDCAM_DOUT23_MODE_V  0x00000003U
-#define LCDCAM_DOUT23_MODE_S  14
-/** LCDCAM_LCD_CD_MODE : R/W; bitpos: [17:16]; default: 0;
- *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
- *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
- */
-#define LCDCAM_LCD_CD_MODE    0x00000003U
-#define LCDCAM_LCD_CD_MODE_M  (LCDCAM_LCD_CD_MODE_V << LCDCAM_LCD_CD_MODE_S)
-#define LCDCAM_LCD_CD_MODE_V  0x00000003U
-#define LCDCAM_LCD_CD_MODE_S  16
-/** LCDCAM_LCD_DE_MODE : R/W; bitpos: [19:18]; default: 0;
- *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
- *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
- */
-#define LCDCAM_LCD_DE_MODE    0x00000003U
-#define LCDCAM_LCD_DE_MODE_M  (LCDCAM_LCD_DE_MODE_V << LCDCAM_LCD_DE_MODE_S)
-#define LCDCAM_LCD_DE_MODE_V  0x00000003U
-#define LCDCAM_LCD_DE_MODE_S  18
-/** LCDCAM_LCD_HSYNC_MODE : R/W; bitpos: [21:20]; default: 0;
- *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
- *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
- */
-#define LCDCAM_LCD_HSYNC_MODE    0x00000003U
-#define LCDCAM_LCD_HSYNC_MODE_M  (LCDCAM_LCD_HSYNC_MODE_V << LCDCAM_LCD_HSYNC_MODE_S)
-#define LCDCAM_LCD_HSYNC_MODE_V  0x00000003U
-#define LCDCAM_LCD_HSYNC_MODE_S  20
-/** LCDCAM_LCD_VSYNC_MODE : R/W; bitpos: [23:22]; default: 0;
- *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
- *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
- */
-#define LCDCAM_LCD_VSYNC_MODE    0x00000003U
-#define LCDCAM_LCD_VSYNC_MODE_M  (LCDCAM_LCD_VSYNC_MODE_V << LCDCAM_LCD_VSYNC_MODE_S)
-#define LCDCAM_LCD_VSYNC_MODE_V  0x00000003U
-#define LCDCAM_LCD_VSYNC_MODE_S  22
-
-/** LCDCAM_LCD_DLY_MODE_CFG2_REG register
- *  LCD config register.
- */
-#define LCDCAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCDCAM_BASE + 0x38)
-/** LCDCAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT0_MODE    0x00000003U
-#define LCDCAM_DOUT0_MODE_M  (LCDCAM_DOUT0_MODE_V << LCDCAM_DOUT0_MODE_S)
-#define LCDCAM_DOUT0_MODE_V  0x00000003U
-#define LCDCAM_DOUT0_MODE_S  0
-/** LCDCAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT1_MODE    0x00000003U
-#define LCDCAM_DOUT1_MODE_M  (LCDCAM_DOUT1_MODE_V << LCDCAM_DOUT1_MODE_S)
-#define LCDCAM_DOUT1_MODE_V  0x00000003U
-#define LCDCAM_DOUT1_MODE_S  2
-/** LCDCAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT2_MODE    0x00000003U
-#define LCDCAM_DOUT2_MODE_M  (LCDCAM_DOUT2_MODE_V << LCDCAM_DOUT2_MODE_S)
-#define LCDCAM_DOUT2_MODE_V  0x00000003U
-#define LCDCAM_DOUT2_MODE_S  4
-/** LCDCAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT3_MODE    0x00000003U
-#define LCDCAM_DOUT3_MODE_M  (LCDCAM_DOUT3_MODE_V << LCDCAM_DOUT3_MODE_S)
-#define LCDCAM_DOUT3_MODE_V  0x00000003U
-#define LCDCAM_DOUT3_MODE_S  6
-/** LCDCAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT4_MODE    0x00000003U
-#define LCDCAM_DOUT4_MODE_M  (LCDCAM_DOUT4_MODE_V << LCDCAM_DOUT4_MODE_S)
-#define LCDCAM_DOUT4_MODE_V  0x00000003U
-#define LCDCAM_DOUT4_MODE_S  8
-/** LCDCAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT5_MODE    0x00000003U
-#define LCDCAM_DOUT5_MODE_M  (LCDCAM_DOUT5_MODE_V << LCDCAM_DOUT5_MODE_S)
-#define LCDCAM_DOUT5_MODE_V  0x00000003U
-#define LCDCAM_DOUT5_MODE_S  10
-/** LCDCAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT6_MODE    0x00000003U
-#define LCDCAM_DOUT6_MODE_M  (LCDCAM_DOUT6_MODE_V << LCDCAM_DOUT6_MODE_S)
-#define LCDCAM_DOUT6_MODE_V  0x00000003U
-#define LCDCAM_DOUT6_MODE_S  12
-/** LCDCAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT7_MODE    0x00000003U
-#define LCDCAM_DOUT7_MODE_M  (LCDCAM_DOUT7_MODE_V << LCDCAM_DOUT7_MODE_S)
-#define LCDCAM_DOUT7_MODE_V  0x00000003U
-#define LCDCAM_DOUT7_MODE_S  14
-/** LCDCAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT8_MODE    0x00000003U
-#define LCDCAM_DOUT8_MODE_M  (LCDCAM_DOUT8_MODE_V << LCDCAM_DOUT8_MODE_S)
-#define LCDCAM_DOUT8_MODE_V  0x00000003U
-#define LCDCAM_DOUT8_MODE_S  16
-/** LCDCAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT9_MODE    0x00000003U
-#define LCDCAM_DOUT9_MODE_M  (LCDCAM_DOUT9_MODE_V << LCDCAM_DOUT9_MODE_S)
-#define LCDCAM_DOUT9_MODE_V  0x00000003U
-#define LCDCAM_DOUT9_MODE_S  18
-/** LCDCAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT10_MODE    0x00000003U
-#define LCDCAM_DOUT10_MODE_M  (LCDCAM_DOUT10_MODE_V << LCDCAM_DOUT10_MODE_S)
-#define LCDCAM_DOUT10_MODE_V  0x00000003U
-#define LCDCAM_DOUT10_MODE_S  20
-/** LCDCAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT11_MODE    0x00000003U
-#define LCDCAM_DOUT11_MODE_M  (LCDCAM_DOUT11_MODE_V << LCDCAM_DOUT11_MODE_S)
-#define LCDCAM_DOUT11_MODE_V  0x00000003U
-#define LCDCAM_DOUT11_MODE_S  22
-/** LCDCAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT12_MODE    0x00000003U
-#define LCDCAM_DOUT12_MODE_M  (LCDCAM_DOUT12_MODE_V << LCDCAM_DOUT12_MODE_S)
-#define LCDCAM_DOUT12_MODE_V  0x00000003U
-#define LCDCAM_DOUT12_MODE_S  24
-/** LCDCAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT13_MODE    0x00000003U
-#define LCDCAM_DOUT13_MODE_M  (LCDCAM_DOUT13_MODE_V << LCDCAM_DOUT13_MODE_S)
-#define LCDCAM_DOUT13_MODE_V  0x00000003U
-#define LCDCAM_DOUT13_MODE_S  26
-/** LCDCAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT14_MODE    0x00000003U
-#define LCDCAM_DOUT14_MODE_M  (LCDCAM_DOUT14_MODE_V << LCDCAM_DOUT14_MODE_S)
-#define LCDCAM_DOUT14_MODE_V  0x00000003U
-#define LCDCAM_DOUT14_MODE_S  28
-/** LCDCAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0;
- *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
- *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
- *  LCD_CLK.
- */
-#define LCDCAM_DOUT15_MODE    0x00000003U
-#define LCDCAM_DOUT15_MODE_M  (LCDCAM_DOUT15_MODE_V << LCDCAM_DOUT15_MODE_S)
-#define LCDCAM_DOUT15_MODE_V  0x00000003U
-#define LCDCAM_DOUT15_MODE_S  30
-
-/** LCDCAM_LC_DMA_INT_ENA_REG register
- *  LCDCAM interrupt enable register.
- */
-#define LCDCAM_LC_DMA_INT_ENA_REG (DR_REG_LCDCAM_BASE + 0x64)
-/** LCDCAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for LCD frame end interrupt.
- */
-#define LCDCAM_LCD_VSYNC_INT_ENA    (BIT(0))
-#define LCDCAM_LCD_VSYNC_INT_ENA_M  (LCDCAM_LCD_VSYNC_INT_ENA_V << LCDCAM_LCD_VSYNC_INT_ENA_S)
-#define LCDCAM_LCD_VSYNC_INT_ENA_V  0x00000001U
-#define LCDCAM_LCD_VSYNC_INT_ENA_S  0
-/** LCDCAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for lcd transfer end interrupt.
- */
-#define LCDCAM_LCD_TRANS_DONE_INT_ENA    (BIT(1))
-#define LCDCAM_LCD_TRANS_DONE_INT_ENA_M  (LCDCAM_LCD_TRANS_DONE_INT_ENA_V << LCDCAM_LCD_TRANS_DONE_INT_ENA_S)
-#define LCDCAM_LCD_TRANS_DONE_INT_ENA_V  0x00000001U
-#define LCDCAM_LCD_TRANS_DONE_INT_ENA_S  1
-/** LCDCAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for Camera frame end interrupt.
- */
-#define LCDCAM_CAM_VSYNC_INT_ENA    (BIT(2))
-#define LCDCAM_CAM_VSYNC_INT_ENA_M  (LCDCAM_CAM_VSYNC_INT_ENA_V << LCDCAM_CAM_VSYNC_INT_ENA_S)
-#define LCDCAM_CAM_VSYNC_INT_ENA_V  0x00000001U
-#define LCDCAM_CAM_VSYNC_INT_ENA_S  2
-/** LCDCAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for Camera line interrupt.
- */
-#define LCDCAM_CAM_HS_INT_ENA    (BIT(3))
-#define LCDCAM_CAM_HS_INT_ENA_M  (LCDCAM_CAM_HS_INT_ENA_V << LCDCAM_CAM_HS_INT_ENA_S)
-#define LCDCAM_CAM_HS_INT_ENA_V  0x00000001U
-#define LCDCAM_CAM_HS_INT_ENA_S  3
-
-/** LCDCAM_LC_DMA_INT_RAW_REG register
- *  LCDCAM interrupt raw register, valid in level.
- */
-#define LCDCAM_LC_DMA_INT_RAW_REG (DR_REG_LCDCAM_BASE + 0x68)
-/** LCDCAM_LCD_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit for LCD frame end interrupt.
- */
-#define LCDCAM_LCD_VSYNC_INT_RAW    (BIT(0))
-#define LCDCAM_LCD_VSYNC_INT_RAW_M  (LCDCAM_LCD_VSYNC_INT_RAW_V << LCDCAM_LCD_VSYNC_INT_RAW_S)
-#define LCDCAM_LCD_VSYNC_INT_RAW_V  0x00000001U
-#define LCDCAM_LCD_VSYNC_INT_RAW_S  0
-/** LCDCAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit for lcd transfer end interrupt.
- */
-#define LCDCAM_LCD_TRANS_DONE_INT_RAW    (BIT(1))
-#define LCDCAM_LCD_TRANS_DONE_INT_RAW_M  (LCDCAM_LCD_TRANS_DONE_INT_RAW_V << LCDCAM_LCD_TRANS_DONE_INT_RAW_S)
-#define LCDCAM_LCD_TRANS_DONE_INT_RAW_V  0x00000001U
-#define LCDCAM_LCD_TRANS_DONE_INT_RAW_S  1
-/** LCDCAM_CAM_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for Camera frame end interrupt.
- */
-#define LCDCAM_CAM_VSYNC_INT_RAW    (BIT(2))
-#define LCDCAM_CAM_VSYNC_INT_RAW_M  (LCDCAM_CAM_VSYNC_INT_RAW_V << LCDCAM_CAM_VSYNC_INT_RAW_S)
-#define LCDCAM_CAM_VSYNC_INT_RAW_V  0x00000001U
-#define LCDCAM_CAM_VSYNC_INT_RAW_S  2
-/** LCDCAM_CAM_HS_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for Camera line interrupt.
- */
-#define LCDCAM_CAM_HS_INT_RAW    (BIT(3))
-#define LCDCAM_CAM_HS_INT_RAW_M  (LCDCAM_CAM_HS_INT_RAW_V << LCDCAM_CAM_HS_INT_RAW_S)
-#define LCDCAM_CAM_HS_INT_RAW_V  0x00000001U
-#define LCDCAM_CAM_HS_INT_RAW_S  3
-
-/** LCDCAM_LC_DMA_INT_ST_REG register
- *  LCDCAM interrupt status register.
- */
-#define LCDCAM_LC_DMA_INT_ST_REG (DR_REG_LCDCAM_BASE + 0x6c)
-/** LCDCAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for LCD frame end interrupt.
- */
-#define LCDCAM_LCD_VSYNC_INT_ST    (BIT(0))
-#define LCDCAM_LCD_VSYNC_INT_ST_M  (LCDCAM_LCD_VSYNC_INT_ST_V << LCDCAM_LCD_VSYNC_INT_ST_S)
-#define LCDCAM_LCD_VSYNC_INT_ST_V  0x00000001U
-#define LCDCAM_LCD_VSYNC_INT_ST_S  0
-/** LCDCAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for lcd transfer end interrupt.
- */
-#define LCDCAM_LCD_TRANS_DONE_INT_ST    (BIT(1))
-#define LCDCAM_LCD_TRANS_DONE_INT_ST_M  (LCDCAM_LCD_TRANS_DONE_INT_ST_V << LCDCAM_LCD_TRANS_DONE_INT_ST_S)
-#define LCDCAM_LCD_TRANS_DONE_INT_ST_V  0x00000001U
-#define LCDCAM_LCD_TRANS_DONE_INT_ST_S  1
-/** LCDCAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for Camera frame end interrupt.
- */
-#define LCDCAM_CAM_VSYNC_INT_ST    (BIT(2))
-#define LCDCAM_CAM_VSYNC_INT_ST_M  (LCDCAM_CAM_VSYNC_INT_ST_V << LCDCAM_CAM_VSYNC_INT_ST_S)
-#define LCDCAM_CAM_VSYNC_INT_ST_V  0x00000001U
-#define LCDCAM_CAM_VSYNC_INT_ST_S  2
-/** LCDCAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for Camera transfer end interrupt.
- */
-#define LCDCAM_CAM_HS_INT_ST    (BIT(3))
-#define LCDCAM_CAM_HS_INT_ST_M  (LCDCAM_CAM_HS_INT_ST_V << LCDCAM_CAM_HS_INT_ST_S)
-#define LCDCAM_CAM_HS_INT_ST_V  0x00000001U
-#define LCDCAM_CAM_HS_INT_ST_S  3
-
-/** LCDCAM_LC_DMA_INT_CLR_REG register
- *  LCDCAM interrupt clear register.
- */
-#define LCDCAM_LC_DMA_INT_CLR_REG (DR_REG_LCDCAM_BASE + 0x70)
-/** LCDCAM_LCD_VSYNC_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for LCD frame end interrupt.
- */
-#define LCDCAM_LCD_VSYNC_INT_CLR    (BIT(0))
-#define LCDCAM_LCD_VSYNC_INT_CLR_M  (LCDCAM_LCD_VSYNC_INT_CLR_V << LCDCAM_LCD_VSYNC_INT_CLR_S)
-#define LCDCAM_LCD_VSYNC_INT_CLR_V  0x00000001U
-#define LCDCAM_LCD_VSYNC_INT_CLR_S  0
-/** LCDCAM_LCD_TRANS_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for lcd transfer end interrupt.
- */
-#define LCDCAM_LCD_TRANS_DONE_INT_CLR    (BIT(1))
-#define LCDCAM_LCD_TRANS_DONE_INT_CLR_M  (LCDCAM_LCD_TRANS_DONE_INT_CLR_V << LCDCAM_LCD_TRANS_DONE_INT_CLR_S)
-#define LCDCAM_LCD_TRANS_DONE_INT_CLR_V  0x00000001U
-#define LCDCAM_LCD_TRANS_DONE_INT_CLR_S  1
-/** LCDCAM_CAM_VSYNC_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for Camera frame end interrupt.
- */
-#define LCDCAM_CAM_VSYNC_INT_CLR    (BIT(2))
-#define LCDCAM_CAM_VSYNC_INT_CLR_M  (LCDCAM_CAM_VSYNC_INT_CLR_V << LCDCAM_CAM_VSYNC_INT_CLR_S)
-#define LCDCAM_CAM_VSYNC_INT_CLR_V  0x00000001U
-#define LCDCAM_CAM_VSYNC_INT_CLR_S  2
-/** LCDCAM_CAM_HS_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for Camera line interrupt.
- */
-#define LCDCAM_CAM_HS_INT_CLR    (BIT(3))
-#define LCDCAM_CAM_HS_INT_CLR_M  (LCDCAM_CAM_HS_INT_CLR_V << LCDCAM_CAM_HS_INT_CLR_S)
-#define LCDCAM_CAM_HS_INT_CLR_V  0x00000001U
-#define LCDCAM_CAM_HS_INT_CLR_S  3
-
-/** LCDCAM_LC_REG_DATE_REG register
- *  Version register
- */
-#define LCDCAM_LC_REG_DATE_REG (DR_REG_LCDCAM_BASE + 0xfc)
-/** LCDCAM_LC_DATE : R/W; bitpos: [27:0]; default: 36712592;
- *  LCD_CAM version control register
- */
-#define LCDCAM_LC_DATE    0x0FFFFFFFU
-#define LCDCAM_LC_DATE_M  (LCDCAM_LC_DATE_V << LCDCAM_LC_DATE_S)
-#define LCDCAM_LC_DATE_V  0x0FFFFFFFU
-#define LCDCAM_LC_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lcdcam_struct.h b/components/soc/esp32p4/include/soc/lcdcam_struct.h
deleted file mode 100644
index 7d79afce3c..0000000000
--- a/components/soc/esp32p4/include/soc/lcdcam_struct.h
+++ /dev/null
@@ -1,855 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: lcd configuration registers */
-/** Type of lcd_clock register
- *  LCD clock config register.
- */
-typedef union {
-    struct {
-        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
-         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
-         */
-        uint32_t lcd_clkcnt_n:6;
-        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
-         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
-         */
-        uint32_t lcd_clk_equ_sysclk:1;
-        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
-         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
-         */
-        uint32_t lcd_ck_idle_edge:1;
-        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
-         *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
-         *  in the second half data cycle.
-         */
-        uint32_t lcd_ck_out_edge:1;
-        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
-         *  Integral LCD clock divider value
-         */
-        uint32_t lcd_clkm_div_num:8;
-        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
-         *  Fractional clock divider numerator value
-         */
-        uint32_t lcd_clkm_div_b:6;
-        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
-         *  Fractional clock divider denominator value
-         */
-        uint32_t lcd_clkm_div_a:6;
-        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
-         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
-         */
-        uint32_t lcd_clk_sel:2;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to enable clk gate
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_clock_reg_t;
-
-/** Type of lcd_rgb_yuv register
- *  LCD YUV/RGB converter configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
-         *  1:invert every two 8bits input data. 2. disabled.
-         */
-        uint32_t lcd_conv_8bits_data_inv:1;
-        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
-         *  0: txtorx mode off. 1: txtorx mode on.
-         */
-        uint32_t lcd_conv_txtorx:1;
-        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
-         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-         *  trans_mode must be set to 1.
-         */
-        uint32_t lcd_conv_yuv2yuv_mode:2;
-        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
-         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-         *  mode of Data_in
-         */
-        uint32_t lcd_conv_yuv_mode:2;
-        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
-         *  0:BT601. 1:BT709.
-         */
-        uint32_t lcd_conv_protocol_mode:1;
-        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
-         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
-         */
-        uint32_t lcd_conv_data_out_mode:1;
-        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
-         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
-         */
-        uint32_t lcd_conv_data_in_mode:1;
-        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
-         *  0: 16bits mode. 1: 8bits mode.
-         */
-        uint32_t lcd_conv_mode_8bits_on:1;
-        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
-         *  0: YUV to RGB. 1: RGB to YUV.
-         */
-        uint32_t lcd_conv_trans_mode:1;
-        /** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
-         *  0: Bypass converter. 1: Enable converter.
-         */
-        uint32_t lcd_conv_enable:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_rgb_yuv_reg_t;
-
-/** Type of lcd_user register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
-         *  The output data cycles minus 1 of LCD module.
-         */
-        uint32_t lcd_dout_cyclelen:13;
-        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
-         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
-         *  reg_lcd_reset is set.
-         */
-        uint32_t lcd_always_out_en:1;
-        /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
-         *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
-         */
-        uint32_t lcd_dout_byte_swizzle_mode:3;
-        /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
-         *  1: enable byte swizzle 0: disable
-         */
-        uint32_t lcd_dout_byte_swizzle_enable:1;
-        /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
-         *  1: change bit order in every byte. 0: Not change.
-         */
-        uint32_t lcd_dout_bit_order:1;
-        /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
-         *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
-         */
-        uint32_t lcd_byte_mode:2;
-        /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
-         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
-         */
-        uint32_t lcd_update_reg:1;
-        /** lcd_bit_order : R/W; bitpos: [22]; default: 0;
-         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
-         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
-         */
-        uint32_t lcd_bit_order:1;
-        /** lcd_byte_order : R/W; bitpos: [23]; default: 0;
-         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
-         */
-        uint32_t lcd_byte_order:1;
-        /** lcd_dout : R/W; bitpos: [24]; default: 0;
-         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
-         */
-        uint32_t lcd_dout:1;
-        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
-         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
-         */
-        uint32_t lcd_dummy:1;
-        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
-         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
-         */
-        uint32_t lcd_cmd:1;
-        /** lcd_start : R/W/SC; bitpos: [27]; default: 0;
-         *  LCD start sending data enable signal, valid in high level.
-         */
-        uint32_t lcd_start:1;
-        /** lcd_reset : WT; bitpos: [28]; default: 0;
-         *  The value of  command.
-         */
-        uint32_t lcd_reset:1;
-        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
-         *  The dummy cycle length minus 1.
-         */
-        uint32_t lcd_dummy_cyclelen:2;
-        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
-         *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
-         */
-        uint32_t lcd_cmd_2_cycle_en:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_user_reg_t;
-
-/** Type of lcd_misc register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
-         *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
-         */
-        uint32_t lcd_wire_mode:2;
-        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
-         *  The setup cycle length minus 1 in LCD non-RGB mode.
-         */
-        uint32_t lcd_vfk_cyclelen:6;
-        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
-         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
-         *  time cycle length in LCD non-RGB mode.
-         */
-        uint32_t lcd_vbk_cyclelen:13;
-        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
-         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
-         *  the current frame is sent out.
-         */
-        uint32_t lcd_next_frame_en:1;
-        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
-         *  1: Enable blank region when LCD sends data out. 0: No blank region.
-         */
-        uint32_t lcd_bk_en:1;
-        /** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
-         *  LCD AFIFO reset signal.
-         */
-        uint32_t lcd_afifo_reset:1;
-        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
-         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
-         *  reg_cd_idle_edge.
-         */
-        uint32_t lcd_cd_data_set:1;
-        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
-         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
-         *  reg_cd_idle_edge.
-         */
-        uint32_t lcd_cd_dummy_set:1;
-        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
-         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
-         *  reg_cd_idle_edge.
-         */
-        uint32_t lcd_cd_cmd_set:1;
-        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
-         *  The default value of LCD_CD.
-         */
-        uint32_t lcd_cd_idle_edge:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_misc_reg_t;
-
-/** Type of lcd_ctrl register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
-         *  It is the horizontal blank front porch of a frame.
-         */
-        uint32_t lcd_hb_front:11;
-        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
-         *  It is the vertical active height of a frame.
-         */
-        uint32_t lcd_va_height:10;
-        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
-         *  It is the vertical total height of a frame.
-         */
-        uint32_t lcd_vt_height:10;
-        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
-         *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
-         */
-        uint32_t lcd_rgb_mode_en:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_ctrl_reg_t;
-
-/** Type of lcd_ctrl1 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
-         *  It is the vertical blank front porch of a frame.
-         */
-        uint32_t lcd_vb_front:8;
-        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
-         *  It is the horizontal active width of a frame.
-         */
-        uint32_t lcd_ha_width:12;
-        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
-         *  It is the horizontal total width of a frame.
-         */
-        uint32_t lcd_ht_width:12;
-    };
-    uint32_t val;
-} lcdcam_lcd_ctrl1_reg_t;
-
-/** Type of lcd_ctrl2 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
-         *  It is the position of LCD_VSYNC active pulse in a line.
-         */
-        uint32_t lcd_vsync_width:7;
-        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
-         *  It is the idle value of LCD_VSYNC.
-         */
-        uint32_t lcd_vsync_idle_pol:1;
-        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
-         *  It is the idle value of LCD_DE.
-         */
-        uint32_t lcd_de_idle_pol:1;
-        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
-         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
-         *  pulse is valid only in active region lines in RGB mode.
-         */
-        uint32_t lcd_hs_blank_en:1;
-        uint32_t reserved_10:6;
-        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
-         *  It is the position of LCD_HSYNC active pulse in a line.
-         */
-        uint32_t lcd_hsync_width:7;
-        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
-         *  It is the idle value of LCD_HSYNC.
-         */
-        uint32_t lcd_hsync_idle_pol:1;
-        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
-         *  It is the position of LCD_HSYNC active pulse in a line.
-         */
-        uint32_t lcd_hsync_position:8;
-    };
-    uint32_t val;
-} lcdcam_lcd_ctrl2_reg_t;
-
-/** Type of lcd_first_cmd_val register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
-         *  The LCD write command value of first cmd cycle.
-         */
-        uint32_t lcd_first_cmd_value:32;
-    };
-    uint32_t val;
-} lcdcam_lcd_first_cmd_val_reg_t;
-
-/** Type of lcd_latter_cmd_val register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
-         *  The LCD write command value of latter cmd cycle.
-         */
-        uint32_t lcd_latter_cmd_value:32;
-    };
-    uint32_t val;
-} lcdcam_lcd_latter_cmd_val_reg_t;
-
-/** Type of lcd_dly_mode_cfg1 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** dout16_mode : R/W; bitpos: [1:0]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout16_mode:2;
-        /** dout17_mode : R/W; bitpos: [3:2]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout17_mode:2;
-        /** dout18_mode : R/W; bitpos: [5:4]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout18_mode:2;
-        /** dout19_mode : R/W; bitpos: [7:6]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout19_mode:2;
-        /** dout20_mode : R/W; bitpos: [9:8]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout20_mode:2;
-        /** dout21_mode : R/W; bitpos: [11:10]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout21_mode:2;
-        /** dout22_mode : R/W; bitpos: [13:12]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout22_mode:2;
-        /** dout23_mode : R/W; bitpos: [15:14]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout23_mode:2;
-        /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
-         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
-         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_cd_mode:2;
-        /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
-         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
-         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_de_mode:2;
-        /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
-         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
-         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_hsync_mode:2;
-        /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
-         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
-         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_vsync_mode:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lcdcam_lcd_dly_mode_cfg1_reg_t;
-
-/** Type of lcd_dly_mode_cfg2 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout0_mode:2;
-        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout1_mode:2;
-        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout2_mode:2;
-        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout3_mode:2;
-        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout4_mode:2;
-        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout5_mode:2;
-        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout6_mode:2;
-        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout7_mode:2;
-        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout8_mode:2;
-        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout9_mode:2;
-        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout10_mode:2;
-        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout11_mode:2;
-        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout12_mode:2;
-        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout13_mode:2;
-        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout14_mode:2;
-        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout15_mode:2;
-    };
-    uint32_t val;
-} lcdcam_lcd_dly_mode_cfg2_reg_t;
-
-
-/** Group: cam configuration registers */
-/** Type of cam_ctrl register
- *  CAM config register.
- */
-typedef union {
-    struct {
-        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
-         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
-         */
-        uint32_t cam_stop_en:1;
-        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
-         *  Filter threshold value for CAM_VSYNC signal.
-         */
-        uint32_t cam_vsync_filter_thres:3;
-        /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
-         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
-         */
-        uint32_t cam_update_reg:1;
-        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
-         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
-         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
-         */
-        uint32_t cam_byte_order:1;
-        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
-         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
-         */
-        uint32_t cam_bit_order:1;
-        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
-         *  1: Enable to generate CAM_HS_INT. 0: Disable.
-         */
-        uint32_t cam_line_int_en:1;
-        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
-         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
-         *  reg_cam_rec_data_cyclelen.
-         */
-        uint32_t cam_vs_eof_en:1;
-        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
-         *  Integral Camera clock divider value
-         */
-        uint32_t cam_clkm_div_num:8;
-        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
-         *  Fractional clock divider numerator value
-         */
-        uint32_t cam_clkm_div_b:6;
-        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
-         *  Fractional clock divider denominator value
-         */
-        uint32_t cam_clkm_div_a:6;
-        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
-         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
-         */
-        uint32_t cam_clk_sel:2;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} lcdcam_cam_ctrl_reg_t;
-
-/** Type of cam_ctrl1 register
- *  CAM config register.
- */
-typedef union {
-    struct {
-        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
-         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
-         */
-        uint32_t cam_rec_data_bytelen:16;
-        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
-         *  The line number minus 1 to generate cam_hs_int.
-         */
-        uint32_t cam_line_int_num:6;
-        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
-         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
-         */
-        uint32_t cam_clk_inv:1;
-        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
-         *  1: Enable CAM_VSYNC filter function. 0: bypass.
-         */
-        uint32_t cam_vsync_filter_en:1;
-        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
-         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
-         */
-        uint32_t cam_2byte_en:1;
-        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
-         *  CAM_DE invert enable signal, valid in high level.
-         */
-        uint32_t cam_de_inv:1;
-        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
-         *  CAM_HSYNC invert enable signal, valid in high level.
-         */
-        uint32_t cam_hsync_inv:1;
-        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
-         *  CAM_VSYNC invert enable signal, valid in high level.
-         */
-        uint32_t cam_vsync_inv:1;
-        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
-         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
-         *  signals are CAM_DE and CAM_VSYNC.
-         */
-        uint32_t cam_vh_de_mode_en:1;
-        /** cam_start : R/W/SC; bitpos: [29]; default: 0;
-         *  Camera module start signal.
-         */
-        uint32_t cam_start:1;
-        /** cam_reset : WT; bitpos: [30]; default: 0;
-         *  Camera module reset signal.
-         */
-        uint32_t cam_reset:1;
-        /** cam_afifo_reset : WT; bitpos: [31]; default: 0;
-         *  Camera AFIFO reset signal.
-         */
-        uint32_t cam_afifo_reset:1;
-    };
-    uint32_t val;
-} lcdcam_cam_ctrl1_reg_t;
-
-/** Type of cam_rgb_yuv register
- *  CAM YUV/RGB converter configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
-         *  1:invert every two 8bits input data. 2. disabled.
-         */
-        uint32_t cam_conv_8bits_data_inv:1;
-        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
-         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-         *  trans_mode must be set to 1.
-         */
-        uint32_t cam_conv_yuv2yuv_mode:2;
-        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
-         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-         *  mode of Data_in
-         */
-        uint32_t cam_conv_yuv_mode:2;
-        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
-         *  0:BT601. 1:BT709.
-         */
-        uint32_t cam_conv_protocol_mode:1;
-        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
-         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
-         */
-        uint32_t cam_conv_data_out_mode:1;
-        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
-         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
-         */
-        uint32_t cam_conv_data_in_mode:1;
-        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
-         *  0: 16bits mode. 1: 8bits mode.
-         */
-        uint32_t cam_conv_mode_8bits_on:1;
-        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
-         *  0: YUV to RGB. 1: RGB to YUV.
-         */
-        uint32_t cam_conv_trans_mode:1;
-        /** cam_conv_enable : R/W; bitpos: [31]; default: 0;
-         *  0: Bypass converter. 1: Enable converter.
-         */
-        uint32_t cam_conv_enable:1;
-    };
-    uint32_t val;
-} lcdcam_cam_rgb_yuv_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of lc_dma_int_ena register
- *  LCDCAM interrupt enable register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_ena:1;
-        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_ena:1;
-        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_ena:1;
-        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for Camera line interrupt.
-         */
-        uint32_t cam_hs_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_ena_reg_t;
-
-/** Type of lc_dma_int_raw register
- *  LCDCAM interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_raw:1;
-        /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_raw:1;
-        /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_raw:1;
-        /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for Camera line interrupt.
-         */
-        uint32_t cam_hs_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_raw_reg_t;
-
-/** Type of lc_dma_int_st register
- *  LCDCAM interrupt status register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_st:1;
-        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_st:1;
-        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_st:1;
-        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for Camera transfer end interrupt.
-         */
-        uint32_t cam_hs_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_st_reg_t;
-
-/** Type of lc_dma_int_clr register
- *  LCDCAM interrupt clear register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_clr:1;
-        /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_clr:1;
-        /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_clr:1;
-        /** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for Camera line interrupt.
-         */
-        uint32_t cam_hs_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_clr_reg_t;
-
-
-/** Group: Version register */
-/** Type of lc_reg_date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** lc_date : R/W; bitpos: [27:0]; default: 36712592;
-         *  LCD_CAM version control register
-         */
-        uint32_t lc_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lcdcam_lc_reg_date_reg_t;
-
-
-typedef struct lcd_cam_dev_s {
-    volatile lcdcam_lcd_clock_reg_t lcd_clock;
-    volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
-    volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
-    volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
-    volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
-    volatile lcdcam_lcd_user_reg_t lcd_user;
-    volatile lcdcam_lcd_misc_reg_t lcd_misc;
-    volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
-    volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
-    volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
-    volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
-    volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
-    volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
-    uint32_t reserved_034;
-    volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
-    uint32_t reserved_03c[10];
-    volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
-    volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
-    volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
-    volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
-    uint32_t reserved_074[34];
-    volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
-} lcdcam_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_aon_reg.h b/components/soc/esp32p4/include/soc/lp_aon_reg.h
deleted file mode 100644
index 07d035f462..0000000000
--- a/components/soc/esp32p4/include/soc/lp_aon_reg.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_AON_STORE0_REG register
- *  need_des
- */
-#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
-/** LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE0    0xFFFFFFFFU
-#define LP_AON_STORE0_M  (LP_AON_STORE0_V << LP_AON_STORE0_S)
-#define LP_AON_STORE0_V  0xFFFFFFFFU
-#define LP_AON_STORE0_S  0
-
-/** LP_AON_STORE1_REG register
- *  need_des
- */
-#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
-/** LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE1    0xFFFFFFFFU
-#define LP_AON_STORE1_M  (LP_AON_STORE1_V << LP_AON_STORE1_S)
-#define LP_AON_STORE1_V  0xFFFFFFFFU
-#define LP_AON_STORE1_S  0
-
-/** LP_AON_STORE2_REG register
- *  need_des
- */
-#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
-/** LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE2    0xFFFFFFFFU
-#define LP_AON_STORE2_M  (LP_AON_STORE2_V << LP_AON_STORE2_S)
-#define LP_AON_STORE2_V  0xFFFFFFFFU
-#define LP_AON_STORE2_S  0
-
-/** LP_AON_STORE3_REG register
- *  need_des
- */
-#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
-/** LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE3    0xFFFFFFFFU
-#define LP_AON_STORE3_M  (LP_AON_STORE3_V << LP_AON_STORE3_S)
-#define LP_AON_STORE3_V  0xFFFFFFFFU
-#define LP_AON_STORE3_S  0
-
-/** LP_AON_STORE4_REG register
- *  need_des
- */
-#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
-/** LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE4    0xFFFFFFFFU
-#define LP_AON_STORE4_M  (LP_AON_STORE4_V << LP_AON_STORE4_S)
-#define LP_AON_STORE4_V  0xFFFFFFFFU
-#define LP_AON_STORE4_S  0
-
-/** LP_AON_STORE5_REG register
- *  need_des
- */
-#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
-/** LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE5    0xFFFFFFFFU
-#define LP_AON_STORE5_M  (LP_AON_STORE5_V << LP_AON_STORE5_S)
-#define LP_AON_STORE5_V  0xFFFFFFFFU
-#define LP_AON_STORE5_S  0
-
-/** LP_AON_STORE6_REG register
- *  need_des
- */
-#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
-/** LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE6    0xFFFFFFFFU
-#define LP_AON_STORE6_M  (LP_AON_STORE6_V << LP_AON_STORE6_S)
-#define LP_AON_STORE6_V  0xFFFFFFFFU
-#define LP_AON_STORE6_S  0
-
-/** LP_AON_STORE7_REG register
- *  need_des
- */
-#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
-/** LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE7    0xFFFFFFFFU
-#define LP_AON_STORE7_M  (LP_AON_STORE7_V << LP_AON_STORE7_S)
-#define LP_AON_STORE7_V  0xFFFFFFFFU
-#define LP_AON_STORE7_S  0
-
-/** LP_AON_STORE8_REG register
- *  need_des
- */
-#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
-/** LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE8    0xFFFFFFFFU
-#define LP_AON_STORE8_M  (LP_AON_STORE8_V << LP_AON_STORE8_S)
-#define LP_AON_STORE8_V  0xFFFFFFFFU
-#define LP_AON_STORE8_S  0
-
-/** LP_AON_STORE9_REG register
- *  need_des
- */
-#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
-/** LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_STORE9    0xFFFFFFFFU
-#define LP_AON_STORE9_M  (LP_AON_STORE9_V << LP_AON_STORE9_S)
-#define LP_AON_STORE9_V  0xFFFFFFFFU
-#define LP_AON_STORE9_S  0
-
-/** LP_AON_GPIO_MUX_REG register
- *  need_des
- */
-#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
-/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define LP_AON_GPIO_MUX_SEL    0x000000FFU
-#define LP_AON_GPIO_MUX_SEL_M  (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
-#define LP_AON_GPIO_MUX_SEL_V  0x000000FFU
-#define LP_AON_GPIO_MUX_SEL_S  0
-
-/** LP_AON_GPIO_HOLD0_REG register
- *  need_des
- */
-#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
-/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_GPIO_HOLD0    0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD0_M  (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
-#define LP_AON_GPIO_HOLD0_V  0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD0_S  0
-
-/** LP_AON_GPIO_HOLD1_REG register
- *  need_des
- */
-#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
-/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_GPIO_HOLD1    0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD1_M  (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
-#define LP_AON_GPIO_HOLD1_V  0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD1_S  0
-
-/** LP_AON_SYS_CFG_REG register
- *  need_des
- */
-#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
-/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AON_FORCE_DOWNLOAD_BOOT    (BIT(30))
-#define LP_AON_FORCE_DOWNLOAD_BOOT_M  (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
-#define LP_AON_FORCE_DOWNLOAD_BOOT_V  0x00000001U
-#define LP_AON_FORCE_DOWNLOAD_BOOT_S  30
-/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_HPSYS_SW_RESET    (BIT(31))
-#define LP_AON_HPSYS_SW_RESET_M  (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
-#define LP_AON_HPSYS_SW_RESET_V  0x00000001U
-#define LP_AON_HPSYS_SW_RESET_S  31
-
-/** LP_AON_CPUCORE0_CFG_REG register
- *  need_des
- */
-#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
-/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_SW_STALL    0x000000FFU
-#define LP_AON_CPU_CORE0_SW_STALL_M  (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
-#define LP_AON_CPU_CORE0_SW_STALL_V  0x000000FFU
-#define LP_AON_CPU_CORE0_SW_STALL_S  0
-/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_SW_RESET    (BIT(28))
-#define LP_AON_CPU_CORE0_SW_RESET_M  (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
-#define LP_AON_CPU_CORE0_SW_RESET_V  0x00000001U
-#define LP_AON_CPU_CORE0_SW_RESET_S  28
-/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET    (BIT(29))
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M  (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V  0x00000001U
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S  29
-/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL    (BIT(30))
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M  (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V  0x00000001U
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S  30
-/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_DRESET_MASK    (BIT(31))
-#define LP_AON_CPU_CORE0_DRESET_MASK_M  (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
-#define LP_AON_CPU_CORE0_DRESET_MASK_V  0x00000001U
-#define LP_AON_CPU_CORE0_DRESET_MASK_S  31
-
-/** LP_AON_IO_MUX_REG register
- *  need_des
- */
-#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
-/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_IO_MUX_RESET_DISABLE    (BIT(31))
-#define LP_AON_IO_MUX_RESET_DISABLE_M  (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
-#define LP_AON_IO_MUX_RESET_DISABLE_V  0x00000001U
-#define LP_AON_IO_MUX_RESET_DISABLE_S  31
-
-/** LP_AON_EXT_WAKEUP_CNTL_REG register
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
-/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_STATUS    0x000000FFU
-#define LP_AON_EXT_WAKEUP_STATUS_M  (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
-#define LP_AON_EXT_WAKEUP_STATUS_V  0x000000FFU
-#define LP_AON_EXT_WAKEUP_STATUS_S  0
-/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_STATUS_CLR    (BIT(14))
-#define LP_AON_EXT_WAKEUP_STATUS_CLR_M  (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
-#define LP_AON_EXT_WAKEUP_STATUS_CLR_V  0x00000001U
-#define LP_AON_EXT_WAKEUP_STATUS_CLR_S  14
-/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_SEL    0x000000FFU
-#define LP_AON_EXT_WAKEUP_SEL_M  (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
-#define LP_AON_EXT_WAKEUP_SEL_V  0x000000FFU
-#define LP_AON_EXT_WAKEUP_SEL_S  15
-/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_LV    0x000000FFU
-#define LP_AON_EXT_WAKEUP_LV_M  (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
-#define LP_AON_EXT_WAKEUP_LV_V  0x000000FFU
-#define LP_AON_EXT_WAKEUP_LV_S  23
-/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_FILTER    (BIT(31))
-#define LP_AON_EXT_WAKEUP_FILTER_M  (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
-#define LP_AON_EXT_WAKEUP_FILTER_V  0x00000001U
-#define LP_AON_EXT_WAKEUP_FILTER_S  31
-
-/** LP_AON_USB_REG register
- *  need_des
- */
-#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
-/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_USB_RESET_DISABLE    (BIT(31))
-#define LP_AON_USB_RESET_DISABLE_M  (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
-#define LP_AON_USB_RESET_DISABLE_V  0x00000001U
-#define LP_AON_USB_RESET_DISABLE_S  31
-
-/** LP_AON_LPBUS_REG register
- *  need_des
- */
-#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
-/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0;
- *  This field controls fast memory WPULSE parameter.
- */
-#define LP_AON_FAST_MEM_WPULSE    0x00000007U
-#define LP_AON_FAST_MEM_WPULSE_M  (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S)
-#define LP_AON_FAST_MEM_WPULSE_V  0x00000007U
-#define LP_AON_FAST_MEM_WPULSE_S  16
-/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4;
- *  This field controls fast memory WA parameter.
- */
-#define LP_AON_FAST_MEM_WA    0x00000007U
-#define LP_AON_FAST_MEM_WA_M  (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S)
-#define LP_AON_FAST_MEM_WA_V  0x00000007U
-#define LP_AON_FAST_MEM_WA_S  19
-/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0;
- *  This field controls fast memory RA parameter.
- */
-#define LP_AON_FAST_MEM_RA    0x00000003U
-#define LP_AON_FAST_MEM_RA_M  (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S)
-#define LP_AON_FAST_MEM_RA_V  0x00000003U
-#define LP_AON_FAST_MEM_RA_S  22
-/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE    (BIT(28))
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M  (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S  28
-/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS    (BIT(29))
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M  (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S  29
-/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE    (BIT(30))
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M  (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S  30
-/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_SEL    (BIT(31))
-#define LP_AON_FAST_MEM_MUX_SEL_M  (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
-#define LP_AON_FAST_MEM_MUX_SEL_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_SEL_S  31
-
-/** LP_AON_SDIO_ACTIVE_REG register
- *  need_des
- */
-#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
-/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
- *  need_des
- */
-#define LP_AON_SDIO_ACT_DNUM    0x000003FFU
-#define LP_AON_SDIO_ACT_DNUM_M  (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
-#define LP_AON_SDIO_ACT_DNUM_V  0x000003FFU
-#define LP_AON_SDIO_ACT_DNUM_S  22
-
-/** LP_AON_LPCORE_REG register
- *  need_des
- */
-#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
-/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR    (BIT(0))
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S  0
-/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG    (BIT(1))
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V  0x00000001U
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S  1
-/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_LPCORE_DISABLE    (BIT(31))
-#define LP_AON_LPCORE_DISABLE_M  (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
-#define LP_AON_LPCORE_DISABLE_V  0x00000001U
-#define LP_AON_LPCORE_DISABLE_S  31
-
-/** LP_AON_SAR_CCT_REG register
- *  need_des
- */
-#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
-/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
- *  need_des
- */
-#define LP_AON_SAR2_PWDET_CCT    0x00000007U
-#define LP_AON_SAR2_PWDET_CCT_M  (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
-#define LP_AON_SAR2_PWDET_CCT_V  0x00000007U
-#define LP_AON_SAR2_PWDET_CCT_S  29
-
-/** LP_AON_DATE_REG register
- *  need_des
- */
-#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
-/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704;
- *  need_des
- */
-#define LP_AON_DATE    0x7FFFFFFFU
-#define LP_AON_DATE_M  (LP_AON_DATE_V << LP_AON_DATE_S)
-#define LP_AON_DATE_V  0x7FFFFFFFU
-#define LP_AON_DATE_S  0
-/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_CLK_EN    (BIT(31))
-#define LP_AON_CLK_EN_M  (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
-#define LP_AON_CLK_EN_V  0x00000001U
-#define LP_AON_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_aon_struct.h b/components/soc/esp32p4/include/soc/lp_aon_struct.h
deleted file mode 100644
index 372d3b06ea..0000000000
--- a/components/soc/esp32p4/include/soc/lp_aon_struct.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of store register
- *  need_des
- */
-typedef union {
-    struct {
-        /** store : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t store:32;
-    };
-    uint32_t val;
-} lp_aon_store_reg_t;
-
-/** Type of gpio_mux register
- *  need_des
- */
-typedef union {
-    struct {
-        /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t gpio_mux_sel:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_aon_gpio_mux_reg_t;
-
-/** Type of gpio_hold0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t gpio_hold0:32;
-    };
-    uint32_t val;
-} lp_aon_gpio_hold0_reg_t;
-
-/** Type of gpio_hold1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t gpio_hold1:32;
-    };
-    uint32_t val;
-} lp_aon_gpio_hold1_reg_t;
-
-/** Type of sys_cfg register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** force_download_boot : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t force_download_boot:1;
-        /** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hpsys_sw_reset:1;
-    };
-    uint32_t val;
-} lp_aon_sys_cfg_reg_t;
-
-/** Type of cpucore0_cfg register
- *  need_des
- */
-typedef union {
-    struct {
-        /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_sw_stall:8;
-        uint32_t reserved_8:20;
-        /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_sw_reset:1;
-        /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_ocd_halt_on_reset:1;
-        /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
-         *  need_des
-         */
-        uint32_t cpu_core0_stat_vector_sel:1;
-        /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_dreset_mask:1;
-    };
-    uint32_t val;
-} lp_aon_cpucore0_cfg_reg_t;
-
-/** Type of io_mux register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t io_mux_reset_disable:1;
-    };
-    uint32_t val;
-} lp_aon_io_mux_reg_t;
-
-/** Type of ext_wakeup_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_status:8;
-        uint32_t reserved_8:6;
-        /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_status_clr:1;
-        /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_sel:8;
-        /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_lv:8;
-        /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_filter:1;
-    };
-    uint32_t val;
-} lp_aon_ext_wakeup_cntl_reg_t;
-
-/** Type of usb register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** usb_reset_disable : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t usb_reset_disable:1;
-    };
-    uint32_t val;
-} lp_aon_usb_reg_t;
-
-/** Type of lpbus register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0;
-         *  This field controls fast memory WPULSE parameter.
-         */
-        uint32_t fast_mem_wpulse:3;
-        /** fast_mem_wa : R/W; bitpos: [21:19]; default: 4;
-         *  This field controls fast memory WA parameter.
-         */
-        uint32_t fast_mem_wa:3;
-        /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0;
-         *  This field controls fast memory RA parameter.
-         */
-        uint32_t fast_mem_ra:2;
-        uint32_t reserved_24:4;
-        /** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_fsm_idle:1;
-        /** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_sel_status:1;
-        /** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_sel_update:1;
-        /** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_sel:1;
-    };
-    uint32_t val;
-} lp_aon_lpbus_reg_t;
-
-/** Type of sdio_active register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
-         *  need_des
-         */
-        uint32_t sdio_act_dnum:10;
-    };
-    uint32_t val;
-} lp_aon_sdio_active_reg_t;
-
-/** Type of lpcore register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_etm_wakeup_flag_clr:1;
-        /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_etm_wakeup_flag:1;
-        uint32_t reserved_2:29;
-        /** lpcore_disable : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_disable:1;
-    };
-    uint32_t val;
-} lp_aon_lpcore_reg_t;
-
-/** Type of sar_cct register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:29;
-        /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
-         *  need_des
-         */
-        uint32_t sar2_pwdet_cct:3;
-    };
-    uint32_t val;
-} lp_aon_sar_cct_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [30:0]; default: 35672704;
-         *  need_des
-         */
-        uint32_t date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_aon_date_reg_t;
-
-
-typedef struct lp_aon_dev_t {
-    volatile lp_aon_store_reg_t store[10];
-    volatile lp_aon_gpio_mux_reg_t gpio_mux;
-    volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
-    volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
-    volatile lp_aon_sys_cfg_reg_t sys_cfg;
-    volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
-    volatile lp_aon_io_mux_reg_t io_mux;
-    volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
-    volatile lp_aon_usb_reg_t usb;
-    volatile lp_aon_lpbus_reg_t lpbus;
-    volatile lp_aon_sdio_active_reg_t sdio_active;
-    volatile lp_aon_lpcore_reg_t lpcore;
-    volatile lp_aon_sar_cct_reg_t sar_cct;
-    uint32_t reserved_058[233];
-    volatile lp_aon_date_reg_t date;
-} lp_aon_dev_t;
-
-extern lp_aon_dev_t LP_AON;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h b/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h
deleted file mode 100644
index 901915903a..0000000000
--- a/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h
+++ /dev/null
@@ -1,1036 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_AONCLKRST_LP_CLK_CONF_REG register
- *  need_des
- */
-#define LP_AONCLKRST_LP_CLK_CONF_REG (DR_REG_LP_AONCLKRST_BASE + 0x0)
-/** LP_AONCLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_SLOW_CLK_SEL    0x00000003U
-#define LP_AONCLKRST_SLOW_CLK_SEL_M  (LP_AONCLKRST_SLOW_CLK_SEL_V << LP_AONCLKRST_SLOW_CLK_SEL_S)
-#define LP_AONCLKRST_SLOW_CLK_SEL_V  0x00000003U
-#define LP_AONCLKRST_SLOW_CLK_SEL_S  0
-/** LP_AONCLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
- *  need_des
- */
-#define LP_AONCLKRST_FAST_CLK_SEL    0x00000003U
-#define LP_AONCLKRST_FAST_CLK_SEL_M  (LP_AONCLKRST_FAST_CLK_SEL_V << LP_AONCLKRST_FAST_CLK_SEL_S)
-#define LP_AONCLKRST_FAST_CLK_SEL_V  0x00000003U
-#define LP_AONCLKRST_FAST_CLK_SEL_S  2
-/** LP_AONCLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_LP_PERI_DIV_NUM    0x0000003FU
-#define LP_AONCLKRST_LP_PERI_DIV_NUM_M  (LP_AONCLKRST_LP_PERI_DIV_NUM_V << LP_AONCLKRST_LP_PERI_DIV_NUM_S)
-#define LP_AONCLKRST_LP_PERI_DIV_NUM_V  0x0000003FU
-#define LP_AONCLKRST_LP_PERI_DIV_NUM_S  4
-/** LP_AONCLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_ANA_SEL_REF_PLL8M    (BIT(10))
-#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_M  (LP_AONCLKRST_ANA_SEL_REF_PLL8M_V << LP_AONCLKRST_ANA_SEL_REF_PLL8M_S)
-#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_V  0x00000001U
-#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_S  10
-
-/** LP_AONCLKRST_LP_CLK_PO_EN_REG register
- *  need_des
- */
-#define LP_AONCLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0x4)
-/** LP_AONCLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN    (BIT(0))
-#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_M  (LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V << LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S)
-#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S  0
-/** LP_AONCLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_LP_BUS_OEN    (BIT(1))
-#define LP_AONCLKRST_CLK_LP_BUS_OEN_M  (LP_AONCLKRST_CLK_LP_BUS_OEN_V << LP_AONCLKRST_CLK_LP_BUS_OEN_S)
-#define LP_AONCLKRST_CLK_LP_BUS_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_LP_BUS_OEN_S  1
-/** LP_AONCLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_AON_SLOW_OEN    (BIT(2))
-#define LP_AONCLKRST_CLK_AON_SLOW_OEN_M  (LP_AONCLKRST_CLK_AON_SLOW_OEN_V << LP_AONCLKRST_CLK_AON_SLOW_OEN_S)
-#define LP_AONCLKRST_CLK_AON_SLOW_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_AON_SLOW_OEN_S  2
-/** LP_AONCLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_AON_FAST_OEN    (BIT(3))
-#define LP_AONCLKRST_CLK_AON_FAST_OEN_M  (LP_AONCLKRST_CLK_AON_FAST_OEN_V << LP_AONCLKRST_CLK_AON_FAST_OEN_S)
-#define LP_AONCLKRST_CLK_AON_FAST_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_AON_FAST_OEN_S  3
-/** LP_AONCLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_SLOW_OEN    (BIT(4))
-#define LP_AONCLKRST_CLK_SLOW_OEN_M  (LP_AONCLKRST_CLK_SLOW_OEN_V << LP_AONCLKRST_CLK_SLOW_OEN_S)
-#define LP_AONCLKRST_CLK_SLOW_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_SLOW_OEN_S  4
-/** LP_AONCLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_FAST_OEN    (BIT(5))
-#define LP_AONCLKRST_CLK_FAST_OEN_M  (LP_AONCLKRST_CLK_FAST_OEN_V << LP_AONCLKRST_CLK_FAST_OEN_S)
-#define LP_AONCLKRST_CLK_FAST_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_FAST_OEN_S  5
-/** LP_AONCLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_FOSC_OEN    (BIT(6))
-#define LP_AONCLKRST_CLK_FOSC_OEN_M  (LP_AONCLKRST_CLK_FOSC_OEN_V << LP_AONCLKRST_CLK_FOSC_OEN_S)
-#define LP_AONCLKRST_CLK_FOSC_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_FOSC_OEN_S  6
-/** LP_AONCLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_RC32K_OEN    (BIT(7))
-#define LP_AONCLKRST_CLK_RC32K_OEN_M  (LP_AONCLKRST_CLK_RC32K_OEN_V << LP_AONCLKRST_CLK_RC32K_OEN_S)
-#define LP_AONCLKRST_CLK_RC32K_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_RC32K_OEN_S  7
-/** LP_AONCLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_SXTAL_OEN    (BIT(8))
-#define LP_AONCLKRST_CLK_SXTAL_OEN_M  (LP_AONCLKRST_CLK_SXTAL_OEN_V << LP_AONCLKRST_CLK_SXTAL_OEN_S)
-#define LP_AONCLKRST_CLK_SXTAL_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_SXTAL_OEN_S  8
-/** LP_AONCLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0;
- *  1'b1: probe sosc clk on
- *  1'b0: probe sosc clk off
- */
-#define LP_AONCLKRST_CLK_SOSC_OEN    (BIT(9))
-#define LP_AONCLKRST_CLK_SOSC_OEN_M  (LP_AONCLKRST_CLK_SOSC_OEN_V << LP_AONCLKRST_CLK_SOSC_OEN_S)
-#define LP_AONCLKRST_CLK_SOSC_OEN_V  0x00000001U
-#define LP_AONCLKRST_CLK_SOSC_OEN_S  9
-
-/** LP_AONCLKRST_LP_CLK_EN_REG register
- *  need_des
- */
-#define LP_AONCLKRST_LP_CLK_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0x8)
-/** LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON    (BIT(26))
-#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_M  (LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_S)
-#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_V  0x00000001U
-#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_S  26
-/** LP_AONCLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1;
- *  need_des
- */
-#define LP_AONCLKRST_CK_EN_LP_RAM    (BIT(27))
-#define LP_AONCLKRST_CK_EN_LP_RAM_M  (LP_AONCLKRST_CK_EN_LP_RAM_V << LP_AONCLKRST_CK_EN_LP_RAM_S)
-#define LP_AONCLKRST_CK_EN_LP_RAM_V  0x00000001U
-#define LP_AONCLKRST_CK_EN_LP_RAM_S  27
-/** LP_AONCLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_ETM_EVENT_TICK_EN    (BIT(28))
-#define LP_AONCLKRST_ETM_EVENT_TICK_EN_M  (LP_AONCLKRST_ETM_EVENT_TICK_EN_V << LP_AONCLKRST_ETM_EVENT_TICK_EN_S)
-#define LP_AONCLKRST_ETM_EVENT_TICK_EN_V  0x00000001U
-#define LP_AONCLKRST_ETM_EVENT_TICK_EN_S  28
-/** LP_AONCLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON    (BIT(29))
-#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_M  (LP_AONCLKRST_PLL8M_CLK_FORCE_ON_V << LP_AONCLKRST_PLL8M_CLK_FORCE_ON_S)
-#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_V  0x00000001U
-#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_S  29
-/** LP_AONCLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_XTAL_CLK_FORCE_ON    (BIT(30))
-#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_M  (LP_AONCLKRST_XTAL_CLK_FORCE_ON_V << LP_AONCLKRST_XTAL_CLK_FORCE_ON_S)
-#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_V  0x00000001U
-#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_S  30
-/** LP_AONCLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_FOSC_CLK_FORCE_ON    (BIT(31))
-#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_M  (LP_AONCLKRST_FOSC_CLK_FORCE_ON_V << LP_AONCLKRST_FOSC_CLK_FORCE_ON_S)
-#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_V  0x00000001U
-#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_S  31
-
-/** LP_AONCLKRST_LP_RST_EN_REG register
- *  need_des
- */
-#define LP_AONCLKRST_LP_RST_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0xc)
-/** LP_AONCLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_HUK    (BIT(24))
-#define LP_AONCLKRST_RST_EN_LP_HUK_M  (LP_AONCLKRST_RST_EN_LP_HUK_V << LP_AONCLKRST_RST_EN_LP_HUK_S)
-#define LP_AONCLKRST_RST_EN_LP_HUK_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_HUK_S  24
-/** LP_AONCLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_ANAPERI    (BIT(25))
-#define LP_AONCLKRST_RST_EN_LP_ANAPERI_M  (LP_AONCLKRST_RST_EN_LP_ANAPERI_V << LP_AONCLKRST_RST_EN_LP_ANAPERI_S)
-#define LP_AONCLKRST_RST_EN_LP_ANAPERI_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_ANAPERI_S  25
-/** LP_AONCLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_WDT    (BIT(26))
-#define LP_AONCLKRST_RST_EN_LP_WDT_M  (LP_AONCLKRST_RST_EN_LP_WDT_V << LP_AONCLKRST_RST_EN_LP_WDT_S)
-#define LP_AONCLKRST_RST_EN_LP_WDT_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_WDT_S  26
-/** LP_AONCLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_TIMER    (BIT(27))
-#define LP_AONCLKRST_RST_EN_LP_TIMER_M  (LP_AONCLKRST_RST_EN_LP_TIMER_V << LP_AONCLKRST_RST_EN_LP_TIMER_S)
-#define LP_AONCLKRST_RST_EN_LP_TIMER_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_TIMER_S  27
-/** LP_AONCLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_RTC    (BIT(28))
-#define LP_AONCLKRST_RST_EN_LP_RTC_M  (LP_AONCLKRST_RST_EN_LP_RTC_V << LP_AONCLKRST_RST_EN_LP_RTC_S)
-#define LP_AONCLKRST_RST_EN_LP_RTC_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_RTC_S  28
-/** LP_AONCLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_MAILBOX    (BIT(29))
-#define LP_AONCLKRST_RST_EN_LP_MAILBOX_M  (LP_AONCLKRST_RST_EN_LP_MAILBOX_V << LP_AONCLKRST_RST_EN_LP_MAILBOX_S)
-#define LP_AONCLKRST_RST_EN_LP_MAILBOX_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_MAILBOX_S  29
-/** LP_AONCLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG    (BIT(30))
-#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_M  (LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_V << LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_S)
-#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_S  30
-/** LP_AONCLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_RST_EN_LP_RAM    (BIT(31))
-#define LP_AONCLKRST_RST_EN_LP_RAM_M  (LP_AONCLKRST_RST_EN_LP_RAM_V << LP_AONCLKRST_RST_EN_LP_RAM_S)
-#define LP_AONCLKRST_RST_EN_LP_RAM_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_LP_RAM_S  31
-
-/** LP_AONCLKRST_RESET_CAUSE_REG register
- *  need_des
- */
-#define LP_AONCLKRST_RESET_CAUSE_REG (DR_REG_LP_AONCLKRST_BASE + 0x10)
-/** LP_AONCLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0;
- *  6'h1: POR reset
- *  6'h9: PMU LP PERI power down reset
- *  6'ha: PMU LP CPU reset
- *  6'hf: brown out reset
- *  6'h10: LP watchdog chip reset
- *  6'h12: super watch dog reset
- *  6'h13: glitch reset
- *  6'h14: software reset
- */
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE    0x0000003FU
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_M  (LP_AONCLKRST_LPCORE_RESET_CAUSE_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_S)
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_V  0x0000003FU
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_S  0
-/** LP_AONCLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_LPCORE_RESET_FLAG    (BIT(6))
-#define LP_AONCLKRST_LPCORE_RESET_FLAG_M  (LP_AONCLKRST_LPCORE_RESET_FLAG_V << LP_AONCLKRST_LPCORE_RESET_FLAG_S)
-#define LP_AONCLKRST_LPCORE_RESET_FLAG_V  0x00000001U
-#define LP_AONCLKRST_LPCORE_RESET_FLAG_S  6
-/** LP_AONCLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0;
- *  6'h1: POR reset
- *  6'h3: digital system software reset
- *  6'h5: PMU HP system power down reset
- *  6'h7: HP system reset from HP watchdog
- *  6'h9: HP system reset from LP watchdog
- *  6'hb: HP core reset from HP watchdog
- *  6'hc: HP core software reset
- *  6'hd: HP core reset from LP watchdog
- *  6'hf: brown out reset
- *  6'h10: LP watchdog chip reset
- *  6'h12: super watch dog reset
- *  6'h13: glitch reset
- *  6'h14: efuse crc error reset
- *  6'h16: HP usb jtag chip reset
- *  6'h17: HP usb uart chip reset
- *  6'h18: HP jtag reset
- *  6'h1a: HP core lockup
- */
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE    0x0000003FU
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_M  (LP_AONCLKRST_HPCORE0_RESET_CAUSE_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_S)
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_V  0x0000003FU
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_S  7
-/** LP_AONCLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG    (BIT(13))
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG_M  (LP_AONCLKRST_HPCORE0_RESET_FLAG_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_S)
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG_S  13
-/** LP_AONCLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0;
- *  6'h1: POR reset
- *  6'h3: digital system software reset
- *  6'h5: PMU HP system power down reset
- *  6'h7: HP system reset from HP watchdog
- *  6'h9: HP system reset from LP watchdog
- *  6'hb: HP core reset from HP watchdog
- *  6'hc: HP core software reset
- *  6'hd: HP core reset from LP watchdog
- *  6'hf: brown out reset
- *  6'h10: LP watchdog chip reset
- *  6'h12: super watch dog reset
- *  6'h13: glitch reset
- *  6'h14: efuse crc error reset
- *  6'h16: HP usb jtag chip reset
- *  6'h17: HP usb uart chip reset
- *  6'h18: HP jtag reset
- *  6'h1a: HP core lockup
- */
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE    0x0000003FU
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_M  (LP_AONCLKRST_HPCORE1_RESET_CAUSE_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_S)
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_V  0x0000003FU
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_S  14
-/** LP_AONCLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG    (BIT(20))
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG_M  (LP_AONCLKRST_HPCORE1_RESET_FLAG_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_S)
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG_S  20
-/** LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1;
- *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
- *  pmu_lp_cpu_reset reset_cause
- */
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK    (BIT(25))
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M  (LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S)
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V  0x00000001U
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S  25
-/** LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR    (BIT(26))
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_M  (LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S)
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S  26
-/** LP_AONCLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR    (BIT(27))
-#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_M  (LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V << LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S)
-#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V  0x00000001U
-#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S  27
-/** LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR    (BIT(28))
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_M  (LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S)
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S  28
-/** LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR    (BIT(29))
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_M  (LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S)
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S  29
-/** LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR    (BIT(30))
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_M  (LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S)
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S  30
-/** LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR    (BIT(31))
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_M  (LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S)
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S  31
-
-/** LP_AONCLKRST_HPCPU_RESET_CTRL0_REG register
- *  need_des
- */
-#define LP_AONCLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_AONCLKRST_BASE + 0x14)
-/** LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0;
- *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
- *  reset feature
- */
-#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(0))
-#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S)
-#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S  0
-/** LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1;
- *  need_des
- */
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH    0x00000007U
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M  (LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S)
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V  0x00000007U
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S  1
-/** LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0;
- *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
- *  hpcore0 feature
- */
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN    (BIT(4))
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_M  (LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_S)
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_V  0x00000001U
-#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_S  4
-/** LP_AONCLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE0_STALL_WAIT    0x0000007FU
-#define LP_AONCLKRST_HPCORE0_STALL_WAIT_M  (LP_AONCLKRST_HPCORE0_STALL_WAIT_V << LP_AONCLKRST_HPCORE0_STALL_WAIT_S)
-#define LP_AONCLKRST_HPCORE0_STALL_WAIT_V  0x0000007FU
-#define LP_AONCLKRST_HPCORE0_STALL_WAIT_S  5
-/** LP_AONCLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE0_STALL_EN    (BIT(12))
-#define LP_AONCLKRST_HPCORE0_STALL_EN_M  (LP_AONCLKRST_HPCORE0_STALL_EN_V << LP_AONCLKRST_HPCORE0_STALL_EN_S)
-#define LP_AONCLKRST_HPCORE0_STALL_EN_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_STALL_EN_S  12
-/** LP_AONCLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE0_SW_RESET    (BIT(13))
-#define LP_AONCLKRST_HPCORE0_SW_RESET_M  (LP_AONCLKRST_HPCORE0_SW_RESET_V << LP_AONCLKRST_HPCORE0_SW_RESET_S)
-#define LP_AONCLKRST_HPCORE0_SW_RESET_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_SW_RESET_S  13
-/** LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET    (BIT(14))
-#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_M  (LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S)
-#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S  14
-/** LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1;
- *  1'b1: boot from HP TCM ROM: 0x4FC00000
- *  1'b0: boot from LP TCM RAM:  0x50108000
- */
-#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL    (BIT(15))
-#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_M  (LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S)
-#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V  0x00000001U
-#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S  15
-/** LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0;
- *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
- *  reset feature
- */
-#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN    (BIT(16))
-#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_M  (LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S)
-#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S  16
-/** LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1;
- *  need_des
- */
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH    0x00000007U
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M  (LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S)
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V  0x00000007U
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S  17
-/** LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0;
- *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
- *  hpcore1 feature
- */
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN    (BIT(20))
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_M  (LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_S)
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_V  0x00000001U
-#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_S  20
-/** LP_AONCLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE1_STALL_WAIT    0x0000007FU
-#define LP_AONCLKRST_HPCORE1_STALL_WAIT_M  (LP_AONCLKRST_HPCORE1_STALL_WAIT_V << LP_AONCLKRST_HPCORE1_STALL_WAIT_S)
-#define LP_AONCLKRST_HPCORE1_STALL_WAIT_V  0x0000007FU
-#define LP_AONCLKRST_HPCORE1_STALL_WAIT_S  21
-/** LP_AONCLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE1_STALL_EN    (BIT(28))
-#define LP_AONCLKRST_HPCORE1_STALL_EN_M  (LP_AONCLKRST_HPCORE1_STALL_EN_V << LP_AONCLKRST_HPCORE1_STALL_EN_S)
-#define LP_AONCLKRST_HPCORE1_STALL_EN_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_STALL_EN_S  28
-/** LP_AONCLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE1_SW_RESET    (BIT(29))
-#define LP_AONCLKRST_HPCORE1_SW_RESET_M  (LP_AONCLKRST_HPCORE1_SW_RESET_V << LP_AONCLKRST_HPCORE1_SW_RESET_S)
-#define LP_AONCLKRST_HPCORE1_SW_RESET_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_SW_RESET_S  29
-/** LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET    (BIT(30))
-#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_M  (LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S)
-#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S  30
-/** LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1;
- *  1'b1: boot from HP TCM ROM: 0x4FC00000
- *  1'b0: boot from LP TCM RAM:  0x50108000
- */
-#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL    (BIT(31))
-#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_M  (LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S)
-#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V  0x00000001U
-#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S  31
-
-/** LP_AONCLKRST_HPCPU_RESET_CTRL1_REG register
- *  need_des
- */
-#define LP_AONCLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_AONCLKRST_BASE + 0x18)
-/** LP_AONCLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0;
- *  HP core0 software stall when set to 8'h86
- */
-#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE    0x000000FFU
-#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_M  (LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S)
-#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V  0x000000FFU
-#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S  16
-/** LP_AONCLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0;
- *  HP core1 software stall when set to 8'h86
- */
-#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE    0x000000FFU
-#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_M  (LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S)
-#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V  0x000000FFU
-#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S  24
-
-/** LP_AONCLKRST_FOSC_CNTL_REG register
- *  need_des
- */
-#define LP_AONCLKRST_FOSC_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x1c)
-/** LP_AONCLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400;
- *  need_des
- */
-#define LP_AONCLKRST_FOSC_DFREQ    0x000003FFU
-#define LP_AONCLKRST_FOSC_DFREQ_M  (LP_AONCLKRST_FOSC_DFREQ_V << LP_AONCLKRST_FOSC_DFREQ_S)
-#define LP_AONCLKRST_FOSC_DFREQ_V  0x000003FFU
-#define LP_AONCLKRST_FOSC_DFREQ_S  22
-
-/** LP_AONCLKRST_RC32K_CNTL_REG register
- *  need_des
- */
-#define LP_AONCLKRST_RC32K_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x20)
-/** LP_AONCLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650;
- *  need_des
- */
-#define LP_AONCLKRST_RC32K_DFREQ    0xFFFFFFFFU
-#define LP_AONCLKRST_RC32K_DFREQ_M  (LP_AONCLKRST_RC32K_DFREQ_V << LP_AONCLKRST_RC32K_DFREQ_S)
-#define LP_AONCLKRST_RC32K_DFREQ_V  0xFFFFFFFFU
-#define LP_AONCLKRST_RC32K_DFREQ_S  0
-
-/** LP_AONCLKRST_SOSC_CNTL_REG register
- *  need_des
- */
-#define LP_AONCLKRST_SOSC_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x24)
-/** LP_AONCLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
- *  need_des
- */
-#define LP_AONCLKRST_SOSC_DFREQ    0x000003FFU
-#define LP_AONCLKRST_SOSC_DFREQ_M  (LP_AONCLKRST_SOSC_DFREQ_V << LP_AONCLKRST_SOSC_DFREQ_S)
-#define LP_AONCLKRST_SOSC_DFREQ_V  0x000003FFU
-#define LP_AONCLKRST_SOSC_DFREQ_S  22
-
-/** LP_AONCLKRST_CLK_TO_HP_REG register
- *  need_des
- */
-#define LP_AONCLKRST_CLK_TO_HP_REG (DR_REG_LP_AONCLKRST_BASE + 0x28)
-/** LP_AONCLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
- *  reserved
- */
-#define LP_AONCLKRST_ICG_HP_XTAL32K    (BIT(28))
-#define LP_AONCLKRST_ICG_HP_XTAL32K_M  (LP_AONCLKRST_ICG_HP_XTAL32K_V << LP_AONCLKRST_ICG_HP_XTAL32K_S)
-#define LP_AONCLKRST_ICG_HP_XTAL32K_V  0x00000001U
-#define LP_AONCLKRST_ICG_HP_XTAL32K_S  28
-/** LP_AONCLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
- *  reserved
- */
-#define LP_AONCLKRST_ICG_HP_SOSC    (BIT(29))
-#define LP_AONCLKRST_ICG_HP_SOSC_M  (LP_AONCLKRST_ICG_HP_SOSC_V << LP_AONCLKRST_ICG_HP_SOSC_S)
-#define LP_AONCLKRST_ICG_HP_SOSC_V  0x00000001U
-#define LP_AONCLKRST_ICG_HP_SOSC_S  29
-/** LP_AONCLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
- *  reserved
- */
-#define LP_AONCLKRST_ICG_HP_OSC32K    (BIT(30))
-#define LP_AONCLKRST_ICG_HP_OSC32K_M  (LP_AONCLKRST_ICG_HP_OSC32K_V << LP_AONCLKRST_ICG_HP_OSC32K_S)
-#define LP_AONCLKRST_ICG_HP_OSC32K_V  0x00000001U
-#define LP_AONCLKRST_ICG_HP_OSC32K_S  30
-/** LP_AONCLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
- *  reserved
- */
-#define LP_AONCLKRST_ICG_HP_FOSC    (BIT(31))
-#define LP_AONCLKRST_ICG_HP_FOSC_M  (LP_AONCLKRST_ICG_HP_FOSC_V << LP_AONCLKRST_ICG_HP_FOSC_S)
-#define LP_AONCLKRST_ICG_HP_FOSC_V  0x00000001U
-#define LP_AONCLKRST_ICG_HP_FOSC_S  31
-
-/** LP_AONCLKRST_LPMEM_FORCE_REG register
- *  need_des
- */
-#define LP_AONCLKRST_LPMEM_FORCE_REG (DR_REG_LP_AONCLKRST_BASE + 0x2c)
-/** LP_AONCLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  reserved
- */
-#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
-#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_M  (LP_AONCLKRST_LPMEM_CLK_FORCE_ON_V << LP_AONCLKRST_LPMEM_CLK_FORCE_ON_S)
-#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
-#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_S  31
-
-/** LP_AONCLKRST_XTAL32K_REG register
- *  need_des
- */
-#define LP_AONCLKRST_XTAL32K_REG (DR_REG_LP_AONCLKRST_BASE + 0x30)
-/** LP_AONCLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
- *  need_des
- */
-#define LP_AONCLKRST_DRES_XTAL32K    0x00000007U
-#define LP_AONCLKRST_DRES_XTAL32K_M  (LP_AONCLKRST_DRES_XTAL32K_V << LP_AONCLKRST_DRES_XTAL32K_S)
-#define LP_AONCLKRST_DRES_XTAL32K_V  0x00000007U
-#define LP_AONCLKRST_DRES_XTAL32K_S  22
-/** LP_AONCLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
- *  need_des
- */
-#define LP_AONCLKRST_DGM_XTAL32K    0x00000007U
-#define LP_AONCLKRST_DGM_XTAL32K_M  (LP_AONCLKRST_DGM_XTAL32K_V << LP_AONCLKRST_DGM_XTAL32K_S)
-#define LP_AONCLKRST_DGM_XTAL32K_V  0x00000007U
-#define LP_AONCLKRST_DGM_XTAL32K_S  25
-/** LP_AONCLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_DBUF_XTAL32K    (BIT(28))
-#define LP_AONCLKRST_DBUF_XTAL32K_M  (LP_AONCLKRST_DBUF_XTAL32K_V << LP_AONCLKRST_DBUF_XTAL32K_S)
-#define LP_AONCLKRST_DBUF_XTAL32K_V  0x00000001U
-#define LP_AONCLKRST_DBUF_XTAL32K_S  28
-/** LP_AONCLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
- *  need_des
- */
-#define LP_AONCLKRST_DAC_XTAL32K    0x00000007U
-#define LP_AONCLKRST_DAC_XTAL32K_M  (LP_AONCLKRST_DAC_XTAL32K_V << LP_AONCLKRST_DAC_XTAL32K_S)
-#define LP_AONCLKRST_DAC_XTAL32K_V  0x00000007U
-#define LP_AONCLKRST_DAC_XTAL32K_S  29
-
-/** LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_REG register
- *  need_des
- */
-#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x34)
-/** LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS    0xFFFFFFFFU
-#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_M  (LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_S)
-#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_V  0xFFFFFFFFU
-#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_S  0
-
-/** LP_AONCLKRST_HPSYS_0_RESET_BYPASS_REG register
- *  need_des
- */
-#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x38)
-/** LP_AONCLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS    0xFFFFFFFFU
-#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_M  (LP_AONCLKRST_HPSYS_0_RESET_BYPASS_V << LP_AONCLKRST_HPSYS_0_RESET_BYPASS_S)
-#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_V  0xFFFFFFFFU
-#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_S  0
-
-/** LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_REG register
- *  need_des
- */
-#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x3c)
-/** LP_AONCLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS    0xFFFFFFFFU
-#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_M  (LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_V << LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_S)
-#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_V  0xFFFFFFFFU
-#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_S  0
-
-/** LP_AONCLKRST_HP_CLK_CTRL_REG register
- *  HP Clock Control Register.
- */
-#define LP_AONCLKRST_HP_CLK_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x40)
-/** LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
- *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
- */
-#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL    0x00000003U
-#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_M  (LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_S)
-#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_V  0x00000003U
-#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_S  0
-/** LP_AONCLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  HP SoC Root Clock Enable.
- */
-#define LP_AONCLKRST_HP_ROOT_CLK_EN    (BIT(2))
-#define LP_AONCLKRST_HP_ROOT_CLK_EN_M  (LP_AONCLKRST_HP_ROOT_CLK_EN_V << LP_AONCLKRST_HP_ROOT_CLK_EN_S)
-#define LP_AONCLKRST_HP_ROOT_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_ROOT_CLK_EN_S  2
-/** LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  PARLIO TX Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN    (BIT(3))
-#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_M  (LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_S  3
-/** LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  PARLIO RX Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN    (BIT(4))
-#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_M  (LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_S  4
-/** LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  UART4 SLP Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN    (BIT(5))
-#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_M  (LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_S  5
-/** LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  UART3 SLP Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN    (BIT(6))
-#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_M  (LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_S  6
-/** LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1;
- *  UART2 SLP Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN    (BIT(7))
-#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_M  (LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_S  7
-/** LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1;
- *  UART1 SLP Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN    (BIT(8))
-#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_M  (LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_S  8
-/** LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1;
- *  UART0 SLP Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN    (BIT(9))
-#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_M  (LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_S  9
-/** LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1;
- *  I2S2 MCLK Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN    (BIT(10))
-#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_M  (LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_S  10
-/** LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1;
- *  I2S1 MCLK Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN    (BIT(11))
-#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_M  (LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_S  11
-/** LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1;
- *  I2S0 MCLK Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN    (BIT(12))
-#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_M  (LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_S  12
-/** LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1;
- *  EMAC RX Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN    (BIT(13))
-#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_M  (LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_S  13
-/** LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1;
- *  EMAC TX Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN    (BIT(14))
-#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_M  (LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_S  14
-/** LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1;
- *  EMAC TXRX Clock From Pad Enable.
- */
-#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN    (BIT(15))
-#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M  (LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S)
-#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S  15
-/** LP_AONCLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1;
- *  XTAL 32K Clock Enable.
- */
-#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN    (BIT(16))
-#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_M  (LP_AONCLKRST_HP_XTAL_32K_CLK_EN_V << LP_AONCLKRST_HP_XTAL_32K_CLK_EN_S)
-#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_S  16
-/** LP_AONCLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1;
- *  RC 32K Clock Enable.
- */
-#define LP_AONCLKRST_HP_RC_32K_CLK_EN    (BIT(17))
-#define LP_AONCLKRST_HP_RC_32K_CLK_EN_M  (LP_AONCLKRST_HP_RC_32K_CLK_EN_V << LP_AONCLKRST_HP_RC_32K_CLK_EN_S)
-#define LP_AONCLKRST_HP_RC_32K_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_RC_32K_CLK_EN_S  17
-/** LP_AONCLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1;
- *  SOSC 150K Clock Enable.
- */
-#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN    (BIT(18))
-#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_M  (LP_AONCLKRST_HP_SOSC_150K_CLK_EN_V << LP_AONCLKRST_HP_SOSC_150K_CLK_EN_S)
-#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_S  18
-/** LP_AONCLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1;
- *  PLL 8M Clock Enable.
- */
-#define LP_AONCLKRST_HP_PLL_8M_CLK_EN    (BIT(19))
-#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_M  (LP_AONCLKRST_HP_PLL_8M_CLK_EN_V << LP_AONCLKRST_HP_PLL_8M_CLK_EN_S)
-#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_S  19
-/** LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1;
- *  AUDIO PLL Clock Enable.
- */
-#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN    (BIT(20))
-#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_M  (LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_S)
-#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_S  20
-/** LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1;
- *  SDIO PLL2 Clock Enable.
- */
-#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN    (BIT(21))
-#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_M  (LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_S)
-#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_S  21
-/** LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  SDIO PLL1 Clock Enable.
- */
-#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN    (BIT(22))
-#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_M  (LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_S)
-#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_S  22
-/** LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1;
- *  SDIO PLL0 Clock Enable.
- */
-#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN    (BIT(23))
-#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_M  (LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_S)
-#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_S  23
-/** LP_AONCLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1;
- *  FOSC 20M Clock Enable.
- */
-#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN    (BIT(24))
-#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_M  (LP_AONCLKRST_HP_FOSC_20M_CLK_EN_V << LP_AONCLKRST_HP_FOSC_20M_CLK_EN_S)
-#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_S  24
-/** LP_AONCLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1;
- *  XTAL 40M Clock Enalbe.
- */
-#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN    (BIT(25))
-#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_M  (LP_AONCLKRST_HP_XTAL_40M_CLK_EN_V << LP_AONCLKRST_HP_XTAL_40M_CLK_EN_S)
-#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_S  25
-/** LP_AONCLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1;
- *  CPLL 400M Clock Enable.
- */
-#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN    (BIT(26))
-#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_M  (LP_AONCLKRST_HP_CPLL_400M_CLK_EN_V << LP_AONCLKRST_HP_CPLL_400M_CLK_EN_S)
-#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_S  26
-/** LP_AONCLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1;
- *  SPLL 480M Clock Enable.
- */
-#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN    (BIT(27))
-#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_M  (LP_AONCLKRST_HP_SPLL_480M_CLK_EN_V << LP_AONCLKRST_HP_SPLL_480M_CLK_EN_S)
-#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_S  27
-/** LP_AONCLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1;
- *  MPLL 500M Clock Enable.
- */
-#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN    (BIT(28))
-#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_M  (LP_AONCLKRST_HP_MPLL_500M_CLK_EN_V << LP_AONCLKRST_HP_MPLL_500M_CLK_EN_S)
-#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_S  28
-
-/** LP_AONCLKRST_HP_USB_CLKRST_CTRL0_REG register
- *  HP USB Clock Reset Control Register.
- */
-#define LP_AONCLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_AONCLKRST_BASE + 0x44)
-/** LP_AONCLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0;
- *  unused.
- */
-#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE    (BIT(0))
-#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_M  (LP_AONCLKRST_USB_OTG20_SLEEP_MODE_V << LP_AONCLKRST_USB_OTG20_SLEEP_MODE_S)
-#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_V  0x00000001U
-#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_S  0
-/** LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  unused.
- */
-#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN    (BIT(1))
-#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_M  (LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_S)
-#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_S  1
-/** LP_AONCLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0;
- *  unused.
- */
-#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE    (BIT(2))
-#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_M  (LP_AONCLKRST_USB_OTG11_SLEEP_MODE_V << LP_AONCLKRST_USB_OTG11_SLEEP_MODE_S)
-#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_V  0x00000001U
-#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_S  2
-/** LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  unused.
- */
-#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN    (BIT(3))
-#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_M  (LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_S)
-#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_S  3
-/** LP_AONCLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  usb otg11 fs phy clock enable.
- */
-#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN    (BIT(4))
-#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_M  (LP_AONCLKRST_USB_OTG11_48M_CLK_EN_V << LP_AONCLKRST_USB_OTG11_48M_CLK_EN_S)
-#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_S  4
-/** LP_AONCLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  usb device fs phy clock enable.
- */
-#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN    (BIT(5))
-#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_M  (LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_V << LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_S)
-#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_S  5
-/** LP_AONCLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9;
- *  usb 480m to 25m divide number.
- */
-#define LP_AONCLKRST_USB_48M_DIV_NUM    0x000000FFU
-#define LP_AONCLKRST_USB_48M_DIV_NUM_M  (LP_AONCLKRST_USB_48M_DIV_NUM_V << LP_AONCLKRST_USB_48M_DIV_NUM_S)
-#define LP_AONCLKRST_USB_48M_DIV_NUM_V  0x000000FFU
-#define LP_AONCLKRST_USB_48M_DIV_NUM_S  6
-/** LP_AONCLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19;
- *  usb 500m to 25m divide number.
- */
-#define LP_AONCLKRST_USB_25M_DIV_NUM    0x000000FFU
-#define LP_AONCLKRST_USB_25M_DIV_NUM_M  (LP_AONCLKRST_USB_25M_DIV_NUM_V << LP_AONCLKRST_USB_25M_DIV_NUM_S)
-#define LP_AONCLKRST_USB_25M_DIV_NUM_V  0x000000FFU
-#define LP_AONCLKRST_USB_25M_DIV_NUM_S  14
-/** LP_AONCLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39;
- *  usb 480m to 12m divide number.
- */
-#define LP_AONCLKRST_USB_12M_DIV_NUM    0x000000FFU
-#define LP_AONCLKRST_USB_12M_DIV_NUM_M  (LP_AONCLKRST_USB_12M_DIV_NUM_V << LP_AONCLKRST_USB_12M_DIV_NUM_S)
-#define LP_AONCLKRST_USB_12M_DIV_NUM_V  0x000000FFU
-#define LP_AONCLKRST_USB_12M_DIV_NUM_S  22
-
-/** LP_AONCLKRST_HP_USB_CLKRST_CTRL1_REG register
- *  HP USB Clock Reset Control Register.
- */
-#define LP_AONCLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_AONCLKRST_BASE + 0x48)
-/** LP_AONCLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0;
- *  usb otg20 adp reset en
- */
-#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP    (BIT(0))
-#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_M  (LP_AONCLKRST_RST_EN_USB_OTG20_ADP_V << LP_AONCLKRST_RST_EN_USB_OTG20_ADP_S)
-#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_S  0
-/** LP_AONCLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0;
- *  usb otg20 phy reset en
- */
-#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY    (BIT(1))
-#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_M  (LP_AONCLKRST_RST_EN_USB_OTG20_PHY_V << LP_AONCLKRST_RST_EN_USB_OTG20_PHY_S)
-#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_S  1
-/** LP_AONCLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0;
- *  usb otg20 reset en
- */
-#define LP_AONCLKRST_RST_EN_USB_OTG20    (BIT(2))
-#define LP_AONCLKRST_RST_EN_USB_OTG20_M  (LP_AONCLKRST_RST_EN_USB_OTG20_V << LP_AONCLKRST_RST_EN_USB_OTG20_S)
-#define LP_AONCLKRST_RST_EN_USB_OTG20_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_USB_OTG20_S  2
-/** LP_AONCLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0;
- *  usb org11 reset en
- */
-#define LP_AONCLKRST_RST_EN_USB_OTG11    (BIT(3))
-#define LP_AONCLKRST_RST_EN_USB_OTG11_M  (LP_AONCLKRST_RST_EN_USB_OTG11_V << LP_AONCLKRST_RST_EN_USB_OTG11_S)
-#define LP_AONCLKRST_RST_EN_USB_OTG11_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_USB_OTG11_S  3
-/** LP_AONCLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0;
- *  usb device reset en
- */
-#define LP_AONCLKRST_RST_EN_USB_DEVICE    (BIT(4))
-#define LP_AONCLKRST_RST_EN_USB_DEVICE_M  (LP_AONCLKRST_RST_EN_USB_DEVICE_V << LP_AONCLKRST_RST_EN_USB_DEVICE_S)
-#define LP_AONCLKRST_RST_EN_USB_DEVICE_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_USB_DEVICE_S  4
-/** LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0;
- *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
- */
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL    0x00000003U
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M  (LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S)
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V  0x00000003U
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S  28
-/** LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1;
- *  usb otg20 hs phy refclk enable.
- */
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN    (BIT(30))
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_M  (LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_S)
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_S  30
-/** LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1;
- *  usb otg20 ulpi clock enable.
- */
-#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN    (BIT(31))
-#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_M  (LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_S)
-#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_S  31
-
-/** LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register
- *  need_des
- */
-#define LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x4c)
-/** LP_AONCLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0;
- *  hp sdmmc reset en
- */
-#define LP_AONCLKRST_RST_EN_SDMMC    (BIT(28))
-#define LP_AONCLKRST_RST_EN_SDMMC_M  (LP_AONCLKRST_RST_EN_SDMMC_V << LP_AONCLKRST_RST_EN_SDMMC_S)
-#define LP_AONCLKRST_RST_EN_SDMMC_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_SDMMC_S  28
-/** LP_AONCLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0;
- *  hp sdmmc force norst
- */
-#define LP_AONCLKRST_FORCE_NORST_SDMMC    (BIT(29))
-#define LP_AONCLKRST_FORCE_NORST_SDMMC_M  (LP_AONCLKRST_FORCE_NORST_SDMMC_V << LP_AONCLKRST_FORCE_NORST_SDMMC_S)
-#define LP_AONCLKRST_FORCE_NORST_SDMMC_V  0x00000001U
-#define LP_AONCLKRST_FORCE_NORST_SDMMC_S  29
-/** LP_AONCLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0;
- *  hp emac reset en
- */
-#define LP_AONCLKRST_RST_EN_EMAC    (BIT(30))
-#define LP_AONCLKRST_RST_EN_EMAC_M  (LP_AONCLKRST_RST_EN_EMAC_V << LP_AONCLKRST_RST_EN_EMAC_S)
-#define LP_AONCLKRST_RST_EN_EMAC_V  0x00000001U
-#define LP_AONCLKRST_RST_EN_EMAC_S  30
-/** LP_AONCLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0;
- *  hp emac force norst
- */
-#define LP_AONCLKRST_FORCE_NORST_EMAC    (BIT(31))
-#define LP_AONCLKRST_FORCE_NORST_EMAC_M  (LP_AONCLKRST_FORCE_NORST_EMAC_V << LP_AONCLKRST_FORCE_NORST_EMAC_S)
-#define LP_AONCLKRST_FORCE_NORST_EMAC_V  0x00000001U
-#define LP_AONCLKRST_FORCE_NORST_EMAC_S  31
-
-/** LP_AONCLKRST_DATE_REG register
- *  need_des
- */
-#define LP_AONCLKRST_DATE_REG (DR_REG_LP_AONCLKRST_BASE + 0x3fc)
-/** LP_AONCLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AONCLKRST_CLK_EN    (BIT(31))
-#define LP_AONCLKRST_CLK_EN_M  (LP_AONCLKRST_CLK_EN_V << LP_AONCLKRST_CLK_EN_S)
-#define LP_AONCLKRST_CLK_EN_V  0x00000001U
-#define LP_AONCLKRST_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h b/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h
deleted file mode 100644
index 6012eb38d7..0000000000
--- a/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h
+++ /dev/null
@@ -1,795 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of lp_clk_conf register
- *  need_des
- */
-typedef union {
-    struct {
-        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
-         *  need_des
-         */
-        uint32_t slow_clk_sel:2;
-        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_clk_sel:2;
-        /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_peri_div_num:6;
-        /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_sel_ref_pll8m:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_aonclkrst_lp_clk_conf_reg_t;
-
-/** Type of lp_clk_po_en register
- *  need_des
- */
-typedef union {
-    struct {
-        /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_core_efuse_oen:1;
-        /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_lp_bus_oen:1;
-        /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_aon_slow_oen:1;
-        /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_aon_fast_oen:1;
-        /** clk_slow_oen : R/W; bitpos: [4]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_slow_oen:1;
-        /** clk_fast_oen : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_fast_oen:1;
-        /** clk_fosc_oen : R/W; bitpos: [6]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_fosc_oen:1;
-        /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_rc32k_oen:1;
-        /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_sxtal_oen:1;
-        /** clk_sosc_oen : R/W; bitpos: [9]; default: 0;
-         *  1'b1: probe sosc clk on
-         *  1'b0: probe sosc clk off
-         */
-        uint32_t clk_sosc_oen:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} lp_aonclkrst_lp_clk_po_en_reg_t;
-
-/** Type of lp_clk_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_rtc_xtal_force_on:1;
-        /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1;
-         *  need_des
-         */
-        uint32_t ck_en_lp_ram:1;
-        /** etm_event_tick_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t etm_event_tick_en:1;
-        /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t pll8m_clk_force_on:1;
-        /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t xtal_clk_force_on:1;
-        /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t fosc_clk_force_on:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_lp_clk_en_reg_t;
-
-/** Type of lp_rst_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_huk:1;
-        /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_anaperi:1;
-        /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_wdt:1;
-        /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_timer:1;
-        /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_rtc:1;
-        /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_mailbox:1;
-        /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_aonefusereg:1;
-        /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_ram:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_lp_rst_en_reg_t;
-
-/** Type of reset_cause register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0;
-         *  6'h1: POR reset
-         *  6'h9: PMU LP PERI power down reset
-         *  6'ha: PMU LP CPU reset
-         *  6'hf: brown out reset
-         *  6'h10: LP watchdog chip reset
-         *  6'h12: super watch dog reset
-         *  6'h13: glitch reset
-         *  6'h14: software reset
-         */
-        uint32_t lpcore_reset_cause:6;
-        /** lpcore_reset_flag : RO; bitpos: [6]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_reset_flag:1;
-        /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0;
-         *  6'h1: POR reset
-         *  6'h3: digital system software reset
-         *  6'h5: PMU HP system power down reset
-         *  6'h7: HP system reset from HP watchdog
-         *  6'h9: HP system reset from LP watchdog
-         *  6'hb: HP core reset from HP watchdog
-         *  6'hc: HP core software reset
-         *  6'hd: HP core reset from LP watchdog
-         *  6'hf: brown out reset
-         *  6'h10: LP watchdog chip reset
-         *  6'h12: super watch dog reset
-         *  6'h13: glitch reset
-         *  6'h14: efuse crc error reset
-         *  6'h16: HP usb jtag chip reset
-         *  6'h17: HP usb uart chip reset
-         *  6'h18: HP jtag reset
-         *  6'h1a: HP core lockup
-         */
-        uint32_t hpcore0_reset_cause:6;
-        /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_reset_flag:1;
-        /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0;
-         *  6'h1: POR reset
-         *  6'h3: digital system software reset
-         *  6'h5: PMU HP system power down reset
-         *  6'h7: HP system reset from HP watchdog
-         *  6'h9: HP system reset from LP watchdog
-         *  6'hb: HP core reset from HP watchdog
-         *  6'hc: HP core software reset
-         *  6'hd: HP core reset from LP watchdog
-         *  6'hf: brown out reset
-         *  6'h10: LP watchdog chip reset
-         *  6'h12: super watch dog reset
-         *  6'h13: glitch reset
-         *  6'h14: efuse crc error reset
-         *  6'h16: HP usb jtag chip reset
-         *  6'h17: HP usb uart chip reset
-         *  6'h18: HP jtag reset
-         *  6'h1a: HP core lockup
-         */
-        uint32_t hpcore1_reset_cause:6;
-        /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_reset_flag:1;
-        uint32_t reserved_21:4;
-        /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1;
-         *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
-         *  pmu_lp_cpu_reset reset_cause
-         */
-        uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1;
-        /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_reset_cause_clr:1;
-        /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_reset_flag_clr:1;
-        /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_reset_cause_clr:1;
-        /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_reset_flag_clr:1;
-        /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_reset_cause_clr:1;
-        /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_reset_flag_clr:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_reset_cause_reg_t;
-
-/** Type of hpcpu_reset_ctrl0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0;
-         *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
-         *  reset feature
-         */
-        uint32_t hpcore0_lockup_reset_en:1;
-        /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_wdt_hpcore0_reset_length:3;
-        /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0;
-         *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
-         *  hpcore0 feature
-         */
-        uint32_t lp_wdt_hpcore0_reset_en:1;
-        /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_stall_wait:7;
-        /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_stall_en:1;
-        /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_sw_reset:1;
-        /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_ocd_halt_on_reset:1;
-        /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1;
-         *  1'b1: boot from HP TCM ROM: 0x4FC00000
-         *  1'b0: boot from LP TCM RAM:  0x50108000
-         */
-        uint32_t hpcore0_stat_vector_sel:1;
-        /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0;
-         *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
-         *  reset feature
-         */
-        uint32_t hpcore1_lockup_reset_en:1;
-        /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_wdt_hpcore1_reset_length:3;
-        /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0;
-         *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
-         *  hpcore1 feature
-         */
-        uint32_t lp_wdt_hpcore1_reset_en:1;
-        /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_stall_wait:7;
-        /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_stall_en:1;
-        /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_sw_reset:1;
-        /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_ocd_halt_on_reset:1;
-        /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1;
-         *  1'b1: boot from HP TCM ROM: 0x4FC00000
-         *  1'b0: boot from LP TCM RAM:  0x50108000
-         */
-        uint32_t hpcore1_stat_vector_sel:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_hpcpu_reset_ctrl0_reg_t;
-
-/** Type of hpcpu_reset_ctrl1 register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
-         *  HP core0 software stall when set to 8'h86
-         */
-        uint32_t hpcore0_sw_stall_code:8;
-        /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
-         *  HP core1 software stall when set to 8'h86
-         */
-        uint32_t hpcore1_sw_stall_code:8;
-    };
-    uint32_t val;
-} lp_aonclkrst_hpcpu_reset_ctrl1_reg_t;
-
-/** Type of fosc_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400;
-         *  need_des
-         */
-        uint32_t fosc_dfreq:10;
-    };
-    uint32_t val;
-} lp_aonclkrst_fosc_cntl_reg_t;
-
-/** Type of rc32k_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650;
-         *  need_des
-         */
-        uint32_t rc32k_dfreq:32;
-    };
-    uint32_t val;
-} lp_aonclkrst_rc32k_cntl_reg_t;
-
-/** Type of sosc_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172;
-         *  need_des
-         */
-        uint32_t sosc_dfreq:10;
-    };
-    uint32_t val;
-} lp_aonclkrst_sosc_cntl_reg_t;
-
-/** Type of clk_to_hp register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_xtal32k:1;
-        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_sosc:1;
-        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_osc32k:1;
-        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_fosc:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_clk_to_hp_reg_t;
-
-/** Type of lpmem_force register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
-         *  reserved
-         */
-        uint32_t lpmem_clk_force_on:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_lpmem_force_reg_t;
-
-/** Type of xtal32k register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
-         *  need_des
-         */
-        uint32_t dres_xtal32k:3;
-        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
-         *  need_des
-         */
-        uint32_t dgm_xtal32k:3;
-        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t dbuf_xtal32k:1;
-        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
-         *  need_des
-         */
-        uint32_t dac_xtal32k:3;
-    };
-    uint32_t val;
-} lp_aonclkrst_xtal32k_reg_t;
-
-/** Type of mux_hpsys_reset_bypass register
- *  need_des
- */
-typedef union {
-    struct {
-        /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t mux_hpsys_reset_bypass:32;
-    };
-    uint32_t val;
-} lp_aonclkrst_mux_hpsys_reset_bypass_reg_t;
-
-/** Type of hpsys_0_reset_bypass register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t hpsys_0_reset_bypass:32;
-    };
-    uint32_t val;
-} lp_aonclkrst_hpsys_0_reset_bypass_reg_t;
-
-/** Type of hpsys_apm_reset_bypass register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t hpsys_apm_reset_bypass:32;
-    };
-    uint32_t val;
-} lp_aonclkrst_hpsys_apm_reset_bypass_reg_t;
-
-/** Type of hp_clk_ctrl register
- *  HP Clock Control Register.
- */
-typedef union {
-    struct {
-        /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
-         *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
-         */
-        uint32_t hp_root_clk_src_sel:2;
-        /** hp_root_clk_en : R/W; bitpos: [2]; default: 1;
-         *  HP SoC Root Clock Enable.
-         */
-        uint32_t hp_root_clk_en:1;
-        /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1;
-         *  PARLIO TX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_parlio_tx_clk_en:1;
-        /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1;
-         *  PARLIO RX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_parlio_rx_clk_en:1;
-        /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1;
-         *  UART4 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart4_slp_clk_en:1;
-        /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1;
-         *  UART3 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart3_slp_clk_en:1;
-        /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1;
-         *  UART2 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart2_slp_clk_en:1;
-        /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1;
-         *  UART1 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart1_slp_clk_en:1;
-        /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1;
-         *  UART0 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart0_slp_clk_en:1;
-        /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1;
-         *  I2S2 MCLK Clock From Pad Enable.
-         */
-        uint32_t hp_pad_i2s2_mclk_en:1;
-        /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1;
-         *  I2S1 MCLK Clock From Pad Enable.
-         */
-        uint32_t hp_pad_i2s1_mclk_en:1;
-        /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1;
-         *  I2S0 MCLK Clock From Pad Enable.
-         */
-        uint32_t hp_pad_i2s0_mclk_en:1;
-        /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1;
-         *  EMAC RX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_emac_tx_clk_en:1;
-        /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1;
-         *  EMAC TX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_emac_rx_clk_en:1;
-        /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1;
-         *  EMAC TXRX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_emac_txrx_clk_en:1;
-        /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1;
-         *  XTAL 32K Clock Enable.
-         */
-        uint32_t hp_xtal_32k_clk_en:1;
-        /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1;
-         *  RC 32K Clock Enable.
-         */
-        uint32_t hp_rc_32k_clk_en:1;
-        /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1;
-         *  SOSC 150K Clock Enable.
-         */
-        uint32_t hp_sosc_150k_clk_en:1;
-        /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1;
-         *  PLL 8M Clock Enable.
-         */
-        uint32_t hp_pll_8m_clk_en:1;
-        /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1;
-         *  AUDIO PLL Clock Enable.
-         */
-        uint32_t hp_audio_pll_clk_en:1;
-        /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1;
-         *  SDIO PLL2 Clock Enable.
-         */
-        uint32_t hp_sdio_pll2_clk_en:1;
-        /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1;
-         *  SDIO PLL1 Clock Enable.
-         */
-        uint32_t hp_sdio_pll1_clk_en:1;
-        /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1;
-         *  SDIO PLL0 Clock Enable.
-         */
-        uint32_t hp_sdio_pll0_clk_en:1;
-        /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1;
-         *  FOSC 20M Clock Enable.
-         */
-        uint32_t hp_fosc_20m_clk_en:1;
-        /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
-         *  XTAL 40M Clock Enalbe.
-         */
-        uint32_t hp_xtal_40m_clk_en:1;
-        /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;
-         *  CPLL 400M Clock Enable.
-         */
-        uint32_t hp_cpll_400m_clk_en:1;
-        /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1;
-         *  SPLL 480M Clock Enable.
-         */
-        uint32_t hp_spll_480m_clk_en:1;
-        /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1;
-         *  MPLL 500M Clock Enable.
-         */
-        uint32_t hp_mpll_500m_clk_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} lp_aonclkrst_hp_clk_ctrl_reg_t;
-
-/** Type of hp_usb_clkrst_ctrl0 register
- *  HP USB Clock Reset Control Register.
- */
-typedef union {
-    struct {
-        /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0;
-         *  unused.
-         */
-        uint32_t usb_otg20_sleep_mode:1;
-        /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1;
-         *  unused.
-         */
-        uint32_t usb_otg20_bk_sys_clk_en:1;
-        /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0;
-         *  unused.
-         */
-        uint32_t usb_otg11_sleep_mode:1;
-        /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1;
-         *  unused.
-         */
-        uint32_t usb_otg11_bk_sys_clk_en:1;
-        /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  usb otg11 fs phy clock enable.
-         */
-        uint32_t usb_otg11_48m_clk_en:1;
-        /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  usb device fs phy clock enable.
-         */
-        uint32_t usb_device_48m_clk_en:1;
-        /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9;
-         *  usb 480m to 25m divide number.
-         */
-        uint32_t usb_48m_div_num:8;
-        /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19;
-         *  usb 500m to 25m divide number.
-         */
-        uint32_t usb_25m_div_num:8;
-        /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39;
-         *  usb 480m to 12m divide number.
-         */
-        uint32_t usb_12m_div_num:8;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t;
-
-/** Type of hp_usb_clkrst_ctrl1 register
- *  HP USB Clock Reset Control Register.
- */
-typedef union {
-    struct {
-        /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0;
-         *  usb otg20 adp reset en
-         */
-        uint32_t rst_en_usb_otg20_adp:1;
-        /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0;
-         *  usb otg20 phy reset en
-         */
-        uint32_t rst_en_usb_otg20_phy:1;
-        /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0;
-         *  usb otg20 reset en
-         */
-        uint32_t rst_en_usb_otg20:1;
-        /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0;
-         *  usb org11 reset en
-         */
-        uint32_t rst_en_usb_otg11:1;
-        /** rst_en_usb_device : R/W; bitpos: [4]; default: 0;
-         *  usb device reset en
-         */
-        uint32_t rst_en_usb_device:1;
-        uint32_t reserved_5:23;
-        /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0;
-         *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
-         */
-        uint32_t usb_otg20_phyref_clk_src_sel:2;
-        /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1;
-         *  usb otg20 hs phy refclk enable.
-         */
-        uint32_t usb_otg20_phyref_clk_en:1;
-        /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1;
-         *  usb otg20 ulpi clock enable.
-         */
-        uint32_t usb_otg20_ulpi_clk_en:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t;
-
-/** Type of hp_sdmmc_emac_rst_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0;
-         *  hp sdmmc reset en
-         */
-        uint32_t rst_en_sdmmc:1;
-        /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0;
-         *  hp sdmmc force norst
-         */
-        uint32_t force_norst_sdmmc:1;
-        /** rst_en_emac : R/W; bitpos: [30]; default: 0;
-         *  hp emac reset en
-         */
-        uint32_t rst_en_emac:1;
-        /** force_norst_emac : R/W; bitpos: [31]; default: 0;
-         *  hp emac force norst
-         */
-        uint32_t force_norst_emac:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_aonclkrst_date_reg_t;
-
-
-typedef struct {
-    volatile lp_aonclkrst_lp_clk_conf_reg_t lp_clk_conf;
-    volatile lp_aonclkrst_lp_clk_po_en_reg_t lp_clk_po_en;
-    volatile lp_aonclkrst_lp_clk_en_reg_t lp_clk_en;
-    volatile lp_aonclkrst_lp_rst_en_reg_t lp_rst_en;
-    volatile lp_aonclkrst_reset_cause_reg_t reset_cause;
-    volatile lp_aonclkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0;
-    volatile lp_aonclkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1;
-    volatile lp_aonclkrst_fosc_cntl_reg_t fosc_cntl;
-    volatile lp_aonclkrst_rc32k_cntl_reg_t rc32k_cntl;
-    volatile lp_aonclkrst_sosc_cntl_reg_t sosc_cntl;
-    volatile lp_aonclkrst_clk_to_hp_reg_t clk_to_hp;
-    volatile lp_aonclkrst_lpmem_force_reg_t lpmem_force;
-    volatile lp_aonclkrst_xtal32k_reg_t xtal32k;
-    volatile lp_aonclkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass;
-    volatile lp_aonclkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass;
-    volatile lp_aonclkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass;
-    volatile lp_aonclkrst_hp_clk_ctrl_reg_t hp_clk_ctrl;
-    volatile lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0;
-    volatile lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1;
-    volatile lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl;
-    uint32_t reserved_050[235];
-    volatile lp_aonclkrst_date_reg_t date;
-} lp_aonclkrst_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm0_reg.h b/components/soc/esp32p4/include/soc/lp_apm0_reg.h
deleted file mode 100644
index 495cc35ba2..0000000000
--- a/components/soc/esp32p4/include/soc/lp_apm0_reg.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_APM0_REGION_FILTER_EN_REG register
- *  Region filter enable register
- */
-#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
-/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
- *  Region filter enable
- */
-#define LP_APM0_REGION_FILTER_EN    0x0000000FU
-#define LP_APM0_REGION_FILTER_EN_M  (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
-#define LP_APM0_REGION_FILTER_EN_V  0x0000000FU
-#define LP_APM0_REGION_FILTER_EN_S  0
-
-/** LP_APM0_REGION0_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
-/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region0
- */
-#define LP_APM0_REGION0_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_START_M  (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
-#define LP_APM0_REGION0_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_START_S  0
-
-/** LP_APM0_REGION0_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
-/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region0
- */
-#define LP_APM0_REGION0_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_END_M  (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
-#define LP_APM0_REGION0_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_END_S  0
-
-/** LP_APM0_REGION0_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
-/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION0_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION0_R0_PMS_X_M  (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S)
-#define LP_APM0_REGION0_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION0_R0_PMS_X_S  0
-/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION0_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION0_R0_PMS_W_M  (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S)
-#define LP_APM0_REGION0_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION0_R0_PMS_W_S  1
-/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION0_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION0_R0_PMS_R_M  (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S)
-#define LP_APM0_REGION0_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION0_R0_PMS_R_S  2
-/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION0_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION0_R1_PMS_X_M  (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S)
-#define LP_APM0_REGION0_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION0_R1_PMS_X_S  4
-/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION0_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION0_R1_PMS_W_M  (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S)
-#define LP_APM0_REGION0_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION0_R1_PMS_W_S  5
-/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION0_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION0_R1_PMS_R_M  (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S)
-#define LP_APM0_REGION0_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION0_R1_PMS_R_S  6
-/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION0_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION0_R2_PMS_X_M  (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S)
-#define LP_APM0_REGION0_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION0_R2_PMS_X_S  8
-/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION0_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION0_R2_PMS_W_M  (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S)
-#define LP_APM0_REGION0_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION0_R2_PMS_W_S  9
-/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION0_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION0_R2_PMS_R_M  (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S)
-#define LP_APM0_REGION0_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION0_R2_PMS_R_S  10
-
-/** LP_APM0_REGION1_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
-/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region1
- */
-#define LP_APM0_REGION1_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_START_M  (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
-#define LP_APM0_REGION1_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_START_S  0
-
-/** LP_APM0_REGION1_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
-/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region1
- */
-#define LP_APM0_REGION1_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_END_M  (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
-#define LP_APM0_REGION1_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_END_S  0
-
-/** LP_APM0_REGION1_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
-/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION1_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION1_R0_PMS_X_M  (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S)
-#define LP_APM0_REGION1_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION1_R0_PMS_X_S  0
-/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION1_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION1_R0_PMS_W_M  (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S)
-#define LP_APM0_REGION1_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION1_R0_PMS_W_S  1
-/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION1_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION1_R0_PMS_R_M  (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S)
-#define LP_APM0_REGION1_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION1_R0_PMS_R_S  2
-/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION1_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION1_R1_PMS_X_M  (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S)
-#define LP_APM0_REGION1_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION1_R1_PMS_X_S  4
-/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION1_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION1_R1_PMS_W_M  (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S)
-#define LP_APM0_REGION1_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION1_R1_PMS_W_S  5
-/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION1_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION1_R1_PMS_R_M  (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S)
-#define LP_APM0_REGION1_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION1_R1_PMS_R_S  6
-/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION1_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION1_R2_PMS_X_M  (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S)
-#define LP_APM0_REGION1_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION1_R2_PMS_X_S  8
-/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION1_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION1_R2_PMS_W_M  (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S)
-#define LP_APM0_REGION1_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION1_R2_PMS_W_S  9
-/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION1_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION1_R2_PMS_R_M  (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S)
-#define LP_APM0_REGION1_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION1_R2_PMS_R_S  10
-
-/** LP_APM0_REGION2_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
-/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region2
- */
-#define LP_APM0_REGION2_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_START_M  (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
-#define LP_APM0_REGION2_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_START_S  0
-
-/** LP_APM0_REGION2_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
-/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region2
- */
-#define LP_APM0_REGION2_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_END_M  (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
-#define LP_APM0_REGION2_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_END_S  0
-
-/** LP_APM0_REGION2_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
-/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION2_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION2_R0_PMS_X_M  (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S)
-#define LP_APM0_REGION2_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION2_R0_PMS_X_S  0
-/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION2_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION2_R0_PMS_W_M  (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S)
-#define LP_APM0_REGION2_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION2_R0_PMS_W_S  1
-/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION2_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION2_R0_PMS_R_M  (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S)
-#define LP_APM0_REGION2_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION2_R0_PMS_R_S  2
-/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION2_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION2_R1_PMS_X_M  (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S)
-#define LP_APM0_REGION2_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION2_R1_PMS_X_S  4
-/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION2_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION2_R1_PMS_W_M  (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S)
-#define LP_APM0_REGION2_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION2_R1_PMS_W_S  5
-/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION2_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION2_R1_PMS_R_M  (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S)
-#define LP_APM0_REGION2_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION2_R1_PMS_R_S  6
-/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION2_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION2_R2_PMS_X_M  (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S)
-#define LP_APM0_REGION2_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION2_R2_PMS_X_S  8
-/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION2_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION2_R2_PMS_W_M  (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S)
-#define LP_APM0_REGION2_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION2_R2_PMS_W_S  9
-/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION2_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION2_R2_PMS_R_M  (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S)
-#define LP_APM0_REGION2_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION2_R2_PMS_R_S  10
-
-/** LP_APM0_REGION3_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
-/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region3
- */
-#define LP_APM0_REGION3_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_START_M  (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
-#define LP_APM0_REGION3_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_START_S  0
-
-/** LP_APM0_REGION3_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
-/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region3
- */
-#define LP_APM0_REGION3_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_END_M  (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
-#define LP_APM0_REGION3_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_END_S  0
-
-/** LP_APM0_REGION3_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
-/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION3_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION3_R0_PMS_X_M  (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S)
-#define LP_APM0_REGION3_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION3_R0_PMS_X_S  0
-/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION3_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION3_R0_PMS_W_M  (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S)
-#define LP_APM0_REGION3_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION3_R0_PMS_W_S  1
-/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION3_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION3_R0_PMS_R_M  (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S)
-#define LP_APM0_REGION3_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION3_R0_PMS_R_S  2
-/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION3_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION3_R1_PMS_X_M  (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S)
-#define LP_APM0_REGION3_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION3_R1_PMS_X_S  4
-/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION3_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION3_R1_PMS_W_M  (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S)
-#define LP_APM0_REGION3_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION3_R1_PMS_W_S  5
-/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION3_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION3_R1_PMS_R_M  (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S)
-#define LP_APM0_REGION3_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION3_R1_PMS_R_S  6
-/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION3_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION3_R2_PMS_X_M  (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S)
-#define LP_APM0_REGION3_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION3_R2_PMS_X_S  8
-/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION3_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION3_R2_PMS_W_M  (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S)
-#define LP_APM0_REGION3_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION3_R2_PMS_W_S  9
-/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION3_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION3_R2_PMS_R_M  (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S)
-#define LP_APM0_REGION3_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION3_R2_PMS_R_S  10
-
-/** LP_APM0_FUNC_CTRL_REG register
- *  PMS function control register
- */
-#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
-/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
- *  PMS M0 function enable
- */
-#define LP_APM0_M0_PMS_FUNC_EN    (BIT(0))
-#define LP_APM0_M0_PMS_FUNC_EN_M  (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S)
-#define LP_APM0_M0_PMS_FUNC_EN_V  0x00000001U
-#define LP_APM0_M0_PMS_FUNC_EN_S  0
-
-/** LP_APM0_M0_STATUS_REG register
- *  M0 status register
- */
-#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
-/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define LP_APM0_M0_EXCEPTION_STATUS    0x00000003U
-#define LP_APM0_M0_EXCEPTION_STATUS_M  (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
-#define LP_APM0_M0_EXCEPTION_STATUS_V  0x00000003U
-#define LP_APM0_M0_EXCEPTION_STATUS_S  0
-
-/** LP_APM0_M0_STATUS_CLR_REG register
- *  M0 status clear register
- */
-#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
-/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define LP_APM0_M0_REGION_STATUS_CLR    (BIT(0))
-#define LP_APM0_M0_REGION_STATUS_CLR_M  (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S)
-#define LP_APM0_M0_REGION_STATUS_CLR_V  0x00000001U
-#define LP_APM0_M0_REGION_STATUS_CLR_S  0
-
-/** LP_APM0_M0_EXCEPTION_INFO0_REG register
- *  M0 exception_info0 register
- */
-#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
-/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
- *  Exception region
- */
-#define LP_APM0_M0_EXCEPTION_REGION    0x0000000FU
-#define LP_APM0_M0_EXCEPTION_REGION_M  (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
-#define LP_APM0_M0_EXCEPTION_REGION_V  0x0000000FU
-#define LP_APM0_M0_EXCEPTION_REGION_S  0
-/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define LP_APM0_M0_EXCEPTION_MODE    0x00000003U
-#define LP_APM0_M0_EXCEPTION_MODE_M  (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
-#define LP_APM0_M0_EXCEPTION_MODE_V  0x00000003U
-#define LP_APM0_M0_EXCEPTION_MODE_S  16
-/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define LP_APM0_M0_EXCEPTION_ID    0x0000001FU
-#define LP_APM0_M0_EXCEPTION_ID_M  (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
-#define LP_APM0_M0_EXCEPTION_ID_V  0x0000001FU
-#define LP_APM0_M0_EXCEPTION_ID_S  18
-
-/** LP_APM0_M0_EXCEPTION_INFO1_REG register
- *  M0 exception_info1 register
- */
-#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
-/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define LP_APM0_M0_EXCEPTION_ADDR    0xFFFFFFFFU
-#define LP_APM0_M0_EXCEPTION_ADDR_M  (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
-#define LP_APM0_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define LP_APM0_M0_EXCEPTION_ADDR_S  0
-
-/** LP_APM0_INT_EN_REG register
- *  APM interrupt enable register
- */
-#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
-/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
- *  APM M0 interrupt enable
- */
-#define LP_APM0_M0_APM_INT_EN    (BIT(0))
-#define LP_APM0_M0_APM_INT_EN_M  (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
-#define LP_APM0_M0_APM_INT_EN_V  0x00000001U
-#define LP_APM0_M0_APM_INT_EN_S  0
-
-/** LP_APM0_CLOCK_GATE_REG register
- *  clock gating register
- */
-#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
-/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define LP_APM0_CLK_EN    (BIT(0))
-#define LP_APM0_CLK_EN_M  (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
-#define LP_APM0_CLK_EN_V  0x00000001U
-#define LP_APM0_CLK_EN_S  0
-
-/** LP_APM0_DATE_REG register
- *  Version register
- */
-#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
-/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640;
- *  reg_date
- */
-#define LP_APM0_DATE    0x0FFFFFFFU
-#define LP_APM0_DATE_M  (LP_APM0_DATE_V << LP_APM0_DATE_S)
-#define LP_APM0_DATE_V  0x0FFFFFFFU
-#define LP_APM0_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm0_struct.h b/components/soc/esp32p4/include/soc/lp_apm0_struct.h
deleted file mode 100644
index 79939b7b37..0000000000
--- a/components/soc/esp32p4/include/soc/lp_apm0_struct.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Region filter enable register */
-/** Type of region_filter_en register
- *  Region filter enable register
- */
-typedef union {
-    struct {
-        /** region_filter_en : R/W; bitpos: [3:0]; default: 1;
-         *  Region filter enable
-         */
-        uint32_t region_filter_en:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_apm0_region_filter_en_reg_t;
-
-
-/** Group: Region address register */
-/** Type of region0_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region0
-         */
-        uint32_t region0_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region0_addr_start_reg_t;
-
-/** Type of region0_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region0
-         */
-        uint32_t region0_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region0_addr_end_reg_t;
-
-/** Type of region1_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region1
-         */
-        uint32_t region1_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region1_addr_start_reg_t;
-
-/** Type of region1_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region1
-         */
-        uint32_t region1_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region1_addr_end_reg_t;
-
-/** Type of region2_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region2
-         */
-        uint32_t region2_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region2_addr_start_reg_t;
-
-/** Type of region2_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region2
-         */
-        uint32_t region2_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region2_addr_end_reg_t;
-
-/** Type of region3_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region3
-         */
-        uint32_t region3_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region3_addr_start_reg_t;
-
-/** Type of region3_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region3
-         */
-        uint32_t region3_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region3_addr_end_reg_t;
-
-
-/** Group: Region access authority attribute register */
-/** Type of region0_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_x:1;
-        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_w:1;
-        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_x:1;
-        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_w:1;
-        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_x:1;
-        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_w:1;
-        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm0_region0_pms_attr_reg_t;
-
-/** Type of region1_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_x:1;
-        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_w:1;
-        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_x:1;
-        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_w:1;
-        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_x:1;
-        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_w:1;
-        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm0_region1_pms_attr_reg_t;
-
-/** Type of region2_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_x:1;
-        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_w:1;
-        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_x:1;
-        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_w:1;
-        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_x:1;
-        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_w:1;
-        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm0_region2_pms_attr_reg_t;
-
-/** Type of region3_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_x:1;
-        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_w:1;
-        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_x:1;
-        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_w:1;
-        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_x:1;
-        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_w:1;
-        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm0_region3_pms_attr_reg_t;
-
-
-/** Group: PMS function control register */
-/** Type of func_ctrl register
- *  PMS function control register
- */
-typedef union {
-    struct {
-        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
-         *  PMS M0 function enable
-         */
-        uint32_t m0_pms_func_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_func_ctrl_reg_t;
-
-
-/** Group: M0 status register */
-/** Type of m0_status register
- *  M0 status register
- */
-typedef union {
-    struct {
-        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m0_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm0_m0_status_reg_t;
-
-
-/** Group: M0 status clear register */
-/** Type of m0_status_clr register
- *  M0 status clear register
- */
-typedef union {
-    struct {
-        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m0_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_m0_status_clr_reg_t;
-
-
-/** Group: M0 exception_info0 register */
-/** Type of m0_exception_info0 register
- *  M0 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m0_exception_region : RO; bitpos: [3:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m0_exception_region:4;
-        uint32_t reserved_4:12;
-        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m0_exception_mode:2;
-        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m0_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_apm0_m0_exception_info0_reg_t;
-
-
-/** Group: M0 exception_info1 register */
-/** Type of m0_exception_info1 register
- *  M0 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m0_exception_addr:32;
-    };
-    uint32_t val;
-} lp_apm0_m0_exception_info1_reg_t;
-
-
-/** Group: APM interrupt enable register */
-/** Type of int_en register
- *  APM interrupt enable register
- */
-typedef union {
-    struct {
-        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
-         *  APM M0 interrupt enable
-         */
-        uint32_t m0_apm_int_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_int_en_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35672640;
-         *  reg_date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_apm0_date_reg_t;
-
-
-typedef struct lp_apm0_dev_t {
-    volatile lp_apm0_region_filter_en_reg_t region_filter_en;
-    volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
-    volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
-    volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr;
-    volatile lp_apm0_region1_addr_start_reg_t region1_addr_start;
-    volatile lp_apm0_region1_addr_end_reg_t region1_addr_end;
-    volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr;
-    volatile lp_apm0_region2_addr_start_reg_t region2_addr_start;
-    volatile lp_apm0_region2_addr_end_reg_t region2_addr_end;
-    volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr;
-    volatile lp_apm0_region3_addr_start_reg_t region3_addr_start;
-    volatile lp_apm0_region3_addr_end_reg_t region3_addr_end;
-    volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr;
-    uint32_t reserved_034[36];
-    volatile lp_apm0_func_ctrl_reg_t func_ctrl;
-    volatile lp_apm0_m0_status_reg_t m0_status;
-    volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
-    volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
-    volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
-    volatile lp_apm0_int_en_reg_t int_en;
-    volatile lp_apm0_clock_gate_reg_t clock_gate;
-    uint32_t reserved_0e0[455];
-    volatile lp_apm0_date_reg_t date;
-} lp_apm0_dev_t;
-
-extern lp_apm0_dev_t LP_APM0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm_reg.h b/components/soc/esp32p4/include/soc/lp_apm_reg.h
deleted file mode 100644
index 30b6038345..0000000000
--- a/components/soc/esp32p4/include/soc/lp_apm_reg.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_APM_REGION_FILTER_EN_REG register
- *  Region filter enable register
- */
-#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
-/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
- *  Region filter enable
- */
-#define LP_APM_REGION_FILTER_EN    0x0000000FU
-#define LP_APM_REGION_FILTER_EN_M  (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
-#define LP_APM_REGION_FILTER_EN_V  0x0000000FU
-#define LP_APM_REGION_FILTER_EN_S  0
-
-/** LP_APM_REGION0_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
-/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region0
- */
-#define LP_APM_REGION0_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_START_M  (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
-#define LP_APM_REGION0_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_START_S  0
-
-/** LP_APM_REGION0_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
-/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region0
- */
-#define LP_APM_REGION0_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_END_M  (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
-#define LP_APM_REGION0_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_END_S  0
-
-/** LP_APM_REGION0_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
-/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION0_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION0_R0_PMS_X_M  (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
-#define LP_APM_REGION0_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION0_R0_PMS_X_S  0
-/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION0_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION0_R0_PMS_W_M  (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
-#define LP_APM_REGION0_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION0_R0_PMS_W_S  1
-/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION0_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION0_R0_PMS_R_M  (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
-#define LP_APM_REGION0_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION0_R0_PMS_R_S  2
-/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION0_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION0_R1_PMS_X_M  (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
-#define LP_APM_REGION0_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION0_R1_PMS_X_S  4
-/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION0_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION0_R1_PMS_W_M  (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
-#define LP_APM_REGION0_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION0_R1_PMS_W_S  5
-/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION0_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION0_R1_PMS_R_M  (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
-#define LP_APM_REGION0_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION0_R1_PMS_R_S  6
-/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION0_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION0_R2_PMS_X_M  (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
-#define LP_APM_REGION0_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION0_R2_PMS_X_S  8
-/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION0_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION0_R2_PMS_W_M  (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
-#define LP_APM_REGION0_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION0_R2_PMS_W_S  9
-/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION0_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION0_R2_PMS_R_M  (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
-#define LP_APM_REGION0_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION0_R2_PMS_R_S  10
-
-/** LP_APM_REGION1_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
-/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region1
- */
-#define LP_APM_REGION1_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_START_M  (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
-#define LP_APM_REGION1_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_START_S  0
-
-/** LP_APM_REGION1_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
-/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region1
- */
-#define LP_APM_REGION1_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_END_M  (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
-#define LP_APM_REGION1_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_END_S  0
-
-/** LP_APM_REGION1_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
-/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION1_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION1_R0_PMS_X_M  (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
-#define LP_APM_REGION1_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION1_R0_PMS_X_S  0
-/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION1_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION1_R0_PMS_W_M  (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
-#define LP_APM_REGION1_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION1_R0_PMS_W_S  1
-/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION1_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION1_R0_PMS_R_M  (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
-#define LP_APM_REGION1_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION1_R0_PMS_R_S  2
-/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION1_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION1_R1_PMS_X_M  (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
-#define LP_APM_REGION1_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION1_R1_PMS_X_S  4
-/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION1_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION1_R1_PMS_W_M  (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
-#define LP_APM_REGION1_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION1_R1_PMS_W_S  5
-/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION1_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION1_R1_PMS_R_M  (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
-#define LP_APM_REGION1_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION1_R1_PMS_R_S  6
-/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION1_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION1_R2_PMS_X_M  (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
-#define LP_APM_REGION1_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION1_R2_PMS_X_S  8
-/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION1_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION1_R2_PMS_W_M  (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
-#define LP_APM_REGION1_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION1_R2_PMS_W_S  9
-/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION1_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION1_R2_PMS_R_M  (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
-#define LP_APM_REGION1_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION1_R2_PMS_R_S  10
-
-/** LP_APM_REGION2_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
-/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region2
- */
-#define LP_APM_REGION2_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_START_M  (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
-#define LP_APM_REGION2_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_START_S  0
-
-/** LP_APM_REGION2_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
-/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region2
- */
-#define LP_APM_REGION2_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_END_M  (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
-#define LP_APM_REGION2_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_END_S  0
-
-/** LP_APM_REGION2_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
-/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION2_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION2_R0_PMS_X_M  (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
-#define LP_APM_REGION2_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION2_R0_PMS_X_S  0
-/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION2_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION2_R0_PMS_W_M  (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
-#define LP_APM_REGION2_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION2_R0_PMS_W_S  1
-/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION2_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION2_R0_PMS_R_M  (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
-#define LP_APM_REGION2_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION2_R0_PMS_R_S  2
-/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION2_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION2_R1_PMS_X_M  (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
-#define LP_APM_REGION2_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION2_R1_PMS_X_S  4
-/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION2_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION2_R1_PMS_W_M  (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
-#define LP_APM_REGION2_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION2_R1_PMS_W_S  5
-/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION2_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION2_R1_PMS_R_M  (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
-#define LP_APM_REGION2_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION2_R1_PMS_R_S  6
-/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION2_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION2_R2_PMS_X_M  (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
-#define LP_APM_REGION2_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION2_R2_PMS_X_S  8
-/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION2_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION2_R2_PMS_W_M  (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
-#define LP_APM_REGION2_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION2_R2_PMS_W_S  9
-/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION2_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION2_R2_PMS_R_M  (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
-#define LP_APM_REGION2_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION2_R2_PMS_R_S  10
-
-/** LP_APM_REGION3_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
-/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region3
- */
-#define LP_APM_REGION3_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_START_M  (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
-#define LP_APM_REGION3_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_START_S  0
-
-/** LP_APM_REGION3_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
-/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region3
- */
-#define LP_APM_REGION3_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_END_M  (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
-#define LP_APM_REGION3_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_END_S  0
-
-/** LP_APM_REGION3_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
-/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION3_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION3_R0_PMS_X_M  (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
-#define LP_APM_REGION3_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION3_R0_PMS_X_S  0
-/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION3_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION3_R0_PMS_W_M  (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
-#define LP_APM_REGION3_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION3_R0_PMS_W_S  1
-/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION3_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION3_R0_PMS_R_M  (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
-#define LP_APM_REGION3_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION3_R0_PMS_R_S  2
-/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION3_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION3_R1_PMS_X_M  (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
-#define LP_APM_REGION3_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION3_R1_PMS_X_S  4
-/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION3_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION3_R1_PMS_W_M  (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
-#define LP_APM_REGION3_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION3_R1_PMS_W_S  5
-/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION3_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION3_R1_PMS_R_M  (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
-#define LP_APM_REGION3_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION3_R1_PMS_R_S  6
-/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION3_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION3_R2_PMS_X_M  (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
-#define LP_APM_REGION3_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION3_R2_PMS_X_S  8
-/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION3_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION3_R2_PMS_W_M  (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
-#define LP_APM_REGION3_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION3_R2_PMS_W_S  9
-/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION3_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION3_R2_PMS_R_M  (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
-#define LP_APM_REGION3_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION3_R2_PMS_R_S  10
-
-/** LP_APM_FUNC_CTRL_REG register
- *  PMS function control register
- */
-#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
-/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
- *  PMS M0 function enable
- */
-#define LP_APM_M0_PMS_FUNC_EN    (BIT(0))
-#define LP_APM_M0_PMS_FUNC_EN_M  (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
-#define LP_APM_M0_PMS_FUNC_EN_V  0x00000001U
-#define LP_APM_M0_PMS_FUNC_EN_S  0
-/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
- *  PMS M1 function enable
- */
-#define LP_APM_M1_PMS_FUNC_EN    (BIT(1))
-#define LP_APM_M1_PMS_FUNC_EN_M  (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S)
-#define LP_APM_M1_PMS_FUNC_EN_V  0x00000001U
-#define LP_APM_M1_PMS_FUNC_EN_S  1
-
-/** LP_APM_M0_STATUS_REG register
- *  M0 status register
- */
-#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
-/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define LP_APM_M0_EXCEPTION_STATUS    0x00000003U
-#define LP_APM_M0_EXCEPTION_STATUS_M  (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
-#define LP_APM_M0_EXCEPTION_STATUS_V  0x00000003U
-#define LP_APM_M0_EXCEPTION_STATUS_S  0
-
-/** LP_APM_M0_STATUS_CLR_REG register
- *  M0 status clear register
- */
-#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
-/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define LP_APM_M0_REGION_STATUS_CLR    (BIT(0))
-#define LP_APM_M0_REGION_STATUS_CLR_M  (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
-#define LP_APM_M0_REGION_STATUS_CLR_V  0x00000001U
-#define LP_APM_M0_REGION_STATUS_CLR_S  0
-
-/** LP_APM_M0_EXCEPTION_INFO0_REG register
- *  M0 exception_info0 register
- */
-#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
-/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
- *  Exception region
- */
-#define LP_APM_M0_EXCEPTION_REGION    0x0000000FU
-#define LP_APM_M0_EXCEPTION_REGION_M  (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
-#define LP_APM_M0_EXCEPTION_REGION_V  0x0000000FU
-#define LP_APM_M0_EXCEPTION_REGION_S  0
-/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define LP_APM_M0_EXCEPTION_MODE    0x00000003U
-#define LP_APM_M0_EXCEPTION_MODE_M  (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
-#define LP_APM_M0_EXCEPTION_MODE_V  0x00000003U
-#define LP_APM_M0_EXCEPTION_MODE_S  16
-/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define LP_APM_M0_EXCEPTION_ID    0x0000001FU
-#define LP_APM_M0_EXCEPTION_ID_M  (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
-#define LP_APM_M0_EXCEPTION_ID_V  0x0000001FU
-#define LP_APM_M0_EXCEPTION_ID_S  18
-
-/** LP_APM_M0_EXCEPTION_INFO1_REG register
- *  M0 exception_info1 register
- */
-#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
-/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define LP_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
-#define LP_APM_M0_EXCEPTION_ADDR_M  (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
-#define LP_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define LP_APM_M0_EXCEPTION_ADDR_S  0
-
-/** LP_APM_M1_STATUS_REG register
- *  M1 status register
- */
-#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
-/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define LP_APM_M1_EXCEPTION_STATUS    0x00000003U
-#define LP_APM_M1_EXCEPTION_STATUS_M  (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
-#define LP_APM_M1_EXCEPTION_STATUS_V  0x00000003U
-#define LP_APM_M1_EXCEPTION_STATUS_S  0
-
-/** LP_APM_M1_STATUS_CLR_REG register
- *  M1 status clear register
- */
-#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
-/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define LP_APM_M1_REGION_STATUS_CLR    (BIT(0))
-#define LP_APM_M1_REGION_STATUS_CLR_M  (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S)
-#define LP_APM_M1_REGION_STATUS_CLR_V  0x00000001U
-#define LP_APM_M1_REGION_STATUS_CLR_S  0
-
-/** LP_APM_M1_EXCEPTION_INFO0_REG register
- *  M1 exception_info0 register
- */
-#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
-/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
- *  Exception region
- */
-#define LP_APM_M1_EXCEPTION_REGION    0x0000000FU
-#define LP_APM_M1_EXCEPTION_REGION_M  (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
-#define LP_APM_M1_EXCEPTION_REGION_V  0x0000000FU
-#define LP_APM_M1_EXCEPTION_REGION_S  0
-/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define LP_APM_M1_EXCEPTION_MODE    0x00000003U
-#define LP_APM_M1_EXCEPTION_MODE_M  (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
-#define LP_APM_M1_EXCEPTION_MODE_V  0x00000003U
-#define LP_APM_M1_EXCEPTION_MODE_S  16
-/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define LP_APM_M1_EXCEPTION_ID    0x0000001FU
-#define LP_APM_M1_EXCEPTION_ID_M  (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
-#define LP_APM_M1_EXCEPTION_ID_V  0x0000001FU
-#define LP_APM_M1_EXCEPTION_ID_S  18
-
-/** LP_APM_M1_EXCEPTION_INFO1_REG register
- *  M1 exception_info1 register
- */
-#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
-/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define LP_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
-#define LP_APM_M1_EXCEPTION_ADDR_M  (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
-#define LP_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define LP_APM_M1_EXCEPTION_ADDR_S  0
-
-/** LP_APM_INT_EN_REG register
- *  APM interrupt enable register
- */
-#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
-/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
- *  APM M0 interrupt enable
- */
-#define LP_APM_M0_APM_INT_EN    (BIT(0))
-#define LP_APM_M0_APM_INT_EN_M  (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
-#define LP_APM_M0_APM_INT_EN_V  0x00000001U
-#define LP_APM_M0_APM_INT_EN_S  0
-/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
- *  APM M1 interrupt enable
- */
-#define LP_APM_M1_APM_INT_EN    (BIT(1))
-#define LP_APM_M1_APM_INT_EN_M  (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
-#define LP_APM_M1_APM_INT_EN_V  0x00000001U
-#define LP_APM_M1_APM_INT_EN_S  1
-
-/** LP_APM_CLOCK_GATE_REG register
- *  clock gating register
- */
-#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
-/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define LP_APM_CLK_EN    (BIT(0))
-#define LP_APM_CLK_EN_M  (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
-#define LP_APM_CLK_EN_V  0x00000001U
-#define LP_APM_CLK_EN_S  0
-
-/** LP_APM_DATE_REG register
- *  Version register
- */
-#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
-/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
- *  reg_date
- */
-#define LP_APM_DATE    0x0FFFFFFFU
-#define LP_APM_DATE_M  (LP_APM_DATE_V << LP_APM_DATE_S)
-#define LP_APM_DATE_V  0x0FFFFFFFU
-#define LP_APM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_apm_struct.h b/components/soc/esp32p4/include/soc/lp_apm_struct.h
deleted file mode 100644
index 82587d5501..0000000000
--- a/components/soc/esp32p4/include/soc/lp_apm_struct.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Region filter enable register */
-/** Type of region_filter_en register
- *  Region filter enable register
- */
-typedef union {
-    struct {
-        /** region_filter_en : R/W; bitpos: [3:0]; default: 1;
-         *  Region filter enable
-         */
-        uint32_t region_filter_en:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_apm_region_filter_en_reg_t;
-
-
-/** Group: Region address register */
-/** Type of region0_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region0
-         */
-        uint32_t region0_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region0_addr_start_reg_t;
-
-/** Type of region0_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region0
-         */
-        uint32_t region0_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region0_addr_end_reg_t;
-
-/** Type of region1_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region1
-         */
-        uint32_t region1_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region1_addr_start_reg_t;
-
-/** Type of region1_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region1
-         */
-        uint32_t region1_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region1_addr_end_reg_t;
-
-/** Type of region2_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region2
-         */
-        uint32_t region2_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region2_addr_start_reg_t;
-
-/** Type of region2_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region2
-         */
-        uint32_t region2_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region2_addr_end_reg_t;
-
-/** Type of region3_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region3
-         */
-        uint32_t region3_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region3_addr_start_reg_t;
-
-/** Type of region3_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region3
-         */
-        uint32_t region3_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region3_addr_end_reg_t;
-
-
-/** Group: Region access authority attribute register */
-/** Type of region0_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_x:1;
-        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_w:1;
-        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_x:1;
-        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_w:1;
-        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_x:1;
-        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_w:1;
-        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm_region0_pms_attr_reg_t;
-
-/** Type of region1_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_x:1;
-        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_w:1;
-        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_x:1;
-        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_w:1;
-        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_x:1;
-        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_w:1;
-        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm_region1_pms_attr_reg_t;
-
-/** Type of region2_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_x:1;
-        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_w:1;
-        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_x:1;
-        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_w:1;
-        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_x:1;
-        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_w:1;
-        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm_region2_pms_attr_reg_t;
-
-/** Type of region3_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_x:1;
-        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_w:1;
-        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_x:1;
-        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_w:1;
-        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_x:1;
-        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_w:1;
-        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_r:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_apm_region3_pms_attr_reg_t;
-
-
-/** Group: PMS function control register */
-/** Type of func_ctrl register
- *  PMS function control register
- */
-typedef union {
-    struct {
-        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
-         *  PMS M0 function enable
-         */
-        uint32_t m0_pms_func_en:1;
-        /** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
-         *  PMS M1 function enable
-         */
-        uint32_t m1_pms_func_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_func_ctrl_reg_t;
-
-
-/** Group: M0 status register */
-/** Type of m0_status register
- *  M0 status register
- */
-typedef union {
-    struct {
-        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m0_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_m0_status_reg_t;
-
-
-/** Group: M0 status clear register */
-/** Type of m0_status_clr register
- *  M0 status clear register
- */
-typedef union {
-    struct {
-        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m0_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm_m0_status_clr_reg_t;
-
-
-/** Group: M0 exception_info0 register */
-/** Type of m0_exception_info0 register
- *  M0 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m0_exception_region : RO; bitpos: [3:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m0_exception_region:4;
-        uint32_t reserved_4:12;
-        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m0_exception_mode:2;
-        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m0_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_apm_m0_exception_info0_reg_t;
-
-
-/** Group: M0 exception_info1 register */
-/** Type of m0_exception_info1 register
- *  M0 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m0_exception_addr:32;
-    };
-    uint32_t val;
-} lp_apm_m0_exception_info1_reg_t;
-
-
-/** Group: M1 status register */
-/** Type of m1_status register
- *  M1 status register
- */
-typedef union {
-    struct {
-        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m1_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_m1_status_reg_t;
-
-
-/** Group: M1 status clear register */
-/** Type of m1_status_clr register
- *  M1 status clear register
- */
-typedef union {
-    struct {
-        /** m1_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m1_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm_m1_status_clr_reg_t;
-
-
-/** Group: M1 exception_info0 register */
-/** Type of m1_exception_info0 register
- *  M1 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m1_exception_region : RO; bitpos: [3:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m1_exception_region:4;
-        uint32_t reserved_4:12;
-        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m1_exception_mode:2;
-        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m1_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_apm_m1_exception_info0_reg_t;
-
-
-/** Group: M1 exception_info1 register */
-/** Type of m1_exception_info1 register
- *  M1 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m1_exception_addr:32;
-    };
-    uint32_t val;
-} lp_apm_m1_exception_info1_reg_t;
-
-
-/** Group: APM interrupt enable register */
-/** Type of int_en register
- *  APM interrupt enable register
- */
-typedef union {
-    struct {
-        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
-         *  APM M0 interrupt enable
-         */
-        uint32_t m0_apm_int_en:1;
-        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
-         *  APM M1 interrupt enable
-         */
-        uint32_t m1_apm_int_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_int_en_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35672640;
-         *  reg_date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_apm_date_reg_t;
-
-
-typedef struct lp_apm_dev_t {
-    volatile lp_apm_region_filter_en_reg_t region_filter_en;
-    volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
-    volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
-    volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
-    volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
-    volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
-    volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
-    volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
-    volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
-    volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
-    volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
-    volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
-    volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
-    uint32_t reserved_034[36];
-    volatile lp_apm_func_ctrl_reg_t func_ctrl;
-    volatile lp_apm_m0_status_reg_t m0_status;
-    volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
-    volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
-    volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
-    volatile lp_apm_m1_status_reg_t m1_status;
-    volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
-    volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
-    volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
-    volatile lp_apm_int_en_reg_t int_en;
-    volatile lp_apm_clock_gate_reg_t clock_gate;
-    uint32_t reserved_0f0[3];
-    volatile lp_apm_date_reg_t date;
-} lp_apm_dev_t;
-
-extern lp_apm_dev_t LP_APM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h
index 6d7ef6a48c..de3f17820c 100644
--- a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h
+++ b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -22,226 +22,495 @@ extern "C" {
 #define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
 #define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
 #define LP_CLKRST_SLOW_CLK_SEL_S  0
-/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1;
+/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
  *  need_des
  */
-#define LP_CLKRST_FAST_CLK_SEL    (BIT(2))
+#define LP_CLKRST_FAST_CLK_SEL    0x00000003U
 #define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
-#define LP_CLKRST_FAST_CLK_SEL_V  0x00000001U
+#define LP_CLKRST_FAST_CLK_SEL_V  0x00000003U
 #define LP_CLKRST_FAST_CLK_SEL_S  2
-/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_LP_PERI_DIV_NUM    0x000000FFU
+#define LP_CLKRST_LP_PERI_DIV_NUM    0x0000003FU
 #define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
-#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x000000FFU
-#define LP_CLKRST_LP_PERI_DIV_NUM_S  3
+#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x0000003FU
+#define LP_CLKRST_LP_PERI_DIV_NUM_S  4
+/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_ANA_SEL_REF_PLL8M    (BIT(10))
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_M  (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S)
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_V  0x00000001U
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_S  10
 
 /** LP_CLKRST_LP_CLK_PO_EN_REG register
  *  need_des
  */
 #define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
-/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
+/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_AON_SLOW_OEN    (BIT(0))
-#define LP_CLKRST_AON_SLOW_OEN_M  (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
-#define LP_CLKRST_AON_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_AON_SLOW_OEN_S  0
-/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN    (BIT(0))
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M  (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S)
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S  0
+/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_AON_FAST_OEN    (BIT(1))
-#define LP_CLKRST_AON_FAST_OEN_M  (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
-#define LP_CLKRST_AON_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_AON_FAST_OEN_S  1
-/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
+#define LP_CLKRST_CLK_LP_BUS_OEN    (BIT(1))
+#define LP_CLKRST_CLK_LP_BUS_OEN_M  (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S)
+#define LP_CLKRST_CLK_LP_BUS_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_LP_BUS_OEN_S  1
+/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_SOSC_OEN    (BIT(2))
-#define LP_CLKRST_SOSC_OEN_M  (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
-#define LP_CLKRST_SOSC_OEN_V  0x00000001U
-#define LP_CLKRST_SOSC_OEN_S  2
-/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
+#define LP_CLKRST_CLK_AON_SLOW_OEN    (BIT(2))
+#define LP_CLKRST_CLK_AON_SLOW_OEN_M  (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S)
+#define LP_CLKRST_CLK_AON_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_AON_SLOW_OEN_S  2
+/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_FOSC_OEN    (BIT(3))
-#define LP_CLKRST_FOSC_OEN_M  (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
-#define LP_CLKRST_FOSC_OEN_V  0x00000001U
-#define LP_CLKRST_FOSC_OEN_S  3
-/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
+#define LP_CLKRST_CLK_AON_FAST_OEN    (BIT(3))
+#define LP_CLKRST_CLK_AON_FAST_OEN_M  (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S)
+#define LP_CLKRST_CLK_AON_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_AON_FAST_OEN_S  3
+/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_OSC32K_OEN    (BIT(4))
-#define LP_CLKRST_OSC32K_OEN_M  (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
-#define LP_CLKRST_OSC32K_OEN_V  0x00000001U
-#define LP_CLKRST_OSC32K_OEN_S  4
-/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
+#define LP_CLKRST_CLK_SLOW_OEN    (BIT(4))
+#define LP_CLKRST_CLK_SLOW_OEN_M  (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S)
+#define LP_CLKRST_CLK_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SLOW_OEN_S  4
+/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_XTAL32K_OEN    (BIT(5))
-#define LP_CLKRST_XTAL32K_OEN_M  (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
-#define LP_CLKRST_XTAL32K_OEN_V  0x00000001U
-#define LP_CLKRST_XTAL32K_OEN_S  5
-/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
+#define LP_CLKRST_CLK_FAST_OEN    (BIT(5))
+#define LP_CLKRST_CLK_FAST_OEN_M  (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S)
+#define LP_CLKRST_CLK_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_FAST_OEN_S  5
+/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_CORE_EFUSE_OEN    (BIT(6))
-#define LP_CLKRST_CORE_EFUSE_OEN_M  (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
-#define LP_CLKRST_CORE_EFUSE_OEN_V  0x00000001U
-#define LP_CLKRST_CORE_EFUSE_OEN_S  6
-/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
+#define LP_CLKRST_CLK_FOSC_OEN    (BIT(6))
+#define LP_CLKRST_CLK_FOSC_OEN_M  (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S)
+#define LP_CLKRST_CLK_FOSC_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_FOSC_OEN_S  6
+/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_SLOW_OEN    (BIT(7))
-#define LP_CLKRST_SLOW_OEN_M  (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
-#define LP_CLKRST_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_SLOW_OEN_S  7
-/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
+#define LP_CLKRST_CLK_RC32K_OEN    (BIT(7))
+#define LP_CLKRST_CLK_RC32K_OEN_M  (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S)
+#define LP_CLKRST_CLK_RC32K_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_RC32K_OEN_S  7
+/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_FAST_OEN    (BIT(8))
-#define LP_CLKRST_FAST_OEN_M  (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
-#define LP_CLKRST_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_FAST_OEN_S  8
-/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
- *  need_des
+#define LP_CLKRST_CLK_SXTAL_OEN    (BIT(8))
+#define LP_CLKRST_CLK_SXTAL_OEN_M  (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S)
+#define LP_CLKRST_CLK_SXTAL_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SXTAL_OEN_S  8
+/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0;
+ *  1'b1: probe sosc clk on
+ *  1'b0: probe sosc clk off
  */
-#define LP_CLKRST_RNG_OEN    (BIT(9))
-#define LP_CLKRST_RNG_OEN_M  (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
-#define LP_CLKRST_RNG_OEN_V  0x00000001U
-#define LP_CLKRST_RNG_OEN_S  9
-/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_LPBUS_OEN    (BIT(10))
-#define LP_CLKRST_LPBUS_OEN_M  (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
-#define LP_CLKRST_LPBUS_OEN_V  0x00000001U
-#define LP_CLKRST_LPBUS_OEN_S  10
+#define LP_CLKRST_CLK_SOSC_OEN    (BIT(9))
+#define LP_CLKRST_CLK_SOSC_OEN_M  (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S)
+#define LP_CLKRST_CLK_SOSC_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SOSC_OEN_S  9
 
 /** LP_CLKRST_LP_CLK_EN_REG register
  *  need_des
  */
 #define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
-/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
+/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_FAST_ORI_GATE    (BIT(31))
-#define LP_CLKRST_FAST_ORI_GATE_M  (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
-#define LP_CLKRST_FAST_ORI_GATE_V  0x00000001U
-#define LP_CLKRST_FAST_ORI_GATE_S  31
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON    (BIT(26))
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M  (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S)
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S  26
+/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_CK_EN_LP_RAM    (BIT(27))
+#define LP_CLKRST_CK_EN_LP_RAM_M  (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S)
+#define LP_CLKRST_CK_EN_LP_RAM_V  0x00000001U
+#define LP_CLKRST_CK_EN_LP_RAM_S  27
+/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_ETM_EVENT_TICK_EN    (BIT(28))
+#define LP_CLKRST_ETM_EVENT_TICK_EN_M  (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S)
+#define LP_CLKRST_ETM_EVENT_TICK_EN_V  0x00000001U
+#define LP_CLKRST_ETM_EVENT_TICK_EN_S  28
+/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON    (BIT(29))
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M  (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S)
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S  29
+/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_XTAL_CLK_FORCE_ON    (BIT(30))
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_M  (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S)
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_S  30
+/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_CLK_FORCE_ON    (BIT(31))
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_M  (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S)
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_S  31
 
 /** LP_CLKRST_LP_RST_EN_REG register
  *  need_des
  */
 #define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
-/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
+/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN    (BIT(28))
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M  (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V  0x00000001U
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S  28
-/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
+#define LP_CLKRST_RST_EN_LP_HUK    (BIT(24))
+#define LP_CLKRST_RST_EN_LP_HUK_M  (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S)
+#define LP_CLKRST_RST_EN_LP_HUK_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_HUK_S  24
+/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_LP_TIMER_RESET_EN    (BIT(29))
-#define LP_CLKRST_LP_TIMER_RESET_EN_M  (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
-#define LP_CLKRST_LP_TIMER_RESET_EN_V  0x00000001U
-#define LP_CLKRST_LP_TIMER_RESET_EN_S  29
-/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
+#define LP_CLKRST_RST_EN_LP_ANAPERI    (BIT(25))
+#define LP_CLKRST_RST_EN_LP_ANAPERI_M  (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S)
+#define LP_CLKRST_RST_EN_LP_ANAPERI_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_ANAPERI_S  25
+/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_WDT_RESET_EN    (BIT(30))
-#define LP_CLKRST_WDT_RESET_EN_M  (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
-#define LP_CLKRST_WDT_RESET_EN_V  0x00000001U
-#define LP_CLKRST_WDT_RESET_EN_S  30
-/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
+#define LP_CLKRST_RST_EN_LP_WDT    (BIT(26))
+#define LP_CLKRST_RST_EN_LP_WDT_M  (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S)
+#define LP_CLKRST_RST_EN_LP_WDT_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_WDT_S  26
+/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_ANA_PERI_RESET_EN    (BIT(31))
-#define LP_CLKRST_ANA_PERI_RESET_EN_M  (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
-#define LP_CLKRST_ANA_PERI_RESET_EN_V  0x00000001U
-#define LP_CLKRST_ANA_PERI_RESET_EN_S  31
+#define LP_CLKRST_RST_EN_LP_TIMER    (BIT(27))
+#define LP_CLKRST_RST_EN_LP_TIMER_M  (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S)
+#define LP_CLKRST_RST_EN_LP_TIMER_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_TIMER_S  27
+/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_RTC    (BIT(28))
+#define LP_CLKRST_RST_EN_LP_RTC_M  (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S)
+#define LP_CLKRST_RST_EN_LP_RTC_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_RTC_S  28
+/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_MAILBOX    (BIT(29))
+#define LP_CLKRST_RST_EN_LP_MAILBOX_M  (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S)
+#define LP_CLKRST_RST_EN_LP_MAILBOX_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_MAILBOX_S  29
+/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG    (BIT(30))
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M  (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S)
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S  30
+/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_RAM    (BIT(31))
+#define LP_CLKRST_RST_EN_LP_RAM_M  (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S)
+#define LP_CLKRST_RST_EN_LP_RAM_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_RAM_S  31
 
 /** LP_CLKRST_RESET_CAUSE_REG register
  *  need_des
  */
 #define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
-/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
+/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0;
+ *  6'h1: POR reset
+ *  6'h9: PMU LP PERI power down reset
+ *  6'ha: PMU LP CPU reset
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: software reset
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_LPCORE_RESET_CAUSE_M  (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_LPCORE_RESET_CAUSE_S  0
+/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_RESET_CAUSE    0x0000001FU
-#define LP_CLKRST_RESET_CAUSE_M  (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
-#define LP_CLKRST_RESET_CAUSE_V  0x0000001FU
-#define LP_CLKRST_RESET_CAUSE_S  0
-/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
+#define LP_CLKRST_LPCORE_RESET_FLAG    (BIT(6))
+#define LP_CLKRST_LPCORE_RESET_FLAG_M  (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S)
+#define LP_CLKRST_LPCORE_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_FLAG_S  6
+/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0;
+ *  6'h1: POR reset
+ *  6'h3: digital system software reset
+ *  6'h5: PMU HP system power down reset
+ *  6'h7: HP system reset from HP watchdog
+ *  6'h9: HP system reset from LP watchdog
+ *  6'hb: HP core reset from HP watchdog
+ *  6'hc: HP core software reset
+ *  6'hd: HP core reset from LP watchdog
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: efuse crc error reset
+ *  6'h16: HP usb jtag chip reset
+ *  6'h17: HP usb uart chip reset
+ *  6'h18: HP jtag reset
+ *  6'h1a: HP core lockup
+ */
+#define LP_CLKRST_HPCORE0_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S)
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_S  7
+/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_CORE0_RESET_FLAG    (BIT(5))
-#define LP_CLKRST_CORE0_RESET_FLAG_M  (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_S  5
-/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
+#define LP_CLKRST_HPCORE0_RESET_FLAG    (BIT(13))
+#define LP_CLKRST_HPCORE0_RESET_FLAG_M  (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S)
+#define LP_CLKRST_HPCORE0_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_FLAG_S  13
+/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0;
+ *  6'h1: POR reset
+ *  6'h3: digital system software reset
+ *  6'h5: PMU HP system power down reset
+ *  6'h7: HP system reset from HP watchdog
+ *  6'h9: HP system reset from LP watchdog
+ *  6'hb: HP core reset from HP watchdog
+ *  6'hc: HP core software reset
+ *  6'hd: HP core reset from LP watchdog
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: efuse crc error reset
+ *  6'h16: HP usb jtag chip reset
+ *  6'h17: HP usb uart chip reset
+ *  6'h18: HP jtag reset
+ *  6'h1a: HP core lockup
+ */
+#define LP_CLKRST_HPCORE1_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S)
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_S  14
+/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR    (BIT(29))
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S  29
-/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
+#define LP_CLKRST_HPCORE1_RESET_FLAG    (BIT(20))
+#define LP_CLKRST_HPCORE1_RESET_FLAG_M  (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S)
+#define LP_CLKRST_HPCORE1_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_FLAG_S  20
+/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1;
+ *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
+ *  pmu_lp_cpu_reset reset_cause
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK    (BIT(25))
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M  (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S  25
+/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_CORE0_RESET_FLAG_SET    (BIT(30))
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_M  (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_S  30
-/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR    (BIT(26))
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M  (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S  26
+/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR    (BIT(31))
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M  (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S  31
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR    (BIT(27))
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M  (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S)
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S  27
+/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR    (BIT(28))
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S  28
+/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR    (BIT(29))
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S)
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S  29
+/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR    (BIT(30))
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S  30
+/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR    (BIT(31))
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S)
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S  31
 
-/** LP_CLKRST_CPU_RESET_REG register
+/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register
  *  need_des
  */
-#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
-/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
+#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14)
+/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0;
+ *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
+ *  reset feature
+ */
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(0))
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S  0
+/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1;
  *  need_des
  */
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH    0x00000007U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M  (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V  0x00000007U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S  22
-/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S)
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S  1
+/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0;
+ *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
+ *  hpcore0 feature
+ */
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN    (BIT(4))
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S)
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S  4
+/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN    (BIT(25))
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M  (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V  0x00000001U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S  25
-/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
+#define LP_CLKRST_HPCORE0_STALL_WAIT    0x0000007FU
+#define LP_CLKRST_HPCORE0_STALL_WAIT_M  (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S)
+#define LP_CLKRST_HPCORE0_STALL_WAIT_V  0x0000007FU
+#define LP_CLKRST_HPCORE0_STALL_WAIT_S  5
+/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_CPU_STALL_WAIT    0x0000001FU
-#define LP_CLKRST_CPU_STALL_WAIT_M  (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
-#define LP_CLKRST_CPU_STALL_WAIT_V  0x0000001FU
-#define LP_CLKRST_CPU_STALL_WAIT_S  26
-/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
+#define LP_CLKRST_HPCORE0_STALL_EN    (BIT(12))
+#define LP_CLKRST_HPCORE0_STALL_EN_M  (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S)
+#define LP_CLKRST_HPCORE0_STALL_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE0_STALL_EN_S  12
+/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0;
  *  need_des
  */
-#define LP_CLKRST_CPU_STALL_EN    (BIT(31))
-#define LP_CLKRST_CPU_STALL_EN_M  (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
-#define LP_CLKRST_CPU_STALL_EN_V  0x00000001U
-#define LP_CLKRST_CPU_STALL_EN_S  31
+#define LP_CLKRST_HPCORE0_SW_RESET    (BIT(13))
+#define LP_CLKRST_HPCORE0_SW_RESET_M  (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S)
+#define LP_CLKRST_HPCORE0_SW_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE0_SW_RESET_S  13
+/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET    (BIT(14))
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S)
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S  14
+/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1;
+ *  1'b1: boot from HP TCM ROM: 0x4FC00000
+ *  1'b0: boot from LP TCM RAM:  0x50108000
+ */
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL    (BIT(15))
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S)
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V  0x00000001U
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S  15
+/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0;
+ *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
+ *  reset feature
+ */
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN    (BIT(16))
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S)
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S  16
+/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S)
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S  17
+/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0;
+ *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
+ *  hpcore1 feature
+ */
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN    (BIT(20))
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S)
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S  20
+/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_STALL_WAIT    0x0000007FU
+#define LP_CLKRST_HPCORE1_STALL_WAIT_M  (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S)
+#define LP_CLKRST_HPCORE1_STALL_WAIT_V  0x0000007FU
+#define LP_CLKRST_HPCORE1_STALL_WAIT_S  21
+/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_STALL_EN    (BIT(28))
+#define LP_CLKRST_HPCORE1_STALL_EN_M  (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S)
+#define LP_CLKRST_HPCORE1_STALL_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE1_STALL_EN_S  28
+/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_SW_RESET    (BIT(29))
+#define LP_CLKRST_HPCORE1_SW_RESET_M  (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S)
+#define LP_CLKRST_HPCORE1_SW_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE1_SW_RESET_S  29
+/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET    (BIT(30))
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S)
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S  30
+/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1;
+ *  1'b1: boot from HP TCM ROM: 0x4FC00000
+ *  1'b0: boot from LP TCM RAM:  0x50108000
+ */
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL    (BIT(31))
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S)
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V  0x00000001U
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S  31
+
+/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18)
+/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0;
+ *  HP core0 software stall when set to 8'h86
+ */
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE    0x000000FFU
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M  (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S)
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V  0x000000FFU
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S  16
+/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0;
+ *  HP core1 software stall when set to 8'h86
+ */
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE    0x000000FFU
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M  (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S)
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V  0x000000FFU
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S  24
 
 /** LP_CLKRST_FOSC_CNTL_REG register
  *  need_des
  */
-#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
-/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
+#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
+/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400;
  *  need_des
  */
 #define LP_CLKRST_FOSC_DFREQ    0x000003FFU
@@ -252,42 +521,54 @@ extern "C" {
 /** LP_CLKRST_RC32K_CNTL_REG register
  *  need_des
  */
-#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
-/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
+#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20)
+/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650;
  *  need_des
  */
-#define LP_CLKRST_RC32K_DFREQ    0x000003FFU
+#define LP_CLKRST_RC32K_DFREQ    0xFFFFFFFFU
 #define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
-#define LP_CLKRST_RC32K_DFREQ_V  0x000003FFU
-#define LP_CLKRST_RC32K_DFREQ_S  22
+#define LP_CLKRST_RC32K_DFREQ_V  0xFFFFFFFFU
+#define LP_CLKRST_RC32K_DFREQ_S  0
+
+/** LP_CLKRST_SOSC_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24)
+/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
+ *  need_des
+ */
+#define LP_CLKRST_SOSC_DFREQ    0x000003FFU
+#define LP_CLKRST_SOSC_DFREQ_M  (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S)
+#define LP_CLKRST_SOSC_DFREQ_V  0x000003FFU
+#define LP_CLKRST_SOSC_DFREQ_S  22
 
 /** LP_CLKRST_CLK_TO_HP_REG register
  *  need_des
  */
-#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
+#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28)
 /** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
- *  need_des
+ *  reserved
  */
 #define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
 #define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
 #define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
 #define LP_CLKRST_ICG_HP_XTAL32K_S  28
 /** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
- *  need_des
+ *  reserved
  */
 #define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
 #define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
 #define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
 #define LP_CLKRST_ICG_HP_SOSC_S  29
 /** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
- *  need_des
+ *  reserved
  */
 #define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
 #define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
 #define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
 #define LP_CLKRST_ICG_HP_OSC32K_S  30
 /** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
- *  need_des
+ *  reserved
  */
 #define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
 #define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
@@ -297,38 +578,19 @@ extern "C" {
 /** LP_CLKRST_LPMEM_FORCE_REG register
  *  need_des
  */
-#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
+#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
 /** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  need_des
+ *  reserved
  */
 #define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
 #define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
 #define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
 #define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
 
-/** LP_CLKRST_LPPERI_REG register
- *  need_des
- */
-#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
-/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_I2C_CLK_SEL    (BIT(30))
-#define LP_CLKRST_LP_I2C_CLK_SEL_M  (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
-#define LP_CLKRST_LP_I2C_CLK_SEL_V  0x00000001U
-#define LP_CLKRST_LP_I2C_CLK_SEL_S  30
-/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_UART_CLK_SEL    (BIT(31))
-#define LP_CLKRST_LP_UART_CLK_SEL_M  (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
-#define LP_CLKRST_LP_UART_CLK_SEL_V  0x00000001U
-#define LP_CLKRST_LP_UART_CLK_SEL_S  31
-
 /** LP_CLKRST_XTAL32K_REG register
  *  need_des
  */
-#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
+#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30)
 /** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
  *  need_des
  */
@@ -358,17 +620,409 @@ extern "C" {
 #define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
 #define LP_CLKRST_DAC_XTAL32K_S  29
 
+/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34)
+/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M  (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S)
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38)
+/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M  (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S)
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c)
+/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M  (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S)
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HP_CLK_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40)
+/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
+ */
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL    0x00000003U
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M  (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S)
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V  0x00000003U
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S  0
+/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  HP SoC Root Clock Enable.
+ */
+#define LP_CLKRST_HP_ROOT_CLK_EN    (BIT(2))
+#define LP_CLKRST_HP_ROOT_CLK_EN_M  (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S)
+#define LP_CLKRST_HP_ROOT_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_ROOT_CLK_EN_S  2
+/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  PARLIO TX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN    (BIT(3))
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S  3
+/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  PARLIO RX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN    (BIT(4))
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S  4
+/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  UART4 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN    (BIT(5))
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S  5
+/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  UART3 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN    (BIT(6))
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S  6
+/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  UART2 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN    (BIT(7))
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S  7
+/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  UART1 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN    (BIT(8))
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S  8
+/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  UART0 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN    (BIT(9))
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S  9
+/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1;
+ *  I2S2 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN    (BIT(10))
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S  10
+/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1;
+ *  I2S1 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN    (BIT(11))
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S  11
+/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1;
+ *  I2S0 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN    (BIT(12))
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S  12
+/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1;
+ *  EMAC RX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN    (BIT(13))
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S  13
+/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  EMAC TX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN    (BIT(14))
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S  14
+/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  EMAC TXRX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN    (BIT(15))
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S  15
+/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  XTAL 32K Clock Enable.
+ */
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN    (BIT(16))
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M  (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S)
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S  16
+/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  RC 32K Clock Enable.
+ */
+#define LP_CLKRST_HP_RC_32K_CLK_EN    (BIT(17))
+#define LP_CLKRST_HP_RC_32K_CLK_EN_M  (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S)
+#define LP_CLKRST_HP_RC_32K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_RC_32K_CLK_EN_S  17
+/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  SOSC 150K Clock Enable.
+ */
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN    (BIT(18))
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M  (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S)
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S  18
+/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  PLL 8M Clock Enable.
+ */
+#define LP_CLKRST_HP_PLL_8M_CLK_EN    (BIT(19))
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_M  (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S)
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_S  19
+/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  AUDIO PLL Clock Enable.
+ */
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN    (BIT(20))
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M  (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S)
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S  20
+/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  SDIO PLL2 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN    (BIT(21))
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S  21
+/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  SDIO PLL1 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN    (BIT(22))
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S  22
+/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  SDIO PLL0 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN    (BIT(23))
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S  23
+/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  FOSC 20M Clock Enable.
+ */
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN    (BIT(24))
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M  (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S)
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S  24
+/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  XTAL 40M Clock Enalbe.
+ */
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN    (BIT(25))
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M  (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S)
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S  25
+/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  CPLL 400M Clock Enable.
+ */
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN    (BIT(26))
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M  (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S)
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S  26
+/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  SPLL 480M Clock Enable.
+ */
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN    (BIT(27))
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M  (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S)
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S  27
+/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  MPLL 500M Clock Enable.
+ */
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN    (BIT(28))
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M  (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S)
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S  28
+
+/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44)
+/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE    (BIT(0))
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M  (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S)
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S  0
+/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN    (BIT(1))
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S  1
+/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE    (BIT(2))
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M  (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S)
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S  2
+/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN    (BIT(3))
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S)
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S  3
+/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  usb otg11 fs phy clock enable.
+ */
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN    (BIT(4))
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M  (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S)
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S  4
+/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  usb device fs phy clock enable.
+ */
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN    (BIT(5))
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M  (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S)
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S  5
+/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9;
+ *  usb 480m to 25m divide number.
+ */
+#define LP_CLKRST_USB_48M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_48M_DIV_NUM_M  (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S)
+#define LP_CLKRST_USB_48M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_48M_DIV_NUM_S  6
+/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19;
+ *  usb 500m to 25m divide number.
+ */
+#define LP_CLKRST_USB_25M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_25M_DIV_NUM_M  (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S)
+#define LP_CLKRST_USB_25M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_25M_DIV_NUM_S  14
+/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39;
+ *  usb 480m to 12m divide number.
+ */
+#define LP_CLKRST_USB_12M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_12M_DIV_NUM_M  (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S)
+#define LP_CLKRST_USB_12M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_12M_DIV_NUM_S  22
+
+/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48)
+/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0;
+ *  usb otg20 adp reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP    (BIT(0))
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M  (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S  0
+/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0;
+ *  usb otg20 phy reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY    (BIT(1))
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M  (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S  1
+/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0;
+ *  usb otg20 reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20    (BIT(2))
+#define LP_CLKRST_RST_EN_USB_OTG20_M  (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_S  2
+/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0;
+ *  usb org11 reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG11    (BIT(3))
+#define LP_CLKRST_RST_EN_USB_OTG11_M  (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S)
+#define LP_CLKRST_RST_EN_USB_OTG11_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG11_S  3
+/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0;
+ *  usb device reset en
+ */
+#define LP_CLKRST_RST_EN_USB_DEVICE    (BIT(4))
+#define LP_CLKRST_RST_EN_USB_DEVICE_M  (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S)
+#define LP_CLKRST_RST_EN_USB_DEVICE_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_DEVICE_S  4
+/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0;
+ *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
+ */
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL    0x00000003U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S)
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V  0x00000003U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S  28
+/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  usb otg20 hs phy refclk enable.
+ */
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN    (BIT(30))
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S  30
+/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  usb otg20 ulpi clock enable.
+ */
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN    (BIT(31))
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M  (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S  31
+
+/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c)
+/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0;
+ *  hp sdmmc reset en
+ */
+#define LP_CLKRST_RST_EN_SDMMC    (BIT(28))
+#define LP_CLKRST_RST_EN_SDMMC_M  (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S)
+#define LP_CLKRST_RST_EN_SDMMC_V  0x00000001U
+#define LP_CLKRST_RST_EN_SDMMC_S  28
+/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0;
+ *  hp sdmmc force norst
+ */
+#define LP_CLKRST_FORCE_NORST_SDMMC    (BIT(29))
+#define LP_CLKRST_FORCE_NORST_SDMMC_M  (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S)
+#define LP_CLKRST_FORCE_NORST_SDMMC_V  0x00000001U
+#define LP_CLKRST_FORCE_NORST_SDMMC_S  29
+/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0;
+ *  hp emac reset en
+ */
+#define LP_CLKRST_RST_EN_EMAC    (BIT(30))
+#define LP_CLKRST_RST_EN_EMAC_M  (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S)
+#define LP_CLKRST_RST_EN_EMAC_V  0x00000001U
+#define LP_CLKRST_RST_EN_EMAC_S  30
+/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0;
+ *  hp emac force norst
+ */
+#define LP_CLKRST_FORCE_NORST_EMAC    (BIT(31))
+#define LP_CLKRST_FORCE_NORST_EMAC_M  (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S)
+#define LP_CLKRST_FORCE_NORST_EMAC_V  0x00000001U
+#define LP_CLKRST_FORCE_NORST_EMAC_S  31
+
 /** LP_CLKRST_DATE_REG register
  *  need_des
  */
 #define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
-/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35676304;
- *  need_des
- */
-#define LP_CLKRST_CLKRST_DATE    0x7FFFFFFFU
-#define LP_CLKRST_CLKRST_DATE_M  (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
-#define LP_CLKRST_CLKRST_DATE_V  0x7FFFFFFFU
-#define LP_CLKRST_CLKRST_DATE_S  0
 /** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h
index 453817997f..2ade245136 100644
--- a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h
+++ b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -20,14 +20,18 @@ typedef union {
          *  need_des
          */
         uint32_t slow_clk_sel:2;
-        /** fast_clk_sel : R/W; bitpos: [2]; default: 1;
+        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
          *  need_des
          */
-        uint32_t fast_clk_sel:1;
-        /** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0;
+        uint32_t fast_clk_sel:2;
+        /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0;
          *  need_des
          */
-        uint32_t lp_peri_div_num:8;
+        uint32_t lp_peri_div_num:6;
+        /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_sel_ref_pll8m:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
@@ -38,51 +42,48 @@ typedef union {
  */
 typedef union {
     struct {
-        /** aon_slow_oen : R/W; bitpos: [0]; default: 1;
+        /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0;
          *  need_des
          */
-        uint32_t aon_slow_oen:1;
-        /** aon_fast_oen : R/W; bitpos: [1]; default: 1;
+        uint32_t clk_core_efuse_oen:1;
+        /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0;
          *  need_des
          */
-        uint32_t aon_fast_oen:1;
-        /** sosc_oen : R/W; bitpos: [2]; default: 1;
+        uint32_t clk_lp_bus_oen:1;
+        /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0;
          *  need_des
          */
-        uint32_t sosc_oen:1;
-        /** fosc_oen : R/W; bitpos: [3]; default: 1;
+        uint32_t clk_aon_slow_oen:1;
+        /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0;
          *  need_des
          */
-        uint32_t fosc_oen:1;
-        /** osc32k_oen : R/W; bitpos: [4]; default: 1;
+        uint32_t clk_aon_fast_oen:1;
+        /** clk_slow_oen : R/W; bitpos: [4]; default: 0;
          *  need_des
          */
-        uint32_t osc32k_oen:1;
-        /** xtal32k_oen : R/W; bitpos: [5]; default: 1;
+        uint32_t clk_slow_oen:1;
+        /** clk_fast_oen : R/W; bitpos: [5]; default: 0;
          *  need_des
          */
-        uint32_t xtal32k_oen:1;
-        /** core_efuse_oen : R/W; bitpos: [6]; default: 1;
+        uint32_t clk_fast_oen:1;
+        /** clk_fosc_oen : R/W; bitpos: [6]; default: 0;
          *  need_des
          */
-        uint32_t core_efuse_oen:1;
-        /** slow_oen : R/W; bitpos: [7]; default: 1;
+        uint32_t clk_fosc_oen:1;
+        /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0;
          *  need_des
          */
-        uint32_t slow_oen:1;
-        /** fast_oen : R/W; bitpos: [8]; default: 1;
+        uint32_t clk_rc32k_oen:1;
+        /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0;
          *  need_des
          */
-        uint32_t fast_oen:1;
-        /** rng_oen : R/W; bitpos: [9]; default: 1;
-         *  need_des
+        uint32_t clk_sxtal_oen:1;
+        /** clk_sosc_oen : R/W; bitpos: [9]; default: 0;
+         *  1'b1: probe sosc clk on
+         *  1'b0: probe sosc clk off
          */
-        uint32_t rng_oen:1;
-        /** lpbus_oen : R/W; bitpos: [10]; default: 1;
-         *  need_des
-         */
-        uint32_t lpbus_oen:1;
-        uint32_t reserved_11:21;
+        uint32_t clk_sosc_oen:1;
+        uint32_t reserved_10:22;
     };
     uint32_t val;
 } lp_clkrst_lp_clk_po_en_reg_t;
@@ -92,11 +93,31 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** fast_ori_gate : R/W; bitpos: [31]; default: 0;
+        uint32_t reserved_0:26;
+        /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0;
          *  need_des
          */
-        uint32_t fast_ori_gate:1;
+        uint32_t lp_rtc_xtal_force_on:1;
+        /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_ram:1;
+        /** etm_event_tick_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t etm_event_tick_en:1;
+        /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t pll8m_clk_force_on:1;
+        /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t xtal_clk_force_on:1;
+        /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t fosc_clk_force_on:1;
     };
     uint32_t val;
 } lp_clkrst_lp_clk_en_reg_t;
@@ -106,23 +127,39 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:28;
-        /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
+        uint32_t reserved_0:24;
+        /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0;
          *  need_des
          */
-        uint32_t aon_efuse_core_reset_en:1;
-        /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
+        uint32_t rst_en_lp_huk:1;
+        /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0;
          *  need_des
          */
-        uint32_t lp_timer_reset_en:1;
-        /** wdt_reset_en : R/W; bitpos: [30]; default: 0;
+        uint32_t rst_en_lp_anaperi:1;
+        /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0;
          *  need_des
          */
-        uint32_t wdt_reset_en:1;
-        /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
+        uint32_t rst_en_lp_wdt:1;
+        /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0;
          *  need_des
          */
-        uint32_t ana_peri_reset_en:1;
+        uint32_t rst_en_lp_timer:1;
+        /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rtc:1;
+        /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_mailbox:1;
+        /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_aonefusereg:1;
+        /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_ram:1;
     };
     uint32_t val;
 } lp_clkrst_lp_rst_en_reg_t;
@@ -132,56 +169,199 @@ typedef union {
  */
 typedef union {
     struct {
-        /** reset_cause : RO; bitpos: [4:0]; default: 0;
+        /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0;
+         *  6'h1: POR reset
+         *  6'h9: PMU LP PERI power down reset
+         *  6'ha: PMU LP CPU reset
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: software reset
+         */
+        uint32_t lpcore_reset_cause:6;
+        /** lpcore_reset_flag : RO; bitpos: [6]; default: 0;
          *  need_des
          */
-        uint32_t reset_cause:5;
-        /** core0_reset_flag : RO; bitpos: [5]; default: 1;
+        uint32_t lpcore_reset_flag:1;
+        /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore0_reset_cause:6;
+        /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0;
          *  need_des
          */
-        uint32_t core0_reset_flag:1;
-        uint32_t reserved_6:23;
-        /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
+        uint32_t hpcore0_reset_flag:1;
+        /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore1_reset_cause:6;
+        /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0;
          *  need_des
          */
-        uint32_t core0_reset_cause_clr:1;
-        /** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
+        uint32_t hpcore1_reset_flag:1;
+        uint32_t reserved_21:4;
+        /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1;
+         *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
+         *  pmu_lp_cpu_reset reset_cause
+         */
+        uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1;
+        /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0;
          *  need_des
          */
-        uint32_t core0_reset_flag_set:1;
-        /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
+        uint32_t lpcore_reset_cause_clr:1;
+        /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0;
          *  need_des
          */
-        uint32_t core0_reset_flag_clr:1;
+        uint32_t lpcore_reset_flag_clr:1;
+        /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_cause_clr:1;
+        /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_flag_clr:1;
+        /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_cause_clr:1;
+        /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_flag_clr:1;
     };
     uint32_t val;
 } lp_clkrst_reset_cause_reg_t;
 
-/** Type of cpu_reset register
+/** Type of hpcpu_reset_ctrl0 register
  *  need_des
  */
 typedef union {
     struct {
-        uint32_t reserved_0:22;
-        /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
+        /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
+         *  reset feature
+         */
+        uint32_t hpcore0_lockup_reset_en:1;
+        /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1;
          *  need_des
          */
-        uint32_t rtc_wdt_cpu_reset_length:3;
-        /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
+        uint32_t lp_wdt_hpcore0_reset_length:3;
+        /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
+         *  hpcore0 feature
+         */
+        uint32_t lp_wdt_hpcore0_reset_en:1;
+        /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0;
          *  need_des
          */
-        uint32_t rtc_wdt_cpu_reset_en:1;
-        /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
+        uint32_t hpcore0_stall_wait:7;
+        /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0;
          *  need_des
          */
-        uint32_t cpu_stall_wait:5;
-        /** cpu_stall_en : R/W; bitpos: [31]; default: 0;
+        uint32_t hpcore0_stall_en:1;
+        /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0;
          *  need_des
          */
-        uint32_t cpu_stall_en:1;
+        uint32_t hpcore0_sw_reset:1;
+        /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_ocd_halt_on_reset:1;
+        /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore0_stat_vector_sel:1;
+        /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0;
+         *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
+         *  reset feature
+         */
+        uint32_t hpcore1_lockup_reset_en:1;
+        /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_wdt_hpcore1_reset_length:3;
+        /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
+         *  hpcore1 feature
+         */
+        uint32_t lp_wdt_hpcore1_reset_en:1;
+        /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_wait:7;
+        /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_en:1;
+        /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_sw_reset:1;
+        /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_ocd_halt_on_reset:1;
+        /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore1_stat_vector_sel:1;
     };
     uint32_t val;
-} lp_clkrst_cpu_reset_reg_t;
+} lp_clkrst_hpcpu_reset_ctrl0_reg_t;
+
+/** Type of hpcpu_reset_ctrl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
+         *  HP core0 software stall when set to 8'h86
+         */
+        uint32_t hpcore0_sw_stall_code:8;
+        /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
+         *  HP core1 software stall when set to 8'h86
+         */
+        uint32_t hpcore1_sw_stall_code:8;
+    };
+    uint32_t val;
+} lp_clkrst_hpcpu_reset_ctrl1_reg_t;
 
 /** Type of fosc_cntl register
  *  need_des
@@ -189,7 +369,7 @@ typedef union {
 typedef union {
     struct {
         uint32_t reserved_0:22;
-        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
+        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400;
          *  need_des
          */
         uint32_t fosc_dfreq:10;
@@ -202,15 +382,28 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:22;
-        /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
+        /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650;
          *  need_des
          */
-        uint32_t rc32k_dfreq:10;
+        uint32_t rc32k_dfreq:32;
     };
     uint32_t val;
 } lp_clkrst_rc32k_cntl_reg_t;
 
+/** Type of sosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  need_des
+         */
+        uint32_t sosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_clkrst_sosc_cntl_reg_t;
+
 /** Type of clk_to_hp register
  *  need_des
  */
@@ -218,19 +411,19 @@ typedef union {
     struct {
         uint32_t reserved_0:28;
         /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
-         *  need_des
+         *  reserved
          */
         uint32_t icg_hp_xtal32k:1;
         /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
-         *  need_des
+         *  reserved
          */
         uint32_t icg_hp_sosc:1;
         /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
-         *  need_des
+         *  reserved
          */
         uint32_t icg_hp_osc32k:1;
         /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
-         *  need_des
+         *  reserved
          */
         uint32_t icg_hp_fosc:1;
     };
@@ -244,31 +437,13 @@ typedef union {
     struct {
         uint32_t reserved_0:31;
         /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
-         *  need_des
+         *  reserved
          */
         uint32_t lpmem_clk_force_on:1;
     };
     uint32_t val;
 } lp_clkrst_lpmem_force_reg_t;
 
-/** Type of lpperi register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_i2c_clk_sel:1;
-        /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_uart_clk_sel:1;
-    };
-    uint32_t val;
-} lp_clkrst_lpperi_reg_t;
-
 /** Type of xtal32k register
  *  need_des
  */
@@ -295,15 +470,287 @@ typedef union {
     uint32_t val;
 } lp_clkrst_xtal32k_reg_t;
 
+/** Type of mux_hpsys_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t mux_hpsys_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_clkrst_mux_hpsys_reset_bypass_reg_t;
+
+/** Type of hpsys_0_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_0_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_clkrst_hpsys_0_reset_bypass_reg_t;
+
+/** Type of hpsys_apm_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_apm_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_clkrst_hpsys_apm_reset_bypass_reg_t;
+
+/** Type of hp_clk_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
+         */
+        uint32_t hp_root_clk_src_sel:2;
+        /** hp_root_clk_en : R/W; bitpos: [2]; default: 1;
+         *  HP SoC Root Clock Enable.
+         */
+        uint32_t hp_root_clk_en:1;
+        /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1;
+         *  PARLIO TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_tx_clk_en:1;
+        /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1;
+         *  PARLIO RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_rx_clk_en:1;
+        /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1;
+         *  UART4 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart4_slp_clk_en:1;
+        /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1;
+         *  UART3 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart3_slp_clk_en:1;
+        /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1;
+         *  UART2 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart2_slp_clk_en:1;
+        /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1;
+         *  UART1 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart1_slp_clk_en:1;
+        /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1;
+         *  UART0 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart0_slp_clk_en:1;
+        /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1;
+         *  I2S2 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s2_mclk_en:1;
+        /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1;
+         *  I2S1 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s1_mclk_en:1;
+        /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1;
+         *  I2S0 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s0_mclk_en:1;
+        /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1;
+         *  EMAC RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_tx_clk_en:1;
+        /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1;
+         *  EMAC TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_rx_clk_en:1;
+        /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1;
+         *  EMAC TXRX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_txrx_clk_en:1;
+        /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1;
+         *  XTAL 32K Clock Enable.
+         */
+        uint32_t hp_xtal_32k_clk_en:1;
+        /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1;
+         *  RC 32K Clock Enable.
+         */
+        uint32_t hp_rc_32k_clk_en:1;
+        /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1;
+         *  SOSC 150K Clock Enable.
+         */
+        uint32_t hp_sosc_150k_clk_en:1;
+        /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1;
+         *  PLL 8M Clock Enable.
+         */
+        uint32_t hp_pll_8m_clk_en:1;
+        /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1;
+         *  AUDIO PLL Clock Enable.
+         */
+        uint32_t hp_audio_pll_clk_en:1;
+        /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1;
+         *  SDIO PLL2 Clock Enable.
+         */
+        uint32_t hp_sdio_pll2_clk_en:1;
+        /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1;
+         *  SDIO PLL1 Clock Enable.
+         */
+        uint32_t hp_sdio_pll1_clk_en:1;
+        /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1;
+         *  SDIO PLL0 Clock Enable.
+         */
+        uint32_t hp_sdio_pll0_clk_en:1;
+        /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1;
+         *  FOSC 20M Clock Enable.
+         */
+        uint32_t hp_fosc_20m_clk_en:1;
+        /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
+         *  XTAL 40M Clock Enalbe.
+         */
+        uint32_t hp_xtal_40m_clk_en:1;
+        /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;
+         *  CPLL 400M Clock Enable.
+         */
+        uint32_t hp_cpll_400m_clk_en:1;
+        /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1;
+         *  SPLL 480M Clock Enable.
+         */
+        uint32_t hp_spll_480m_clk_en:1;
+        /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1;
+         *  MPLL 500M Clock Enable.
+         */
+        uint32_t hp_mpll_500m_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_clkrst_hp_clk_ctrl_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl0 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg20_sleep_mode:1;
+        /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg20_bk_sys_clk_en:1;
+        /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg11_sleep_mode:1;
+        /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg11_bk_sys_clk_en:1;
+        /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  usb otg11 fs phy clock enable.
+         */
+        uint32_t usb_otg11_48m_clk_en:1;
+        /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1;
+         *  usb device fs phy clock enable.
+         */
+        uint32_t usb_device_48m_clk_en:1;
+        /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9;
+         *  usb 480m to 25m divide number.
+         */
+        uint32_t usb_48m_div_num:8;
+        /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19;
+         *  usb 500m to 25m divide number.
+         */
+        uint32_t usb_25m_div_num:8;
+        /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39;
+         *  usb 480m to 12m divide number.
+         */
+        uint32_t usb_12m_div_num:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_clkrst_hp_usb_clkrst_ctrl0_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl1 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0;
+         *  usb otg20 adp reset en
+         */
+        uint32_t rst_en_usb_otg20_adp:1;
+        /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0;
+         *  usb otg20 phy reset en
+         */
+        uint32_t rst_en_usb_otg20_phy:1;
+        /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0;
+         *  usb otg20 reset en
+         */
+        uint32_t rst_en_usb_otg20:1;
+        /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0;
+         *  usb org11 reset en
+         */
+        uint32_t rst_en_usb_otg11:1;
+        /** rst_en_usb_device : R/W; bitpos: [4]; default: 0;
+         *  usb device reset en
+         */
+        uint32_t rst_en_usb_device:1;
+        uint32_t reserved_5:23;
+        /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0;
+         *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
+         */
+        uint32_t usb_otg20_phyref_clk_src_sel:2;
+        /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1;
+         *  usb otg20 hs phy refclk enable.
+         */
+        uint32_t usb_otg20_phyref_clk_en:1;
+        /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1;
+         *  usb otg20 ulpi clock enable.
+         */
+        uint32_t usb_otg20_ulpi_clk_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_hp_usb_clkrst_ctrl1_reg_t;
+
+/** Type of hp_sdmmc_emac_rst_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0;
+         *  hp sdmmc reset en
+         */
+        uint32_t rst_en_sdmmc:1;
+        /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0;
+         *  hp sdmmc force norst
+         */
+        uint32_t force_norst_sdmmc:1;
+        /** rst_en_emac : R/W; bitpos: [30]; default: 0;
+         *  hp emac reset en
+         */
+        uint32_t rst_en_emac:1;
+        /** force_norst_emac : R/W; bitpos: [31]; default: 0;
+         *  hp emac force norst
+         */
+        uint32_t force_norst_emac:1;
+    };
+    uint32_t val;
+} lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t;
+
 /** Type of date register
  *  need_des
  */
 typedef union {
     struct {
-        /** clkrst_date : R/W; bitpos: [30:0]; default: 35676304;
-         *  need_des
-         */
-        uint32_t clkrst_date:31;
+        uint32_t reserved_0:31;
         /** clk_en : R/W; bitpos: [31]; default: 0;
          *  need_des
          */
@@ -313,24 +760,31 @@ typedef union {
 } lp_clkrst_date_reg_t;
 
 
-typedef struct lp_clkrst_dev_t {
+typedef struct {
     volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
     volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
     volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
     volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
     volatile lp_clkrst_reset_cause_reg_t reset_cause;
-    volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
+    volatile lp_clkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0;
+    volatile lp_clkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1;
     volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
     volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
+    volatile lp_clkrst_sosc_cntl_reg_t sosc_cntl;
     volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
     volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
-    volatile lp_clkrst_lpperi_reg_t lpperi;
     volatile lp_clkrst_xtal32k_reg_t xtal32k;
-    uint32_t reserved_030[243];
+    volatile lp_clkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass;
+    volatile lp_clkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass;
+    volatile lp_clkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass;
+    volatile lp_clkrst_hp_clk_ctrl_reg_t hp_clk_ctrl;
+    volatile lp_clkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0;
+    volatile lp_clkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1;
+    volatile lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl;
+    uint32_t reserved_050[235];
     volatile lp_clkrst_date_reg_t date;
 } lp_clkrst_dev_t;
 
-extern lp_clkrst_dev_t LP_CLKRST;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
diff --git a/components/soc/esp32p4/include/soc/lp_gpio_struct.h b/components/soc/esp32p4/include/soc/lp_gpio_struct.h
index 78bcfcaff9..507cf47a8f 100644
--- a/components/soc/esp32p4/include/soc/lp_gpio_struct.h
+++ b/components/soc/esp32p4/include/soc/lp_gpio_struct.h
@@ -1449,7 +1449,7 @@ typedef union {
 } lp_gpio_func15_out_sel_cfg_reg_t;
 
 
-typedef struct {
+typedef struct lp_gpio_dev_t {
     volatile lp_gpio_clk_en_reg_t clk_en;
     volatile lp_gpio_ver_date_reg_t ver_date;
     volatile lp_gpio_out_reg_t out;
@@ -1512,6 +1512,8 @@ typedef struct {
     volatile lp_gpio_func15_out_sel_cfg_reg_t func15_out_sel_cfg;
 } lp_gpio_dev_t;
 
+extern lp_gpio_dev_t LP_GPIO;
+
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_gpio_dev_t) == 0x134, "Invalid size of lp_gpio_dev_t structure");
diff --git a/components/soc/esp32p4/include/soc/lp_io_reg.h b/components/soc/esp32p4/include/soc/lp_io_reg.h
deleted file mode 100644
index 64b5f6c425..0000000000
--- a/components/soc/esp32p4/include/soc/lp_io_reg.h
+++ /dev/null
@@ -1,1263 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_IO_OUT_DATA_REG register
- *  need des
- */
-#define LP_IO_OUT_DATA_REG (DR_REG_LP_IO_BASE + 0x0)
-/** LP_IO_LP_GPIO_OUT_DATA : R/W/WTC; bitpos: [7:0]; default: 0;
- *  set lp gpio output data
- */
-#define LP_IO_LP_GPIO_OUT_DATA    0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_M  (LP_IO_LP_GPIO_OUT_DATA_V << LP_IO_LP_GPIO_OUT_DATA_S)
-#define LP_IO_LP_GPIO_OUT_DATA_V  0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_S  0
-
-/** LP_IO_OUT_DATA_W1TS_REG register
- *  need des
- */
-#define LP_IO_OUT_DATA_W1TS_REG (DR_REG_LP_IO_BASE + 0x4)
-/** LP_IO_LP_GPIO_OUT_DATA_W1TS : WT; bitpos: [7:0]; default: 0;
- *  set one time output data
- */
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS    0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS_M  (LP_IO_LP_GPIO_OUT_DATA_W1TS_V << LP_IO_LP_GPIO_OUT_DATA_W1TS_S)
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS_V  0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS_S  0
-
-/** LP_IO_OUT_DATA_W1TC_REG register
- *  need des
- */
-#define LP_IO_OUT_DATA_W1TC_REG (DR_REG_LP_IO_BASE + 0x8)
-/** LP_IO_LP_GPIO_OUT_DATA_W1TC : WT; bitpos: [7:0]; default: 0;
- *  clear one time output data
- */
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC    0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC_M  (LP_IO_LP_GPIO_OUT_DATA_W1TC_V << LP_IO_LP_GPIO_OUT_DATA_W1TC_S)
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC_V  0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC_S  0
-
-/** LP_IO_OUT_ENABLE_REG register
- *  need des
- */
-#define LP_IO_OUT_ENABLE_REG (DR_REG_LP_IO_BASE + 0xc)
-/** LP_IO_LP_GPIO_ENABLE : R/W/WTC; bitpos: [7:0]; default: 0;
- *  set lp gpio output data
- */
-#define LP_IO_LP_GPIO_ENABLE    0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_M  (LP_IO_LP_GPIO_ENABLE_V << LP_IO_LP_GPIO_ENABLE_S)
-#define LP_IO_LP_GPIO_ENABLE_V  0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_S  0
-
-/** LP_IO_OUT_ENABLE_W1TS_REG register
- *  need des
- */
-#define LP_IO_OUT_ENABLE_W1TS_REG (DR_REG_LP_IO_BASE + 0x10)
-/** LP_IO_LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0;
- *  set one time output data
- */
-#define LP_IO_LP_GPIO_ENABLE_W1TS    0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TS_M  (LP_IO_LP_GPIO_ENABLE_W1TS_V << LP_IO_LP_GPIO_ENABLE_W1TS_S)
-#define LP_IO_LP_GPIO_ENABLE_W1TS_V  0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TS_S  0
-
-/** LP_IO_OUT_ENABLE_W1TC_REG register
- *  need des
- */
-#define LP_IO_OUT_ENABLE_W1TC_REG (DR_REG_LP_IO_BASE + 0x14)
-/** LP_IO_LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0;
- *  clear one time output data
- */
-#define LP_IO_LP_GPIO_ENABLE_W1TC    0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TC_M  (LP_IO_LP_GPIO_ENABLE_W1TC_V << LP_IO_LP_GPIO_ENABLE_W1TC_S)
-#define LP_IO_LP_GPIO_ENABLE_W1TC_V  0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TC_S  0
-
-/** LP_IO_STATUS_REG register
- *  need des
- */
-#define LP_IO_STATUS_REG (DR_REG_LP_IO_BASE + 0x18)
-/** LP_IO_LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0;
- *  set lp gpio output data
- */
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT    0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_M  (LP_IO_LP_GPIO_STATUS_INTERRUPT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_S)
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_V  0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_S  0
-
-/** LP_IO_STATUS_W1TS_REG register
- *  need des
- */
-#define LP_IO_STATUS_W1TS_REG (DR_REG_LP_IO_BASE + 0x1c)
-/** LP_IO_LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0;
- *  set one time output data
- */
-#define LP_IO_LP_GPIO_STATUS_W1TS    0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TS_M  (LP_IO_LP_GPIO_STATUS_W1TS_V << LP_IO_LP_GPIO_STATUS_W1TS_S)
-#define LP_IO_LP_GPIO_STATUS_W1TS_V  0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TS_S  0
-
-/** LP_IO_STATUS_W1TC_REG register
- *  need des
- */
-#define LP_IO_STATUS_W1TC_REG (DR_REG_LP_IO_BASE + 0x20)
-/** LP_IO_LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0;
- *  clear one time output data
- */
-#define LP_IO_LP_GPIO_STATUS_W1TC    0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TC_M  (LP_IO_LP_GPIO_STATUS_W1TC_V << LP_IO_LP_GPIO_STATUS_W1TC_S)
-#define LP_IO_LP_GPIO_STATUS_W1TC_V  0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TC_S  0
-
-/** LP_IO_IN_REG register
- *  need des
- */
-#define LP_IO_IN_REG (DR_REG_LP_IO_BASE + 0x24)
-/** LP_IO_LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO_IN_DATA_NEXT    0x000000FFU
-#define LP_IO_LP_GPIO_IN_DATA_NEXT_M  (LP_IO_LP_GPIO_IN_DATA_NEXT_V << LP_IO_LP_GPIO_IN_DATA_NEXT_S)
-#define LP_IO_LP_GPIO_IN_DATA_NEXT_V  0x000000FFU
-#define LP_IO_LP_GPIO_IN_DATA_NEXT_S  0
-
-/** LP_IO_PIN0_REG register
- *  need des
- */
-#define LP_IO_PIN0_REG (DR_REG_LP_IO_BASE + 0x28)
-/** LP_IO_LP_GPIO0_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO0_SYNC_BYPASS_M  (LP_IO_LP_GPIO0_SYNC_BYPASS_V << LP_IO_LP_GPIO0_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO0_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO0_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO0_PAD_DRIVER_M  (LP_IO_LP_GPIO0_PAD_DRIVER_V << LP_IO_LP_GPIO0_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO0_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO0_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO0_INT_TYPE_M  (LP_IO_LP_GPIO0_INT_TYPE_V << LP_IO_LP_GPIO0_INT_TYPE_S)
-#define LP_IO_LP_GPIO0_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO0_INT_TYPE_S  7
-/** LP_IO_LP_GPIO0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO0_WAKEUP_ENABLE_V << LP_IO_LP_GPIO0_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO0_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO0_FILTER_EN_M  (LP_IO_LP_GPIO0_FILTER_EN_V << LP_IO_LP_GPIO0_FILTER_EN_S)
-#define LP_IO_LP_GPIO0_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO0_FILTER_EN_S  11
-
-/** LP_IO_PIN1_REG register
- *  need des
- */
-#define LP_IO_PIN1_REG (DR_REG_LP_IO_BASE + 0x2c)
-/** LP_IO_LP_GPIO1_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO1_SYNC_BYPASS_M  (LP_IO_LP_GPIO1_SYNC_BYPASS_V << LP_IO_LP_GPIO1_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO1_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO1_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO1_PAD_DRIVER_M  (LP_IO_LP_GPIO1_PAD_DRIVER_V << LP_IO_LP_GPIO1_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO1_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO1_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO1_INT_TYPE_M  (LP_IO_LP_GPIO1_INT_TYPE_V << LP_IO_LP_GPIO1_INT_TYPE_S)
-#define LP_IO_LP_GPIO1_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO1_INT_TYPE_S  7
-/** LP_IO_LP_GPIO1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO1_WAKEUP_ENABLE_V << LP_IO_LP_GPIO1_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO1_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO1_FILTER_EN_M  (LP_IO_LP_GPIO1_FILTER_EN_V << LP_IO_LP_GPIO1_FILTER_EN_S)
-#define LP_IO_LP_GPIO1_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO1_FILTER_EN_S  11
-
-/** LP_IO_PIN2_REG register
- *  need des
- */
-#define LP_IO_PIN2_REG (DR_REG_LP_IO_BASE + 0x30)
-/** LP_IO_LP_GPIO2_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO2_SYNC_BYPASS_M  (LP_IO_LP_GPIO2_SYNC_BYPASS_V << LP_IO_LP_GPIO2_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO2_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO2_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO2_PAD_DRIVER_M  (LP_IO_LP_GPIO2_PAD_DRIVER_V << LP_IO_LP_GPIO2_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO2_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO2_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO2_INT_TYPE_M  (LP_IO_LP_GPIO2_INT_TYPE_V << LP_IO_LP_GPIO2_INT_TYPE_S)
-#define LP_IO_LP_GPIO2_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO2_INT_TYPE_S  7
-/** LP_IO_LP_GPIO2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO2_WAKEUP_ENABLE_V << LP_IO_LP_GPIO2_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO2_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO2_FILTER_EN_M  (LP_IO_LP_GPIO2_FILTER_EN_V << LP_IO_LP_GPIO2_FILTER_EN_S)
-#define LP_IO_LP_GPIO2_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO2_FILTER_EN_S  11
-
-/** LP_IO_PIN3_REG register
- *  need des
- */
-#define LP_IO_PIN3_REG (DR_REG_LP_IO_BASE + 0x34)
-/** LP_IO_LP_GPIO3_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO3_SYNC_BYPASS_M  (LP_IO_LP_GPIO3_SYNC_BYPASS_V << LP_IO_LP_GPIO3_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO3_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO3_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO3_PAD_DRIVER_M  (LP_IO_LP_GPIO3_PAD_DRIVER_V << LP_IO_LP_GPIO3_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO3_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO3_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO3_INT_TYPE_M  (LP_IO_LP_GPIO3_INT_TYPE_V << LP_IO_LP_GPIO3_INT_TYPE_S)
-#define LP_IO_LP_GPIO3_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO3_INT_TYPE_S  7
-/** LP_IO_LP_GPIO3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO3_WAKEUP_ENABLE_V << LP_IO_LP_GPIO3_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO3_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO3_FILTER_EN_M  (LP_IO_LP_GPIO3_FILTER_EN_V << LP_IO_LP_GPIO3_FILTER_EN_S)
-#define LP_IO_LP_GPIO3_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO3_FILTER_EN_S  11
-
-/** LP_IO_PIN4_REG register
- *  need des
- */
-#define LP_IO_PIN4_REG (DR_REG_LP_IO_BASE + 0x38)
-/** LP_IO_LP_GPIO4_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO4_SYNC_BYPASS_M  (LP_IO_LP_GPIO4_SYNC_BYPASS_V << LP_IO_LP_GPIO4_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO4_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO4_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO4_PAD_DRIVER_M  (LP_IO_LP_GPIO4_PAD_DRIVER_V << LP_IO_LP_GPIO4_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO4_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO4_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO4_INT_TYPE_M  (LP_IO_LP_GPIO4_INT_TYPE_V << LP_IO_LP_GPIO4_INT_TYPE_S)
-#define LP_IO_LP_GPIO4_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO4_INT_TYPE_S  7
-/** LP_IO_LP_GPIO4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO4_WAKEUP_ENABLE_V << LP_IO_LP_GPIO4_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO4_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO4_FILTER_EN_M  (LP_IO_LP_GPIO4_FILTER_EN_V << LP_IO_LP_GPIO4_FILTER_EN_S)
-#define LP_IO_LP_GPIO4_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO4_FILTER_EN_S  11
-
-/** LP_IO_PIN5_REG register
- *  need des
- */
-#define LP_IO_PIN5_REG (DR_REG_LP_IO_BASE + 0x3c)
-/** LP_IO_LP_GPIO5_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO5_SYNC_BYPASS_M  (LP_IO_LP_GPIO5_SYNC_BYPASS_V << LP_IO_LP_GPIO5_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO5_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO5_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO5_PAD_DRIVER_M  (LP_IO_LP_GPIO5_PAD_DRIVER_V << LP_IO_LP_GPIO5_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO5_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO5_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO5_INT_TYPE_M  (LP_IO_LP_GPIO5_INT_TYPE_V << LP_IO_LP_GPIO5_INT_TYPE_S)
-#define LP_IO_LP_GPIO5_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO5_INT_TYPE_S  7
-/** LP_IO_LP_GPIO5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO5_WAKEUP_ENABLE_V << LP_IO_LP_GPIO5_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO5_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO5_FILTER_EN_M  (LP_IO_LP_GPIO5_FILTER_EN_V << LP_IO_LP_GPIO5_FILTER_EN_S)
-#define LP_IO_LP_GPIO5_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO5_FILTER_EN_S  11
-
-/** LP_IO_PIN6_REG register
- *  need des
- */
-#define LP_IO_PIN6_REG (DR_REG_LP_IO_BASE + 0x40)
-/** LP_IO_LP_GPIO6_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO6_SYNC_BYPASS_M  (LP_IO_LP_GPIO6_SYNC_BYPASS_V << LP_IO_LP_GPIO6_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO6_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO6_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO6_PAD_DRIVER_M  (LP_IO_LP_GPIO6_PAD_DRIVER_V << LP_IO_LP_GPIO6_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO6_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO6_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO6_INT_TYPE_M  (LP_IO_LP_GPIO6_INT_TYPE_V << LP_IO_LP_GPIO6_INT_TYPE_S)
-#define LP_IO_LP_GPIO6_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO6_INT_TYPE_S  7
-/** LP_IO_LP_GPIO6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO6_WAKEUP_ENABLE_V << LP_IO_LP_GPIO6_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO6_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO6_FILTER_EN_M  (LP_IO_LP_GPIO6_FILTER_EN_V << LP_IO_LP_GPIO6_FILTER_EN_S)
-#define LP_IO_LP_GPIO6_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO6_FILTER_EN_S  11
-
-/** LP_IO_PIN7_REG register
- *  need des
- */
-#define LP_IO_PIN7_REG (DR_REG_LP_IO_BASE + 0x44)
-/** LP_IO_LP_GPIO7_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO7_SYNC_BYPASS_M  (LP_IO_LP_GPIO7_SYNC_BYPASS_V << LP_IO_LP_GPIO7_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO7_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO7_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO7_PAD_DRIVER_M  (LP_IO_LP_GPIO7_PAD_DRIVER_V << LP_IO_LP_GPIO7_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO7_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO7_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO7_INT_TYPE_M  (LP_IO_LP_GPIO7_INT_TYPE_V << LP_IO_LP_GPIO7_INT_TYPE_S)
-#define LP_IO_LP_GPIO7_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO7_INT_TYPE_S  7
-/** LP_IO_LP_GPIO7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO7_WAKEUP_ENABLE_V << LP_IO_LP_GPIO7_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO7_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO7_FILTER_EN_M  (LP_IO_LP_GPIO7_FILTER_EN_V << LP_IO_LP_GPIO7_FILTER_EN_S)
-#define LP_IO_LP_GPIO7_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO7_FILTER_EN_S  11
-
-/** LP_IO_GPIO0_REG register
- *  need des
- */
-#define LP_IO_GPIO0_REG (DR_REG_LP_IO_BASE + 0x48)
-/** LP_IO_LP_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO0_MCU_OE_M  (LP_IO_LP_GPIO0_MCU_OE_V << LP_IO_LP_GPIO0_MCU_OE_S)
-#define LP_IO_LP_GPIO0_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_OE_S  0
-/** LP_IO_LP_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO0_SLP_SEL_M  (LP_IO_LP_GPIO0_SLP_SEL_V << LP_IO_LP_GPIO0_SLP_SEL_S)
-#define LP_IO_LP_GPIO0_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO0_SLP_SEL_S  1
-/** LP_IO_LP_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO0_MCU_WPD_M  (LP_IO_LP_GPIO0_MCU_WPD_V << LP_IO_LP_GPIO0_MCU_WPD_S)
-#define LP_IO_LP_GPIO0_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_WPD_S  2
-/** LP_IO_LP_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO0_MCU_WPU_M  (LP_IO_LP_GPIO0_MCU_WPU_V << LP_IO_LP_GPIO0_MCU_WPU_S)
-#define LP_IO_LP_GPIO0_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_WPU_S  3
-/** LP_IO_LP_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO0_MCU_IE_M  (LP_IO_LP_GPIO0_MCU_IE_V << LP_IO_LP_GPIO0_MCU_IE_S)
-#define LP_IO_LP_GPIO0_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_IE_S  4
-/** LP_IO_LP_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO0_MCU_DRV_M  (LP_IO_LP_GPIO0_MCU_DRV_V << LP_IO_LP_GPIO0_MCU_DRV_S)
-#define LP_IO_LP_GPIO0_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO0_MCU_DRV_S  5
-/** LP_IO_LP_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO0_FUN_WPD_M  (LP_IO_LP_GPIO0_FUN_WPD_V << LP_IO_LP_GPIO0_FUN_WPD_S)
-#define LP_IO_LP_GPIO0_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO0_FUN_WPD_S  7
-/** LP_IO_LP_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO0_FUN_WPU_M  (LP_IO_LP_GPIO0_FUN_WPU_V << LP_IO_LP_GPIO0_FUN_WPU_S)
-#define LP_IO_LP_GPIO0_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO0_FUN_WPU_S  8
-/** LP_IO_LP_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO0_FUN_IE_M  (LP_IO_LP_GPIO0_FUN_IE_V << LP_IO_LP_GPIO0_FUN_IE_S)
-#define LP_IO_LP_GPIO0_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO0_FUN_IE_S  9
-/** LP_IO_LP_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO0_FUN_DRV_M  (LP_IO_LP_GPIO0_FUN_DRV_V << LP_IO_LP_GPIO0_FUN_DRV_S)
-#define LP_IO_LP_GPIO0_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO0_FUN_DRV_S  10
-/** LP_IO_LP_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO0_MCU_SEL_M  (LP_IO_LP_GPIO0_MCU_SEL_V << LP_IO_LP_GPIO0_MCU_SEL_S)
-#define LP_IO_LP_GPIO0_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO0_MCU_SEL_S  12
-
-/** LP_IO_GPIO1_REG register
- *  need des
- */
-#define LP_IO_GPIO1_REG (DR_REG_LP_IO_BASE + 0x4c)
-/** LP_IO_LP_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO1_MCU_OE_M  (LP_IO_LP_GPIO1_MCU_OE_V << LP_IO_LP_GPIO1_MCU_OE_S)
-#define LP_IO_LP_GPIO1_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_OE_S  0
-/** LP_IO_LP_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO1_SLP_SEL_M  (LP_IO_LP_GPIO1_SLP_SEL_V << LP_IO_LP_GPIO1_SLP_SEL_S)
-#define LP_IO_LP_GPIO1_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO1_SLP_SEL_S  1
-/** LP_IO_LP_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO1_MCU_WPD_M  (LP_IO_LP_GPIO1_MCU_WPD_V << LP_IO_LP_GPIO1_MCU_WPD_S)
-#define LP_IO_LP_GPIO1_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_WPD_S  2
-/** LP_IO_LP_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO1_MCU_WPU_M  (LP_IO_LP_GPIO1_MCU_WPU_V << LP_IO_LP_GPIO1_MCU_WPU_S)
-#define LP_IO_LP_GPIO1_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_WPU_S  3
-/** LP_IO_LP_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO1_MCU_IE_M  (LP_IO_LP_GPIO1_MCU_IE_V << LP_IO_LP_GPIO1_MCU_IE_S)
-#define LP_IO_LP_GPIO1_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_IE_S  4
-/** LP_IO_LP_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO1_MCU_DRV_M  (LP_IO_LP_GPIO1_MCU_DRV_V << LP_IO_LP_GPIO1_MCU_DRV_S)
-#define LP_IO_LP_GPIO1_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO1_MCU_DRV_S  5
-/** LP_IO_LP_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO1_FUN_WPD_M  (LP_IO_LP_GPIO1_FUN_WPD_V << LP_IO_LP_GPIO1_FUN_WPD_S)
-#define LP_IO_LP_GPIO1_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO1_FUN_WPD_S  7
-/** LP_IO_LP_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO1_FUN_WPU_M  (LP_IO_LP_GPIO1_FUN_WPU_V << LP_IO_LP_GPIO1_FUN_WPU_S)
-#define LP_IO_LP_GPIO1_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO1_FUN_WPU_S  8
-/** LP_IO_LP_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO1_FUN_IE_M  (LP_IO_LP_GPIO1_FUN_IE_V << LP_IO_LP_GPIO1_FUN_IE_S)
-#define LP_IO_LP_GPIO1_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO1_FUN_IE_S  9
-/** LP_IO_LP_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO1_FUN_DRV_M  (LP_IO_LP_GPIO1_FUN_DRV_V << LP_IO_LP_GPIO1_FUN_DRV_S)
-#define LP_IO_LP_GPIO1_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO1_FUN_DRV_S  10
-/** LP_IO_LP_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO1_MCU_SEL_M  (LP_IO_LP_GPIO1_MCU_SEL_V << LP_IO_LP_GPIO1_MCU_SEL_S)
-#define LP_IO_LP_GPIO1_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO1_MCU_SEL_S  12
-
-/** LP_IO_GPIO2_REG register
- *  need des
- */
-#define LP_IO_GPIO2_REG (DR_REG_LP_IO_BASE + 0x50)
-/** LP_IO_LP_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO2_MCU_OE_M  (LP_IO_LP_GPIO2_MCU_OE_V << LP_IO_LP_GPIO2_MCU_OE_S)
-#define LP_IO_LP_GPIO2_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_OE_S  0
-/** LP_IO_LP_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO2_SLP_SEL_M  (LP_IO_LP_GPIO2_SLP_SEL_V << LP_IO_LP_GPIO2_SLP_SEL_S)
-#define LP_IO_LP_GPIO2_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO2_SLP_SEL_S  1
-/** LP_IO_LP_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO2_MCU_WPD_M  (LP_IO_LP_GPIO2_MCU_WPD_V << LP_IO_LP_GPIO2_MCU_WPD_S)
-#define LP_IO_LP_GPIO2_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_WPD_S  2
-/** LP_IO_LP_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO2_MCU_WPU_M  (LP_IO_LP_GPIO2_MCU_WPU_V << LP_IO_LP_GPIO2_MCU_WPU_S)
-#define LP_IO_LP_GPIO2_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_WPU_S  3
-/** LP_IO_LP_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO2_MCU_IE_M  (LP_IO_LP_GPIO2_MCU_IE_V << LP_IO_LP_GPIO2_MCU_IE_S)
-#define LP_IO_LP_GPIO2_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_IE_S  4
-/** LP_IO_LP_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO2_MCU_DRV_M  (LP_IO_LP_GPIO2_MCU_DRV_V << LP_IO_LP_GPIO2_MCU_DRV_S)
-#define LP_IO_LP_GPIO2_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO2_MCU_DRV_S  5
-/** LP_IO_LP_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO2_FUN_WPD_M  (LP_IO_LP_GPIO2_FUN_WPD_V << LP_IO_LP_GPIO2_FUN_WPD_S)
-#define LP_IO_LP_GPIO2_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO2_FUN_WPD_S  7
-/** LP_IO_LP_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO2_FUN_WPU_M  (LP_IO_LP_GPIO2_FUN_WPU_V << LP_IO_LP_GPIO2_FUN_WPU_S)
-#define LP_IO_LP_GPIO2_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO2_FUN_WPU_S  8
-/** LP_IO_LP_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO2_FUN_IE_M  (LP_IO_LP_GPIO2_FUN_IE_V << LP_IO_LP_GPIO2_FUN_IE_S)
-#define LP_IO_LP_GPIO2_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO2_FUN_IE_S  9
-/** LP_IO_LP_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO2_FUN_DRV_M  (LP_IO_LP_GPIO2_FUN_DRV_V << LP_IO_LP_GPIO2_FUN_DRV_S)
-#define LP_IO_LP_GPIO2_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO2_FUN_DRV_S  10
-/** LP_IO_LP_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO2_MCU_SEL_M  (LP_IO_LP_GPIO2_MCU_SEL_V << LP_IO_LP_GPIO2_MCU_SEL_S)
-#define LP_IO_LP_GPIO2_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO2_MCU_SEL_S  12
-
-/** LP_IO_GPIO3_REG register
- *  need des
- */
-#define LP_IO_GPIO3_REG (DR_REG_LP_IO_BASE + 0x54)
-/** LP_IO_LP_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO3_MCU_OE_M  (LP_IO_LP_GPIO3_MCU_OE_V << LP_IO_LP_GPIO3_MCU_OE_S)
-#define LP_IO_LP_GPIO3_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_OE_S  0
-/** LP_IO_LP_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO3_SLP_SEL_M  (LP_IO_LP_GPIO3_SLP_SEL_V << LP_IO_LP_GPIO3_SLP_SEL_S)
-#define LP_IO_LP_GPIO3_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO3_SLP_SEL_S  1
-/** LP_IO_LP_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO3_MCU_WPD_M  (LP_IO_LP_GPIO3_MCU_WPD_V << LP_IO_LP_GPIO3_MCU_WPD_S)
-#define LP_IO_LP_GPIO3_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_WPD_S  2
-/** LP_IO_LP_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO3_MCU_WPU_M  (LP_IO_LP_GPIO3_MCU_WPU_V << LP_IO_LP_GPIO3_MCU_WPU_S)
-#define LP_IO_LP_GPIO3_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_WPU_S  3
-/** LP_IO_LP_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO3_MCU_IE_M  (LP_IO_LP_GPIO3_MCU_IE_V << LP_IO_LP_GPIO3_MCU_IE_S)
-#define LP_IO_LP_GPIO3_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_IE_S  4
-/** LP_IO_LP_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO3_MCU_DRV_M  (LP_IO_LP_GPIO3_MCU_DRV_V << LP_IO_LP_GPIO3_MCU_DRV_S)
-#define LP_IO_LP_GPIO3_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO3_MCU_DRV_S  5
-/** LP_IO_LP_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO3_FUN_WPD_M  (LP_IO_LP_GPIO3_FUN_WPD_V << LP_IO_LP_GPIO3_FUN_WPD_S)
-#define LP_IO_LP_GPIO3_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO3_FUN_WPD_S  7
-/** LP_IO_LP_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO3_FUN_WPU_M  (LP_IO_LP_GPIO3_FUN_WPU_V << LP_IO_LP_GPIO3_FUN_WPU_S)
-#define LP_IO_LP_GPIO3_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO3_FUN_WPU_S  8
-/** LP_IO_LP_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO3_FUN_IE_M  (LP_IO_LP_GPIO3_FUN_IE_V << LP_IO_LP_GPIO3_FUN_IE_S)
-#define LP_IO_LP_GPIO3_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO3_FUN_IE_S  9
-/** LP_IO_LP_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO3_FUN_DRV_M  (LP_IO_LP_GPIO3_FUN_DRV_V << LP_IO_LP_GPIO3_FUN_DRV_S)
-#define LP_IO_LP_GPIO3_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO3_FUN_DRV_S  10
-/** LP_IO_LP_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO3_MCU_SEL_M  (LP_IO_LP_GPIO3_MCU_SEL_V << LP_IO_LP_GPIO3_MCU_SEL_S)
-#define LP_IO_LP_GPIO3_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO3_MCU_SEL_S  12
-
-/** LP_IO_GPIO4_REG register
- *  need des
- */
-#define LP_IO_GPIO4_REG (DR_REG_LP_IO_BASE + 0x58)
-/** LP_IO_LP_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO4_MCU_OE_M  (LP_IO_LP_GPIO4_MCU_OE_V << LP_IO_LP_GPIO4_MCU_OE_S)
-#define LP_IO_LP_GPIO4_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_OE_S  0
-/** LP_IO_LP_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO4_SLP_SEL_M  (LP_IO_LP_GPIO4_SLP_SEL_V << LP_IO_LP_GPIO4_SLP_SEL_S)
-#define LP_IO_LP_GPIO4_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO4_SLP_SEL_S  1
-/** LP_IO_LP_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO4_MCU_WPD_M  (LP_IO_LP_GPIO4_MCU_WPD_V << LP_IO_LP_GPIO4_MCU_WPD_S)
-#define LP_IO_LP_GPIO4_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_WPD_S  2
-/** LP_IO_LP_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO4_MCU_WPU_M  (LP_IO_LP_GPIO4_MCU_WPU_V << LP_IO_LP_GPIO4_MCU_WPU_S)
-#define LP_IO_LP_GPIO4_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_WPU_S  3
-/** LP_IO_LP_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO4_MCU_IE_M  (LP_IO_LP_GPIO4_MCU_IE_V << LP_IO_LP_GPIO4_MCU_IE_S)
-#define LP_IO_LP_GPIO4_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_IE_S  4
-/** LP_IO_LP_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO4_MCU_DRV_M  (LP_IO_LP_GPIO4_MCU_DRV_V << LP_IO_LP_GPIO4_MCU_DRV_S)
-#define LP_IO_LP_GPIO4_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO4_MCU_DRV_S  5
-/** LP_IO_LP_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO4_FUN_WPD_M  (LP_IO_LP_GPIO4_FUN_WPD_V << LP_IO_LP_GPIO4_FUN_WPD_S)
-#define LP_IO_LP_GPIO4_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO4_FUN_WPD_S  7
-/** LP_IO_LP_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO4_FUN_WPU_M  (LP_IO_LP_GPIO4_FUN_WPU_V << LP_IO_LP_GPIO4_FUN_WPU_S)
-#define LP_IO_LP_GPIO4_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO4_FUN_WPU_S  8
-/** LP_IO_LP_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO4_FUN_IE_M  (LP_IO_LP_GPIO4_FUN_IE_V << LP_IO_LP_GPIO4_FUN_IE_S)
-#define LP_IO_LP_GPIO4_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO4_FUN_IE_S  9
-/** LP_IO_LP_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO4_FUN_DRV_M  (LP_IO_LP_GPIO4_FUN_DRV_V << LP_IO_LP_GPIO4_FUN_DRV_S)
-#define LP_IO_LP_GPIO4_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO4_FUN_DRV_S  10
-/** LP_IO_LP_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO4_MCU_SEL_M  (LP_IO_LP_GPIO4_MCU_SEL_V << LP_IO_LP_GPIO4_MCU_SEL_S)
-#define LP_IO_LP_GPIO4_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO4_MCU_SEL_S  12
-
-/** LP_IO_GPIO5_REG register
- *  need des
- */
-#define LP_IO_GPIO5_REG (DR_REG_LP_IO_BASE + 0x5c)
-/** LP_IO_LP_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO5_MCU_OE_M  (LP_IO_LP_GPIO5_MCU_OE_V << LP_IO_LP_GPIO5_MCU_OE_S)
-#define LP_IO_LP_GPIO5_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_OE_S  0
-/** LP_IO_LP_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO5_SLP_SEL_M  (LP_IO_LP_GPIO5_SLP_SEL_V << LP_IO_LP_GPIO5_SLP_SEL_S)
-#define LP_IO_LP_GPIO5_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO5_SLP_SEL_S  1
-/** LP_IO_LP_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO5_MCU_WPD_M  (LP_IO_LP_GPIO5_MCU_WPD_V << LP_IO_LP_GPIO5_MCU_WPD_S)
-#define LP_IO_LP_GPIO5_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_WPD_S  2
-/** LP_IO_LP_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO5_MCU_WPU_M  (LP_IO_LP_GPIO5_MCU_WPU_V << LP_IO_LP_GPIO5_MCU_WPU_S)
-#define LP_IO_LP_GPIO5_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_WPU_S  3
-/** LP_IO_LP_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO5_MCU_IE_M  (LP_IO_LP_GPIO5_MCU_IE_V << LP_IO_LP_GPIO5_MCU_IE_S)
-#define LP_IO_LP_GPIO5_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_IE_S  4
-/** LP_IO_LP_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO5_MCU_DRV_M  (LP_IO_LP_GPIO5_MCU_DRV_V << LP_IO_LP_GPIO5_MCU_DRV_S)
-#define LP_IO_LP_GPIO5_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO5_MCU_DRV_S  5
-/** LP_IO_LP_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO5_FUN_WPD_M  (LP_IO_LP_GPIO5_FUN_WPD_V << LP_IO_LP_GPIO5_FUN_WPD_S)
-#define LP_IO_LP_GPIO5_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO5_FUN_WPD_S  7
-/** LP_IO_LP_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO5_FUN_WPU_M  (LP_IO_LP_GPIO5_FUN_WPU_V << LP_IO_LP_GPIO5_FUN_WPU_S)
-#define LP_IO_LP_GPIO5_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO5_FUN_WPU_S  8
-/** LP_IO_LP_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO5_FUN_IE_M  (LP_IO_LP_GPIO5_FUN_IE_V << LP_IO_LP_GPIO5_FUN_IE_S)
-#define LP_IO_LP_GPIO5_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO5_FUN_IE_S  9
-/** LP_IO_LP_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO5_FUN_DRV_M  (LP_IO_LP_GPIO5_FUN_DRV_V << LP_IO_LP_GPIO5_FUN_DRV_S)
-#define LP_IO_LP_GPIO5_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO5_FUN_DRV_S  10
-/** LP_IO_LP_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO5_MCU_SEL_M  (LP_IO_LP_GPIO5_MCU_SEL_V << LP_IO_LP_GPIO5_MCU_SEL_S)
-#define LP_IO_LP_GPIO5_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO5_MCU_SEL_S  12
-
-/** LP_IO_GPIO6_REG register
- *  need des
- */
-#define LP_IO_GPIO6_REG (DR_REG_LP_IO_BASE + 0x60)
-/** LP_IO_LP_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO6_MCU_OE_M  (LP_IO_LP_GPIO6_MCU_OE_V << LP_IO_LP_GPIO6_MCU_OE_S)
-#define LP_IO_LP_GPIO6_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_OE_S  0
-/** LP_IO_LP_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO6_SLP_SEL_M  (LP_IO_LP_GPIO6_SLP_SEL_V << LP_IO_LP_GPIO6_SLP_SEL_S)
-#define LP_IO_LP_GPIO6_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO6_SLP_SEL_S  1
-/** LP_IO_LP_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO6_MCU_WPD_M  (LP_IO_LP_GPIO6_MCU_WPD_V << LP_IO_LP_GPIO6_MCU_WPD_S)
-#define LP_IO_LP_GPIO6_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_WPD_S  2
-/** LP_IO_LP_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO6_MCU_WPU_M  (LP_IO_LP_GPIO6_MCU_WPU_V << LP_IO_LP_GPIO6_MCU_WPU_S)
-#define LP_IO_LP_GPIO6_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_WPU_S  3
-/** LP_IO_LP_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO6_MCU_IE_M  (LP_IO_LP_GPIO6_MCU_IE_V << LP_IO_LP_GPIO6_MCU_IE_S)
-#define LP_IO_LP_GPIO6_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_IE_S  4
-/** LP_IO_LP_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO6_MCU_DRV_M  (LP_IO_LP_GPIO6_MCU_DRV_V << LP_IO_LP_GPIO6_MCU_DRV_S)
-#define LP_IO_LP_GPIO6_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO6_MCU_DRV_S  5
-/** LP_IO_LP_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO6_FUN_WPD_M  (LP_IO_LP_GPIO6_FUN_WPD_V << LP_IO_LP_GPIO6_FUN_WPD_S)
-#define LP_IO_LP_GPIO6_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO6_FUN_WPD_S  7
-/** LP_IO_LP_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO6_FUN_WPU_M  (LP_IO_LP_GPIO6_FUN_WPU_V << LP_IO_LP_GPIO6_FUN_WPU_S)
-#define LP_IO_LP_GPIO6_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO6_FUN_WPU_S  8
-/** LP_IO_LP_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO6_FUN_IE_M  (LP_IO_LP_GPIO6_FUN_IE_V << LP_IO_LP_GPIO6_FUN_IE_S)
-#define LP_IO_LP_GPIO6_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO6_FUN_IE_S  9
-/** LP_IO_LP_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO6_FUN_DRV_M  (LP_IO_LP_GPIO6_FUN_DRV_V << LP_IO_LP_GPIO6_FUN_DRV_S)
-#define LP_IO_LP_GPIO6_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO6_FUN_DRV_S  10
-/** LP_IO_LP_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO6_MCU_SEL_M  (LP_IO_LP_GPIO6_MCU_SEL_V << LP_IO_LP_GPIO6_MCU_SEL_S)
-#define LP_IO_LP_GPIO6_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO6_MCU_SEL_S  12
-
-/** LP_IO_GPIO7_REG register
- *  need des
- */
-#define LP_IO_GPIO7_REG (DR_REG_LP_IO_BASE + 0x64)
-/** LP_IO_LP_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO7_MCU_OE_M  (LP_IO_LP_GPIO7_MCU_OE_V << LP_IO_LP_GPIO7_MCU_OE_S)
-#define LP_IO_LP_GPIO7_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_OE_S  0
-/** LP_IO_LP_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO7_SLP_SEL_M  (LP_IO_LP_GPIO7_SLP_SEL_V << LP_IO_LP_GPIO7_SLP_SEL_S)
-#define LP_IO_LP_GPIO7_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO7_SLP_SEL_S  1
-/** LP_IO_LP_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO7_MCU_WPD_M  (LP_IO_LP_GPIO7_MCU_WPD_V << LP_IO_LP_GPIO7_MCU_WPD_S)
-#define LP_IO_LP_GPIO7_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_WPD_S  2
-/** LP_IO_LP_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO7_MCU_WPU_M  (LP_IO_LP_GPIO7_MCU_WPU_V << LP_IO_LP_GPIO7_MCU_WPU_S)
-#define LP_IO_LP_GPIO7_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_WPU_S  3
-/** LP_IO_LP_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO7_MCU_IE_M  (LP_IO_LP_GPIO7_MCU_IE_V << LP_IO_LP_GPIO7_MCU_IE_S)
-#define LP_IO_LP_GPIO7_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_IE_S  4
-/** LP_IO_LP_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO7_MCU_DRV_M  (LP_IO_LP_GPIO7_MCU_DRV_V << LP_IO_LP_GPIO7_MCU_DRV_S)
-#define LP_IO_LP_GPIO7_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO7_MCU_DRV_S  5
-/** LP_IO_LP_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO7_FUN_WPD_M  (LP_IO_LP_GPIO7_FUN_WPD_V << LP_IO_LP_GPIO7_FUN_WPD_S)
-#define LP_IO_LP_GPIO7_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO7_FUN_WPD_S  7
-/** LP_IO_LP_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO7_FUN_WPU_M  (LP_IO_LP_GPIO7_FUN_WPU_V << LP_IO_LP_GPIO7_FUN_WPU_S)
-#define LP_IO_LP_GPIO7_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO7_FUN_WPU_S  8
-/** LP_IO_LP_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO7_FUN_IE_M  (LP_IO_LP_GPIO7_FUN_IE_V << LP_IO_LP_GPIO7_FUN_IE_S)
-#define LP_IO_LP_GPIO7_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO7_FUN_IE_S  9
-/** LP_IO_LP_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO7_FUN_DRV_M  (LP_IO_LP_GPIO7_FUN_DRV_V << LP_IO_LP_GPIO7_FUN_DRV_S)
-#define LP_IO_LP_GPIO7_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO7_FUN_DRV_S  10
-/** LP_IO_LP_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO7_MCU_SEL_M  (LP_IO_LP_GPIO7_MCU_SEL_V << LP_IO_LP_GPIO7_MCU_SEL_S)
-#define LP_IO_LP_GPIO7_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO7_MCU_SEL_S  12
-
-/** LP_IO_STATUS_INTERRUPT_REG register
- *  need des
- */
-#define LP_IO_STATUS_INTERRUPT_REG (DR_REG_LP_IO_BASE + 0x68)
-/** LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT    0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_M  (LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S)
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V  0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S  0
-
-/** LP_IO_DEBUG_SEL0_REG register
- *  need des
- */
-#define LP_IO_DEBUG_SEL0_REG (DR_REG_LP_IO_BASE + 0x6c)
-/** LP_IO_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL0    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL0_M  (LP_IO_LP_DEBUG_SEL0_V << LP_IO_LP_DEBUG_SEL0_S)
-#define LP_IO_LP_DEBUG_SEL0_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL0_S  0
-/** LP_IO_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL1    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL1_M  (LP_IO_LP_DEBUG_SEL1_V << LP_IO_LP_DEBUG_SEL1_S)
-#define LP_IO_LP_DEBUG_SEL1_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL1_S  7
-/** LP_IO_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL2    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL2_M  (LP_IO_LP_DEBUG_SEL2_V << LP_IO_LP_DEBUG_SEL2_S)
-#define LP_IO_LP_DEBUG_SEL2_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL2_S  14
-/** LP_IO_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL3    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL3_M  (LP_IO_LP_DEBUG_SEL3_V << LP_IO_LP_DEBUG_SEL3_S)
-#define LP_IO_LP_DEBUG_SEL3_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL3_S  21
-
-/** LP_IO_DEBUG_SEL1_REG register
- *  need des
- */
-#define LP_IO_DEBUG_SEL1_REG (DR_REG_LP_IO_BASE + 0x70)
-/** LP_IO_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL4    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL4_M  (LP_IO_LP_DEBUG_SEL4_V << LP_IO_LP_DEBUG_SEL4_S)
-#define LP_IO_LP_DEBUG_SEL4_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL4_S  0
-
-/** LP_IO_LPI2C_REG register
- *  need des
- */
-#define LP_IO_LPI2C_REG (DR_REG_LP_IO_BASE + 0x74)
-/** LP_IO_LP_I2C_SDA_IE : R/W; bitpos: [30]; default: 1;
- *  need des
- */
-#define LP_IO_LP_I2C_SDA_IE    (BIT(30))
-#define LP_IO_LP_I2C_SDA_IE_M  (LP_IO_LP_I2C_SDA_IE_V << LP_IO_LP_I2C_SDA_IE_S)
-#define LP_IO_LP_I2C_SDA_IE_V  0x00000001U
-#define LP_IO_LP_I2C_SDA_IE_S  30
-/** LP_IO_LP_I2C_SCL_IE : R/W; bitpos: [31]; default: 1;
- *  need des
- */
-#define LP_IO_LP_I2C_SCL_IE    (BIT(31))
-#define LP_IO_LP_I2C_SCL_IE_M  (LP_IO_LP_I2C_SCL_IE_V << LP_IO_LP_I2C_SCL_IE_S)
-#define LP_IO_LP_I2C_SCL_IE_V  0x00000001U
-#define LP_IO_LP_I2C_SCL_IE_S  31
-
-/** LP_IO_DATE_REG register
- *  need des
- */
-#define LP_IO_DATE_REG (DR_REG_LP_IO_BASE + 0x3fc)
-/** LP_IO_LP_IO_DATE : R/W; bitpos: [30:0]; default: 35660032;
- *  need des
- */
-#define LP_IO_LP_IO_DATE    0x7FFFFFFFU
-#define LP_IO_LP_IO_DATE_M  (LP_IO_LP_IO_DATE_V << LP_IO_LP_IO_DATE_S)
-#define LP_IO_LP_IO_DATE_V  0x7FFFFFFFU
-#define LP_IO_LP_IO_DATE_S  0
-/** LP_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need des
- */
-#define LP_IO_CLK_EN    (BIT(31))
-#define LP_IO_CLK_EN_M  (LP_IO_CLK_EN_V << LP_IO_CLK_EN_S)
-#define LP_IO_CLK_EN_V  0x00000001U
-#define LP_IO_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_io_struct.h b/components/soc/esp32p4/include/soc/lp_io_struct.h
deleted file mode 100644
index 97404851bb..0000000000
--- a/components/soc/esp32p4/include/soc/lp_io_struct.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of out_data register
- *  need des
- */
-typedef union {
-    struct {
-        /** out_data : R/W/WTC; bitpos: [7:0]; default: 0;
-         *  set lp gpio output data
-         */
-        uint32_t out_data:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_data_reg_t;
-
-/** Type of out_data_w1ts register
- *  need des
- */
-typedef union {
-    struct {
-        /** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
-         *  set one time output data
-         */
-        uint32_t out_data_w1ts:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_data_w1ts_reg_t;
-
-/** Type of out_data_w1tc register
- *  need des
- */
-typedef union {
-    struct {
-        /** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
-         *  clear one time output data
-         */
-        uint32_t out_data_w1tc:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_data_w1tc_reg_t;
-
-/** Type of out_enable register
- *  need des
- */
-typedef union {
-    struct {
-        /** enable : R/W/WTC; bitpos: [7:0]; default: 0;
-         *  set lp gpio output data
-         */
-        uint32_t enable:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_enable_reg_t;
-
-/** Type of out_enable_w1ts register
- *  need des
- */
-typedef union {
-    struct {
-        /** enable_w1ts : WT; bitpos: [7:0]; default: 0;
-         *  set one time output data
-         */
-        uint32_t enable_w1ts:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_enable_w1ts_reg_t;
-
-/** Type of out_enable_w1tc register
- *  need des
- */
-typedef union {
-    struct {
-        /** enable_w1tc : WT; bitpos: [7:0]; default: 0;
-         *  clear one time output data
-         */
-        uint32_t enable_w1tc:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_enable_w1tc_reg_t;
-
-/** Type of status register
- *  need des
- */
-typedef union {
-    struct {
-        /** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
-         *  set lp gpio output data
-         */
-        uint32_t status_interrupt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_reg_t;
-
-/** Type of status_w1ts register
- *  need des
- */
-typedef union {
-    struct {
-        /** status_w1ts : WT; bitpos: [7:0]; default: 0;
-         *  set one time output data
-         */
-        uint32_t status_w1ts:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_w1ts_reg_t;
-
-/** Type of status_w1tc register
- *  need des
- */
-typedef union {
-    struct {
-        /** status_w1tc : WT; bitpos: [7:0]; default: 0;
-         *  clear one time output data
-         */
-        uint32_t status_w1tc:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_w1tc_reg_t;
-
-/** Type of in register
- *  need des
- */
-typedef union {
-    struct {
-        /** in_data_next : RO; bitpos: [7:0]; default: 0;
-         *  need des
-         */
-        uint32_t in_data_next:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_in_reg_t;
-
-/** Type of pin register
- *  need des
- */
-typedef union {
-    struct {
-        /** sync_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  need des
-         */
-        uint32_t sync_bypass:2;
-        /** pad_driver : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t pad_driver:1;
-        /** edge_wakeup_clr : WT; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** int_type : R/W; bitpos: [9:7]; default: 0;
-         *  need des
-         */
-        uint32_t int_type:3;
-        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  need des
-         */
-        uint32_t wakeup_enable:1;
-        /** filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin_reg_t;
-
-/** Type of gpio register
- *  need des
- */
-typedef union {
-    struct {
-        /** mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t mcu_oe:1;
-        /** slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t slp_sel:1;
-        /** mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t mcu_wpd:1;
-        /** mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t mcu_wpu:1;
-        /** mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t mcu_ie:1;
-        /** mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t mcu_drv:2;
-        /** fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t fun_wpd:1;
-        /** fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t fun_wpu:1;
-        /** fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t fun_ie:1;
-        /** fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t fun_drv:2;
-        /** mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio_reg_t;
-
-/** Type of status_interrupt register
- *  need des
- */
-typedef union {
-    struct {
-        /** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
-         *  need des
-         */
-        uint32_t status_interrupt_next:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_interrupt_reg_t;
-
-/** Type of debug_sel0 register
- *  need des
- */
-typedef union {
-    struct {
-        /** debug_sel0 : R/W; bitpos: [6:0]; default: 0;
-         *  need des
-         */
-        uint32_t debug_sel0:7;
-        /** debug_sel1 : R/W; bitpos: [13:7]; default: 0;
-         *  need des
-         */
-        uint32_t debug_sel1:7;
-        /** debug_sel2 : R/W; bitpos: [20:14]; default: 0;
-         *  need des
-         */
-        uint32_t debug_sel2:7;
-        /** debug_sel3 : R/W; bitpos: [27:21]; default: 0;
-         *  need des
-         */
-        uint32_t debug_sel3:7;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_io_debug_sel0_reg_t;
-
-/** Type of debug_sel1 register
- *  need des
- */
-typedef union {
-    struct {
-        /** debug_sel4 : R/W; bitpos: [6:0]; default: 0;
-         *  need des
-         */
-        uint32_t debug_sel4:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_io_debug_sel1_reg_t;
-
-/** Type of lpi2c register
- *  need des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1;
-         *  need des
-         */
-        uint32_t lp_i2c_sda_ie:1;
-        /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1;
-         *  need des
-         */
-        uint32_t lp_i2c_scl_ie:1;
-    };
-    uint32_t val;
-} lp_io_lpi2c_reg_t;
-
-/** Type of date register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032;
-         *  need des
-         */
-        uint32_t lp_io_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_io_date_reg_t;
-
-
-typedef struct lp_io_dev_t {
-    volatile lp_io_out_data_reg_t out_data;
-    volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
-    volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
-    volatile lp_io_out_enable_reg_t out_enable;
-    volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts;
-    volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc;
-    volatile lp_io_status_reg_t status;
-    volatile lp_io_status_w1ts_reg_t status_w1ts;
-    volatile lp_io_status_w1tc_reg_t status_w1tc;
-    volatile lp_io_in_reg_t in;
-    volatile lp_io_pin_reg_t pin[8];
-    volatile lp_io_gpio_reg_t gpio[8];
-    volatile lp_io_status_interrupt_reg_t status_interrupt;
-    volatile lp_io_debug_sel0_reg_t debug_sel0;
-    volatile lp_io_debug_sel1_reg_t debug_sel1;
-    volatile lp_io_lpi2c_reg_t lpi2c;
-    uint32_t reserved_078[225];
-    volatile lp_io_date_reg_t date;
-} lp_io_dev_t;
-
-extern lp_io_dev_t LP_IO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_iomux_struct.h b/components/soc/esp32p4/include/soc/lp_iomux_struct.h
index 5d19cd4a0e..c389b7e4fa 100644
--- a/components/soc/esp32p4/include/soc/lp_iomux_struct.h
+++ b/components/soc/esp32p4/include/soc/lp_iomux_struct.h
@@ -926,7 +926,7 @@ typedef union {
 } lp_iomux_lp_pad_hys_reg_t;
 
 
-typedef struct {
+typedef struct lp_iomux_dev_t {
     volatile lp_iomux_clk_en_reg_t clk_en;
     volatile lp_iomux_ver_date_reg_t ver_date;
     volatile lp_iomux_pad0_reg_t pad0;
diff --git a/components/soc/esp32p4/include/soc/lp_sys_reg.h b/components/soc/esp32p4/include/soc/lp_sys_reg.h
deleted file mode 100644
index 5df8429220..0000000000
--- a/components/soc/esp32p4/include/soc/lp_sys_reg.h
+++ /dev/null
@@ -1,1349 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_SYSTEM_REG_LP_SYS_VER_DATE_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SYS_VER_DATE_REG (DR_REG_LP_SYS_BASE + 0x0)
-/** LP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165961;
- *  need_des
- */
-#define LP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
-#define LP_SYSTEM_REG_VER_DATE_M  (LP_SYSTEM_REG_VER_DATE_V << LP_SYSTEM_REG_VER_DATE_S)
-#define LP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_VER_DATE_S  0
-
-/** LP_SYSTEM_REG_CLK_SEL_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_CLK_SEL_CTRL_REG (DR_REG_LP_SYS_BASE + 0x4)
-/** LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK    (BIT(16))
-#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_M  (LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V << LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S)
-#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V  0x00000001U
-#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S  16
-/** LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL    (BIT(17))
-#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_M  (LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V << LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S)
-#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V  0x00000001U
-#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S  17
-
-/** LP_SYSTEM_REG_SYS_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_SYS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x8)
-/** LP_SYSTEM_REG_LP_CORE_DISABLE : R/W; bitpos: [0]; default: 0;
- *  lp cpu disable
- */
-#define LP_SYSTEM_REG_LP_CORE_DISABLE    (BIT(0))
-#define LP_SYSTEM_REG_LP_CORE_DISABLE_M  (LP_SYSTEM_REG_LP_CORE_DISABLE_V << LP_SYSTEM_REG_LP_CORE_DISABLE_S)
-#define LP_SYSTEM_REG_LP_CORE_DISABLE_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_DISABLE_S  0
-/** LP_SYSTEM_REG_SYS_SW_RST : WT; bitpos: [1]; default: 0;
- *  digital system software reset bit
- */
-#define LP_SYSTEM_REG_SYS_SW_RST    (BIT(1))
-#define LP_SYSTEM_REG_SYS_SW_RST_M  (LP_SYSTEM_REG_SYS_SW_RST_V << LP_SYSTEM_REG_SYS_SW_RST_S)
-#define LP_SYSTEM_REG_SYS_SW_RST_V  0x00000001U
-#define LP_SYSTEM_REG_SYS_SW_RST_S  1
-/** LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [2]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT    (BIT(2))
-#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_M  (LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V << LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S)
-#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V  0x00000001U
-#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S  2
-/** LP_SYSTEM_REG_DIG_FIB : R/W; bitpos: [10:3]; default: 255;
- *  need_des
- */
-#define LP_SYSTEM_REG_DIG_FIB    0x000000FFU
-#define LP_SYSTEM_REG_DIG_FIB_M  (LP_SYSTEM_REG_DIG_FIB_V << LP_SYSTEM_REG_DIG_FIB_S)
-#define LP_SYSTEM_REG_DIG_FIB_V  0x000000FFU
-#define LP_SYSTEM_REG_DIG_FIB_S  3
-/** LP_SYSTEM_REG_IO_MUX_RESET_DISABLE : R/W; bitpos: [11]; default: 0;
- *  reset disable bit for LP IOMUX
- */
-#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE    (BIT(11))
-#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_M  (LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V << LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S)
-#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V  0x00000001U
-#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S  11
-/** LP_SYSTEM_REG_ANA_FIB : RO; bitpos: [20:14]; default: 127;
- *  need_des
- */
-#define LP_SYSTEM_REG_ANA_FIB    0x0000007FU
-#define LP_SYSTEM_REG_ANA_FIB_M  (LP_SYSTEM_REG_ANA_FIB_V << LP_SYSTEM_REG_ANA_FIB_S)
-#define LP_SYSTEM_REG_ANA_FIB_V  0x0000007FU
-#define LP_SYSTEM_REG_ANA_FIB_S  14
-/** LP_SYSTEM_REG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_FIB_SEL    0x000000FFU
-#define LP_SYSTEM_REG_LP_FIB_SEL_M  (LP_SYSTEM_REG_LP_FIB_SEL_V << LP_SYSTEM_REG_LP_FIB_SEL_S)
-#define LP_SYSTEM_REG_LP_FIB_SEL_V  0x000000FFU
-#define LP_SYSTEM_REG_LP_FIB_SEL_S  21
-/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR    (BIT(29))
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S)
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S  29
-/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG    (BIT(30))
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S)
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S  30
-/** LP_SYSTEM_REG_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0;
- *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
- *  hp_core1
- */
-#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL    (BIT(31))
-#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_M  (LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V << LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S)
-#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V  0x00000001U
-#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S  31
-
-/** LP_SYSTEM_REG_LP_CLK_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0xc)
-/** LP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  need_des
- */
-#define LP_SYSTEM_REG_CLK_EN    (BIT(0))
-#define LP_SYSTEM_REG_CLK_EN_M  (LP_SYSTEM_REG_CLK_EN_V << LP_SYSTEM_REG_CLK_EN_S)
-#define LP_SYSTEM_REG_CLK_EN_V  0x00000001U
-#define LP_SYSTEM_REG_CLK_EN_S  0
-/** LP_SYSTEM_REG_LP_FOSC_HP_CKEN : R/W; bitpos: [14]; default: 1;
- *  reserved
- */
-#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN    (BIT(14))
-#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_M  (LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V << LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S)
-#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V  0x00000001U
-#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S  14
-
-/** LP_SYSTEM_REG_LP_RST_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_RST_CTRL_REG (DR_REG_LP_SYS_BASE + 0x10)
-/** LP_SYSTEM_REG_ANA_RST_BYPASS : R/W; bitpos: [0]; default: 1;
- *  analog source reset bypass : wdt,brown out,super wdt,glitch
- */
-#define LP_SYSTEM_REG_ANA_RST_BYPASS    (BIT(0))
-#define LP_SYSTEM_REG_ANA_RST_BYPASS_M  (LP_SYSTEM_REG_ANA_RST_BYPASS_V << LP_SYSTEM_REG_ANA_RST_BYPASS_S)
-#define LP_SYSTEM_REG_ANA_RST_BYPASS_V  0x00000001U
-#define LP_SYSTEM_REG_ANA_RST_BYPASS_S  0
-/** LP_SYSTEM_REG_SYS_RST_BYPASS : R/W; bitpos: [1]; default: 1;
- *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
- */
-#define LP_SYSTEM_REG_SYS_RST_BYPASS    (BIT(1))
-#define LP_SYSTEM_REG_SYS_RST_BYPASS_M  (LP_SYSTEM_REG_SYS_RST_BYPASS_V << LP_SYSTEM_REG_SYS_RST_BYPASS_S)
-#define LP_SYSTEM_REG_SYS_RST_BYPASS_V  0x00000001U
-#define LP_SYSTEM_REG_SYS_RST_BYPASS_S  1
-/** LP_SYSTEM_REG_EFUSE_FORCE_NORST : R/W; bitpos: [2]; default: 0;
- *  efuse force no reset control
- */
-#define LP_SYSTEM_REG_EFUSE_FORCE_NORST    (BIT(2))
-#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_M  (LP_SYSTEM_REG_EFUSE_FORCE_NORST_V << LP_SYSTEM_REG_EFUSE_FORCE_NORST_S)
-#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_V  0x00000001U
-#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_S  2
-
-/** LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG (DR_REG_LP_SYS_BASE + 0x18)
-/** LP_SYSTEM_REG_LP_CPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 1343225856;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_M  (LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V << LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S)
-#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S  0
-
-/** LP_SYSTEM_REG_EXT_WAKEUP1_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_EXT_WAKEUP1_REG (DR_REG_LP_SYS_BASE + 0x1c)
-/** LP_SYSTEM_REG_EXT_WAKEUP1_SEL : R/W; bitpos: [15:0]; default: 0;
- *  Bitmap to select RTC pads for ext wakeup1
- */
-#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL    0x0000FFFFU
-#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_M  (LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V << LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S)
-#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V  0x0000FFFFU
-#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S  0
-/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR : WT; bitpos: [16]; default: 0;
- *  clear ext wakeup1 status
- */
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR    (BIT(16))
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S)
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S  16
-
-/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG (DR_REG_LP_SYS_BASE + 0x20)
-/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS : RO; bitpos: [15:0]; default: 0;
- *  ext wakeup1 status
- */
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS    0x0000FFFFU
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S)
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V  0x0000FFFFU
-#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S  0
-
-/** LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG (DR_REG_LP_SYS_BASE + 0x24)
-/** LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON    (BIT(5))
-#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S)
-#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V  0x00000001U
-#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S  5
-/** LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON    (BIT(7))
-#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S)
-#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V  0x00000001U
-#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S  7
-
-/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG (DR_REG_LP_SYS_BASE + 0x28)
-/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP    0xFFFFFFFFU
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V << LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S)
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S  0
-
-/** LP_SYSTEM_REG_LP_STORE0_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE0_REG (DR_REG_LP_SYS_BASE + 0x2c)
-/** LP_SYSTEM_REG_LP_SCRATCH0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH0    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH0_M  (LP_SYSTEM_REG_LP_SCRATCH0_V << LP_SYSTEM_REG_LP_SCRATCH0_S)
-#define LP_SYSTEM_REG_LP_SCRATCH0_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH0_S  0
-
-/** LP_SYSTEM_REG_LP_STORE1_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE1_REG (DR_REG_LP_SYS_BASE + 0x30)
-/** LP_SYSTEM_REG_LP_SCRATCH1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH1    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH1_M  (LP_SYSTEM_REG_LP_SCRATCH1_V << LP_SYSTEM_REG_LP_SCRATCH1_S)
-#define LP_SYSTEM_REG_LP_SCRATCH1_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH1_S  0
-
-/** LP_SYSTEM_REG_LP_STORE2_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE2_REG (DR_REG_LP_SYS_BASE + 0x34)
-/** LP_SYSTEM_REG_LP_SCRATCH2 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH2    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH2_M  (LP_SYSTEM_REG_LP_SCRATCH2_V << LP_SYSTEM_REG_LP_SCRATCH2_S)
-#define LP_SYSTEM_REG_LP_SCRATCH2_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH2_S  0
-
-/** LP_SYSTEM_REG_LP_STORE3_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE3_REG (DR_REG_LP_SYS_BASE + 0x38)
-/** LP_SYSTEM_REG_LP_SCRATCH3 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH3    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH3_M  (LP_SYSTEM_REG_LP_SCRATCH3_V << LP_SYSTEM_REG_LP_SCRATCH3_S)
-#define LP_SYSTEM_REG_LP_SCRATCH3_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH3_S  0
-
-/** LP_SYSTEM_REG_LP_STORE4_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE4_REG (DR_REG_LP_SYS_BASE + 0x3c)
-/** LP_SYSTEM_REG_LP_SCRATCH4 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH4    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH4_M  (LP_SYSTEM_REG_LP_SCRATCH4_V << LP_SYSTEM_REG_LP_SCRATCH4_S)
-#define LP_SYSTEM_REG_LP_SCRATCH4_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH4_S  0
-
-/** LP_SYSTEM_REG_LP_STORE5_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE5_REG (DR_REG_LP_SYS_BASE + 0x40)
-/** LP_SYSTEM_REG_LP_SCRATCH5 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH5    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH5_M  (LP_SYSTEM_REG_LP_SCRATCH5_V << LP_SYSTEM_REG_LP_SCRATCH5_S)
-#define LP_SYSTEM_REG_LP_SCRATCH5_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH5_S  0
-
-/** LP_SYSTEM_REG_LP_STORE6_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE6_REG (DR_REG_LP_SYS_BASE + 0x44)
-/** LP_SYSTEM_REG_LP_SCRATCH6 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH6    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH6_M  (LP_SYSTEM_REG_LP_SCRATCH6_V << LP_SYSTEM_REG_LP_SCRATCH6_S)
-#define LP_SYSTEM_REG_LP_SCRATCH6_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH6_S  0
-
-/** LP_SYSTEM_REG_LP_STORE7_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE7_REG (DR_REG_LP_SYS_BASE + 0x48)
-/** LP_SYSTEM_REG_LP_SCRATCH7 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH7    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH7_M  (LP_SYSTEM_REG_LP_SCRATCH7_V << LP_SYSTEM_REG_LP_SCRATCH7_S)
-#define LP_SYSTEM_REG_LP_SCRATCH7_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH7_S  0
-
-/** LP_SYSTEM_REG_LP_STORE8_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE8_REG (DR_REG_LP_SYS_BASE + 0x4c)
-/** LP_SYSTEM_REG_LP_SCRATCH8 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH8    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH8_M  (LP_SYSTEM_REG_LP_SCRATCH8_V << LP_SYSTEM_REG_LP_SCRATCH8_S)
-#define LP_SYSTEM_REG_LP_SCRATCH8_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH8_S  0
-
-/** LP_SYSTEM_REG_LP_STORE9_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE9_REG (DR_REG_LP_SYS_BASE + 0x50)
-/** LP_SYSTEM_REG_LP_SCRATCH9 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH9    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH9_M  (LP_SYSTEM_REG_LP_SCRATCH9_V << LP_SYSTEM_REG_LP_SCRATCH9_S)
-#define LP_SYSTEM_REG_LP_SCRATCH9_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH9_S  0
-
-/** LP_SYSTEM_REG_LP_STORE10_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE10_REG (DR_REG_LP_SYS_BASE + 0x54)
-/** LP_SYSTEM_REG_LP_SCRATCH10 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH10    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH10_M  (LP_SYSTEM_REG_LP_SCRATCH10_V << LP_SYSTEM_REG_LP_SCRATCH10_S)
-#define LP_SYSTEM_REG_LP_SCRATCH10_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH10_S  0
-
-/** LP_SYSTEM_REG_LP_STORE11_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE11_REG (DR_REG_LP_SYS_BASE + 0x58)
-/** LP_SYSTEM_REG_LP_SCRATCH11 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH11    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH11_M  (LP_SYSTEM_REG_LP_SCRATCH11_V << LP_SYSTEM_REG_LP_SCRATCH11_S)
-#define LP_SYSTEM_REG_LP_SCRATCH11_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH11_S  0
-
-/** LP_SYSTEM_REG_LP_STORE12_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE12_REG (DR_REG_LP_SYS_BASE + 0x5c)
-/** LP_SYSTEM_REG_LP_SCRATCH12 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH12    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH12_M  (LP_SYSTEM_REG_LP_SCRATCH12_V << LP_SYSTEM_REG_LP_SCRATCH12_S)
-#define LP_SYSTEM_REG_LP_SCRATCH12_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH12_S  0
-
-/** LP_SYSTEM_REG_LP_STORE13_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE13_REG (DR_REG_LP_SYS_BASE + 0x60)
-/** LP_SYSTEM_REG_LP_SCRATCH13 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH13    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH13_M  (LP_SYSTEM_REG_LP_SCRATCH13_V << LP_SYSTEM_REG_LP_SCRATCH13_S)
-#define LP_SYSTEM_REG_LP_SCRATCH13_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH13_S  0
-
-/** LP_SYSTEM_REG_LP_STORE14_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE14_REG (DR_REG_LP_SYS_BASE + 0x64)
-/** LP_SYSTEM_REG_LP_SCRATCH14 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH14    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH14_M  (LP_SYSTEM_REG_LP_SCRATCH14_V << LP_SYSTEM_REG_LP_SCRATCH14_S)
-#define LP_SYSTEM_REG_LP_SCRATCH14_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH14_S  0
-
-/** LP_SYSTEM_REG_LP_STORE15_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_STORE15_REG (DR_REG_LP_SYS_BASE + 0x68)
-/** LP_SYSTEM_REG_LP_SCRATCH15 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_SCRATCH15    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH15_M  (LP_SYSTEM_REG_LP_SCRATCH15_V << LP_SYSTEM_REG_LP_SCRATCH15_S)
-#define LP_SYSTEM_REG_LP_SCRATCH15_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_SCRATCH15_S  0
-
-/** LP_SYSTEM_REG_LP_PROBEA_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_PROBEA_CTRL_REG (DR_REG_LP_SYS_BASE + 0x6c)
-/** LP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
-#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_A_MOD_SEL_V << LP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
-#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
-#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
-/** LP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
-#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_A_TOP_SEL_V << LP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
-#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
-#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
-/** LP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
-#define LP_SYSTEM_REG_PROBE_L_SEL_M  (LP_SYSTEM_REG_PROBE_L_SEL_V << LP_SYSTEM_REG_PROBE_L_SEL_S)
-#define LP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
-#define LP_SYSTEM_REG_PROBE_L_SEL_S  24
-/** LP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
-#define LP_SYSTEM_REG_PROBE_H_SEL_M  (LP_SYSTEM_REG_PROBE_H_SEL_V << LP_SYSTEM_REG_PROBE_H_SEL_S)
-#define LP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
-#define LP_SYSTEM_REG_PROBE_H_SEL_S  26
-/** LP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
-#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (LP_SYSTEM_REG_PROBE_GLOBAL_EN_V << LP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
-#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
-#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
-
-/** LP_SYSTEM_REG_LP_PROBEB_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_PROBEB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x70)
-/** LP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
-#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_B_MOD_SEL_V << LP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
-#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
-#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
-/** LP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
-#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_B_TOP_SEL_V << LP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
-#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
-#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
-/** LP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
-#define LP_SYSTEM_REG_PROBE_B_EN_M  (LP_SYSTEM_REG_PROBE_B_EN_V << LP_SYSTEM_REG_PROBE_B_EN_S)
-#define LP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
-#define LP_SYSTEM_REG_PROBE_B_EN_S  24
-
-/** LP_SYSTEM_REG_LP_PROBE_OUT_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_PROBE_OUT_REG (DR_REG_LP_SYS_BASE + 0x74)
-/** LP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
-#define LP_SYSTEM_REG_PROBE_TOP_OUT_M  (LP_SYSTEM_REG_PROBE_TOP_OUT_V << LP_SYSTEM_REG_PROBE_TOP_OUT_S)
-#define LP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_PROBE_TOP_OUT_S  0
-
-/** LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG (DR_REG_LP_SYS_BASE + 0x9c)
-/** LP_SYSTEM_REG_F2S_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define LP_SYSTEM_REG_F2S_APB_POSTW_EN    (BIT(0))
-#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_M  (LP_SYSTEM_REG_F2S_APB_POSTW_EN_V << LP_SYSTEM_REG_F2S_APB_POSTW_EN_S)
-#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_V  0x00000001U
-#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_S  0
-
-/** LP_SYSTEM_REG_USB_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_USB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x100)
-/** LP_SYSTEM_REG_SW_HW_USB_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL    (BIT(0))
-#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S)
-#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V  0x00000001U
-#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S  0
-/** LP_SYSTEM_REG_SW_USB_PHY_SEL : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_SW_USB_PHY_SEL    (BIT(1))
-#define LP_SYSTEM_REG_SW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_USB_PHY_SEL_S)
-#define LP_SYSTEM_REG_SW_USB_PHY_SEL_V  0x00000001U
-#define LP_SYSTEM_REG_SW_USB_PHY_SEL_S  1
-/** LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR : WT; bitpos: [2]; default: 0;
- *  clear usb wakeup to PMU.
- */
-#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR    (BIT(2))
-#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_M  (LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V << LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S)
-#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S  2
-/** LP_SYSTEM_REG_USBOTG20_IN_SUSPEND : R/W; bitpos: [3]; default: 0;
- *  indicate usb otg2.0 is in suspend state.
- */
-#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND    (BIT(3))
-#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_M  (LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V << LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S)
-#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V  0x00000001U
-#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S  3
-
-/** LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG (DR_REG_LP_SYS_BASE + 0x10c)
-/** LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP : R/W; bitpos: [7:0]; default: 255;
- *  Set 1 to power up pad group
- */
-#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP    0x000000FFU
-#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_M  (LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V << LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S)
-#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V  0x000000FFU
-#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S  0
-
-/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x110)
-/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN    (BIT(0))
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S)
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V  0x00000001U
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S  0
-/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT    (BIT(1))
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S)
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V  0x00000001U
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S  1
-
-/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x114)
-/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S)
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S  0
-
-/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x118)
-/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S)
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S  0
-
-/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x11c)
-/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN    (BIT(0))
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S)
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V  0x00000001U
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S  0
-/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT    (BIT(1))
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S)
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V  0x00000001U
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S  1
-
-/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x120)
-/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S)
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S  0
-
-/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x124)
-/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S)
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S  0
-
-/** LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0x130)
-/** LP_SYSTEM_REG_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  clock gate enable for hp cpu root 400M clk
- */
-#define LP_SYSTEM_REG_CPU_CLK_EN    (BIT(0))
-#define LP_SYSTEM_REG_CPU_CLK_EN_M  (LP_SYSTEM_REG_CPU_CLK_EN_V << LP_SYSTEM_REG_CPU_CLK_EN_S)
-#define LP_SYSTEM_REG_CPU_CLK_EN_V  0x00000001U
-#define LP_SYSTEM_REG_CPU_CLK_EN_S  0
-/** LP_SYSTEM_REG_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  clock gate enable for hp sys root 480M clk
- */
-#define LP_SYSTEM_REG_SYS_CLK_EN    (BIT(1))
-#define LP_SYSTEM_REG_SYS_CLK_EN_M  (LP_SYSTEM_REG_SYS_CLK_EN_V << LP_SYSTEM_REG_SYS_CLK_EN_S)
-#define LP_SYSTEM_REG_SYS_CLK_EN_V  0x00000001U
-#define LP_SYSTEM_REG_SYS_CLK_EN_S  1
-
-/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x138)
-/** LP_SYSTEM_REG_PMU_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW    0xFFFFFFFFU
-#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_M  (LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V << LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S)
-#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S  0
-
-/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x13c)
-/** LP_SYSTEM_REG_PMU_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH    0xFFFFFFFFU
-#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V << LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S)
-#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S  0
-
-/** LP_SYSTEM_REG_PAD_COMP0_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_PAD_COMP0_REG (DR_REG_LP_SYS_BASE + 0x148)
-/** LP_SYSTEM_REG_DREF_COMP0 : R/W; bitpos: [2:0]; default: 0;
- *  pad comp dref
- */
-#define LP_SYSTEM_REG_DREF_COMP0    0x00000007U
-#define LP_SYSTEM_REG_DREF_COMP0_M  (LP_SYSTEM_REG_DREF_COMP0_V << LP_SYSTEM_REG_DREF_COMP0_S)
-#define LP_SYSTEM_REG_DREF_COMP0_V  0x00000007U
-#define LP_SYSTEM_REG_DREF_COMP0_S  0
-/** LP_SYSTEM_REG_MODE_COMP0 : R/W; bitpos: [3]; default: 0;
- *  pad comp mode
- */
-#define LP_SYSTEM_REG_MODE_COMP0    (BIT(3))
-#define LP_SYSTEM_REG_MODE_COMP0_M  (LP_SYSTEM_REG_MODE_COMP0_V << LP_SYSTEM_REG_MODE_COMP0_S)
-#define LP_SYSTEM_REG_MODE_COMP0_V  0x00000001U
-#define LP_SYSTEM_REG_MODE_COMP0_S  3
-/** LP_SYSTEM_REG_XPD_COMP0 : R/W; bitpos: [4]; default: 0;
- *  pad comp xpd
- */
-#define LP_SYSTEM_REG_XPD_COMP0    (BIT(4))
-#define LP_SYSTEM_REG_XPD_COMP0_M  (LP_SYSTEM_REG_XPD_COMP0_V << LP_SYSTEM_REG_XPD_COMP0_S)
-#define LP_SYSTEM_REG_XPD_COMP0_V  0x00000001U
-#define LP_SYSTEM_REG_XPD_COMP0_S  4
-
-/** LP_SYSTEM_REG_PAD_COMP1_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_PAD_COMP1_REG (DR_REG_LP_SYS_BASE + 0x14c)
-/** LP_SYSTEM_REG_DREF_COMP1 : R/W; bitpos: [2:0]; default: 0;
- *  pad comp dref
- */
-#define LP_SYSTEM_REG_DREF_COMP1    0x00000007U
-#define LP_SYSTEM_REG_DREF_COMP1_M  (LP_SYSTEM_REG_DREF_COMP1_V << LP_SYSTEM_REG_DREF_COMP1_S)
-#define LP_SYSTEM_REG_DREF_COMP1_V  0x00000007U
-#define LP_SYSTEM_REG_DREF_COMP1_S  0
-/** LP_SYSTEM_REG_MODE_COMP1 : R/W; bitpos: [3]; default: 0;
- *  pad comp mode
- */
-#define LP_SYSTEM_REG_MODE_COMP1    (BIT(3))
-#define LP_SYSTEM_REG_MODE_COMP1_M  (LP_SYSTEM_REG_MODE_COMP1_V << LP_SYSTEM_REG_MODE_COMP1_S)
-#define LP_SYSTEM_REG_MODE_COMP1_V  0x00000001U
-#define LP_SYSTEM_REG_MODE_COMP1_S  3
-/** LP_SYSTEM_REG_XPD_COMP1 : R/W; bitpos: [4]; default: 0;
- *  pad comp xpd
- */
-#define LP_SYSTEM_REG_XPD_COMP1    (BIT(4))
-#define LP_SYSTEM_REG_XPD_COMP1_M  (LP_SYSTEM_REG_XPD_COMP1_V << LP_SYSTEM_REG_XPD_COMP1_S)
-#define LP_SYSTEM_REG_XPD_COMP1_V  0x00000001U
-#define LP_SYSTEM_REG_XPD_COMP1_S  4
-
-/** LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG (DR_REG_LP_SYS_BASE + 0x154)
-/** LP_SYSTEM_REG_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
- *  need_des
- */
-#define LP_SYSTEM_REG_BURST_LIMIT_AON    0x0000001FU
-#define LP_SYSTEM_REG_BURST_LIMIT_AON_M  (LP_SYSTEM_REG_BURST_LIMIT_AON_V << LP_SYSTEM_REG_BURST_LIMIT_AON_S)
-#define LP_SYSTEM_REG_BURST_LIMIT_AON_V  0x0000001FU
-#define LP_SYSTEM_REG_BURST_LIMIT_AON_S  0
-/** LP_SYSTEM_REG_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10;
- *  need_des
- */
-#define LP_SYSTEM_REG_READ_INTERVAL_AON    0x0000007FU
-#define LP_SYSTEM_REG_READ_INTERVAL_AON_M  (LP_SYSTEM_REG_READ_INTERVAL_AON_V << LP_SYSTEM_REG_READ_INTERVAL_AON_S)
-#define LP_SYSTEM_REG_READ_INTERVAL_AON_V  0x0000007FU
-#define LP_SYSTEM_REG_READ_INTERVAL_AON_S  5
-/** LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [21:12]; default: 100;
- *  need_des
- */
-#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON    0x000003FFU
-#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S)
-#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V  0x000003FFU
-#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S  12
-/** LP_SYSTEM_REG_LINK_TOUT_THRES_AON : R/W; bitpos: [31:22]; default: 100;
- *  need_des
- */
-#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON    0x000003FFU
-#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S)
-#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V  0x000003FFU
-#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S  22
-
-/** LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG (DR_REG_LP_SYS_BASE + 0x158)
-/** LP_SYSTEM_REG_AON_BYPASS : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_AON_BYPASS    (BIT(31))
-#define LP_SYSTEM_REG_AON_BYPASS_M  (LP_SYSTEM_REG_AON_BYPASS_V << LP_SYSTEM_REG_AON_BYPASS_S)
-#define LP_SYSTEM_REG_AON_BYPASS_V  0x00000001U
-#define LP_SYSTEM_REG_AON_BYPASS_S  31
-
-/** LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG (DR_REG_LP_SYS_BASE + 0x15c)
-/** LP_SYSTEM_REG_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LINK_ADDR_AON    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LINK_ADDR_AON_M  (LP_SYSTEM_REG_LINK_ADDR_AON_V << LP_SYSTEM_REG_LINK_ADDR_AON_S)
-#define LP_SYSTEM_REG_LINK_ADDR_AON_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LINK_ADDR_AON_S  0
-
-/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG (DR_REG_LP_SYS_BASE + 0x164)
-/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1    0xFFFFFFFFU
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V << LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S)
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S  0
-
-/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x168)
-/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S  0
-
-/** LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x16c)
-/** LP_SYSTEM_REG_LP_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
- *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
- *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
- *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ID    0x0000001FU
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ID_V << LP_SYSTEM_REG_LP_ADDRHOLE_ID_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_V  0x0000001FU
-#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_S  0
-/** LP_SYSTEM_REG_LP_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
- *  1:write trans, 0: read trans.
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_WR    (BIT(5))
-#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_WR_V << LP_SYSTEM_REG_LP_ADDRHOLE_WR_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_V  0x00000001U
-#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_S  5
-/** LP_SYSTEM_REG_LP_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
- *  1: illegal address access, 0: access without permission
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE    (BIT(6))
-#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V  0x00000001U
-#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S  6
-
-/** LP_SYSTEM_REG_INT_RAW_REG register
- *  raw interrupt register
- */
-#define LP_SYSTEM_REG_INT_RAW_REG (DR_REG_LP_SYS_BASE + 0x170)
-/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
- *  matrix default slave)
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW    (BIT(0))
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V  0x00000001U
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S  0
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW    (BIT(1))
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V  0x00000001U
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S  1
-/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  the raw interrupt status of lp core ahb bus timeout
- */
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW    (BIT(2))
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S)
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S  2
-/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
- *  the raw interrupt status of lp core  ibus timeout
- */
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW    (BIT(3))
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S)
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S  3
-/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
- *  the raw interrupt status of lp core  dbus timeout
- */
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW    (BIT(4))
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S)
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S  4
-/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
- *  the raw interrupt status of etm task ulp
- */
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW    (BIT(5))
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S)
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V  0x00000001U
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S  5
-/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
- *  the raw interrupt status of slow_clk_tick
- */
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW    (BIT(6))
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S)
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V  0x00000001U
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S  6
-
-/** LP_SYSTEM_REG_INT_ST_REG register
- *  masked interrupt register
- */
-#define LP_SYSTEM_REG_INT_ST_REG (DR_REG_LP_SYS_BASE + 0x174)
-/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST : RO; bitpos: [0]; default: 0;
- *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
- *  matrix default slave)
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST    (BIT(0))
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V  0x00000001U
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S  0
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
- *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST    (BIT(1))
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V  0x00000001U
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S  1
-/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
- *  the masked interrupt status of lp core ahb bus timeout
- */
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST    (BIT(2))
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S)
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S  2
-/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
- *  the masked interrupt status of lp core  ibus timeout
- */
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST    (BIT(3))
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S)
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S  3
-/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
- *  the masked interrupt status of lp core  dbus timeout
- */
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST    (BIT(4))
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S)
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S  4
-/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST : RO; bitpos: [5]; default: 0;
- *  the masked interrupt status of etm task ulp
- */
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST    (BIT(5))
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S)
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V  0x00000001U
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S  5
-/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST : RO; bitpos: [6]; default: 0;
- *  the masked interrupt status of slow_clk_tick
- */
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST    (BIT(6))
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S)
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V  0x00000001U
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S  6
-
-/** LP_SYSTEM_REG_INT_ENA_REG register
- *  masked interrupt register
- */
-#define LP_SYSTEM_REG_INT_ENA_REG (DR_REG_LP_SYS_BASE + 0x178)
-/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable lp addrhole int
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA    (BIT(0))
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V  0x00000001U
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S  0
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable idbus addrhole int
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA    (BIT(1))
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V  0x00000001U
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S  1
-/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable lp_core_ahb_timeout int
- */
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA    (BIT(2))
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S)
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S  2
-/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to enable lp_core_ibus_timeout int
- */
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA    (BIT(3))
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S)
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S  3
-/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Write 1 to enable lp_core_dbus_timeout int
- */
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA    (BIT(4))
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S)
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S  4
-/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to enable etm task ulp int
- */
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA    (BIT(5))
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S)
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V  0x00000001U
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S  5
-/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Write 1 to enable slow_clk_tick int
- */
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA    (BIT(6))
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S)
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V  0x00000001U
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S  6
-
-/** LP_SYSTEM_REG_INT_CLR_REG register
- *  interrupt clear register
- */
-#define LP_SYSTEM_REG_INT_CLR_REG (DR_REG_LP_SYS_BASE + 0x17c)
-/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  write 1 to clear lp addrhole int
- */
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR    (BIT(0))
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S)
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S  0
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  write 1 to clear idbus addrhole int
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR    (BIT(1))
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S  1
-/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear lp_core_ahb_timeout int
- */
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR    (BIT(2))
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S)
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S  2
-/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear lp_core_ibus_timeout int
- */
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR    (BIT(3))
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S)
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S  3
-/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear lp_core_dbus_timeout int
- */
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR    (BIT(4))
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S)
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S  4
-/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear etm tasl ulp int
- */
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR    (BIT(5))
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S)
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S  5
-/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear slow_clk_tick int
- */
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR    (BIT(6))
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S)
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V  0x00000001U
-#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S  6
-
-/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180)
-/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  need_des
- */
-#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL    0xFFFFFFFFU
-#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S)
-#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S  0
-
-/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184)
-/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S)
-#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S  0
-
-/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x188)
-/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
- *  need_des
- */
-#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL    0xFFFFFFFFU
-#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S)
-#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S  0
-
-/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x18c)
-/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S)
-#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S  0
-
-/** LP_SYSTEM_REG_LP_CPU_DBG_PC_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CPU_DBG_PC_REG (DR_REG_LP_SYS_BASE + 0x190)
-/** LP_SYSTEM_REG_LP_CPU_DBG_PC : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CPU_DBG_PC    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_CPU_DBG_PC_M  (LP_SYSTEM_REG_LP_CPU_DBG_PC_V << LP_SYSTEM_REG_LP_CPU_DBG_PC_S)
-#define LP_SYSTEM_REG_LP_CPU_DBG_PC_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_CPU_DBG_PC_S  0
-
-/** LP_SYSTEM_REG_LP_CPU_EXC_PC_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CPU_EXC_PC_REG (DR_REG_LP_SYS_BASE + 0x194)
-/** LP_SYSTEM_REG_LP_CPU_EXC_PC : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CPU_EXC_PC    0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_CPU_EXC_PC_M  (LP_SYSTEM_REG_LP_CPU_EXC_PC_V << LP_SYSTEM_REG_LP_CPU_EXC_PC_S)
-#define LP_SYSTEM_REG_LP_CPU_EXC_PC_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_LP_CPU_EXC_PC_S  0
-
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x198)
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR    0xFFFFFFFFU
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S  0
-
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x19c)
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID    0x0000001FU
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V  0x0000001FU
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S  0
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR    (BIT(5))
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V  0x00000001U
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S  5
-/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE    (BIT(6))
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S)
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V  0x00000001U
-#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S  6
-
-/** LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1a0)
-/** LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL : R/W; bitpos: [15:8]; default: 255;
- *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
- *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
- *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
- *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
- *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
- *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
- *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
- *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
- */
-#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL    0x000000FFU
-#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S)
-#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V  0x000000FFU
-#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S  8
-/** LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL : R/W; bitpos: [31:24]; default: 255;
- *  [31] 1'b1: po_rstn bypass sys_sw_rstn
- *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
- *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
- *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
- *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
- *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
- *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
- *  [24] 1'b1: po_rstn bypass efuse_err_rstn
- */
-#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL    0x000000FFU
-#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S)
-#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V  0x000000FFU
-#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S  24
-
-/** LP_SYSTEM_REG_RNG_DATA_REG register
- *  rng data register
- */
-#define LP_SYSTEM_REG_RNG_DATA_REG (DR_REG_LP_SYS_BASE + 0x1a4)
-/** LP_SYSTEM_REG_RND_DATA : RO; bitpos: [31:0]; default: 0;
- *  result of rng output
- */
-#define LP_SYSTEM_REG_RND_DATA    0xFFFFFFFFU
-#define LP_SYSTEM_REG_RND_DATA_M  (LP_SYSTEM_REG_RND_DATA_V << LP_SYSTEM_REG_RND_DATA_S)
-#define LP_SYSTEM_REG_RND_DATA_V  0xFFFFFFFFU
-#define LP_SYSTEM_REG_RND_DATA_S  0
-
-/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b0)
-/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable lp core ahb timeout handle
- */
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN    (BIT(0))
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S)
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S  0
-/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set lp core ahb bus timeout  threshold
- */
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S)
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
-#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S  1
-/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN : R/W; bitpos: [17]; default: 1;
- *  set this field to 1 to enable lp2hp ahb timeout handle
- */
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN    (BIT(17))
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S)
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V  0x00000001U
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S  17
-/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES : R/W; bitpos: [22:18]; default: 31;
- *  This field used to set lp2hp ahb bus timeout  threshold
- */
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES    0x0000001FU
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S)
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V  0x0000001FU
-#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S  18
-
-/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b4)
-/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable lp core ibus timeout handle
- */
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN    (BIT(0))
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S)
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S  0
-/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set lp core ibus timeout  threshold
- */
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S)
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
-#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S  1
-
-/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b8)
-/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable lp core dbus timeout handle
- */
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN    (BIT(0))
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S)
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S  0
-/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set lp core dbus timeout  threshold
- */
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S)
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
-#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S  1
-
-/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG register
- *  need_des
- */
-#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG (DR_REG_LP_SYS_BASE + 0x1bc)
-/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
- *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
- *  disable ahb err resp.
- */
-#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS    0x00000007U
-#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_M  (LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V << LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S)
-#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V  0x00000007U
-#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S  0
-
-/** LP_SYSTEM_REG_RNG_CFG_REG register
- *  rng cfg register
- */
-#define LP_SYSTEM_REG_RNG_CFG_REG (DR_REG_LP_SYS_BASE + 0x1c0)
-/** LP_SYSTEM_REG_RNG_TIMER_EN : R/W; bitpos: [0]; default: 1;
- *  enable rng timer
- */
-#define LP_SYSTEM_REG_RNG_TIMER_EN    (BIT(0))
-#define LP_SYSTEM_REG_RNG_TIMER_EN_M  (LP_SYSTEM_REG_RNG_TIMER_EN_V << LP_SYSTEM_REG_RNG_TIMER_EN_S)
-#define LP_SYSTEM_REG_RNG_TIMER_EN_V  0x00000001U
-#define LP_SYSTEM_REG_RNG_TIMER_EN_S  0
-/** LP_SYSTEM_REG_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 1;
- *  configure ng timer pscale
- */
-#define LP_SYSTEM_REG_RNG_TIMER_PSCALE    0x000000FFU
-#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_M  (LP_SYSTEM_REG_RNG_TIMER_PSCALE_V << LP_SYSTEM_REG_RNG_TIMER_PSCALE_S)
-#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_V  0x000000FFU
-#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_S  1
-/** LP_SYSTEM_REG_RNG_SAR_ENABLE : R/W; bitpos: [9]; default: 0;
- *  enable rng_saradc
- */
-#define LP_SYSTEM_REG_RNG_SAR_ENABLE    (BIT(9))
-#define LP_SYSTEM_REG_RNG_SAR_ENABLE_M  (LP_SYSTEM_REG_RNG_SAR_ENABLE_V << LP_SYSTEM_REG_RNG_SAR_ENABLE_S)
-#define LP_SYSTEM_REG_RNG_SAR_ENABLE_V  0x00000001U
-#define LP_SYSTEM_REG_RNG_SAR_ENABLE_S  9
-/** LP_SYSTEM_REG_RNG_SAR_DATA : RO; bitpos: [28:16]; default: 0;
- *  debug rng sar sample cnt
- */
-#define LP_SYSTEM_REG_RNG_SAR_DATA    0x00001FFFU
-#define LP_SYSTEM_REG_RNG_SAR_DATA_M  (LP_SYSTEM_REG_RNG_SAR_DATA_V << LP_SYSTEM_REG_RNG_SAR_DATA_S)
-#define LP_SYSTEM_REG_RNG_SAR_DATA_V  0x00001FFFU
-#define LP_SYSTEM_REG_RNG_SAR_DATA_S  16
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_sys_struct.h b/components/soc/esp32p4/include/soc/lp_sys_struct.h
deleted file mode 100644
index f54c249eec..0000000000
--- a/components/soc/esp32p4/include/soc/lp_sys_struct.h
+++ /dev/null
@@ -1,1333 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of lp_sys_ver_date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ver_date : R/W; bitpos: [31:0]; default: 539165961;
-         *  need_des
-         */
-        uint32_t ver_date:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_sys_ver_date_reg_t;
-
-/** Type of clk_sel_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** ena_sw_sel_sys_clk : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t ena_sw_sel_sys_clk:1;
-        /** sw_sys_clk_src_sel : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t sw_sys_clk_src_sel:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} lp_system_reg_clk_sel_ctrl_reg_t;
-
-/** Type of sys_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_core_disable : R/W; bitpos: [0]; default: 0;
-         *  lp cpu disable
-         */
-        uint32_t lp_core_disable:1;
-        /** sys_sw_rst : WT; bitpos: [1]; default: 0;
-         *  digital system software reset bit
-         */
-        uint32_t sys_sw_rst:1;
-        /** force_download_boot : R/W; bitpos: [2]; default: 0;
-         *  need_des
-         */
-        uint32_t force_download_boot:1;
-        /** dig_fib : R/W; bitpos: [10:3]; default: 255;
-         *  need_des
-         */
-        uint32_t dig_fib:8;
-        /** io_mux_reset_disable : R/W; bitpos: [11]; default: 0;
-         *  reset disable bit for LP IOMUX
-         */
-        uint32_t io_mux_reset_disable:1;
-        uint32_t reserved_12:2;
-        /** ana_fib : RO; bitpos: [20:14]; default: 127;
-         *  need_des
-         */
-        uint32_t ana_fib:7;
-        /** lp_fib_sel : R/W; bitpos: [28:21]; default: 255;
-         *  need_des
-         */
-        uint32_t lp_fib_sel:8;
-        /** lp_core_etm_wakeup_flag_clr : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_core_etm_wakeup_flag_clr:1;
-        /** lp_core_etm_wakeup_flag : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_core_etm_wakeup_flag:1;
-        /** systimer_stall_sel : R/W; bitpos: [31]; default: 0;
-         *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
-         *  hp_core1
-         */
-        uint32_t systimer_stall_sel:1;
-    };
-    uint32_t val;
-} lp_system_reg_sys_ctrl_reg_t;
-
-/** Type of lp_clk_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:13;
-        /** lp_fosc_hp_cken : R/W; bitpos: [14]; default: 1;
-         *  reserved
-         */
-        uint32_t lp_fosc_hp_cken:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_system_reg_lp_clk_ctrl_reg_t;
-
-/** Type of lp_rst_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ana_rst_bypass : R/W; bitpos: [0]; default: 1;
-         *  analog source reset bypass : wdt,brown out,super wdt,glitch
-         */
-        uint32_t ana_rst_bypass:1;
-        /** sys_rst_bypass : R/W; bitpos: [1]; default: 1;
-         *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
-         */
-        uint32_t sys_rst_bypass:1;
-        /** efuse_force_norst : R/W; bitpos: [2]; default: 0;
-         *  efuse force no reset control
-         */
-        uint32_t efuse_force_norst:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} lp_system_reg_lp_rst_ctrl_reg_t;
-
-/** Type of lp_core_boot_addr register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_cpu_boot_addr : R/W; bitpos: [31:0]; default: 1343225856;
-         *  need_des
-         */
-        uint32_t lp_cpu_boot_addr:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_core_boot_addr_reg_t;
-
-/** Type of ext_wakeup1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ext_wakeup1_sel : R/W; bitpos: [15:0]; default: 0;
-         *  Bitmap to select RTC pads for ext wakeup1
-         */
-        uint32_t ext_wakeup1_sel:16;
-        /** ext_wakeup1_status_clr : WT; bitpos: [16]; default: 0;
-         *  clear ext wakeup1 status
-         */
-        uint32_t ext_wakeup1_status_clr:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_system_reg_ext_wakeup1_reg_t;
-
-/** Type of ext_wakeup1_status register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ext_wakeup1_status : RO; bitpos: [15:0]; default: 0;
-         *  ext wakeup1 status
-         */
-        uint32_t ext_wakeup1_status:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_system_reg_ext_wakeup1_status_reg_t;
-
-/** Type of lp_tcm_pwr_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** lp_tcm_rom_clk_force_on : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_rom_clk_force_on:1;
-        uint32_t reserved_6:1;
-        /** lp_tcm_ram_clk_force_on : R/W; bitpos: [7]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_ram_clk_force_on:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_system_reg_lp_tcm_pwr_ctrl_reg_t;
-
-/** Type of boot_addr_hp_lp_reg register
- *  need_des
- */
-typedef union {
-    struct {
-        /** boot_addr_hp_lp : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t boot_addr_hp_lp:32;
-    };
-    uint32_t val;
-} lp_system_reg_boot_addr_hp_lp_reg_reg_t;
-
-/** Type of lp_store0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch0 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch0:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store0_reg_t;
-
-/** Type of lp_store1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch1 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch1:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store1_reg_t;
-
-/** Type of lp_store2 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch2 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch2:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store2_reg_t;
-
-/** Type of lp_store3 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch3 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch3:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store3_reg_t;
-
-/** Type of lp_store4 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch4 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch4:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store4_reg_t;
-
-/** Type of lp_store5 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch5 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch5:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store5_reg_t;
-
-/** Type of lp_store6 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch6 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch6:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store6_reg_t;
-
-/** Type of lp_store7 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch7 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch7:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store7_reg_t;
-
-/** Type of lp_store8 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch8 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch8:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store8_reg_t;
-
-/** Type of lp_store9 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch9 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch9:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store9_reg_t;
-
-/** Type of lp_store10 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch10 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch10:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store10_reg_t;
-
-/** Type of lp_store11 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch11 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch11:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store11_reg_t;
-
-/** Type of lp_store12 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch12 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch12:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store12_reg_t;
-
-/** Type of lp_store13 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch13 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch13:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store13_reg_t;
-
-/** Type of lp_store14 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch14 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch14:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store14_reg_t;
-
-/** Type of lp_store15 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_scratch15 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_scratch15:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_store15_reg_t;
-
-/** Type of lp_probea_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_a_mod_sel:16;
-        /** probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_a_top_sel:8;
-        /** probe_l_sel : R/W; bitpos: [25:24]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_l_sel:2;
-        /** probe_h_sel : R/W; bitpos: [27:26]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_h_sel:2;
-        /** probe_global_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_global_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} lp_system_reg_lp_probea_ctrl_reg_t;
-
-/** Type of lp_probeb_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_b_mod_sel:16;
-        /** probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_b_top_sel:8;
-        /** probe_b_en : R/W; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_b_en:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} lp_system_reg_lp_probeb_ctrl_reg_t;
-
-/** Type of lp_probe_out register
- *  need_des
- */
-typedef union {
-    struct {
-        /** probe_top_out : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t probe_top_out:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_probe_out_reg_t;
-
-/** Type of f2s_apb_brg_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** f2s_apb_postw_en : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t f2s_apb_postw_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_system_reg_f2s_apb_brg_cntl_reg_t;
-
-/** Type of usb_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** sw_hw_usb_phy_sel : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t sw_hw_usb_phy_sel:1;
-        /** sw_usb_phy_sel : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t sw_usb_phy_sel:1;
-        /** usbotg20_wakeup_clr : WT; bitpos: [2]; default: 0;
-         *  clear usb wakeup to PMU.
-         */
-        uint32_t usbotg20_wakeup_clr:1;
-        /** usbotg20_in_suspend : R/W; bitpos: [3]; default: 0;
-         *  indicate usb otg2.0 is in suspend state.
-         */
-        uint32_t usbotg20_in_suspend:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_system_reg_usb_ctrl_reg_t;
-
-/** Type of ana_xpd_pad_group register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ana_reg_xpd_pad_group : R/W; bitpos: [7:0]; default: 255;
-         *  Set 1 to power up pad group
-         */
-        uint32_t ana_reg_xpd_pad_group:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_system_reg_ana_xpd_pad_group_reg_t;
-
-/** Type of lp_tcm_ram_rdn_eco_cs register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_tcm_ram_rdn_eco_en : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_ram_rdn_eco_en:1;
-        /** lp_tcm_ram_rdn_eco_result : RO; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_ram_rdn_eco_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t;
-
-/** Type of lp_tcm_ram_rdn_eco_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_tcm_ram_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_ram_rdn_eco_low:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t;
-
-/** Type of lp_tcm_ram_rdn_eco_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_tcm_ram_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t lp_tcm_ram_rdn_eco_high:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t;
-
-/** Type of lp_tcm_rom_rdn_eco_cs register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_tcm_rom_rdn_eco_en : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_rom_rdn_eco_en:1;
-        /** lp_tcm_rom_rdn_eco_result : RO; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_rom_rdn_eco_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t;
-
-/** Type of lp_tcm_rom_rdn_eco_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_tcm_rom_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_tcm_rom_rdn_eco_low:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t;
-
-/** Type of lp_tcm_rom_rdn_eco_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_tcm_rom_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t lp_tcm_rom_rdn_eco_high:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t;
-
-/** Type of hp_root_clk_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** cpu_clk_en : R/W; bitpos: [0]; default: 1;
-         *  clock gate enable for hp cpu root 400M clk
-         */
-        uint32_t cpu_clk_en:1;
-        /** sys_clk_en : R/W; bitpos: [1]; default: 1;
-         *  clock gate enable for hp sys root 480M clk
-         */
-        uint32_t sys_clk_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_system_reg_hp_root_clk_ctrl_reg_t;
-
-/** Type of lp_pmu_rdn_eco_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** pmu_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t pmu_rdn_eco_low:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_pmu_rdn_eco_low_reg_t;
-
-/** Type of lp_pmu_rdn_eco_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** pmu_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t pmu_rdn_eco_high:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_pmu_rdn_eco_high_reg_t;
-
-/** Type of pad_comp0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** dref_comp0 : R/W; bitpos: [2:0]; default: 0;
-         *  pad comp dref
-         */
-        uint32_t dref_comp0:3;
-        /** mode_comp0 : R/W; bitpos: [3]; default: 0;
-         *  pad comp mode
-         */
-        uint32_t mode_comp0:1;
-        /** xpd_comp0 : R/W; bitpos: [4]; default: 0;
-         *  pad comp xpd
-         */
-        uint32_t xpd_comp0:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lp_system_reg_pad_comp0_reg_t;
-
-/** Type of pad_comp1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** dref_comp1 : R/W; bitpos: [2:0]; default: 0;
-         *  pad comp dref
-         */
-        uint32_t dref_comp1:3;
-        /** mode_comp1 : R/W; bitpos: [3]; default: 0;
-         *  pad comp mode
-         */
-        uint32_t mode_comp1:1;
-        /** xpd_comp1 : R/W; bitpos: [4]; default: 0;
-         *  pad comp xpd
-         */
-        uint32_t xpd_comp1:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lp_system_reg_pad_comp1_reg_t;
-
-/** Type of backup_dma_cfg0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** burst_limit_aon : R/W; bitpos: [4:0]; default: 10;
-         *  need_des
-         */
-        uint32_t burst_limit_aon:5;
-        /** read_interval_aon : R/W; bitpos: [11:5]; default: 10;
-         *  need_des
-         */
-        uint32_t read_interval_aon:7;
-        /** link_backup_tout_thres_aon : R/W; bitpos: [21:12]; default: 100;
-         *  need_des
-         */
-        uint32_t link_backup_tout_thres_aon:10;
-        /** link_tout_thres_aon : R/W; bitpos: [31:22]; default: 100;
-         *  need_des
-         */
-        uint32_t link_tout_thres_aon:10;
-    };
-    uint32_t val;
-} lp_system_reg_backup_dma_cfg0_reg_t;
-
-/** Type of backup_dma_cfg1 register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** aon_bypass : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t aon_bypass:1;
-    };
-    uint32_t val;
-} lp_system_reg_backup_dma_cfg1_reg_t;
-
-/** Type of backup_dma_cfg2 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** link_addr_aon : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t link_addr_aon:32;
-    };
-    uint32_t val;
-} lp_system_reg_backup_dma_cfg2_reg_t;
-
-/** Type of boot_addr_hp_core1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** boot_addr_hp_core1 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t boot_addr_hp_core1:32;
-    };
-    uint32_t val;
-} lp_system_reg_boot_addr_hp_core1_reg_t;
-
-/** Type of hp_mem_aux_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
-         *  need_des
-         */
-        uint32_t hp_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} lp_system_reg_hp_mem_aux_ctrl_reg_t;
-
-/** Type of lp_mem_aux_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
-         *  need_des
-         */
-        uint32_t lp_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_mem_aux_ctrl_reg_t;
-
-/** Type of hp_rom_aux_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
-         *  need_des
-         */
-        uint32_t hp_rom_aux_ctrl:32;
-    };
-    uint32_t val;
-} lp_system_reg_hp_rom_aux_ctrl_reg_t;
-
-/** Type of lp_rom_aux_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
-         *  need_des
-         */
-        uint32_t lp_rom_aux_ctrl:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_rom_aux_ctrl_reg_t;
-
-/** Type of hp_por_rst_bypass_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** hp_po_cnnt_rstn_bypass_ctrl : R/W; bitpos: [15:8]; default: 255;
-         *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
-         *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
-         *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
-         *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
-         *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
-         *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
-         *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
-         *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
-         */
-        uint32_t hp_po_cnnt_rstn_bypass_ctrl:8;
-        uint32_t reserved_16:8;
-        /** hp_po_rstn_bypass_ctrl : R/W; bitpos: [31:24]; default: 255;
-         *  [31] 1'b1: po_rstn bypass sys_sw_rstn
-         *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
-         *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
-         *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
-         *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
-         *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
-         *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
-         *  [24] 1'b1: po_rstn bypass efuse_err_rstn
-         */
-        uint32_t hp_po_rstn_bypass_ctrl:8;
-    };
-    uint32_t val;
-} lp_system_reg_hp_por_rst_bypass_ctrl_reg_t;
-
-/** Type of lp_core_ahb_timeout register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_core_ahb_timeout_en : R/W; bitpos: [0]; default: 1;
-         *  set this field to 1 to enable lp core ahb timeout handle
-         */
-        uint32_t lp_core_ahb_timeout_en:1;
-        /** lp_core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
-         *  This field used to set lp core ahb bus timeout  threshold
-         */
-        uint32_t lp_core_ahb_timeout_thres:16;
-        /** lp2hp_ahb_timeout_en : R/W; bitpos: [17]; default: 1;
-         *  set this field to 1 to enable lp2hp ahb timeout handle
-         */
-        uint32_t lp2hp_ahb_timeout_en:1;
-        /** lp2hp_ahb_timeout_thres : R/W; bitpos: [22:18]; default: 31;
-         *  This field used to set lp2hp ahb bus timeout  threshold
-         */
-        uint32_t lp2hp_ahb_timeout_thres:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_system_reg_lp_core_ahb_timeout_reg_t;
-
-/** Type of lp_core_ibus_timeout register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_core_ibus_timeout_en : R/W; bitpos: [0]; default: 1;
-         *  set this field to 1 to enable lp core ibus timeout handle
-         */
-        uint32_t lp_core_ibus_timeout_en:1;
-        /** lp_core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
-         *  This field used to set lp core ibus timeout  threshold
-         */
-        uint32_t lp_core_ibus_timeout_thres:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_system_reg_lp_core_ibus_timeout_reg_t;
-
-/** Type of lp_core_dbus_timeout register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_core_dbus_timeout_en : R/W; bitpos: [0]; default: 1;
-         *  set this field to 1 to enable lp core dbus timeout handle
-         */
-        uint32_t lp_core_dbus_timeout_en:1;
-        /** lp_core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
-         *  This field used to set lp core dbus timeout  threshold
-         */
-        uint32_t lp_core_dbus_timeout_thres:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_system_reg_lp_core_dbus_timeout_reg_t;
-
-
-/** Group: status_register */
-/** Type of lp_addrhole_addr register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_addrhole_addr : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_addrhole_addr:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_addrhole_addr_reg_t;
-
-/** Type of lp_addrhole_info register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_addrhole_id : RO; bitpos: [4:0]; default: 0;
-         *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
-         *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
-         *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
-         */
-        uint32_t lp_addrhole_id:5;
-        /** lp_addrhole_wr : RO; bitpos: [5]; default: 0;
-         *  1:write trans, 0: read trans.
-         */
-        uint32_t lp_addrhole_wr:1;
-        /** lp_addrhole_secure : RO; bitpos: [6]; default: 0;
-         *  1: illegal address access, 0: access without permission
-         */
-        uint32_t lp_addrhole_secure:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_system_reg_lp_addrhole_info_reg_t;
-
-/** Type of lp_cpu_dbg_pc register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_cpu_dbg_pc : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_dbg_pc:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_cpu_dbg_pc_reg_t;
-
-/** Type of lp_cpu_exc_pc register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_cpu_exc_pc : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_exc_pc:32;
-    };
-    uint32_t val;
-} lp_system_reg_lp_cpu_exc_pc_reg_t;
-
-/** Type of idbus_addrhole_addr register
- *  need_des
- */
-typedef union {
-    struct {
-        /** idbus_addrhole_addr : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t idbus_addrhole_addr:32;
-    };
-    uint32_t val;
-} lp_system_reg_idbus_addrhole_addr_reg_t;
-
-/** Type of idbus_addrhole_info register
- *  need_des
- */
-typedef union {
-    struct {
-        /** idbus_addrhole_id : RO; bitpos: [4:0]; default: 0;
-         *  need_des
-         */
-        uint32_t idbus_addrhole_id:5;
-        /** idbus_addrhole_wr : RO; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t idbus_addrhole_wr:1;
-        /** idbus_addrhole_secure : RO; bitpos: [6]; default: 0;
-         *  need_des
-         */
-        uint32_t idbus_addrhole_secure:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_system_reg_idbus_addrhole_info_reg_t;
-
-/** Type of rng_data register
- *  rng data register
- */
-typedef union {
-    struct {
-        /** rnd_data : RO; bitpos: [31:0]; default: 0;
-         *  result of rng output
-         */
-        uint32_t rnd_data:32;
-    };
-    uint32_t val;
-} lp_system_reg_rng_data_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_raw register
- *  raw interrupt register
- */
-typedef union {
-    struct {
-        /** lp_addrhole_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
-         *  matrix default slave)
-         */
-        uint32_t lp_addrhole_int_raw:1;
-        /** idbus_addrhole_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
-         */
-        uint32_t idbus_addrhole_int_raw:1;
-        /** lp_core_ahb_timeout_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  the raw interrupt status of lp core ahb bus timeout
-         */
-        uint32_t lp_core_ahb_timeout_int_raw:1;
-        /** lp_core_ibus_timeout_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
-         *  the raw interrupt status of lp core  ibus timeout
-         */
-        uint32_t lp_core_ibus_timeout_int_raw:1;
-        /** lp_core_dbus_timeout_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
-         *  the raw interrupt status of lp core  dbus timeout
-         */
-        uint32_t lp_core_dbus_timeout_int_raw:1;
-        /** etm_task_ulp_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
-         *  the raw interrupt status of etm task ulp
-         */
-        uint32_t etm_task_ulp_int_raw:1;
-        /** slow_clk_tick_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
-         *  the raw interrupt status of slow_clk_tick
-         */
-        uint32_t slow_clk_tick_int_raw:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_system_reg_int_raw_reg_t;
-
-/** Type of int_st register
- *  masked interrupt register
- */
-typedef union {
-    struct {
-        /** lp_addrhole_int_st : RO; bitpos: [0]; default: 0;
-         *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
-         *  matrix default slave)
-         */
-        uint32_t lp_addrhole_int_st:1;
-        /** idbus_addrhole_int_st : RO; bitpos: [1]; default: 0;
-         *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
-         */
-        uint32_t idbus_addrhole_int_st:1;
-        /** lp_core_ahb_timeout_int_st : RO; bitpos: [2]; default: 0;
-         *  the masked interrupt status of lp core ahb bus timeout
-         */
-        uint32_t lp_core_ahb_timeout_int_st:1;
-        /** lp_core_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
-         *  the masked interrupt status of lp core  ibus timeout
-         */
-        uint32_t lp_core_ibus_timeout_int_st:1;
-        /** lp_core_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
-         *  the masked interrupt status of lp core  dbus timeout
-         */
-        uint32_t lp_core_dbus_timeout_int_st:1;
-        /** etm_task_ulp_int_st : RO; bitpos: [5]; default: 0;
-         *  the masked interrupt status of etm task ulp
-         */
-        uint32_t etm_task_ulp_int_st:1;
-        /** slow_clk_tick_int_st : RO; bitpos: [6]; default: 0;
-         *  the masked interrupt status of slow_clk_tick
-         */
-        uint32_t slow_clk_tick_int_st:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_system_reg_int_st_reg_t;
-
-/** Type of int_ena register
- *  masked interrupt register
- */
-typedef union {
-    struct {
-        /** lp_addrhole_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable lp addrhole int
-         */
-        uint32_t lp_addrhole_int_ena:1;
-        /** idbus_addrhole_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable idbus addrhole int
-         */
-        uint32_t idbus_addrhole_int_ena:1;
-        /** lp_core_ahb_timeout_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable lp_core_ahb_timeout int
-         */
-        uint32_t lp_core_ahb_timeout_int_ena:1;
-        /** lp_core_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable lp_core_ibus_timeout int
-         */
-        uint32_t lp_core_ibus_timeout_int_ena:1;
-        /** lp_core_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to enable lp_core_dbus_timeout int
-         */
-        uint32_t lp_core_dbus_timeout_int_ena:1;
-        /** etm_task_ulp_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable etm task ulp int
-         */
-        uint32_t etm_task_ulp_int_ena:1;
-        /** slow_clk_tick_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to enable slow_clk_tick int
-         */
-        uint32_t slow_clk_tick_int_ena:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_system_reg_int_ena_reg_t;
-
-/** Type of int_clr register
- *  interrupt clear register
- */
-typedef union {
-    struct {
-        /** lp_addrhole_int_clr : WT; bitpos: [0]; default: 0;
-         *  write 1 to clear lp addrhole int
-         */
-        uint32_t lp_addrhole_int_clr:1;
-        /** idbus_addrhole_int_clr : WT; bitpos: [1]; default: 0;
-         *  write 1 to clear idbus addrhole int
-         */
-        uint32_t idbus_addrhole_int_clr:1;
-        /** lp_core_ahb_timeout_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear lp_core_ahb_timeout int
-         */
-        uint32_t lp_core_ahb_timeout_int_clr:1;
-        /** lp_core_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear lp_core_ibus_timeout int
-         */
-        uint32_t lp_core_ibus_timeout_int_clr:1;
-        /** lp_core_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear lp_core_dbus_timeout int
-         */
-        uint32_t lp_core_dbus_timeout_int_clr:1;
-        /** etm_task_ulp_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear etm tasl ulp int
-         */
-        uint32_t etm_task_ulp_int_clr:1;
-        /** slow_clk_tick_int_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear slow_clk_tick int
-         */
-        uint32_t slow_clk_tick_int_clr:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_system_reg_int_clr_reg_t;
-
-
-/** Group: control registers */
-/** Type of lp_core_err_resp_dis register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
-         *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
-         *  disable ahb err resp.
-         */
-        uint32_t lp_core_err_resp_dis:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} lp_system_reg_lp_core_err_resp_dis_reg_t;
-
-/** Type of rng_cfg register
- *  rng cfg register
- */
-typedef union {
-    struct {
-        /** rng_timer_en : R/W; bitpos: [0]; default: 1;
-         *  enable rng timer
-         */
-        uint32_t rng_timer_en:1;
-        /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 1;
-         *  configure ng timer pscale
-         */
-        uint32_t rng_timer_pscale:8;
-        /** rng_sar_enable : R/W; bitpos: [9]; default: 0;
-         *  enable rng_saradc
-         */
-        uint32_t rng_sar_enable:1;
-        uint32_t reserved_10:6;
-        /** rng_sar_data : RO; bitpos: [28:16]; default: 0;
-         *  debug rng sar sample cnt
-         */
-        uint32_t rng_sar_data:13;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} lp_system_reg_rng_cfg_reg_t;
-
-
-typedef struct {
-    volatile lp_system_reg_lp_sys_ver_date_reg_t lp_sys_ver_date;
-    volatile lp_system_reg_clk_sel_ctrl_reg_t clk_sel_ctrl;
-    volatile lp_system_reg_sys_ctrl_reg_t sys_ctrl;
-    volatile lp_system_reg_lp_clk_ctrl_reg_t lp_clk_ctrl;
-    volatile lp_system_reg_lp_rst_ctrl_reg_t lp_rst_ctrl;
-    uint32_t reserved_014;
-    volatile lp_system_reg_lp_core_boot_addr_reg_t lp_core_boot_addr;
-    volatile lp_system_reg_ext_wakeup1_reg_t ext_wakeup1;
-    volatile lp_system_reg_ext_wakeup1_status_reg_t ext_wakeup1_status;
-    volatile lp_system_reg_lp_tcm_pwr_ctrl_reg_t lp_tcm_pwr_ctrl;
-    volatile lp_system_reg_boot_addr_hp_lp_reg_reg_t boot_addr_hp_lp_reg;
-    volatile lp_system_reg_lp_store0_reg_t lp_store0;
-    volatile lp_system_reg_lp_store1_reg_t lp_store1;
-    volatile lp_system_reg_lp_store2_reg_t lp_store2;
-    volatile lp_system_reg_lp_store3_reg_t lp_store3;
-    volatile lp_system_reg_lp_store4_reg_t lp_store4;
-    volatile lp_system_reg_lp_store5_reg_t lp_store5;
-    volatile lp_system_reg_lp_store6_reg_t lp_store6;
-    volatile lp_system_reg_lp_store7_reg_t lp_store7;
-    volatile lp_system_reg_lp_store8_reg_t lp_store8;
-    volatile lp_system_reg_lp_store9_reg_t lp_store9;
-    volatile lp_system_reg_lp_store10_reg_t lp_store10;
-    volatile lp_system_reg_lp_store11_reg_t lp_store11;
-    volatile lp_system_reg_lp_store12_reg_t lp_store12;
-    volatile lp_system_reg_lp_store13_reg_t lp_store13;
-    volatile lp_system_reg_lp_store14_reg_t lp_store14;
-    volatile lp_system_reg_lp_store15_reg_t lp_store15;
-    volatile lp_system_reg_lp_probea_ctrl_reg_t lp_probea_ctrl;
-    volatile lp_system_reg_lp_probeb_ctrl_reg_t lp_probeb_ctrl;
-    volatile lp_system_reg_lp_probe_out_reg_t lp_probe_out;
-    uint32_t reserved_078[9];
-    volatile lp_system_reg_f2s_apb_brg_cntl_reg_t f2s_apb_brg_cntl;
-    uint32_t reserved_0a0[24];
-    volatile lp_system_reg_usb_ctrl_reg_t usb_ctrl;
-    uint32_t reserved_104[2];
-    volatile lp_system_reg_ana_xpd_pad_group_reg_t ana_xpd_pad_group;
-    volatile lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t lp_tcm_ram_rdn_eco_cs;
-    volatile lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t lp_tcm_ram_rdn_eco_low;
-    volatile lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t lp_tcm_ram_rdn_eco_high;
-    volatile lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t lp_tcm_rom_rdn_eco_cs;
-    volatile lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t lp_tcm_rom_rdn_eco_low;
-    volatile lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t lp_tcm_rom_rdn_eco_high;
-    uint32_t reserved_128[2];
-    volatile lp_system_reg_hp_root_clk_ctrl_reg_t hp_root_clk_ctrl;
-    uint32_t reserved_134;
-    volatile lp_system_reg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low;
-    volatile lp_system_reg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high;
-    uint32_t reserved_140[2];
-    volatile lp_system_reg_pad_comp0_reg_t pad_comp0;
-    volatile lp_system_reg_pad_comp1_reg_t pad_comp1;
-    uint32_t reserved_150;
-    volatile lp_system_reg_backup_dma_cfg0_reg_t backup_dma_cfg0;
-    volatile lp_system_reg_backup_dma_cfg1_reg_t backup_dma_cfg1;
-    volatile lp_system_reg_backup_dma_cfg2_reg_t backup_dma_cfg2;
-    uint32_t reserved_160;
-    volatile lp_system_reg_boot_addr_hp_core1_reg_t boot_addr_hp_core1;
-    volatile lp_system_reg_lp_addrhole_addr_reg_t lp_addrhole_addr;
-    volatile lp_system_reg_lp_addrhole_info_reg_t lp_addrhole_info;
-    volatile lp_system_reg_int_raw_reg_t int_raw;
-    volatile lp_system_reg_int_st_reg_t int_st;
-    volatile lp_system_reg_int_ena_reg_t int_ena;
-    volatile lp_system_reg_int_clr_reg_t int_clr;
-    volatile lp_system_reg_hp_mem_aux_ctrl_reg_t hp_mem_aux_ctrl;
-    volatile lp_system_reg_lp_mem_aux_ctrl_reg_t lp_mem_aux_ctrl;
-    volatile lp_system_reg_hp_rom_aux_ctrl_reg_t hp_rom_aux_ctrl;
-    volatile lp_system_reg_lp_rom_aux_ctrl_reg_t lp_rom_aux_ctrl;
-    volatile lp_system_reg_lp_cpu_dbg_pc_reg_t lp_cpu_dbg_pc;
-    volatile lp_system_reg_lp_cpu_exc_pc_reg_t lp_cpu_exc_pc;
-    volatile lp_system_reg_idbus_addrhole_addr_reg_t idbus_addrhole_addr;
-    volatile lp_system_reg_idbus_addrhole_info_reg_t idbus_addrhole_info;
-    volatile lp_system_reg_hp_por_rst_bypass_ctrl_reg_t hp_por_rst_bypass_ctrl;
-    volatile lp_system_reg_rng_data_reg_t rng_data;
-    uint32_t reserved_1a8[2];
-    volatile lp_system_reg_lp_core_ahb_timeout_reg_t lp_core_ahb_timeout;
-    volatile lp_system_reg_lp_core_ibus_timeout_reg_t lp_core_ibus_timeout;
-    volatile lp_system_reg_lp_core_dbus_timeout_reg_t lp_core_dbus_timeout;
-    volatile lp_system_reg_lp_core_err_resp_dis_reg_t lp_core_err_resp_dis;
-    volatile lp_system_reg_rng_cfg_reg_t rng_cfg;
-} lp_system_reg_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_system_reg_dev_t) == 0x1c4, "Invalid size of lp_system_reg_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_tee_reg.h b/components/soc/esp32p4/include/soc/lp_tee_reg.h
deleted file mode 100644
index 932c959d04..0000000000
--- a/components/soc/esp32p4/include/soc/lp_tee_reg.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_TEE_M0_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
-/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define LP_TEE_M0_MODE    0x00000003U
-#define LP_TEE_M0_MODE_M  (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
-#define LP_TEE_M0_MODE_V  0x00000003U
-#define LP_TEE_M0_MODE_S  0
-
-/** LP_TEE_CLOCK_GATE_REG register
- *  Clock gating register
- */
-#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
-/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define LP_TEE_CLK_EN    (BIT(0))
-#define LP_TEE_CLK_EN_M  (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
-#define LP_TEE_CLK_EN_V  0x00000001U
-#define LP_TEE_CLK_EN_S  0
-
-/** LP_TEE_FORCE_ACC_HP_REG register
- *  need_des
- */
-#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
-/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_TEE_FORCE_ACC_HPMEM_EN    (BIT(0))
-#define LP_TEE_FORCE_ACC_HPMEM_EN_M  (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
-#define LP_TEE_FORCE_ACC_HPMEM_EN_V  0x00000001U
-#define LP_TEE_FORCE_ACC_HPMEM_EN_S  0
-
-/** LP_TEE_DATE_REG register
- *  Version register
- */
-#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
-/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688;
- *  reg_tee_date
- */
-#define LP_TEE_DATE_REG    0x0FFFFFFFU
-#define LP_TEE_DATE_REG_M  (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
-#define LP_TEE_DATE_REG_V  0x0FFFFFFFU
-#define LP_TEE_DATE_REG_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_tee_struct.h b/components/soc/esp32p4/include/soc/lp_tee_struct.h
deleted file mode 100644
index b769f963c6..0000000000
--- a/components/soc/esp32p4/include/soc/lp_tee_struct.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Tee mode control register */
-/** Type of m0_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m0_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m0_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_tee_m0_mode_ctrl_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  Clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_tee_clock_gate_reg_t;
-
-
-/** Group: configure_register */
-/** Type of force_acc_hp register
- *  need_des
- */
-typedef union {
-    struct {
-        /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_acc_hpmem_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_tee_force_acc_hp_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date_reg : R/W; bitpos: [27:0]; default: 35672688;
-         *  reg_tee_date
-         */
-        uint32_t date_reg:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_tee_date_reg_t;
-
-
-typedef struct lp_tee_dev_t {
-    volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
-    volatile lp_tee_clock_gate_reg_t clock_gate;
-    uint32_t reserved_008[34];
-    volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
-    uint32_t reserved_094[26];
-    volatile lp_tee_date_reg_t date;
-} lp_tee_dev_t;
-
-extern lp_tee_dev_t LP_TEE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/mem_monitor_reg.h b/components/soc/esp32p4/include/soc/mem_monitor_reg.h
deleted file mode 100644
index 3aec488661..0000000000
--- a/components/soc/esp32p4/include/soc/mem_monitor_reg.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_MEM_MONITOR_REG_H_
-#define _SOC_MEM_MONITOR_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define MEM_MONITOR_LOG_SETTING_REG          (DR_REG_MEM_MONITOR_BASE + 0x0)
-/* MEM_MONITOR_LOG_DMA_1_ENA : R/W ;bitpos:[31:24] ;default: 8'b0 ; */
-/*description: enable dma_1 log.*/
-#define MEM_MONITOR_LOG_DMA_1_ENA    0x000000FF
-#define MEM_MONITOR_LOG_DMA_1_ENA_M  ((MEM_MONITOR_LOG_DMA_1_ENA_V)<<(MEM_MONITOR_LOG_DMA_1_ENA_S))
-#define MEM_MONITOR_LOG_DMA_1_ENA_V  0xFF
-#define MEM_MONITOR_LOG_DMA_1_ENA_S  24
-/* MEM_MONITOR_LOG_DMA_0_ENA : R/W ;bitpos:[23:16] ;default: 8'b0 ; */
-/*description: enable dma_0 log.*/
-#define MEM_MONITOR_LOG_DMA_0_ENA    0x000000FF
-#define MEM_MONITOR_LOG_DMA_0_ENA_M  ((MEM_MONITOR_LOG_DMA_0_ENA_V)<<(MEM_MONITOR_LOG_DMA_0_ENA_S))
-#define MEM_MONITOR_LOG_DMA_0_ENA_V  0xFF
-#define MEM_MONITOR_LOG_DMA_0_ENA_S  16
-/* MEM_MONITOR_LOG_CORE_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
-/*description: enable core log.*/
-#define MEM_MONITOR_LOG_CORE_ENA    0x000000FF
-#define MEM_MONITOR_LOG_CORE_ENA_M  ((MEM_MONITOR_LOG_CORE_ENA_V)<<(MEM_MONITOR_LOG_CORE_ENA_S))
-#define MEM_MONITOR_LOG_CORE_ENA_V  0xFF
-#define MEM_MONITOR_LOG_CORE_ENA_S  8
-/* MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END.*/
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(4))
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (BIT(4))
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x1
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  4
-/* MEM_MONITOR_LOG_MODE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYT
-E monitor.*/
-#define MEM_MONITOR_LOG_MODE    0x0000000F
-#define MEM_MONITOR_LOG_MODE_M  ((MEM_MONITOR_LOG_MODE_V)<<(MEM_MONITOR_LOG_MODE_S))
-#define MEM_MONITOR_LOG_MODE_V  0xF
-#define MEM_MONITOR_LOG_MODE_S  0
-
-#define MEM_MONITOR_LOG_SETTING1_REG          (DR_REG_MEM_MONITOR_BASE + 0x4)
-/* MEM_MONITOR_LOG_DMA_3_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
-/*description: enable dma_3 log.*/
-#define MEM_MONITOR_LOG_DMA_3_ENA    0x000000FF
-#define MEM_MONITOR_LOG_DMA_3_ENA_M  ((MEM_MONITOR_LOG_DMA_3_ENA_V)<<(MEM_MONITOR_LOG_DMA_3_ENA_S))
-#define MEM_MONITOR_LOG_DMA_3_ENA_V  0xFF
-#define MEM_MONITOR_LOG_DMA_3_ENA_S  8
-/* MEM_MONITOR_LOG_DMA_2_ENA : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: enable dma_2 log.*/
-#define MEM_MONITOR_LOG_DMA_2_ENA    0x000000FF
-#define MEM_MONITOR_LOG_DMA_2_ENA_M  ((MEM_MONITOR_LOG_DMA_2_ENA_V)<<(MEM_MONITOR_LOG_DMA_2_ENA_S))
-#define MEM_MONITOR_LOG_DMA_2_ENA_V  0xFF
-#define MEM_MONITOR_LOG_DMA_2_ENA_S  0
-
-#define MEM_MONITOR_LOG_CHECK_DATA_REG          (DR_REG_MEM_MONITOR_BASE + 0x8)
-/* MEM_MONITOR_LOG_CHECK_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The special check data, when write this special data, it will trigger logging..*/
-#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFF
-#define MEM_MONITOR_LOG_CHECK_DATA_M  ((MEM_MONITOR_LOG_CHECK_DATA_V)<<(MEM_MONITOR_LOG_CHECK_DATA_S))
-#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFF
-#define MEM_MONITOR_LOG_CHECK_DATA_S  0
-
-#define MEM_MONITOR_LOG_DATA_MASK_REG          (DR_REG_MEM_MONITOR_BASE + 0xC)
-/* MEM_MONITOR_LOG_DATA_MASK : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BI
-T1 mask second byte, and so on..*/
-#define MEM_MONITOR_LOG_DATA_MASK    0x0000000F
-#define MEM_MONITOR_LOG_DATA_MASK_M  ((MEM_MONITOR_LOG_DATA_MASK_V)<<(MEM_MONITOR_LOG_DATA_MASK_S))
-#define MEM_MONITOR_LOG_DATA_MASK_V  0xF
-#define MEM_MONITOR_LOG_DATA_MASK_S  0
-
-#define MEM_MONITOR_LOG_MIN_REG          (DR_REG_MEM_MONITOR_BASE + 0x10)
-/* MEM_MONITOR_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: the min address of log range.*/
-#define MEM_MONITOR_LOG_MIN    0xFFFFFFFF
-#define MEM_MONITOR_LOG_MIN_M  ((MEM_MONITOR_LOG_MIN_V)<<(MEM_MONITOR_LOG_MIN_S))
-#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFF
-#define MEM_MONITOR_LOG_MIN_S  0
-
-#define MEM_MONITOR_LOG_MAX_REG          (DR_REG_MEM_MONITOR_BASE + 0x14)
-/* MEM_MONITOR_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: the max address of log range.*/
-#define MEM_MONITOR_LOG_MAX    0xFFFFFFFF
-#define MEM_MONITOR_LOG_MAX_M  ((MEM_MONITOR_LOG_MAX_V)<<(MEM_MONITOR_LOG_MAX_S))
-#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFF
-#define MEM_MONITOR_LOG_MAX_S  0
-
-#define MEM_MONITOR_LOG_MEM_START_REG          (DR_REG_MEM_MONITOR_BASE + 0x18)
-/* MEM_MONITOR_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: the start address of writing logging message.*/
-#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFF
-#define MEM_MONITOR_LOG_MEM_START_M  ((MEM_MONITOR_LOG_MEM_START_V)<<(MEM_MONITOR_LOG_MEM_START_S))
-#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFF
-#define MEM_MONITOR_LOG_MEM_START_S  0
-
-#define MEM_MONITOR_LOG_MEM_END_REG          (DR_REG_MEM_MONITOR_BASE + 0x1C)
-/* MEM_MONITOR_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: the end address of writing logging message.*/
-#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFF
-#define MEM_MONITOR_LOG_MEM_END_M  ((MEM_MONITOR_LOG_MEM_END_V)<<(MEM_MONITOR_LOG_MEM_END_S))
-#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFF
-#define MEM_MONITOR_LOG_MEM_END_S  0
-
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG          (DR_REG_MEM_MONITOR_BASE + 0x20)
-/* MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: means next writing address.*/
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFF
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  ((MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V)<<(MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S))
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFF
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
-
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG          (DR_REG_MEM_MONITOR_BASE + 0x24)
-/* MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_ME
-M_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START.*/
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (BIT(0))
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x1
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
-
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG          (DR_REG_MEM_MONITOR_BASE + 0x28)
-/* MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG.*/
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (BIT(1))
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x1
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
-/* MEM_MONITOR_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1 means memory write loop at least one time at the range of MEM_START and MEM_EN
-D.*/
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (BIT(0))
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x1
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
-
-#define MEM_MONITOR_CLOCK_GATE_REG          (DR_REG_MEM_MONITOR_BASE + 0x2C)
-/* MEM_MONITOR_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set 1 to force on the clk of mem_monitor register.*/
-#define MEM_MONITOR_CLK_EN    (BIT(0))
-#define MEM_MONITOR_CLK_EN_M  (BIT(0))
-#define MEM_MONITOR_CLK_EN_V  0x1
-#define MEM_MONITOR_CLK_EN_S  0
-
-#define MEM_MONITOR_DATE_REG          (DR_REG_MEM_MONITOR_BASE + 0x3FC)
-/* MEM_MONITOR_DATE : R/W ;bitpos:[27:0] ;default: 28'h2302220 ; */
-/*description: version register.*/
-#define MEM_MONITOR_DATE    0x0FFFFFFF
-#define MEM_MONITOR_DATE_M  ((MEM_MONITOR_DATE_V)<<(MEM_MONITOR_DATE_S))
-#define MEM_MONITOR_DATE_V  0xFFFFFFF
-#define MEM_MONITOR_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_MEM_MONITOR_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/mem_monitor_struct.h b/components/soc/esp32p4/include/soc/mem_monitor_struct.h
deleted file mode 100644
index 463f58aa4e..0000000000
--- a/components/soc/esp32p4/include/soc/mem_monitor_struct.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_MEM_MONITOR_STRUCT_H_
-#define _SOC_MEM_MONITOR_STRUCT_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc/soc.h"
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t reg_log_mode                  :    4;  /*Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE monitor */
-            uint32_t reg_log_mem_loop_enable       :    1;  /*Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END*/
-            uint32_t reserved5                     :    3;  /*reseved*/
-            uint32_t reg_log_core_ena              :    8;  /*enable core log*/
-            uint32_t reg_log_dma_0_ena             :    8;  /*enable dma_0 log*/
-            uint32_t reg_log_dma_1_ena             :    8;  /*enable dma_1 log*/
-        };
-        uint32_t val;
-    } log_setting;
-    union {
-        struct {
-            uint32_t reg_log_dma_2_ena             :    8;  /*enable dma_2 log*/
-            uint32_t reg_log_dma_3_ena             :    8;  /*enable dma_3 log*/
-            uint32_t reserved16                    :    16;  /*reseved*/
-        };
-        uint32_t val;
-    } log_setting1;
-    uint32_t log_check_data;
-    union {
-        struct {
-            uint32_t reg_log_data_mask             :    4;  /*byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on.*/
-            uint32_t reserved4                     :    28;  /*reseved*/
-        };
-        uint32_t val;
-    } log_data_mask;
-    uint32_t log_min;
-    uint32_t log_max;
-    uint32_t log_mem_start;
-    uint32_t log_mem_end;
-    uint32_t log_mem_current_addr;
-    union {
-        struct {
-            uint32_t reg_log_mem_addr_update       :    1;  /*Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START */
-            uint32_t reserved1                     :    31;  /*reseved*/
-        };
-        uint32_t val;
-    } log_mem_addr_update;
-    union {
-        struct {
-            uint32_t reg_log_mem_full_flag         :    1;  /*1 means memory write loop at least one time at the range of MEM_START and MEM_END*/
-            uint32_t reg_clr_log_mem_full_flag     :    1;  /*Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG*/
-            uint32_t reserved2                     :    30;  /*reseved*/
-        };
-        uint32_t val;
-    } log_mem_full_flag;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;  /*Set 1 to force on the clk of mem_monitor register */
-            uint32_t reserved1                     :    31;  /*reseved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_30;
-    uint32_t reserved_34;
-    uint32_t reserved_38;
-    uint32_t reserved_3c;
-    uint32_t reserved_40;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t reg_mem_monitor_date          :    28;  /*version register*/
-            uint32_t reserved28                    :    4;  /*reseved*/
-        };
-        uint32_t val;
-    } date;
-} mem_monitor_dev_t;
-extern mem_monitor_dev_t MEM_MONITOR;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_MEM_MONITOR_STRUCT_H_ */
diff --git a/components/soc/esp32p4/include/soc/mmu.h b/components/soc/esp32p4/include/soc/mmu.h
index f0eb7f00f4..94937c2117 100644
--- a/components/soc/esp32p4/include/soc/mmu.h
+++ b/components/soc/esp32p4/include/soc/mmu.h
@@ -13,21 +13,8 @@
 extern "C" {
 #endif
 
-/* Defined for flash mmap */
-#define SOC_MMU_REGIONS_COUNT                   1
-#define SOC_MMU_PAGES_PER_REGION                1024
-#define SOC_MMU_IROM0_PAGES_START               (CACHE_IROM_MMU_START / sizeof(uint32_t))
-#define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
-#define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
-#define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
-#define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
-#define SOC_MMU_ADDR_MASK                       (MMU_VALID - 1)
-#define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
-#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE       FLASH_MMU_TABLE
-#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
-#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
-#define SOC_MMU_VADDR0_START_ADDR               (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
-#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW
+//To delete this file
+//TODO: IDF-7686
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/otp_debug_reg.h b/components/soc/esp32p4/include/soc/otp_debug_reg.h
deleted file mode 100644
index 521f116aa0..0000000000
--- a/components/soc/esp32p4/include/soc/otp_debug_reg.h
+++ /dev/null
@@ -1,1600 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** OTP_DEBUG_WR_DIS_REG register
- *  Otp debuger block0 data register1.
- */
-#define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0)
-/** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 write disable data.
- */
-#define OTP_DEBUG_BLOCK0_WR_DIS    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_WR_DIS_M  (OTP_DEBUG_BLOCK0_WR_DIS_V << OTP_DEBUG_BLOCK0_WR_DIS_S)
-#define OTP_DEBUG_BLOCK0_WR_DIS_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_WR_DIS_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W1_REG register
- *  Otp debuger block0 data register2.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1_M  (OTP_DEBUG_BLOCK0_BACKUP1_W1_V << OTP_DEBUG_BLOCK0_BACKUP1_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W2_REG register
- *  Otp debuger block0 data register3.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2_M  (OTP_DEBUG_BLOCK0_BACKUP1_W2_V << OTP_DEBUG_BLOCK0_BACKUP1_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W3_REG register
- *  Otp debuger block0 data register4.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3_M  (OTP_DEBUG_BLOCK0_BACKUP1_W3_V << OTP_DEBUG_BLOCK0_BACKUP1_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W4_REG register
- *  Otp debuger block0 data register5.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4_M  (OTP_DEBUG_BLOCK0_BACKUP1_W4_V << OTP_DEBUG_BLOCK0_BACKUP1_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W5_REG register
- *  Otp debuger block0 data register6.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5_M  (OTP_DEBUG_BLOCK0_BACKUP1_W5_V << OTP_DEBUG_BLOCK0_BACKUP1_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W1_REG register
- *  Otp debuger block0 data register7.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1_M  (OTP_DEBUG_BLOCK0_BACKUP2_W1_V << OTP_DEBUG_BLOCK0_BACKUP2_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W2_REG register
- *  Otp debuger block0 data register8.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2_M  (OTP_DEBUG_BLOCK0_BACKUP2_W2_V << OTP_DEBUG_BLOCK0_BACKUP2_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W3_REG register
- *  Otp debuger block0 data register9.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3_M  (OTP_DEBUG_BLOCK0_BACKUP2_W3_V << OTP_DEBUG_BLOCK0_BACKUP2_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W4_REG register
- *  Otp debuger block0 data register10.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4_M  (OTP_DEBUG_BLOCK0_BACKUP2_W4_V << OTP_DEBUG_BLOCK0_BACKUP2_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W5_REG register
- *  Otp debuger block0 data register11.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5_M  (OTP_DEBUG_BLOCK0_BACKUP2_W5_V << OTP_DEBUG_BLOCK0_BACKUP2_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W1_REG register
- *  Otp debuger block0 data register12.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1_M  (OTP_DEBUG_BLOCK0_BACKUP3_W1_V << OTP_DEBUG_BLOCK0_BACKUP3_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W2_REG register
- *  Otp debuger block0 data register13.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2_M  (OTP_DEBUG_BLOCK0_BACKUP3_W2_V << OTP_DEBUG_BLOCK0_BACKUP3_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W3_REG register
- *  Otp debuger block0 data register14.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3_M  (OTP_DEBUG_BLOCK0_BACKUP3_W3_V << OTP_DEBUG_BLOCK0_BACKUP3_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W4_REG register
- *  Otp debuger block0 data register15.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4_M  (OTP_DEBUG_BLOCK0_BACKUP3_W4_V << OTP_DEBUG_BLOCK0_BACKUP3_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W5_REG register
- *  Otp debuger block0 data register16.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5_M  (OTP_DEBUG_BLOCK0_BACKUP3_W5_V << OTP_DEBUG_BLOCK0_BACKUP3_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W1_REG register
- *  Otp debuger block0 data register17.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1_M  (OTP_DEBUG_BLOCK0_BACKUP4_W1_V << OTP_DEBUG_BLOCK0_BACKUP4_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W2_REG register
- *  Otp debuger block0 data register18.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2_M  (OTP_DEBUG_BLOCK0_BACKUP4_W2_V << OTP_DEBUG_BLOCK0_BACKUP4_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W3_REG register
- *  Otp debuger block0 data register19.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3_M  (OTP_DEBUG_BLOCK0_BACKUP4_W3_V << OTP_DEBUG_BLOCK0_BACKUP4_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W4_REG register
- *  Otp debuger block0 data register20.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4_M  (OTP_DEBUG_BLOCK0_BACKUP4_W4_V << OTP_DEBUG_BLOCK0_BACKUP4_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W5_REG register
- *  Otp debuger block0 data register21.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5_M  (OTP_DEBUG_BLOCK0_BACKUP4_W5_V << OTP_DEBUG_BLOCK0_BACKUP4_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5_S  0
-
-/** OTP_DEBUG_BLK1_W1_REG register
- *  Otp debuger block1 data register1.
- */
-#define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54)
-/** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word1 data.
- */
-#define OTP_DEBUG_BLOCK1_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W1_M  (OTP_DEBUG_BLOCK1_W1_V << OTP_DEBUG_BLOCK1_W1_S)
-#define OTP_DEBUG_BLOCK1_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W1_S  0
-
-/** OTP_DEBUG_BLK1_W2_REG register
- *  Otp debuger block1 data register2.
- */
-#define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58)
-/** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word2 data.
- */
-#define OTP_DEBUG_BLOCK1_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W2_M  (OTP_DEBUG_BLOCK1_W2_V << OTP_DEBUG_BLOCK1_W2_S)
-#define OTP_DEBUG_BLOCK1_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W2_S  0
-
-/** OTP_DEBUG_BLK1_W3_REG register
- *  Otp debuger block1 data register3.
- */
-#define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c)
-/** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word3 data.
- */
-#define OTP_DEBUG_BLOCK1_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W3_M  (OTP_DEBUG_BLOCK1_W3_V << OTP_DEBUG_BLOCK1_W3_S)
-#define OTP_DEBUG_BLOCK1_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W3_S  0
-
-/** OTP_DEBUG_BLK1_W4_REG register
- *  Otp debuger block1 data register4.
- */
-#define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60)
-/** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word4 data.
- */
-#define OTP_DEBUG_BLOCK1_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W4_M  (OTP_DEBUG_BLOCK1_W4_V << OTP_DEBUG_BLOCK1_W4_S)
-#define OTP_DEBUG_BLOCK1_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W4_S  0
-
-/** OTP_DEBUG_BLK1_W5_REG register
- *  Otp debuger block1 data register5.
- */
-#define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64)
-/** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word5 data.
- */
-#define OTP_DEBUG_BLOCK1_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W5_M  (OTP_DEBUG_BLOCK1_W5_V << OTP_DEBUG_BLOCK1_W5_S)
-#define OTP_DEBUG_BLOCK1_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W5_S  0
-
-/** OTP_DEBUG_BLK1_W6_REG register
- *  Otp debuger block1 data register6.
- */
-#define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68)
-/** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word6 data.
- */
-#define OTP_DEBUG_BLOCK1_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W6_M  (OTP_DEBUG_BLOCK1_W6_V << OTP_DEBUG_BLOCK1_W6_S)
-#define OTP_DEBUG_BLOCK1_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W6_S  0
-
-/** OTP_DEBUG_BLK1_W7_REG register
- *  Otp debuger block1 data register7.
- */
-#define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c)
-/** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word7 data.
- */
-#define OTP_DEBUG_BLOCK1_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W7_M  (OTP_DEBUG_BLOCK1_W7_V << OTP_DEBUG_BLOCK1_W7_S)
-#define OTP_DEBUG_BLOCK1_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W7_S  0
-
-/** OTP_DEBUG_BLK1_W8_REG register
- *  Otp debuger block1 data register8.
- */
-#define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70)
-/** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word8 data.
- */
-#define OTP_DEBUG_BLOCK1_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W8_M  (OTP_DEBUG_BLOCK1_W8_V << OTP_DEBUG_BLOCK1_W8_S)
-#define OTP_DEBUG_BLOCK1_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W8_S  0
-
-/** OTP_DEBUG_BLK1_W9_REG register
- *  Otp debuger block1 data register9.
- */
-#define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74)
-/** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word9 data.
- */
-#define OTP_DEBUG_BLOCK1_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W9_M  (OTP_DEBUG_BLOCK1_W9_V << OTP_DEBUG_BLOCK1_W9_S)
-#define OTP_DEBUG_BLOCK1_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W9_S  0
-
-/** OTP_DEBUG_BLK2_W1_REG register
- *  Otp debuger block2 data register1.
- */
-#define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78)
-/** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word1 data.
- */
-#define OTP_DEBUG_BLOCK2_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W1_M  (OTP_DEBUG_BLOCK2_W1_V << OTP_DEBUG_BLOCK2_W1_S)
-#define OTP_DEBUG_BLOCK2_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W1_S  0
-
-/** OTP_DEBUG_BLK2_W2_REG register
- *  Otp debuger block2 data register2.
- */
-#define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c)
-/** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word2 data.
- */
-#define OTP_DEBUG_BLOCK2_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W2_M  (OTP_DEBUG_BLOCK2_W2_V << OTP_DEBUG_BLOCK2_W2_S)
-#define OTP_DEBUG_BLOCK2_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W2_S  0
-
-/** OTP_DEBUG_BLK2_W3_REG register
- *  Otp debuger block2 data register3.
- */
-#define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80)
-/** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word3 data.
- */
-#define OTP_DEBUG_BLOCK2_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W3_M  (OTP_DEBUG_BLOCK2_W3_V << OTP_DEBUG_BLOCK2_W3_S)
-#define OTP_DEBUG_BLOCK2_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W3_S  0
-
-/** OTP_DEBUG_BLK2_W4_REG register
- *  Otp debuger block2 data register4.
- */
-#define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84)
-/** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word4 data.
- */
-#define OTP_DEBUG_BLOCK2_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W4_M  (OTP_DEBUG_BLOCK2_W4_V << OTP_DEBUG_BLOCK2_W4_S)
-#define OTP_DEBUG_BLOCK2_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W4_S  0
-
-/** OTP_DEBUG_BLK2_W5_REG register
- *  Otp debuger block2 data register5.
- */
-#define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88)
-/** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word5 data.
- */
-#define OTP_DEBUG_BLOCK2_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W5_M  (OTP_DEBUG_BLOCK2_W5_V << OTP_DEBUG_BLOCK2_W5_S)
-#define OTP_DEBUG_BLOCK2_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W5_S  0
-
-/** OTP_DEBUG_BLK2_W6_REG register
- *  Otp debuger block2 data register6.
- */
-#define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c)
-/** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word6 data.
- */
-#define OTP_DEBUG_BLOCK2_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W6_M  (OTP_DEBUG_BLOCK2_W6_V << OTP_DEBUG_BLOCK2_W6_S)
-#define OTP_DEBUG_BLOCK2_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W6_S  0
-
-/** OTP_DEBUG_BLK2_W7_REG register
- *  Otp debuger block2 data register7.
- */
-#define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90)
-/** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word7 data.
- */
-#define OTP_DEBUG_BLOCK2_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W7_M  (OTP_DEBUG_BLOCK2_W7_V << OTP_DEBUG_BLOCK2_W7_S)
-#define OTP_DEBUG_BLOCK2_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W7_S  0
-
-/** OTP_DEBUG_BLK2_W8_REG register
- *  Otp debuger block2 data register8.
- */
-#define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94)
-/** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word8 data.
- */
-#define OTP_DEBUG_BLOCK2_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W8_M  (OTP_DEBUG_BLOCK2_W8_V << OTP_DEBUG_BLOCK2_W8_S)
-#define OTP_DEBUG_BLOCK2_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W8_S  0
-
-/** OTP_DEBUG_BLK2_W9_REG register
- *  Otp debuger block2 data register9.
- */
-#define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98)
-/** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word9 data.
- */
-#define OTP_DEBUG_BLOCK2_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W9_M  (OTP_DEBUG_BLOCK2_W9_V << OTP_DEBUG_BLOCK2_W9_S)
-#define OTP_DEBUG_BLOCK2_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W9_S  0
-
-/** OTP_DEBUG_BLK2_W10_REG register
- *  Otp debuger block2 data register10.
- */
-#define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c)
-/** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word10 data.
- */
-#define OTP_DEBUG_BLOCK2_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W10_M  (OTP_DEBUG_BLOCK2_W10_V << OTP_DEBUG_BLOCK2_W10_S)
-#define OTP_DEBUG_BLOCK2_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W10_S  0
-
-/** OTP_DEBUG_BLK2_W11_REG register
- *  Otp debuger block2 data register11.
- */
-#define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0)
-/** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word11 data.
- */
-#define OTP_DEBUG_BLOCK2_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W11_M  (OTP_DEBUG_BLOCK2_W11_V << OTP_DEBUG_BLOCK2_W11_S)
-#define OTP_DEBUG_BLOCK2_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W11_S  0
-
-/** OTP_DEBUG_BLK3_W1_REG register
- *  Otp debuger block3 data register1.
- */
-#define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4)
-/** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word1 data.
- */
-#define OTP_DEBUG_BLOCK3_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W1_M  (OTP_DEBUG_BLOCK3_W1_V << OTP_DEBUG_BLOCK3_W1_S)
-#define OTP_DEBUG_BLOCK3_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W1_S  0
-
-/** OTP_DEBUG_BLK3_W2_REG register
- *  Otp debuger block3 data register2.
- */
-#define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8)
-/** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word2 data.
- */
-#define OTP_DEBUG_BLOCK3_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W2_M  (OTP_DEBUG_BLOCK3_W2_V << OTP_DEBUG_BLOCK3_W2_S)
-#define OTP_DEBUG_BLOCK3_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W2_S  0
-
-/** OTP_DEBUG_BLK3_W3_REG register
- *  Otp debuger block3 data register3.
- */
-#define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac)
-/** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word3 data.
- */
-#define OTP_DEBUG_BLOCK3_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W3_M  (OTP_DEBUG_BLOCK3_W3_V << OTP_DEBUG_BLOCK3_W3_S)
-#define OTP_DEBUG_BLOCK3_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W3_S  0
-
-/** OTP_DEBUG_BLK3_W4_REG register
- *  Otp debuger block3 data register4.
- */
-#define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0)
-/** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word4 data.
- */
-#define OTP_DEBUG_BLOCK3_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W4_M  (OTP_DEBUG_BLOCK3_W4_V << OTP_DEBUG_BLOCK3_W4_S)
-#define OTP_DEBUG_BLOCK3_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W4_S  0
-
-/** OTP_DEBUG_BLK3_W5_REG register
- *  Otp debuger block3 data register5.
- */
-#define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4)
-/** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word5 data.
- */
-#define OTP_DEBUG_BLOCK3_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W5_M  (OTP_DEBUG_BLOCK3_W5_V << OTP_DEBUG_BLOCK3_W5_S)
-#define OTP_DEBUG_BLOCK3_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W5_S  0
-
-/** OTP_DEBUG_BLK3_W6_REG register
- *  Otp debuger block3 data register6.
- */
-#define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8)
-/** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word6 data.
- */
-#define OTP_DEBUG_BLOCK3_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W6_M  (OTP_DEBUG_BLOCK3_W6_V << OTP_DEBUG_BLOCK3_W6_S)
-#define OTP_DEBUG_BLOCK3_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W6_S  0
-
-/** OTP_DEBUG_BLK3_W7_REG register
- *  Otp debuger block3 data register7.
- */
-#define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc)
-/** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word7 data.
- */
-#define OTP_DEBUG_BLOCK3_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W7_M  (OTP_DEBUG_BLOCK3_W7_V << OTP_DEBUG_BLOCK3_W7_S)
-#define OTP_DEBUG_BLOCK3_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W7_S  0
-
-/** OTP_DEBUG_BLK3_W8_REG register
- *  Otp debuger block3 data register8.
- */
-#define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0)
-/** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word8 data.
- */
-#define OTP_DEBUG_BLOCK3_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W8_M  (OTP_DEBUG_BLOCK3_W8_V << OTP_DEBUG_BLOCK3_W8_S)
-#define OTP_DEBUG_BLOCK3_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W8_S  0
-
-/** OTP_DEBUG_BLK3_W9_REG register
- *  Otp debuger block3 data register9.
- */
-#define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4)
-/** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word9 data.
- */
-#define OTP_DEBUG_BLOCK3_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W9_M  (OTP_DEBUG_BLOCK3_W9_V << OTP_DEBUG_BLOCK3_W9_S)
-#define OTP_DEBUG_BLOCK3_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W9_S  0
-
-/** OTP_DEBUG_BLK3_W10_REG register
- *  Otp debuger block3 data register10.
- */
-#define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8)
-/** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word10 data.
- */
-#define OTP_DEBUG_BLOCK3_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W10_M  (OTP_DEBUG_BLOCK3_W10_V << OTP_DEBUG_BLOCK3_W10_S)
-#define OTP_DEBUG_BLOCK3_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W10_S  0
-
-/** OTP_DEBUG_BLK3_W11_REG register
- *  Otp debuger block3 data register11.
- */
-#define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc)
-/** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word11 data.
- */
-#define OTP_DEBUG_BLOCK3_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W11_M  (OTP_DEBUG_BLOCK3_W11_V << OTP_DEBUG_BLOCK3_W11_S)
-#define OTP_DEBUG_BLOCK3_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W11_S  0
-
-/** OTP_DEBUG_BLK4_W1_REG register
- *  Otp debuger block4 data register1.
- */
-#define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0)
-/** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word1 data.
- */
-#define OTP_DEBUG_BLOCK4_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W1_M  (OTP_DEBUG_BLOCK4_W1_V << OTP_DEBUG_BLOCK4_W1_S)
-#define OTP_DEBUG_BLOCK4_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W1_S  0
-
-/** OTP_DEBUG_BLK4_W2_REG register
- *  Otp debuger block4 data register2.
- */
-#define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4)
-/** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word2 data.
- */
-#define OTP_DEBUG_BLOCK4_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W2_M  (OTP_DEBUG_BLOCK4_W2_V << OTP_DEBUG_BLOCK4_W2_S)
-#define OTP_DEBUG_BLOCK4_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W2_S  0
-
-/** OTP_DEBUG_BLK4_W3_REG register
- *  Otp debuger block4 data register3.
- */
-#define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8)
-/** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word3 data.
- */
-#define OTP_DEBUG_BLOCK4_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W3_M  (OTP_DEBUG_BLOCK4_W3_V << OTP_DEBUG_BLOCK4_W3_S)
-#define OTP_DEBUG_BLOCK4_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W3_S  0
-
-/** OTP_DEBUG_BLK4_W4_REG register
- *  Otp debuger block4 data register4.
- */
-#define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc)
-/** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word4 data.
- */
-#define OTP_DEBUG_BLOCK4_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W4_M  (OTP_DEBUG_BLOCK4_W4_V << OTP_DEBUG_BLOCK4_W4_S)
-#define OTP_DEBUG_BLOCK4_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W4_S  0
-
-/** OTP_DEBUG_BLK4_W5_REG register
- *  Otp debuger block4 data register5.
- */
-#define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0)
-/** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word5 data.
- */
-#define OTP_DEBUG_BLOCK4_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W5_M  (OTP_DEBUG_BLOCK4_W5_V << OTP_DEBUG_BLOCK4_W5_S)
-#define OTP_DEBUG_BLOCK4_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W5_S  0
-
-/** OTP_DEBUG_BLK4_W6_REG register
- *  Otp debuger block4 data register6.
- */
-#define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4)
-/** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word6 data.
- */
-#define OTP_DEBUG_BLOCK4_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W6_M  (OTP_DEBUG_BLOCK4_W6_V << OTP_DEBUG_BLOCK4_W6_S)
-#define OTP_DEBUG_BLOCK4_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W6_S  0
-
-/** OTP_DEBUG_BLK4_W7_REG register
- *  Otp debuger block4 data register7.
- */
-#define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8)
-/** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word7 data.
- */
-#define OTP_DEBUG_BLOCK4_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W7_M  (OTP_DEBUG_BLOCK4_W7_V << OTP_DEBUG_BLOCK4_W7_S)
-#define OTP_DEBUG_BLOCK4_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W7_S  0
-
-/** OTP_DEBUG_BLK4_W8_REG register
- *  Otp debuger block4 data register8.
- */
-#define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec)
-/** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word8 data.
- */
-#define OTP_DEBUG_BLOCK4_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W8_M  (OTP_DEBUG_BLOCK4_W8_V << OTP_DEBUG_BLOCK4_W8_S)
-#define OTP_DEBUG_BLOCK4_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W8_S  0
-
-/** OTP_DEBUG_BLK4_W9_REG register
- *  Otp debuger block4 data register9.
- */
-#define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0)
-/** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word9 data.
- */
-#define OTP_DEBUG_BLOCK4_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W9_M  (OTP_DEBUG_BLOCK4_W9_V << OTP_DEBUG_BLOCK4_W9_S)
-#define OTP_DEBUG_BLOCK4_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W9_S  0
-
-/** OTP_DEBUG_BLK4_W10_REG register
- *  Otp debuger block4 data registe10.
- */
-#define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4)
-/** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word10 data.
- */
-#define OTP_DEBUG_BLOCK4_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W10_M  (OTP_DEBUG_BLOCK4_W10_V << OTP_DEBUG_BLOCK4_W10_S)
-#define OTP_DEBUG_BLOCK4_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W10_S  0
-
-/** OTP_DEBUG_BLK4_W11_REG register
- *  Otp debuger block4 data register11.
- */
-#define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8)
-/** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word11 data.
- */
-#define OTP_DEBUG_BLOCK4_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W11_M  (OTP_DEBUG_BLOCK4_W11_V << OTP_DEBUG_BLOCK4_W11_S)
-#define OTP_DEBUG_BLOCK4_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W11_S  0
-
-/** OTP_DEBUG_BLK5_W1_REG register
- *  Otp debuger block5 data register1.
- */
-#define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc)
-/** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word1 data.
- */
-#define OTP_DEBUG_BLOCK5_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W1_M  (OTP_DEBUG_BLOCK5_W1_V << OTP_DEBUG_BLOCK5_W1_S)
-#define OTP_DEBUG_BLOCK5_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W1_S  0
-
-/** OTP_DEBUG_BLK5_W2_REG register
- *  Otp debuger block5 data register2.
- */
-#define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100)
-/** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word2 data.
- */
-#define OTP_DEBUG_BLOCK5_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W2_M  (OTP_DEBUG_BLOCK5_W2_V << OTP_DEBUG_BLOCK5_W2_S)
-#define OTP_DEBUG_BLOCK5_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W2_S  0
-
-/** OTP_DEBUG_BLK5_W3_REG register
- *  Otp debuger block5 data register3.
- */
-#define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104)
-/** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word3 data.
- */
-#define OTP_DEBUG_BLOCK5_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W3_M  (OTP_DEBUG_BLOCK5_W3_V << OTP_DEBUG_BLOCK5_W3_S)
-#define OTP_DEBUG_BLOCK5_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W3_S  0
-
-/** OTP_DEBUG_BLK5_W4_REG register
- *  Otp debuger block5 data register4.
- */
-#define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108)
-/** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word4 data.
- */
-#define OTP_DEBUG_BLOCK5_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W4_M  (OTP_DEBUG_BLOCK5_W4_V << OTP_DEBUG_BLOCK5_W4_S)
-#define OTP_DEBUG_BLOCK5_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W4_S  0
-
-/** OTP_DEBUG_BLK5_W5_REG register
- *  Otp debuger block5 data register5.
- */
-#define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c)
-/** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word5 data.
- */
-#define OTP_DEBUG_BLOCK5_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W5_M  (OTP_DEBUG_BLOCK5_W5_V << OTP_DEBUG_BLOCK5_W5_S)
-#define OTP_DEBUG_BLOCK5_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W5_S  0
-
-/** OTP_DEBUG_BLK5_W6_REG register
- *  Otp debuger block5 data register6.
- */
-#define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110)
-/** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word6 data.
- */
-#define OTP_DEBUG_BLOCK5_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W6_M  (OTP_DEBUG_BLOCK5_W6_V << OTP_DEBUG_BLOCK5_W6_S)
-#define OTP_DEBUG_BLOCK5_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W6_S  0
-
-/** OTP_DEBUG_BLK5_W7_REG register
- *  Otp debuger block5 data register7.
- */
-#define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114)
-/** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word7 data.
- */
-#define OTP_DEBUG_BLOCK5_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W7_M  (OTP_DEBUG_BLOCK5_W7_V << OTP_DEBUG_BLOCK5_W7_S)
-#define OTP_DEBUG_BLOCK5_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W7_S  0
-
-/** OTP_DEBUG_BLK5_W8_REG register
- *  Otp debuger block5 data register8.
- */
-#define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118)
-/** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word8 data.
- */
-#define OTP_DEBUG_BLOCK5_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W8_M  (OTP_DEBUG_BLOCK5_W8_V << OTP_DEBUG_BLOCK5_W8_S)
-#define OTP_DEBUG_BLOCK5_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W8_S  0
-
-/** OTP_DEBUG_BLK5_W9_REG register
- *  Otp debuger block5 data register9.
- */
-#define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c)
-/** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word9 data.
- */
-#define OTP_DEBUG_BLOCK5_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W9_M  (OTP_DEBUG_BLOCK5_W9_V << OTP_DEBUG_BLOCK5_W9_S)
-#define OTP_DEBUG_BLOCK5_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W9_S  0
-
-/** OTP_DEBUG_BLK5_W10_REG register
- *  Otp debuger block5 data register10.
- */
-#define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120)
-/** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word10 data.
- */
-#define OTP_DEBUG_BLOCK5_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W10_M  (OTP_DEBUG_BLOCK5_W10_V << OTP_DEBUG_BLOCK5_W10_S)
-#define OTP_DEBUG_BLOCK5_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W10_S  0
-
-/** OTP_DEBUG_BLK5_W11_REG register
- *  Otp debuger block5 data register11.
- */
-#define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124)
-/** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word11 data.
- */
-#define OTP_DEBUG_BLOCK5_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W11_M  (OTP_DEBUG_BLOCK5_W11_V << OTP_DEBUG_BLOCK5_W11_S)
-#define OTP_DEBUG_BLOCK5_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W11_S  0
-
-/** OTP_DEBUG_BLK6_W1_REG register
- *  Otp debuger block6 data register1.
- */
-#define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128)
-/** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word1 data.
- */
-#define OTP_DEBUG_BLOCK6_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W1_M  (OTP_DEBUG_BLOCK6_W1_V << OTP_DEBUG_BLOCK6_W1_S)
-#define OTP_DEBUG_BLOCK6_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W1_S  0
-
-/** OTP_DEBUG_BLK6_W2_REG register
- *  Otp debuger block6 data register2.
- */
-#define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c)
-/** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word2 data.
- */
-#define OTP_DEBUG_BLOCK6_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W2_M  (OTP_DEBUG_BLOCK6_W2_V << OTP_DEBUG_BLOCK6_W2_S)
-#define OTP_DEBUG_BLOCK6_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W2_S  0
-
-/** OTP_DEBUG_BLK6_W3_REG register
- *  Otp debuger block6 data register3.
- */
-#define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130)
-/** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word3 data.
- */
-#define OTP_DEBUG_BLOCK6_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W3_M  (OTP_DEBUG_BLOCK6_W3_V << OTP_DEBUG_BLOCK6_W3_S)
-#define OTP_DEBUG_BLOCK6_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W3_S  0
-
-/** OTP_DEBUG_BLK6_W4_REG register
- *  Otp debuger block6 data register4.
- */
-#define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134)
-/** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word4 data.
- */
-#define OTP_DEBUG_BLOCK6_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W4_M  (OTP_DEBUG_BLOCK6_W4_V << OTP_DEBUG_BLOCK6_W4_S)
-#define OTP_DEBUG_BLOCK6_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W4_S  0
-
-/** OTP_DEBUG_BLK6_W5_REG register
- *  Otp debuger block6 data register5.
- */
-#define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138)
-/** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word5 data.
- */
-#define OTP_DEBUG_BLOCK6_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W5_M  (OTP_DEBUG_BLOCK6_W5_V << OTP_DEBUG_BLOCK6_W5_S)
-#define OTP_DEBUG_BLOCK6_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W5_S  0
-
-/** OTP_DEBUG_BLK6_W6_REG register
- *  Otp debuger block6 data register6.
- */
-#define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c)
-/** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word6 data.
- */
-#define OTP_DEBUG_BLOCK6_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W6_M  (OTP_DEBUG_BLOCK6_W6_V << OTP_DEBUG_BLOCK6_W6_S)
-#define OTP_DEBUG_BLOCK6_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W6_S  0
-
-/** OTP_DEBUG_BLK6_W7_REG register
- *  Otp debuger block6 data register7.
- */
-#define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140)
-/** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word7 data.
- */
-#define OTP_DEBUG_BLOCK6_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W7_M  (OTP_DEBUG_BLOCK6_W7_V << OTP_DEBUG_BLOCK6_W7_S)
-#define OTP_DEBUG_BLOCK6_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W7_S  0
-
-/** OTP_DEBUG_BLK6_W8_REG register
- *  Otp debuger block6 data register8.
- */
-#define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144)
-/** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word8 data.
- */
-#define OTP_DEBUG_BLOCK6_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W8_M  (OTP_DEBUG_BLOCK6_W8_V << OTP_DEBUG_BLOCK6_W8_S)
-#define OTP_DEBUG_BLOCK6_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W8_S  0
-
-/** OTP_DEBUG_BLK6_W9_REG register
- *  Otp debuger block6 data register9.
- */
-#define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148)
-/** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word9 data.
- */
-#define OTP_DEBUG_BLOCK6_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W9_M  (OTP_DEBUG_BLOCK6_W9_V << OTP_DEBUG_BLOCK6_W9_S)
-#define OTP_DEBUG_BLOCK6_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W9_S  0
-
-/** OTP_DEBUG_BLK6_W10_REG register
- *  Otp debuger block6 data register10.
- */
-#define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c)
-/** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word10 data.
- */
-#define OTP_DEBUG_BLOCK6_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W10_M  (OTP_DEBUG_BLOCK6_W10_V << OTP_DEBUG_BLOCK6_W10_S)
-#define OTP_DEBUG_BLOCK6_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W10_S  0
-
-/** OTP_DEBUG_BLK6_W11_REG register
- *  Otp debuger block6 data register11.
- */
-#define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150)
-/** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word11 data.
- */
-#define OTP_DEBUG_BLOCK6_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W11_M  (OTP_DEBUG_BLOCK6_W11_V << OTP_DEBUG_BLOCK6_W11_S)
-#define OTP_DEBUG_BLOCK6_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W11_S  0
-
-/** OTP_DEBUG_BLK7_W1_REG register
- *  Otp debuger block7 data register1.
- */
-#define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154)
-/** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word1 data.
- */
-#define OTP_DEBUG_BLOCK7_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W1_M  (OTP_DEBUG_BLOCK7_W1_V << OTP_DEBUG_BLOCK7_W1_S)
-#define OTP_DEBUG_BLOCK7_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W1_S  0
-
-/** OTP_DEBUG_BLK7_W2_REG register
- *  Otp debuger block7 data register2.
- */
-#define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158)
-/** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word2 data.
- */
-#define OTP_DEBUG_BLOCK7_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W2_M  (OTP_DEBUG_BLOCK7_W2_V << OTP_DEBUG_BLOCK7_W2_S)
-#define OTP_DEBUG_BLOCK7_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W2_S  0
-
-/** OTP_DEBUG_BLK7_W3_REG register
- *  Otp debuger block7 data register3.
- */
-#define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c)
-/** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word3 data.
- */
-#define OTP_DEBUG_BLOCK7_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W3_M  (OTP_DEBUG_BLOCK7_W3_V << OTP_DEBUG_BLOCK7_W3_S)
-#define OTP_DEBUG_BLOCK7_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W3_S  0
-
-/** OTP_DEBUG_BLK7_W4_REG register
- *  Otp debuger block7 data register4.
- */
-#define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160)
-/** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word4 data.
- */
-#define OTP_DEBUG_BLOCK7_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W4_M  (OTP_DEBUG_BLOCK7_W4_V << OTP_DEBUG_BLOCK7_W4_S)
-#define OTP_DEBUG_BLOCK7_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W4_S  0
-
-/** OTP_DEBUG_BLK7_W5_REG register
- *  Otp debuger block7 data register5.
- */
-#define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164)
-/** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word5 data.
- */
-#define OTP_DEBUG_BLOCK7_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W5_M  (OTP_DEBUG_BLOCK7_W5_V << OTP_DEBUG_BLOCK7_W5_S)
-#define OTP_DEBUG_BLOCK7_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W5_S  0
-
-/** OTP_DEBUG_BLK7_W6_REG register
- *  Otp debuger block7 data register6.
- */
-#define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168)
-/** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word6 data.
- */
-#define OTP_DEBUG_BLOCK7_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W6_M  (OTP_DEBUG_BLOCK7_W6_V << OTP_DEBUG_BLOCK7_W6_S)
-#define OTP_DEBUG_BLOCK7_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W6_S  0
-
-/** OTP_DEBUG_BLK7_W7_REG register
- *  Otp debuger block7 data register7.
- */
-#define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c)
-/** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word7 data.
- */
-#define OTP_DEBUG_BLOCK7_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W7_M  (OTP_DEBUG_BLOCK7_W7_V << OTP_DEBUG_BLOCK7_W7_S)
-#define OTP_DEBUG_BLOCK7_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W7_S  0
-
-/** OTP_DEBUG_BLK7_W8_REG register
- *  Otp debuger block7 data register8.
- */
-#define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170)
-/** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word8 data.
- */
-#define OTP_DEBUG_BLOCK7_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W8_M  (OTP_DEBUG_BLOCK7_W8_V << OTP_DEBUG_BLOCK7_W8_S)
-#define OTP_DEBUG_BLOCK7_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W8_S  0
-
-/** OTP_DEBUG_BLK7_W9_REG register
- *  Otp debuger block7 data register9.
- */
-#define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174)
-/** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word9 data.
- */
-#define OTP_DEBUG_BLOCK7_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W9_M  (OTP_DEBUG_BLOCK7_W9_V << OTP_DEBUG_BLOCK7_W9_S)
-#define OTP_DEBUG_BLOCK7_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W9_S  0
-
-/** OTP_DEBUG_BLK7_W10_REG register
- *  Otp debuger block7 data register10.
- */
-#define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178)
-/** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word10 data.
- */
-#define OTP_DEBUG_BLOCK7_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W10_M  (OTP_DEBUG_BLOCK7_W10_V << OTP_DEBUG_BLOCK7_W10_S)
-#define OTP_DEBUG_BLOCK7_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W10_S  0
-
-/** OTP_DEBUG_BLK7_W11_REG register
- *  Otp debuger block7 data register11.
- */
-#define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c)
-/** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word11 data.
- */
-#define OTP_DEBUG_BLOCK7_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W11_M  (OTP_DEBUG_BLOCK7_W11_V << OTP_DEBUG_BLOCK7_W11_S)
-#define OTP_DEBUG_BLOCK7_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W11_S  0
-
-/** OTP_DEBUG_BLK8_W1_REG register
- *  Otp debuger block8 data register1.
- */
-#define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180)
-/** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word1 data.
- */
-#define OTP_DEBUG_BLOCK8_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W1_M  (OTP_DEBUG_BLOCK8_W1_V << OTP_DEBUG_BLOCK8_W1_S)
-#define OTP_DEBUG_BLOCK8_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W1_S  0
-
-/** OTP_DEBUG_BLK8_W2_REG register
- *  Otp debuger block8 data register2.
- */
-#define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184)
-/** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word2 data.
- */
-#define OTP_DEBUG_BLOCK8_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W2_M  (OTP_DEBUG_BLOCK8_W2_V << OTP_DEBUG_BLOCK8_W2_S)
-#define OTP_DEBUG_BLOCK8_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W2_S  0
-
-/** OTP_DEBUG_BLK8_W3_REG register
- *  Otp debuger block8 data register3.
- */
-#define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188)
-/** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word3 data.
- */
-#define OTP_DEBUG_BLOCK8_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W3_M  (OTP_DEBUG_BLOCK8_W3_V << OTP_DEBUG_BLOCK8_W3_S)
-#define OTP_DEBUG_BLOCK8_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W3_S  0
-
-/** OTP_DEBUG_BLK8_W4_REG register
- *  Otp debuger block8 data register4.
- */
-#define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c)
-/** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word4 data.
- */
-#define OTP_DEBUG_BLOCK8_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W4_M  (OTP_DEBUG_BLOCK8_W4_V << OTP_DEBUG_BLOCK8_W4_S)
-#define OTP_DEBUG_BLOCK8_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W4_S  0
-
-/** OTP_DEBUG_BLK8_W5_REG register
- *  Otp debuger block8 data register5.
- */
-#define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190)
-/** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word5 data.
- */
-#define OTP_DEBUG_BLOCK8_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W5_M  (OTP_DEBUG_BLOCK8_W5_V << OTP_DEBUG_BLOCK8_W5_S)
-#define OTP_DEBUG_BLOCK8_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W5_S  0
-
-/** OTP_DEBUG_BLK8_W6_REG register
- *  Otp debuger block8 data register6.
- */
-#define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194)
-/** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word6 data.
- */
-#define OTP_DEBUG_BLOCK8_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W6_M  (OTP_DEBUG_BLOCK8_W6_V << OTP_DEBUG_BLOCK8_W6_S)
-#define OTP_DEBUG_BLOCK8_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W6_S  0
-
-/** OTP_DEBUG_BLK8_W7_REG register
- *  Otp debuger block8 data register7.
- */
-#define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198)
-/** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word7 data.
- */
-#define OTP_DEBUG_BLOCK8_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W7_M  (OTP_DEBUG_BLOCK8_W7_V << OTP_DEBUG_BLOCK8_W7_S)
-#define OTP_DEBUG_BLOCK8_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W7_S  0
-
-/** OTP_DEBUG_BLK8_W8_REG register
- *  Otp debuger block8 data register8.
- */
-#define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c)
-/** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word8 data.
- */
-#define OTP_DEBUG_BLOCK8_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W8_M  (OTP_DEBUG_BLOCK8_W8_V << OTP_DEBUG_BLOCK8_W8_S)
-#define OTP_DEBUG_BLOCK8_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W8_S  0
-
-/** OTP_DEBUG_BLK8_W9_REG register
- *  Otp debuger block8 data register9.
- */
-#define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0)
-/** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word9 data.
- */
-#define OTP_DEBUG_BLOCK8_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W9_M  (OTP_DEBUG_BLOCK8_W9_V << OTP_DEBUG_BLOCK8_W9_S)
-#define OTP_DEBUG_BLOCK8_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W9_S  0
-
-/** OTP_DEBUG_BLK8_W10_REG register
- *  Otp debuger block8 data register10.
- */
-#define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4)
-/** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word10 data.
- */
-#define OTP_DEBUG_BLOCK8_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W10_M  (OTP_DEBUG_BLOCK8_W10_V << OTP_DEBUG_BLOCK8_W10_S)
-#define OTP_DEBUG_BLOCK8_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W10_S  0
-
-/** OTP_DEBUG_BLK8_W11_REG register
- *  Otp debuger block8 data register11.
- */
-#define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8)
-/** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word11 data.
- */
-#define OTP_DEBUG_BLOCK8_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W11_M  (OTP_DEBUG_BLOCK8_W11_V << OTP_DEBUG_BLOCK8_W11_S)
-#define OTP_DEBUG_BLOCK8_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W11_S  0
-
-/** OTP_DEBUG_BLK9_W1_REG register
- *  Otp debuger block9 data register1.
- */
-#define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac)
-/** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word1 data.
- */
-#define OTP_DEBUG_BLOCK9_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W1_M  (OTP_DEBUG_BLOCK9_W1_V << OTP_DEBUG_BLOCK9_W1_S)
-#define OTP_DEBUG_BLOCK9_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W1_S  0
-
-/** OTP_DEBUG_BLK9_W2_REG register
- *  Otp debuger block9 data register2.
- */
-#define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0)
-/** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word2 data.
- */
-#define OTP_DEBUG_BLOCK9_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W2_M  (OTP_DEBUG_BLOCK9_W2_V << OTP_DEBUG_BLOCK9_W2_S)
-#define OTP_DEBUG_BLOCK9_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W2_S  0
-
-/** OTP_DEBUG_BLK9_W3_REG register
- *  Otp debuger block9 data register3.
- */
-#define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4)
-/** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word3 data.
- */
-#define OTP_DEBUG_BLOCK9_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W3_M  (OTP_DEBUG_BLOCK9_W3_V << OTP_DEBUG_BLOCK9_W3_S)
-#define OTP_DEBUG_BLOCK9_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W3_S  0
-
-/** OTP_DEBUG_BLK9_W4_REG register
- *  Otp debuger block9 data register4.
- */
-#define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8)
-/** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word4 data.
- */
-#define OTP_DEBUG_BLOCK9_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W4_M  (OTP_DEBUG_BLOCK9_W4_V << OTP_DEBUG_BLOCK9_W4_S)
-#define OTP_DEBUG_BLOCK9_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W4_S  0
-
-/** OTP_DEBUG_BLK9_W5_REG register
- *  Otp debuger block9 data register5.
- */
-#define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc)
-/** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word5 data.
- */
-#define OTP_DEBUG_BLOCK9_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W5_M  (OTP_DEBUG_BLOCK9_W5_V << OTP_DEBUG_BLOCK9_W5_S)
-#define OTP_DEBUG_BLOCK9_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W5_S  0
-
-/** OTP_DEBUG_BLK9_W6_REG register
- *  Otp debuger block9 data register6.
- */
-#define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0)
-/** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word6 data.
- */
-#define OTP_DEBUG_BLOCK9_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W6_M  (OTP_DEBUG_BLOCK9_W6_V << OTP_DEBUG_BLOCK9_W6_S)
-#define OTP_DEBUG_BLOCK9_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W6_S  0
-
-/** OTP_DEBUG_BLK9_W7_REG register
- *  Otp debuger block9 data register7.
- */
-#define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4)
-/** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word7 data.
- */
-#define OTP_DEBUG_BLOCK9_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W7_M  (OTP_DEBUG_BLOCK9_W7_V << OTP_DEBUG_BLOCK9_W7_S)
-#define OTP_DEBUG_BLOCK9_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W7_S  0
-
-/** OTP_DEBUG_BLK9_W8_REG register
- *  Otp debuger block9 data register8.
- */
-#define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8)
-/** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word8 data.
- */
-#define OTP_DEBUG_BLOCK9_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W8_M  (OTP_DEBUG_BLOCK9_W8_V << OTP_DEBUG_BLOCK9_W8_S)
-#define OTP_DEBUG_BLOCK9_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W8_S  0
-
-/** OTP_DEBUG_BLK9_W9_REG register
- *  Otp debuger block9 data register9.
- */
-#define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc)
-/** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word9 data.
- */
-#define OTP_DEBUG_BLOCK9_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W9_M  (OTP_DEBUG_BLOCK9_W9_V << OTP_DEBUG_BLOCK9_W9_S)
-#define OTP_DEBUG_BLOCK9_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W9_S  0
-
-/** OTP_DEBUG_BLK9_W10_REG register
- *  Otp debuger block9 data register10.
- */
-#define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0)
-/** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word10 data.
- */
-#define OTP_DEBUG_BLOCK9_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W10_M  (OTP_DEBUG_BLOCK9_W10_V << OTP_DEBUG_BLOCK9_W10_S)
-#define OTP_DEBUG_BLOCK9_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W10_S  0
-
-/** OTP_DEBUG_BLK9_W11_REG register
- *  Otp debuger block9 data register11.
- */
-#define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4)
-/** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word11 data.
- */
-#define OTP_DEBUG_BLOCK9_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W11_M  (OTP_DEBUG_BLOCK9_W11_V << OTP_DEBUG_BLOCK9_W11_S)
-#define OTP_DEBUG_BLOCK9_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W11_S  0
-
-/** OTP_DEBUG_BLK10_W1_REG register
- *  Otp debuger block10 data register1.
- */
-#define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8)
-/** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word1 data.
- */
-#define OTP_DEBUG_BLOCK10_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W1_M  (OTP_DEBUG_BLOCK10_W1_V << OTP_DEBUG_BLOCK10_W1_S)
-#define OTP_DEBUG_BLOCK10_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W1_S  0
-
-/** OTP_DEBUG_BLK10_W2_REG register
- *  Otp debuger block10 data register2.
- */
-#define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc)
-/** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word2 data.
- */
-#define OTP_DEBUG_BLOCK10_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W2_M  (OTP_DEBUG_BLOCK10_W2_V << OTP_DEBUG_BLOCK10_W2_S)
-#define OTP_DEBUG_BLOCK10_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W2_S  0
-
-/** OTP_DEBUG_BLK10_W3_REG register
- *  Otp debuger block10 data register3.
- */
-#define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0)
-/** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word3 data.
- */
-#define OTP_DEBUG_BLOCK10_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W3_M  (OTP_DEBUG_BLOCK10_W3_V << OTP_DEBUG_BLOCK10_W3_S)
-#define OTP_DEBUG_BLOCK10_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W3_S  0
-
-/** OTP_DEBUG_BLK10_W4_REG register
- *  Otp debuger block10 data register4.
- */
-#define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4)
-/** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word4 data.
- */
-#define OTP_DEBUG_BLOCK10_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W4_M  (OTP_DEBUG_BLOCK10_W4_V << OTP_DEBUG_BLOCK10_W4_S)
-#define OTP_DEBUG_BLOCK10_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W4_S  0
-
-/** OTP_DEBUG_BLK10_W5_REG register
- *  Otp debuger block10 data register5.
- */
-#define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8)
-/** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word5 data.
- */
-#define OTP_DEBUG_BLOCK10_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W5_M  (OTP_DEBUG_BLOCK10_W5_V << OTP_DEBUG_BLOCK10_W5_S)
-#define OTP_DEBUG_BLOCK10_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W5_S  0
-
-/** OTP_DEBUG_BLK10_W6_REG register
- *  Otp debuger block10 data register6.
- */
-#define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec)
-/** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word6 data.
- */
-#define OTP_DEBUG_BLOCK10_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W6_M  (OTP_DEBUG_BLOCK10_W6_V << OTP_DEBUG_BLOCK10_W6_S)
-#define OTP_DEBUG_BLOCK10_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W6_S  0
-
-/** OTP_DEBUG_BLK10_W7_REG register
- *  Otp debuger block10 data register7.
- */
-#define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0)
-/** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word7 data.
- */
-#define OTP_DEBUG_BLOCK10_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W7_M  (OTP_DEBUG_BLOCK10_W7_V << OTP_DEBUG_BLOCK10_W7_S)
-#define OTP_DEBUG_BLOCK10_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W7_S  0
-
-/** OTP_DEBUG_BLK10_W8_REG register
- *  Otp debuger block10 data register8.
- */
-#define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4)
-/** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word8 data.
- */
-#define OTP_DEBUG_BLOCK10_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W8_M  (OTP_DEBUG_BLOCK10_W8_V << OTP_DEBUG_BLOCK10_W8_S)
-#define OTP_DEBUG_BLOCK10_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W8_S  0
-
-/** OTP_DEBUG_BLK10_W9_REG register
- *  Otp debuger block10 data register9.
- */
-#define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8)
-/** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word9 data.
- */
-#define OTP_DEBUG_BLOCK10_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W9_M  (OTP_DEBUG_BLOCK10_W9_V << OTP_DEBUG_BLOCK10_W9_S)
-#define OTP_DEBUG_BLOCK10_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W9_S  0
-
-/** OTP_DEBUG_BLK10_W10_REG register
- *  Otp debuger block10 data register10.
- */
-#define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc)
-/** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word10 data.
- */
-#define OTP_DEBUG_BLOCK19_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK19_W10_M  (OTP_DEBUG_BLOCK19_W10_V << OTP_DEBUG_BLOCK19_W10_S)
-#define OTP_DEBUG_BLOCK19_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK19_W10_S  0
-
-/** OTP_DEBUG_BLK10_W11_REG register
- *  Otp debuger block10 data register11.
- */
-#define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200)
-/** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word11 data.
- */
-#define OTP_DEBUG_BLOCK10_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W11_M  (OTP_DEBUG_BLOCK10_W11_V << OTP_DEBUG_BLOCK10_W11_S)
-#define OTP_DEBUG_BLOCK10_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W11_S  0
-
-/** OTP_DEBUG_CLK_REG register
- *  Otp debuger clk_en configuration register.
- */
-#define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204)
-/** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Force clock on for this register file.
- */
-#define OTP_DEBUG_CLK_EN    (BIT(0))
-#define OTP_DEBUG_CLK_EN_M  (OTP_DEBUG_CLK_EN_V << OTP_DEBUG_CLK_EN_S)
-#define OTP_DEBUG_CLK_EN_V  0x00000001U
-#define OTP_DEBUG_CLK_EN_S  0
-
-/** OTP_DEBUG_APB2OTP_EN_REG register
- *  Otp_debuger apb2otp enable configuration register.
- */
-#define OTP_DEBUG_APB2OTP_EN_REG (DR_REG_OTP_DEBUG_BASE + 0x208)
-/** OTP_DEBUG_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
- *  Debug mode enable signal.
- */
-#define OTP_DEBUG_APB2OTP_EN    (BIT(0))
-#define OTP_DEBUG_APB2OTP_EN_M  (OTP_DEBUG_APB2OTP_EN_V << OTP_DEBUG_APB2OTP_EN_S)
-#define OTP_DEBUG_APB2OTP_EN_V  0x00000001U
-#define OTP_DEBUG_APB2OTP_EN_S  0
-
-/** OTP_DEBUG_DATE_REG register
- *  eFuse version register.
- */
-#define OTP_DEBUG_DATE_REG (DR_REG_OTP_DEBUG_BASE + 0x20c)
-/** OTP_DEBUG_DATE : R/W; bitpos: [27:0]; default: 539037736;
- *  Stores otp_debug version.
- */
-#define OTP_DEBUG_DATE    0x0FFFFFFFU
-#define OTP_DEBUG_DATE_M  (OTP_DEBUG_DATE_V << OTP_DEBUG_DATE_S)
-#define OTP_DEBUG_DATE_V  0x0FFFFFFFU
-#define OTP_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/otp_debug_struct.h b/components/soc/esp32p4/include/soc/otp_debug_struct.h
deleted file mode 100644
index 8166a857cb..0000000000
--- a/components/soc/esp32p4/include/soc/otp_debug_struct.h
+++ /dev/null
@@ -1,2137 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: OTP_DEBUG Block0 Write Disable Data */
-/** Type of wr_dis register
- *  Otp debuger block0 data register1.
- */
-typedef union {
-    struct {
-        /** block0_wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 write disable data.
-         */
-        uint32_t block0_wr_dis:32;
-    };
-    uint32_t val;
-} otp_debug_wr_dis_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word1 Data */
-/** Type of blk0_backup1_w1 register
- *  Otp debuger block0 data register2.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word1 data.
-         */
-        uint32_t block0_backup1_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word2 Data */
-/** Type of blk0_backup1_w2 register
- *  Otp debuger block0 data register3.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word2 data.
-         */
-        uint32_t block0_backup1_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word3 Data */
-/** Type of blk0_backup1_w3 register
- *  Otp debuger block0 data register4.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word3 data.
-         */
-        uint32_t block0_backup1_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word4 Data */
-/** Type of blk0_backup1_w4 register
- *  Otp debuger block0 data register5.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word4 data.
-         */
-        uint32_t block0_backup1_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word5 Data */
-/** Type of blk0_backup1_w5 register
- *  Otp debuger block0 data register6.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word5 data.
-         */
-        uint32_t block0_backup1_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word1 Data */
-/** Type of blk0_backup2_w1 register
- *  Otp debuger block0 data register7.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word1 data.
-         */
-        uint32_t block0_backup2_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word2 Data */
-/** Type of blk0_backup2_w2 register
- *  Otp debuger block0 data register8.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word2 data.
-         */
-        uint32_t block0_backup2_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word3 Data */
-/** Type of blk0_backup2_w3 register
- *  Otp debuger block0 data register9.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word3 data.
-         */
-        uint32_t block0_backup2_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word4 Data */
-/** Type of blk0_backup2_w4 register
- *  Otp debuger block0 data register10.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word4 data.
-         */
-        uint32_t block0_backup2_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word5 Data */
-/** Type of blk0_backup2_w5 register
- *  Otp debuger block0 data register11.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word5 data.
-         */
-        uint32_t block0_backup2_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word1 Data */
-/** Type of blk0_backup3_w1 register
- *  Otp debuger block0 data register12.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word1 data.
-         */
-        uint32_t block0_backup3_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word2 Data */
-/** Type of blk0_backup3_w2 register
- *  Otp debuger block0 data register13.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word2 data.
-         */
-        uint32_t block0_backup3_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word3 Data */
-/** Type of blk0_backup3_w3 register
- *  Otp debuger block0 data register14.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word3 data.
-         */
-        uint32_t block0_backup3_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word4 Data */
-/** Type of blk0_backup3_w4 register
- *  Otp debuger block0 data register15.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word4 data.
-         */
-        uint32_t block0_backup3_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word5 Data */
-/** Type of blk0_backup3_w5 register
- *  Otp debuger block0 data register16.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word5 data.
-         */
-        uint32_t block0_backup3_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word1 Data */
-/** Type of blk0_backup4_w1 register
- *  Otp debuger block0 data register17.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word1 data.
-         */
-        uint32_t block0_backup4_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word2 Data */
-/** Type of blk0_backup4_w2 register
- *  Otp debuger block0 data register18.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word2 data.
-         */
-        uint32_t block0_backup4_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word3 Data */
-/** Type of blk0_backup4_w3 register
- *  Otp debuger block0 data register19.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word3 data.
-         */
-        uint32_t block0_backup4_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word4 Data */
-/** Type of blk0_backup4_w4 register
- *  Otp debuger block0 data register20.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word4 data.
-         */
-        uint32_t block0_backup4_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word5 Data */
-/** Type of blk0_backup4_w5 register
- *  Otp debuger block0 data register21.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word5 data.
-         */
-        uint32_t block0_backup4_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word1 Data */
-/** Type of blk1_w1 register
- *  Otp debuger block1 data register1.
- */
-typedef union {
-    struct {
-        /** block1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word1 data.
-         */
-        uint32_t block1_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word2 Data */
-/** Type of blk1_w2 register
- *  Otp debuger block1 data register2.
- */
-typedef union {
-    struct {
-        /** block1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word2 data.
-         */
-        uint32_t block1_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word3 Data */
-/** Type of blk1_w3 register
- *  Otp debuger block1 data register3.
- */
-typedef union {
-    struct {
-        /** block1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word3 data.
-         */
-        uint32_t block1_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word4 Data */
-/** Type of blk1_w4 register
- *  Otp debuger block1 data register4.
- */
-typedef union {
-    struct {
-        /** block1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word4 data.
-         */
-        uint32_t block1_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word5 Data */
-/** Type of blk1_w5 register
- *  Otp debuger block1 data register5.
- */
-typedef union {
-    struct {
-        /** block1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word5 data.
-         */
-        uint32_t block1_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word6 Data */
-/** Type of blk1_w6 register
- *  Otp debuger block1 data register6.
- */
-typedef union {
-    struct {
-        /** block1_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word6 data.
-         */
-        uint32_t block1_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word7 Data */
-/** Type of blk1_w7 register
- *  Otp debuger block1 data register7.
- */
-typedef union {
-    struct {
-        /** block1_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word7 data.
-         */
-        uint32_t block1_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word8 Data */
-/** Type of blk1_w8 register
- *  Otp debuger block1 data register8.
- */
-typedef union {
-    struct {
-        /** block1_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word8 data.
-         */
-        uint32_t block1_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word9 Data */
-/** Type of blk1_w9 register
- *  Otp debuger block1 data register9.
- */
-typedef union {
-    struct {
-        /** block1_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word9 data.
-         */
-        uint32_t block1_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word1 Data */
-/** Type of blk2_w1 register
- *  Otp debuger block2 data register1.
- */
-typedef union {
-    struct {
-        /** block2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word1 data.
-         */
-        uint32_t block2_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word2 Data */
-/** Type of blk2_w2 register
- *  Otp debuger block2 data register2.
- */
-typedef union {
-    struct {
-        /** block2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word2 data.
-         */
-        uint32_t block2_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word3 Data */
-/** Type of blk2_w3 register
- *  Otp debuger block2 data register3.
- */
-typedef union {
-    struct {
-        /** block2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word3 data.
-         */
-        uint32_t block2_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word4 Data */
-/** Type of blk2_w4 register
- *  Otp debuger block2 data register4.
- */
-typedef union {
-    struct {
-        /** block2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word4 data.
-         */
-        uint32_t block2_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word5 Data */
-/** Type of blk2_w5 register
- *  Otp debuger block2 data register5.
- */
-typedef union {
-    struct {
-        /** block2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word5 data.
-         */
-        uint32_t block2_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word6 Data */
-/** Type of blk2_w6 register
- *  Otp debuger block2 data register6.
- */
-typedef union {
-    struct {
-        /** block2_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word6 data.
-         */
-        uint32_t block2_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word7 Data */
-/** Type of blk2_w7 register
- *  Otp debuger block2 data register7.
- */
-typedef union {
-    struct {
-        /** block2_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word7 data.
-         */
-        uint32_t block2_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word8 Data */
-/** Type of blk2_w8 register
- *  Otp debuger block2 data register8.
- */
-typedef union {
-    struct {
-        /** block2_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word8 data.
-         */
-        uint32_t block2_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word9 Data */
-/** Type of blk2_w9 register
- *  Otp debuger block2 data register9.
- */
-typedef union {
-    struct {
-        /** block2_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word9 data.
-         */
-        uint32_t block2_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word10 Data */
-/** Type of blk2_w10 register
- *  Otp debuger block2 data register10.
- */
-typedef union {
-    struct {
-        /** block2_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word10 data.
-         */
-        uint32_t block2_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word11 Data */
-/** Type of blk2_w11 register
- *  Otp debuger block2 data register11.
- */
-typedef union {
-    struct {
-        /** block2_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word11 data.
-         */
-        uint32_t block2_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w11_reg_t;
-
-/** Type of blk10_w11 register
- *  Otp debuger block10 data register11.
- */
-typedef union {
-    struct {
-        /** block10_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word11 data.
-         */
-        uint32_t block10_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word1 Data */
-/** Type of blk3_w1 register
- *  Otp debuger block3 data register1.
- */
-typedef union {
-    struct {
-        /** block3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word1 data.
-         */
-        uint32_t block3_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word2 Data */
-/** Type of blk3_w2 register
- *  Otp debuger block3 data register2.
- */
-typedef union {
-    struct {
-        /** block3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word2 data.
-         */
-        uint32_t block3_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word3 Data */
-/** Type of blk3_w3 register
- *  Otp debuger block3 data register3.
- */
-typedef union {
-    struct {
-        /** block3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word3 data.
-         */
-        uint32_t block3_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word4 Data */
-/** Type of blk3_w4 register
- *  Otp debuger block3 data register4.
- */
-typedef union {
-    struct {
-        /** block3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word4 data.
-         */
-        uint32_t block3_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word5 Data */
-/** Type of blk3_w5 register
- *  Otp debuger block3 data register5.
- */
-typedef union {
-    struct {
-        /** block3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word5 data.
-         */
-        uint32_t block3_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word6 Data */
-/** Type of blk3_w6 register
- *  Otp debuger block3 data register6.
- */
-typedef union {
-    struct {
-        /** block3_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word6 data.
-         */
-        uint32_t block3_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word7 Data */
-/** Type of blk3_w7 register
- *  Otp debuger block3 data register7.
- */
-typedef union {
-    struct {
-        /** block3_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word7 data.
-         */
-        uint32_t block3_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word8 Data */
-/** Type of blk3_w8 register
- *  Otp debuger block3 data register8.
- */
-typedef union {
-    struct {
-        /** block3_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word8 data.
-         */
-        uint32_t block3_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word9 Data */
-/** Type of blk3_w9 register
- *  Otp debuger block3 data register9.
- */
-typedef union {
-    struct {
-        /** block3_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word9 data.
-         */
-        uint32_t block3_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word10 Data */
-/** Type of blk3_w10 register
- *  Otp debuger block3 data register10.
- */
-typedef union {
-    struct {
-        /** block3_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word10 data.
-         */
-        uint32_t block3_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word11 Data */
-/** Type of blk3_w11 register
- *  Otp debuger block3 data register11.
- */
-typedef union {
-    struct {
-        /** block3_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word11 data.
-         */
-        uint32_t block3_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word1 Data */
-/** Type of blk4_w1 register
- *  Otp debuger block4 data register1.
- */
-typedef union {
-    struct {
-        /** block4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word1 data.
-         */
-        uint32_t block4_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word2 Data */
-/** Type of blk4_w2 register
- *  Otp debuger block4 data register2.
- */
-typedef union {
-    struct {
-        /** block4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word2 data.
-         */
-        uint32_t block4_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word3 Data */
-/** Type of blk4_w3 register
- *  Otp debuger block4 data register3.
- */
-typedef union {
-    struct {
-        /** block4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word3 data.
-         */
-        uint32_t block4_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word4 Data */
-/** Type of blk4_w4 register
- *  Otp debuger block4 data register4.
- */
-typedef union {
-    struct {
-        /** block4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word4 data.
-         */
-        uint32_t block4_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word5 Data */
-/** Type of blk4_w5 register
- *  Otp debuger block4 data register5.
- */
-typedef union {
-    struct {
-        /** block4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word5 data.
-         */
-        uint32_t block4_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word6 Data */
-/** Type of blk4_w6 register
- *  Otp debuger block4 data register6.
- */
-typedef union {
-    struct {
-        /** block4_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word6 data.
-         */
-        uint32_t block4_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word7 Data */
-/** Type of blk4_w7 register
- *  Otp debuger block4 data register7.
- */
-typedef union {
-    struct {
-        /** block4_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word7 data.
-         */
-        uint32_t block4_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word8 Data */
-/** Type of blk4_w8 register
- *  Otp debuger block4 data register8.
- */
-typedef union {
-    struct {
-        /** block4_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word8 data.
-         */
-        uint32_t block4_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word9 Data */
-/** Type of blk4_w9 register
- *  Otp debuger block4 data register9.
- */
-typedef union {
-    struct {
-        /** block4_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word9 data.
-         */
-        uint32_t block4_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word10 Data */
-/** Type of blk4_w10 register
- *  Otp debuger block4 data registe10.
- */
-typedef union {
-    struct {
-        /** block4_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word10 data.
-         */
-        uint32_t block4_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word11 Data */
-/** Type of blk4_w11 register
- *  Otp debuger block4 data register11.
- */
-typedef union {
-    struct {
-        /** block4_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word11 data.
-         */
-        uint32_t block4_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word1 Data */
-/** Type of blk5_w1 register
- *  Otp debuger block5 data register1.
- */
-typedef union {
-    struct {
-        /** block5_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word1 data.
-         */
-        uint32_t block5_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word2 Data */
-/** Type of blk5_w2 register
- *  Otp debuger block5 data register2.
- */
-typedef union {
-    struct {
-        /** block5_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word2 data.
-         */
-        uint32_t block5_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word3 Data */
-/** Type of blk5_w3 register
- *  Otp debuger block5 data register3.
- */
-typedef union {
-    struct {
-        /** block5_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word3 data.
-         */
-        uint32_t block5_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word4 Data */
-/** Type of blk5_w4 register
- *  Otp debuger block5 data register4.
- */
-typedef union {
-    struct {
-        /** block5_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word4 data.
-         */
-        uint32_t block5_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word5 Data */
-/** Type of blk5_w5 register
- *  Otp debuger block5 data register5.
- */
-typedef union {
-    struct {
-        /** block5_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word5 data.
-         */
-        uint32_t block5_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word6 Data */
-/** Type of blk5_w6 register
- *  Otp debuger block5 data register6.
- */
-typedef union {
-    struct {
-        /** block5_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word6 data.
-         */
-        uint32_t block5_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word7 Data */
-/** Type of blk5_w7 register
- *  Otp debuger block5 data register7.
- */
-typedef union {
-    struct {
-        /** block5_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word7 data.
-         */
-        uint32_t block5_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word8 Data */
-/** Type of blk5_w8 register
- *  Otp debuger block5 data register8.
- */
-typedef union {
-    struct {
-        /** block5_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word8 data.
-         */
-        uint32_t block5_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word9 Data */
-/** Type of blk5_w9 register
- *  Otp debuger block5 data register9.
- */
-typedef union {
-    struct {
-        /** block5_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word9 data.
-         */
-        uint32_t block5_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word10 Data */
-/** Type of blk5_w10 register
- *  Otp debuger block5 data register10.
- */
-typedef union {
-    struct {
-        /** block5_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word10 data.
-         */
-        uint32_t block5_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word11 Data */
-/** Type of blk5_w11 register
- *  Otp debuger block5 data register11.
- */
-typedef union {
-    struct {
-        /** block5_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word11 data.
-         */
-        uint32_t block5_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word1 Data */
-/** Type of blk6_w1 register
- *  Otp debuger block6 data register1.
- */
-typedef union {
-    struct {
-        /** block6_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word1 data.
-         */
-        uint32_t block6_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word2 Data */
-/** Type of blk6_w2 register
- *  Otp debuger block6 data register2.
- */
-typedef union {
-    struct {
-        /** block6_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word2 data.
-         */
-        uint32_t block6_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word3 Data */
-/** Type of blk6_w3 register
- *  Otp debuger block6 data register3.
- */
-typedef union {
-    struct {
-        /** block6_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word3 data.
-         */
-        uint32_t block6_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word4 Data */
-/** Type of blk6_w4 register
- *  Otp debuger block6 data register4.
- */
-typedef union {
-    struct {
-        /** block6_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word4 data.
-         */
-        uint32_t block6_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word5 Data */
-/** Type of blk6_w5 register
- *  Otp debuger block6 data register5.
- */
-typedef union {
-    struct {
-        /** block6_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word5 data.
-         */
-        uint32_t block6_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word6 Data */
-/** Type of blk6_w6 register
- *  Otp debuger block6 data register6.
- */
-typedef union {
-    struct {
-        /** block6_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word6 data.
-         */
-        uint32_t block6_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word7 Data */
-/** Type of blk6_w7 register
- *  Otp debuger block6 data register7.
- */
-typedef union {
-    struct {
-        /** block6_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word7 data.
-         */
-        uint32_t block6_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word8 Data */
-/** Type of blk6_w8 register
- *  Otp debuger block6 data register8.
- */
-typedef union {
-    struct {
-        /** block6_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word8 data.
-         */
-        uint32_t block6_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word9 Data */
-/** Type of blk6_w9 register
- *  Otp debuger block6 data register9.
- */
-typedef union {
-    struct {
-        /** block6_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word9 data.
-         */
-        uint32_t block6_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word10 Data */
-/** Type of blk6_w10 register
- *  Otp debuger block6 data register10.
- */
-typedef union {
-    struct {
-        /** block6_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word10 data.
-         */
-        uint32_t block6_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word11 Data */
-/** Type of blk6_w11 register
- *  Otp debuger block6 data register11.
- */
-typedef union {
-    struct {
-        /** block6_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word11 data.
-         */
-        uint32_t block6_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word1 Data */
-/** Type of blk7_w1 register
- *  Otp debuger block7 data register1.
- */
-typedef union {
-    struct {
-        /** block7_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word1 data.
-         */
-        uint32_t block7_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word2 Data */
-/** Type of blk7_w2 register
- *  Otp debuger block7 data register2.
- */
-typedef union {
-    struct {
-        /** block7_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word2 data.
-         */
-        uint32_t block7_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word3 Data */
-/** Type of blk7_w3 register
- *  Otp debuger block7 data register3.
- */
-typedef union {
-    struct {
-        /** block7_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word3 data.
-         */
-        uint32_t block7_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word4 Data */
-/** Type of blk7_w4 register
- *  Otp debuger block7 data register4.
- */
-typedef union {
-    struct {
-        /** block7_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word4 data.
-         */
-        uint32_t block7_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word5 Data */
-/** Type of blk7_w5 register
- *  Otp debuger block7 data register5.
- */
-typedef union {
-    struct {
-        /** block7_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word5 data.
-         */
-        uint32_t block7_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word6 Data */
-/** Type of blk7_w6 register
- *  Otp debuger block7 data register6.
- */
-typedef union {
-    struct {
-        /** block7_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word6 data.
-         */
-        uint32_t block7_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word7 Data */
-/** Type of blk7_w7 register
- *  Otp debuger block7 data register7.
- */
-typedef union {
-    struct {
-        /** block7_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word7 data.
-         */
-        uint32_t block7_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word8 Data */
-/** Type of blk7_w8 register
- *  Otp debuger block7 data register8.
- */
-typedef union {
-    struct {
-        /** block7_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word8 data.
-         */
-        uint32_t block7_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word9 Data */
-/** Type of blk7_w9 register
- *  Otp debuger block7 data register9.
- */
-typedef union {
-    struct {
-        /** block7_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word9 data.
-         */
-        uint32_t block7_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word10 Data */
-/** Type of blk7_w10 register
- *  Otp debuger block7 data register10.
- */
-typedef union {
-    struct {
-        /** block7_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word10 data.
-         */
-        uint32_t block7_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word11 Data */
-/** Type of blk7_w11 register
- *  Otp debuger block7 data register11.
- */
-typedef union {
-    struct {
-        /** block7_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word11 data.
-         */
-        uint32_t block7_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word1 Data */
-/** Type of blk8_w1 register
- *  Otp debuger block8 data register1.
- */
-typedef union {
-    struct {
-        /** block8_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word1 data.
-         */
-        uint32_t block8_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word2 Data */
-/** Type of blk8_w2 register
- *  Otp debuger block8 data register2.
- */
-typedef union {
-    struct {
-        /** block8_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word2 data.
-         */
-        uint32_t block8_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word3 Data */
-/** Type of blk8_w3 register
- *  Otp debuger block8 data register3.
- */
-typedef union {
-    struct {
-        /** block8_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word3 data.
-         */
-        uint32_t block8_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word4 Data */
-/** Type of blk8_w4 register
- *  Otp debuger block8 data register4.
- */
-typedef union {
-    struct {
-        /** block8_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word4 data.
-         */
-        uint32_t block8_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word5 Data */
-/** Type of blk8_w5 register
- *  Otp debuger block8 data register5.
- */
-typedef union {
-    struct {
-        /** block8_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word5 data.
-         */
-        uint32_t block8_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word6 Data */
-/** Type of blk8_w6 register
- *  Otp debuger block8 data register6.
- */
-typedef union {
-    struct {
-        /** block8_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word6 data.
-         */
-        uint32_t block8_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word7 Data */
-/** Type of blk8_w7 register
- *  Otp debuger block8 data register7.
- */
-typedef union {
-    struct {
-        /** block8_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word7 data.
-         */
-        uint32_t block8_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word8 Data */
-/** Type of blk8_w8 register
- *  Otp debuger block8 data register8.
- */
-typedef union {
-    struct {
-        /** block8_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word8 data.
-         */
-        uint32_t block8_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word9 Data */
-/** Type of blk8_w9 register
- *  Otp debuger block8 data register9.
- */
-typedef union {
-    struct {
-        /** block8_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word9 data.
-         */
-        uint32_t block8_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word10 Data */
-/** Type of blk8_w10 register
- *  Otp debuger block8 data register10.
- */
-typedef union {
-    struct {
-        /** block8_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word10 data.
-         */
-        uint32_t block8_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word11 Data */
-/** Type of blk8_w11 register
- *  Otp debuger block8 data register11.
- */
-typedef union {
-    struct {
-        /** block8_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word11 data.
-         */
-        uint32_t block8_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word1 Data */
-/** Type of blk9_w1 register
- *  Otp debuger block9 data register1.
- */
-typedef union {
-    struct {
-        /** block9_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word1 data.
-         */
-        uint32_t block9_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word2 Data */
-/** Type of blk9_w2 register
- *  Otp debuger block9 data register2.
- */
-typedef union {
-    struct {
-        /** block9_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word2 data.
-         */
-        uint32_t block9_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word3 Data */
-/** Type of blk9_w3 register
- *  Otp debuger block9 data register3.
- */
-typedef union {
-    struct {
-        /** block9_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word3 data.
-         */
-        uint32_t block9_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word4 Data */
-/** Type of blk9_w4 register
- *  Otp debuger block9 data register4.
- */
-typedef union {
-    struct {
-        /** block9_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word4 data.
-         */
-        uint32_t block9_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word5 Data */
-/** Type of blk9_w5 register
- *  Otp debuger block9 data register5.
- */
-typedef union {
-    struct {
-        /** block9_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word5 data.
-         */
-        uint32_t block9_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word6 Data */
-/** Type of blk9_w6 register
- *  Otp debuger block9 data register6.
- */
-typedef union {
-    struct {
-        /** block9_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word6 data.
-         */
-        uint32_t block9_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word7 Data */
-/** Type of blk9_w7 register
- *  Otp debuger block9 data register7.
- */
-typedef union {
-    struct {
-        /** block9_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word7 data.
-         */
-        uint32_t block9_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word8 Data */
-/** Type of blk9_w8 register
- *  Otp debuger block9 data register8.
- */
-typedef union {
-    struct {
-        /** block9_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word8 data.
-         */
-        uint32_t block9_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word9 Data */
-/** Type of blk9_w9 register
- *  Otp debuger block9 data register9.
- */
-typedef union {
-    struct {
-        /** block9_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word9 data.
-         */
-        uint32_t block9_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word10 Data */
-/** Type of blk9_w10 register
- *  Otp debuger block9 data register10.
- */
-typedef union {
-    struct {
-        /** block9_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word10 data.
-         */
-        uint32_t block9_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word11 Data */
-/** Type of blk9_w11 register
- *  Otp debuger block9 data register11.
- */
-typedef union {
-    struct {
-        /** block9_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word11 data.
-         */
-        uint32_t block9_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word1 Data */
-/** Type of blk10_w1 register
- *  Otp debuger block10 data register1.
- */
-typedef union {
-    struct {
-        /** block10_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word1 data.
-         */
-        uint32_t block10_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word2 Data */
-/** Type of blk10_w2 register
- *  Otp debuger block10 data register2.
- */
-typedef union {
-    struct {
-        /** block10_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word2 data.
-         */
-        uint32_t block10_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word3 Data */
-/** Type of blk10_w3 register
- *  Otp debuger block10 data register3.
- */
-typedef union {
-    struct {
-        /** block10_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word3 data.
-         */
-        uint32_t block10_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word4 Data */
-/** Type of blk10_w4 register
- *  Otp debuger block10 data register4.
- */
-typedef union {
-    struct {
-        /** block10_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word4 data.
-         */
-        uint32_t block10_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word5 Data */
-/** Type of blk10_w5 register
- *  Otp debuger block10 data register5.
- */
-typedef union {
-    struct {
-        /** block10_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word5 data.
-         */
-        uint32_t block10_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word6 Data */
-/** Type of blk10_w6 register
- *  Otp debuger block10 data register6.
- */
-typedef union {
-    struct {
-        /** block10_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word6 data.
-         */
-        uint32_t block10_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word7 Data */
-/** Type of blk10_w7 register
- *  Otp debuger block10 data register7.
- */
-typedef union {
-    struct {
-        /** block10_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word7 data.
-         */
-        uint32_t block10_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word8 Data */
-/** Type of blk10_w8 register
- *  Otp debuger block10 data register8.
- */
-typedef union {
-    struct {
-        /** block10_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word8 data.
-         */
-        uint32_t block10_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word9 Data */
-/** Type of blk10_w9 register
- *  Otp debuger block10 data register9.
- */
-typedef union {
-    struct {
-        /** block10_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word9 data.
-         */
-        uint32_t block10_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word10 Data */
-/** Type of blk10_w10 register
- *  Otp debuger block10 data register10.
- */
-typedef union {
-    struct {
-        /** block19_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word10 data.
-         */
-        uint32_t block19_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Clock_en Configuration Register */
-/** Type of clk register
- *  Otp debuger clk_en configuration register.
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Force clock on for this register file.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} otp_debug_clk_reg_t;
-
-
-/** Group: OTP_DEBUG Apb2otp Enable Singal */
-/** Type of apb2otp_en register
- *  Otp_debuger apb2otp enable configuration register.
- */
-typedef union {
-    struct {
-        /** apb2otp_en : R/W; bitpos: [0]; default: 0;
-         *  Debug mode enable signal.
-         */
-        uint32_t apb2otp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} otp_debug_apb2otp_en_reg_t;
-
-
-/** Group: OTP_DEBUG Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 539037736;
-         *  Stores otp_debug version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} otp_debug_date_reg_t;
-
-
-typedef struct otp_debug_dev_t {
-    volatile otp_debug_wr_dis_reg_t wr_dis;
-    volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1;
-    volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2;
-    volatile otp_debug_blk0_backup1_w3_reg_t blk0_backup1_w3;
-    volatile otp_debug_blk0_backup1_w4_reg_t blk0_backup1_w4;
-    volatile otp_debug_blk0_backup1_w5_reg_t blk0_backup1_w5;
-    volatile otp_debug_blk0_backup2_w1_reg_t blk0_backup2_w1;
-    volatile otp_debug_blk0_backup2_w2_reg_t blk0_backup2_w2;
-    volatile otp_debug_blk0_backup2_w3_reg_t blk0_backup2_w3;
-    volatile otp_debug_blk0_backup2_w4_reg_t blk0_backup2_w4;
-    volatile otp_debug_blk0_backup2_w5_reg_t blk0_backup2_w5;
-    volatile otp_debug_blk0_backup3_w1_reg_t blk0_backup3_w1;
-    volatile otp_debug_blk0_backup3_w2_reg_t blk0_backup3_w2;
-    volatile otp_debug_blk0_backup3_w3_reg_t blk0_backup3_w3;
-    volatile otp_debug_blk0_backup3_w4_reg_t blk0_backup3_w4;
-    volatile otp_debug_blk0_backup3_w5_reg_t blk0_backup3_w5;
-    volatile otp_debug_blk0_backup4_w1_reg_t blk0_backup4_w1;
-    volatile otp_debug_blk0_backup4_w2_reg_t blk0_backup4_w2;
-    volatile otp_debug_blk0_backup4_w3_reg_t blk0_backup4_w3;
-    volatile otp_debug_blk0_backup4_w4_reg_t blk0_backup4_w4;
-    volatile otp_debug_blk0_backup4_w5_reg_t blk0_backup4_w5;
-    volatile otp_debug_blk1_w1_reg_t blk1_w1;
-    volatile otp_debug_blk1_w2_reg_t blk1_w2;
-    volatile otp_debug_blk1_w3_reg_t blk1_w3;
-    volatile otp_debug_blk1_w4_reg_t blk1_w4;
-    volatile otp_debug_blk1_w5_reg_t blk1_w5;
-    volatile otp_debug_blk1_w6_reg_t blk1_w6;
-    volatile otp_debug_blk1_w7_reg_t blk1_w7;
-    volatile otp_debug_blk1_w8_reg_t blk1_w8;
-    volatile otp_debug_blk1_w9_reg_t blk1_w9;
-    volatile otp_debug_blk2_w1_reg_t blk2_w1;
-    volatile otp_debug_blk2_w2_reg_t blk2_w2;
-    volatile otp_debug_blk2_w3_reg_t blk2_w3;
-    volatile otp_debug_blk2_w4_reg_t blk2_w4;
-    volatile otp_debug_blk2_w5_reg_t blk2_w5;
-    volatile otp_debug_blk2_w6_reg_t blk2_w6;
-    volatile otp_debug_blk2_w7_reg_t blk2_w7;
-    volatile otp_debug_blk2_w8_reg_t blk2_w8;
-    volatile otp_debug_blk2_w9_reg_t blk2_w9;
-    volatile otp_debug_blk2_w10_reg_t blk2_w10;
-    volatile otp_debug_blk2_w11_reg_t blk2_w11;
-    volatile otp_debug_blk3_w1_reg_t blk3_w1;
-    volatile otp_debug_blk3_w2_reg_t blk3_w2;
-    volatile otp_debug_blk3_w3_reg_t blk3_w3;
-    volatile otp_debug_blk3_w4_reg_t blk3_w4;
-    volatile otp_debug_blk3_w5_reg_t blk3_w5;
-    volatile otp_debug_blk3_w6_reg_t blk3_w6;
-    volatile otp_debug_blk3_w7_reg_t blk3_w7;
-    volatile otp_debug_blk3_w8_reg_t blk3_w8;
-    volatile otp_debug_blk3_w9_reg_t blk3_w9;
-    volatile otp_debug_blk3_w10_reg_t blk3_w10;
-    volatile otp_debug_blk3_w11_reg_t blk3_w11;
-    volatile otp_debug_blk4_w1_reg_t blk4_w1;
-    volatile otp_debug_blk4_w2_reg_t blk4_w2;
-    volatile otp_debug_blk4_w3_reg_t blk4_w3;
-    volatile otp_debug_blk4_w4_reg_t blk4_w4;
-    volatile otp_debug_blk4_w5_reg_t blk4_w5;
-    volatile otp_debug_blk4_w6_reg_t blk4_w6;
-    volatile otp_debug_blk4_w7_reg_t blk4_w7;
-    volatile otp_debug_blk4_w8_reg_t blk4_w8;
-    volatile otp_debug_blk4_w9_reg_t blk4_w9;
-    volatile otp_debug_blk4_w10_reg_t blk4_w10;
-    volatile otp_debug_blk4_w11_reg_t blk4_w11;
-    volatile otp_debug_blk5_w1_reg_t blk5_w1;
-    volatile otp_debug_blk5_w2_reg_t blk5_w2;
-    volatile otp_debug_blk5_w3_reg_t blk5_w3;
-    volatile otp_debug_blk5_w4_reg_t blk5_w4;
-    volatile otp_debug_blk5_w5_reg_t blk5_w5;
-    volatile otp_debug_blk5_w6_reg_t blk5_w6;
-    volatile otp_debug_blk5_w7_reg_t blk5_w7;
-    volatile otp_debug_blk5_w8_reg_t blk5_w8;
-    volatile otp_debug_blk5_w9_reg_t blk5_w9;
-    volatile otp_debug_blk5_w10_reg_t blk5_w10;
-    volatile otp_debug_blk5_w11_reg_t blk5_w11;
-    volatile otp_debug_blk6_w1_reg_t blk6_w1;
-    volatile otp_debug_blk6_w2_reg_t blk6_w2;
-    volatile otp_debug_blk6_w3_reg_t blk6_w3;
-    volatile otp_debug_blk6_w4_reg_t blk6_w4;
-    volatile otp_debug_blk6_w5_reg_t blk6_w5;
-    volatile otp_debug_blk6_w6_reg_t blk6_w6;
-    volatile otp_debug_blk6_w7_reg_t blk6_w7;
-    volatile otp_debug_blk6_w8_reg_t blk6_w8;
-    volatile otp_debug_blk6_w9_reg_t blk6_w9;
-    volatile otp_debug_blk6_w10_reg_t blk6_w10;
-    volatile otp_debug_blk6_w11_reg_t blk6_w11;
-    volatile otp_debug_blk7_w1_reg_t blk7_w1;
-    volatile otp_debug_blk7_w2_reg_t blk7_w2;
-    volatile otp_debug_blk7_w3_reg_t blk7_w3;
-    volatile otp_debug_blk7_w4_reg_t blk7_w4;
-    volatile otp_debug_blk7_w5_reg_t blk7_w5;
-    volatile otp_debug_blk7_w6_reg_t blk7_w6;
-    volatile otp_debug_blk7_w7_reg_t blk7_w7;
-    volatile otp_debug_blk7_w8_reg_t blk7_w8;
-    volatile otp_debug_blk7_w9_reg_t blk7_w9;
-    volatile otp_debug_blk7_w10_reg_t blk7_w10;
-    volatile otp_debug_blk7_w11_reg_t blk7_w11;
-    volatile otp_debug_blk8_w1_reg_t blk8_w1;
-    volatile otp_debug_blk8_w2_reg_t blk8_w2;
-    volatile otp_debug_blk8_w3_reg_t blk8_w3;
-    volatile otp_debug_blk8_w4_reg_t blk8_w4;
-    volatile otp_debug_blk8_w5_reg_t blk8_w5;
-    volatile otp_debug_blk8_w6_reg_t blk8_w6;
-    volatile otp_debug_blk8_w7_reg_t blk8_w7;
-    volatile otp_debug_blk8_w8_reg_t blk8_w8;
-    volatile otp_debug_blk8_w9_reg_t blk8_w9;
-    volatile otp_debug_blk8_w10_reg_t blk8_w10;
-    volatile otp_debug_blk8_w11_reg_t blk8_w11;
-    volatile otp_debug_blk9_w1_reg_t blk9_w1;
-    volatile otp_debug_blk9_w2_reg_t blk9_w2;
-    volatile otp_debug_blk9_w3_reg_t blk9_w3;
-    volatile otp_debug_blk9_w4_reg_t blk9_w4;
-    volatile otp_debug_blk9_w5_reg_t blk9_w5;
-    volatile otp_debug_blk9_w6_reg_t blk9_w6;
-    volatile otp_debug_blk9_w7_reg_t blk9_w7;
-    volatile otp_debug_blk9_w8_reg_t blk9_w8;
-    volatile otp_debug_blk9_w9_reg_t blk9_w9;
-    volatile otp_debug_blk9_w10_reg_t blk9_w10;
-    volatile otp_debug_blk9_w11_reg_t blk9_w11;
-    volatile otp_debug_blk10_w1_reg_t blk10_w1;
-    volatile otp_debug_blk10_w2_reg_t blk10_w2;
-    volatile otp_debug_blk10_w3_reg_t blk10_w3;
-    volatile otp_debug_blk10_w4_reg_t blk10_w4;
-    volatile otp_debug_blk10_w5_reg_t blk10_w5;
-    volatile otp_debug_blk10_w6_reg_t blk10_w6;
-    volatile otp_debug_blk10_w7_reg_t blk10_w7;
-    volatile otp_debug_blk10_w8_reg_t blk10_w8;
-    volatile otp_debug_blk10_w9_reg_t blk10_w9;
-    volatile otp_debug_blk10_w10_reg_t blk10_w10;
-    volatile otp_debug_blk10_w11_reg_t blk10_w11;
-    volatile otp_debug_clk_reg_t clk;
-    volatile otp_debug_apb2otp_en_reg_t apb2otp_en;
-    volatile otp_debug_date_reg_t date;
-} otp_debug_dev_t;
-
-extern otp_debug_dev_t OTP_DEBUG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(otp_debug_dev_t) == 0x210, "Invalid size of otp_debug_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/parl_io_struct.h b/components/soc/esp32p4/include/soc/parl_io_struct.h
index 97c911c737..7c1693b9bc 100644
--- a/components/soc/esp32p4/include/soc/parl_io_struct.h
+++ b/components/soc/esp32p4/include/soc/parl_io_struct.h
@@ -472,7 +472,7 @@ typedef union {
 } parl_io_version_reg_t;
 
 
-typedef struct {
+typedef struct parl_io_dev_t {
     volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
     volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
     volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
diff --git a/components/soc/esp32p4/include/soc/pcr_reg.h b/components/soc/esp32p4/include/soc/pcr_reg.h
deleted file mode 100644
index 7209befa4a..0000000000
--- a/components/soc/esp32p4/include/soc/pcr_reg.h
+++ /dev/null
@@ -1,2065 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PCR_UART0_CONF_REG register
- *  UART0 configuration register
- */
-#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
-/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart0 apb clock
- */
-#define PCR_UART0_CLK_EN    (BIT(0))
-#define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
-#define PCR_UART0_CLK_EN_V  0x00000001U
-#define PCR_UART0_CLK_EN_S  0
-/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart0 module
- */
-#define PCR_UART0_RST_EN    (BIT(1))
-#define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
-#define PCR_UART0_RST_EN_V  0x00000001U
-#define PCR_UART0_RST_EN_S  1
-
-/** PCR_UART0_SCLK_CONF_REG register
- *  UART0_SCLK configuration register
- */
-#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
-/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_A    0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
-#define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_S  0
-/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_B    0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
-#define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_S  6
-/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
-#define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_S  12
-/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_UART0_SCLK_SEL    0x00000003U
-#define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
-#define PCR_UART0_SCLK_SEL_V  0x00000003U
-#define PCR_UART0_SCLK_SEL_S  20
-/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART0_SCLK_EN    (BIT(22))
-#define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
-#define PCR_UART0_SCLK_EN_V  0x00000001U
-#define PCR_UART0_SCLK_EN_S  22
-
-/** PCR_UART0_PD_CTRL_REG register
- *  UART0 power control register
- */
-#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
-/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
-#define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PU_S  1
-/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
-#define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PD_S  2
-
-/** PCR_UART1_CONF_REG register
- *  UART1 configuration register
- */
-#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
-/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart1 apb clock
- */
-#define PCR_UART1_CLK_EN    (BIT(0))
-#define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
-#define PCR_UART1_CLK_EN_V  0x00000001U
-#define PCR_UART1_CLK_EN_S  0
-/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart1 module
- */
-#define PCR_UART1_RST_EN    (BIT(1))
-#define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
-#define PCR_UART1_RST_EN_V  0x00000001U
-#define PCR_UART1_RST_EN_S  1
-
-/** PCR_UART1_SCLK_CONF_REG register
- *  UART1_SCLK configuration register
- */
-#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
-/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_A    0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
-#define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_S  0
-/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_B    0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
-#define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_S  6
-/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
-#define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_S  12
-/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_UART1_SCLK_SEL    0x00000003U
-#define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
-#define PCR_UART1_SCLK_SEL_V  0x00000003U
-#define PCR_UART1_SCLK_SEL_S  20
-/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART1_SCLK_EN    (BIT(22))
-#define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
-#define PCR_UART1_SCLK_EN_V  0x00000001U
-#define PCR_UART1_SCLK_EN_S  22
-
-/** PCR_UART1_PD_CTRL_REG register
- *  UART1 power control register
- */
-#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
-/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
-#define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PU_S  1
-/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
-#define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PD_S  2
-
-/** PCR_MSPI_CONF_REG register
- *  MSPI configuration register
- */
-#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
-/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mspi clock, include mspi pll clock
- */
-#define PCR_MSPI_CLK_EN    (BIT(0))
-#define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
-#define PCR_MSPI_CLK_EN_V  0x00000001U
-#define PCR_MSPI_CLK_EN_S  0
-/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mspi module
- */
-#define PCR_MSPI_RST_EN    (BIT(1))
-#define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
-#define PCR_MSPI_RST_EN_V  0x00000001U
-#define PCR_MSPI_RST_EN_S  1
-/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable mspi pll clock
- */
-#define PCR_MSPI_PLL_CLK_EN    (BIT(2))
-#define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
-#define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
-#define PCR_MSPI_PLL_CLK_EN_S  2
-
-/** PCR_MSPI_CLK_CONF_REG register
- *  MSPI_CLK configuration register
- */
-#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
-/** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
- *  low-speed clock-source such as XTAL/FOSC.
- */
-#define PCR_MSPI_FAST_LS_DIV_NUM    0x000000FFU
-#define PCR_MSPI_FAST_LS_DIV_NUM_M  (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S)
-#define PCR_MSPI_FAST_LS_DIV_NUM_V  0x000000FFU
-#define PCR_MSPI_FAST_LS_DIV_NUM_S  0
-/** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
- *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
- *  high-speed clock-source such as SPLL.
- */
-#define PCR_MSPI_FAST_HS_DIV_NUM    0x000000FFU
-#define PCR_MSPI_FAST_HS_DIV_NUM_M  (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S)
-#define PCR_MSPI_FAST_HS_DIV_NUM_V  0x000000FFU
-#define PCR_MSPI_FAST_HS_DIV_NUM_S  8
-
-/** PCR_I2C_CONF_REG register
- *  I2C configuration register
- */
-#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20)
-/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2c apb clock
- */
-#define PCR_I2C_CLK_EN    (BIT(0))
-#define PCR_I2C_CLK_EN_M  (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S)
-#define PCR_I2C_CLK_EN_V  0x00000001U
-#define PCR_I2C_CLK_EN_S  0
-/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2c module
- */
-#define PCR_I2C_RST_EN    (BIT(1))
-#define PCR_I2C_RST_EN_M  (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S)
-#define PCR_I2C_RST_EN_V  0x00000001U
-#define PCR_I2C_RST_EN_S  1
-
-/** PCR_I2C_SCLK_CONF_REG register
- *  I2C_SCLK configuration register
- */
-#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
-/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_A    0x0000003FU
-#define PCR_I2C_SCLK_DIV_A_M  (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S)
-#define PCR_I2C_SCLK_DIV_A_V  0x0000003FU
-#define PCR_I2C_SCLK_DIV_A_S  0
-/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_B    0x0000003FU
-#define PCR_I2C_SCLK_DIV_B_M  (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S)
-#define PCR_I2C_SCLK_DIV_B_V  0x0000003FU
-#define PCR_I2C_SCLK_DIV_B_S  6
-/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_NUM    0x000000FFU
-#define PCR_I2C_SCLK_DIV_NUM_M  (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S)
-#define PCR_I2C_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_I2C_SCLK_DIV_NUM_S  12
-/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_I2C_SCLK_SEL    (BIT(20))
-#define PCR_I2C_SCLK_SEL_M  (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S)
-#define PCR_I2C_SCLK_SEL_V  0x00000001U
-#define PCR_I2C_SCLK_SEL_S  20
-/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2c function clock
- */
-#define PCR_I2C_SCLK_EN    (BIT(22))
-#define PCR_I2C_SCLK_EN_M  (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S)
-#define PCR_I2C_SCLK_EN_V  0x00000001U
-#define PCR_I2C_SCLK_EN_S  22
-
-/** PCR_UHCI_CONF_REG register
- *  UHCI configuration register
- */
-#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28)
-/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uhci clock
- */
-#define PCR_UHCI_CLK_EN    (BIT(0))
-#define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
-#define PCR_UHCI_CLK_EN_V  0x00000001U
-#define PCR_UHCI_CLK_EN_S  0
-/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uhci module
- */
-#define PCR_UHCI_RST_EN    (BIT(1))
-#define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
-#define PCR_UHCI_RST_EN_V  0x00000001U
-#define PCR_UHCI_RST_EN_S  1
-
-/** PCR_RMT_CONF_REG register
- *  RMT configuration register
- */
-#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c)
-/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rmt apb clock
- */
-#define PCR_RMT_CLK_EN    (BIT(0))
-#define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
-#define PCR_RMT_CLK_EN_V  0x00000001U
-#define PCR_RMT_CLK_EN_S  0
-/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rmt module
- */
-#define PCR_RMT_RST_EN    (BIT(1))
-#define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
-#define PCR_RMT_RST_EN_V  0x00000001U
-#define PCR_RMT_RST_EN_S  1
-
-/** PCR_RMT_SCLK_CONF_REG register
- *  RMT_SCLK configuration register
- */
-#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30)
-/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_A    0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
-#define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_S  0
-/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_B    0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
-#define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_S  6
-/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
- *  The integral part of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
-#define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_S  12
-/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1;
- *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
- *  80MHz, 2: FOSC, 3: XTAL.
- */
-#define PCR_RMT_SCLK_SEL    0x00000003U
-#define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
-#define PCR_RMT_SCLK_SEL_V  0x00000003U
-#define PCR_RMT_SCLK_SEL_S  20
-/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable rmt function clock
- */
-#define PCR_RMT_SCLK_EN    (BIT(22))
-#define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
-#define PCR_RMT_SCLK_EN_V  0x00000001U
-#define PCR_RMT_SCLK_EN_S  22
-
-/** PCR_LEDC_CONF_REG register
- *  LEDC configuration register
- */
-#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34)
-/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ledc apb clock
- */
-#define PCR_LEDC_CLK_EN    (BIT(0))
-#define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
-#define PCR_LEDC_CLK_EN_V  0x00000001U
-#define PCR_LEDC_CLK_EN_S  0
-/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ledc module
- */
-#define PCR_LEDC_RST_EN    (BIT(1))
-#define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
-#define PCR_LEDC_RST_EN_V  0x00000001U
-#define PCR_LEDC_RST_EN_S  1
-
-/** PCR_LEDC_SCLK_CONF_REG register
- *  LEDC_SCLK configuration register
- */
-#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
-/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  80MHz, 2: FOSC, 3: XTAL.
- */
-#define PCR_LEDC_SCLK_SEL    0x00000003U
-#define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
-#define PCR_LEDC_SCLK_SEL_V  0x00000003U
-#define PCR_LEDC_SCLK_SEL_S  20
-/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable ledc function clock
- */
-#define PCR_LEDC_SCLK_EN    (BIT(22))
-#define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
-#define PCR_LEDC_SCLK_EN_V  0x00000001U
-#define PCR_LEDC_SCLK_EN_S  22
-
-/** PCR_TIMERGROUP0_CONF_REG register
- *  TIMERGROUP0 configuration register
- */
-#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c)
-/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group0 apb clock
- */
-#define PCR_TG0_CLK_EN    (BIT(0))
-#define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
-#define PCR_TG0_CLK_EN_V  0x00000001U
-#define PCR_TG0_CLK_EN_S  0
-/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group0 module
- */
-#define PCR_TG0_RST_EN    (BIT(1))
-#define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
-#define PCR_TG0_RST_EN_V  0x00000001U
-#define PCR_TG0_RST_EN_S  1
-
-/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
- *  TIMERGROUP0_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
-/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
-#define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_S  20
-/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 timer clock
- */
-#define PCR_TG0_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
-#define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG0_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
- *  TIMERGROUP0_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44)
-/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_WDT_CLK_SEL    0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
-#define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_S  20
-/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG0_WDT_CLK_EN    (BIT(22))
-#define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
-#define PCR_TG0_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG0_WDT_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_CONF_REG register
- *  TIMERGROUP1 configuration register
- */
-#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48)
-/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group1 apb clock
- */
-#define PCR_TG1_CLK_EN    (BIT(0))
-#define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
-#define PCR_TG1_CLK_EN_V  0x00000001U
-#define PCR_TG1_CLK_EN_S  0
-/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group1 module
- */
-#define PCR_TG1_RST_EN    (BIT(1))
-#define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
-#define PCR_TG1_RST_EN_V  0x00000001U
-#define PCR_TG1_RST_EN_S  1
-
-/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
- *  TIMERGROUP1_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c)
-/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
-#define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_S  20
-/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group1 timer clock
- */
-#define PCR_TG1_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
-#define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG1_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
- *  TIMERGROUP1_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50)
-/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_WDT_CLK_SEL    0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
-#define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_S  20
-/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG1_WDT_CLK_EN    (BIT(22))
-#define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
-#define PCR_TG1_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG1_WDT_CLK_EN_S  22
-
-/** PCR_SYSTIMER_CONF_REG register
- *  SYSTIMER configuration register
- */
-#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54)
-/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable systimer apb clock
- */
-#define PCR_SYSTIMER_CLK_EN    (BIT(0))
-#define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
-#define PCR_SYSTIMER_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_CLK_EN_S  0
-/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset systimer module
- */
-#define PCR_SYSTIMER_RST_EN    (BIT(1))
-#define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
-#define PCR_SYSTIMER_RST_EN_V  0x00000001U
-#define PCR_SYSTIMER_RST_EN_S  1
-
-/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
- *  SYSTIMER_FUNC_CLK configuration register
- */
-#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58)
-/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
-#define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
-#define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
-/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable systimer function clock
- */
-#define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
-#define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
-#define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_EN_S  22
-
-/** PCR_TWAI0_CONF_REG register
- *  TWAI0 configuration register
- */
-#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c)
-/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable twai0 apb clock
- */
-#define PCR_TWAI0_CLK_EN    (BIT(0))
-#define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
-#define PCR_TWAI0_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_CLK_EN_S  0
-/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset twai0 module
- */
-#define PCR_TWAI0_RST_EN    (BIT(1))
-#define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
-#define PCR_TWAI0_RST_EN_V  0x00000001U
-#define PCR_TWAI0_RST_EN_S  1
-
-/** PCR_TWAI0_FUNC_CLK_CONF_REG register
- *  TWAI0_FUNC_CLK configuration register
- */
-#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
-/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
-#define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
-#define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_SEL_S  20
-/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable twai0 function clock
- */
-#define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
-#define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
-#define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_EN_S  22
-
-/** PCR_TWAI1_CONF_REG register
- *  TWAI1 configuration register
- */
-#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64)
-/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable twai1 apb clock
- */
-#define PCR_TWAI1_CLK_EN    (BIT(0))
-#define PCR_TWAI1_CLK_EN_M  (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S)
-#define PCR_TWAI1_CLK_EN_V  0x00000001U
-#define PCR_TWAI1_CLK_EN_S  0
-/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset twai1 module
- */
-#define PCR_TWAI1_RST_EN    (BIT(1))
-#define PCR_TWAI1_RST_EN_M  (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S)
-#define PCR_TWAI1_RST_EN_V  0x00000001U
-#define PCR_TWAI1_RST_EN_S  1
-
-/** PCR_TWAI1_FUNC_CLK_CONF_REG register
- *  TWAI1_FUNC_CLK configuration register
- */
-#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
-/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_TWAI1_FUNC_CLK_SEL    (BIT(20))
-#define PCR_TWAI1_FUNC_CLK_SEL_M  (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S)
-#define PCR_TWAI1_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_TWAI1_FUNC_CLK_SEL_S  20
-/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable twai1 function clock
- */
-#define PCR_TWAI1_FUNC_CLK_EN    (BIT(22))
-#define PCR_TWAI1_FUNC_CLK_EN_M  (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S)
-#define PCR_TWAI1_FUNC_CLK_EN_V  0x00000001U
-#define PCR_TWAI1_FUNC_CLK_EN_S  22
-
-/** PCR_I2S_CONF_REG register
- *  I2S configuration register
- */
-#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
-/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2s apb clock
- */
-#define PCR_I2S_CLK_EN    (BIT(0))
-#define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
-#define PCR_I2S_CLK_EN_V  0x00000001U
-#define PCR_I2S_CLK_EN_S  0
-/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2s module
- */
-#define PCR_I2S_RST_EN    (BIT(1))
-#define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
-#define PCR_I2S_RST_EN_V  0x00000001U
-#define PCR_I2S_RST_EN_S  1
-
-/** PCR_I2S_TX_CLKM_CONF_REG register
- *  I2S_TX_CLKM configuration register
- */
-#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
-/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
- *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
- *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
- *  (n+1)-div] + y * (n+1)-div.
- */
-#define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
-#define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
- *  I2S_MCLK_in.
- */
-#define PCR_I2S_TX_CLKM_SEL    0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
-#define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_S  20
-/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_tx function clock
- */
-#define PCR_I2S_TX_CLKM_EN    (BIT(22))
-#define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
-#define PCR_I2S_TX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_TX_CLKM_EN_S  22
-
-/** PCR_I2S_TX_CLKM_DIV_CONF_REG register
- *  I2S_TX_CLKM_DIV configuration register
- */
-#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
-/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
-#define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_S  0
-/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
-#define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_S  9
-/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
-#define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_S  18
-/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
-#define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_TX_CLKM_DIV_YN1_S  27
-
-/** PCR_I2S_RX_CLKM_CONF_REG register
- *  I2S_RX_CLKM configuration register
- */
-#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
-/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S clock divider value
- */
-#define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
-#define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
- */
-#define PCR_I2S_RX_CLKM_SEL    0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
-#define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_S  20
-/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_rx function clock
- */
-#define PCR_I2S_RX_CLKM_EN    (BIT(22))
-#define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
-#define PCR_I2S_RX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_RX_CLKM_EN_S  22
-/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
- *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
- */
-#define PCR_I2S_MCLK_SEL    (BIT(23))
-#define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
-#define PCR_I2S_MCLK_SEL_V  0x00000001U
-#define PCR_I2S_MCLK_SEL_S  23
-
-/** PCR_I2S_RX_CLKM_DIV_CONF_REG register
- *  I2S_RX_CLKM_DIV configuration register
- */
-#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
-/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
-#define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_S  0
-/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
-#define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_S  9
-/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
-#define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_S  18
-/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
-#define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_RX_CLKM_DIV_YN1_S  27
-
-/** PCR_SARADC_CONF_REG register
- *  SARADC configuration register
- */
-#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
-/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  no use
- */
-#define PCR_SARADC_CLK_EN    (BIT(0))
-#define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
-#define PCR_SARADC_CLK_EN_V  0x00000001U
-#define PCR_SARADC_CLK_EN_S  0
-/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset function_register of saradc module
- */
-#define PCR_SARADC_RST_EN    (BIT(1))
-#define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
-#define PCR_SARADC_RST_EN_V  0x00000001U
-#define PCR_SARADC_RST_EN_S  1
-/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable saradc apb clock
- */
-#define PCR_SARADC_REG_CLK_EN    (BIT(2))
-#define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
-#define PCR_SARADC_REG_CLK_EN_V  0x00000001U
-#define PCR_SARADC_REG_CLK_EN_S  2
-/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
- *  Set 0 to reset apb_register of saradc module
- */
-#define PCR_SARADC_REG_RST_EN    (BIT(3))
-#define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
-#define PCR_SARADC_REG_RST_EN_V  0x00000001U
-#define PCR_SARADC_REG_RST_EN_S  3
-
-/** PCR_SARADC_CLKM_CONF_REG register
- *  SARADC_CLKM configuration register
- */
-#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
-/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_A    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
-#define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_S  0
-/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_B    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
-#define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_S  6
-/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
-#define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_S  12
-/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SARADC_CLKM_SEL    0x00000003U
-#define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
-#define PCR_SARADC_CLKM_SEL_V  0x00000003U
-#define PCR_SARADC_CLKM_SEL_S  20
-/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable saradc function clock
- */
-#define PCR_SARADC_CLKM_EN    (BIT(22))
-#define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
-#define PCR_SARADC_CLKM_EN_V  0x00000001U
-#define PCR_SARADC_CLKM_EN_S  22
-
-/** PCR_TSENS_CLK_CONF_REG register
- *  TSENS_CLK configuration register
- */
-#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
-/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
- */
-#define PCR_TSENS_CLK_SEL    (BIT(20))
-#define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
-#define PCR_TSENS_CLK_SEL_V  0x00000001U
-#define PCR_TSENS_CLK_SEL_S  20
-/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable tsens clock
- */
-#define PCR_TSENS_CLK_EN    (BIT(22))
-#define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
-#define PCR_TSENS_CLK_EN_V  0x00000001U
-#define PCR_TSENS_CLK_EN_S  22
-/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
- *  Set 0 to reset tsens module
- */
-#define PCR_TSENS_RST_EN    (BIT(23))
-#define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
-#define PCR_TSENS_RST_EN_V  0x00000001U
-#define PCR_TSENS_RST_EN_S  23
-
-/** PCR_USB_DEVICE_CONF_REG register
- *  USB_DEVICE configuration register
- */
-#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
-/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable usb_device clock
- */
-#define PCR_USB_DEVICE_CLK_EN    (BIT(0))
-#define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
-#define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
-#define PCR_USB_DEVICE_CLK_EN_S  0
-/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset usb_device module
- */
-#define PCR_USB_DEVICE_RST_EN    (BIT(1))
-#define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
-#define PCR_USB_DEVICE_RST_EN_V  0x00000001U
-#define PCR_USB_DEVICE_RST_EN_S  1
-
-/** PCR_INTMTX_CONF_REG register
- *  INTMTX configuration register
- */
-#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
-/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable intmtx clock
- */
-#define PCR_INTMTX_CLK_EN    (BIT(0))
-#define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
-#define PCR_INTMTX_CLK_EN_V  0x00000001U
-#define PCR_INTMTX_CLK_EN_S  0
-/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset intmtx module
- */
-#define PCR_INTMTX_RST_EN    (BIT(1))
-#define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
-#define PCR_INTMTX_RST_EN_V  0x00000001U
-#define PCR_INTMTX_RST_EN_S  1
-
-/** PCR_PCNT_CONF_REG register
- *  PCNT configuration register
- */
-#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
-/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pcnt clock
- */
-#define PCR_PCNT_CLK_EN    (BIT(0))
-#define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
-#define PCR_PCNT_CLK_EN_V  0x00000001U
-#define PCR_PCNT_CLK_EN_S  0
-/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pcnt module
- */
-#define PCR_PCNT_RST_EN    (BIT(1))
-#define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
-#define PCR_PCNT_RST_EN_V  0x00000001U
-#define PCR_PCNT_RST_EN_S  1
-
-/** PCR_ETM_CONF_REG register
- *  ETM configuration register
- */
-#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
-/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable etm clock
- */
-#define PCR_ETM_CLK_EN    (BIT(0))
-#define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
-#define PCR_ETM_CLK_EN_V  0x00000001U
-#define PCR_ETM_CLK_EN_S  0
-/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset etm module
- */
-#define PCR_ETM_RST_EN    (BIT(1))
-#define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
-#define PCR_ETM_RST_EN_V  0x00000001U
-#define PCR_ETM_RST_EN_S  1
-
-/** PCR_PWM_CONF_REG register
- *  PWM configuration register
- */
-#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
-/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pwm clock
- */
-#define PCR_PWM_CLK_EN    (BIT(0))
-#define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
-#define PCR_PWM_CLK_EN_V  0x00000001U
-#define PCR_PWM_CLK_EN_S  0
-/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pwm module
- */
-#define PCR_PWM_RST_EN    (BIT(1))
-#define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
-#define PCR_PWM_RST_EN_V  0x00000001U
-#define PCR_PWM_RST_EN_S  1
-
-/** PCR_PWM_CLK_CONF_REG register
- *  PWM_CLK configuration register
- */
-#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
-/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the pwm function clock.
- */
-#define PCR_PWM_DIV_NUM    0x000000FFU
-#define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
-#define PCR_PWM_DIV_NUM_V  0x000000FFU
-#define PCR_PWM_DIV_NUM_S  12
-/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  160MHz, 2: XTAL, 3: FOSC.
- */
-#define PCR_PWM_CLKM_SEL    0x00000003U
-#define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
-#define PCR_PWM_CLKM_SEL_V  0x00000003U
-#define PCR_PWM_CLKM_SEL_S  20
-/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  set this field as 1 to activate pwm clkm.
- */
-#define PCR_PWM_CLKM_EN    (BIT(22))
-#define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
-#define PCR_PWM_CLKM_EN_V  0x00000001U
-#define PCR_PWM_CLKM_EN_S  22
-
-/** PCR_PARL_IO_CONF_REG register
- *  PARL_IO configuration register
- */
-#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
-/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable parl apb clock
- */
-#define PCR_PARL_CLK_EN    (BIT(0))
-#define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
-#define PCR_PARL_CLK_EN_V  0x00000001U
-#define PCR_PARL_CLK_EN_S  0
-/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset parl apb reg
- */
-#define PCR_PARL_RST_EN    (BIT(1))
-#define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
-#define PCR_PARL_RST_EN_V  0x00000001U
-#define PCR_PARL_RST_EN_S  1
-
-/** PCR_PARL_CLK_RX_CONF_REG register
- *  PARL_CLK_RX configuration register
- */
-#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
-/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl rx clock.
- */
-#define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
-#define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_S  0
-/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_RX_SEL    0x00000003U
-#define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
-#define PCR_PARL_CLK_RX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_RX_SEL_S  16
-/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl rx clock
- */
-#define PCR_PARL_CLK_RX_EN    (BIT(18))
-#define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
-#define PCR_PARL_CLK_RX_EN_V  0x00000001U
-#define PCR_PARL_CLK_RX_EN_S  18
-/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl rx module
- */
-#define PCR_PARL_RX_RST_EN    (BIT(19))
-#define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
-#define PCR_PARL_RX_RST_EN_V  0x00000001U
-#define PCR_PARL_RX_RST_EN_S  19
-
-/** PCR_PARL_CLK_TX_CONF_REG register
- *  PARL_CLK_TX configuration register
- */
-#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
-/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl tx clock.
- */
-#define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
-#define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_S  0
-/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_TX_SEL    0x00000003U
-#define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
-#define PCR_PARL_CLK_TX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_TX_SEL_S  16
-/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl tx clock
- */
-#define PCR_PARL_CLK_TX_EN    (BIT(18))
-#define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
-#define PCR_PARL_CLK_TX_EN_V  0x00000001U
-#define PCR_PARL_CLK_TX_EN_S  18
-/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl tx module
- */
-#define PCR_PARL_TX_RST_EN    (BIT(19))
-#define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
-#define PCR_PARL_TX_RST_EN_V  0x00000001U
-#define PCR_PARL_TX_RST_EN_S  19
-
-/** PCR_SDIO_SLAVE_CONF_REG register
- *  SDIO_SLAVE configuration register
- */
-#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0)
-/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable sdio_slave clock
- */
-#define PCR_SDIO_SLAVE_CLK_EN    (BIT(0))
-#define PCR_SDIO_SLAVE_CLK_EN_M  (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S)
-#define PCR_SDIO_SLAVE_CLK_EN_V  0x00000001U
-#define PCR_SDIO_SLAVE_CLK_EN_S  0
-/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset sdio_slave module
- */
-#define PCR_SDIO_SLAVE_RST_EN    (BIT(1))
-#define PCR_SDIO_SLAVE_RST_EN_M  (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S)
-#define PCR_SDIO_SLAVE_RST_EN_V  0x00000001U
-#define PCR_SDIO_SLAVE_RST_EN_S  1
-
-/** PCR_PVT_MONITOR_CONF_REG register
- *  PVT_MONITOR configuration register
- */
-#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4)
-/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable apb clock of pvt module
- */
-#define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
-#define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
-#define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_CLK_EN_S  0
-/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset all pvt monitor module
- */
-#define PCR_PVT_MONITOR_RST_EN    (BIT(1))
-#define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
-#define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_RST_EN_S  1
-/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable function clock of modem pvt module
- */
-#define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
-/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  Set 1 to enable function clock of cpu pvt module
- */
-#define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
-/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  Set 1 to enable function clock of hp_peri pvt module
- */
-#define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
-
-/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
- *  PVT_MONITOR function clock configuration register
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8)
-/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
- *  The integral part of the frequency divider factor of the pvt_monitor function clock.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
-/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
- *  divided by 3.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
-/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable source clock of pvt sitex
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
-
-/** PCR_GDMA_CONF_REG register
- *  GDMA configuration register
- */
-#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc)
-/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable gdma clock
- */
-#define PCR_GDMA_CLK_EN    (BIT(0))
-#define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
-#define PCR_GDMA_CLK_EN_V  0x00000001U
-#define PCR_GDMA_CLK_EN_S  0
-/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset gdma module
- */
-#define PCR_GDMA_RST_EN    (BIT(1))
-#define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
-#define PCR_GDMA_RST_EN_V  0x00000001U
-#define PCR_GDMA_RST_EN_S  1
-
-/** PCR_SPI2_CONF_REG register
- *  SPI2 configuration register
- */
-#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0)
-/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable spi2 apb clock
- */
-#define PCR_SPI2_CLK_EN    (BIT(0))
-#define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
-#define PCR_SPI2_CLK_EN_V  0x00000001U
-#define PCR_SPI2_CLK_EN_S  0
-/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset spi2 module
- */
-#define PCR_SPI2_RST_EN    (BIT(1))
-#define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
-#define PCR_SPI2_RST_EN_V  0x00000001U
-#define PCR_SPI2_RST_EN_S  1
-
-/** PCR_SPI2_CLKM_CONF_REG register
- *  SPI2_CLKM configuration register
- */
-#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4)
-/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SPI2_CLKM_SEL    0x00000003U
-#define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
-#define PCR_SPI2_CLKM_SEL_V  0x00000003U
-#define PCR_SPI2_CLKM_SEL_S  20
-/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable spi2 function clock
- */
-#define PCR_SPI2_CLKM_EN    (BIT(22))
-#define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
-#define PCR_SPI2_CLKM_EN_V  0x00000001U
-#define PCR_SPI2_CLKM_EN_S  22
-
-/** PCR_AES_CONF_REG register
- *  AES configuration register
- */
-#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8)
-/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable aes clock
- */
-#define PCR_AES_CLK_EN    (BIT(0))
-#define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
-#define PCR_AES_CLK_EN_V  0x00000001U
-#define PCR_AES_CLK_EN_S  0
-/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset aes module
- */
-#define PCR_AES_RST_EN    (BIT(1))
-#define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
-#define PCR_AES_RST_EN_V  0x00000001U
-#define PCR_AES_RST_EN_S  1
-
-/** PCR_SHA_CONF_REG register
- *  SHA configuration register
- */
-#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
-/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable sha clock
- */
-#define PCR_SHA_CLK_EN    (BIT(0))
-#define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
-#define PCR_SHA_CLK_EN_V  0x00000001U
-#define PCR_SHA_CLK_EN_S  0
-/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset sha module
- */
-#define PCR_SHA_RST_EN    (BIT(1))
-#define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
-#define PCR_SHA_RST_EN_V  0x00000001U
-#define PCR_SHA_RST_EN_S  1
-
-/** PCR_RSA_CONF_REG register
- *  RSA configuration register
- */
-#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0)
-/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rsa clock
- */
-#define PCR_RSA_CLK_EN    (BIT(0))
-#define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
-#define PCR_RSA_CLK_EN_V  0x00000001U
-#define PCR_RSA_CLK_EN_S  0
-/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rsa module
- */
-#define PCR_RSA_RST_EN    (BIT(1))
-#define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
-#define PCR_RSA_RST_EN_V  0x00000001U
-#define PCR_RSA_RST_EN_S  1
-
-/** PCR_RSA_PD_CTRL_REG register
- *  RSA power control register
- */
-#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4)
-/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down rsa internal memory.
- */
-#define PCR_RSA_MEM_PD    (BIT(0))
-#define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
-#define PCR_RSA_MEM_PD_V  0x00000001U
-#define PCR_RSA_MEM_PD_S  0
-/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up rsa internal memory
- */
-#define PCR_RSA_MEM_FORCE_PU    (BIT(1))
-#define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
-#define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PU_S  1
-/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down rsa internal memory.
- */
-#define PCR_RSA_MEM_FORCE_PD    (BIT(2))
-#define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
-#define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PD_S  2
-
-/** PCR_ECC_CONF_REG register
- *  ECC configuration register
- */
-#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8)
-/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ecc clock
- */
-#define PCR_ECC_CLK_EN    (BIT(0))
-#define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
-#define PCR_ECC_CLK_EN_V  0x00000001U
-#define PCR_ECC_CLK_EN_S  0
-/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ecc module
- */
-#define PCR_ECC_RST_EN    (BIT(1))
-#define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
-#define PCR_ECC_RST_EN_V  0x00000001U
-#define PCR_ECC_RST_EN_S  1
-
-/** PCR_ECC_PD_CTRL_REG register
- *  ECC power control register
- */
-#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc)
-/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down ecc internal memory.
- */
-#define PCR_ECC_MEM_PD    (BIT(0))
-#define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
-#define PCR_ECC_MEM_PD_V  0x00000001U
-#define PCR_ECC_MEM_PD_S  0
-/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up ecc internal memory
- */
-#define PCR_ECC_MEM_FORCE_PU    (BIT(1))
-#define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
-#define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PU_S  1
-/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down ecc internal memory.
- */
-#define PCR_ECC_MEM_FORCE_PD    (BIT(2))
-#define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
-#define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PD_S  2
-
-/** PCR_DS_CONF_REG register
- *  DS configuration register
- */
-#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0)
-/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ds clock
- */
-#define PCR_DS_CLK_EN    (BIT(0))
-#define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
-#define PCR_DS_CLK_EN_V  0x00000001U
-#define PCR_DS_CLK_EN_S  0
-/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ds module
- */
-#define PCR_DS_RST_EN    (BIT(1))
-#define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
-#define PCR_DS_RST_EN_V  0x00000001U
-#define PCR_DS_RST_EN_S  1
-
-/** PCR_HMAC_CONF_REG register
- *  HMAC configuration register
- */
-#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4)
-/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable hmac clock
- */
-#define PCR_HMAC_CLK_EN    (BIT(0))
-#define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
-#define PCR_HMAC_CLK_EN_V  0x00000001U
-#define PCR_HMAC_CLK_EN_S  0
-/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset hmac module
- */
-#define PCR_HMAC_RST_EN    (BIT(1))
-#define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
-#define PCR_HMAC_RST_EN_V  0x00000001U
-#define PCR_HMAC_RST_EN_S  1
-
-/** PCR_IOMUX_CONF_REG register
- *  IOMUX configuration register
- */
-#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
-/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable iomux apb clock
- */
-#define PCR_IOMUX_CLK_EN    (BIT(0))
-#define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
-#define PCR_IOMUX_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_CLK_EN_S  0
-/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset iomux module
- */
-#define PCR_IOMUX_RST_EN    (BIT(1))
-#define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
-#define PCR_IOMUX_RST_EN_V  0x00000001U
-#define PCR_IOMUX_RST_EN_S  1
-
-/** PCR_IOMUX_CLK_CONF_REG register
- *  IOMUX_CLK configuration register
- */
-#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
-/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
-#define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_S  20
-/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable iomux function clock
- */
-#define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
-#define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
-#define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_FUNC_CLK_EN_S  22
-
-/** PCR_MEM_MONITOR_CONF_REG register
- *  MEM_MONITOR configuration register
- */
-#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
-/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mem_monitor clock
- */
-#define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
-#define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
-#define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_CLK_EN_S  0
-/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mem_monitor module
- */
-#define PCR_MEM_MONITOR_RST_EN    (BIT(1))
-#define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
-#define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_RST_EN_S  1
-
-/** PCR_REGDMA_CONF_REG register
- *  REGDMA configuration register
- */
-#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
-/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable regdma clock
- */
-#define PCR_REGDMA_CLK_EN    (BIT(0))
-#define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
-#define PCR_REGDMA_CLK_EN_V  0x00000001U
-#define PCR_REGDMA_CLK_EN_S  0
-/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset regdma module
- */
-#define PCR_REGDMA_RST_EN    (BIT(1))
-#define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
-#define PCR_REGDMA_RST_EN_V  0x00000001U
-#define PCR_REGDMA_RST_EN_S  1
-
-/** PCR_RETENTION_CONF_REG register
- *  retention configuration register
- */
-#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8)
-/** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable retention clock
- */
-#define PCR_RETENTION_CLK_EN    (BIT(0))
-#define PCR_RETENTION_CLK_EN_M  (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S)
-#define PCR_RETENTION_CLK_EN_V  0x00000001U
-#define PCR_RETENTION_CLK_EN_S  0
-/** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset retention module
- */
-#define PCR_RETENTION_RST_EN    (BIT(1))
-#define PCR_RETENTION_RST_EN_M  (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S)
-#define PCR_RETENTION_RST_EN_V  0x00000001U
-#define PCR_RETENTION_RST_EN_S  1
-
-/** PCR_TRACE_CONF_REG register
- *  TRACE configuration register
- */
-#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc)
-/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable trace clock
- */
-#define PCR_TRACE_CLK_EN    (BIT(0))
-#define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
-#define PCR_TRACE_CLK_EN_V  0x00000001U
-#define PCR_TRACE_CLK_EN_S  0
-/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset trace module
- */
-#define PCR_TRACE_RST_EN    (BIT(1))
-#define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
-#define PCR_TRACE_RST_EN_V  0x00000001U
-#define PCR_TRACE_RST_EN_S  1
-
-/** PCR_ASSIST_CONF_REG register
- *  ASSIST configuration register
- */
-#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100)
-/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable assist clock
- */
-#define PCR_ASSIST_CLK_EN    (BIT(0))
-#define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
-#define PCR_ASSIST_CLK_EN_V  0x00000001U
-#define PCR_ASSIST_CLK_EN_S  0
-/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset assist module
- */
-#define PCR_ASSIST_RST_EN    (BIT(1))
-#define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
-#define PCR_ASSIST_RST_EN_V  0x00000001U
-#define PCR_ASSIST_RST_EN_S  1
-
-/** PCR_CACHE_CONF_REG register
- *  CACHE configuration register
- */
-#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104)
-/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable cache clock
- */
-#define PCR_CACHE_CLK_EN    (BIT(0))
-#define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
-#define PCR_CACHE_CLK_EN_V  0x00000001U
-#define PCR_CACHE_CLK_EN_S  0
-/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cache module
- */
-#define PCR_CACHE_RST_EN    (BIT(1))
-#define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
-#define PCR_CACHE_RST_EN_V  0x00000001U
-#define PCR_CACHE_RST_EN_S  1
-
-/** PCR_MODEM_APB_CONF_REG register
- *  MODEM_APB configuration register
- */
-#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108)
-/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
- */
-#define PCR_MODEM_APB_CLK_EN    (BIT(0))
-#define PCR_MODEM_APB_CLK_EN_M  (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S)
-#define PCR_MODEM_APB_CLK_EN_V  0x00000001U
-#define PCR_MODEM_APB_CLK_EN_S  0
-/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set this file as 1 to reset modem-subsystem.
- */
-#define PCR_MODEM_RST_EN    (BIT(1))
-#define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
-#define PCR_MODEM_RST_EN_V  0x00000001U
-#define PCR_MODEM_RST_EN_S  1
-
-/** PCR_TIMEOUT_CONF_REG register
- *  TIMEOUT configuration register
- */
-#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c)
-/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cpu_peri timeout module
- */
-#define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
-#define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
-#define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_CPU_TIMEOUT_RST_EN_S  1
-/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
- */
-#define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
-#define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
-#define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_HP_TIMEOUT_RST_EN_S  2
-
-/** PCR_SYSCLK_CONF_REG register
- *  SYSCLK configuration register
- */
-#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110)
-/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
- *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
- *  clock-source such as XTAL/FOSC.
- */
-#define PCR_LS_DIV_NUM    0x000000FFU
-#define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
-#define PCR_LS_DIV_NUM_V  0x000000FFU
-#define PCR_LS_DIV_NUM_S  0
-/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
- *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
- */
-#define PCR_HS_DIV_NUM    0x000000FFU
-#define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
-#define PCR_HS_DIV_NUM_V  0x000000FFU
-#define PCR_HS_DIV_NUM_S  8
-/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
- */
-#define PCR_SOC_CLK_SEL    0x00000003U
-#define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
-#define PCR_SOC_CLK_SEL_V  0x00000003U
-#define PCR_SOC_CLK_SEL_S  16
-/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40;
- *  This field indicates the frequency(MHz) of XTAL.
- */
-#define PCR_CLK_XTAL_FREQ    0x0000007FU
-#define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
-#define PCR_CLK_XTAL_FREQ_V  0x0000007FU
-#define PCR_CLK_XTAL_FREQ_S  24
-
-/** PCR_CPU_WAITI_CONF_REG register
- *  CPU_WAITI configuration register
- */
-#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114)
-/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
- */
-#define PCR_CPUPERIOD_SEL    0x00000003U
-#define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
-#define PCR_CPUPERIOD_SEL_V  0x00000003U
-#define PCR_CPUPERIOD_SEL_S  0
-/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
- */
-#define PCR_PLL_FREQ_SEL    (BIT(2))
-#define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
-#define PCR_PLL_FREQ_SEL_V  0x00000001U
-#define PCR_PLL_FREQ_SEL_S  2
-/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
- *  Set 1 to force cpu_waiti_clk enable.
- */
-#define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
-#define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
-#define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
-#define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
-/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
- *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
- *  will close
- */
-#define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
-#define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_S  4
-
-/** PCR_CPU_FREQ_CONF_REG register
- *  CPU_FREQ configuration register
- */
-#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
-/** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
- *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
- */
-#define PCR_CPU_LS_DIV_NUM    0x000000FFU
-#define PCR_CPU_LS_DIV_NUM_M  (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S)
-#define PCR_CPU_LS_DIV_NUM_V  0x000000FFU
-#define PCR_CPU_LS_DIV_NUM_S  0
-/** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
- *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
- */
-#define PCR_CPU_HS_DIV_NUM    0x000000FFU
-#define PCR_CPU_HS_DIV_NUM_M  (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S)
-#define PCR_CPU_HS_DIV_NUM_V  0x000000FFU
-#define PCR_CPU_HS_DIV_NUM_S  8
-/** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0;
- *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
- *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
- */
-#define PCR_CPU_HS_120M_FORCE    (BIT(16))
-#define PCR_CPU_HS_120M_FORCE_M  (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S)
-#define PCR_CPU_HS_120M_FORCE_V  0x00000001U
-#define PCR_CPU_HS_120M_FORCE_S  16
-
-/** PCR_AHB_FREQ_CONF_REG register
- *  AHB_FREQ configuration register
- */
-#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
-/** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
- *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
- *  low-speed clock-source such as XTAL/FOSC, and should be used together with
- *  PCR_CPU_LS_DIV_NUM.
- */
-#define PCR_AHB_LS_DIV_NUM    0x000000FFU
-#define PCR_AHB_LS_DIV_NUM_M  (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S)
-#define PCR_AHB_LS_DIV_NUM_V  0x000000FFU
-#define PCR_AHB_LS_DIV_NUM_S  0
-/** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
- *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
- *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
- */
-#define PCR_AHB_HS_DIV_NUM    0x000000FFU
-#define PCR_AHB_HS_DIV_NUM_M  (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S)
-#define PCR_AHB_HS_DIV_NUM_V  0x000000FFU
-#define PCR_AHB_HS_DIV_NUM_S  8
-
-/** PCR_APB_FREQ_CONF_REG register
- *  APB_FREQ configuration register
- */
-#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120)
-/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
- *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
- *  recover to the previous frequency when a new access appears on apb-bus. Set as one
- *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
- *  that enable this function will reduce performance. Users can set this field as zero
- *  to disable the auto-decrease-apb-freq function. By default, this function is
- *  disable.
- */
-#define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
-#define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_S  0
-/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
- *  div1(default)/div2/div4 of clk_ahb.
- */
-#define PCR_APB_DIV_NUM    0x000000FFU
-#define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
-#define PCR_APB_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DIV_NUM_S  8
-
-/** PCR_SYSCLK_FREQ_QUERY_0_REG register
- *  SYSCLK frequency query 0 register
- */
-#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124)
-/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20;
- *  This field indicates the frequency(MHz) of FOSC.
- */
-#define PCR_FOSC_FREQ    0x000000FFU
-#define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
-#define PCR_FOSC_FREQ_V  0x000000FFU
-#define PCR_FOSC_FREQ_S  0
-/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480;
- *  This field indicates the frequency(MHz) of SPLL.
- */
-#define PCR_PLL_FREQ    0x000003FFU
-#define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
-#define PCR_PLL_FREQ_V  0x000003FFU
-#define PCR_PLL_FREQ_S  8
-
-/** PCR_PLL_DIV_CLK_EN_REG register
- *  SPLL DIV clock-gating configuration register
- */
-#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128)
-/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_240M_CLK_EN    (BIT(0))
-#define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
-#define PCR_PLL_240M_CLK_EN_V  0x00000001U
-#define PCR_PLL_240M_CLK_EN_S  0
-/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_160M_CLK_EN    (BIT(1))
-#define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
-#define PCR_PLL_160M_CLK_EN_V  0x00000001U
-#define PCR_PLL_160M_CLK_EN_S  1
-/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_120M_CLK_EN    (BIT(2))
-#define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
-#define PCR_PLL_120M_CLK_EN_V  0x00000001U
-#define PCR_PLL_120M_CLK_EN_S  2
-/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_80M_CLK_EN    (BIT(3))
-#define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
-#define PCR_PLL_80M_CLK_EN_V  0x00000001U
-#define PCR_PLL_80M_CLK_EN_S  3
-/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_48M_CLK_EN    (BIT(4))
-#define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
-#define PCR_PLL_48M_CLK_EN_V  0x00000001U
-#define PCR_PLL_48M_CLK_EN_S  4
-/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_40M_CLK_EN    (BIT(5))
-#define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
-#define PCR_PLL_40M_CLK_EN_V  0x00000001U
-#define PCR_PLL_40M_CLK_EN_S  5
-/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_20M_CLK_EN    (BIT(6))
-#define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
-#define PCR_PLL_20M_CLK_EN_V  0x00000001U
-#define PCR_PLL_20M_CLK_EN_S  6
-
-/** PCR_CTRL_CLK_OUT_EN_REG register
- *  CLK_OUT_EN configuration register
- */
-#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c)
-/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable 20m clock
- */
-#define PCR_CLK20_OEN    (BIT(0))
-#define PCR_CLK20_OEN_M  (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S)
-#define PCR_CLK20_OEN_V  0x00000001U
-#define PCR_CLK20_OEN_S  0
-/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1;
- *  Set 1 to enable 22m clock
- */
-#define PCR_CLK22_OEN    (BIT(1))
-#define PCR_CLK22_OEN_M  (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S)
-#define PCR_CLK22_OEN_V  0x00000001U
-#define PCR_CLK22_OEN_S  1
-/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable 44m clock
- */
-#define PCR_CLK44_OEN    (BIT(2))
-#define PCR_CLK44_OEN_M  (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S)
-#define PCR_CLK44_OEN_V  0x00000001U
-#define PCR_CLK44_OEN_S  2
-/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1;
- *  Set 1 to enable bb clock
- */
-#define PCR_CLK_BB_OEN    (BIT(3))
-#define PCR_CLK_BB_OEN_M  (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S)
-#define PCR_CLK_BB_OEN_V  0x00000001U
-#define PCR_CLK_BB_OEN_S  3
-/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1;
- *  Set 1 to enable 80m clock
- */
-#define PCR_CLK80_OEN    (BIT(4))
-#define PCR_CLK80_OEN_M  (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S)
-#define PCR_CLK80_OEN_V  0x00000001U
-#define PCR_CLK80_OEN_S  4
-/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1;
- *  Set 1 to enable 160m clock
- */
-#define PCR_CLK160_OEN    (BIT(5))
-#define PCR_CLK160_OEN_M  (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S)
-#define PCR_CLK160_OEN_V  0x00000001U
-#define PCR_CLK160_OEN_S  5
-/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1;
- *  Set 1 to enable 320m clock
- */
-#define PCR_CLK_320M_OEN    (BIT(6))
-#define PCR_CLK_320M_OEN_M  (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S)
-#define PCR_CLK_320M_OEN_V  0x00000001U
-#define PCR_CLK_320M_OEN_S  6
-/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_ADC_INF_OEN    (BIT(7))
-#define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
-#define PCR_CLK_ADC_INF_OEN_V  0x00000001U
-#define PCR_CLK_ADC_INF_OEN_S  7
-/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_DAC_CPU_OEN    (BIT(8))
-#define PCR_CLK_DAC_CPU_OEN_M  (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S)
-#define PCR_CLK_DAC_CPU_OEN_V  0x00000001U
-#define PCR_CLK_DAC_CPU_OEN_S  8
-/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1;
- *  Set 1 to enable 40x_bb clock
- */
-#define PCR_CLK40X_BB_OEN    (BIT(9))
-#define PCR_CLK40X_BB_OEN_M  (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S)
-#define PCR_CLK40X_BB_OEN_V  0x00000001U
-#define PCR_CLK40X_BB_OEN_S  9
-/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1;
- *  Set 1 to enable xtal clock
- */
-#define PCR_CLK_XTAL_OEN    (BIT(10))
-#define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
-#define PCR_CLK_XTAL_OEN_V  0x00000001U
-#define PCR_CLK_XTAL_OEN_S  10
-
-/** PCR_CTRL_TICK_CONF_REG register
- *  TICK configuration register
- */
-#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130)
-/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
- *  ******* Description ***********
- */
-#define PCR_XTAL_TICK_NUM    0x000000FFU
-#define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
-#define PCR_XTAL_TICK_NUM_V  0x000000FFU
-#define PCR_XTAL_TICK_NUM_S  0
-/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
- *  ******* Description ***********
- */
-#define PCR_FOSC_TICK_NUM    0x000000FFU
-#define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
-#define PCR_FOSC_TICK_NUM_V  0x000000FFU
-#define PCR_FOSC_TICK_NUM_S  8
-/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
- *  ******* Description ***********
- */
-#define PCR_TICK_ENABLE    (BIT(16))
-#define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
-#define PCR_TICK_ENABLE_V  0x00000001U
-#define PCR_TICK_ENABLE_S  16
-/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
- *  ******* Description ***********
- */
-#define PCR_RST_TICK_CNT    (BIT(17))
-#define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
-#define PCR_RST_TICK_CNT_V  0x00000001U
-#define PCR_RST_TICK_CNT_S  17
-
-/** PCR_CTRL_32K_CONF_REG register
- *  32KHz clock configuration register
- */
-#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134)
-/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
- *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and
- *  timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
- */
-#define PCR_32K_SEL    0x00000003U
-#define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
-#define PCR_32K_SEL_V  0x00000003U
-#define PCR_32K_SEL_S  0
-
-/** PCR_SRAM_POWER_CONF_REG register
- *  HP SRAM/ROM configuration register
- */
-#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138)
-/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15;
- *  Set this bit to force power up SRAM
- */
-#define PCR_SRAM_FORCE_PU    0x0000000FU
-#define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
-#define PCR_SRAM_FORCE_PU_V  0x0000000FU
-#define PCR_SRAM_FORCE_PU_S  0
-/** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0;
- *  Set this bit to force power down SRAM.
- */
-#define PCR_SRAM_FORCE_PD    0x0000000FU
-#define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
-#define PCR_SRAM_FORCE_PD_V  0x0000000FU
-#define PCR_SRAM_FORCE_PD_S  4
-/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
- *  gate-clock will be used when accessing the SRAM.
- */
-#define PCR_SRAM_CLKGATE_FORCE_ON    0x0000000FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
-#define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000000FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_S  8
-/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7;
- *  Set this bit to force power up ROM
- */
-#define PCR_ROM_FORCE_PU    0x00000007U
-#define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
-#define PCR_ROM_FORCE_PU_V  0x00000007U
-#define PCR_ROM_FORCE_PU_S  12
-/** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0;
- *  Set this bit to force power down ROM.
- */
-#define PCR_ROM_FORCE_PD    0x00000007U
-#define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
-#define PCR_ROM_FORCE_PD_V  0x00000007U
-#define PCR_ROM_FORCE_PD_S  15
-/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
- *  gate-clock will be used when accessing the ROM.
- */
-#define PCR_ROM_CLKGATE_FORCE_ON    0x00000007U
-#define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
-#define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000007U
-#define PCR_ROM_CLKGATE_FORCE_ON_S  18
-
-/** PCR_RESET_EVENT_BYPASS_REG register
- *  reset event bypass backdoor configuration register
- */
-#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
-/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
- *  This field is used to control reset event relationship for
- *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
- *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
- *  will not only be reset by power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
-#define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
-#define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_APM_S  0
-/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
- *  This field is used to control reset event relationship for system-bus. 1: system
- *  bus (including arbiter/router) will only be reset by power-reset. some reset event
- *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
- *  power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS    (BIT(1))
-#define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
-#define PCR_RESET_EVENT_BYPASS_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_S  1
-
-/** PCR_FPGA_DEBUG_REG register
- *  fpga debug register
- */
-#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
-/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
- *  Only used in fpga debug.
- */
-#define PCR_FPGA_DEBUG    0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
-#define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_S  0
-
-/** PCR_CLOCK_GATE_REG register
- *  PCR clock gating configure register
- */
-#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
-/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to force on clock gating.
- */
-#define PCR_CLK_EN    (BIT(0))
-#define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
-#define PCR_CLK_EN_V  0x00000001U
-#define PCR_CLK_EN_S  0
-
-/** PCR_DATE_REG register
- *  Date register.
- */
-#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
-/** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496;
- *  PCR version information.
- */
-#define PCR_DATE    0x0FFFFFFFU
-#define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
-#define PCR_DATE_V  0x0FFFFFFFU
-#define PCR_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/plic_reg.h b/components/soc/esp32p4/include/soc/plic_reg.h
deleted file mode 100644
index 3ee0ca70ed..0000000000
--- a/components/soc/esp32p4/include/soc/plic_reg.h
+++ /dev/null
@@ -1,631 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define PLIC_MXINT_CONF_REG       ( 0x200013FC )
-#define PLIC_UXINT_CONF_REG       ( 0x200017FC )
-
-#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
-#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
-
-/*PLIC MX*/
-#define PLIC_MXINT_ENABLE_REG          (DR_REG_PLIC_MX_BASE + 0x0)
-/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT_ENABLE    0xFFFFFFFF
-#define PLIC_CPU_MXINT_ENABLE_M  ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S))
-#define PLIC_CPU_MXINT_ENABLE_V  0xFFFFFFFF
-#define PLIC_CPU_MXINT_ENABLE_S  0
-
-#define PLIC_MXINT_TYPE_REG          (DR_REG_PLIC_MX_BASE + 0x4)
-/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT_TYPE    0xFFFFFFFF
-#define PLIC_CPU_MXINT_TYPE_M  ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S))
-#define PLIC_CPU_MXINT_TYPE_V  0xFFFFFFFF
-#define PLIC_CPU_MXINT_TYPE_S  0
-
-#define PLIC_MXINT_CLEAR_REG          (DR_REG_PLIC_MX_BASE + 0x8)
-/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT_CLEAR    0xFFFFFFFF
-#define PLIC_CPU_MXINT_CLEAR_M  ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S))
-#define PLIC_CPU_MXINT_CLEAR_V  0xFFFFFFFF
-#define PLIC_CPU_MXINT_CLEAR_S  0
-
-#define PLIC_EMIP_STATUS_REG          (DR_REG_PLIC_MX_BASE + 0xC)
-/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_EIP_STATUS    0xFFFFFFFF
-#define PLIC_CPU_EIP_STATUS_M  ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
-#define PLIC_CPU_EIP_STATUS_V  0xFFFFFFFF
-#define PLIC_CPU_EIP_STATUS_S  0
-
-#define PLIC_MXINT0_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x10)
-/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT0_PRI    0x0000000F
-#define PLIC_CPU_MXINT0_PRI_M  ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S))
-#define PLIC_CPU_MXINT0_PRI_V  0xF
-#define PLIC_CPU_MXINT0_PRI_S  0
-
-#define PLIC_MXINT1_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x14)
-/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT1_PRI    0x0000000F
-#define PLIC_CPU_MXINT1_PRI_M  ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S))
-#define PLIC_CPU_MXINT1_PRI_V  0xF
-#define PLIC_CPU_MXINT1_PRI_S  0
-
-#define PLIC_MXINT2_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x18)
-/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT2_PRI    0x0000000F
-#define PLIC_CPU_MXINT2_PRI_M  ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S))
-#define PLIC_CPU_MXINT2_PRI_V  0xF
-#define PLIC_CPU_MXINT2_PRI_S  0
-
-#define PLIC_MXINT3_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x1C)
-/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT3_PRI    0x0000000F
-#define PLIC_CPU_MXINT3_PRI_M  ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S))
-#define PLIC_CPU_MXINT3_PRI_V  0xF
-#define PLIC_CPU_MXINT3_PRI_S  0
-
-#define PLIC_MXINT4_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x20)
-/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT4_PRI    0x0000000F
-#define PLIC_CPU_MXINT4_PRI_M  ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S))
-#define PLIC_CPU_MXINT4_PRI_V  0xF
-#define PLIC_CPU_MXINT4_PRI_S  0
-
-#define PLIC_MXINT5_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x24)
-/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT5_PRI    0x0000000F
-#define PLIC_CPU_MXINT5_PRI_M  ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S))
-#define PLIC_CPU_MXINT5_PRI_V  0xF
-#define PLIC_CPU_MXINT5_PRI_S  0
-
-#define PLIC_MXINT6_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x28)
-/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT6_PRI    0x0000000F
-#define PLIC_CPU_MXINT6_PRI_M  ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S))
-#define PLIC_CPU_MXINT6_PRI_V  0xF
-#define PLIC_CPU_MXINT6_PRI_S  0
-
-#define PLIC_MXINT7_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x2C)
-/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT7_PRI    0x0000000F
-#define PLIC_CPU_MXINT7_PRI_M  ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S))
-#define PLIC_CPU_MXINT7_PRI_V  0xF
-#define PLIC_CPU_MXINT7_PRI_S  0
-
-#define PLIC_MXINT8_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x30)
-/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT8_PRI    0x0000000F
-#define PLIC_CPU_MXINT8_PRI_M  ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S))
-#define PLIC_CPU_MXINT8_PRI_V  0xF
-#define PLIC_CPU_MXINT8_PRI_S  0
-
-#define PLIC_MXINT9_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x34)
-/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT9_PRI    0x0000000F
-#define PLIC_CPU_MXINT9_PRI_M  ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S))
-#define PLIC_CPU_MXINT9_PRI_V  0xF
-#define PLIC_CPU_MXINT9_PRI_S  0
-
-#define PLIC_MXINT10_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x38)
-/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT10_PRI    0x0000000F
-#define PLIC_CPU_MXINT10_PRI_M  ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S))
-#define PLIC_CPU_MXINT10_PRI_V  0xF
-#define PLIC_CPU_MXINT10_PRI_S  0
-
-#define PLIC_MXINT11_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x3C)
-/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT11_PRI    0x0000000F
-#define PLIC_CPU_MXINT11_PRI_M  ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S))
-#define PLIC_CPU_MXINT11_PRI_V  0xF
-#define PLIC_CPU_MXINT11_PRI_S  0
-
-#define PLIC_MXINT12_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x40)
-/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT12_PRI    0x0000000F
-#define PLIC_CPU_MXINT12_PRI_M  ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S))
-#define PLIC_CPU_MXINT12_PRI_V  0xF
-#define PLIC_CPU_MXINT12_PRI_S  0
-
-#define PLIC_MXINT13_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x44)
-/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT13_PRI    0x0000000F
-#define PLIC_CPU_MXINT13_PRI_M  ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S))
-#define PLIC_CPU_MXINT13_PRI_V  0xF
-#define PLIC_CPU_MXINT13_PRI_S  0
-
-#define PLIC_MXINT14_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x48)
-/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT14_PRI    0x0000000F
-#define PLIC_CPU_MXINT14_PRI_M  ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S))
-#define PLIC_CPU_MXINT14_PRI_V  0xF
-#define PLIC_CPU_MXINT14_PRI_S  0
-
-#define PLIC_MXINT15_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x4C)
-/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT15_PRI    0x0000000F
-#define PLIC_CPU_MXINT15_PRI_M  ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S))
-#define PLIC_CPU_MXINT15_PRI_V  0xF
-#define PLIC_CPU_MXINT15_PRI_S  0
-
-#define PLIC_MXINT16_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x50)
-/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT16_PRI    0x0000000F
-#define PLIC_CPU_MXINT16_PRI_M  ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S))
-#define PLIC_CPU_MXINT16_PRI_V  0xF
-#define PLIC_CPU_MXINT16_PRI_S  0
-
-#define PLIC_MXINT17_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x54)
-/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT17_PRI    0x0000000F
-#define PLIC_CPU_MXINT17_PRI_M  ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S))
-#define PLIC_CPU_MXINT17_PRI_V  0xF
-#define PLIC_CPU_MXINT17_PRI_S  0
-
-#define PLIC_MXINT18_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x58)
-/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT18_PRI    0x0000000F
-#define PLIC_CPU_MXINT18_PRI_M  ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S))
-#define PLIC_CPU_MXINT18_PRI_V  0xF
-#define PLIC_CPU_MXINT18_PRI_S  0
-
-#define PLIC_MXINT19_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x5C)
-/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT19_PRI    0x0000000F
-#define PLIC_CPU_MXINT19_PRI_M  ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S))
-#define PLIC_CPU_MXINT19_PRI_V  0xF
-#define PLIC_CPU_MXINT19_PRI_S  0
-
-#define PLIC_MXINT20_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x60)
-/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT20_PRI    0x0000000F
-#define PLIC_CPU_MXINT20_PRI_M  ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S))
-#define PLIC_CPU_MXINT20_PRI_V  0xF
-#define PLIC_CPU_MXINT20_PRI_S  0
-
-#define PLIC_MXINT21_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x64)
-/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT21_PRI    0x0000000F
-#define PLIC_CPU_MXINT21_PRI_M  ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S))
-#define PLIC_CPU_MXINT21_PRI_V  0xF
-#define PLIC_CPU_MXINT21_PRI_S  0
-
-#define PLIC_MXINT22_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x68)
-/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT22_PRI    0x0000000F
-#define PLIC_CPU_MXINT22_PRI_M  ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S))
-#define PLIC_CPU_MXINT22_PRI_V  0xF
-#define PLIC_CPU_MXINT22_PRI_S  0
-
-#define PLIC_MXINT23_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x6C)
-/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT23_PRI    0x0000000F
-#define PLIC_CPU_MXINT23_PRI_M  ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S))
-#define PLIC_CPU_MXINT23_PRI_V  0xF
-#define PLIC_CPU_MXINT23_PRI_S  0
-
-#define PLIC_MXINT24_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x70)
-/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT24_PRI    0x0000000F
-#define PLIC_CPU_MXINT24_PRI_M  ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S))
-#define PLIC_CPU_MXINT24_PRI_V  0xF
-#define PLIC_CPU_MXINT24_PRI_S  0
-
-#define PLIC_MXINT25_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x74)
-/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT25_PRI    0x0000000F
-#define PLIC_CPU_MXINT25_PRI_M  ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S))
-#define PLIC_CPU_MXINT25_PRI_V  0xF
-#define PLIC_CPU_MXINT25_PRI_S  0
-
-#define PLIC_MXINT26_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x78)
-/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT26_PRI    0x0000000F
-#define PLIC_CPU_MXINT26_PRI_M  ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S))
-#define PLIC_CPU_MXINT26_PRI_V  0xF
-#define PLIC_CPU_MXINT26_PRI_S  0
-
-#define PLIC_MXINT27_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x7C)
-/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT27_PRI    0x0000000F
-#define PLIC_CPU_MXINT27_PRI_M  ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S))
-#define PLIC_CPU_MXINT27_PRI_V  0xF
-#define PLIC_CPU_MXINT27_PRI_S  0
-
-#define PLIC_MXINT28_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x80)
-/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT28_PRI    0x0000000F
-#define PLIC_CPU_MXINT28_PRI_M  ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S))
-#define PLIC_CPU_MXINT28_PRI_V  0xF
-#define PLIC_CPU_MXINT28_PRI_S  0
-
-#define PLIC_MXINT29_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x84)
-/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT29_PRI    0x0000000F
-#define PLIC_CPU_MXINT29_PRI_M  ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S))
-#define PLIC_CPU_MXINT29_PRI_V  0xF
-#define PLIC_CPU_MXINT29_PRI_S  0
-
-#define PLIC_MXINT30_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x88)
-/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT30_PRI    0x0000000F
-#define PLIC_CPU_MXINT30_PRI_M  ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S))
-#define PLIC_CPU_MXINT30_PRI_V  0xF
-#define PLIC_CPU_MXINT30_PRI_S  0
-
-#define PLIC_MXINT31_PRI_REG          (DR_REG_PLIC_MX_BASE + 0x8C)
-/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT31_PRI    0x0000000F
-#define PLIC_CPU_MXINT31_PRI_M  ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S))
-#define PLIC_CPU_MXINT31_PRI_V  0xF
-#define PLIC_CPU_MXINT31_PRI_S  0
-
-#define PLIC_MXINT_THRESH_REG          (DR_REG_PLIC_MX_BASE + 0x90)
-/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
-/*description: .*/
-#define PLIC_CPU_MXINT_THRESH    0x000000FF
-#define PLIC_CPU_MXINT_THRESH_M  ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S))
-#define PLIC_CPU_MXINT_THRESH_V  0xFF
-#define PLIC_CPU_MXINT_THRESH_S  0
-
-#define PLIC_MXINT_CLAIM_REG         (DR_REG_PLIC_MX_BASE + 0x94)
-/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/
-#define PLIC_CPU_MXINT_CLAIM    0xFFFFFFFF
-#define PLIC_CPU_MXINT_CLAIM_M  ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S))
-#define PLIC_CPU_MXINT_CLAIM_V  0xFFFFFFFF
-#define PLIC_CPU_MXINT_CLAIM_S  0
-
-/*PLIC UX*/
-#define PLIC_UXINT_ENABLE_REG          (DR_REG_PLIC_UX_BASE + 0x0)
-/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT_ENABLE    0xFFFFFFFF
-#define PLIC_CPU_UXINT_ENABLE_M  ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S))
-#define PLIC_CPU_UXINT_ENABLE_V  0xFFFFFFFF
-#define PLIC_CPU_UXINT_ENABLE_S  0
-
-#define PLIC_UXINT_TYPE_REG          (DR_REG_PLIC_UX_BASE + 0x4)
-/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT_TYPE    0xFFFFFFFF
-#define PLIC_CPU_UXINT_TYPE_M  ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S))
-#define PLIC_CPU_UXINT_TYPE_V  0xFFFFFFFF
-#define PLIC_CPU_UXINT_TYPE_S  0
-
-#define PLIC_UXINT_CLEAR_REG          (DR_REG_PLIC_UX_BASE + 0x8)
-/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT_CLEAR    0xFFFFFFFF
-#define PLIC_CPU_UXINT_CLEAR_M  ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S))
-#define PLIC_CPU_UXINT_CLEAR_V  0xFFFFFFFF
-#define PLIC_CPU_UXINT_CLEAR_S  0
-
-#define PLIC_EUIP_STATUS_REG          (DR_REG_PLIC_UX_BASE + 0xC)
-/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define PLIC_CPU_EIP_STATUS    0xFFFFFFFF
-#define PLIC_CPU_EIP_STATUS_M  ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
-#define PLIC_CPU_EIP_STATUS_V  0xFFFFFFFF
-#define PLIC_CPU_EIP_STATUS_S  0
-
-#define PLIC_UXINT0_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x10)
-/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT0_PRI    0x0000000F
-#define PLIC_CPU_UXINT0_PRI_M  ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S))
-#define PLIC_CPU_UXINT0_PRI_V  0xF
-#define PLIC_CPU_UXINT0_PRI_S  0
-
-#define PLIC_UXINT1_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x14)
-/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT1_PRI    0x0000000F
-#define PLIC_CPU_UXINT1_PRI_M  ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S))
-#define PLIC_CPU_UXINT1_PRI_V  0xF
-#define PLIC_CPU_UXINT1_PRI_S  0
-
-#define PLIC_UXINT2_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x18)
-/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT2_PRI    0x0000000F
-#define PLIC_CPU_UXINT2_PRI_M  ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S))
-#define PLIC_CPU_UXINT2_PRI_V  0xF
-#define PLIC_CPU_UXINT2_PRI_S  0
-
-#define PLIC_UXINT3_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x1C)
-/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT3_PRI    0x0000000F
-#define PLIC_CPU_UXINT3_PRI_M  ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S))
-#define PLIC_CPU_UXINT3_PRI_V  0xF
-#define PLIC_CPU_UXINT3_PRI_S  0
-
-#define PLIC_UXINT4_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x20)
-/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT4_PRI    0x0000000F
-#define PLIC_CPU_UXINT4_PRI_M  ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S))
-#define PLIC_CPU_UXINT4_PRI_V  0xF
-#define PLIC_CPU_UXINT4_PRI_S  0
-
-#define PLIC_UXINT5_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x24)
-/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT5_PRI    0x0000000F
-#define PLIC_CPU_UXINT5_PRI_M  ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S))
-#define PLIC_CPU_UXINT5_PRI_V  0xF
-#define PLIC_CPU_UXINT5_PRI_S  0
-
-#define PLIC_UXINT6_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x28)
-/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT6_PRI    0x0000000F
-#define PLIC_CPU_UXINT6_PRI_M  ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S))
-#define PLIC_CPU_UXINT6_PRI_V  0xF
-#define PLIC_CPU_UXINT6_PRI_S  0
-
-#define PLIC_UXINT7_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x2C)
-/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT7_PRI    0x0000000F
-#define PLIC_CPU_UXINT7_PRI_M  ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S))
-#define PLIC_CPU_UXINT7_PRI_V  0xF
-#define PLIC_CPU_UXINT7_PRI_S  0
-
-#define PLIC_UXINT8_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x30)
-/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT8_PRI    0x0000000F
-#define PLIC_CPU_UXINT8_PRI_M  ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S))
-#define PLIC_CPU_UXINT8_PRI_V  0xF
-#define PLIC_CPU_UXINT8_PRI_S  0
-
-#define PLIC_UXINT9_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x34)
-/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT9_PRI    0x0000000F
-#define PLIC_CPU_UXINT9_PRI_M  ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S))
-#define PLIC_CPU_UXINT9_PRI_V  0xF
-#define PLIC_CPU_UXINT9_PRI_S  0
-
-#define PLIC_UXINT10_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x38)
-/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT10_PRI    0x0000000F
-#define PLIC_CPU_UXINT10_PRI_M  ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S))
-#define PLIC_CPU_UXINT10_PRI_V  0xF
-#define PLIC_CPU_UXINT10_PRI_S  0
-
-#define PLIC_UXINT11_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x3C)
-/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT11_PRI    0x0000000F
-#define PLIC_CPU_UXINT11_PRI_M  ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S))
-#define PLIC_CPU_UXINT11_PRI_V  0xF
-#define PLIC_CPU_UXINT11_PRI_S  0
-
-#define PLIC_UXINT12_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x40)
-/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT12_PRI    0x0000000F
-#define PLIC_CPU_UXINT12_PRI_M  ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S))
-#define PLIC_CPU_UXINT12_PRI_V  0xF
-#define PLIC_CPU_UXINT12_PRI_S  0
-
-#define PLIC_UXINT13_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x44)
-/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT13_PRI    0x0000000F
-#define PLIC_CPU_UXINT13_PRI_M  ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S))
-#define PLIC_CPU_UXINT13_PRI_V  0xF
-#define PLIC_CPU_UXINT13_PRI_S  0
-
-#define PLIC_UXINT14_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x48)
-/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT14_PRI    0x0000000F
-#define PLIC_CPU_UXINT14_PRI_M  ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S))
-#define PLIC_CPU_UXINT14_PRI_V  0xF
-#define PLIC_CPU_UXINT14_PRI_S  0
-
-#define PLIC_UXINT15_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x4C)
-/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT15_PRI    0x0000000F
-#define PLIC_CPU_UXINT15_PRI_M  ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S))
-#define PLIC_CPU_UXINT15_PRI_V  0xF
-#define PLIC_CPU_UXINT15_PRI_S  0
-
-#define PLIC_UXINT16_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x50)
-/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT16_PRI    0x0000000F
-#define PLIC_CPU_UXINT16_PRI_M  ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S))
-#define PLIC_CPU_UXINT16_PRI_V  0xF
-#define PLIC_CPU_UXINT16_PRI_S  0
-
-#define PLIC_UXINT17_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x54)
-/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT17_PRI    0x0000000F
-#define PLIC_CPU_UXINT17_PRI_M  ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S))
-#define PLIC_CPU_UXINT17_PRI_V  0xF
-#define PLIC_CPU_UXINT17_PRI_S  0
-
-#define PLIC_UXINT18_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x58)
-/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT18_PRI    0x0000000F
-#define PLIC_CPU_UXINT18_PRI_M  ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S))
-#define PLIC_CPU_UXINT18_PRI_V  0xF
-#define PLIC_CPU_UXINT18_PRI_S  0
-
-#define PLIC_UXINT19_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x5C)
-/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT19_PRI    0x0000000F
-#define PLIC_CPU_UXINT19_PRI_M  ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S))
-#define PLIC_CPU_UXINT19_PRI_V  0xF
-#define PLIC_CPU_UXINT19_PRI_S  0
-
-#define PLIC_UXINT20_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x60)
-/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT20_PRI    0x0000000F
-#define PLIC_CPU_UXINT20_PRI_M  ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S))
-#define PLIC_CPU_UXINT20_PRI_V  0xF
-#define PLIC_CPU_UXINT20_PRI_S  0
-
-#define PLIC_UXINT21_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x64)
-/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT21_PRI    0x0000000F
-#define PLIC_CPU_UXINT21_PRI_M  ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S))
-#define PLIC_CPU_UXINT21_PRI_V  0xF
-#define PLIC_CPU_UXINT21_PRI_S  0
-
-#define PLIC_UXINT22_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x68)
-/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT22_PRI    0x0000000F
-#define PLIC_CPU_UXINT22_PRI_M  ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S))
-#define PLIC_CPU_UXINT22_PRI_V  0xF
-#define PLIC_CPU_UXINT22_PRI_S  0
-
-#define PLIC_UXINT23_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x6C)
-/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT23_PRI    0x0000000F
-#define PLIC_CPU_UXINT23_PRI_M  ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S))
-#define PLIC_CPU_UXINT23_PRI_V  0xF
-#define PLIC_CPU_UXINT23_PRI_S  0
-
-#define PLIC_UXINT24_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x70)
-/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT24_PRI    0x0000000F
-#define PLIC_CPU_UXINT24_PRI_M  ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S))
-#define PLIC_CPU_UXINT24_PRI_V  0xF
-#define PLIC_CPU_UXINT24_PRI_S  0
-
-#define PLIC_UXINT25_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x74)
-/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT25_PRI    0x0000000F
-#define PLIC_CPU_UXINT25_PRI_M  ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S))
-#define PLIC_CPU_UXINT25_PRI_V  0xF
-#define PLIC_CPU_UXINT25_PRI_S  0
-
-#define PLIC_UXINT26_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x78)
-/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT26_PRI    0x0000000F
-#define PLIC_CPU_UXINT26_PRI_M  ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S))
-#define PLIC_CPU_UXINT26_PRI_V  0xF
-#define PLIC_CPU_UXINT26_PRI_S  0
-
-#define PLIC_UXINT27_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x7C)
-/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT27_PRI    0x0000000F
-#define PLIC_CPU_UXINT27_PRI_M  ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S))
-#define PLIC_CPU_UXINT27_PRI_V  0xF
-#define PLIC_CPU_UXINT27_PRI_S  0
-
-#define PLIC_UXINT28_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x80)
-/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT28_PRI    0x0000000F
-#define PLIC_CPU_UXINT28_PRI_M  ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S))
-#define PLIC_CPU_UXINT28_PRI_V  0xF
-#define PLIC_CPU_UXINT28_PRI_S  0
-
-#define PLIC_UXINT29_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x84)
-/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT29_PRI    0x0000000F
-#define PLIC_CPU_UXINT29_PRI_M  ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S))
-#define PLIC_CPU_UXINT29_PRI_V  0xF
-#define PLIC_CPU_UXINT29_PRI_S  0
-
-#define PLIC_UXINT30_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x88)
-/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT30_PRI    0x0000000F
-#define PLIC_CPU_UXINT30_PRI_M  ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S))
-#define PLIC_CPU_UXINT30_PRI_V  0xF
-#define PLIC_CPU_UXINT30_PRI_S  0
-
-#define PLIC_UXINT31_PRI_REG          (DR_REG_PLIC_UX_BASE + 0x8C)
-/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT31_PRI    0x0000000F
-#define PLIC_CPU_UXINT31_PRI_M  ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S))
-#define PLIC_CPU_UXINT31_PRI_V  0xF
-#define PLIC_CPU_UXINT31_PRI_S  0
-
-#define PLIC_UXINT_THRESH_REG          (DR_REG_PLIC_UX_BASE + 0x90)
-/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT_THRESH    0x000000FF
-#define PLIC_CPU_UXINT_THRESH_M  ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S))
-#define PLIC_CPU_UXINT_THRESH_V  0xFF
-#define PLIC_CPU_UXINT_THRESH_S  0
-
-#define PLIC_UXINT_CLAIM_REG         (DR_REG_PLIC_UX_BASE + 0x94)
-/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define PLIC_CPU_UXINT_CLAIM    0xFFFFFFFF
-#define PLIC_CPU_UXINT_CLAIM_M  ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S))
-#define PLIC_CPU_UXINT_CLAIM_V  0xFFFFFFFF
-#define PLIC_CPU_UXINT_CLAIM_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
index c4b995c52a..f2c4877096 100644
--- a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
+++ b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
@@ -1,68 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_ICG_MAP_H_
-#define _SOC_ICG_MAP_H_
-
-#define PMU_ICG_APB_ENA_CAN0                               18
-#define PMU_ICG_APB_ENA_CAN1                               19
-#define PMU_ICG_APB_ENA_GDMA                               1
-#define PMU_ICG_APB_ENA_I2C                                13
-#define PMU_ICG_APB_ENA_I2S                                4
-#define PMU_ICG_APB_ENA_INTMTX                             3
-#define PMU_ICG_APB_ENA_IOMUX                              26
-#define PMU_ICG_APB_ENA_LEDC                               14
-#define PMU_ICG_APB_ENA_MEM_MONITOR                        25
-#define PMU_ICG_APB_ENA_MSPI                               5
-#define PMU_ICG_APB_ENA_PARL                               23
-#define PMU_ICG_APB_ENA_PCNT                               20
-#define PMU_ICG_APB_ENA_PVT_MONITOR                        27
-#define PMU_ICG_APB_ENA_PWM                                21
-#define PMU_ICG_APB_ENA_REGDMA                             24
-#define PMU_ICG_APB_ENA_RMT                                15
-#define PMU_ICG_APB_ENA_SARADC                             9
-#define PMU_ICG_APB_ENA_SEC                                0
-#define PMU_ICG_APB_ENA_SOC_ETM                            22
-#define PMU_ICG_APB_ENA_SPI2                               2
-#define PMU_ICG_APB_ENA_SYSTIMER                           16
-#define PMU_ICG_APB_ENA_TG0                                11
-#define PMU_ICG_APB_ENA_TG1                                12
-#define PMU_ICG_APB_ENA_UART0                              6
-#define PMU_ICG_APB_ENA_UART1                              7
-#define PMU_ICG_APB_ENA_UHCI                               8
-#define PMU_ICG_APB_ENA_USB_DEVICE                         17
-#define PMU_ICG_FUNC_ENA_CAN0                              31
-#define PMU_ICG_FUNC_ENA_CAN1                              30
-#define PMU_ICG_FUNC_ENA_I2C                               29
-#define PMU_ICG_FUNC_ENA_I2S_RX                            2
-#define PMU_ICG_FUNC_ENA_I2S_TX                            7
-#define PMU_ICG_FUNC_ENA_IOMUX                             28
-#define PMU_ICG_FUNC_ENA_LEDC                              27
-#define PMU_ICG_FUNC_ENA_MEM_MONITOR                       10
-#define PMU_ICG_FUNC_ENA_MSPI                              26
-#define PMU_ICG_FUNC_ENA_PARL_RX                           25
-#define PMU_ICG_FUNC_ENA_PARL_TX                           24
-#define PMU_ICG_FUNC_ENA_PVT_MONITOR                       23
-#define PMU_ICG_FUNC_ENA_PWM                               22
-#define PMU_ICG_FUNC_ENA_RMT                               21
-#define PMU_ICG_FUNC_ENA_SARADC                            20
-#define PMU_ICG_FUNC_ENA_SEC                               19
-#define PMU_ICG_FUNC_ENA_SPI2                              1
-#define PMU_ICG_FUNC_ENA_SYSTIMER                          18
-#define PMU_ICG_FUNC_ENA_TG0                               14
-#define PMU_ICG_FUNC_ENA_TG1                               13
-#define PMU_ICG_FUNC_ENA_TSENS                             12
-#define PMU_ICG_FUNC_ENA_UART0                             3
-#define PMU_ICG_FUNC_ENA_UART1                             4
-#define PMU_ICG_FUNC_ENA_USB_DEVICE                        6
-#define PMU_ICG_FUNC_ENA_GDMA                              0
-#define PMU_ICG_FUNC_ENA_SOC_ETM                           16
-#define PMU_ICG_FUNC_ENA_REGDMA                            8
-#define PMU_ICG_FUNC_ENA_RETENTION                         9
-#define PMU_ICG_FUNC_ENA_SDIO_SLAVE                        11
-#define PMU_ICG_FUNC_ENA_UHCI                              5
-#define PMU_ICG_FUNC_ENA_HPCORE                            17
-#define PMU_ICG_FUNC_ENA_HPBUS                             15
-#endif  /* _SOC_ICG_MAP_H_ */
diff --git a/components/soc/esp32p4/include/soc/pwm_reg.h b/components/soc/esp32p4/include/soc/pwm_reg.h
deleted file mode 100644
index e526c38e60..0000000000
--- a/components/soc/esp32p4/include/soc/pwm_reg.h
+++ /dev/null
@@ -1,4514 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MCPWM_CLK_CFG_REG register
- *  PWM clock prescaler register.
- */
-#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0)
-/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
- *  (PWM_CLK_PRESCALE + 1).
- */
-#define MCPWM_CLK_PRESCALE    0x000000FFU
-#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
-#define MCPWM_CLK_PRESCALE_V  0x000000FFU
-#define MCPWM_CLK_PRESCALE_S  0
-
-/** MCPWM_TIMER0_CFG0_REG register
- *  PWM timer0 period and update method configuration register.
- */
-#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER0_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer0
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer0 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER0_CFG1_REG register
- *  PWM timer$n working mode and start/stop control register.
- */
-#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8)
-/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
- *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
- *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
- *  stops at the next TEP.\\TEP here and below means the event that happens when the
- *  timer equals to period
- */
-#define MCPWM_TIMER0_START    0x00000007U
-#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
-#define MCPWM_TIMER0_START_V  0x00000007U
-#define MCPWM_TIMER0_START_S  0
-/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER0_MOD    0x00000003U
-#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
-#define MCPWM_TIMER0_MOD_V  0x00000003U
-#define MCPWM_TIMER0_MOD_S  3
-
-/** MCPWM_TIMER0_SYNC_REG register
- *  PWM timer$n sync function configuration register.
- */
-#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc)
-/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer$n reloading with phase on sync input
- *  event is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
-#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER0_SYNCI_EN_S  0
-/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
-#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER0_SYNC_SW_S  1
-/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
-#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_S  2
-/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer$n reload on sync event.
- */
-#define MCPWM_TIMER0_PHASE    0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
-#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_S  4
-/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
-#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER0_STATUS_REG register
- *  PWM timer$n status register.
- */
-#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10)
-/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer$n counter value.
- */
-#define MCPWM_TIMER0_VALUE    0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
-#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_S  0
-/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER0_DIRECTION    (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
-#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_DIRECTION_S  16
-
-/** MCPWM_TIMER1_CFG0_REG register
- *  PWM timer1 period and update method configuration register.
- */
-#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER1_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer1
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer1 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER1_CFG1_REG register
- *  PWM timer$n working mode and start/stop control register.
- */
-#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18)
-/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
- *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
- *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
- *  stops at the next TEP.\\TEP here and below means the event that happens when the
- *  timer equals to period
- */
-#define MCPWM_TIMER1_START    0x00000007U
-#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
-#define MCPWM_TIMER1_START_V  0x00000007U
-#define MCPWM_TIMER1_START_S  0
-/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER1_MOD    0x00000003U
-#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
-#define MCPWM_TIMER1_MOD_V  0x00000003U
-#define MCPWM_TIMER1_MOD_S  3
-
-/** MCPWM_TIMER1_SYNC_REG register
- *  PWM timer$n sync function configuration register.
- */
-#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c)
-/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer$n reloading with phase on sync input
- *  event is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
-#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER1_SYNCI_EN_S  0
-/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
-#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER1_SYNC_SW_S  1
-/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
-#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_S  2
-/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer$n reload on sync event.
- */
-#define MCPWM_TIMER1_PHASE    0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
-#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_S  4
-/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
-#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER1_STATUS_REG register
- *  PWM timer$n status register.
- */
-#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20)
-/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer$n counter value.
- */
-#define MCPWM_TIMER1_VALUE    0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
-#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_S  0
-/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER1_DIRECTION    (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
-#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_DIRECTION_S  16
-
-/** MCPWM_TIMER2_CFG0_REG register
- *  PWM timer2 period and update method configuration register.
- */
-#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER2_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer2
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer2 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER2_CFG1_REG register
- *  PWM timer$n working mode and start/stop control register.
- */
-#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28)
-/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
- *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
- *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
- *  stops at the next TEP.\\TEP here and below means the event that happens when the
- *  timer equals to period
- */
-#define MCPWM_TIMER2_START    0x00000007U
-#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
-#define MCPWM_TIMER2_START_V  0x00000007U
-#define MCPWM_TIMER2_START_S  0
-/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER2_MOD    0x00000003U
-#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
-#define MCPWM_TIMER2_MOD_V  0x00000003U
-#define MCPWM_TIMER2_MOD_S  3
-
-/** MCPWM_TIMER2_SYNC_REG register
- *  PWM timer$n sync function configuration register.
- */
-#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c)
-/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer$n reloading with phase on sync input
- *  event is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
-#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER2_SYNCI_EN_S  0
-/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
-#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER2_SYNC_SW_S  1
-/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
-#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_S  2
-/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer$n reload on sync event.
- */
-#define MCPWM_TIMER2_PHASE    0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
-#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_S  4
-/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
-#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER2_STATUS_REG register
- *  PWM timer$n status register.
- */
-#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30)
-/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer$n counter value.
- */
-#define MCPWM_TIMER2_VALUE    0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
-#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_S  0
-/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER2_DIRECTION    (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
-#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_DIRECTION_S  16
-
-/** MCPWM_TIMER_SYNCI_CFG_REG register
- *  Synchronization input selection register for PWM timers.
- */
-#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34)
-/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
- *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER0_SYNCISEL    0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
-#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_S  0
-/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
- *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER1_SYNCISEL    0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
-#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_S  3
-/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
- *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER2_SYNCISEL    0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
-#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_S  6
-/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
-/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
-/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
-
-/** MCPWM_OPERATOR_TIMERSEL_REG register
- *  PWM operator's timer select register
- */
-#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38)
-/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
-#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_S  0
-/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
-#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_S  2
-/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
-#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_S  4
-
-/** MCPWM_GEN0_STMP_CFG_REG register
- *  Generator0 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 0 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 0 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN0_TSTMP_A_REG register
- *  Generator$n time stamp A's shadow register
- */
-#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40)
-/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp A's shadow register.
- */
-#define MCPWM_CMPR0_A    0x0000FFFFU
-#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
-#define MCPWM_CMPR0_A_V  0x0000FFFFU
-#define MCPWM_CMPR0_A_S  0
-
-/** MCPWM_GEN0_TSTMP_B_REG register
- *  Generator$n time stamp B's shadow register
- */
-#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44)
-/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp B's shadow register.
- */
-#define MCPWM_CMPR0_B    0x0000FFFFU
-#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
-#define MCPWM_CMPR0_B_V  0x0000FFFFU
-#define MCPWM_CMPR0_B_S  0
-
-/** MCPWM_GEN0_CFG0_REG register
- *  Generator$n fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48)
-/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator $n's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
-#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_S  0
-/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator $n event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN0_T0_SEL    0x00000007U
-#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
-#define MCPWM_GEN0_T0_SEL_V  0x00000007U
-#define MCPWM_GEN0_T0_SEL_S  4
-/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator $n event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN0_T1_SEL    0x00000007U
-#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
-#define MCPWM_GEN0_T1_SEL_V  0x00000007U
-#define MCPWM_GEN0_T1_SEL_S  7
-
-/** MCPWM_GEN0_FORCE_REG register
- *  Generator$n output signal force mode register.
- */
-#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c)
-/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator$n.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
-#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_A_NCIFORCE_S  10
-/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
-#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_B_NCIFORCE_S  13
-/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN0_A_REG register
- *  PWM$n output signal A actions configuration register
- */
-#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50)
-/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEZ    0x00000003U
-#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
-#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_UTEZ_S  0
-/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEP    0x00000003U
-#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
-#define MCPWM_GEN0_A_UTEP_V  0x00000003U
-#define MCPWM_GEN0_A_UTEP_S  2
-/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEA    0x00000003U
-#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
-#define MCPWM_GEN0_A_UTEA_V  0x00000003U
-#define MCPWM_GEN0_A_UTEA_S  4
-/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEB    0x00000003U
-#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
-#define MCPWM_GEN0_A_UTEB_V  0x00000003U
-#define MCPWM_GEN0_A_UTEB_S  6
-/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UT0    0x00000003U
-#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
-#define MCPWM_GEN0_A_UT0_V  0x00000003U
-#define MCPWM_GEN0_A_UT0_S  8
-/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UT1    0x00000003U
-#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
-#define MCPWM_GEN0_A_UT1_V  0x00000003U
-#define MCPWM_GEN0_A_UT1_S  10
-/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEZ    0x00000003U
-#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
-#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_DTEZ_S  12
-/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEP    0x00000003U
-#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
-#define MCPWM_GEN0_A_DTEP_V  0x00000003U
-#define MCPWM_GEN0_A_DTEP_S  14
-/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEA    0x00000003U
-#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
-#define MCPWM_GEN0_A_DTEA_V  0x00000003U
-#define MCPWM_GEN0_A_DTEA_S  16
-/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEB    0x00000003U
-#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
-#define MCPWM_GEN0_A_DTEB_V  0x00000003U
-#define MCPWM_GEN0_A_DTEB_S  18
-/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DT0    0x00000003U
-#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
-#define MCPWM_GEN0_A_DT0_V  0x00000003U
-#define MCPWM_GEN0_A_DT0_S  20
-/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DT1    0x00000003U
-#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
-#define MCPWM_GEN0_A_DT1_V  0x00000003U
-#define MCPWM_GEN0_A_DT1_S  22
-
-/** MCPWM_GEN0_B_REG register
- *  PWM$n output signal B actions configuration register
- */
-#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54)
-/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEZ    0x00000003U
-#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
-#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_UTEZ_S  0
-/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEP    0x00000003U
-#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
-#define MCPWM_GEN0_B_UTEP_V  0x00000003U
-#define MCPWM_GEN0_B_UTEP_S  2
-/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEA    0x00000003U
-#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
-#define MCPWM_GEN0_B_UTEA_V  0x00000003U
-#define MCPWM_GEN0_B_UTEA_S  4
-/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEB    0x00000003U
-#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
-#define MCPWM_GEN0_B_UTEB_V  0x00000003U
-#define MCPWM_GEN0_B_UTEB_S  6
-/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UT0    0x00000003U
-#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
-#define MCPWM_GEN0_B_UT0_V  0x00000003U
-#define MCPWM_GEN0_B_UT0_S  8
-/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UT1    0x00000003U
-#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
-#define MCPWM_GEN0_B_UT1_V  0x00000003U
-#define MCPWM_GEN0_B_UT1_S  10
-/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEZ    0x00000003U
-#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
-#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_DTEZ_S  12
-/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEP    0x00000003U
-#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
-#define MCPWM_GEN0_B_DTEP_V  0x00000003U
-#define MCPWM_GEN0_B_DTEP_S  14
-/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEA    0x00000003U
-#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
-#define MCPWM_GEN0_B_DTEA_V  0x00000003U
-#define MCPWM_GEN0_B_DTEA_S  16
-/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEB    0x00000003U
-#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
-#define MCPWM_GEN0_B_DTEB_V  0x00000003U
-#define MCPWM_GEN0_B_DTEB_S  18
-/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DT0    0x00000003U
-#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
-#define MCPWM_GEN0_B_DT0_V  0x00000003U
-#define MCPWM_GEN0_B_DT0_S  20
-/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DT1    0x00000003U
-#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
-#define MCPWM_GEN0_B_DT1_V  0x00000003U
-#define MCPWM_GEN0_B_DT1_S  22
-
-/** MCPWM_DT0_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
-/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
-#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_S  0
-/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
-#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_S  4
-/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB0_DEB_MODE    (BIT(8))
-#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
-#define MCPWM_DB0_DEB_MODE_V  0x00000001U
-#define MCPWM_DB0_DEB_MODE_S  8
-/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
-#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_A_OUTSWAP_S  9
-/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
-#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_B_OUTSWAP_S  10
-/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DB0_RED_INSEL    (BIT(11))
-#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
-#define MCPWM_DB0_RED_INSEL_V  0x00000001U
-#define MCPWM_DB0_RED_INSEL_S  11
-/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DB0_FED_INSEL    (BIT(12))
-#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
-#define MCPWM_DB0_FED_INSEL_V  0x00000001U
-#define MCPWM_DB0_FED_INSEL_S  12
-/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
-#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_RED_OUTINVERT_S  13
-/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
-#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_FED_OUTINVERT_S  14
-/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
-#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_A_OUTBYPASS_S  15
-/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
-#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_B_OUTBYPASS_S  16
-/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DB0_CLK_SEL    (BIT(17))
-#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
-#define MCPWM_DB0_CLK_SEL_V  0x00000001U
-#define MCPWM_DB0_CLK_SEL_S  17
-
-/** MCPWM_DT0_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
-/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DB0_FED    0x0000FFFFU
-#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
-#define MCPWM_DB0_FED_V  0x0000FFFFU
-#define MCPWM_DB0_FED_S  0
-
-/** MCPWM_DT0_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
-/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DB0_RED    0x0000FFFFU
-#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
-#define MCPWM_DB0_RED_V  0x0000FFFFU
-#define MCPWM_DB0_RED_S  0
-
-/** MCPWM_CARRIER0_CFG_REG register
- *  Carrier$n configuration register
- */
-#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64)
-/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CHOPPER0_EN    (BIT(0))
-#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
-#define MCPWM_CHOPPER0_EN_V  0x00000001U
-#define MCPWM_CHOPPER0_EN_S  0
-/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
-#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_S  1
-/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
- */
-#define MCPWM_CHOPPER0_DUTY    0x00000007U
-#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
-#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER0_DUTY_S  5
-/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
-#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_S  8
-/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
-#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_OUT_INVERT_S  12
-/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
-#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_IN_INVERT_S  13
-
-/** MCPWM_FH0_CFG0_REG register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68)
-/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_SW_CBC    (BIT(0))
-#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
-#define MCPWM_TZ0_SW_CBC_V  0x00000001U
-#define MCPWM_TZ0_SW_CBC_S  0
-/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F2_CBC    (BIT(1))
-#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
-#define MCPWM_TZ0_F2_CBC_V  0x00000001U
-#define MCPWM_TZ0_F2_CBC_S  1
-/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F1_CBC    (BIT(2))
-#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
-#define MCPWM_TZ0_F1_CBC_V  0x00000001U
-#define MCPWM_TZ0_F1_CBC_S  2
-/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F0_CBC    (BIT(3))
-#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
-#define MCPWM_TZ0_F0_CBC_V  0x00000001U
-#define MCPWM_TZ0_F0_CBC_S  3
-/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_SW_OST    (BIT(4))
-#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
-#define MCPWM_TZ0_SW_OST_V  0x00000001U
-#define MCPWM_TZ0_SW_OST_S  4
-/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F2_OST    (BIT(5))
-#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
-#define MCPWM_TZ0_F2_OST_V  0x00000001U
-#define MCPWM_TZ0_F2_OST_S  5
-/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F1_OST    (BIT(6))
-#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
-#define MCPWM_TZ0_F1_OST_V  0x00000001U
-#define MCPWM_TZ0_F1_OST_S  6
-/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F0_OST    (BIT(7))
-#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
-#define MCPWM_TZ0_F0_OST_V  0x00000001U
-#define MCPWM_TZ0_F0_OST_S  7
-/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_CBC_D    0x00000003U
-#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
-#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_D_S  8
-/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_CBC_U    0x00000003U
-#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
-#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_U_S  10
-/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_OST_D    0x00000003U
-#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
-#define MCPWM_TZ0_A_OST_D_V  0x00000003U
-#define MCPWM_TZ0_A_OST_D_S  12
-/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_OST_U    0x00000003U
-#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
-#define MCPWM_TZ0_A_OST_U_V  0x00000003U
-#define MCPWM_TZ0_A_OST_U_S  14
-/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_CBC_D    0x00000003U
-#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
-#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_D_S  16
-/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_CBC_U    0x00000003U
-#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
-#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_U_S  18
-/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_OST_D    0x00000003U
-#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
-#define MCPWM_TZ0_B_OST_D_V  0x00000003U
-#define MCPWM_TZ0_B_OST_D_S  20
-/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_OST_U    0x00000003U
-#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
-#define MCPWM_TZ0_B_OST_U_V  0x00000003U
-#define MCPWM_TZ0_B_OST_U_S  22
-
-/** MCPWM_FH0_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c)
-/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_TZ0_CLR_OST    (BIT(0))
-#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
-#define MCPWM_TZ0_CLR_OST_V  0x00000001U
-#define MCPWM_TZ0_CLR_OST_S  0
-/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_TZ0_CBCPULSE    0x00000003U
-#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
-#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ0_CBCPULSE_S  1
-/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
-#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ0_FORCE_CBC_S  3
-/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_TZ0_FORCE_OST    (BIT(4))
-#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
-#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ0_FORCE_OST_S  4
-
-/** MCPWM_FH0_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70)
-/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_TZ0_CBC_ON    (BIT(0))
-#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
-#define MCPWM_TZ0_CBC_ON_V  0x00000001U
-#define MCPWM_TZ0_CBC_ON_S  0
-/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_TZ0_OST_ON    (BIT(1))
-#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
-#define MCPWM_TZ0_OST_ON_V  0x00000001U
-#define MCPWM_TZ0_OST_ON_S  1
-
-/** MCPWM_GEN1_STMP_CFG_REG register
- *  Generator1 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 1 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 1 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN1_TSTMP_A_REG register
- *  Generator$n time stamp A's shadow register
- */
-#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78)
-/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp A's shadow register.
- */
-#define MCPWM_CMPR1_A    0x0000FFFFU
-#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
-#define MCPWM_CMPR1_A_V  0x0000FFFFU
-#define MCPWM_CMPR1_A_S  0
-
-/** MCPWM_GEN1_TSTMP_B_REG register
- *  Generator$n time stamp B's shadow register
- */
-#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c)
-/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp B's shadow register.
- */
-#define MCPWM_CMPR1_B    0x0000FFFFU
-#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
-#define MCPWM_CMPR1_B_V  0x0000FFFFU
-#define MCPWM_CMPR1_B_S  0
-
-/** MCPWM_GEN1_CFG0_REG register
- *  Generator$n fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80)
-/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator $n's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
-#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_S  0
-/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator $n event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN1_T0_SEL    0x00000007U
-#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
-#define MCPWM_GEN1_T0_SEL_V  0x00000007U
-#define MCPWM_GEN1_T0_SEL_S  4
-/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator $n event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN1_T1_SEL    0x00000007U
-#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
-#define MCPWM_GEN1_T1_SEL_V  0x00000007U
-#define MCPWM_GEN1_T1_SEL_S  7
-
-/** MCPWM_GEN1_FORCE_REG register
- *  Generator$n output signal force mode register.
- */
-#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84)
-/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator$n.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
-#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_A_NCIFORCE_S  10
-/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
-#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_B_NCIFORCE_S  13
-/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN1_A_REG register
- *  PWM$n output signal A actions configuration register
- */
-#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88)
-/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEZ    0x00000003U
-#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
-#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_UTEZ_S  0
-/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEP    0x00000003U
-#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
-#define MCPWM_GEN1_A_UTEP_V  0x00000003U
-#define MCPWM_GEN1_A_UTEP_S  2
-/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEA    0x00000003U
-#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
-#define MCPWM_GEN1_A_UTEA_V  0x00000003U
-#define MCPWM_GEN1_A_UTEA_S  4
-/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEB    0x00000003U
-#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
-#define MCPWM_GEN1_A_UTEB_V  0x00000003U
-#define MCPWM_GEN1_A_UTEB_S  6
-/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UT0    0x00000003U
-#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
-#define MCPWM_GEN1_A_UT0_V  0x00000003U
-#define MCPWM_GEN1_A_UT0_S  8
-/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UT1    0x00000003U
-#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
-#define MCPWM_GEN1_A_UT1_V  0x00000003U
-#define MCPWM_GEN1_A_UT1_S  10
-/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEZ    0x00000003U
-#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
-#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_DTEZ_S  12
-/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEP    0x00000003U
-#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
-#define MCPWM_GEN1_A_DTEP_V  0x00000003U
-#define MCPWM_GEN1_A_DTEP_S  14
-/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEA    0x00000003U
-#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
-#define MCPWM_GEN1_A_DTEA_V  0x00000003U
-#define MCPWM_GEN1_A_DTEA_S  16
-/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEB    0x00000003U
-#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
-#define MCPWM_GEN1_A_DTEB_V  0x00000003U
-#define MCPWM_GEN1_A_DTEB_S  18
-/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DT0    0x00000003U
-#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
-#define MCPWM_GEN1_A_DT0_V  0x00000003U
-#define MCPWM_GEN1_A_DT0_S  20
-/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DT1    0x00000003U
-#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
-#define MCPWM_GEN1_A_DT1_V  0x00000003U
-#define MCPWM_GEN1_A_DT1_S  22
-
-/** MCPWM_GEN1_B_REG register
- *  PWM$n output signal B actions configuration register
- */
-#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c)
-/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEZ    0x00000003U
-#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
-#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_UTEZ_S  0
-/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEP    0x00000003U
-#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
-#define MCPWM_GEN1_B_UTEP_V  0x00000003U
-#define MCPWM_GEN1_B_UTEP_S  2
-/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEA    0x00000003U
-#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
-#define MCPWM_GEN1_B_UTEA_V  0x00000003U
-#define MCPWM_GEN1_B_UTEA_S  4
-/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEB    0x00000003U
-#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
-#define MCPWM_GEN1_B_UTEB_V  0x00000003U
-#define MCPWM_GEN1_B_UTEB_S  6
-/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UT0    0x00000003U
-#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
-#define MCPWM_GEN1_B_UT0_V  0x00000003U
-#define MCPWM_GEN1_B_UT0_S  8
-/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UT1    0x00000003U
-#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
-#define MCPWM_GEN1_B_UT1_V  0x00000003U
-#define MCPWM_GEN1_B_UT1_S  10
-/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEZ    0x00000003U
-#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
-#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_DTEZ_S  12
-/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEP    0x00000003U
-#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
-#define MCPWM_GEN1_B_DTEP_V  0x00000003U
-#define MCPWM_GEN1_B_DTEP_S  14
-/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEA    0x00000003U
-#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
-#define MCPWM_GEN1_B_DTEA_V  0x00000003U
-#define MCPWM_GEN1_B_DTEA_S  16
-/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEB    0x00000003U
-#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
-#define MCPWM_GEN1_B_DTEB_V  0x00000003U
-#define MCPWM_GEN1_B_DTEB_S  18
-/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DT0    0x00000003U
-#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
-#define MCPWM_GEN1_B_DT0_V  0x00000003U
-#define MCPWM_GEN1_B_DT0_S  20
-/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DT1    0x00000003U
-#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
-#define MCPWM_GEN1_B_DT1_V  0x00000003U
-#define MCPWM_GEN1_B_DT1_S  22
-
-/** MCPWM_DT1_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
-/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
-#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_S  0
-/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
-#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_S  4
-/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB1_DEB_MODE    (BIT(8))
-#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
-#define MCPWM_DB1_DEB_MODE_V  0x00000001U
-#define MCPWM_DB1_DEB_MODE_S  8
-/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
-#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_A_OUTSWAP_S  9
-/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
-#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_B_OUTSWAP_S  10
-/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DB1_RED_INSEL    (BIT(11))
-#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
-#define MCPWM_DB1_RED_INSEL_V  0x00000001U
-#define MCPWM_DB1_RED_INSEL_S  11
-/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DB1_FED_INSEL    (BIT(12))
-#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
-#define MCPWM_DB1_FED_INSEL_V  0x00000001U
-#define MCPWM_DB1_FED_INSEL_S  12
-/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
-#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_RED_OUTINVERT_S  13
-/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
-#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_FED_OUTINVERT_S  14
-/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
-#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_A_OUTBYPASS_S  15
-/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
-#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_B_OUTBYPASS_S  16
-/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DB1_CLK_SEL    (BIT(17))
-#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
-#define MCPWM_DB1_CLK_SEL_V  0x00000001U
-#define MCPWM_DB1_CLK_SEL_S  17
-
-/** MCPWM_DT1_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
-/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DB1_FED    0x0000FFFFU
-#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
-#define MCPWM_DB1_FED_V  0x0000FFFFU
-#define MCPWM_DB1_FED_S  0
-
-/** MCPWM_DT1_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
-/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DB1_RED    0x0000FFFFU
-#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
-#define MCPWM_DB1_RED_V  0x0000FFFFU
-#define MCPWM_DB1_RED_S  0
-
-/** MCPWM_CARRIER1_CFG_REG register
- *  Carrier$n configuration register
- */
-#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c)
-/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CHOPPER1_EN    (BIT(0))
-#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
-#define MCPWM_CHOPPER1_EN_V  0x00000001U
-#define MCPWM_CHOPPER1_EN_S  0
-/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
-#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_S  1
-/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
- */
-#define MCPWM_CHOPPER1_DUTY    0x00000007U
-#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
-#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER1_DUTY_S  5
-/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
-#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_S  8
-/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
-#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_OUT_INVERT_S  12
-/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
-#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_IN_INVERT_S  13
-
-/** MCPWM_FH1_CFG0_REG register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0)
-/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_SW_CBC    (BIT(0))
-#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
-#define MCPWM_TZ1_SW_CBC_V  0x00000001U
-#define MCPWM_TZ1_SW_CBC_S  0
-/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F2_CBC    (BIT(1))
-#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
-#define MCPWM_TZ1_F2_CBC_V  0x00000001U
-#define MCPWM_TZ1_F2_CBC_S  1
-/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F1_CBC    (BIT(2))
-#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
-#define MCPWM_TZ1_F1_CBC_V  0x00000001U
-#define MCPWM_TZ1_F1_CBC_S  2
-/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F0_CBC    (BIT(3))
-#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
-#define MCPWM_TZ1_F0_CBC_V  0x00000001U
-#define MCPWM_TZ1_F0_CBC_S  3
-/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_SW_OST    (BIT(4))
-#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
-#define MCPWM_TZ1_SW_OST_V  0x00000001U
-#define MCPWM_TZ1_SW_OST_S  4
-/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F2_OST    (BIT(5))
-#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
-#define MCPWM_TZ1_F2_OST_V  0x00000001U
-#define MCPWM_TZ1_F2_OST_S  5
-/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F1_OST    (BIT(6))
-#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
-#define MCPWM_TZ1_F1_OST_V  0x00000001U
-#define MCPWM_TZ1_F1_OST_S  6
-/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F0_OST    (BIT(7))
-#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
-#define MCPWM_TZ1_F0_OST_V  0x00000001U
-#define MCPWM_TZ1_F0_OST_S  7
-/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_CBC_D    0x00000003U
-#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
-#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_D_S  8
-/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_CBC_U    0x00000003U
-#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
-#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_U_S  10
-/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_OST_D    0x00000003U
-#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
-#define MCPWM_TZ1_A_OST_D_V  0x00000003U
-#define MCPWM_TZ1_A_OST_D_S  12
-/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_OST_U    0x00000003U
-#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
-#define MCPWM_TZ1_A_OST_U_V  0x00000003U
-#define MCPWM_TZ1_A_OST_U_S  14
-/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_CBC_D    0x00000003U
-#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
-#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_D_S  16
-/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_CBC_U    0x00000003U
-#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
-#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_U_S  18
-/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_OST_D    0x00000003U
-#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
-#define MCPWM_TZ1_B_OST_D_V  0x00000003U
-#define MCPWM_TZ1_B_OST_D_S  20
-/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_OST_U    0x00000003U
-#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
-#define MCPWM_TZ1_B_OST_U_V  0x00000003U
-#define MCPWM_TZ1_B_OST_U_S  22
-
-/** MCPWM_FH1_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4)
-/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_TZ1_CLR_OST    (BIT(0))
-#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
-#define MCPWM_TZ1_CLR_OST_V  0x00000001U
-#define MCPWM_TZ1_CLR_OST_S  0
-/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_TZ1_CBCPULSE    0x00000003U
-#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
-#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ1_CBCPULSE_S  1
-/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
-#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ1_FORCE_CBC_S  3
-/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_TZ1_FORCE_OST    (BIT(4))
-#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
-#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ1_FORCE_OST_S  4
-
-/** MCPWM_FH1_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8)
-/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_TZ1_CBC_ON    (BIT(0))
-#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
-#define MCPWM_TZ1_CBC_ON_V  0x00000001U
-#define MCPWM_TZ1_CBC_ON_S  0
-/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_TZ1_OST_ON    (BIT(1))
-#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
-#define MCPWM_TZ1_OST_ON_V  0x00000001U
-#define MCPWM_TZ1_OST_ON_S  1
-
-/** MCPWM_GEN2_STMP_CFG_REG register
- *  Generator2 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 2 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 2 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN2_TSTMP_A_REG register
- *  Generator$n time stamp A's shadow register
- */
-#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0)
-/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp A's shadow register.
- */
-#define MCPWM_CMPR2_A    0x0000FFFFU
-#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
-#define MCPWM_CMPR2_A_V  0x0000FFFFU
-#define MCPWM_CMPR2_A_S  0
-
-/** MCPWM_GEN2_TSTMP_B_REG register
- *  Generator$n time stamp B's shadow register
- */
-#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4)
-/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp B's shadow register.
- */
-#define MCPWM_CMPR2_B    0x0000FFFFU
-#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
-#define MCPWM_CMPR2_B_V  0x0000FFFFU
-#define MCPWM_CMPR2_B_S  0
-
-/** MCPWM_GEN2_CFG0_REG register
- *  Generator$n fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8)
-/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator $n's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
-#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_S  0
-/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator $n event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN2_T0_SEL    0x00000007U
-#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
-#define MCPWM_GEN2_T0_SEL_V  0x00000007U
-#define MCPWM_GEN2_T0_SEL_S  4
-/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator $n event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN2_T1_SEL    0x00000007U
-#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
-#define MCPWM_GEN2_T1_SEL_V  0x00000007U
-#define MCPWM_GEN2_T1_SEL_S  7
-
-/** MCPWM_GEN2_FORCE_REG register
- *  Generator$n output signal force mode register.
- */
-#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc)
-/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator$n.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
-#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_A_NCIFORCE_S  10
-/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
-#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_B_NCIFORCE_S  13
-/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN2_A_REG register
- *  PWM$n output signal A actions configuration register
- */
-#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0)
-/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEZ    0x00000003U
-#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
-#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_UTEZ_S  0
-/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEP    0x00000003U
-#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
-#define MCPWM_GEN2_A_UTEP_V  0x00000003U
-#define MCPWM_GEN2_A_UTEP_S  2
-/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEA    0x00000003U
-#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
-#define MCPWM_GEN2_A_UTEA_V  0x00000003U
-#define MCPWM_GEN2_A_UTEA_S  4
-/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEB    0x00000003U
-#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
-#define MCPWM_GEN2_A_UTEB_V  0x00000003U
-#define MCPWM_GEN2_A_UTEB_S  6
-/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UT0    0x00000003U
-#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
-#define MCPWM_GEN2_A_UT0_V  0x00000003U
-#define MCPWM_GEN2_A_UT0_S  8
-/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UT1    0x00000003U
-#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
-#define MCPWM_GEN2_A_UT1_V  0x00000003U
-#define MCPWM_GEN2_A_UT1_S  10
-/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEZ    0x00000003U
-#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
-#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_DTEZ_S  12
-/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEP    0x00000003U
-#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
-#define MCPWM_GEN2_A_DTEP_V  0x00000003U
-#define MCPWM_GEN2_A_DTEP_S  14
-/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEA    0x00000003U
-#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
-#define MCPWM_GEN2_A_DTEA_V  0x00000003U
-#define MCPWM_GEN2_A_DTEA_S  16
-/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEB    0x00000003U
-#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
-#define MCPWM_GEN2_A_DTEB_V  0x00000003U
-#define MCPWM_GEN2_A_DTEB_S  18
-/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DT0    0x00000003U
-#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
-#define MCPWM_GEN2_A_DT0_V  0x00000003U
-#define MCPWM_GEN2_A_DT0_S  20
-/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DT1    0x00000003U
-#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
-#define MCPWM_GEN2_A_DT1_V  0x00000003U
-#define MCPWM_GEN2_A_DT1_S  22
-
-/** MCPWM_GEN2_B_REG register
- *  PWM$n output signal B actions configuration register
- */
-#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4)
-/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEZ    0x00000003U
-#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
-#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_UTEZ_S  0
-/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEP    0x00000003U
-#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
-#define MCPWM_GEN2_B_UTEP_V  0x00000003U
-#define MCPWM_GEN2_B_UTEP_S  2
-/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEA    0x00000003U
-#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
-#define MCPWM_GEN2_B_UTEA_V  0x00000003U
-#define MCPWM_GEN2_B_UTEA_S  4
-/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEB    0x00000003U
-#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
-#define MCPWM_GEN2_B_UTEB_V  0x00000003U
-#define MCPWM_GEN2_B_UTEB_S  6
-/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UT0    0x00000003U
-#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
-#define MCPWM_GEN2_B_UT0_V  0x00000003U
-#define MCPWM_GEN2_B_UT0_S  8
-/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UT1    0x00000003U
-#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
-#define MCPWM_GEN2_B_UT1_V  0x00000003U
-#define MCPWM_GEN2_B_UT1_S  10
-/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEZ    0x00000003U
-#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
-#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_DTEZ_S  12
-/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEP    0x00000003U
-#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
-#define MCPWM_GEN2_B_DTEP_V  0x00000003U
-#define MCPWM_GEN2_B_DTEP_S  14
-/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEA    0x00000003U
-#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
-#define MCPWM_GEN2_B_DTEA_V  0x00000003U
-#define MCPWM_GEN2_B_DTEA_S  16
-/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEB    0x00000003U
-#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
-#define MCPWM_GEN2_B_DTEB_V  0x00000003U
-#define MCPWM_GEN2_B_DTEB_S  18
-/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DT0    0x00000003U
-#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
-#define MCPWM_GEN2_B_DT0_V  0x00000003U
-#define MCPWM_GEN2_B_DT0_S  20
-/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DT1    0x00000003U
-#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
-#define MCPWM_GEN2_B_DT1_V  0x00000003U
-#define MCPWM_GEN2_B_DT1_S  22
-
-/** MCPWM_DT2_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
-/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
-#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_S  0
-/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
-#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_S  4
-/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB2_DEB_MODE    (BIT(8))
-#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
-#define MCPWM_DB2_DEB_MODE_V  0x00000001U
-#define MCPWM_DB2_DEB_MODE_S  8
-/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
-#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_A_OUTSWAP_S  9
-/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
-#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_B_OUTSWAP_S  10
-/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DB2_RED_INSEL    (BIT(11))
-#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
-#define MCPWM_DB2_RED_INSEL_V  0x00000001U
-#define MCPWM_DB2_RED_INSEL_S  11
-/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DB2_FED_INSEL    (BIT(12))
-#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
-#define MCPWM_DB2_FED_INSEL_V  0x00000001U
-#define MCPWM_DB2_FED_INSEL_S  12
-/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
-#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_RED_OUTINVERT_S  13
-/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
-#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_FED_OUTINVERT_S  14
-/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
-#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_A_OUTBYPASS_S  15
-/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
-#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_B_OUTBYPASS_S  16
-/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DB2_CLK_SEL    (BIT(17))
-#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
-#define MCPWM_DB2_CLK_SEL_V  0x00000001U
-#define MCPWM_DB2_CLK_SEL_S  17
-
-/** MCPWM_DT2_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
-/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DB2_FED    0x0000FFFFU
-#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
-#define MCPWM_DB2_FED_V  0x0000FFFFU
-#define MCPWM_DB2_FED_S  0
-
-/** MCPWM_DT2_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
-/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DB2_RED    0x0000FFFFU
-#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
-#define MCPWM_DB2_RED_V  0x0000FFFFU
-#define MCPWM_DB2_RED_S  0
-
-/** MCPWM_CARRIER2_CFG_REG register
- *  Carrier$n configuration register
- */
-#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4)
-/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CHOPPER2_EN    (BIT(0))
-#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
-#define MCPWM_CHOPPER2_EN_V  0x00000001U
-#define MCPWM_CHOPPER2_EN_S  0
-/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
-#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_S  1
-/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
- */
-#define MCPWM_CHOPPER2_DUTY    0x00000007U
-#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
-#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER2_DUTY_S  5
-/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
-#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_S  8
-/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
-#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_OUT_INVERT_S  12
-/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
-#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_IN_INVERT_S  13
-
-/** MCPWM_FH2_CFG0_REG register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8)
-/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_SW_CBC    (BIT(0))
-#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
-#define MCPWM_TZ2_SW_CBC_V  0x00000001U
-#define MCPWM_TZ2_SW_CBC_S  0
-/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F2_CBC    (BIT(1))
-#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
-#define MCPWM_TZ2_F2_CBC_V  0x00000001U
-#define MCPWM_TZ2_F2_CBC_S  1
-/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F1_CBC    (BIT(2))
-#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
-#define MCPWM_TZ2_F1_CBC_V  0x00000001U
-#define MCPWM_TZ2_F1_CBC_S  2
-/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F0_CBC    (BIT(3))
-#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
-#define MCPWM_TZ2_F0_CBC_V  0x00000001U
-#define MCPWM_TZ2_F0_CBC_S  3
-/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_SW_OST    (BIT(4))
-#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
-#define MCPWM_TZ2_SW_OST_V  0x00000001U
-#define MCPWM_TZ2_SW_OST_S  4
-/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F2_OST    (BIT(5))
-#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
-#define MCPWM_TZ2_F2_OST_V  0x00000001U
-#define MCPWM_TZ2_F2_OST_S  5
-/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F1_OST    (BIT(6))
-#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
-#define MCPWM_TZ2_F1_OST_V  0x00000001U
-#define MCPWM_TZ2_F1_OST_S  6
-/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F0_OST    (BIT(7))
-#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
-#define MCPWM_TZ2_F0_OST_V  0x00000001U
-#define MCPWM_TZ2_F0_OST_S  7
-/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_CBC_D    0x00000003U
-#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
-#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_D_S  8
-/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_CBC_U    0x00000003U
-#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
-#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_U_S  10
-/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_OST_D    0x00000003U
-#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
-#define MCPWM_TZ2_A_OST_D_V  0x00000003U
-#define MCPWM_TZ2_A_OST_D_S  12
-/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_OST_U    0x00000003U
-#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
-#define MCPWM_TZ2_A_OST_U_V  0x00000003U
-#define MCPWM_TZ2_A_OST_U_S  14
-/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_CBC_D    0x00000003U
-#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
-#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_D_S  16
-/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_CBC_U    0x00000003U
-#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
-#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_U_S  18
-/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_OST_D    0x00000003U
-#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
-#define MCPWM_TZ2_B_OST_D_V  0x00000003U
-#define MCPWM_TZ2_B_OST_D_S  20
-/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_OST_U    0x00000003U
-#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
-#define MCPWM_TZ2_B_OST_U_V  0x00000003U
-#define MCPWM_TZ2_B_OST_U_S  22
-
-/** MCPWM_FH2_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc)
-/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_TZ2_CLR_OST    (BIT(0))
-#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
-#define MCPWM_TZ2_CLR_OST_V  0x00000001U
-#define MCPWM_TZ2_CLR_OST_S  0
-/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_TZ2_CBCPULSE    0x00000003U
-#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
-#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ2_CBCPULSE_S  1
-/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
-#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ2_FORCE_CBC_S  3
-/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_TZ2_FORCE_OST    (BIT(4))
-#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
-#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ2_FORCE_OST_S  4
-
-/** MCPWM_FH2_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0)
-/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_TZ2_CBC_ON    (BIT(0))
-#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
-#define MCPWM_TZ2_CBC_ON_V  0x00000001U
-#define MCPWM_TZ2_CBC_ON_S  0
-/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_TZ2_OST_ON    (BIT(1))
-#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
-#define MCPWM_TZ2_OST_ON_V  0x00000001U
-#define MCPWM_TZ2_OST_ON_S  1
-
-/** MCPWM_FAULT_DETECT_REG register
- *  Fault detection configuration and status register
- */
-#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4)
-/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F0_EN    (BIT(0))
-#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
-#define MCPWM_F0_EN_V  0x00000001U
-#define MCPWM_F0_EN_S  0
-/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F1_EN    (BIT(1))
-#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
-#define MCPWM_F1_EN_V  0x00000001U
-#define MCPWM_F1_EN_S  1
-/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F2_EN    (BIT(2))
-#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
-#define MCPWM_F2_EN_V  0x00000001U
-#define MCPWM_F2_EN_S  2
-/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
- *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F0_POLE    (BIT(3))
-#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
-#define MCPWM_F0_POLE_V  0x00000001U
-#define MCPWM_F0_POLE_S  3
-/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
- *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F1_POLE    (BIT(4))
-#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
-#define MCPWM_F1_POLE_V  0x00000001U
-#define MCPWM_F1_POLE_S  4
-/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
- *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F2_POLE    (BIT(5))
-#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
-#define MCPWM_F2_POLE_V  0x00000001U
-#define MCPWM_F2_POLE_S  5
-/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
- *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F0    (BIT(6))
-#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
-#define MCPWM_EVENT_F0_V  0x00000001U
-#define MCPWM_EVENT_F0_S  6
-/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
- *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F1    (BIT(7))
-#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
-#define MCPWM_EVENT_F1_V  0x00000001U
-#define MCPWM_EVENT_F1_S  7
-/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
- *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F2    (BIT(8))
-#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
-#define MCPWM_EVENT_F2_V  0x00000001U
-#define MCPWM_EVENT_F2_S  8
-
-/** MCPWM_CAP_TIMER_CFG_REG register
- *  Capture timer configuration register
- */
-#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8)
-/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP_TIMER_EN    (BIT(0))
-#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
-#define MCPWM_CAP_TIMER_EN_V  0x00000001U
-#define MCPWM_CAP_TIMER_EN_S  0
-/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP_SYNCI_EN    (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
-#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
-#define MCPWM_CAP_SYNCI_EN_S  1
-/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
- *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
- *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
- *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
- */
-#define MCPWM_CAP_SYNCI_SEL    0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
-#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_S  2
-/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
- *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
- *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
- *  value in phase register
- */
-#define MCPWM_CAP_SYNC_SW    (BIT(5))
-#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
-#define MCPWM_CAP_SYNC_SW_V  0x00000001U
-#define MCPWM_CAP_SYNC_SW_S  5
-
-/** MCPWM_CAP_TIMER_PHASE_REG register
- *  Capture timer sync phase register
- */
-#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec)
-/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
- *  Configures phase value for capture timer sync operation.
- */
-#define MCPWM_CAP_PHASE    0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
-#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_S  0
-
-/** MCPWM_CAP_CH0_CFG_REG register
- *  Capture channel 0 configuration register
- */
-#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 0 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP0. Prescale value =
- *  PWM_CAP0_PRESCALE + 1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 0
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH1_CFG_REG register
- *  Capture channel 1 configuration register
- */
-#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 1 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP1. Prescale value =
- *  PWM_CAP1_PRESCALE + 1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 1
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH2_CFG_REG register
- *  Capture channel 2 configuration register
- */
-#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 2 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP2. Prescale value =
- *  PWM_CAP2_PRESCALE + 1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 2
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH0_REG register
- *  CAP0 capture value register
- */
-#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP0
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH1_REG register
- *  CAP1 capture value register
- */
-#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP1
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH2_REG register
- *  CAP2 capture value register
- */
-#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP2
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_STATUS_REG register
- *  Last capture trigger edge information register
- */
-#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108)
-/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
- *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP0_EDGE    (BIT(0))
-#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
-#define MCPWM_CAP0_EDGE_V  0x00000001U
-#define MCPWM_CAP0_EDGE_S  0
-/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
- *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP1_EDGE    (BIT(1))
-#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
-#define MCPWM_CAP1_EDGE_V  0x00000001U
-#define MCPWM_CAP1_EDGE_S  1
-/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
- *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP2_EDGE    (BIT(2))
-#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
-#define MCPWM_CAP2_EDGE_V  0x00000001U
-#define MCPWM_CAP2_EDGE_S  2
-
-/** MCPWM_UPDATE_CFG_REG register
- *  Generator Update configuration register
- */
-#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c)
-/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
- *  Configures whether or not to enable global update for all active registers in MCPWM
- *  module.\\0: Disable\\1: Enable
- */
-#define MCPWM_GLOBAL_UP_EN    (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
-#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
-#define MCPWM_GLOBAL_UP_EN_S  0
-/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of global forced update for all active registers in MCPWM
- *  module. A toggle (software invert its value) will trigger a global forced update.
- *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
- */
-#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
-#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
-#define MCPWM_GLOBAL_FORCE_UP_S  1
-/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP0_UP_EN    (BIT(2))
-#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
-#define MCPWM_OP0_UP_EN_V  0x00000001U
-#define MCPWM_OP0_UP_EN_S  2
-/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator0. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
- */
-#define MCPWM_OP0_FORCE_UP    (BIT(3))
-#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
-#define MCPWM_OP0_FORCE_UP_V  0x00000001U
-#define MCPWM_OP0_FORCE_UP_S  3
-/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP1_UP_EN    (BIT(4))
-#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
-#define MCPWM_OP1_UP_EN_V  0x00000001U
-#define MCPWM_OP1_UP_EN_S  4
-/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator1. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
- */
-#define MCPWM_OP1_FORCE_UP    (BIT(5))
-#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
-#define MCPWM_OP1_FORCE_UP_V  0x00000001U
-#define MCPWM_OP1_FORCE_UP_S  5
-/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP2_UP_EN    (BIT(6))
-#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
-#define MCPWM_OP2_UP_EN_V  0x00000001U
-#define MCPWM_OP2_UP_EN_S  6
-/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator2. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
- */
-#define MCPWM_OP2_FORCE_UP    (BIT(7))
-#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
-#define MCPWM_OP2_FORCE_UP_V  0x00000001U
-#define MCPWM_OP2_FORCE_UP_S  7
-
-/** MCPWM_INT_ENA_REG register
- *  Interrupt enable register
- */
-#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110)
-/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
-#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ENA_S  0
-/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
-#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ENA_S  1
-/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
-#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ENA_S  2
-/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
-#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
-/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
-#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
-/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
-#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
-/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
-#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ENA_S  6
-/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
-#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ENA_S  7
-/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
-#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ENA_S  8
-/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ENA    (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
-#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_INT_ENA_S  9
-/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ENA    (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
-#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_INT_ENA_S  10
-/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ENA    (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
-#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_INT_ENA_S  11
-/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
-#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ENA_S  12
-/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
-#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ENA_S  13
-/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
-#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ENA_S  14
-/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
- */
-#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
-#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ENA_S  15
-/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
- */
-#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
-#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ENA_S  16
-/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
- */
-#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
-#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ENA_S  17
-/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
- */
-#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
-#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ENA_S  18
-/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
- */
-#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
-#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ENA_S  19
-/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
- */
-#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
-#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ENA_S  20
-/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
-#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ENA_S  21
-/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
-#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ENA_S  22
-/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
-#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ENA_S  23
-/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
-#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ENA_S  24
-/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
-#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ENA_S  25
-/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
-#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ENA_S  26
-/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
- */
-#define MCPWM_CAP0_INT_ENA    (BIT(27))
-#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
-#define MCPWM_CAP0_INT_ENA_V  0x00000001U
-#define MCPWM_CAP0_INT_ENA_S  27
-/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
- */
-#define MCPWM_CAP1_INT_ENA    (BIT(28))
-#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
-#define MCPWM_CAP1_INT_ENA_V  0x00000001U
-#define MCPWM_CAP1_INT_ENA_S  28
-/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
- */
-#define MCPWM_CAP2_INT_ENA    (BIT(29))
-#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
-#define MCPWM_CAP2_INT_ENA_V  0x00000001U
-#define MCPWM_CAP2_INT_ENA_S  29
-
-/** MCPWM_INT_RAW_REG register
- *  Interrupt raw status register
- */
-#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114)
-/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
-#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_RAW_S  0
-/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
-#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_RAW_S  1
-/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
-#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_RAW_S  2
-/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
-#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
-/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
-#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
-/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
-#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
-/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
-#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_RAW_S  6
-/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
-#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_RAW_S  7
-/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
-#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_RAW_S  8
-/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
- *  starts.
- */
-#define MCPWM_FAULT0_INT_RAW    (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
-#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_INT_RAW_S  9
-/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
- *  starts.
- */
-#define MCPWM_FAULT1_INT_RAW    (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
-#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_INT_RAW_S  10
-/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
- *  starts.
- */
-#define MCPWM_FAULT2_INT_RAW    (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
-#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_INT_RAW_S  11
-/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
- *  clears.
- */
-#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
-#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_RAW_S  12
-/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
- *  clears.
- */
-#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
-#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_RAW_S  13
-/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
- *  clears.
- */
-#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
-#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_RAW_S  14
-/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
-#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_RAW_S  15
-/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
-#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_RAW_S  16
-/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
-#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_RAW_S  17
-/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
-#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_RAW_S  18
-/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
-#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_RAW_S  19
-/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
-#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_RAW_S  20
-/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
-#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_RAW_S  21
-/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
-#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_RAW_S  22
-/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
-#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_RAW_S  23
-/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
-#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
-#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_RAW_S  24
-/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
-#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
-#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_RAW_S  25
-/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
-#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
-#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_RAW_S  26
-/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP0.
- */
-#define MCPWM_CAP0_INT_RAW    (BIT(27))
-#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
-#define MCPWM_CAP0_INT_RAW_V  0x00000001U
-#define MCPWM_CAP0_INT_RAW_S  27
-/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP1.
- */
-#define MCPWM_CAP1_INT_RAW    (BIT(28))
-#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
-#define MCPWM_CAP1_INT_RAW_V  0x00000001U
-#define MCPWM_CAP1_INT_RAW_S  28
-/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP2.
- */
-#define MCPWM_CAP2_INT_RAW    (BIT(29))
-#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
-#define MCPWM_CAP2_INT_RAW_V  0x00000001U
-#define MCPWM_CAP2_INT_RAW_S  29
-
-/** MCPWM_INT_ST_REG register
- *  Interrupt masked status register
- */
-#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118)
-/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
-#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ST_S  0
-/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
-#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ST_S  1
-/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
-#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ST_S  2
-/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
-#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ST_S  3
-/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
-#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ST_S  4
-/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
-#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ST_S  5
-/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
-#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ST_S  6
-/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
-#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ST_S  7
-/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
-#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ST_S  8
-/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ST    (BIT(9))
-#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
-#define MCPWM_FAULT0_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_INT_ST_S  9
-/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ST    (BIT(10))
-#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
-#define MCPWM_FAULT1_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_INT_ST_S  10
-/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ST    (BIT(11))
-#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
-#define MCPWM_FAULT2_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_INT_ST_S  11
-/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
-#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ST_S  12
-/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
-#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ST_S  13
-/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
-#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ST_S  14
-/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
-#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ST_S  15
-/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
-#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ST_S  16
-/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
-#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ST_S  17
-/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
-#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ST_S  18
-/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
-#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ST_S  19
-/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
-#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ST_S  20
-/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
-#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ST_S  21
-/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
-#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ST_S  22
-/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
-#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ST_S  23
-/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
-#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ST_S  24
-/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
-#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ST_S  25
-/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
-#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ST_S  26
-/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP0.
- */
-#define MCPWM_CAP0_INT_ST    (BIT(27))
-#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
-#define MCPWM_CAP0_INT_ST_V  0x00000001U
-#define MCPWM_CAP0_INT_ST_S  27
-/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP1.
- */
-#define MCPWM_CAP1_INT_ST    (BIT(28))
-#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
-#define MCPWM_CAP1_INT_ST_V  0x00000001U
-#define MCPWM_CAP1_INT_ST_S  28
-/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP2.
- */
-#define MCPWM_CAP2_INT_ST    (BIT(29))
-#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
-#define MCPWM_CAP2_INT_ST_V  0x00000001U
-#define MCPWM_CAP2_INT_ST_S  29
-
-/** MCPWM_INT_CLR_REG register
- *  Interrupt clear register
- */
-#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c)
-/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
-#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_CLR_S  0
-/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
-#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_CLR_S  1
-/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
-#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_CLR_S  2
-/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
-#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
-/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
-#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
-/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
-#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
-/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
-#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_CLR_S  6
-/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
-#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_CLR_S  7
-/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
-#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_CLR_S  8
-/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_CLR    (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
-#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_INT_CLR_S  9
-/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_CLR    (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
-#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_INT_CLR_S  10
-/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_CLR    (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
-#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_INT_CLR_S  11
-/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
-#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_CLR_S  12
-/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
-#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_CLR_S  13
-/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
-#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_CLR_S  14
-/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
-#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_CLR_S  15
-/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
-#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_CLR_S  16
-/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
-#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_CLR_S  17
-/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
-#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_CLR_S  18
-/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
-#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_CLR_S  19
-/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
-#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_CLR_S  20
-/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
-#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_CLR_S  21
-/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
-#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_CLR_S  22
-/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
-#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_CLR_S  23
-/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
-#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
-#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_CLR_S  24
-/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
-#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
-#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_CLR_S  25
-/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
-#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
-#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_CLR_S  26
-/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
- */
-#define MCPWM_CAP0_INT_CLR    (BIT(27))
-#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
-#define MCPWM_CAP0_INT_CLR_V  0x00000001U
-#define MCPWM_CAP0_INT_CLR_S  27
-/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
- */
-#define MCPWM_CAP1_INT_CLR    (BIT(28))
-#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
-#define MCPWM_CAP1_INT_CLR_V  0x00000001U
-#define MCPWM_CAP1_INT_CLR_S  28
-/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
- */
-#define MCPWM_CAP2_INT_CLR    (BIT(29))
-#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
-#define MCPWM_CAP2_INT_CLR_V  0x00000001U
-#define MCPWM_CAP2_INT_CLR_S  29
-
-/** MCPWM_EVT_EN_REG register
- *  Event enable register
- */
-#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120)
-/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
-#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
-#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_STOP_EN_S  0
-/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
-#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
-#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_STOP_EN_S  1
-/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
-#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
-#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_STOP_EN_S  2
-/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable timer0 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
-#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
-#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
-/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable timer1 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
-#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
-#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
-/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable timer2 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
-#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
-#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
-/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable timer0 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
-#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
-#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEP_EN_S  6
-/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable timer1 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
-#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
-#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEP_EN_S  7
-/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable timer2 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
-#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
-#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEP_EN_S  8
-/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
-#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
-#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEA_EN_S  9
-/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
-#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
-#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEA_EN_S  10
-/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
-#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
-#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEA_EN_S  11
-/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
-#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
-#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEB_EN_S  12
-/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
-#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
-#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEB_EN_S  13
-/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
-#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
-#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEB_EN_S  14
-/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F0_EN    (BIT(15))
-#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
-#define MCPWM_EVT_F0_EN_V  0x00000001U
-#define MCPWM_EVT_F0_EN_S  15
-/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F1_EN    (BIT(16))
-#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
-#define MCPWM_EVT_F1_EN_V  0x00000001U
-#define MCPWM_EVT_F1_EN_S  16
-/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F2_EN    (BIT(17))
-#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
-#define MCPWM_EVT_F2_EN_V  0x00000001U
-#define MCPWM_EVT_F2_EN_S  17
-/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
-#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
-#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F0_CLR_EN_S  18
-/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
-#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
-#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F1_CLR_EN_S  19
-/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
-#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
-#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F2_CLR_EN_S  20
-/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
-#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
-#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_CBC_EN_S  21
-/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
-#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
-#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_CBC_EN_S  22
-/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
-#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
-#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_CBC_EN_S  23
-/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
- *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
-#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
-#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_OST_EN_S  24
-/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
- *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
-#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
-#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_OST_EN_S  25
-/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
- *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
-#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
-#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_OST_EN_S  26
-/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
- *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP0_EN    (BIT(27))
-#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
-#define MCPWM_EVT_CAP0_EN_V  0x00000001U
-#define MCPWM_EVT_CAP0_EN_S  27
-/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP1_EN    (BIT(28))
-#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
-#define MCPWM_EVT_CAP1_EN_V  0x00000001U
-#define MCPWM_EVT_CAP1_EN_S  28
-/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP2_EN    (BIT(29))
-#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
-#define MCPWM_EVT_CAP2_EN_V  0x00000001U
-#define MCPWM_EVT_CAP2_EN_S  29
-
-/** MCPWM_TASK_EN_REG register
- *  Task enable register
- */
-#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124)
-/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
-#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
-#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
-/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
-#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
-#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
-/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
-#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
-#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
-/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
-#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
-#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
-/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
-#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
-#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
-/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
-#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
-#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
-/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable all PWM generate stop task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
-#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
-#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
-#define MCPWM_TASK_GEN_STOP_EN_S  6
-/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
-#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
-#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
-/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
-#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
-#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
-/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
-#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
-#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
-/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable timer0 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
-/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable timer1 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
-/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable timer2 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
-/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
-#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
-#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ0_OST_EN_S  13
-/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
- *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
-#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
-#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ1_OST_EN_S  14
-/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
-#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
-#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ2_OST_EN_S  15
-/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
-#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
-#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR0_OST_EN_S  16
-/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
-#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
-#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR1_OST_EN_S  17
-/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
-#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
-#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR2_OST_EN_S  18
-/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP0_EN    (BIT(19))
-#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
-#define MCPWM_TASK_CAP0_EN_V  0x00000001U
-#define MCPWM_TASK_CAP0_EN_S  19
-/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP1_EN    (BIT(20))
-#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
-#define MCPWM_TASK_CAP1_EN_V  0x00000001U
-#define MCPWM_TASK_CAP1_EN_S  20
-/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP2_EN    (BIT(21))
-#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
-#define MCPWM_TASK_CAP2_EN_V  0x00000001U
-#define MCPWM_TASK_CAP2_EN_S  21
-
-/** MCPWM_EVT_EN2_REG register
- *  Event enable register2
- */
-#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x128)
-/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEE1_EN    (BIT(0))
-#define MCPWM_EVT_OP0_TEE1_EN_M  (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S)
-#define MCPWM_EVT_OP0_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEE1_EN_S  0
-/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEE1_EN    (BIT(1))
-#define MCPWM_EVT_OP1_TEE1_EN_M  (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S)
-#define MCPWM_EVT_OP1_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEE1_EN_S  1
-/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEE1_EN    (BIT(2))
-#define MCPWM_EVT_OP2_TEE1_EN_M  (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S)
-#define MCPWM_EVT_OP2_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEE1_EN_S  2
-/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEE2_EN    (BIT(3))
-#define MCPWM_EVT_OP0_TEE2_EN_M  (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S)
-#define MCPWM_EVT_OP0_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEE2_EN_S  3
-/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEE2_EN    (BIT(4))
-#define MCPWM_EVT_OP1_TEE2_EN_M  (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S)
-#define MCPWM_EVT_OP1_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEE2_EN_S  4
-/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEE2_EN    (BIT(5))
-#define MCPWM_EVT_OP2_TEE2_EN_M  (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S)
-#define MCPWM_EVT_OP2_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEE2_EN_S  5
-
-/** MCPWM_OP0_TSTMP_E1_REG register
- *  Generator0 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x12c)
-/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator0 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
-#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_S  0
-
-/** MCPWM_OP0_TSTMP_E2_REG register
- *  Generator$n timer stamp E2 value register
- */
-#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x130)
-/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator$n timer stamp E2 value register
- */
-#define MCPWM_OP0_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E2_M  (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S)
-#define MCPWM_OP0_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E2_S  0
-
-/** MCPWM_OP1_TSTMP_E1_REG register
- *  Generator1 timer stamp E1 value register
- */
-#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x134)
-/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator1 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
-#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_S  0
-
-/** MCPWM_OP1_TSTMP_E2_REG register
- *  Generator$n timer stamp E2 value register
- */
-#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x138)
-/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator$n timer stamp E2 value register
- */
-#define MCPWM_OP1_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E2_M  (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S)
-#define MCPWM_OP1_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E2_S  0
-
-/** MCPWM_OP2_TSTMP_E1_REG register
- *  Generator2 timer stamp E1 value register
- */
-#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x13c)
-/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator2 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
-#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_S  0
-
-/** MCPWM_OP2_TSTMP_E2_REG register
- *  Generator$n timer stamp E2 value register
- */
-#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x140)
-/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator$n timer stamp E2 value register
- */
-#define MCPWM_OP2_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E2_M  (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S)
-#define MCPWM_OP2_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E2_S  0
-
-/** MCPWM_CLK_REG register
- *  Global configuration register
- */
-#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x144)
-/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
- *  when application writes registers\\1: Force open the clock gate for register
- */
-#define MCPWM_CLK_EN    (BIT(0))
-#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
-#define MCPWM_CLK_EN_V  0x00000001U
-#define MCPWM_CLK_EN_S  0
-
-/** MCPWM_VERSION_REG register
- *  Version register.
- */
-#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x148)
-/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968;
- *  Configures the version.
- */
-#define MCPWM_DATE    0x0FFFFFFFU
-#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
-#define MCPWM_DATE_V  0x0FFFFFFFU
-#define MCPWM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/pwm_struct.h b/components/soc/esp32p4/include/soc/pwm_struct.h
deleted file mode 100644
index f48bd4cf69..0000000000
--- a/components/soc/esp32p4/include/soc/pwm_struct.h
+++ /dev/null
@@ -1,2166 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: clk_cfg */
-/** Type of clk_cfg register
- *  PWM clock prescaler register.
- */
-typedef union {
-    struct {
-        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
-         *  (PWM_CLK_PRESCALE + 1).
-         */
-        uint32_t clk_prescale:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_clk_cfg_reg_t;
-
-
-/** Group: timer */
-/** Type of timern_cfg0 register
- *  PWM timern period and update method configuration register.
- */
-typedef union {
-    struct {
-        /** timer0_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the prescaler value of timern, so that the period of PT0_clk = Period of
-         *  PWM_clk * (PWM_TIMERn_PRESCALE + 1)
-         */
-        uint32_t timer0_prescale:8;
-        /** timer0_period : R/W; bitpos: [23:8]; default: 255;
-         *  Configures the period shadow of PWM timern
-         */
-        uint32_t timer0_period:16;
-        /** timer0_period_upmethod : R/W; bitpos: [25:24]; default: 0;
-         *  Configures the update method for active register of PWM timern period.\\0:
-         *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
-         *  zero event
-         */
-        uint32_t timer0_period_upmethod:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg0_reg_t;
-
-/** Type of timer0_cfg1 register
- *  PWM timer$n working mode and start/stop control register.
- */
-typedef union {
-    struct {
-        /** timer0_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
-         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
-         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
-         *  stops at the next TEP.\\TEP here and below means the event that happens when the
-         *  timer equals to period
-         */
-        uint32_t timer0_start:3;
-        /** timer0_mod : R/W; bitpos: [4:3]; default: 0;
-         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
-         *  Decrease mode\\3: Up-down mode
-         */
-        uint32_t timer0_mod:2;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg1_reg_t;
-
-/** Type of timer0_sync register
- *  PWM timer$n sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timer0_synci_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timer$n reloading with phase on sync input
-         *  event is enabled.\\0: Disable\\1: Enable
-         */
-        uint32_t timer0_synci_en:1;
-        /** timer0_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of software sync. Toggling this bit will trigger a
-         *  software sync.
-         */
-        uint32_t timer0_sync_sw:1;
-        /** timer0_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
-         *  Invalid, sync_out selects noting
-         */
-        uint32_t timer0_synco_sel:2;
-        /** timer0_phase : R/W; bitpos: [19:4]; default: 0;
-         *  Configures the phase for timer$n reload on sync event.
-         */
-        uint32_t timer0_phase:16;
-        /** timer0_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
-         *  Increase\\1: Decrease
-         */
-        uint32_t timer0_phase_direction:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} mcpwm_timer_sync_reg_t;
-
-/** Type of timer0_status register
- *  PWM timer$n status register.
- */
-typedef union {
-    struct {
-        /** timer0_value : RO; bitpos: [15:0]; default: 0;
-         *  Represents current PWM timer$n counter value.
-         */
-        uint32_t timer0_value:16;
-        /** timer0_direction : RO; bitpos: [16]; default: 0;
-         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
-         */
-        uint32_t timer0_direction:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} mcpwm_timer_status_reg_t;
-
-/** Type of timer1_cfg1 register
- *  PWM timer$n working mode and start/stop control register.
- */
-typedef union {
-    struct {
-        /** timer1_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
-         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
-         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
-         *  stops at the next TEP.\\TEP here and below means the event that happens when the
-         *  timer equals to period
-         */
-        uint32_t timer1_start:3;
-        /** timer1_mod : R/W; bitpos: [4:3]; default: 0;
-         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
-         *  Decrease mode\\3: Up-down mode
-         */
-        uint32_t timer1_mod:2;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_timer1_cfg1_reg_t;
-
-/** Type of timer1_sync register
- *  PWM timer$n sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timer1_synci_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timer$n reloading with phase on sync input
-         *  event is enabled.\\0: Disable\\1: Enable
-         */
-        uint32_t timer1_synci_en:1;
-        /** timer1_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of software sync. Toggling this bit will trigger a
-         *  software sync.
-         */
-        uint32_t timer1_sync_sw:1;
-        /** timer1_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
-         *  Invalid, sync_out selects noting
-         */
-        uint32_t timer1_synco_sel:2;
-        /** timer1_phase : R/W; bitpos: [19:4]; default: 0;
-         *  Configures the phase for timer$n reload on sync event.
-         */
-        uint32_t timer1_phase:16;
-        /** timer1_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
-         *  Increase\\1: Decrease
-         */
-        uint32_t timer1_phase_direction:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} mcpwm_timer1_sync_reg_t;
-
-/** Type of timer1_status register
- *  PWM timer$n status register.
- */
-typedef union {
-    struct {
-        /** timer1_value : RO; bitpos: [15:0]; default: 0;
-         *  Represents current PWM timer$n counter value.
-         */
-        uint32_t timer1_value:16;
-        /** timer1_direction : RO; bitpos: [16]; default: 0;
-         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
-         */
-        uint32_t timer1_direction:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} mcpwm_timer1_status_reg_t;
-
-/** Type of timer2_cfg1 register
- *  PWM timer$n working mode and start/stop control register.
- */
-typedef union {
-    struct {
-        /** timer2_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
-         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
-         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
-         *  stops at the next TEP.\\TEP here and below means the event that happens when the
-         *  timer equals to period
-         */
-        uint32_t timer2_start:3;
-        /** timer2_mod : R/W; bitpos: [4:3]; default: 0;
-         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
-         *  Decrease mode\\3: Up-down mode
-         */
-        uint32_t timer2_mod:2;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_timer2_cfg1_reg_t;
-
-/** Type of timer2_sync register
- *  PWM timer$n sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timer2_synci_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timer$n reloading with phase on sync input
-         *  event is enabled.\\0: Disable\\1: Enable
-         */
-        uint32_t timer2_synci_en:1;
-        /** timer2_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of software sync. Toggling this bit will trigger a
-         *  software sync.
-         */
-        uint32_t timer2_sync_sw:1;
-        /** timer2_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
-         *  Invalid, sync_out selects noting
-         */
-        uint32_t timer2_synco_sel:2;
-        /** timer2_phase : R/W; bitpos: [19:4]; default: 0;
-         *  Configures the phase for timer$n reload on sync event.
-         */
-        uint32_t timer2_phase:16;
-        /** timer2_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
-         *  Increase\\1: Decrease
-         */
-        uint32_t timer2_phase_direction:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} mcpwm_timer2_sync_reg_t;
-
-/** Type of timer2_status register
- *  PWM timer$n status register.
- */
-typedef union {
-    struct {
-        /** timer2_value : RO; bitpos: [15:0]; default: 0;
-         *  Represents current PWM timer$n counter value.
-         */
-        uint32_t timer2_value:16;
-        /** timer2_direction : RO; bitpos: [16]; default: 0;
-         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
-         */
-        uint32_t timer2_direction:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} mcpwm_timer2_status_reg_t;
-
-
-/** Group: timer_synci_cfg */
-/** Type of timer_synci_cfg register
- *  Synchronization input selection register for PWM timers.
- */
-typedef union {
-    struct {
-        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
-         *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer0_syncisel:3;
-        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
-         *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer1_syncisel:3;
-        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
-         *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer2_syncisel:3;
-        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci0_invert:1;
-        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci1_invert:1;
-        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci2_invert:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} mcpwm_timer_synci_cfg_reg_t;
-
-
-/** Group: operator_timersel */
-/** Type of operator_timersel register
- *  PWM operator's timer select register
- */
-typedef union {
-    struct {
-        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator0_timersel:2;
-        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator1_timersel:2;
-        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator2_timersel:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_operator_timersel_reg_t;
-
-
-/** Group: operators */
-/** Type of genn_stmp_cfg register
- *  Generatorn time stamp registers A and B transfer status and update method register
- */
-typedef union {
-    struct {
-        /** cmpr0_a_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the update method for PWM generator n time stamp A's active
-         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
-         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t cmpr0_a_upmethod:4;
-        /** cmpr0_b_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Configures the update method for PWM generator n time stamp B's active
-         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
-         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t cmpr0_b_upmethod:4;
-        /** cmpr0_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
-         *  Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0:
-         *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
-         *  reg is filled and waiting to be transferred to A's active reg
-         */
-        uint32_t cmpr0_a_shdw_full:1;
-        /** cmpr0_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
-         *  Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0:
-         *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
-         *  reg is filled and waiting to be transferred to B's active reg
-         */
-        uint32_t cmpr0_b_shdw_full:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_stmp_cfg_reg_t;
-
-/** Type of gen0_tstmp_a register
- *  Generator$n time stamp A's shadow register
- */
-typedef union {
-    struct {
-        /** cmpr0_a : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the value of PWM generator $n time stamp A's shadow register.
-         */
-        uint32_t cmpr0_a:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_tstmp_a_reg_t;
-
-/** Type of gen0_tstmp_b register
- *  Generator$n time stamp B's shadow register
- */
-typedef union {
-    struct {
-        /** cmpr0_b : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the value of PWM generator $n time stamp B's shadow register.
-         */
-        uint32_t cmpr0_b:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_tstmp_b_reg_t;
-
-/** Type of gen0_cfg0 register
- *  Generator$n fault event T0 and T1 configuration register
- */
-typedef union {
-    struct {
-        /** gen0_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures update method for PWM generator $n's active register.\\0:
-         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t gen0_cfg_upmethod:4;
-        /** gen0_t0_sel : R/W; bitpos: [6:4]; default: 0;
-         *  Configures source selection for PWM generator $n event_t0, take effect
-         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
-         *  Invalid, Select nothing
-         */
-        uint32_t gen0_t0_sel:3;
-        /** gen0_t1_sel : R/W; bitpos: [9:7]; default: 0;
-         *  Configures source selection for PWM generator $n event_t1, take effect
-         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
-         *  Invalid, Select nothing
-         */
-        uint32_t gen0_t1_sel:3;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_cfg0_reg_t;
-
-/** Type of gen0_force register
- *  Generator$n output signal force mode register.
- */
-typedef union {
-    struct {
-        /** gen0_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
-         *  Configures update method for continuous software force of PWM generator$n.\\0:
-         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
-         *  update. TEA/B here and below means an event generated when the timer's value equals
-         *  to that of register A/B.
-         */
-        uint32_t gen0_cntuforce_upmethod:6;
-        /** gen0_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
-         *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
-         *  High\\3: Disabled
-         */
-        uint32_t gen0_a_cntuforce_mode:2;
-        /** gen0_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
-         *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
-         *  High\\3: Disabled
-         */
-        uint32_t gen0_b_cntuforce_mode:2;
-        /** gen0_a_nciforce : R/W; bitpos: [10]; default: 0;
-         *  Configures the generation of non-continuous immediate software-force event for
-         *  PWM$n A, a toggle will trigger a force event.
-         */
-        uint32_t gen0_a_nciforce:1;
-        /** gen0_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
-         *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
-         *  Disabled\\1: Low\\2: High\\3: Disabled
-         */
-        uint32_t gen0_a_nciforce_mode:2;
-        /** gen0_b_nciforce : R/W; bitpos: [13]; default: 0;
-         *  Configures the generation of non-continuous immediate software-force event for
-         *  PWM$n B, a toggle will trigger a force event.
-         */
-        uint32_t gen0_b_nciforce:1;
-        /** gen0_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
-         *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
-         *  Disabled\\1: Low\\2: High\\3: Disabled
-         */
-        uint32_t gen0_b_nciforce_mode:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_force_reg_t;
-
-/** Type of gen0_a register
- *  PWM$n output signal A actions configuration register
- */
-typedef union {
-    struct {
-        /** gen0_a_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_utez:2;
-        /** gen0_a_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_utep:2;
-        /** gen0_a_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_utea:2;
-        /** gen0_a_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_uteb:2;
-        /** gen0_a_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_ut0:2;
-        /** gen0_a_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_ut1:2;
-        /** gen0_a_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_dtez:2;
-        /** gen0_a_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_dtep:2;
-        /** gen0_a_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_dtea:2;
-        /** gen0_a_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_dteb:2;
-        /** gen0_a_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_dt0:2;
-        /** gen0_a_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_a_dt1:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_gen_a_reg_t;
-
-/** Type of gen0_b register
- *  PWM$n output signal B actions configuration register
- */
-typedef union {
-    struct {
-        /** gen0_b_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_utez:2;
-        /** gen0_b_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_utep:2;
-        /** gen0_b_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_utea:2;
-        /** gen0_b_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_uteb:2;
-        /** gen0_b_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_ut0:2;
-        /** gen0_b_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_ut1:2;
-        /** gen0_b_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_dtez:2;
-        /** gen0_b_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_dtep:2;
-        /** gen0_b_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_dtea:2;
-        /** gen0_b_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_dteb:2;
-        /** gen0_b_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_dt0:2;
-        /** gen0_b_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen0_b_dt1:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_gen_b_reg_t;
-
-/** Type of dt0_cfg register
- *  Dead time configuration register
- */
-typedef union {
-    struct {
-        /** db0_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures update method for FED (Falling edge delay) active register.\\0:
-         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t db0_fed_upmethod:4;
-        /** db0_red_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Configures update method for RED (rising edge delay) active register.\\0:
-         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t db0_red_upmethod:4;
-        /** db0_deb_mode : R/W; bitpos: [8]; default: 0;
-         *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
-         *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
-         */
-        uint32_t db0_deb_mode:1;
-        /** db0_a_outswap : R/W; bitpos: [9]; default: 0;
-         *  Configures S6 in table.
-         */
-        uint32_t db0_a_outswap:1;
-        /** db0_b_outswap : R/W; bitpos: [10]; default: 0;
-         *  Configures S7 in table.
-         */
-        uint32_t db0_b_outswap:1;
-        /** db0_red_insel : R/W; bitpos: [11]; default: 0;
-         *  Configures S4 in table.
-         */
-        uint32_t db0_red_insel:1;
-        /** db0_fed_insel : R/W; bitpos: [12]; default: 0;
-         *  Configures S5 in table.
-         */
-        uint32_t db0_fed_insel:1;
-        /** db0_red_outinvert : R/W; bitpos: [13]; default: 0;
-         *  Configures S2 in table.
-         */
-        uint32_t db0_red_outinvert:1;
-        /** db0_fed_outinvert : R/W; bitpos: [14]; default: 0;
-         *  Configures S3 in table.
-         */
-        uint32_t db0_fed_outinvert:1;
-        /** db0_a_outbypass : R/W; bitpos: [15]; default: 1;
-         *  Configures S1 in table.
-         */
-        uint32_t db0_a_outbypass:1;
-        /** db0_b_outbypass : R/W; bitpos: [16]; default: 1;
-         *  Configures S0 in table.
-         */
-        uint32_t db0_b_outbypass:1;
-        /** db0_clk_sel : R/W; bitpos: [17]; default: 0;
-         *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
-         */
-        uint32_t db0_clk_sel:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} mcpwm_dt_cfg_reg_t;
-
-/** Type of dt0_fed_cfg register
- *  Falling edge delay (FED) shadow register
- */
-typedef union {
-    struct {
-        /** db0_fed : R/W; bitpos: [15:0]; default: 0;
-         *  Configures shadow register for FED.
-         */
-        uint32_t db0_fed:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_fed_cfg_reg_t;
-
-/** Type of dt0_red_cfg register
- *  Rising edge delay (RED) shadow register
- */
-typedef union {
-    struct {
-        /** db0_red : R/W; bitpos: [15:0]; default: 0;
-         *  Configures shadow register for RED.
-         */
-        uint32_t db0_red:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_red_cfg_reg_t;
-
-/** Type of carrier0_cfg register
- *  Carrier$n configuration register
- */
-typedef union {
-    struct {
-        /** chopper0_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
-         */
-        uint32_t chopper0_en:1;
-        /** chopper0_prescale : R/W; bitpos: [4:1]; default: 0;
-         *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
-         *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
-         */
-        uint32_t chopper0_prescale:4;
-        /** chopper0_duty : R/W; bitpos: [7:5]; default: 0;
-         *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
-         */
-        uint32_t chopper0_duty:3;
-        /** chopper0_oshtwth : R/W; bitpos: [11:8]; default: 0;
-         *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
-         */
-        uint32_t chopper0_oshtwth:4;
-        /** chopper0_out_invert : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
-         *  submodule.\\0: Normal\\1: Invert
-         */
-        uint32_t chopper0_out_invert:1;
-        /** chopper0_in_invert : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
-         *  submodule.\\0: Normal\\1: Invert
-         */
-        uint32_t chopper0_in_invert:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} mcpwm_carrier_cfg_reg_t;
-
-/** Type of fh0_cfg0 register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-typedef union {
-    struct {
-        /** tz0_sw_cbc : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_sw_cbc:1;
-        /** tz0_f2_cbc : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_f2_cbc:1;
-        /** tz0_f1_cbc : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_f1_cbc:1;
-        /** tz0_f0_cbc : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_f0_cbc:1;
-        /** tz0_sw_ost : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable software force one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_sw_ost:1;
-        /** tz0_f2_ost : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_f2_ost:1;
-        /** tz0_f1_ost : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_f1_ost:1;
-        /** tz0_f0_ost : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz0_f0_ost:1;
-        /** tz0_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
-         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_a_cbc_d:2;
-        /** tz0_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
-         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_a_cbc_u:2;
-        /** tz0_a_ost_d : R/W; bitpos: [13:12]; default: 0;
-         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
-         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_a_ost_d:2;
-        /** tz0_a_ost_u : R/W; bitpos: [15:14]; default: 0;
-         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
-         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_a_ost_u:2;
-        /** tz0_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
-         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_b_cbc_d:2;
-        /** tz0_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
-         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_b_cbc_u:2;
-        /** tz0_b_ost_d : R/W; bitpos: [21:20]; default: 0;
-         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
-         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_b_ost_d:2;
-        /** tz0_b_ost_u : R/W; bitpos: [23:22]; default: 0;
-         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
-         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz0_b_ost_u:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg0_reg_t;
-
-/** Type of fh0_cfg1 register
- *  Software triggers for fault handler actions configuration register
- */
-typedef union {
-    struct {
-        /** tz0_clr_ost : R/W; bitpos: [0]; default: 0;
-         *  Configures the generation of software one-shot mode action clear. A toggle
-         *  (software negate its value) triggers a clear for on going one-shot mode action.
-         */
-        uint32_t tz0_clr_ost:1;
-        /** tz0_cbcpulse : R/W; bitpos: [2:1]; default: 0;
-         *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
-         *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
-         */
-        uint32_t tz0_cbcpulse:2;
-        /** tz0_force_cbc : R/W; bitpos: [3]; default: 0;
-         *  Configures the generation of software cycle-by-cycle mode action. A toggle
-         *  (software negate its value) triggers a cycle-by-cycle mode action.
-         */
-        uint32_t tz0_force_cbc:1;
-        /** tz0_force_ost : R/W; bitpos: [4]; default: 0;
-         *  Configures the generation of software one-shot mode action. A toggle (software
-         *  negate its value) triggers a one-shot mode action.
-         */
-        uint32_t tz0_force_ost:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg1_reg_t;
-
-/** Type of fh0_status register
- *  Fault events status register
- */
-typedef union {
-    struct {
-        /** tz0_cbc_on : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
-         *  action\\1: On going
-         */
-        uint32_t tz0_cbc_on:1;
-        /** tz0_ost_on : RO; bitpos: [1]; default: 0;
-         *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
-         *  going
-         */
-        uint32_t tz0_ost_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mcpwm_fh_status_reg_t;
-
-/** Group: fault_detect */
-/** Type of fault_detect register
- *  Fault detection configuration and status register
- */
-typedef union {
-    struct {
-        /** f0_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f0_en:1;
-        /** f1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f1_en:1;
-        /** f2_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f2_en:1;
-        /** f0_pole : R/W; bitpos: [3]; default: 0;
-         *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f0_pole:1;
-        /** f1_pole : R/W; bitpos: [4]; default: 0;
-         *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f1_pole:1;
-        /** f2_pole : R/W; bitpos: [5]; default: 0;
-         *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f2_pole:1;
-        /** event_f0 : RO; bitpos: [6]; default: 0;
-         *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f0:1;
-        /** event_f1 : RO; bitpos: [7]; default: 0;
-         *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f1:1;
-        /** event_f2 : RO; bitpos: [8]; default: 0;
-         *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f2:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} mcpwm_fault_detect_reg_t;
-
-
-/** Group: cap_timer_cfg */
-/** Type of cap_timer_cfg register
- *  Capture timer configuration register
- */
-typedef union {
-    struct {
-        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
-         */
-        uint32_t cap_timer_en:1;
-        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
-         */
-        uint32_t cap_synci_en:1;
-        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
-         *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
-         *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
-         *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
-         */
-        uint32_t cap_synci_sel:3;
-        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
-         *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
-         *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
-         *  value in phase register
-         */
-        uint32_t cap_sync_sw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_cfg_reg_t;
-
-
-/** Group: cap_timer_phase */
-/** Type of cap_timer_phase register
- *  Capture timer sync phase register
- */
-typedef union {
-    struct {
-        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
-         *  Configures phase value for capture timer sync operation.
-         */
-        uint32_t cap_phase:32;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_phase_reg_t;
-
-
-/** Group: cap_chn_cfg */
-/** Type of cap_chn_cfg register
- *  Capture channel n configuration register
- */
-typedef union {
-    struct {
-        /** cap0_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable
-         */
-        uint32_t cap0_en:1;
-        /** cap0_mode : R/W; bitpos: [2:1]; default: 0;
-         *  Configures which edge of capture on channel n after prescaling is used.\\0:
-         *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
-         *  Enable capture on the positive edge
-         */
-        uint32_t cap0_mode:2;
-        /** cap0_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Configures prescale value on possitive edge of CAPn. Prescale value =
-         *  PWM_CAPn_PRESCALE + 1
-         */
-        uint32_t cap0_prescale:8;
-        /** cap0_in_invert : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0:
-         *  Normal\\1: Invert
-         */
-        uint32_t cap0_in_invert:1;
-        /** cap0_sw : WT; bitpos: [12]; default: 0;
-         *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
-         *  software forced capture on channel n
-         */
-        uint32_t cap0_sw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_cfg_reg_t;
-
-
-/** Group: cap_chn */
-/** Type of cap_chn register
- *  CAPn capture value register
- */
-typedef union {
-    struct {
-        /** cap0_value : RO; bitpos: [31:0]; default: 0;
-         *  Represents value of last capture on CAPn
-         */
-        uint32_t cap0_value:32;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_reg_t;
-
-
-/** Group: cap_status */
-/** Type of cap_status register
- *  Last capture trigger edge information register
- */
-typedef union {
-    struct {
-        /** cap0_edge : RO; bitpos: [0]; default: 0;
-         *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap0_edge:1;
-        /** cap1_edge : RO; bitpos: [1]; default: 0;
-         *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap1_edge:1;
-        /** cap2_edge : RO; bitpos: [2]; default: 0;
-         *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap2_edge:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} mcpwm_cap_status_reg_t;
-
-
-/** Group: update_cfg */
-/** Type of update_cfg register
- *  Generator Update configuration register
- */
-typedef union {
-    struct {
-        /** global_up_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether or not to enable global update for all active registers in MCPWM
-         *  module.\\0: Disable\\1: Enable
-         */
-        uint32_t global_up_en:1;
-        /** global_force_up : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of global forced update for all active registers in MCPWM
-         *  module. A toggle (software invert its value) will trigger a global forced update.
-         *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
-         */
-        uint32_t global_force_up:1;
-        /** op0_up_en : R/W; bitpos: [2]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op0_up_en:1;
-        /** op0_force_up : R/W; bitpos: [3]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator0. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
-         */
-        uint32_t op0_force_up:1;
-        /** op1_up_en : R/W; bitpos: [4]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op1_up_en:1;
-        /** op1_force_up : R/W; bitpos: [5]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator1. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
-         */
-        uint32_t op1_force_up:1;
-        /** op2_up_en : R/W; bitpos: [6]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op2_up_en:1;
-        /** op2_force_up : R/W; bitpos: [7]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator2. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
-         */
-        uint32_t op2_force_up:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_update_cfg_reg_t;
-
-
-/** Group: int_ena */
-/** Type of int_ena register
- *  Interrupt enable register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_ena:1;
-        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_ena:1;
-        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_ena:1;
-        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_ena:1;
-        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_ena:1;
-        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_ena:1;
-        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_ena:1;
-        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_ena:1;
-        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_ena:1;
-        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_ena:1;
-        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_ena:1;
-        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_ena:1;
-        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
-         */
-        uint32_t fault0_clr_int_ena:1;
-        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
-         */
-        uint32_t fault1_clr_int_ena:1;
-        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
-         */
-        uint32_t fault2_clr_int_ena:1;
-        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
-         */
-        uint32_t cmpr0_tea_int_ena:1;
-        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
-         */
-        uint32_t cmpr1_tea_int_ena:1;
-        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
-         */
-        uint32_t cmpr2_tea_int_ena:1;
-        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
-         */
-        uint32_t cmpr0_teb_int_ena:1;
-        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
-         */
-        uint32_t cmpr1_teb_int_ena:1;
-        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
-         */
-        uint32_t cmpr2_teb_int_ena:1;
-        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM0.
-         */
-        uint32_t tz0_cbc_int_ena:1;
-        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM1.
-         */
-        uint32_t tz1_cbc_int_ena:1;
-        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM2.
-         */
-        uint32_t tz2_cbc_int_ena:1;
-        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_ost_int_ena:1;
-        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_ost_int_ena:1;
-        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_ost_int_ena:1;
-        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
-         */
-        uint32_t cap0_int_ena:1;
-        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
-         */
-        uint32_t cap1_int_ena:1;
-        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
-         */
-        uint32_t cap2_int_ena:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_ena_reg_t;
-
-
-/** Group: int_raw */
-/** Type of int_raw register
- *  Interrupt raw status register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  0 stops.
-         */
-        uint32_t timer0_stop_int_raw:1;
-        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  1 stops.
-         */
-        uint32_t timer1_stop_int_raw:1;
-        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  2 stops.
-         */
-        uint32_t timer2_stop_int_raw:1;
-        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  0 TEZ event.
-         */
-        uint32_t timer0_tez_int_raw:1;
-        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  1 TEZ event.
-         */
-        uint32_t timer1_tez_int_raw:1;
-        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  2 TEZ event.
-         */
-        uint32_t timer2_tez_int_raw:1;
-        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  0 TEP event.
-         */
-        uint32_t timer0_tep_int_raw:1;
-        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  1 TEP event.
-         */
-        uint32_t timer1_tep_int_raw:1;
-        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  2 TEP event.
-         */
-        uint32_t timer2_tep_int_raw:1;
-        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
-         *  starts.
-         */
-        uint32_t fault0_int_raw:1;
-        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
-         *  starts.
-         */
-        uint32_t fault1_int_raw:1;
-        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
-         *  starts.
-         */
-        uint32_t fault2_int_raw:1;
-        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
-         *  clears.
-         */
-        uint32_t fault0_clr_int_raw:1;
-        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
-         *  clears.
-         */
-        uint32_t fault1_clr_int_raw:1;
-        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
-         *  clears.
-         */
-        uint32_t fault2_clr_int_raw:1;
-        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_raw:1;
-        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_raw:1;
-        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_raw:1;
-        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_raw:1;
-        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_raw:1;
-        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_raw:1;
-        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_raw:1;
-        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_raw:1;
-        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_raw:1;
-        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_raw:1;
-        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_raw:1;
-        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_raw:1;
-        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP0.
-         */
-        uint32_t cap0_int_raw:1;
-        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP1.
-         */
-        uint32_t cap1_int_raw:1;
-        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP2.
-         */
-        uint32_t cap2_int_raw:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_raw_reg_t;
-
-
-/** Group: int_st */
-/** Type of int_st register
- *  Interrupt masked status register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 0 stops.
-         */
-        uint32_t timer0_stop_int_st:1;
-        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 1 stops.
-         */
-        uint32_t timer1_stop_int_st:1;
-        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 2 stops.
-         */
-        uint32_t timer2_stop_int_st:1;
-        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_st:1;
-        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_st:1;
-        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_st:1;
-        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_st:1;
-        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_st:1;
-        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_st:1;
-        /** fault0_int_st : RO; bitpos: [9]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f0 starts.
-         */
-        uint32_t fault0_int_st:1;
-        /** fault1_int_st : RO; bitpos: [10]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f1 starts.
-         */
-        uint32_t fault1_int_st:1;
-        /** fault2_int_st : RO; bitpos: [11]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f2 starts.
-         */
-        uint32_t fault2_int_st:1;
-        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f0 clears.
-         */
-        uint32_t fault0_clr_int_st:1;
-        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f1 clears.
-         */
-        uint32_t fault1_clr_int_st:1;
-        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f2 clears.
-         */
-        uint32_t fault2_clr_int_st:1;
-        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_st:1;
-        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_st:1;
-        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_st:1;
-        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_st:1;
-        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_st:1;
-        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_st:1;
-        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_st:1;
-        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_st:1;
-        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_st:1;
-        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_st:1;
-        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_st:1;
-        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_st:1;
-        /** cap0_int_st : RO; bitpos: [27]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP0.
-         */
-        uint32_t cap0_int_st:1;
-        /** cap1_int_st : RO; bitpos: [28]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP1.
-         */
-        uint32_t cap1_int_st:1;
-        /** cap2_int_st : RO; bitpos: [29]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP2.
-         */
-        uint32_t cap2_int_st:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_st_reg_t;
-
-
-/** Group: int_clr */
-/** Type of int_clr register
- *  Interrupt clear register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_clr:1;
-        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_clr:1;
-        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_clr:1;
-        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_clr:1;
-        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_clr:1;
-        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_clr:1;
-        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_clr:1;
-        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_clr:1;
-        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_clr:1;
-        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_clr:1;
-        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_clr:1;
-        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_clr:1;
-        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
-         */
-        uint32_t fault0_clr_int_clr:1;
-        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
-         */
-        uint32_t fault1_clr_int_clr:1;
-        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
-         */
-        uint32_t fault2_clr_int_clr:1;
-        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_clr:1;
-        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_clr:1;
-        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_clr:1;
-        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_clr:1;
-        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_clr:1;
-        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_clr:1;
-        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM0.
-         */
-        uint32_t tz0_cbc_int_clr:1;
-        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM1.
-         */
-        uint32_t tz1_cbc_int_clr:1;
-        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM2.
-         */
-        uint32_t tz2_cbc_int_clr:1;
-        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_ost_int_clr:1;
-        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_ost_int_clr:1;
-        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_ost_int_clr:1;
-        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
-         */
-        uint32_t cap0_int_clr:1;
-        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
-         */
-        uint32_t cap1_int_clr:1;
-        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
-         */
-        uint32_t cap2_int_clr:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_clr_reg_t;
-
-
-/** Group: evt_en */
-/** Type of evt_en register
- *  Event enable register
- */
-typedef union {
-    struct {
-        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer0_stop_en:1;
-        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer1_stop_en:1;
-        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer2_stop_en:1;
-        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable timer0 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer0_tez_en:1;
-        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable timer1 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer1_tez_en:1;
-        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable timer2 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer2_tez_en:1;
-        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable timer0 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer0_tep_en:1;
-        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable timer1 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer1_tep_en:1;
-        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable timer2 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer2_tep_en:1;
-        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tea_en:1;
-        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tea_en:1;
-        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tea_en:1;
-        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_teb_en:1;
-        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_teb_en:1;
-        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_teb_en:1;
-        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f0_en:1;
-        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f1_en:1;
-        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f2_en:1;
-        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f0_clr_en:1;
-        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f1_clr_en:1;
-        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f2_clr_en:1;
-        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz0_cbc_en:1;
-        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz1_cbc_en:1;
-        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz2_cbc_en:1;
-        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz0_ost_en:1;
-        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
-         *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz1_ost_en:1;
-        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
-         *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz2_ost_en:1;
-        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap0_en:1;
-        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap1_en:1;
-        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap2_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_evt_en_reg_t;
-
-
-/** Group: task_en */
-/** Type of task_en register
- *  Task enable register
- */
-typedef union {
-    struct {
-        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr0_a_up_en:1;
-        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr1_a_up_en:1;
-        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr2_a_up_en:1;
-        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr0_b_up_en:1;
-        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr1_b_up_en:1;
-        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr2_b_up_en:1;
-        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable all PWM generate stop task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_gen_stop_en:1;
-        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer0_sync_en:1;
-        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer1_sync_en:1;
-        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer2_sync_en:1;
-        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable timer0 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer0_period_up_en:1;
-        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable timer1 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer1_period_up_en:1;
-        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable timer2 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer2_period_up_en:1;
-        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz0_ost_en:1;
-        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz1_ost_en:1;
-        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz2_ost_en:1;
-        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr0_ost_en:1;
-        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr1_ost_en:1;
-        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr2_ost_en:1;
-        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap0_en:1;
-        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap1_en:1;
-        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap2_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} mcpwm_task_en_reg_t;
-
-
-/** Group: evt_en2 */
-/** Type of evt_en2 register
- *  Event enable register2
- */
-typedef union {
-    struct {
-        /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tee1_en:1;
-        /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tee1_en:1;
-        /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tee1_en:1;
-        /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tee2_en:1;
-        /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tee2_en:1;
-        /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tee2_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_evt_en2_reg_t;
-
-
-/** Group: Configuration register */
-/** Type of opn_tstmp_e1 register
- *  Generatorn timer stamp E1 value register
- */
-typedef union {
-    struct {
-        /** op0_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures generatorn timer stamp E1 value register
-         */
-        uint32_t op0_tstmp_e1:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_op_tstmp_e1_reg_t;
-
-/** Type of op0_tstmp_e2 register
- *  Generator$n timer stamp E2 value register
- */
-typedef union {
-    struct {
-        /** op0_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures generator$n timer stamp E2 value register
-         */
-        uint32_t op0_tstmp_e2:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_op_tstmp_e2_reg_t;
-
-/** Type of clk register
- *  Global configuration register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
-         *  when application writes registers\\1: Force open the clock gate for register
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mcpwm_clk_reg_t;
-
-
-/** Group: Version register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725968;
-         *  Configures the version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mcpwm_version_reg_t;
-
-typedef struct {
-    volatile mcpwm_timer_cfg0_reg_t cfg0;
-    volatile mcpwm_timer_cfg1_reg_t cfg1;
-    volatile mcpwm_timer_sync_reg_t sync;
-    volatile mcpwm_timer_status_reg_t status;
-} mcpwm_timer_regs_t;
-
-typedef struct {
-    volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
-    volatile mcpwm_gen_tstmp_a_reg_t gen_tstmp_a;
-    volatile mcpwm_gen_tstmp_b_reg_t gen_tstmp_b;
-    volatile mcpwm_gen_cfg0_reg_t gen_cfg0;
-    volatile mcpwm_gen_force_reg_t gen_force;
-    volatile mcpwm_gen_a_reg_t gen_a;
-    volatile mcpwm_gen_b_reg_t gen_b;
-    volatile mcpwm_dt_cfg_reg_t dt_cfg;
-    volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
-    volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg;
-    volatile mcpwm_carrier_cfg_reg_t carrier_cfg;
-    volatile mcpwm_fh_cfg0_reg_t fh_cfg0;
-    volatile mcpwm_fh_cfg1_reg_t fh_cfg1;
-    volatile mcpwm_fh_status_reg_t fh_status;
-} mcpwm_operator_reg_t;
-
-typedef struct {
-    volatile mcpwm_op_tstmp_e1_reg_t tstmp_e1;
-    volatile mcpwm_op_tstmp_e2_reg_t tstmp_e2;
-} mcpwm_operator_tstmp_reg_t;
-
-typedef struct {
-    volatile mcpwm_clk_cfg_reg_t clk_cfg;
-    volatile mcpwm_timer_regs_t timer[3];
-    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
-    volatile mcpwm_operator_timersel_reg_t operator_timersel;
-    volatile mcpwm_operator_reg_t operators[3];
-    volatile mcpwm_fault_detect_reg_t fault_detect;
-    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
-    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
-    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
-    volatile mcpwm_cap_chn_reg_t cap_chn[3];
-    volatile mcpwm_cap_status_reg_t cap_status;
-    volatile mcpwm_update_cfg_reg_t update_cfg;
-    volatile mcpwm_int_ena_reg_t int_ena;
-    volatile mcpwm_int_raw_reg_t int_raw;
-    volatile mcpwm_int_st_reg_t int_st;
-    volatile mcpwm_int_clr_reg_t int_clr;
-    volatile mcpwm_evt_en_reg_t evt_en;
-    volatile mcpwm_task_en_reg_t task_en;
-    volatile mcpwm_evt_en2_reg_t evt_en2;
-    volatile mcpwm_operator_tstmp_reg_t op_tstmp[3];
-    volatile mcpwm_clk_reg_t clk;
-    volatile mcpwm_version_reg_t version;
-} mcpwm_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h
index bdb3e63aae..c6397f4729 100644
--- a/components/soc/esp32p4/include/soc/reg_base.h
+++ b/components/soc/esp32p4/include/soc/reg_base.h
@@ -4,11 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-//#define DR_REG_PLIC_MX_BASE                     0x20001000
-//#define DR_REG_PLIC_UX_BASE                     0x20001400
-//#define DR_REG_CLINT_M_BASE                     0x20001800
-//#define DR_REG_CLINT_U_BASE                     0x20001C00
-
 /* Basic address */
 #define DR_REG_HPCPUTCP_BASE          0x3FF00000
 #define DR_REG_HPPERIPH0_BASE         0x50000000
@@ -127,7 +122,7 @@
  * @size: 64KB
  */
 #define DR_REG_LP_SYS_BASE            (DR_REG_LPAON_BASE + 0x0)
-#define DR_REG_LP_AONCLKRST_BASE      (DR_REG_LPAON_BASE + 0x1000)
+#define DR_REG_LP_CLKRST_BASE         (DR_REG_LPAON_BASE + 0x1000)
 #define DR_REG_LP_TIMER_BASE          (DR_REG_LPAON_BASE + 0x2000)
 #define DR_REG_LP_ANAPERI_BASE        (DR_REG_LPAON_BASE + 0x3000)
 #define DR_REG_LP_HUK_BASE            (DR_REG_LPAON_BASE + 0x4000)
@@ -153,30 +148,24 @@
 #define DR_REG_LP_ADC_BASE            (DR_REG_LPPERIPH_BASE + 0x7000)
 #define DR_REG_LP_TOUCH_BASE          (DR_REG_LPPERIPH_BASE + 0x8000)
 #define DR_REG_LP_GPIO_BASE           (DR_REG_LPPERIPH_BASE + 0xA000)
+#define DR_REG_LP_IOMUX_BASE          (DR_REG_LPPERIPH_BASE + 0xB000)
 #define DR_REG_LP_INTR_BASE           (DR_REG_LPPERIPH_BASE + 0xC000)
-#define DR_REG_LP_IOMUX_BASE          0 // just for compile, need remove later
 #define DR_REG_EFUSE_BASE             (DR_REG_LPPERIPH_BASE + 0xD000)
 #define DR_REG_LP_PERI_PMS_BASE       (DR_REG_LPPERIPH_BASE + 0xE000)
 #define DR_REG_HP2LP_PERI_PMS_BASE    (DR_REG_LPPERIPH_BASE + 0xE800)
 #define DR_REG_LP_TSENSOR_BASE        (DR_REG_LPPERIPH_BASE + 0xF000)
 
-/* this is some module helper MACROs for quick module reference
+/**
+ * This are module helper MACROs for quick module reference
  * including some module(renamed) address
  */
 #define DR_REG_UART_BASE                        DR_REG_UART0_BASE
-// ESP32P4-TODO: check this
-#define DR_REG_I2C_EXT_BASE                     0x60004000
 #define DR_REG_UHCI0_BASE                       DR_REG_UHCI_BASE
 #define DR_REG_TIMERGROUP0_BASE                 DR_REG_TIMG0_BASE
 #define DR_REG_TIMERGROUP1_BASE                 DR_REG_TIMG1_BASE
 #define DR_REG_I2S_BASE                         DR_REG_I2S0_BASE
-// ESP32P4-TODO: check this
-#define DR_REG_APB_SARADC_BASE                  0x6000E000
 #define DR_REG_USB_SERIAL_JTAG_BASE             DR_REG_USB2JTAG_BASE
 #define DR_REG_INTERRUPT_MATRIX_BASE            DR_REG_INTR_BASE
-// ESP32P4-TODO: check this
-#define DR_REG_ATOMIC_BASE                      0x60011000
-// ESP32P4-TODO: check this
 #define DR_REG_SOC_ETM_BASE                     DR_REG_ETM_BASE
 #define DR_REG_MCPWM_BASE                       DR_REG_MCPWM0_BASE
 #define DR_REG_PARL_IO_BASE                     DR_REG_PARIO_BASE
@@ -189,41 +178,31 @@
 #define DR_REG_DIGITAL_SIGNATURE_BASE           DR_REG_DS_BASE
 #define DR_REG_HMAC_BASE                        (DR_REG_CRYPTO_BASE + 0x5000)
 #define DR_REG_ECDSA_BASE                       (DR_REG_CRYPTO_BASE + 0x6000)
-// ESP32P4-TODO: check this
-#define DR_REG_GPIO_EXT_BASE                    0x60091f00 //ESP32C6-TODO
 #define DR_REG_MEM_MONITOR_BASE                 DR_REG_L2MEM_MON_BASE
-// ESP32P4-TODO: check this
-#define DR_REG_PAU_BASE                         0x60093000
-// ESP32P4-TODO: check this
-#define DR_REG_HP_SYSTEM_BASE                   0x60095000
-// ESP32P4-TODO: should remove this
-#define DR_REG_SYSTEM_BASE                      DR_REG_HP_SYS_BASE
-// ESP32P4-TODO: should remove this
-#define DR_REG_RTCCNTL_BASE                     0x60008000
-// ESP32P4-TODO: should remove this
-#define DR_REG_AES_XTS_BASE                     0x600CC000
-#define DR_REG_PCR_BASE                         0x60096000
-#define DR_REG_TEE_BASE                         0x60098000
-#define DR_REG_HP_APM_BASE                      0x60099000
-#define DR_REG_LP_APM0_BASE                     0x60099800
-#define DR_REG_MISC_BASE                        0x6009F000
-
 #define DR_REG_HP_CLKRST_BASE                   DR_REG_HP_SYS_CLKRST_BASE
-#define DR_REG_DSPI_MEM_BASE                    (DR_REG_PSRAM_MSPI0_BASE)
+#define DR_REG_DSPI_MEM_BASE                    DR_REG_PSRAM_MSPI0_BASE
 #define DR_REG_INTERRUPT_CORE0_BASE             DR_REG_INTR_BASE
 #define DR_REG_INTERRUPT_CORE1_BASE             (DR_REG_INTR_BASE + 0x800)
-
-#define DR_REG_LP_CLKRST_BASE                   0x600B0400
-#define DR_REG_LP_AON_BASE                      0x600B1000
-#define DR_REG_LP_IO_BASE                       0x600B2000
-#define DR_REG_LP_I2C_ANA_MST_BASE              0x600B2400
 #define DR_REG_LPPERI_BASE                      DR_REG_LP_PERI_CLKRST_BASE
-#define DR_REG_LP_ANALOG_PERI_BASE              0x600B2C00
-#define DR_REG_LP_TEE_BASE                      0x600B3400
-#define DR_REG_LP_APM_BASE                      0x600B3800
-#define DR_REG_OPT_DEBUG_BASE                   0x600B3C00
+#define DR_REG_CPU_BUS_MONITOR_BASE             DR_REG_CPU_BUS_MON_BASE
 
-#define DR_REG_TRACE_BASE                       0x600C0000
+
+//TODO: IDF-7481, TODO: IDF-7479, TODO: IDF-7551
+// #define DR_REG_GPIO_EXT_BASE                    0x60091f00
+
+//TODO: IDF-7542
+// #define DR_REG_TEE_BASE                         0x60098000
+// #define DR_REG_HP_APM_BASE                      0x60099000
+// #define DR_REG_LP_APM0_BASE                     0x60099800
+// #define DR_REG_LP_TEE_BASE                      0x600B3400
+// #define DR_REG_LP_APM_BASE                      0x600B3800
+
+//TODO: IDF-7531
+// #define DR_REG_PAU_BASE                         0x60093000
+// #define DR_REG_LP_ANALOG_PERI_BASE              0x600B2C00
+// #define DR_REG_LP_I2C_ANA_MST_BASE              0x600B2400
+// #define DR_REG_LP_AON_BASE                      0x600B1000
+
+//TODO: IDF-7688
+// #define DR_REG_TRACE_BASE                       0x600C0000
 #define DR_REG_ASSIST_DEBUG_BASE                0x3FF06000
-#define DR_REG_CPU_BUS_MONITOR_BASE             0x600C2000
-#define DR_REG_INTPRI_BASE                      0x600C5000
diff --git a/components/soc/esp32p4/include/soc/regi2c_bbpll.h b/components/soc/esp32p4/include/soc/regi2c_bbpll.h
index 0b0cb7af45..235bca28dd 100644
--- a/components/soc/esp32p4/include/soc/regi2c_bbpll.h
+++ b/components/soc/esp32p4/include/soc/regi2c_bbpll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,162 +14,3 @@
  * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_cpu_freq_set function in rtc_clk.c.
  */
-
-#define I2C_BBPLL           0x66
-#define I2C_BBPLL_HOSTID    0
-
-#define I2C_BBPLL_IR_CAL_DELAY        0
-#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
-#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_BBPLL_IR_CAL_CK_DIV        0
-#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
-#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    6
-#define I2C_BBPLL_IR_CAL_START_LSB    6
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        1
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
-#define I2C_BBPLL_OC_REF_DIV        2
-#define I2C_BBPLL_OC_REF_DIV_MSB    3
-#define I2C_BBPLL_OC_REF_DIV_LSB    0
-
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_OC_ENB_FCAL        2
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_RSTB_DIV_ADC        4
-#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
-#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
-
-#define I2C_BBPLL_MODE_HF        4
-#define I2C_BBPLL_MODE_HF_MSB    1
-#define I2C_BBPLL_MODE_HF_LSB    1
-
-#define I2C_BBPLL_DIV_ADC        4
-#define I2C_BBPLL_DIV_ADC_MSB    3
-#define I2C_BBPLL_DIV_ADC_LSB    2
-
-#define I2C_BBPLL_DIV_DAC        4
-#define I2C_BBPLL_DIV_DAC_MSB    4
-#define I2C_BBPLL_DIV_DAC_LSB    4
-
-#define I2C_BBPLL_DIV_CPU        4
-#define I2C_BBPLL_DIV_CPU_MSB    5
-#define I2C_BBPLL_DIV_CPU_LSB    5
-
-#define I2C_BBPLL_OC_ENB_VCON        4
-#define I2C_BBPLL_OC_ENB_VCON_MSB    6
-#define I2C_BBPLL_OC_ENB_VCON_LSB    6
-
-#define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    7
-#define I2C_BBPLL_OC_TSCHGP_LSB    7
-
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
-
-#define I2C_BBPLL_EN_USB        5
-#define I2C_BBPLL_EN_USB_MSB    7
-#define I2C_BBPLL_EN_USB_LSB    7
-
-#define I2C_BBPLL_OC_DCUR        6
-#define I2C_BBPLL_OC_DCUR_MSB    2
-#define I2C_BBPLL_OC_DCUR_LSB    0
-
-#define I2C_BBPLL_INC_CUR        6
-#define I2C_BBPLL_INC_CUR_MSB    3
-#define I2C_BBPLL_INC_CUR_LSB    3
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
-#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
-#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
-
-#define I2C_BBPLL_OC_DLREF_SEL        6
-#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
-#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_CAL_CAP        8
-#define I2C_BBPLL_OR_CAL_CAP_MSB    3
-#define I2C_BBPLL_OR_CAL_CAP_LSB    0
-
-#define I2C_BBPLL_OR_CAL_UDF        8
-#define I2C_BBPLL_OR_CAL_UDF_MSB    4
-#define I2C_BBPLL_OR_CAL_UDF_LSB    4
-
-#define I2C_BBPLL_OR_CAL_OVF        8
-#define I2C_BBPLL_OR_CAL_OVF_MSB    5
-#define I2C_BBPLL_OR_CAL_OVF_LSB    5
-
-#define I2C_BBPLL_OR_CAL_END        8
-#define I2C_BBPLL_OR_CAL_END_MSB    6
-#define I2C_BBPLL_OR_CAL_END_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    7
-#define I2C_BBPLL_OR_LOCK_LSB    7
-
-#define I2C_BBPLL_OC_VCO_DBIAS        9
-#define I2C_BBPLL_OC_VCO_DBIAS_MSB    1
-#define I2C_BBPLL_OC_VCO_DBIAS_LSB    0
-
-#define I2C_BBPLL_BBADC_DELAY2        9
-#define I2C_BBPLL_BBADC_DELAY2_MSB    3
-#define I2C_BBPLL_BBADC_DELAY2_LSB    2
-
-#define I2C_BBPLL_BBADC_DVDD        9
-#define I2C_BBPLL_BBADC_DVDD_MSB    5
-#define I2C_BBPLL_BBADC_DVDD_LSB    4
-
-#define I2C_BBPLL_BBADC_DREF        9
-#define I2C_BBPLL_BBADC_DREF_MSB    7
-#define I2C_BBPLL_BBADC_DREF_LSB    6
-
-#define I2C_BBPLL_BBADC_DCUR        10
-#define I2C_BBPLL_BBADC_DCUR_MSB    1
-#define I2C_BBPLL_BBADC_DCUR_LSB    0
-
-#define I2C_BBPLL_BBADC_INPUT_SHORT        10
-#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
-#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
-
-#define I2C_BBPLL_ENT_ADC        10
-#define I2C_BBPLL_ENT_ADC_MSB    7
-#define I2C_BBPLL_ENT_ADC_LSB    6
diff --git a/components/soc/esp32p4/include/soc/regi2c_bias.h b/components/soc/esp32p4/include/soc/regi2c_bias.h
index fba5d6dbb5..c3abe087e8 100644
--- a/components/soc/esp32p4/include/soc/regi2c_bias.h
+++ b/components/soc/esp32p4/include/soc/regi2c_bias.h
@@ -13,10 +13,3 @@
  * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
  * bootloader_hardware_init function in bootloader_esp32c6.c.
  */
-
-#define I2C_BIAS            0X6A
-#define I2C_BIAS_HOSTID     0
-
-#define I2C_BIAS_DREG_1P1_PVT 1
-#define I2C_BIAS_DREG_1P1_PVT_MSB 3
-#define I2C_BIAS_DREG_1P1_PVT_LSB 0
diff --git a/components/soc/esp32p4/include/soc/regi2c_brownout.h b/components/soc/esp32p4/include/soc/regi2c_brownout.h
index 6a5ca15769..24377f9356 100644
--- a/components/soc/esp32p4/include/soc/regi2c_brownout.h
+++ b/components/soc/esp32p4/include/soc/regi2c_brownout.h
@@ -13,10 +13,3 @@
  * This file lists register fields of the brownout detector, located on an internal configuration
  * bus. These definitions are used via macros defined in regi2c_ctrl.h.
  */
-
-#define I2C_BOD            0x61
-#define I2C_BOD_HOSTID     0
-
-#define I2C_BOD_THRESHOLD           0x5
-#define I2C_BOD_THRESHOLD_MSB       2
-#define I2C_BOD_THRESHOLD_LSB       0
diff --git a/components/soc/esp32p4/include/soc/regi2c_defs.h b/components/soc/esp32p4/include/soc/regi2c_defs.h
index f9a2415bda..38db4f1595 100644
--- a/components/soc/esp32p4/include/soc/regi2c_defs.h
+++ b/components/soc/esp32p4/include/soc/regi2c_defs.h
@@ -27,11 +27,3 @@
 #define ANA_CONFIG2_M    BIT(18)
 
 #define ANA_I2C_SAR_FORCE_PU BIT(16)
-
-
-/**
- * Restore regi2c analog calibration related configuration registers.
- * This is a workaround, and is fixed on later chips
- */
-#define REGI2C_ANA_CALI_PD_WORKAROUND    1
-#define REGI2C_ANA_CALI_BYTE_NUM         8
diff --git a/components/soc/esp32p4/include/soc/regi2c_lp_bias.h b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h
index 5ca1c6833e..2388cd02fd 100644
--- a/components/soc/esp32p4/include/soc/regi2c_lp_bias.h
+++ b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,42 +14,3 @@
  * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_init function in rtc_init.c.
  */
-
-#define I2C_ULP 0x61
-#define I2C_ULP_HOSTID 0
-
-#define I2C_ULP_IR_RESETB 0
-#define I2C_ULP_IR_RESETB_MSB 0
-#define I2C_ULP_IR_RESETB_LSB 0
-
-#define I2C_ULP_IR_FORCE_XPD_CK 0
-#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
-#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
-
-#define I2C_ULP_IR_FORCE_XPD_IPH 0
-#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
-#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
-
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
-
-#define I2C_ULP_O_DONE_FLAG 3
-#define I2C_ULP_O_DONE_FLAG_MSB 0
-#define I2C_ULP_O_DONE_FLAG_LSB 0
-
-#define I2C_ULP_BG_O_DONE_FLAG 3
-#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
-#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
-
-#define I2C_ULP_OCODE 4
-#define I2C_ULP_OCODE_MSB 7
-#define I2C_ULP_OCODE_LSB 0
-
-#define I2C_ULP_IR_FORCE_CODE 5
-#define I2C_ULP_IR_FORCE_CODE_MSB 6
-#define I2C_ULP_IR_FORCE_CODE_LSB 6
-
-#define I2C_ULP_EXT_CODE 6
-#define I2C_ULP_EXT_CODE_MSB 7
-#define I2C_ULP_EXT_CODE_LSB 0
diff --git a/components/soc/esp32p4/include/soc/regi2c_saradc.h b/components/soc/esp32p4/include/soc/regi2c_saradc.h
index ea76c6620d..7511dfa4e2 100644
--- a/components/soc/esp32p4/include/soc/regi2c_saradc.h
+++ b/components/soc/esp32p4/include/soc/regi2c_saradc.h
@@ -14,66 +14,3 @@
  * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * function in adc_ll.h.
  */
-
-#define I2C_SAR_ADC            0X69
-#define I2C_SAR_ADC_HOSTID     0
-
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR1_DREF_ADDR  0x2
-#define ADC_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_SAR1_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR2_DREF_ADDR  0x5
-#define ADC_SAR2_DREF_ADDR_MSB  0x6
-#define ADC_SAR2_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
-
-#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
-#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
-
-#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
-#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
-
-#define I2C_SARADC_TSENS_DAC 0x6
-#define I2C_SARADC_TSENS_DAC_MSB 3
-#define I2C_SARADC_TSENS_DAC_LSB 0
diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h
index 5a4e577205..b7e3b101a2 100644
--- a/components/soc/esp32p4/include/soc/reset_reasons.h
+++ b/components/soc/esp32p4/include/soc/reset_reasons.h
@@ -23,7 +23,7 @@ extern "C" {
 #endif
 
 
-// TODO: IDF-5719
+// TODO: IDF-7791
 /**
  * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
  * @note refer to TRM: <Reset and Clock> chapter
diff --git a/components/soc/esp32p4/include/soc/rtc.h b/components/soc/esp32p4/include/soc/rtc.h
index 407e6d636e..a27bacea55 100644
--- a/components/soc/esp32p4/include/soc/rtc.h
+++ b/components/soc/esp32p4/include/soc/rtc.h
@@ -51,7 +51,7 @@ extern "C" {
 #define OTHER_BLOCKS_POWERUP        1
 #define OTHER_BLOCKS_WAIT           1
 
-// TODO: IDF-5781
+// TODO: IDF-7528, TODO: IDF-7529
 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
  * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
  */
@@ -75,7 +75,7 @@ extern "C" {
 #define SOC_DELAY_RC_FAST_DIGI_SWITCH       5
 #define SOC_DELAY_RC32K_ENABLE              300
 
-/* Core voltage: // TODO: IDF-5781
+/* Core voltage: // TODO: IDF-7528, TODO: IDF-7529
  * Currently, ESP32C6 never adjust its wake voltage in runtime
  * Only sets dig/rtc voltage dbias at startup time
  */
diff --git a/components/soc/esp32p4/include/soc/rtc_io_channel.h b/components/soc/esp32p4/include/soc/rtc_io_channel.h
index a3e2090e3b..d2aa55b41e 100644
--- a/components/soc/esp32p4/include/soc/rtc_io_channel.h
+++ b/components/soc/esp32p4/include/soc/rtc_io_channel.h
@@ -5,28 +5,3 @@
  */
 
 #pragma once
-
-//RTC GPIO channels
-#define RTCIO_GPIO0_CHANNEL         0   //RTCIO_CHANNEL_0
-#define RTCIO_CHANNEL_0_GPIO_NUM    0
-
-#define RTCIO_GPIO1_CHANNEL         1   //RTCIO_CHANNEL_1
-#define RTCIO_CHANNEL_1_GPIO_NUM    1
-
-#define RTCIO_GPIO2_CHANNEL         2   //RTCIO_CHANNEL_2
-#define RTCIO_CHANNEL_2_GPIO_NUM    2
-
-#define RTCIO_GPIO3_CHANNEL         3   //RTCIO_CHANNEL_3
-#define RTCIO_CHANNEL_3_GPIO_NUM    3
-
-#define RTCIO_GPIO4_CHANNEL         4   //RTCIO_CHANNEL_4
-#define RTCIO_CHANNEL_4_GPIO_NUM    4
-
-#define RTCIO_GPIO5_CHANNEL         5   //RTCIO_CHANNEL_5
-#define RTCIO_CHANNEL_5_GPIO_NUM    5
-
-#define RTCIO_GPIO6_CHANNEL         6   //RTCIO_CHANNEL_6
-#define RTCIO_CHANNEL_6_GPIO_NUM    6
-
-#define RTCIO_GPIO7_CHANNEL         7   //RTCIO_CHANNEL_7
-#define RTCIO_CHANNEL_7_GPIO_NUM    7
diff --git a/components/soc/esp32p4/include/soc/rtc_io_reg.h b/components/soc/esp32p4/include/soc/rtc_io_reg.h
index a687a96dec..c053494821 100644
--- a/components/soc/esp32p4/include/soc/rtc_io_reg.h
+++ b/components/soc/esp32p4/include/soc/rtc_io_reg.h
@@ -5,4 +5,5 @@
  */
 #pragma once
 
-#include "soc/lp_io_reg.h"
+#include "soc/lp_gpio_reg.h"
+#include "soc/lp_iomux_reg.h"
diff --git a/components/soc/esp32p4/include/soc/rtc_io_struct.h b/components/soc/esp32p4/include/soc/rtc_io_struct.h
index 67de8aadad..5e314ff7d8 100644
--- a/components/soc/esp32p4/include/soc/rtc_io_struct.h
+++ b/components/soc/esp32p4/include/soc/rtc_io_struct.h
@@ -5,14 +5,14 @@
  */
 #pragma once
 
-#include "soc/lp_io_struct.h"
+#include "soc/lp_gpio_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef lp_io_dev_t     rtc_io_dev_t;
-#define RTCIO           LP_IO
+typedef lp_gpio_dev_t   rtc_io_dev_t;
+#define RTCIO           LP_GPIO
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/sdio_slave_pins.h b/components/soc/esp32p4/include/soc/sdio_slave_pins.h
deleted file mode 100644
index e7f4d11db2..0000000000
--- a/components/soc/esp32p4/include/soc/sdio_slave_pins.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  18
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  19
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0   20
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1   21
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2   22
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3   23
-#define SDIO_SLAVE_SLOT0_FUNC               0
diff --git a/components/soc/esp32p4/include/soc/sdmmc_pins.h b/components/soc/esp32p4/include/soc/sdmmc_pins.h
index 1399d210fb..2a5810ff32 100644
--- a/components/soc/esp32p4/include/soc/sdmmc_pins.h
+++ b/components/soc/esp32p4/include/soc/sdmmc_pins.h
@@ -1,34 +1,7 @@
-/*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _SOC_SDMMC_PINS_H_
-#define _SOC_SDMMC_PINS_H_
-
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK  39
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD  40
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0   41
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1   42
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2   43
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3   44
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4   45
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5   46
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6   47
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7   48
-#define SDMMC_SLOT0_FUNC               0
-
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK  53
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD  54
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0   55
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1   56
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2   57
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3   58
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D4   59
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D5   60
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D6   61
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D7   62
-#define SDMMC_SLOT1_FUNC               0
-
-#endif /* _SOC_SDMMC_PINS_H_ */
+#pragma once
diff --git a/components/soc/esp32p4/include/soc/slc_reg.h b/components/soc/esp32p4/include/soc/slc_reg.h
deleted file mode 100644
index d47cf53dbe..0000000000
--- a/components/soc/esp32p4/include/soc/slc_reg.h
+++ /dev/null
@@ -1,4301 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SDIO_SLCCONF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCCONF0_REG (DR_REG_SLC_BASE + 0x0)
-/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0;
- *  Set 1 to reset tx fsm in dma slc0.
- */
-#define SDIO_SLC0_TX_RST    (BIT(0))
-#define SDIO_SLC0_TX_RST_M  (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S)
-#define SDIO_SLC0_TX_RST_V  0x00000001U
-#define SDIO_SLC0_TX_RST_S  0
-/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0;
- *  Set 1 to reset rx fsm in dma slc0.
- */
-#define SDIO_SLC0_RX_RST    (BIT(1))
-#define SDIO_SLC0_RX_RST_M  (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S)
-#define SDIO_SLC0_RX_RST_V  0x00000001U
-#define SDIO_SLC0_RX_RST_S  1
-/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0;
- *  reset the command fifo of AHB bus of sdio slave
- */
-#define SDIO_SLC_AHBM_FIFO_RST    (BIT(2))
-#define SDIO_SLC_AHBM_FIFO_RST_M  (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S)
-#define SDIO_SLC_AHBM_FIFO_RST_V  0x00000001U
-#define SDIO_SLC_AHBM_FIFO_RST_S  2
-/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0;
- *  reset the AHB bus of sdio slave
- */
-#define SDIO_SLC_AHBM_RST    (BIT(3))
-#define SDIO_SLC_AHBM_RST_M  (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S)
-#define SDIO_SLC_AHBM_RST_V  0x00000001U
-#define SDIO_SLC_AHBM_RST_S  3
-/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0;
- *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC0_TX_LOOP_TEST    (BIT(4))
-#define SDIO_SLC0_TX_LOOP_TEST_M  (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S)
-#define SDIO_SLC0_TX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC0_TX_LOOP_TEST_S  4
-/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0;
- *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC0_RX_LOOP_TEST    (BIT(5))
-#define SDIO_SLC0_RX_LOOP_TEST_M  (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S)
-#define SDIO_SLC0_RX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC0_RX_LOOP_TEST_S  5
-/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0;
- *  Set 1 to enable change the owner bit of rx link descriptor
- */
-#define SDIO_SLC0_RX_AUTO_WRBACK    (BIT(6))
-#define SDIO_SLC0_RX_AUTO_WRBACK_M  (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S)
-#define SDIO_SLC0_RX_AUTO_WRBACK_V  0x00000001U
-#define SDIO_SLC0_RX_AUTO_WRBACK_S  6
-/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_NO_RESTART_CLR    (BIT(7))
-#define SDIO_SLC0_RX_NO_RESTART_CLR_M  (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S)
-#define SDIO_SLC0_RX_NO_RESTART_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_NO_RESTART_CLR_S  7
-/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1;
- *  0- AHB burst type is single when slave read rx-descriptor from memory through
- *  slc0,1-AHB burst type is not single when slave read rx-descriptor from memory
- *  through slc0
- */
-#define SDIO_SLC0_RXDSCR_BURST_EN    (BIT(8))
-#define SDIO_SLC0_RXDSCR_BURST_EN_M  (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S)
-#define SDIO_SLC0_RXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_RXDSCR_BURST_EN_S  8
-/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1;
- *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
- *  is not single when slave receives data from memory
- */
-#define SDIO_SLC0_RXDATA_BURST_EN    (BIT(9))
-#define SDIO_SLC0_RXDATA_BURST_EN_M  (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S)
-#define SDIO_SLC0_RXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_RXDATA_BURST_EN_S  9
-/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1;
- *  enable the function that when host reading packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC0_RXLINK_AUTO_RET    (BIT(10))
-#define SDIO_SLC0_RXLINK_AUTO_RET_M  (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S)
-#define SDIO_SLC0_RXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC0_RXLINK_AUTO_RET_S  10
-/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1;
- *  enable the function that when host sending packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC0_TXLINK_AUTO_RET    (BIT(11))
-#define SDIO_SLC0_TXLINK_AUTO_RET_M  (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S)
-#define SDIO_SLC0_TXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC0_TXLINK_AUTO_RET_S  11
-/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1;
- *  0- AHB burst type is single when slave read tx-descriptor from memory through
- *  slc0,1-AHB burst type is not single when slave read tx-descriptor from memory
- *  through slc0
- */
-#define SDIO_SLC0_TXDSCR_BURST_EN    (BIT(12))
-#define SDIO_SLC0_TXDSCR_BURST_EN_M  (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S)
-#define SDIO_SLC0_TXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_TXDSCR_BURST_EN_S  12
-/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1;
- *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
- *  single when slave send data to memory
- */
-#define SDIO_SLC0_TXDATA_BURST_EN    (BIT(13))
-#define SDIO_SLC0_TXDATA_BURST_EN_M  (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S)
-#define SDIO_SLC0_TXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_TXDATA_BURST_EN_S  13
-/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1;
- *  auto clear slc0_token1 enable
- */
-#define SDIO_SLC0_TOKEN_AUTO_CLR    (BIT(14))
-#define SDIO_SLC0_TOKEN_AUTO_CLR_M  (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S)
-#define SDIO_SLC0_TOKEN_AUTO_CLR_V  0x00000001U
-#define SDIO_SLC0_TOKEN_AUTO_CLR_S  14
-/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN_SEL    (BIT(15))
-#define SDIO_SLC0_TOKEN_SEL_M  (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S)
-#define SDIO_SLC0_TOKEN_SEL_V  0x00000001U
-#define SDIO_SLC0_TOKEN_SEL_S  15
-/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0;
- *  Set 1 to reset tx fsm in dma slc0.
- */
-#define SDIO_SLC1_TX_RST    (BIT(16))
-#define SDIO_SLC1_TX_RST_M  (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S)
-#define SDIO_SLC1_TX_RST_V  0x00000001U
-#define SDIO_SLC1_TX_RST_S  16
-/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0;
- *  Set 1 to reset rx fsm in dma slc0.
- */
-#define SDIO_SLC1_RX_RST    (BIT(17))
-#define SDIO_SLC1_RX_RST_M  (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S)
-#define SDIO_SLC1_RX_RST_V  0x00000001U
-#define SDIO_SLC1_RX_RST_S  17
-/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_MASK_EN    (BIT(18))
-#define SDIO_SLC0_WR_RETRY_MASK_EN_M  (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S)
-#define SDIO_SLC0_WR_RETRY_MASK_EN_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_MASK_EN_S  18
-/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_MASK_EN    (BIT(19))
-#define SDIO_SLC1_WR_RETRY_MASK_EN_M  (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S)
-#define SDIO_SLC1_WR_RETRY_MASK_EN_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_MASK_EN_S  19
-/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1;
- *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC1_TX_LOOP_TEST    (BIT(20))
-#define SDIO_SLC1_TX_LOOP_TEST_M  (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S)
-#define SDIO_SLC1_TX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC1_TX_LOOP_TEST_S  20
-/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1;
- *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC1_RX_LOOP_TEST    (BIT(21))
-#define SDIO_SLC1_RX_LOOP_TEST_M  (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S)
-#define SDIO_SLC1_RX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC1_RX_LOOP_TEST_S  21
-/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0;
- *  Set 1 to enable change the owner bit of rx link descriptor
- */
-#define SDIO_SLC1_RX_AUTO_WRBACK    (BIT(22))
-#define SDIO_SLC1_RX_AUTO_WRBACK_M  (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S)
-#define SDIO_SLC1_RX_AUTO_WRBACK_V  0x00000001U
-#define SDIO_SLC1_RX_AUTO_WRBACK_S  22
-/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0;
- *  ******* Description ***********
- */
-#define SDIO_SLC1_RX_NO_RESTART_CLR    (BIT(23))
-#define SDIO_SLC1_RX_NO_RESTART_CLR_M  (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S)
-#define SDIO_SLC1_RX_NO_RESTART_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_NO_RESTART_CLR_S  23
-/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1;
- *  0- AHB burst type is single when slave read rx-descriptor from memory through
- *  slc1,1-AHB burst type is not single when slave read rx-descriptor from memory
- *  through slc1
- */
-#define SDIO_SLC1_RXDSCR_BURST_EN    (BIT(24))
-#define SDIO_SLC1_RXDSCR_BURST_EN_M  (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S)
-#define SDIO_SLC1_RXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_RXDSCR_BURST_EN_S  24
-/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1;
- *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
- *  is not single when slave receives data from memory
- */
-#define SDIO_SLC1_RXDATA_BURST_EN    (BIT(25))
-#define SDIO_SLC1_RXDATA_BURST_EN_M  (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S)
-#define SDIO_SLC1_RXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_RXDATA_BURST_EN_S  25
-/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1;
- *  enable the function that when host reading packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC1_RXLINK_AUTO_RET    (BIT(26))
-#define SDIO_SLC1_RXLINK_AUTO_RET_M  (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S)
-#define SDIO_SLC1_RXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC1_RXLINK_AUTO_RET_S  26
-/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1;
- *  enable the function that when host sending packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC1_TXLINK_AUTO_RET    (BIT(27))
-#define SDIO_SLC1_TXLINK_AUTO_RET_M  (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S)
-#define SDIO_SLC1_TXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC1_TXLINK_AUTO_RET_S  27
-/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1;
- *  0- AHB burst type is single when slave read tx-descriptor from memory through
- *  slc1,1-AHB burst type is not single when slave read tx-descriptor from memory
- *  through slc1
- */
-#define SDIO_SLC1_TXDSCR_BURST_EN    (BIT(28))
-#define SDIO_SLC1_TXDSCR_BURST_EN_M  (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S)
-#define SDIO_SLC1_TXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_TXDSCR_BURST_EN_S  28
-/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1;
- *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
- *  single when slave send data to memory
- */
-#define SDIO_SLC1_TXDATA_BURST_EN    (BIT(29))
-#define SDIO_SLC1_TXDATA_BURST_EN_M  (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S)
-#define SDIO_SLC1_TXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_TXDATA_BURST_EN_S  29
-/** SDIO_SLC1_TOKEN_AUTO_CLR : R/W; bitpos: [30]; default: 1;
- *  auto clear slc1_token1 enable
- */
-#define SDIO_SLC1_TOKEN_AUTO_CLR    (BIT(30))
-#define SDIO_SLC1_TOKEN_AUTO_CLR_M  (SDIO_SLC1_TOKEN_AUTO_CLR_V << SDIO_SLC1_TOKEN_AUTO_CLR_S)
-#define SDIO_SLC1_TOKEN_AUTO_CLR_V  0x00000001U
-#define SDIO_SLC1_TOKEN_AUTO_CLR_S  30
-/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN_SEL    (BIT(31))
-#define SDIO_SLC1_TOKEN_SEL_M  (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S)
-#define SDIO_SLC1_TOKEN_SEL_V  0x00000001U
-#define SDIO_SLC1_TOKEN_SEL_S  31
-
-/** SDIO_SLC0INT_RAW_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
-/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M  (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M  (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M  (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M  (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M  (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M  (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M  (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M  (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S  7
-/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_RAW    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_RAW_M  (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S)
-#define SDIO_SLC0_RX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_RAW_S  8
-/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_RAW    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_RAW_M  (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S)
-#define SDIO_SLC0_TX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_RAW_S  9
-/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_RAW    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_RAW_M  (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S)
-#define SDIO_SLC0_RX_UDF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_RAW_S  10
-/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_RAW    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_RAW_M  (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S)
-#define SDIO_SLC0_TX_OVF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_RAW_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M  (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M  (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S  13
-/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit of slc0 finishing receiving data to one buffer
- */
-#define SDIO_SLC0_TX_DONE_INT_RAW    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_RAW_M  (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S)
-#define SDIO_SLC0_TX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_RAW_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit of slc0 finishing receiving data
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M  (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S  15
-/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw interrupt bit of slc0 finishing sending data from one buffer
- */
-#define SDIO_SLC0_RX_DONE_INT_RAW    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_RAW_M  (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S)
-#define SDIO_SLC0_RX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_RAW_S  16
-/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw interrupt bit of slc0 finishing sending data
- */
-#define SDIO_SLC0_RX_EOF_INT_RAW    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_RAW_M  (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S)
-#define SDIO_SLC0_RX_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_RAW_S  17
-/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_RAW    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_RAW_M  (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S)
-#define SDIO_SLC0_TOHOST_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_RAW_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw interrupt bit of slc0 tx link descriptor error
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M  (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw interrupt bit of slc0 rx link descriptor error
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M  (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M  (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M  (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M  (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S  24
-/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_RAW    (BIT(25))
-#define SDIO_CMD_DTC_INT_RAW_M  (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S)
-#define SDIO_CMD_DTC_INT_RAW_V  0x00000001U
-#define SDIO_CMD_DTC_INT_RAW_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M  (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S  27
-/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_RAW    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_RAW_M  (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S)
-#define SDIO_HDA_RECV_DONE_INT_RAW_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_RAW_S  28
-
-/** SDIO_SLC0INT_ST_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
-/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ST    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ST_M  (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ST_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ST    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ST_M  (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ST_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ST    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ST_M  (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ST_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ST    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ST_M  (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ST_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ST    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ST_M  (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ST_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ST    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ST_M  (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ST_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ST    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ST_M  (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ST_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ST    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ST_M  (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ST_S  7
-/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ST    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ST_M  (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S)
-#define SDIO_SLC0_RX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ST_S  8
-/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ST    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ST_M  (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S)
-#define SDIO_SLC0_TX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ST_S  9
-/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ST    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ST_M  (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S)
-#define SDIO_SLC0_RX_UDF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ST_S  10
-/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ST    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ST_M  (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S)
-#define SDIO_SLC0_TX_OVF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ST_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S  13
-/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ST    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ST_M  (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S)
-#define SDIO_SLC0_TX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ST_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M  (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S  15
-/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ST    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ST_M  (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S)
-#define SDIO_SLC0_RX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ST_S  16
-/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ST    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ST_M  (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S)
-#define SDIO_SLC0_RX_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ST_S  17
-/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ST    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ST_M  (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S)
-#define SDIO_SLC0_TOHOST_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ST_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M  (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M  (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S  24
-/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ST    (BIT(25))
-#define SDIO_CMD_DTC_INT_ST_M  (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S)
-#define SDIO_CMD_DTC_INT_ST_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ST_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S  27
-/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ST    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ST_M  (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S)
-#define SDIO_HDA_RECV_DONE_INT_ST_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ST_S  28
-
-/** SDIO_SLC0INT_ENA_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_ENA_REG (DR_REG_SLC_BASE + 0xc)
-/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M  (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M  (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M  (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M  (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M  (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M  (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M  (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M  (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S  7
-/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ENA    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ENA_M  (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S)
-#define SDIO_SLC0_RX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ENA_S  8
-/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ENA    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ENA_M  (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S)
-#define SDIO_SLC0_TX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ENA_S  9
-/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ENA    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ENA_M  (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S)
-#define SDIO_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ENA_S  10
-/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ENA    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ENA_M  (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S)
-#define SDIO_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ENA_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S  13
-/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ENA    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ENA_M  (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S)
-#define SDIO_SLC0_TX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ENA_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M  (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S  15
-/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ENA    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ENA_M  (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S)
-#define SDIO_SLC0_RX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ENA_S  16
-/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ENA    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ENA_M  (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S)
-#define SDIO_SLC0_RX_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ENA_S  17
-/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ENA    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ENA_M  (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S)
-#define SDIO_SLC0_TOHOST_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ENA_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M  (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M  (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S  24
-/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ENA    (BIT(25))
-#define SDIO_CMD_DTC_INT_ENA_M  (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S)
-#define SDIO_CMD_DTC_INT_ENA_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ENA_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S  27
-/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ENA    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ENA_M  (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S)
-#define SDIO_HDA_RECV_DONE_INT_ENA_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ENA_S  28
-
-/** SDIO_SLC0INT_CLR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
-/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M  (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M  (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M  (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M  (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M  (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M  (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M  (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M  (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S  7
-/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_CLR    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_CLR_M  (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S)
-#define SDIO_SLC0_RX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_CLR_S  8
-/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_CLR    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_CLR_M  (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S)
-#define SDIO_SLC0_TX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_CLR_S  9
-/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_CLR    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_CLR_M  (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S)
-#define SDIO_SLC0_RX_UDF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_CLR_S  10
-/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_CLR    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_CLR_M  (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S)
-#define SDIO_SLC0_TX_OVF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_CLR_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M  (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M  (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S  13
-/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_CLR    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_CLR_M  (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S)
-#define SDIO_SLC0_TX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_CLR_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M  (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S  15
-/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_CLR    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_CLR_M  (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S)
-#define SDIO_SLC0_RX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_CLR_S  16
-/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_CLR    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_CLR_M  (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S)
-#define SDIO_SLC0_RX_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_CLR_S  17
-/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_CLR    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_CLR_M  (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S)
-#define SDIO_SLC0_TOHOST_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_CLR_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M  (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M  (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M  (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M  (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M  (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S  24
-/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_CLR    (BIT(25))
-#define SDIO_CMD_DTC_INT_CLR_M  (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S)
-#define SDIO_CMD_DTC_INT_CLR_V  0x00000001U
-#define SDIO_CMD_DTC_INT_CLR_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M  (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S  27
-/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_CLR    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_CLR_M  (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S)
-#define SDIO_HDA_RECV_DONE_INT_CLR_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_CLR_S  28
-
-/** SDIO_SLC1INT_RAW_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_RAW_REG (DR_REG_SLC_BASE + 0x14)
-/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M  (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M  (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M  (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M  (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M  (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M  (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M  (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M  (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S  7
-/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_RAW    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_RAW_M  (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S)
-#define SDIO_SLC1_RX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_RAW_S  8
-/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_RAW    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_RAW_M  (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S)
-#define SDIO_SLC1_TX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_RAW_S  9
-/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_RAW    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_RAW_M  (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S)
-#define SDIO_SLC1_RX_UDF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_RAW_S  10
-/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_RAW    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_RAW_M  (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S)
-#define SDIO_SLC1_TX_OVF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_RAW_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M  (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M  (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S  13
-/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_RAW    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_RAW_M  (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S)
-#define SDIO_SLC1_TX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_RAW_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M  (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S  15
-/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_RAW    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_RAW_M  (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S)
-#define SDIO_SLC1_RX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_RAW_S  16
-/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_RAW    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_RAW_M  (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S)
-#define SDIO_SLC1_RX_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_RAW_S  17
-/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_RAW    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_RAW_M  (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S)
-#define SDIO_SLC1_TOHOST_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_RAW_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M  (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M  (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M  (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M  (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M  (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S  24
-
-/** SDIO_SLC1INT_ST_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ST_REG (DR_REG_SLC_BASE + 0x18)
-/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ST    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ST_M  (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ST_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ST    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ST_M  (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ST_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ST    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ST_M  (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ST_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ST    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ST_M  (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ST_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ST    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ST_M  (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ST_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ST    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ST_M  (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ST_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ST    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ST_M  (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ST_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ST    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ST_M  (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ST_S  7
-/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ST    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ST_M  (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S)
-#define SDIO_SLC1_RX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ST_S  8
-/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ST    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ST_M  (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S)
-#define SDIO_SLC1_TX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ST_S  9
-/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ST    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ST_M  (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S)
-#define SDIO_SLC1_RX_UDF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ST_S  10
-/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ST    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ST_M  (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S)
-#define SDIO_SLC1_TX_OVF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ST_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S  13
-/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ST    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ST_M  (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S)
-#define SDIO_SLC1_TX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ST_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M  (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S  15
-/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ST    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ST_M  (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S)
-#define SDIO_SLC1_RX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ST_S  16
-/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ST    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ST_M  (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S)
-#define SDIO_SLC1_RX_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ST_S  17
-/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ST    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ST_M  (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S)
-#define SDIO_SLC1_TOHOST_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ST_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M  (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M  (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S  24
-
-/** SDIO_SLC1INT_ENA_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ENA_REG (DR_REG_SLC_BASE + 0x1c)
-/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M  (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M  (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M  (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M  (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M  (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M  (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M  (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M  (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S  7
-/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ENA    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ENA_M  (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S)
-#define SDIO_SLC1_RX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ENA_S  8
-/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ENA    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ENA_M  (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S)
-#define SDIO_SLC1_TX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ENA_S  9
-/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ENA    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ENA_M  (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S)
-#define SDIO_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ENA_S  10
-/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ENA    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ENA_M  (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S)
-#define SDIO_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ENA_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S  13
-/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ENA    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ENA_M  (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S)
-#define SDIO_SLC1_TX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ENA_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M  (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S  15
-/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ENA    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ENA_M  (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S)
-#define SDIO_SLC1_RX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ENA_S  16
-/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ENA    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ENA_M  (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S)
-#define SDIO_SLC1_RX_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ENA_S  17
-/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ENA    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ENA_M  (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S)
-#define SDIO_SLC1_TOHOST_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ENA_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M  (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M  (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S  24
-
-/** SDIO_SLC1INT_CLR_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_CLR_REG (DR_REG_SLC_BASE + 0x20)
-/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M  (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M  (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M  (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M  (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M  (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M  (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M  (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M  (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S  7
-/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_CLR    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_CLR_M  (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S)
-#define SDIO_SLC1_RX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_CLR_S  8
-/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_CLR    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_CLR_M  (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S)
-#define SDIO_SLC1_TX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_CLR_S  9
-/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_CLR    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_CLR_M  (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S)
-#define SDIO_SLC1_RX_UDF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_CLR_S  10
-/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_CLR    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_CLR_M  (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S)
-#define SDIO_SLC1_TX_OVF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_CLR_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M  (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M  (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S  13
-/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_CLR    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_CLR_M  (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S)
-#define SDIO_SLC1_TX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_CLR_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M  (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S  15
-/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_CLR    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_CLR_M  (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S)
-#define SDIO_SLC1_RX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_CLR_S  16
-/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_CLR    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_CLR_M  (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S)
-#define SDIO_SLC1_RX_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_CLR_S  17
-/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_CLR    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_CLR_M  (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S)
-#define SDIO_SLC1_TOHOST_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_CLR_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M  (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M  (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M  (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M  (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M  (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S  24
-
-/** SDIO_SLCRX_STATUS_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCRX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
-/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_FULL    (BIT(0))
-#define SDIO_SLC0_RX_FULL_M  (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S)
-#define SDIO_SLC0_RX_FULL_V  0x00000001U
-#define SDIO_SLC0_RX_FULL_S  0
-/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RX_EMPTY    (BIT(1))
-#define SDIO_SLC0_RX_EMPTY_M  (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S)
-#define SDIO_SLC0_RX_EMPTY_V  0x00000001U
-#define SDIO_SLC0_RX_EMPTY_S  1
-/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0;
- *  the current buffer length when slc0 reads data from rx link
- */
-#define SDIO_SLC0_RX_BUF_LEN    0x00003FFFU
-#define SDIO_SLC0_RX_BUF_LEN_M  (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S)
-#define SDIO_SLC0_RX_BUF_LEN_V  0x00003FFFU
-#define SDIO_SLC0_RX_BUF_LEN_S  2
-/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_FULL    (BIT(16))
-#define SDIO_SLC1_RX_FULL_M  (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S)
-#define SDIO_SLC1_RX_FULL_V  0x00000001U
-#define SDIO_SLC1_RX_FULL_S  16
-/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RX_EMPTY    (BIT(17))
-#define SDIO_SLC1_RX_EMPTY_M  (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S)
-#define SDIO_SLC1_RX_EMPTY_V  0x00000001U
-#define SDIO_SLC1_RX_EMPTY_S  17
-/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0;
- *  the current buffer length when slc1 reads data from rx link
- */
-#define SDIO_SLC1_RX_BUF_LEN    0x00003FFFU
-#define SDIO_SLC1_RX_BUF_LEN_M  (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S)
-#define SDIO_SLC1_RX_BUF_LEN_V  0x00003FFFU
-#define SDIO_SLC1_RX_BUF_LEN_S  18
-
-/** SDIO_SLC0RXFIFO_PUSH_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28)
-/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXFIFO_WDATA    0x000001FFU
-#define SDIO_SLC0_RXFIFO_WDATA_M  (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S)
-#define SDIO_SLC0_RXFIFO_WDATA_V  0x000001FFU
-#define SDIO_SLC0_RXFIFO_WDATA_S  0
-/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXFIFO_PUSH    (BIT(16))
-#define SDIO_SLC0_RXFIFO_PUSH_M  (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S)
-#define SDIO_SLC0_RXFIFO_PUSH_V  0x00000001U
-#define SDIO_SLC0_RXFIFO_PUSH_S  16
-
-/** SDIO_SLC1RXFIFO_PUSH_REG register
- *  reserved
- */
-#define SDIO_SLC1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2c)
-/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXFIFO_WDATA    0x000001FFU
-#define SDIO_SLC1_RXFIFO_WDATA_M  (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S)
-#define SDIO_SLC1_RXFIFO_WDATA_V  0x000001FFU
-#define SDIO_SLC1_RXFIFO_WDATA_S  0
-/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXFIFO_PUSH    (BIT(16))
-#define SDIO_SLC1_RXFIFO_PUSH_M  (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S)
-#define SDIO_SLC1_RXFIFO_PUSH_V  0x00000001U
-#define SDIO_SLC1_RXFIFO_PUSH_S  16
-
-/** SDIO_SLCTX_STATUS_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCTX_STATUS_REG (DR_REG_SLC_BASE + 0x30)
-/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_FULL    (BIT(0))
-#define SDIO_SLC0_TX_FULL_M  (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S)
-#define SDIO_SLC0_TX_FULL_V  0x00000001U
-#define SDIO_SLC0_TX_FULL_S  0
-/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_EMPTY    (BIT(1))
-#define SDIO_SLC0_TX_EMPTY_M  (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S)
-#define SDIO_SLC0_TX_EMPTY_V  0x00000001U
-#define SDIO_SLC0_TX_EMPTY_S  1
-/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_FULL    (BIT(16))
-#define SDIO_SLC1_TX_FULL_M  (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S)
-#define SDIO_SLC1_TX_FULL_V  0x00000001U
-#define SDIO_SLC1_TX_FULL_S  16
-/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TX_EMPTY    (BIT(17))
-#define SDIO_SLC1_TX_EMPTY_M  (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S)
-#define SDIO_SLC1_TX_EMPTY_V  0x00000001U
-#define SDIO_SLC1_TX_EMPTY_S  17
-
-/** SDIO_SLC0TXFIFO_POP_REG register
- *  reserved
- */
-#define SDIO_SLC0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34)
-/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024;
- *  reserved
- */
-#define SDIO_SLC0_TXFIFO_RDATA    0x000007FFU
-#define SDIO_SLC0_TXFIFO_RDATA_M  (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S)
-#define SDIO_SLC0_TXFIFO_RDATA_V  0x000007FFU
-#define SDIO_SLC0_TXFIFO_RDATA_S  0
-/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXFIFO_POP    (BIT(16))
-#define SDIO_SLC0_TXFIFO_POP_M  (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S)
-#define SDIO_SLC0_TXFIFO_POP_V  0x00000001U
-#define SDIO_SLC0_TXFIFO_POP_S  16
-
-/** SDIO_SLC1TXFIFO_POP_REG register
- *  reserved
- */
-#define SDIO_SLC1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38)
-/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024;
- *  reserved
- */
-#define SDIO_SLC1_TXFIFO_RDATA    0x000007FFU
-#define SDIO_SLC1_TXFIFO_RDATA_M  (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S)
-#define SDIO_SLC1_TXFIFO_RDATA_V  0x000007FFU
-#define SDIO_SLC1_TXFIFO_RDATA_S  0
-/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXFIFO_POP    (BIT(16))
-#define SDIO_SLC1_TXFIFO_POP_M  (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S)
-#define SDIO_SLC1_TXFIFO_POP_V  0x00000001U
-#define SDIO_SLC1_TXFIFO_POP_S  16
-
-/** SDIO_SLC0RX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC0RX_LINK_REG (DR_REG_SLC_BASE + 0x3c)
-/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_STOP    (BIT(28))
-#define SDIO_SLC0_RXLINK_STOP_M  (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S)
-#define SDIO_SLC0_RXLINK_STOP_V  0x00000001U
-#define SDIO_SLC0_RXLINK_STOP_S  28
-/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_START    (BIT(29))
-#define SDIO_SLC0_RXLINK_START_M  (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S)
-#define SDIO_SLC0_RXLINK_START_V  0x00000001U
-#define SDIO_SLC0_RXLINK_START_S  29
-/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_RESTART    (BIT(30))
-#define SDIO_SLC0_RXLINK_RESTART_M  (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S)
-#define SDIO_SLC0_RXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC0_RXLINK_RESTART_S  30
-/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_PARK    (BIT(31))
-#define SDIO_SLC0_RXLINK_PARK_M  (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S)
-#define SDIO_SLC0_RXLINK_PARK_V  0x00000001U
-#define SDIO_SLC0_RXLINK_PARK_S  31
-
-/** SDIO_SLC0RX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x40)
-/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_ADDR_M  (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S)
-#define SDIO_SLC0_RXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_ADDR_S  0
-
-/** SDIO_SLC0TX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC0TX_LINK_REG (DR_REG_SLC_BASE + 0x44)
-/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_STOP    (BIT(28))
-#define SDIO_SLC0_TXLINK_STOP_M  (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S)
-#define SDIO_SLC0_TXLINK_STOP_V  0x00000001U
-#define SDIO_SLC0_TXLINK_STOP_S  28
-/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_START    (BIT(29))
-#define SDIO_SLC0_TXLINK_START_M  (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S)
-#define SDIO_SLC0_TXLINK_START_V  0x00000001U
-#define SDIO_SLC0_TXLINK_START_S  29
-/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_RESTART    (BIT(30))
-#define SDIO_SLC0_TXLINK_RESTART_M  (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S)
-#define SDIO_SLC0_TXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC0_TXLINK_RESTART_S  30
-/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_PARK    (BIT(31))
-#define SDIO_SLC0_TXLINK_PARK_M  (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S)
-#define SDIO_SLC0_TXLINK_PARK_V  0x00000001U
-#define SDIO_SLC0_TXLINK_PARK_S  31
-
-/** SDIO_SLC0TX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x48)
-/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_ADDR_M  (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S)
-#define SDIO_SLC0_TXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_ADDR_S  0
-
-/** SDIO_SLC1RX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC1RX_LINK_REG (DR_REG_SLC_BASE + 0x4c)
-/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_BT_PACKET    (BIT(20))
-#define SDIO_SLC1_BT_PACKET_M  (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S)
-#define SDIO_SLC1_BT_PACKET_V  0x00000001U
-#define SDIO_SLC1_BT_PACKET_S  20
-/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_STOP    (BIT(28))
-#define SDIO_SLC1_RXLINK_STOP_M  (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S)
-#define SDIO_SLC1_RXLINK_STOP_V  0x00000001U
-#define SDIO_SLC1_RXLINK_STOP_S  28
-/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_START    (BIT(29))
-#define SDIO_SLC1_RXLINK_START_M  (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S)
-#define SDIO_SLC1_RXLINK_START_V  0x00000001U
-#define SDIO_SLC1_RXLINK_START_S  29
-/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_RESTART    (BIT(30))
-#define SDIO_SLC1_RXLINK_RESTART_M  (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S)
-#define SDIO_SLC1_RXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC1_RXLINK_RESTART_S  30
-/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_PARK    (BIT(31))
-#define SDIO_SLC1_RXLINK_PARK_M  (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S)
-#define SDIO_SLC1_RXLINK_PARK_V  0x00000001U
-#define SDIO_SLC1_RXLINK_PARK_S  31
-
-/** SDIO_SLC1RX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x50)
-/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_ADDR_M  (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S)
-#define SDIO_SLC1_RXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_ADDR_S  0
-
-/** SDIO_SLC1TX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC1TX_LINK_REG (DR_REG_SLC_BASE + 0x54)
-/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_STOP    (BIT(28))
-#define SDIO_SLC1_TXLINK_STOP_M  (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S)
-#define SDIO_SLC1_TXLINK_STOP_V  0x00000001U
-#define SDIO_SLC1_TXLINK_STOP_S  28
-/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_START    (BIT(29))
-#define SDIO_SLC1_TXLINK_START_M  (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S)
-#define SDIO_SLC1_TXLINK_START_V  0x00000001U
-#define SDIO_SLC1_TXLINK_START_S  29
-/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_RESTART    (BIT(30))
-#define SDIO_SLC1_TXLINK_RESTART_M  (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S)
-#define SDIO_SLC1_TXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC1_TXLINK_RESTART_S  30
-/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_PARK    (BIT(31))
-#define SDIO_SLC1_TXLINK_PARK_M  (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S)
-#define SDIO_SLC1_TXLINK_PARK_V  0x00000001U
-#define SDIO_SLC1_TXLINK_PARK_S  31
-
-/** SDIO_SLC1TX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x58)
-/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_ADDR_M  (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S)
-#define SDIO_SLC1_TXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_ADDR_S  0
-
-/** SDIO_SLCINTVEC_TOHOST_REG register
- *  reserved
- */
-#define SDIO_SLCINTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x5c)
-/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INTVEC    0x000000FFU
-#define SDIO_SLC0_TOHOST_INTVEC_M  (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S)
-#define SDIO_SLC0_TOHOST_INTVEC_V  0x000000FFU
-#define SDIO_SLC0_TOHOST_INTVEC_S  0
-/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INTVEC    0x000000FFU
-#define SDIO_SLC1_TOHOST_INTVEC_M  (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S)
-#define SDIO_SLC1_TOHOST_INTVEC_V  0x000000FFU
-#define SDIO_SLC1_TOHOST_INTVEC_S  16
-
-/** SDIO_SLC0TOKEN0_REG register
- *  reserved
- */
-#define SDIO_SLC0TOKEN0_REG (DR_REG_SLC_BASE + 0x60)
-/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_WDATA    0x00000FFFU
-#define SDIO_SLC0_TOKEN0_WDATA_M  (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S)
-#define SDIO_SLC0_TOKEN0_WDATA_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN0_WDATA_S  0
-/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_WR    (BIT(12))
-#define SDIO_SLC0_TOKEN0_WR_M  (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S)
-#define SDIO_SLC0_TOKEN0_WR_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_WR_S  12
-/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_INC    (BIT(13))
-#define SDIO_SLC0_TOKEN0_INC_M  (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S)
-#define SDIO_SLC0_TOKEN0_INC_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_INC_S  13
-/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_INC_MORE    (BIT(14))
-#define SDIO_SLC0_TOKEN0_INC_MORE_M  (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S)
-#define SDIO_SLC0_TOKEN0_INC_MORE_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_INC_MORE_S  14
-/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0    0x00000FFFU
-#define SDIO_SLC0_TOKEN0_M  (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S)
-#define SDIO_SLC0_TOKEN0_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN0_S  16
-
-/** SDIO_SLC0TOKEN1_REG register
- *  reserved
- */
-#define SDIO_SLC0TOKEN1_REG (DR_REG_SLC_BASE + 0x64)
-/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0;
- *  slc0 token1 wdata
- */
-#define SDIO_SLC0_TOKEN1_WDATA    0x00000FFFU
-#define SDIO_SLC0_TOKEN1_WDATA_M  (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S)
-#define SDIO_SLC0_TOKEN1_WDATA_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN1_WDATA_S  0
-/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0;
- *  update slc0_token1_wdata into slc0 token1
- */
-#define SDIO_SLC0_TOKEN1_WR    (BIT(12))
-#define SDIO_SLC0_TOKEN1_WR_M  (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S)
-#define SDIO_SLC0_TOKEN1_WR_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_WR_S  12
-/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0;
- *  slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1
- */
-#define SDIO_SLC0_TOKEN1_INC    (BIT(13))
-#define SDIO_SLC0_TOKEN1_INC_M  (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S)
-#define SDIO_SLC0_TOKEN1_INC_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_INC_S  13
-/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0;
- *  slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add
- *  slc0_token1_wdata to slc0_token1
- */
-#define SDIO_SLC0_TOKEN1_INC_MORE    (BIT(14))
-#define SDIO_SLC0_TOKEN1_INC_MORE_M  (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S)
-#define SDIO_SLC0_TOKEN1_INC_MORE_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_INC_MORE_S  14
-/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1    0x00000FFFU
-#define SDIO_SLC0_TOKEN1_M  (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S)
-#define SDIO_SLC0_TOKEN1_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN1_S  16
-
-/** SDIO_SLC1TOKEN0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1TOKEN0_REG (DR_REG_SLC_BASE + 0x68)
-/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_WDATA    0x00000FFFU
-#define SDIO_SLC1_TOKEN0_WDATA_M  (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S)
-#define SDIO_SLC1_TOKEN0_WDATA_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN0_WDATA_S  0
-/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_WR    (BIT(12))
-#define SDIO_SLC1_TOKEN0_WR_M  (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S)
-#define SDIO_SLC1_TOKEN0_WR_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_WR_S  12
-/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0;
- *  Add 1 to  slc1_token0
- */
-#define SDIO_SLC1_TOKEN0_INC    (BIT(13))
-#define SDIO_SLC1_TOKEN0_INC_M  (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S)
-#define SDIO_SLC1_TOKEN0_INC_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_INC_S  13
-/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0;
- *  Add  slc1_token0_wdata to  slc1_token0
- */
-#define SDIO_SLC1_TOKEN0_INC_MORE    (BIT(14))
-#define SDIO_SLC1_TOKEN0_INC_MORE_M  (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S)
-#define SDIO_SLC1_TOKEN0_INC_MORE_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_INC_MORE_S  14
-/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0    0x00000FFFU
-#define SDIO_SLC1_TOKEN0_M  (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S)
-#define SDIO_SLC1_TOKEN0_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN0_S  16
-
-/** SDIO_SLC1TOKEN1_REG register
- *  reserved
- */
-#define SDIO_SLC1TOKEN1_REG (DR_REG_SLC_BASE + 0x6c)
-/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_WDATA    0x00000FFFU
-#define SDIO_SLC1_TOKEN1_WDATA_M  (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S)
-#define SDIO_SLC1_TOKEN1_WDATA_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN1_WDATA_S  0
-/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0;
- *  update slc1_token1_wdata into slc1 token1
- */
-#define SDIO_SLC1_TOKEN1_WR    (BIT(12))
-#define SDIO_SLC1_TOKEN1_WR_M  (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S)
-#define SDIO_SLC1_TOKEN1_WR_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_WR_S  12
-/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_INC    (BIT(13))
-#define SDIO_SLC1_TOKEN1_INC_M  (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S)
-#define SDIO_SLC1_TOKEN1_INC_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_INC_S  13
-/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_INC_MORE    (BIT(14))
-#define SDIO_SLC1_TOKEN1_INC_MORE_M  (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S)
-#define SDIO_SLC1_TOKEN1_INC_MORE_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_INC_MORE_S  14
-/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1    0x00000FFFU
-#define SDIO_SLC1_TOKEN1_M  (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S)
-#define SDIO_SLC1_TOKEN1_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN1_S  16
-
-/** SDIO_SLCCONF1_REG register
- *  reserved
- */
-#define SDIO_SLCCONF1_REG (DR_REG_SLC_BASE + 0x70)
-/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_CHECK_OWNER    (BIT(0))
-#define SDIO_SLC0_CHECK_OWNER_M  (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S)
-#define SDIO_SLC0_CHECK_OWNER_V  0x00000001U
-#define SDIO_SLC0_CHECK_OWNER_S  0
-/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_CHECK_SUM_EN    (BIT(1))
-#define SDIO_SLC0_TX_CHECK_SUM_EN_M  (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S)
-#define SDIO_SLC0_TX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC0_TX_CHECK_SUM_EN_S  1
-/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_CHECK_SUM_EN    (BIT(2))
-#define SDIO_SLC0_RX_CHECK_SUM_EN_M  (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S)
-#define SDIO_SLC0_RX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC0_RX_CHECK_SUM_EN_S  2
-/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1;
- *  reserved
- */
-#define SDIO_SDIO_CMD_HOLD_EN    (BIT(3))
-#define SDIO_SDIO_CMD_HOLD_EN_M  (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S)
-#define SDIO_SDIO_CMD_HOLD_EN_V  0x00000001U
-#define SDIO_SDIO_CMD_HOLD_EN_S  3
-/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_LEN_AUTO_CLR    (BIT(4))
-#define SDIO_SLC0_LEN_AUTO_CLR_M  (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S)
-#define SDIO_SLC0_LEN_AUTO_CLR_V  0x00000001U
-#define SDIO_SLC0_LEN_AUTO_CLR_S  4
-/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_STITCH_EN    (BIT(5))
-#define SDIO_SLC0_TX_STITCH_EN_M  (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S)
-#define SDIO_SLC0_TX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC0_TX_STITCH_EN_S  5
-/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RX_STITCH_EN    (BIT(6))
-#define SDIO_SLC0_RX_STITCH_EN_M  (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S)
-#define SDIO_SLC0_RX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC0_RX_STITCH_EN_S  6
-/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_CHECK_OWNER    (BIT(16))
-#define SDIO_SLC1_CHECK_OWNER_M  (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S)
-#define SDIO_SLC1_CHECK_OWNER_V  0x00000001U
-#define SDIO_SLC1_CHECK_OWNER_S  16
-/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_CHECK_SUM_EN    (BIT(17))
-#define SDIO_SLC1_TX_CHECK_SUM_EN_M  (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S)
-#define SDIO_SLC1_TX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC1_TX_CHECK_SUM_EN_S  17
-/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_CHECK_SUM_EN    (BIT(18))
-#define SDIO_SLC1_RX_CHECK_SUM_EN_M  (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S)
-#define SDIO_SLC1_RX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC1_RX_CHECK_SUM_EN_S  18
-/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_HOST_INT_LEVEL_SEL    (BIT(19))
-#define SDIO_HOST_INT_LEVEL_SEL_M  (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S)
-#define SDIO_HOST_INT_LEVEL_SEL_V  0x00000001U
-#define SDIO_HOST_INT_LEVEL_SEL_S  19
-/** SDIO_SLC1_TX_STITCH_EN : R/W; bitpos: [20]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TX_STITCH_EN    (BIT(20))
-#define SDIO_SLC1_TX_STITCH_EN_M  (SDIO_SLC1_TX_STITCH_EN_V << SDIO_SLC1_TX_STITCH_EN_S)
-#define SDIO_SLC1_TX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC1_TX_STITCH_EN_S  20
-/** SDIO_SLC1_RX_STITCH_EN : R/W; bitpos: [21]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RX_STITCH_EN    (BIT(21))
-#define SDIO_SLC1_RX_STITCH_EN_M  (SDIO_SLC1_RX_STITCH_EN_V << SDIO_SLC1_RX_STITCH_EN_S)
-#define SDIO_SLC1_RX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC1_RX_STITCH_EN_S  21
-/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_CLK_EN    (BIT(22))
-#define SDIO_SDIO_CLK_EN_M  (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S)
-#define SDIO_SDIO_CLK_EN_V  0x00000001U
-#define SDIO_SDIO_CLK_EN_S  22
-
-/** SDIO_SLC0_STATE0_REG register
- *  reserved
- */
-#define SDIO_SLC0_STATE0_REG (DR_REG_SLC_BASE + 0x74)
-/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_STATE0    0xFFFFFFFFU
-#define SDIO_SLC0_STATE0_M  (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S)
-#define SDIO_SLC0_STATE0_V  0xFFFFFFFFU
-#define SDIO_SLC0_STATE0_S  0
-
-/** SDIO_SLC0_STATE1_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_STATE1_REG (DR_REG_SLC_BASE + 0x78)
-/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0;
- *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
- *  rx_link fsm state, [30:24] rx_fifo_cnt
- */
-#define SDIO_SLC0_STATE1    0xFFFFFFFFU
-#define SDIO_SLC0_STATE1_M  (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S)
-#define SDIO_SLC0_STATE1_V  0xFFFFFFFFU
-#define SDIO_SLC0_STATE1_S  0
-
-/** SDIO_SLC1_STATE0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_STATE0_REG (DR_REG_SLC_BASE + 0x7c)
-/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_STATE0    0xFFFFFFFFU
-#define SDIO_SLC1_STATE0_M  (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S)
-#define SDIO_SLC1_STATE0_V  0xFFFFFFFFU
-#define SDIO_SLC1_STATE0_S  0
-
-/** SDIO_SLC1_STATE1_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_STATE1_REG (DR_REG_SLC_BASE + 0x80)
-/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0;
- *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
- *  rx_link fsm state, [30:24] rx_fifo_cnt
- */
-#define SDIO_SLC1_STATE1    0xFFFFFFFFU
-#define SDIO_SLC1_STATE1_M  (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S)
-#define SDIO_SLC1_STATE1_V  0xFFFFFFFFU
-#define SDIO_SLC1_STATE1_S  0
-
-/** SDIO_SLCBRIDGE_CONF_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCBRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x84)
-/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32;
- *  reserved
- */
-#define SDIO_SLC_TXEOF_ENA    0x0000003FU
-#define SDIO_SLC_TXEOF_ENA_M  (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S)
-#define SDIO_SLC_TXEOF_ENA_V  0x0000003FU
-#define SDIO_SLC_TXEOF_ENA_S  0
-/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7;
- *  reserved
- */
-#define SDIO_SLC_FIFO_MAP_ENA    0x0000000FU
-#define SDIO_SLC_FIFO_MAP_ENA_M  (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S)
-#define SDIO_SLC_FIFO_MAP_ENA_V  0x0000000FU
-#define SDIO_SLC_FIFO_MAP_ENA_S  8
-/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_DUMMY_MODE    (BIT(12))
-#define SDIO_SLC0_TX_DUMMY_MODE_M  (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S)
-#define SDIO_SLC0_TX_DUMMY_MODE_V  0x00000001U
-#define SDIO_SLC0_TX_DUMMY_MODE_S  12
-/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1;
- *  reserved
- */
-#define SDIO_SLC_HDA_MAP_128K    (BIT(13))
-#define SDIO_SLC_HDA_MAP_128K_M  (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S)
-#define SDIO_SLC_HDA_MAP_128K_V  0x00000001U
-#define SDIO_SLC_HDA_MAP_128K_S  13
-/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TX_DUMMY_MODE    (BIT(14))
-#define SDIO_SLC1_TX_DUMMY_MODE_M  (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S)
-#define SDIO_SLC1_TX_DUMMY_MODE_V  0x00000001U
-#define SDIO_SLC1_TX_DUMMY_MODE_S  14
-/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10;
- *  reserved
- */
-#define SDIO_SLC_TX_PUSH_IDLE_NUM    0x0000FFFFU
-#define SDIO_SLC_TX_PUSH_IDLE_NUM_M  (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S)
-#define SDIO_SLC_TX_PUSH_IDLE_NUM_V  0x0000FFFFU
-#define SDIO_SLC_TX_PUSH_IDLE_NUM_S  16
-
-/** SDIO_SLC0_TO_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88)
-/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_DES_ADDR_M  (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S)
-#define SDIO_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC0_TX_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8c)
-/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M  (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S)
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x90)
-/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M  (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S)
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S  0
-
-/** SDIO_SLC1_TO_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x94)
-/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_DES_ADDR_M  (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S)
-#define SDIO_SLC1_TO_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC1_TX_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x98)
-/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M  (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S)
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x9c)
-/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M  (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S)
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S  0
-
-/** SDIO_SLC_AHB_TEST_REG register
- *  reserved
- */
-#define SDIO_SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0xa0)
-/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_AHB_TESTMODE    0x00000007U
-#define SDIO_SLC_AHB_TESTMODE_M  (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S)
-#define SDIO_SLC_AHB_TESTMODE_V  0x00000007U
-#define SDIO_SLC_AHB_TESTMODE_S  0
-/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_AHB_TESTADDR    0x00000003U
-#define SDIO_SLC_AHB_TESTADDR_M  (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S)
-#define SDIO_SLC_AHB_TESTADDR_V  0x00000003U
-#define SDIO_SLC_AHB_TESTADDR_S  4
-
-/** SDIO_SLC_SDIO_ST_REG register
- *  reserved
- */
-#define SDIO_SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0xa4)
-/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_ST    0x00000007U
-#define SDIO_CMD_ST_M  (SDIO_CMD_ST_V << SDIO_CMD_ST_S)
-#define SDIO_CMD_ST_V  0x00000007U
-#define SDIO_CMD_ST_S  0
-/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0;
- *  reserved
- */
-#define SDIO_FUNC_ST    0x0000000FU
-#define SDIO_FUNC_ST_M  (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S)
-#define SDIO_FUNC_ST_V  0x0000000FU
-#define SDIO_FUNC_ST_S  4
-/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_WAKEUP    (BIT(8))
-#define SDIO_SDIO_WAKEUP_M  (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S)
-#define SDIO_SDIO_WAKEUP_V  0x00000001U
-#define SDIO_SDIO_WAKEUP_S  8
-/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0;
- *  reserved
- */
-#define SDIO_BUS_ST    0x00000007U
-#define SDIO_BUS_ST_M  (SDIO_BUS_ST_V << SDIO_BUS_ST_S)
-#define SDIO_BUS_ST_V  0x00000007U
-#define SDIO_BUS_ST_S  12
-/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0;
- *  reserved
- */
-#define SDIO_FUNC1_ACC_STATE    0x0000001FU
-#define SDIO_FUNC1_ACC_STATE_M  (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S)
-#define SDIO_FUNC1_ACC_STATE_V  0x0000001FU
-#define SDIO_FUNC1_ACC_STATE_S  16
-/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0;
- *  reserved
- */
-#define SDIO_FUNC2_ACC_STATE    0x0000001FU
-#define SDIO_FUNC2_ACC_STATE_M  (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S)
-#define SDIO_FUNC2_ACC_STATE_V  0x0000001FU
-#define SDIO_FUNC2_ACC_STATE_S  24
-
-/** SDIO_SLC_RX_DSCR_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xa8)
-/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN_NO_REPLACE    (BIT(0))
-#define SDIO_SLC0_TOKEN_NO_REPLACE_M  (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S)
-#define SDIO_SLC0_TOKEN_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC0_TOKEN_NO_REPLACE_S  0
-/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_INFOR_NO_REPLACE    (BIT(1))
-#define SDIO_SLC0_INFOR_NO_REPLACE_M  (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S)
-#define SDIO_SLC0_INFOR_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC0_INFOR_NO_REPLACE_S  1
-/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0;
- *  slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next
- *  pop doesn't occur after 255 cycles since the current pop
- */
-#define SDIO_SLC0_RX_FILL_MODE    (BIT(2))
-#define SDIO_SLC0_RX_FILL_MODE_M  (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S)
-#define SDIO_SLC0_RX_FILL_MODE_V  0x00000001U
-#define SDIO_SLC0_RX_FILL_MODE_S  2
-/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1;
- *  0-slc0 rx_push_eof, 1-slc0 rx_pop_eof
- */
-#define SDIO_SLC0_RX_EOF_MODE    (BIT(3))
-#define SDIO_SLC0_RX_EOF_MODE_M  (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S)
-#define SDIO_SLC0_RX_EOF_MODE_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_MODE_S  3
-/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RX_FILL_EN    (BIT(4))
-#define SDIO_SLC0_RX_FILL_EN_M  (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S)
-#define SDIO_SLC0_RX_FILL_EN_V  0x00000001U
-#define SDIO_SLC0_RX_FILL_EN_S  4
-/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128;
- *  reserved
- */
-#define SDIO_SLC0_RD_RETRY_THRESHOLD    0x000007FFU
-#define SDIO_SLC0_RD_RETRY_THRESHOLD_M  (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S)
-#define SDIO_SLC0_RD_RETRY_THRESHOLD_V  0x000007FFU
-#define SDIO_SLC0_RD_RETRY_THRESHOLD_S  5
-/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN_NO_REPLACE    (BIT(16))
-#define SDIO_SLC1_TOKEN_NO_REPLACE_M  (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S)
-#define SDIO_SLC1_TOKEN_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC1_TOKEN_NO_REPLACE_S  16
-/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_INFOR_NO_REPLACE    (BIT(17))
-#define SDIO_SLC1_INFOR_NO_REPLACE_M  (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S)
-#define SDIO_SLC1_INFOR_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC1_INFOR_NO_REPLACE_S  17
-/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0;
- *  slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next
- *  pop doesn't occur after 255 cycles since the current pop
- */
-#define SDIO_SLC1_RX_FILL_MODE    (BIT(18))
-#define SDIO_SLC1_RX_FILL_MODE_M  (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S)
-#define SDIO_SLC1_RX_FILL_MODE_V  0x00000001U
-#define SDIO_SLC1_RX_FILL_MODE_S  18
-/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1;
- *  0-slc1 rx_push_eof, 1-slc1 rx_pop_eof
- */
-#define SDIO_SLC1_RX_EOF_MODE    (BIT(19))
-#define SDIO_SLC1_RX_EOF_MODE_M  (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S)
-#define SDIO_SLC1_RX_EOF_MODE_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_MODE_S  19
-/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RX_FILL_EN    (BIT(20))
-#define SDIO_SLC1_RX_FILL_EN_M  (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S)
-#define SDIO_SLC1_RX_FILL_EN_V  0x00000001U
-#define SDIO_SLC1_RX_FILL_EN_S  20
-/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128;
- *  reserved
- */
-#define SDIO_SLC1_RD_RETRY_THRESHOLD    0x000007FFU
-#define SDIO_SLC1_RD_RETRY_THRESHOLD_M  (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S)
-#define SDIO_SLC1_RD_RETRY_THRESHOLD_V  0x000007FFU
-#define SDIO_SLC1_RD_RETRY_THRESHOLD_S  21
-
-/** SDIO_SLC0_TXLINK_DSCR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xac)
-/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_M  (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S)
-#define SDIO_SLC0_TXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_S  0
-
-/** SDIO_SLC0_TXLINK_DSCR_BF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xb0)
-/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF0_M  (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S)
-#define SDIO_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC0_TXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xb4)
-/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF1_M  (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S)
-#define SDIO_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC0_RXLINK_DSCR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xb8)
-/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  the third word of slc0 link descriptor, or known as the next descriptor address
- */
-#define SDIO_SLC0_RXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_M  (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S)
-#define SDIO_SLC0_RXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_S  0
-
-/** SDIO_SLC0_RXLINK_DSCR_BF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xbc)
-/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF0_M  (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S)
-#define SDIO_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC0_RXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xc0)
-/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF1_M  (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S)
-#define SDIO_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC1_TXLINK_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xc4)
-/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_M  (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S)
-#define SDIO_SLC1_TXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_S  0
-
-/** SDIO_SLC1_TXLINK_DSCR_BF0_REG register
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xc8)
-/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF0_M  (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S)
-#define SDIO_SLC1_TXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC1_TXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xcc)
-/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF1_M  (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S)
-#define SDIO_SLC1_TXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC1_RXLINK_DSCR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xd0)
-/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  the third word of slc1 link descriptor, or known as the next descriptor address
- */
-#define SDIO_SLC1_RXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_M  (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S)
-#define SDIO_SLC1_RXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_S  0
-
-/** SDIO_SLC1_RXLINK_DSCR_BF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xd4)
-/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF0_M  (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S)
-#define SDIO_SLC1_RXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC1_RXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xd8)
-/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF1_M  (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S)
-#define SDIO_SLC1_RXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC0_TX_ERREOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xdc)
-/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M  (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S)
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC1_TX_ERREOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xe0)
-/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M  (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S)
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC_TOKEN_LAT_REG register
- *  reserved
- */
-#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xe4)
-/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN    0x00000FFFU
-#define SDIO_SLC0_TOKEN_M  (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S)
-#define SDIO_SLC0_TOKEN_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN_S  0
-/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN    0x00000FFFU
-#define SDIO_SLC1_TOKEN_M  (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S)
-#define SDIO_SLC1_TOKEN_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN_S  16
-
-/** SDIO_SLC_TX_DSCR_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xe8)
-/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128;
- *  reserved
- */
-#define SDIO_SLC_WR_RETRY_THRESHOLD    0x000007FFU
-#define SDIO_SLC_WR_RETRY_THRESHOLD_M  (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S)
-#define SDIO_SLC_WR_RETRY_THRESHOLD_V  0x000007FFU
-#define SDIO_SLC_WR_RETRY_THRESHOLD_S  0
-
-/** SDIO_SLC_CMD_INFOR0_REG register
- *  reserved
- */
-#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xec)
-/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_CONTENT0    0xFFFFFFFFU
-#define SDIO_CMD_CONTENT0_M  (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S)
-#define SDIO_CMD_CONTENT0_V  0xFFFFFFFFU
-#define SDIO_CMD_CONTENT0_S  0
-
-/** SDIO_SLC_CMD_INFOR1_REG register
- *  reserved
- */
-#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xf0)
-/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_CONTENT1    0xFFFFFFFFU
-#define SDIO_CMD_CONTENT1_M  (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S)
-#define SDIO_CMD_CONTENT1_V  0xFFFFFFFFU
-#define SDIO_CMD_CONTENT1_S  0
-
-/** SDIO_SLC0_LEN_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xf4)
-/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_WDATA    0x000FFFFFU
-#define SDIO_SLC0_LEN_WDATA_M  (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S)
-#define SDIO_SLC0_LEN_WDATA_V  0x000FFFFFU
-#define SDIO_SLC0_LEN_WDATA_S  0
-/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_WR    (BIT(20))
-#define SDIO_SLC0_LEN_WR_M  (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S)
-#define SDIO_SLC0_LEN_WR_V  0x00000001U
-#define SDIO_SLC0_LEN_WR_S  20
-/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_INC    (BIT(21))
-#define SDIO_SLC0_LEN_INC_M  (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S)
-#define SDIO_SLC0_LEN_INC_V  0x00000001U
-#define SDIO_SLC0_LEN_INC_S  21
-/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_INC_MORE    (BIT(22))
-#define SDIO_SLC0_LEN_INC_MORE_M  (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S)
-#define SDIO_SLC0_LEN_INC_MORE_V  0x00000001U
-#define SDIO_SLC0_LEN_INC_MORE_S  22
-/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PACKET_LOAD_EN    (BIT(23))
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_M  (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S)
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_V  0x00000001U
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_S  23
-/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PACKET_LOAD_EN    (BIT(24))
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_M  (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S)
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_V  0x00000001U
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_S  24
-/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_GET_USED_DSCR    (BIT(25))
-#define SDIO_SLC0_RX_GET_USED_DSCR_M  (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S)
-#define SDIO_SLC0_RX_GET_USED_DSCR_V  0x00000001U
-#define SDIO_SLC0_RX_GET_USED_DSCR_S  25
-/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_GET_USED_DSCR    (BIT(26))
-#define SDIO_SLC0_TX_GET_USED_DSCR_M  (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S)
-#define SDIO_SLC0_TX_GET_USED_DSCR_V  0x00000001U
-#define SDIO_SLC0_TX_GET_USED_DSCR_S  26
-/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_NEW_PKT_IND    (BIT(27))
-#define SDIO_SLC0_RX_NEW_PKT_IND_M  (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S)
-#define SDIO_SLC0_RX_NEW_PKT_IND_V  0x00000001U
-#define SDIO_SLC0_RX_NEW_PKT_IND_S  27
-/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_NEW_PKT_IND    (BIT(28))
-#define SDIO_SLC0_TX_NEW_PKT_IND_M  (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S)
-#define SDIO_SLC0_TX_NEW_PKT_IND_V  0x00000001U
-#define SDIO_SLC0_TX_NEW_PKT_IND_S  28
-/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST    (BIT(29))
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M  (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S)
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V  0x00000001U
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S  29
-/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST    (BIT(30))
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M  (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S)
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V  0x00000001U
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S  30
-
-/** SDIO_SLC0_LENGTH_REG register
- *  reserved
- */
-#define SDIO_SLC0_LENGTH_REG (DR_REG_SLC_BASE + 0xf8)
-/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN    0x000FFFFFU
-#define SDIO_SLC0_LEN_M  (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S)
-#define SDIO_SLC0_LEN_V  0x000FFFFFU
-#define SDIO_SLC0_LEN_S  0
-
-/** SDIO_SLC0_TXPKT_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xfc)
-/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_TXPKT_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x100)
-/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKT_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0x104)
-/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKT_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x108)
-/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_TXPKTU_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x10c)
-/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_TXPKTU_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x110)
-/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKTU_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x114)
-/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKTU_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x118)
-/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S  0
-
-/** SDIO_SLC_SEQ_POSITION_REG register
- *  reserved
- */
-#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x11c)
-/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9;
- *  reserved
- */
-#define SDIO_SLC0_SEQ_POSITION    0x000000FFU
-#define SDIO_SLC0_SEQ_POSITION_M  (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S)
-#define SDIO_SLC0_SEQ_POSITION_V  0x000000FFU
-#define SDIO_SLC0_SEQ_POSITION_S  0
-/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5;
- *  reserved
- */
-#define SDIO_SLC1_SEQ_POSITION    0x000000FFU
-#define SDIO_SLC1_SEQ_POSITION_M  (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S)
-#define SDIO_SLC1_SEQ_POSITION_V  0x000000FFU
-#define SDIO_SLC1_SEQ_POSITION_S  8
-
-/** SDIO_SLC0_DSCR_REC_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x120)
-/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_REC_LIM    0x000003FFU
-#define SDIO_SLC0_RX_DSCR_REC_LIM_M  (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S)
-#define SDIO_SLC0_RX_DSCR_REC_LIM_V  0x000003FFU
-#define SDIO_SLC0_RX_DSCR_REC_LIM_S  0
-
-/** SDIO_SLC_SDIO_CRC_ST0_REG register
- *  reserved
- */
-#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x124)
-/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define SDIO_DAT0_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT0_CRC_ERR_CNT_M  (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S)
-#define SDIO_DAT0_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT0_CRC_ERR_CNT_S  0
-/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0;
- *  reserved
- */
-#define SDIO_DAT1_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT1_CRC_ERR_CNT_M  (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S)
-#define SDIO_DAT1_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT1_CRC_ERR_CNT_S  8
-/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0;
- *  reserved
- */
-#define SDIO_DAT2_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT2_CRC_ERR_CNT_M  (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S)
-#define SDIO_DAT2_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT2_CRC_ERR_CNT_S  16
-/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define SDIO_DAT3_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT3_CRC_ERR_CNT_M  (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S)
-#define SDIO_DAT3_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT3_CRC_ERR_CNT_S  24
-
-/** SDIO_SLC_SDIO_CRC_ST1_REG register
- *  reserved
- */
-#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x128)
-/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_CRC_ERR_CNT    0x000000FFU
-#define SDIO_CMD_CRC_ERR_CNT_M  (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S)
-#define SDIO_CMD_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_CMD_CRC_ERR_CNT_S  0
-/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0;
- *  reserved
- */
-#define SDIO_ERR_CNT_CLR    (BIT(31))
-#define SDIO_ERR_CNT_CLR_M  (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S)
-#define SDIO_ERR_CNT_CLR_V  0x00000001U
-#define SDIO_ERR_CNT_CLR_S  31
-
-/** SDIO_SLC0_EOF_START_DES_REG register
- *  reserved
- */
-#define SDIO_SLC0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x12c)
-/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_EOF_START_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_EOF_START_DES_ADDR_M  (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S)
-#define SDIO_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_EOF_START_DES_ADDR_S  0
-
-/** SDIO_SLC0_PUSH_DSCR_ADDR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x130)
-/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
- */
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M  (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_DONE_DSCR_ADDR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x134)
-/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  the current descriptor address when slc0 finishes reading data from one buffer,
- *  aligned with word
- */
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M  (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_SUB_START_DES_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x138)
-/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
- */
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M  (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S)
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_DSCR_CNT_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x13c)
-/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0;
- *  the number of descriptors got by slc0 when it tries to read data from memory
- */
-#define SDIO_SLC0_RX_DSCR_CNT_LAT    0x000003FFU
-#define SDIO_SLC0_RX_DSCR_CNT_LAT_M  (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S)
-#define SDIO_SLC0_RX_DSCR_CNT_LAT_V  0x000003FFU
-#define SDIO_SLC0_RX_DSCR_CNT_LAT_S  0
-/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_GET_EOF_OCC    (BIT(16))
-#define SDIO_SLC0_RX_GET_EOF_OCC_M  (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S)
-#define SDIO_SLC0_RX_GET_EOF_OCC_V  0x00000001U
-#define SDIO_SLC0_RX_GET_EOF_OCC_S  16
-
-/** SDIO_SLC0_LEN_LIM_CONF_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x140)
-/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504;
- *  reserved
- */
-#define SDIO_SLC0_LEN_LIM    0x000FFFFFU
-#define SDIO_SLC0_LEN_LIM_M  (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S)
-#define SDIO_SLC0_LEN_LIM_V  0x000FFFFFU
-#define SDIO_SLC0_LEN_LIM_S  0
-
-/** SDIO_SLC0INT_ST1_REG register
- *  reserved
- */
-#define SDIO_SLC0INT_ST1_REG (DR_REG_SLC_BASE + 0x144)
-/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M  (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M  (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M  (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M  (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M  (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M  (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M  (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M  (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S  7
-/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ST1    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ST1_M  (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S)
-#define SDIO_SLC0_RX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ST1_S  8
-/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ST1    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ST1_M  (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S)
-#define SDIO_SLC0_TX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ST1_S  9
-/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ST1    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ST1_M  (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S)
-#define SDIO_SLC0_RX_UDF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ST1_S  10
-/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ST1    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ST1_M  (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S)
-#define SDIO_SLC0_TX_OVF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ST1_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S  13
-/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ST1    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ST1_M  (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S)
-#define SDIO_SLC0_TX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ST1_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M  (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S  15
-/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ST1    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ST1_M  (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S)
-#define SDIO_SLC0_RX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ST1_S  16
-/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ST1    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ST1_M  (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S)
-#define SDIO_SLC0_RX_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ST1_S  17
-/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ST1    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ST1_M  (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S)
-#define SDIO_SLC0_TOHOST_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ST1_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M  (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M  (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S  24
-/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ST1    (BIT(25))
-#define SDIO_CMD_DTC_INT_ST1_M  (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S)
-#define SDIO_CMD_DTC_INT_ST1_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ST1_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S  27
-/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ST1    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ST1_M  (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S)
-#define SDIO_HDA_RECV_DONE_INT_ST1_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ST1_S  28
-
-/** SDIO_SLC0INT_ENA1_REG register
- *  reserved
- */
-#define SDIO_SLC0INT_ENA1_REG (DR_REG_SLC_BASE + 0x148)
-/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S  7
-/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ENA1    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ENA1_M  (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S)
-#define SDIO_SLC0_RX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ENA1_S  8
-/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ENA1    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ENA1_M  (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S)
-#define SDIO_SLC0_TX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ENA1_S  9
-/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ENA1    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ENA1_M  (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S)
-#define SDIO_SLC0_RX_UDF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ENA1_S  10
-/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ENA1    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ENA1_M  (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S)
-#define SDIO_SLC0_TX_OVF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ENA1_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
-/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ENA1    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ENA1_M  (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S)
-#define SDIO_SLC0_TX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ENA1_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M  (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S  15
-/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ENA1    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ENA1_M  (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S)
-#define SDIO_SLC0_RX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ENA1_S  16
-/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ENA1    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ENA1_M  (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S)
-#define SDIO_SLC0_RX_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ENA1_S  17
-/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ENA1    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ENA1_M  (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S)
-#define SDIO_SLC0_TOHOST_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ENA1_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M  (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M  (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S  24
-/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ENA1    (BIT(25))
-#define SDIO_CMD_DTC_INT_ENA1_M  (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S)
-#define SDIO_CMD_DTC_INT_ENA1_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ENA1_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S  27
-/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ENA1    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ENA1_M  (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S)
-#define SDIO_HDA_RECV_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ENA1_S  28
-
-/** SDIO_SLC1INT_ST1_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ST1_REG (DR_REG_SLC_BASE + 0x14c)
-/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M  (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M  (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M  (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M  (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M  (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M  (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M  (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M  (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S  7
-/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ST1    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ST1_M  (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S)
-#define SDIO_SLC1_RX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ST1_S  8
-/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ST1    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ST1_M  (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S)
-#define SDIO_SLC1_TX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ST1_S  9
-/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ST1    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ST1_M  (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S)
-#define SDIO_SLC1_RX_UDF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ST1_S  10
-/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ST1    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ST1_M  (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S)
-#define SDIO_SLC1_TX_OVF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ST1_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S  13
-/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ST1    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ST1_M  (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S)
-#define SDIO_SLC1_TX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ST1_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M  (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S  15
-/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ST1    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ST1_M  (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S)
-#define SDIO_SLC1_RX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ST1_S  16
-/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ST1    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ST1_M  (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S)
-#define SDIO_SLC1_RX_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ST1_S  17
-/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ST1    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ST1_M  (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S)
-#define SDIO_SLC1_TOHOST_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ST1_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M  (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M  (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S  24
-
-/** SDIO_SLC1INT_ENA1_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ENA1_REG (DR_REG_SLC_BASE + 0x150)
-/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S  7
-/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ENA1    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ENA1_M  (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S)
-#define SDIO_SLC1_RX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ENA1_S  8
-/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ENA1    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ENA1_M  (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S)
-#define SDIO_SLC1_TX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ENA1_S  9
-/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ENA1    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ENA1_M  (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S)
-#define SDIO_SLC1_RX_UDF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ENA1_S  10
-/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ENA1    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ENA1_M  (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S)
-#define SDIO_SLC1_TX_OVF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ENA1_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S  13
-/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ENA1    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ENA1_M  (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S)
-#define SDIO_SLC1_TX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ENA1_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M  (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S  15
-/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ENA1    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ENA1_M  (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S)
-#define SDIO_SLC1_RX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ENA1_S  16
-/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ENA1    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ENA1_M  (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S)
-#define SDIO_SLC1_RX_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ENA1_S  17
-/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ENA1    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ENA1_M  (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S)
-#define SDIO_SLC1_TOHOST_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ENA1_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M  (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M  (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S  24
-
-/** SDIO_SLC0_TX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x154)
-/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC0_TX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x158)
-/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_SLC0_RX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC0_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x15c)
-/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC0_RX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC0_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x160)
-/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_SLC1_TX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x164)
-/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC1_TX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x168)
-/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_SLC1_RX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC1_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x16c)
-/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC1_RX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC1_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x170)
-/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_HDA_TX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_HDA_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x174)
-/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_HDA_RX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_HDA_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x178)
-/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC_BURST_LEN_REG register
- *  reserved
- */
-#define SDIO_SLC_BURST_LEN_REG (DR_REG_SLC_BASE + 0x17c)
-/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC0_TXDATA_BURST_LEN    (BIT(0))
-#define SDIO_SLC0_TXDATA_BURST_LEN_M  (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S)
-#define SDIO_SLC0_TXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC0_TXDATA_BURST_LEN_S  0
-/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC0_RXDATA_BURST_LEN    (BIT(1))
-#define SDIO_SLC0_RXDATA_BURST_LEN_M  (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S)
-#define SDIO_SLC0_RXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC0_RXDATA_BURST_LEN_S  1
-/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC1_TXDATA_BURST_LEN    (BIT(2))
-#define SDIO_SLC1_TXDATA_BURST_LEN_M  (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S)
-#define SDIO_SLC1_TXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC1_TXDATA_BURST_LEN_S  2
-/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC1_RXDATA_BURST_LEN    (BIT(3))
-#define SDIO_SLC1_RXDATA_BURST_LEN_M  (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S)
-#define SDIO_SLC1_RXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC1_RXDATA_BURST_LEN_S  3
-
-/** SDIO_SLCDATE_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCDATE_REG (DR_REG_SLC_BASE + 0x1f8)
-/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400;
- *  reserved
- */
-#define SDIO_SLC_DATE    0xFFFFFFFFU
-#define SDIO_SLC_DATE_M  (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S)
-#define SDIO_SLC_DATE_V  0xFFFFFFFFU
-#define SDIO_SLC_DATE_S  0
-
-/** SDIO_SLCID_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCID_REG (DR_REG_SLC_BASE + 0x1fc)
-/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256;
- *  reserved
- */
-#define SDIO_SLC_ID    0xFFFFFFFFU
-#define SDIO_SLC_ID_M  (SDIO_SLC_ID_V << SDIO_SLC_ID_S)
-#define SDIO_SLC_ID_V  0xFFFFFFFFU
-#define SDIO_SLC_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/slc_struct.h b/components/soc/esp32p4/include/soc/slc_struct.h
deleted file mode 100644
index 7d57757704..0000000000
--- a/components/soc/esp32p4/include/soc/slc_struct.h
+++ /dev/null
@@ -1,3253 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration registers */
-/** Type of slcconf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_tx_rst : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to reset tx fsm in dma slc0.
-         */
-        uint32_t slc0_tx_rst:1;
-        /** slc0_rx_rst : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to reset rx fsm in dma slc0.
-         */
-        uint32_t slc0_rx_rst:1;
-        /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0;
-         *  reset the command fifo of AHB bus of sdio slave
-         */
-        uint32_t slc_ahbm_fifo_rst:1;
-        /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0;
-         *  reset the AHB bus of sdio slave
-         */
-        uint32_t slc_ahbm_rst:1;
-        /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0;
-         *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc0_tx_loop_test:1;
-        /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0;
-         *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc0_rx_loop_test:1;
-        /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0;
-         *  Set 1 to enable change the owner bit of rx link descriptor
-         */
-        uint32_t slc0_rx_auto_wrback:1;
-        /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_no_restart_clr:1;
-        /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1;
-         *  0- AHB burst type is single when slave read rx-descriptor from memory through
-         *  slc0,1-AHB burst type is not single when slave read rx-descriptor from memory
-         *  through slc0
-         */
-        uint32_t slc0_rxdscr_burst_en:1;
-        /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1;
-         *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
-         *  is not single when slave receives data from memory
-         */
-        uint32_t slc0_rxdata_burst_en:1;
-        /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1;
-         *  enable the function that when host reading packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc0_rxlink_auto_ret:1;
-        /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1;
-         *  enable the function that when host sending packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc0_txlink_auto_ret:1;
-        /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1;
-         *  0- AHB burst type is single when slave read tx-descriptor from memory through
-         *  slc0,1-AHB burst type is not single when slave read tx-descriptor from memory
-         *  through slc0
-         */
-        uint32_t slc0_txdscr_burst_en:1;
-        /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1;
-         *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
-         *  single when slave send data to memory
-         */
-        uint32_t slc0_txdata_burst_en:1;
-        /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1;
-         *  auto clear slc0_token1 enable
-         */
-        uint32_t slc0_token_auto_clr:1;
-        /** slc0_token_sel : R/W; bitpos: [15]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_token_sel:1;
-        /** slc1_tx_rst : R/W; bitpos: [16]; default: 0;
-         *  Set 1 to reset tx fsm in dma slc0.
-         */
-        uint32_t slc1_tx_rst:1;
-        /** slc1_rx_rst : R/W; bitpos: [17]; default: 0;
-         *  Set 1 to reset rx fsm in dma slc0.
-         */
-        uint32_t slc1_rx_rst:1;
-        /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_mask_en:1;
-        /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_mask_en:1;
-        /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1;
-         *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc1_tx_loop_test:1;
-        /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1;
-         *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc1_rx_loop_test:1;
-        /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0;
-         *  Set 1 to enable change the owner bit of rx link descriptor
-         */
-        uint32_t slc1_rx_auto_wrback:1;
-        /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0;
-         *  ******* Description ***********
-         */
-        uint32_t slc1_rx_no_restart_clr:1;
-        /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1;
-         *  0- AHB burst type is single when slave read rx-descriptor from memory through
-         *  slc1,1-AHB burst type is not single when slave read rx-descriptor from memory
-         *  through slc1
-         */
-        uint32_t slc1_rxdscr_burst_en:1;
-        /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1;
-         *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
-         *  is not single when slave receives data from memory
-         */
-        uint32_t slc1_rxdata_burst_en:1;
-        /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1;
-         *  enable the function that when host reading packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc1_rxlink_auto_ret:1;
-        /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1;
-         *  enable the function that when host sending packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc1_txlink_auto_ret:1;
-        /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1;
-         *  0- AHB burst type is single when slave read tx-descriptor from memory through
-         *  slc1,1-AHB burst type is not single when slave read tx-descriptor from memory
-         *  through slc1
-         */
-        uint32_t slc1_txdscr_burst_en:1;
-        /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1;
-         *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
-         *  single when slave send data to memory
-         */
-        uint32_t slc1_txdata_burst_en:1;
-        /** slc1_token_auto_clr : R/W; bitpos: [30]; default: 1;
-         *  auto clear slc1_token1 enable
-         */
-        uint32_t slc1_token_auto_clr:1;
-        /** slc1_token_sel : R/W; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_token_sel:1;
-    };
-    uint32_t val;
-} sdio_slcconf0_reg_t;
-
-/** Type of slc0rxfifo_push register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxfifo_wdata:9;
-        uint32_t reserved_9:7;
-        /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxfifo_push:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc0rxfifo_push_reg_t;
-
-/** Type of slc1rxfifo_push register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxfifo_wdata:9;
-        uint32_t reserved_9:7;
-        /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxfifo_push:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc1rxfifo_push_reg_t;
-
-/** Type of slc0rx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_stop:1;
-        /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_start:1;
-        /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_restart:1;
-        /** slc0_rxlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc0rx_link_reg_t;
-
-/** Type of slc0rx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0rx_link_addr_reg_t;
-
-/** Type of slc0tx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_stop:1;
-        /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_start:1;
-        /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_restart:1;
-        /** slc0_txlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_txlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc0tx_link_reg_t;
-
-/** Type of slc0tx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0tx_link_addr_reg_t;
-
-/** Type of slc1rx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** slc1_bt_packet : R/W; bitpos: [20]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_bt_packet:1;
-        uint32_t reserved_21:7;
-        /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_stop:1;
-        /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_start:1;
-        /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_restart:1;
-        /** slc1_rxlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc1rx_link_reg_t;
-
-/** Type of slc1rx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1rx_link_addr_reg_t;
-
-/** Type of slc1tx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_stop:1;
-        /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_start:1;
-        /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_restart:1;
-        /** slc1_txlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_txlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc1tx_link_reg_t;
-
-/** Type of slc1tx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1tx_link_addr_reg_t;
-
-/** Type of slcintvec_tohost register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_intvec:8;
-        uint32_t reserved_8:8;
-        /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_intvec:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} sdio_slcintvec_tohost_reg_t;
-
-/** Type of slc0token0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_wdata:12;
-        /** slc0_token0_wr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_wr:1;
-        /** slc0_token0_inc : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_inc:1;
-        /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc0_token0 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc0token0_reg_t;
-
-/** Type of slc0token1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0;
-         *  slc0 token1 wdata
-         */
-        uint32_t slc0_token1_wdata:12;
-        /** slc0_token1_wr : WT; bitpos: [12]; default: 0;
-         *  update slc0_token1_wdata into slc0 token1
-         */
-        uint32_t slc0_token1_wr:1;
-        /** slc0_token1_inc : WT; bitpos: [13]; default: 0;
-         *  slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1
-         */
-        uint32_t slc0_token1_inc:1;
-        /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0;
-         *  slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add
-         *  slc0_token1_wdata to slc0_token1
-         */
-        uint32_t slc0_token1_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc0_token1 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc0token1_reg_t;
-
-/** Type of slc1token0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_wdata:12;
-        /** slc1_token0_wr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_wr:1;
-        /** slc1_token0_inc : WT; bitpos: [13]; default: 0;
-         *  Add 1 to  slc1_token0
-         */
-        uint32_t slc1_token0_inc:1;
-        /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0;
-         *  Add  slc1_token0_wdata to  slc1_token0
-         */
-        uint32_t slc1_token0_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc1_token0 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc1token0_reg_t;
-
-/** Type of slc1token1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_wdata:12;
-        /** slc1_token1_wr : WT; bitpos: [12]; default: 0;
-         *  update slc1_token1_wdata into slc1 token1
-         */
-        uint32_t slc1_token1_wr:1;
-        /** slc1_token1_inc : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_inc:1;
-        /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc1_token1 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc1token1_reg_t;
-
-/** Type of slcconf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_check_owner : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_check_owner:1;
-        /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_check_sum_en:1;
-        /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_check_sum_en:1;
-        /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1;
-         *  reserved
-         */
-        uint32_t sdio_cmd_hold_en:1;
-        /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_len_auto_clr:1;
-        /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_stitch_en:1;
-        /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rx_stitch_en:1;
-        uint32_t reserved_7:9;
-        /** slc1_check_owner : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_check_owner:1;
-        /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_check_sum_en:1;
-        /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_check_sum_en:1;
-        /** host_int_level_sel : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t host_int_level_sel:1;
-        /** slc1_tx_stitch_en : R/W; bitpos: [20]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_tx_stitch_en:1;
-        /** slc1_rx_stitch_en : R/W; bitpos: [21]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rx_stitch_en:1;
-        /** sdio_clk_en : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} sdio_slcconf1_reg_t;
-
-/** Type of slcbridge_conf register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32;
-         *  reserved
-         */
-        uint32_t slc_txeof_ena:6;
-        uint32_t reserved_6:2;
-        /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7;
-         *  reserved
-         */
-        uint32_t slc_fifo_map_ena:4;
-        /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_dummy_mode:1;
-        /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1;
-         *  reserved
-         */
-        uint32_t slc_hda_map_128k:1;
-        /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_tx_dummy_mode:1;
-        uint32_t reserved_15:1;
-        /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10;
-         *  reserved
-         */
-        uint32_t slc_tx_push_idle_num:16;
-    };
-    uint32_t val;
-} sdio_slcbridge_conf_reg_t;
-
-/** Type of slc0_to_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_to_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_to_eof_des_addr_reg_t;
-
-/** Type of slc0_tx_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_eof_des_addr_reg_t;
-
-/** Type of slc0_to_eof_bfr_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_to_eof_bfr_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_to_eof_bfr_des_addr_reg_t;
-
-/** Type of slc1_to_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_to_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_to_eof_des_addr_reg_t;
-
-/** Type of slc1_tx_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_eof_des_addr_reg_t;
-
-/** Type of slc1_to_eof_bfr_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_to_eof_bfr_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_to_eof_bfr_des_addr_reg_t;
-
-/** Type of slc_rx_dscr_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token_no_replace:1;
-        /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_infor_no_replace:1;
-        /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0;
-         *  slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next
-         *  pop doesn't occur after 255 cycles since the current pop
-         */
-        uint32_t slc0_rx_fill_mode:1;
-        /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1;
-         *  0-slc0 rx_push_eof, 1-slc0 rx_pop_eof
-         */
-        uint32_t slc0_rx_eof_mode:1;
-        /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rx_fill_en:1;
-        /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128;
-         *  reserved
-         */
-        uint32_t slc0_rd_retry_threshold:11;
-        /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_token_no_replace:1;
-        /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_infor_no_replace:1;
-        /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0;
-         *  slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next
-         *  pop doesn't occur after 255 cycles since the current pop
-         */
-        uint32_t slc1_rx_fill_mode:1;
-        /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1;
-         *  0-slc1 rx_push_eof, 1-slc1 rx_pop_eof
-         */
-        uint32_t slc1_rx_eof_mode:1;
-        /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rx_fill_en:1;
-        /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128;
-         *  reserved
-         */
-        uint32_t slc1_rd_retry_threshold:11;
-    };
-    uint32_t val;
-} sdio_slc_rx_dscr_conf_reg_t;
-
-/** Type of slc_tx_dscr_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128;
-         *  reserved
-         */
-        uint32_t slc_wr_retry_threshold:11;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} sdio_slc_tx_dscr_conf_reg_t;
-
-/** Type of slc0_len_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_wdata:20;
-        /** slc0_len_wr : WT; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_wr:1;
-        /** slc0_len_inc : WT; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_inc:1;
-        /** slc0_len_inc_more : WT; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_inc_more:1;
-        /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_packet_load_en:1;
-        /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_packet_load_en:1;
-        /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_get_used_dscr:1;
-        /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_get_used_dscr:1;
-        /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_new_pkt_ind:1;
-        /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_new_pkt_ind:1;
-        /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_packet_load_en_st:1;
-        /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_packet_load_en_st:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} sdio_slc0_len_conf_reg_t;
-
-/** Type of slc0_txpkt_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_h_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpkt_h_dscr_reg_t;
-
-/** Type of slc0_txpkt_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_e_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpkt_e_dscr_reg_t;
-
-/** Type of slc0_rxpkt_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_h_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpkt_h_dscr_reg_t;
-
-/** Type of slc0_rxpkt_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_e_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpkt_e_dscr_reg_t;
-
-/** Type of slc0_txpktu_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_start_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpktu_h_dscr_reg_t;
-
-/** Type of slc0_txpktu_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_end_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpktu_e_dscr_reg_t;
-
-/** Type of slc0_rxpktu_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_start_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpktu_h_dscr_reg_t;
-
-/** Type of slc0_rxpktu_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_end_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpktu_e_dscr_reg_t;
-
-/** Type of slc_seq_position register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9;
-         *  reserved
-         */
-        uint32_t slc0_seq_position:8;
-        /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5;
-         *  reserved
-         */
-        uint32_t slc1_seq_position:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} sdio_slc_seq_position_reg_t;
-
-/** Type of slc0_dscr_rec_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_rec_lim:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} sdio_slc0_dscr_rec_conf_reg_t;
-
-/** Type of slc_sdio_crc_st1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_crc_err_cnt:8;
-        uint32_t reserved_8:23;
-        /** err_cnt_clr : R/W; bitpos: [31]; default: 0;
-         *  reserved
-         */
-        uint32_t err_cnt_clr:1;
-    };
-    uint32_t val;
-} sdio_slc_sdio_crc_st1_reg_t;
-
-/** Type of slc0_len_lim_conf register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504;
-         *  reserved
-         */
-        uint32_t slc0_len_lim:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} sdio_slc0_len_lim_conf_reg_t;
-
-/** Type of slc0_tx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc0_tx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_sharemem_start_reg_t;
-
-/** Type of slc0_tx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc0_tx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_sharemem_end_reg_t;
-
-/** Type of slc0_rx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc0_rx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rx_sharemem_start_reg_t;
-
-/** Type of slc0_rx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc0_rx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rx_sharemem_end_reg_t;
-
-/** Type of slc1_tx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc1_tx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_sharemem_start_reg_t;
-
-/** Type of slc1_tx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc1_tx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_sharemem_end_reg_t;
-
-/** Type of slc1_rx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc1_rx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_rx_sharemem_start_reg_t;
-
-/** Type of slc1_rx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc1_rx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_rx_sharemem_end_reg_t;
-
-/** Type of hda_tx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_hda_tx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_hda_tx_sharemem_start_reg_t;
-
-/** Type of hda_rx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_hda_rx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_hda_rx_sharemem_start_reg_t;
-
-/** Type of slc_burst_len register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc0_txdata_burst_len:1;
-        /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc0_rxdata_burst_len:1;
-        /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc1_txdata_burst_len:1;
-        /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc1_rxdata_burst_len:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} sdio_slc_burst_len_reg_t;
-
-/** Type of slcid register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_id : R/W; bitpos: [31:0]; default: 256;
-         *  reserved
-         */
-        uint32_t slc_id:32;
-    };
-    uint32_t val;
-} sdio_slcid_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of slc0int_raw register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_raw:1;
-        /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_raw:1;
-        /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_raw:1;
-        /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_raw:1;
-        /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_raw:1;
-        /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_raw:1;
-        /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_raw:1;
-        /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_raw:1;
-        /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_raw:1;
-        /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_raw:1;
-        /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_raw:1;
-        /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_raw:1;
-        /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_raw:1;
-        /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_raw:1;
-        /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt bit of slc0 finishing receiving data to one buffer
-         */
-        uint32_t slc0_tx_done_int_raw:1;
-        /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw interrupt bit of slc0 finishing receiving data
-         */
-        uint32_t slc0_tx_suc_eof_int_raw:1;
-        /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw interrupt bit of slc0 finishing sending data from one buffer
-         */
-        uint32_t slc0_rx_done_int_raw:1;
-        /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw interrupt bit of slc0 finishing sending data
-         */
-        uint32_t slc0_rx_eof_int_raw:1;
-        /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_raw:1;
-        /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw interrupt bit of slc0 tx link descriptor error
-         */
-        uint32_t slc0_tx_dscr_err_int_raw:1;
-        /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw interrupt bit of slc0 rx link descriptor error
-         */
-        uint32_t slc0_rx_dscr_err_int_raw:1;
-        /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_raw:1;
-        /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_raw:1;
-        /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_raw:1;
-        /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_raw:1;
-        /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_raw:1;
-        /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_raw:1;
-        /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_raw:1;
-        /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_raw:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_raw_reg_t;
-
-/** Type of slc0int_st register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_st:1;
-        /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_st:1;
-        /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_st:1;
-        /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_st:1;
-        /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_st:1;
-        /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_st:1;
-        /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_st:1;
-        /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_st:1;
-        /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_st:1;
-        /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_st:1;
-        /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_st:1;
-        /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_st:1;
-        /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_st:1;
-        /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_st:1;
-        /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_st:1;
-        /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_st:1;
-        /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_st:1;
-        /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_st:1;
-        /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_st:1;
-        /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_st:1;
-        /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_st:1;
-        /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_st:1;
-        /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_st:1;
-        /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_st:1;
-        /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_st:1;
-        /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_st:1;
-        /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_st:1;
-        /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_st:1;
-        /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_st:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_st_reg_t;
-
-/** Type of slc0int_ena register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_ena:1;
-        /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_ena:1;
-        /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_ena:1;
-        /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_ena:1;
-        /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_ena:1;
-        /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_ena:1;
-        /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_ena:1;
-        /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_ena:1;
-        /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_ena:1;
-        /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_ena:1;
-        /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_ena:1;
-        /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_ena:1;
-        /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_ena:1;
-        /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_ena:1;
-        /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_ena:1;
-        /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_ena:1;
-        /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_ena:1;
-        /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_ena:1;
-        /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_ena:1;
-        /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_ena:1;
-        /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_ena:1;
-        /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_ena:1;
-        /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_ena:1;
-        /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_ena:1;
-        /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_ena:1;
-        /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_ena:1;
-        /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_ena:1;
-        /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_ena:1;
-        /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_ena:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_ena_reg_t;
-
-/** Type of slc0int_clr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_clr:1;
-        /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_clr:1;
-        /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_clr:1;
-        /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_clr:1;
-        /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_clr:1;
-        /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_clr:1;
-        /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_clr:1;
-        /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_clr:1;
-        /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_clr:1;
-        /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_clr:1;
-        /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_clr:1;
-        /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_clr:1;
-        /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_clr:1;
-        /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_clr:1;
-        /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_clr:1;
-        /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_clr:1;
-        /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_clr:1;
-        /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_clr:1;
-        /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_clr:1;
-        /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_clr:1;
-        /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_clr:1;
-        /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_clr:1;
-        /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_clr:1;
-        /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_clr:1;
-        /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_clr:1;
-        /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_clr:1;
-        /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_clr:1;
-        /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_clr:1;
-        /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_clr:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_clr_reg_t;
-
-/** Type of slc1int_raw register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_raw:1;
-        /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_raw:1;
-        /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_raw:1;
-        /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_raw:1;
-        /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_raw:1;
-        /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_raw:1;
-        /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_raw:1;
-        /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_raw:1;
-        /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_raw:1;
-        /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_raw:1;
-        /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_raw:1;
-        /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_raw:1;
-        /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_raw:1;
-        /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_raw:1;
-        /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_raw:1;
-        /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_raw:1;
-        /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_raw:1;
-        /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_raw:1;
-        /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_raw:1;
-        /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_raw:1;
-        /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_raw:1;
-        /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_raw:1;
-        /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_raw:1;
-        /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_raw:1;
-        /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_raw:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_raw_reg_t;
-
-/** Type of slc1int_st register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_st:1;
-        /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_st:1;
-        /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_st:1;
-        /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_st:1;
-        /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_st:1;
-        /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_st:1;
-        /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_st:1;
-        /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_st:1;
-        /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_st:1;
-        /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_st:1;
-        /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_st:1;
-        /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_st:1;
-        /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_st:1;
-        /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_st:1;
-        /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_st:1;
-        /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_st:1;
-        /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_st:1;
-        /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_st:1;
-        /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_st:1;
-        /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_st:1;
-        /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_st:1;
-        /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_st:1;
-        /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_st:1;
-        /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_st:1;
-        /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_st:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_st_reg_t;
-
-/** Type of slc1int_ena register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_ena:1;
-        /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_ena:1;
-        /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_ena:1;
-        /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_ena:1;
-        /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_ena:1;
-        /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_ena:1;
-        /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_ena:1;
-        /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_ena:1;
-        /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_ena:1;
-        /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_ena:1;
-        /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_ena:1;
-        /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_ena:1;
-        /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_ena:1;
-        /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_ena:1;
-        /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_ena:1;
-        /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_ena:1;
-        /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_ena:1;
-        /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_ena:1;
-        /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_ena:1;
-        /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_ena:1;
-        /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_ena:1;
-        /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_ena:1;
-        /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_ena:1;
-        /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_ena:1;
-        /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_ena:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_ena_reg_t;
-
-/** Type of slc1int_clr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_clr:1;
-        /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_clr:1;
-        /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_clr:1;
-        /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_clr:1;
-        /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_clr:1;
-        /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_clr:1;
-        /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_clr:1;
-        /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_clr:1;
-        /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_clr:1;
-        /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_clr:1;
-        /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_clr:1;
-        /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_clr:1;
-        /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_clr:1;
-        /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_clr:1;
-        /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_clr:1;
-        /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_clr:1;
-        /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_clr:1;
-        /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_clr:1;
-        /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_clr:1;
-        /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_clr:1;
-        /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_clr:1;
-        /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_clr:1;
-        /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_clr:1;
-        /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_clr:1;
-        /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_clr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_clr_reg_t;
-
-/** Type of slc0int_st1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_st1:1;
-        /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_st1:1;
-        /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_st1:1;
-        /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_st1:1;
-        /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_st1:1;
-        /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_st1:1;
-        /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_st1:1;
-        /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_st1:1;
-        /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_st1:1;
-        /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_st1:1;
-        /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_st1:1;
-        /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_st1:1;
-        /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_st1:1;
-        /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_st1:1;
-        /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_st1:1;
-        /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_st1:1;
-        /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_st1:1;
-        /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_st1:1;
-        /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_st1:1;
-        /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_st1:1;
-        /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_st1:1;
-        /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_st1:1;
-        /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_st1:1;
-        /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_st1:1;
-        /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_st1:1;
-        /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_st1:1;
-        /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_st1:1;
-        /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_st1:1;
-        /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_st1:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_st1_reg_t;
-
-/** Type of slc0int_ena1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_ena1:1;
-        /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_ena1:1;
-        /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_ena1:1;
-        /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_ena1:1;
-        /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_ena1:1;
-        /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_ena1:1;
-        /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_ena1:1;
-        /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_ena1:1;
-        /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_ena1:1;
-        /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_ena1:1;
-        /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_ena1:1;
-        /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_ena1:1;
-        /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_ena1:1;
-        /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_ena1:1;
-        /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_ena1:1;
-        /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_ena1:1;
-        /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_ena1:1;
-        /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_ena1:1;
-        /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_ena1:1;
-        /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_ena1:1;
-        /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_ena1:1;
-        /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_ena1:1;
-        /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_ena1:1;
-        /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_ena1:1;
-        /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_ena1:1;
-        /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_ena1:1;
-        /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_ena1:1;
-        /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_ena1:1;
-        /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_ena1:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_ena1_reg_t;
-
-/** Type of slc1int_st1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_st1:1;
-        /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_st1:1;
-        /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_st1:1;
-        /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_st1:1;
-        /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_st1:1;
-        /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_st1:1;
-        /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_st1:1;
-        /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_st1:1;
-        /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_st1:1;
-        /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_st1:1;
-        /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_st1:1;
-        /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_st1:1;
-        /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_st1:1;
-        /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_st1:1;
-        /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_st1:1;
-        /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_st1:1;
-        /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_st1:1;
-        /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_st1:1;
-        /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_st1:1;
-        /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_st1:1;
-        /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_st1:1;
-        /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_st1:1;
-        /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_st1:1;
-        /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_st1:1;
-        /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_st1:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_st1_reg_t;
-
-/** Type of slc1int_ena1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_ena1:1;
-        /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_ena1:1;
-        /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_ena1:1;
-        /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_ena1:1;
-        /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_ena1:1;
-        /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_ena1:1;
-        /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_ena1:1;
-        /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_ena1:1;
-        /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_ena1:1;
-        /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_ena1:1;
-        /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_ena1:1;
-        /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_ena1:1;
-        /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_ena1:1;
-        /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_ena1:1;
-        /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_ena1:1;
-        /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_ena1:1;
-        /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_ena1:1;
-        /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_ena1:1;
-        /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_ena1:1;
-        /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_ena1:1;
-        /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_ena1:1;
-        /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_ena1:1;
-        /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_ena1:1;
-        /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_ena1:1;
-        /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_ena1:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_ena1_reg_t;
-
-
-/** Group: Status registers */
-/** Type of slcrx_status register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_full : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_full:1;
-        /** slc0_rx_empty : RO; bitpos: [1]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rx_empty:1;
-        /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0;
-         *  the current buffer length when slc0 reads data from rx link
-         */
-        uint32_t slc0_rx_buf_len:14;
-        /** slc1_rx_full : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_full:1;
-        /** slc1_rx_empty : RO; bitpos: [17]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rx_empty:1;
-        /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0;
-         *  the current buffer length when slc1 reads data from rx link
-         */
-        uint32_t slc1_rx_buf_len:14;
-    };
-    uint32_t val;
-} sdio_slcrx_status_reg_t;
-
-/** Type of slctx_status register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_tx_full : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_full:1;
-        /** slc0_tx_empty : RO; bitpos: [1]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_empty:1;
-        uint32_t reserved_2:14;
-        /** slc1_tx_full : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_full:1;
-        /** slc1_tx_empty : RO; bitpos: [17]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_tx_empty:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} sdio_slctx_status_reg_t;
-
-/** Type of slc0_state0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_state0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_state0:32;
-    };
-    uint32_t val;
-} sdio_slc0_state0_reg_t;
-
-/** Type of slc0_state1 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_state1 : RO; bitpos: [31:0]; default: 0;
-         *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
-         *  rx_link fsm state, [30:24] rx_fifo_cnt
-         */
-        uint32_t slc0_state1:32;
-    };
-    uint32_t val;
-} sdio_slc0_state1_reg_t;
-
-/** Type of slc1_state0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_state0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_state0:32;
-    };
-    uint32_t val;
-} sdio_slc1_state0_reg_t;
-
-/** Type of slc1_state1 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_state1 : RO; bitpos: [31:0]; default: 0;
-         *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
-         *  rx_link fsm state, [30:24] rx_fifo_cnt
-         */
-        uint32_t slc1_state1:32;
-    };
-    uint32_t val;
-} sdio_slc1_state1_reg_t;
-
-/** Type of slc_sdio_st register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_st : RO; bitpos: [2:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_st:3;
-        uint32_t reserved_3:1;
-        /** func_st : RO; bitpos: [7:4]; default: 0;
-         *  reserved
-         */
-        uint32_t func_st:4;
-        /** sdio_wakeup : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_wakeup:1;
-        uint32_t reserved_9:3;
-        /** bus_st : RO; bitpos: [14:12]; default: 0;
-         *  reserved
-         */
-        uint32_t bus_st:3;
-        uint32_t reserved_15:1;
-        /** func1_acc_state : RO; bitpos: [20:16]; default: 0;
-         *  reserved
-         */
-        uint32_t func1_acc_state:5;
-        uint32_t reserved_21:3;
-        /** func2_acc_state : RO; bitpos: [28:24]; default: 0;
-         *  reserved
-         */
-        uint32_t func2_acc_state:5;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc_sdio_st_reg_t;
-
-/** Type of slc0_txlink_dscr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txlink_dscr_reg_t;
-
-/** Type of slc0_txlink_dscr_bf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc0_txlink_dscr_bf0_reg_t;
-
-/** Type of slc0_txlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc0_txlink_dscr_bf1_reg_t;
-
-/** Type of slc0_rxlink_dscr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  the third word of slc0 link descriptor, or known as the next descriptor address
-         */
-        uint32_t slc0_rxlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxlink_dscr_reg_t;
-
-/** Type of slc0_rxlink_dscr_bf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxlink_dscr_bf0_reg_t;
-
-/** Type of slc0_rxlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxlink_dscr_bf1_reg_t;
-
-/** Type of slc1_txlink_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc1_txlink_dscr_reg_t;
-
-/** Type of slc1_txlink_dscr_bf0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc1_txlink_dscr_bf0_reg_t;
-
-/** Type of slc1_txlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc1_txlink_dscr_bf1_reg_t;
-
-/** Type of slc1_rxlink_dscr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  the third word of slc1 link descriptor, or known as the next descriptor address
-         */
-        uint32_t slc1_rxlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc1_rxlink_dscr_reg_t;
-
-/** Type of slc1_rxlink_dscr_bf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc1_rxlink_dscr_bf0_reg_t;
-
-/** Type of slc1_rxlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc1_rxlink_dscr_bf1_reg_t;
-
-/** Type of slc0_tx_erreof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_erreof_des_addr_reg_t;
-
-/** Type of slc1_tx_erreof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_erreof_des_addr_reg_t;
-
-/** Type of slc_token_lat register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token : RO; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token:12;
-        uint32_t reserved_12:4;
-        /** slc1_token : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc_token_lat_reg_t;
-
-/** Type of slc_cmd_infor0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_content0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_content0:32;
-    };
-    uint32_t val;
-} sdio_slc_cmd_infor0_reg_t;
-
-/** Type of slc_cmd_infor1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_content1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_content1:32;
-    };
-    uint32_t val;
-} sdio_slc_cmd_infor1_reg_t;
-
-/** Type of slc0_length register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_len : RO; bitpos: [19:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} sdio_slc0_length_reg_t;
-
-/** Type of slc_sdio_crc_st0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t dat0_crc_err_cnt:8;
-        /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0;
-         *  reserved
-         */
-        uint32_t dat1_crc_err_cnt:8;
-        /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0;
-         *  reserved
-         */
-        uint32_t dat2_crc_err_cnt:8;
-        /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t dat3_crc_err_cnt:8;
-    };
-    uint32_t val;
-} sdio_slc_sdio_crc_st0_reg_t;
-
-/** Type of slc0_eof_start_des register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_eof_start_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_eof_start_des_reg_t;
-
-/** Type of slc0_push_dscr_addr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
-         */
-        uint32_t slc0_rx_push_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_push_dscr_addr_reg_t;
-
-/** Type of slc0_done_dscr_addr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  the current descriptor address when slc0 finishes reading data from one buffer,
-         *  aligned with word
-         */
-        uint32_t slc0_rx_done_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_done_dscr_addr_reg_t;
-
-/** Type of slc0_sub_start_des register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
-         */
-        uint32_t slc0_sub_pac_start_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_sub_start_des_reg_t;
-
-/** Type of slc0_dscr_cnt register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0;
-         *  the number of descriptors got by slc0 when it tries to read data from memory
-         */
-        uint32_t slc0_rx_dscr_cnt_lat:10;
-        uint32_t reserved_10:6;
-        /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_get_eof_occ:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc0_dscr_cnt_reg_t;
-
-
-/** Group: Debud registers */
-/** Type of slc0txfifo_pop register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024;
-         *  reserved
-         */
-        uint32_t slc0_txfifo_rdata:11;
-        uint32_t reserved_11:5;
-        /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txfifo_pop:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc0txfifo_pop_reg_t;
-
-/** Type of slc1txfifo_pop register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024;
-         *  reserved
-         */
-        uint32_t slc1_txfifo_rdata:11;
-        uint32_t reserved_11:5;
-        /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txfifo_pop:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc1txfifo_pop_reg_t;
-
-/** Type of slc_ahb_test register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_ahb_testmode:3;
-        uint32_t reserved_3:1;
-        /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_ahb_testaddr:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} sdio_slc_ahb_test_reg_t;
-
-
-/** Group: Version registers */
-/** Type of slcdate register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_date : R/W; bitpos: [31:0]; default: 554182400;
-         *  reserved
-         */
-        uint32_t slc_date:32;
-    };
-    uint32_t val;
-} sdio_slcdate_reg_t;
-
-
-typedef struct slc_dev_t {
-    volatile sdio_slcconf0_reg_t slcconf0;
-    volatile sdio_slc0int_raw_reg_t slc0int_raw;
-    volatile sdio_slc0int_st_reg_t slc0int_st;
-    volatile sdio_slc0int_ena_reg_t slc0int_ena;
-    volatile sdio_slc0int_clr_reg_t slc0int_clr;
-    volatile sdio_slc1int_raw_reg_t slc1int_raw;
-    volatile sdio_slc1int_st_reg_t slc1int_st;
-    volatile sdio_slc1int_ena_reg_t slc1int_ena;
-    volatile sdio_slc1int_clr_reg_t slc1int_clr;
-    volatile sdio_slcrx_status_reg_t slcrx_status;
-    volatile sdio_slc0rxfifo_push_reg_t slc0rxfifo_push;
-    volatile sdio_slc1rxfifo_push_reg_t slc1rxfifo_push;
-    volatile sdio_slctx_status_reg_t slctx_status;
-    volatile sdio_slc0txfifo_pop_reg_t slc0txfifo_pop;
-    volatile sdio_slc1txfifo_pop_reg_t slc1txfifo_pop;
-    volatile sdio_slc0rx_link_reg_t slc0rx_link;
-    volatile sdio_slc0rx_link_addr_reg_t slc0rx_link_addr;
-    volatile sdio_slc0tx_link_reg_t slc0tx_link;
-    volatile sdio_slc0tx_link_addr_reg_t slc0tx_link_addr;
-    volatile sdio_slc1rx_link_reg_t slc1rx_link;
-    volatile sdio_slc1rx_link_addr_reg_t slc1rx_link_addr;
-    volatile sdio_slc1tx_link_reg_t slc1tx_link;
-    volatile sdio_slc1tx_link_addr_reg_t slc1tx_link_addr;
-    volatile sdio_slcintvec_tohost_reg_t slcintvec_tohost;
-    volatile sdio_slc0token0_reg_t slc0token0;
-    volatile sdio_slc0token1_reg_t slc0token1;
-    volatile sdio_slc1token0_reg_t slc1token0;
-    volatile sdio_slc1token1_reg_t slc1token1;
-    volatile sdio_slcconf1_reg_t slcconf1;
-    volatile sdio_slc0_state0_reg_t slc0_state0;
-    volatile sdio_slc0_state1_reg_t slc0_state1;
-    volatile sdio_slc1_state0_reg_t slc1_state0;
-    volatile sdio_slc1_state1_reg_t slc1_state1;
-    volatile sdio_slcbridge_conf_reg_t slcbridge_conf;
-    volatile sdio_slc0_to_eof_des_addr_reg_t slc0_to_eof_des_addr;
-    volatile sdio_slc0_tx_eof_des_addr_reg_t slc0_tx_eof_des_addr;
-    volatile sdio_slc0_to_eof_bfr_des_addr_reg_t slc0_to_eof_bfr_des_addr;
-    volatile sdio_slc1_to_eof_des_addr_reg_t slc1_to_eof_des_addr;
-    volatile sdio_slc1_tx_eof_des_addr_reg_t slc1_tx_eof_des_addr;
-    volatile sdio_slc1_to_eof_bfr_des_addr_reg_t slc1_to_eof_bfr_des_addr;
-    volatile sdio_slc_ahb_test_reg_t slc_ahb_test;
-    volatile sdio_slc_sdio_st_reg_t slc_sdio_st;
-    volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf;
-    volatile sdio_slc0_txlink_dscr_reg_t slc0_txlink_dscr;
-    volatile sdio_slc0_txlink_dscr_bf0_reg_t slc0_txlink_dscr_bf0;
-    volatile sdio_slc0_txlink_dscr_bf1_reg_t slc0_txlink_dscr_bf1;
-    volatile sdio_slc0_rxlink_dscr_reg_t slc0_rxlink_dscr;
-    volatile sdio_slc0_rxlink_dscr_bf0_reg_t slc0_rxlink_dscr_bf0;
-    volatile sdio_slc0_rxlink_dscr_bf1_reg_t slc0_rxlink_dscr_bf1;
-    volatile sdio_slc1_txlink_dscr_reg_t slc1_txlink_dscr;
-    volatile sdio_slc1_txlink_dscr_bf0_reg_t slc1_txlink_dscr_bf0;
-    volatile sdio_slc1_txlink_dscr_bf1_reg_t slc1_txlink_dscr_bf1;
-    volatile sdio_slc1_rxlink_dscr_reg_t slc1_rxlink_dscr;
-    volatile sdio_slc1_rxlink_dscr_bf0_reg_t slc1_rxlink_dscr_bf0;
-    volatile sdio_slc1_rxlink_dscr_bf1_reg_t slc1_rxlink_dscr_bf1;
-    volatile sdio_slc0_tx_erreof_des_addr_reg_t slc0_tx_erreof_des_addr;
-    volatile sdio_slc1_tx_erreof_des_addr_reg_t slc1_tx_erreof_des_addr;
-    volatile sdio_slc_token_lat_reg_t slc_token_lat;
-    volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf;
-    volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0;
-    volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1;
-    volatile sdio_slc0_len_conf_reg_t slc0_len_conf;
-    volatile sdio_slc0_length_reg_t slc0_length;
-    volatile sdio_slc0_txpkt_h_dscr_reg_t slc0_txpkt_h_dscr;
-    volatile sdio_slc0_txpkt_e_dscr_reg_t slc0_txpkt_e_dscr;
-    volatile sdio_slc0_rxpkt_h_dscr_reg_t slc0_rxpkt_h_dscr;
-    volatile sdio_slc0_rxpkt_e_dscr_reg_t slc0_rxpkt_e_dscr;
-    volatile sdio_slc0_txpktu_h_dscr_reg_t slc0_txpktu_h_dscr;
-    volatile sdio_slc0_txpktu_e_dscr_reg_t slc0_txpktu_e_dscr;
-    volatile sdio_slc0_rxpktu_h_dscr_reg_t slc0_rxpktu_h_dscr;
-    volatile sdio_slc0_rxpktu_e_dscr_reg_t slc0_rxpktu_e_dscr;
-    volatile sdio_slc_seq_position_reg_t slc_seq_position;
-    volatile sdio_slc0_dscr_rec_conf_reg_t slc0_dscr_rec_conf;
-    volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0;
-    volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1;
-    volatile sdio_slc0_eof_start_des_reg_t slc0_eof_start_des;
-    volatile sdio_slc0_push_dscr_addr_reg_t slc0_push_dscr_addr;
-    volatile sdio_slc0_done_dscr_addr_reg_t slc0_done_dscr_addr;
-    volatile sdio_slc0_sub_start_des_reg_t slc0_sub_start_des;
-    volatile sdio_slc0_dscr_cnt_reg_t slc0_dscr_cnt;
-    volatile sdio_slc0_len_lim_conf_reg_t slc0_len_lim_conf;
-    volatile sdio_slc0int_st1_reg_t slc0int_st1;
-    volatile sdio_slc0int_ena1_reg_t slc0int_ena1;
-    volatile sdio_slc1int_st1_reg_t slc1int_st1;
-    volatile sdio_slc1int_ena1_reg_t slc1int_ena1;
-    volatile sdio_slc0_tx_sharemem_start_reg_t slc0_tx_sharemem_start;
-    volatile sdio_slc0_tx_sharemem_end_reg_t slc0_tx_sharemem_end;
-    volatile sdio_slc0_rx_sharemem_start_reg_t slc0_rx_sharemem_start;
-    volatile sdio_slc0_rx_sharemem_end_reg_t slc0_rx_sharemem_end;
-    volatile sdio_slc1_tx_sharemem_start_reg_t slc1_tx_sharemem_start;
-    volatile sdio_slc1_tx_sharemem_end_reg_t slc1_tx_sharemem_end;
-    volatile sdio_slc1_rx_sharemem_start_reg_t slc1_rx_sharemem_start;
-    volatile sdio_slc1_rx_sharemem_end_reg_t slc1_rx_sharemem_end;
-    volatile sdio_hda_tx_sharemem_start_reg_t hda_tx_sharemem_start;
-    volatile sdio_hda_rx_sharemem_start_reg_t hda_rx_sharemem_start;
-    volatile sdio_slc_burst_len_reg_t slc_burst_len;
-    uint32_t reserved_180[30];
-    volatile sdio_slcdate_reg_t slcdate;
-    volatile sdio_slcid_reg_t slcid;
-} slc_dev_t;
-
-extern slc_dev_t SLC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
index a0e2870af6..ba04102638 100644
--- a/components/soc/esp32p4/include/soc/soc.h
+++ b/components/soc/esp32p4/include/soc/soc.h
@@ -134,6 +134,7 @@
 #endif /* !__ASSEMBLER__ */
 //}}
 
+//TODO: IDF-7526
 //Periheral Clock {{
 #define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
diff --git a/components/soc/esp32p4/include/soc/spi_mem_struct.h b/components/soc/esp32p4/include/soc/spi_mem_struct.h
index 888ad4e031..73af7d2536 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_struct.h
@@ -10,7 +10,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct spi_mem_dev_s {
     union {
         struct {
             uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
diff --git a/components/soc/esp32p4/include/soc/spi_pins.h b/components/soc/esp32p4/include/soc/spi_pins.h
index bdfce943a2..d2aa55b41e 100644
--- a/components/soc/esp32p4/include/soc/spi_pins.h
+++ b/components/soc/esp32p4/include/soc/spi_pins.h
@@ -4,23 +4,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _SOC_SPI_PINS_H_
-#define _SOC_SPI_PINS_H_
-
-#define SPI_FUNC_NUM            0
-#define SPI_IOMUX_PIN_NUM_HD    12
-#define SPI_IOMUX_PIN_NUM_CS    14
-#define SPI_IOMUX_PIN_NUM_MOSI  16
-#define SPI_IOMUX_PIN_NUM_CLK   15
-#define SPI_IOMUX_PIN_NUM_MISO  17
-#define SPI_IOMUX_PIN_NUM_WP    13
-
-#define SPI2_FUNC_NUM           2
-#define SPI2_IOMUX_PIN_NUM_MISO 2
-#define SPI2_IOMUX_PIN_NUM_HD   4
-#define SPI2_IOMUX_PIN_NUM_WP   5
-#define SPI2_IOMUX_PIN_NUM_CLK  6
-#define SPI2_IOMUX_PIN_NUM_MOSI 7
-#define SPI2_IOMUX_PIN_NUM_CS   10
-
-#endif
+#pragma once
diff --git a/components/soc/esp32p4/include/soc/sys_clkrst_reg.h b/components/soc/esp32p4/include/soc/sys_clkrst_reg.h
deleted file mode 100644
index 202223cf00..0000000000
--- a/components/soc/esp32p4/include/soc/sys_clkrst_reg.h
+++ /dev/null
@@ -1,1118 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SYS_CLKRST_REG_H_
-#define _SOC_SYS_CLKRST_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define SYS_CLKRST_SYS_CLK_VER_DATE_REG          (DR_REG_SYS_CLKRST_BASE + 0x0)
-/* SYS_CLKRST_VER_DATE : R/W ;bitpos:[31:0] ;default: 32'h20210610 ; */
-/*description: .*/
-#define SYS_CLKRST_VER_DATE    0xFFFFFFFF
-#define SYS_CLKRST_VER_DATE_M  ((SYS_CLKRST_VER_DATE_V)<<(SYS_CLKRST_VER_DATE_S))
-#define SYS_CLKRST_VER_DATE_V  0xFFFFFFFF
-#define SYS_CLKRST_VER_DATE_S  0
-
-#define SYS_CLKRST_SYS_ICM_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x4)
-/* SYS_CLKRST_SYS_ICM_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: system icm clock enable.*/
-#define SYS_CLKRST_SYS_ICM_APB_CLK_EN    (BIT(0))
-#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_S  0
-
-#define SYS_CLKRST_JPEG_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x8)
-/* SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_JPEG_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_JPEG_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_JPEG_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_JPEG_CLK_DIV_NUM_M  ((SYS_CLKRST_JPEG_CLK_DIV_NUM_V)<<(SYS_CLKRST_JPEG_CLK_DIV_NUM_S))
-#define SYS_CLKRST_JPEG_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_JPEG_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_JPEG_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_JPEG_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_JPEG_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_JPEG_FORCE_NORST_V  0x1
-#define SYS_CLKRST_JPEG_FORCE_NORST_S  5
-/* SYS_CLKRST_JPEG_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_JPEG_RSTN    (BIT(4))
-#define SYS_CLKRST_JPEG_RSTN_M  (BIT(4))
-#define SYS_CLKRST_JPEG_RSTN_V  0x1
-#define SYS_CLKRST_JPEG_RSTN_S  4
-/* SYS_CLKRST_JPEG_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_JPEG_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_JPEG_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_JPEG_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_JPEG_APB_CLK_EN_S  3
-/* SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_JPEG_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_JPEG_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_JPEG_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_JPEG_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_JPEG_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_JPEG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_JPEG_CLK_EN    (BIT(0))
-#define SYS_CLKRST_JPEG_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_JPEG_CLK_EN_V  0x1
-#define SYS_CLKRST_JPEG_CLK_EN_S  0
-
-#define SYS_CLKRST_GFX_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0xC)
-/* SYS_CLKRST_GFX_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_GFX_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_GFX_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GFX_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_GFX_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_GFX_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_GFX_CLK_DIV_NUM_M  ((SYS_CLKRST_GFX_CLK_DIV_NUM_V)<<(SYS_CLKRST_GFX_CLK_DIV_NUM_S))
-#define SYS_CLKRST_GFX_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_GFX_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_GFX_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_GFX_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_GFX_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_GFX_FORCE_NORST_V  0x1
-#define SYS_CLKRST_GFX_FORCE_NORST_S  5
-/* SYS_CLKRST_GFX_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_GFX_RSTN    (BIT(4))
-#define SYS_CLKRST_GFX_RSTN_M  (BIT(4))
-#define SYS_CLKRST_GFX_RSTN_V  0x1
-#define SYS_CLKRST_GFX_RSTN_S  4
-/* SYS_CLKRST_GFX_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_GFX_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_GFX_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_GFX_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_GFX_APB_CLK_EN_S  3
-/* SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_GFX_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_GFX_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_GFX_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_GFX_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_GFX_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_GFX_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_GFX_CLK_EN    (BIT(0))
-#define SYS_CLKRST_GFX_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_GFX_CLK_EN_V  0x1
-#define SYS_CLKRST_GFX_CLK_EN_S  0
-
-#define SYS_CLKRST_PSRAM_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x10)
-/* SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_PSRAM_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_PSRAM_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_M  ((SYS_CLKRST_PSRAM_CLK_DIV_NUM_V)<<(SYS_CLKRST_PSRAM_CLK_DIV_NUM_S))
-#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_PSRAM_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_PSRAM_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_PSRAM_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_PSRAM_FORCE_NORST_V  0x1
-#define SYS_CLKRST_PSRAM_FORCE_NORST_S  5
-/* SYS_CLKRST_PSRAM_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_PSRAM_RSTN    (BIT(4))
-#define SYS_CLKRST_PSRAM_RSTN_M  (BIT(4))
-#define SYS_CLKRST_PSRAM_RSTN_V  0x1
-#define SYS_CLKRST_PSRAM_RSTN_S  4
-/* SYS_CLKRST_PSRAM_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_PSRAM_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_PSRAM_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_PSRAM_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_PSRAM_APB_CLK_EN_S  3
-/* SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_PSRAM_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_PSRAM_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_PSRAM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_PSRAM_CLK_EN    (BIT(0))
-#define SYS_CLKRST_PSRAM_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_PSRAM_CLK_EN_V  0x1
-#define SYS_CLKRST_PSRAM_CLK_EN_S  0
-
-#define SYS_CLKRST_MSPI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x14)
-/* SYS_CLKRST_MSPI_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_MSPI_FORCE_NORST    (BIT(2))
-#define SYS_CLKRST_MSPI_FORCE_NORST_M  (BIT(2))
-#define SYS_CLKRST_MSPI_FORCE_NORST_V  0x1
-#define SYS_CLKRST_MSPI_FORCE_NORST_S  2
-/* SYS_CLKRST_MSPI_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_MSPI_RSTN    (BIT(1))
-#define SYS_CLKRST_MSPI_RSTN_M  (BIT(1))
-#define SYS_CLKRST_MSPI_RSTN_V  0x1
-#define SYS_CLKRST_MSPI_RSTN_S  1
-/* SYS_CLKRST_MSPI_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_MSPI_APB_CLK_EN    (BIT(0))
-#define SYS_CLKRST_MSPI_APB_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_MSPI_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_MSPI_APB_CLK_EN_S  0
-
-#define SYS_CLKRST_DSI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x18)
-/* SYS_CLKRST_DSI_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_DSI_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_DSI_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_DSI_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_DSI_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_DSI_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_DSI_CLK_DIV_NUM_M  ((SYS_CLKRST_DSI_CLK_DIV_NUM_V)<<(SYS_CLKRST_DSI_CLK_DIV_NUM_S))
-#define SYS_CLKRST_DSI_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_DSI_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_DSI_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_DSI_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_DSI_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_DSI_FORCE_NORST_V  0x1
-#define SYS_CLKRST_DSI_FORCE_NORST_S  5
-/* SYS_CLKRST_DSI_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_DSI_RSTN    (BIT(4))
-#define SYS_CLKRST_DSI_RSTN_M  (BIT(4))
-#define SYS_CLKRST_DSI_RSTN_V  0x1
-#define SYS_CLKRST_DSI_RSTN_S  4
-/* SYS_CLKRST_DSI_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_DSI_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_DSI_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_DSI_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_DSI_APB_CLK_EN_S  3
-/* SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_DSI_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_DSI_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_DSI_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_DSI_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_DSI_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_DSI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_DSI_CLK_EN    (BIT(0))
-#define SYS_CLKRST_DSI_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_DSI_CLK_EN_V  0x1
-#define SYS_CLKRST_DSI_CLK_EN_S  0
-
-#define SYS_CLKRST_CSI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x1C)
-/* SYS_CLKRST_CSI_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_CSI_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_CSI_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_CSI_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_CSI_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_CSI_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_CSI_CLK_DIV_NUM_M  ((SYS_CLKRST_CSI_CLK_DIV_NUM_V)<<(SYS_CLKRST_CSI_CLK_DIV_NUM_S))
-#define SYS_CLKRST_CSI_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_CSI_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_CSI_BRG_RSTN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_CSI_BRG_RSTN    (BIT(6))
-#define SYS_CLKRST_CSI_BRG_RSTN_M  (BIT(6))
-#define SYS_CLKRST_CSI_BRG_RSTN_V  0x1
-#define SYS_CLKRST_CSI_BRG_RSTN_S  6
-/* SYS_CLKRST_CSI_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_CSI_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_CSI_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_CSI_FORCE_NORST_V  0x1
-#define SYS_CLKRST_CSI_FORCE_NORST_S  5
-/* SYS_CLKRST_CSI_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_CSI_RSTN    (BIT(4))
-#define SYS_CLKRST_CSI_RSTN_M  (BIT(4))
-#define SYS_CLKRST_CSI_RSTN_V  0x1
-#define SYS_CLKRST_CSI_RSTN_S  4
-/* SYS_CLKRST_CSI_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_CSI_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_CSI_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_CSI_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_CSI_APB_CLK_EN_S  3
-/* SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_CSI_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_CSI_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_CSI_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_CSI_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_CSI_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_CSI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_CSI_CLK_EN    (BIT(0))
-#define SYS_CLKRST_CSI_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_CSI_CLK_EN_V  0x1
-#define SYS_CLKRST_CSI_CLK_EN_S  0
-
-#define SYS_CLKRST_USB_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x20)
-/* SYS_CLKRST_USB_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_USB_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_USB_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_USB_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_USB_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_USB_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_USB_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_USB_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_USB_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_USB_CLK_DIV_NUM_M  ((SYS_CLKRST_USB_CLK_DIV_NUM_V)<<(SYS_CLKRST_USB_CLK_DIV_NUM_S))
-#define SYS_CLKRST_USB_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_USB_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_USB_PHY_FORCE_NORST : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Usb phy software force no reset.*/
-#define SYS_CLKRST_USB_PHY_FORCE_NORST    (BIT(7))
-#define SYS_CLKRST_USB_PHY_FORCE_NORST_M  (BIT(7))
-#define SYS_CLKRST_USB_PHY_FORCE_NORST_V  0x1
-#define SYS_CLKRST_USB_PHY_FORCE_NORST_S  7
-/* SYS_CLKRST_USB_FORCE_NORST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Usb software force no reset.*/
-#define SYS_CLKRST_USB_FORCE_NORST    (BIT(6))
-#define SYS_CLKRST_USB_FORCE_NORST_M  (BIT(6))
-#define SYS_CLKRST_USB_FORCE_NORST_V  0x1
-#define SYS_CLKRST_USB_FORCE_NORST_S  6
-/* SYS_CLKRST_USB_PHY_RSTN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: Usb phy software reset : low active.*/
-#define SYS_CLKRST_USB_PHY_RSTN    (BIT(5))
-#define SYS_CLKRST_USB_PHY_RSTN_M  (BIT(5))
-#define SYS_CLKRST_USB_PHY_RSTN_V  0x1
-#define SYS_CLKRST_USB_PHY_RSTN_S  5
-/* SYS_CLKRST_USB_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: Usb software reset : low active.*/
-#define SYS_CLKRST_USB_RSTN    (BIT(4))
-#define SYS_CLKRST_USB_RSTN_M  (BIT(4))
-#define SYS_CLKRST_USB_RSTN_V  0x1
-#define SYS_CLKRST_USB_RSTN_S  4
-/* SYS_CLKRST_USB_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_USB_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_USB_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_USB_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_USB_APB_CLK_EN_S  3
-/* SYS_CLKRST_USB_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_USB_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_USB_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_USB_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_USB_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_USB_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_USB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_USB_CLK_EN    (BIT(0))
-#define SYS_CLKRST_USB_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_USB_CLK_EN_V  0x1
-#define SYS_CLKRST_USB_CLK_EN_S  0
-
-#define SYS_CLKRST_GMAC_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x24)
-/* SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'b0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_GMAC_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_GMAC_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_GMAC_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_GMAC_CLK_DIV_NUM_M  ((SYS_CLKRST_GMAC_CLK_DIV_NUM_V)<<(SYS_CLKRST_GMAC_CLK_DIV_NUM_S))
-#define SYS_CLKRST_GMAC_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_GMAC_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_GMAC_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_GMAC_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_GMAC_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_GMAC_FORCE_NORST_V  0x1
-#define SYS_CLKRST_GMAC_FORCE_NORST_S  5
-/* SYS_CLKRST_GMAC_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_GMAC_RSTN    (BIT(4))
-#define SYS_CLKRST_GMAC_RSTN_M  (BIT(4))
-#define SYS_CLKRST_GMAC_RSTN_V  0x1
-#define SYS_CLKRST_GMAC_RSTN_S  4
-/* SYS_CLKRST_GMAC_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_GMAC_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_GMAC_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_GMAC_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_GMAC_APB_CLK_EN_S  3
-/* SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_GMAC_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_GMAC_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_GMAC_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_GMAC_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_GMAC_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_GMAC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_GMAC_CLK_EN    (BIT(0))
-#define SYS_CLKRST_GMAC_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_GMAC_CLK_EN_V  0x1
-#define SYS_CLKRST_GMAC_CLK_EN_S  0
-
-#define SYS_CLKRST_SDMMC_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x28)
-/* SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_SDMMC_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_SDMMC_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_M  ((SYS_CLKRST_SDMMC_CLK_DIV_NUM_V)<<(SYS_CLKRST_SDMMC_CLK_DIV_NUM_S))
-#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_SDMMC_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_SDMMC_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_SDMMC_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_SDMMC_FORCE_NORST_V  0x1
-#define SYS_CLKRST_SDMMC_FORCE_NORST_S  5
-/* SYS_CLKRST_SDMMC_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_SDMMC_RSTN    (BIT(4))
-#define SYS_CLKRST_SDMMC_RSTN_M  (BIT(4))
-#define SYS_CLKRST_SDMMC_RSTN_V  0x1
-#define SYS_CLKRST_SDMMC_RSTN_S  4
-/* SYS_CLKRST_SDMMC_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_SDMMC_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_SDMMC_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_SDMMC_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_SDMMC_APB_CLK_EN_S  3
-/* SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_SDMMC_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_SDMMC_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_SDMMC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_SDMMC_CLK_EN    (BIT(0))
-#define SYS_CLKRST_SDMMC_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_SDMMC_CLK_EN_V  0x1
-#define SYS_CLKRST_SDMMC_CLK_EN_S  0
-
-#define SYS_CLKRST_DDRC_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x2C)
-/* SYS_CLKRST_DDRC_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_DDRC_FORCE_NORST    (BIT(2))
-#define SYS_CLKRST_DDRC_FORCE_NORST_M  (BIT(2))
-#define SYS_CLKRST_DDRC_FORCE_NORST_V  0x1
-#define SYS_CLKRST_DDRC_FORCE_NORST_S  2
-/* SYS_CLKRST_DDRC_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_DDRC_RSTN    (BIT(1))
-#define SYS_CLKRST_DDRC_RSTN_M  (BIT(1))
-#define SYS_CLKRST_DDRC_RSTN_V  0x1
-#define SYS_CLKRST_DDRC_RSTN_S  1
-/* SYS_CLKRST_DDRC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_DDRC_CLK_EN    (BIT(0))
-#define SYS_CLKRST_DDRC_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_DDRC_CLK_EN_V  0x1
-#define SYS_CLKRST_DDRC_CLK_EN_S  0
-
-#define SYS_CLKRST_GDMA_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x30)
-/* SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: current clock divider number.*/
-#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_GDMA_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: clock phase offset compare to hp clock sync signal.*/
-#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_GDMA_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: clock divider number.*/
-#define SYS_CLKRST_GDMA_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_GDMA_CLK_DIV_NUM_M  ((SYS_CLKRST_GDMA_CLK_DIV_NUM_V)<<(SYS_CLKRST_GDMA_CLK_DIV_NUM_S))
-#define SYS_CLKRST_GDMA_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_GDMA_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_GDMA_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: software force no reset.*/
-#define SYS_CLKRST_GDMA_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_GDMA_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_GDMA_FORCE_NORST_V  0x1
-#define SYS_CLKRST_GDMA_FORCE_NORST_S  5
-/* SYS_CLKRST_GDMA_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: software reset : low active.*/
-#define SYS_CLKRST_GDMA_RSTN    (BIT(4))
-#define SYS_CLKRST_GDMA_RSTN_M  (BIT(4))
-#define SYS_CLKRST_GDMA_RSTN_V  0x1
-#define SYS_CLKRST_GDMA_RSTN_S  4
-/* SYS_CLKRST_GDMA_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: apb clock enable.*/
-#define SYS_CLKRST_GDMA_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_GDMA_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_GDMA_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_GDMA_APB_CLK_EN_S  3
-/* SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: clock force sync enable : clock output only available when clock is synced.*/
-#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_GDMA_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
-#define SYS_CLKRST_GDMA_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_GDMA_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_GDMA_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_GDMA_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_GDMA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: clock output enable.*/
-#define SYS_CLKRST_GDMA_CLK_EN    (BIT(0))
-#define SYS_CLKRST_GDMA_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_GDMA_CLK_EN_V  0x1
-#define SYS_CLKRST_GDMA_CLK_EN_S  0
-
-#define SYS_CLKRST_USBOTG_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x34)
-/* SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_USBOTG_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_M  ((SYS_CLKRST_USBOTG_CLK_DIV_NUM_V)<<(SYS_CLKRST_USBOTG_CLK_DIV_NUM_S))
-#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_USBOTG_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_USBOTG_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_USBOTG_FORCE_NORST_V  0x1
-#define SYS_CLKRST_USBOTG_FORCE_NORST_S  5
-/* SYS_CLKRST_USBOTG_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_RSTN    (BIT(4))
-#define SYS_CLKRST_USBOTG_RSTN_M  (BIT(4))
-#define SYS_CLKRST_USBOTG_RSTN_V  0x1
-#define SYS_CLKRST_USBOTG_RSTN_S  4
-/* SYS_CLKRST_USBOTG_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_APB_CLK_EN    (BIT(3))
-#define SYS_CLKRST_USBOTG_APB_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_USBOTG_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_USBOTG_APB_CLK_EN_S  3
-/* SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_USBOTG_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_USBOTG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_USBOTG_CLK_EN    (BIT(0))
-#define SYS_CLKRST_USBOTG_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_USBOTG_CLK_EN_V  0x1
-#define SYS_CLKRST_USBOTG_CLK_EN_S  0
-
-#define SYS_CLKRST_SDIO_SLAVE_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x38)
-/* SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM    0x000000FF
-#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_M  ((SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_S))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_V  0xFF
-#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_S  24
-/* SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET    0x000000FF
-#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_M  ((SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_S))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_V  0xFF
-#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_S  16
-/* SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM    0x000000FF
-#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_M  ((SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_S))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_V  0xFF
-#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_S  8
-/* SYS_CLKRST_SDIO_SLAVE_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST    (BIT(5))
-#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_M  (BIT(5))
-#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_V  0x1
-#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_S  5
-/* SYS_CLKRST_SDIO_SLAVE_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_RSTN    (BIT(4))
-#define SYS_CLKRST_SDIO_SLAVE_RSTN_M  (BIT(4))
-#define SYS_CLKRST_SDIO_SLAVE_RSTN_V  0x1
-#define SYS_CLKRST_SDIO_SLAVE_RSTN_S  4
-/* SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN    (BIT(2))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_M  (BIT(2))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_V  0x1
-#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_S  2
-/* SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN    (BIT(1))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_M  (BIT(1))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_V  0x1
-#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_S  1
-/* SYS_CLKRST_SDIO_SLAVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_CLK_EN    (BIT(0))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_V  0x1
-#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_S  0
-
-#define SYS_CLKRST_ISP_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x40)
-/* SYS_CLKRST_ISP_CLK_DIV_NUM : R/W ;bitpos:[6:3] ;default: 4'd1 ; */
-/*description: .*/
-#define SYS_CLKRST_ISP_CLK_DIV_NUM    0x0000000F
-#define SYS_CLKRST_ISP_CLK_DIV_NUM_M  ((SYS_CLKRST_ISP_CLK_DIV_NUM_V)<<(SYS_CLKRST_ISP_CLK_DIV_NUM_S))
-#define SYS_CLKRST_ISP_CLK_DIV_NUM_V  0xF
-#define SYS_CLKRST_ISP_CLK_DIV_NUM_S  3
-/* SYS_CLKRST_ISP_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_ISP_FORCE_NORST    (BIT(2))
-#define SYS_CLKRST_ISP_FORCE_NORST_M  (BIT(2))
-#define SYS_CLKRST_ISP_FORCE_NORST_V  0x1
-#define SYS_CLKRST_ISP_FORCE_NORST_S  2
-/* SYS_CLKRST_ISP_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_ISP_RSTN    (BIT(1))
-#define SYS_CLKRST_ISP_RSTN_M  (BIT(1))
-#define SYS_CLKRST_ISP_RSTN_V  0x1
-#define SYS_CLKRST_ISP_RSTN_S  1
-/* SYS_CLKRST_ISP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_ISP_CLK_EN    (BIT(0))
-#define SYS_CLKRST_ISP_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_ISP_CLK_EN_V  0x1
-#define SYS_CLKRST_ISP_CLK_EN_S  0
-
-#define SYS_CLKRST_DMA2D_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x44)
-/* SYS_CLKRST_DMA2D_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_DMA2D_FORCE_NORST    (BIT(2))
-#define SYS_CLKRST_DMA2D_FORCE_NORST_M  (BIT(2))
-#define SYS_CLKRST_DMA2D_FORCE_NORST_V  0x1
-#define SYS_CLKRST_DMA2D_FORCE_NORST_S  2
-/* SYS_CLKRST_DMA2D_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_DMA2D_RSTN    (BIT(1))
-#define SYS_CLKRST_DMA2D_RSTN_M  (BIT(1))
-#define SYS_CLKRST_DMA2D_RSTN_V  0x1
-#define SYS_CLKRST_DMA2D_RSTN_S  1
-/* SYS_CLKRST_DMA2D_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_DMA2D_CLK_EN    (BIT(0))
-#define SYS_CLKRST_DMA2D_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_DMA2D_CLK_EN_V  0x1
-#define SYS_CLKRST_DMA2D_CLK_EN_S  0
-
-#define SYS_CLKRST_PPA_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x48)
-/* SYS_CLKRST_PPA_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PPA_FORCE_NORST    (BIT(2))
-#define SYS_CLKRST_PPA_FORCE_NORST_M  (BIT(2))
-#define SYS_CLKRST_PPA_FORCE_NORST_V  0x1
-#define SYS_CLKRST_PPA_FORCE_NORST_S  2
-/* SYS_CLKRST_PPA_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_PPA_RSTN    (BIT(1))
-#define SYS_CLKRST_PPA_RSTN_M  (BIT(1))
-#define SYS_CLKRST_PPA_RSTN_V  0x1
-#define SYS_CLKRST_PPA_RSTN_S  1
-/* SYS_CLKRST_PPA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_PPA_CLK_EN    (BIT(0))
-#define SYS_CLKRST_PPA_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_PPA_CLK_EN_V  0x1
-#define SYS_CLKRST_PPA_CLK_EN_S  0
-
-#define SYS_CLKRST_GDMA_DBG_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x50)
-/* SYS_CLKRST_DEBUG_CH_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_DEBUG_CH_NUM    0x00000003
-#define SYS_CLKRST_DEBUG_CH_NUM_M  ((SYS_CLKRST_DEBUG_CH_NUM_V)<<(SYS_CLKRST_DEBUG_CH_NUM_S))
-#define SYS_CLKRST_DEBUG_CH_NUM_V  0x3
-#define SYS_CLKRST_DEBUG_CH_NUM_S  0
-
-#define SYS_CLKRST_GMAC_PTP_RD0_REG          (DR_REG_SYS_CLKRST_BASE + 0x54)
-/* SYS_CLKRST_PTP_TIMESTAMP_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_PTP_TIMESTAMP_LO    0xFFFFFFFF
-#define SYS_CLKRST_PTP_TIMESTAMP_LO_M  ((SYS_CLKRST_PTP_TIMESTAMP_LO_V)<<(SYS_CLKRST_PTP_TIMESTAMP_LO_S))
-#define SYS_CLKRST_PTP_TIMESTAMP_LO_V  0xFFFFFFFF
-#define SYS_CLKRST_PTP_TIMESTAMP_LO_S  0
-
-#define SYS_CLKRST_GMAC_PTP_RD1_REG          (DR_REG_SYS_CLKRST_BASE + 0x58)
-/* SYS_CLKRST_PTP_TIMESTAMP_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_PTP_TIMESTAMP_HI    0xFFFFFFFF
-#define SYS_CLKRST_PTP_TIMESTAMP_HI_M  ((SYS_CLKRST_PTP_TIMESTAMP_HI_V)<<(SYS_CLKRST_PTP_TIMESTAMP_HI_S))
-#define SYS_CLKRST_PTP_TIMESTAMP_HI_V  0xFFFFFFFF
-#define SYS_CLKRST_PTP_TIMESTAMP_HI_S  0
-
-#define SYS_CLKRST_GMAC_PTP_PPS_REG          (DR_REG_SYS_CLKRST_BASE + 0x5C)
-/* SYS_CLKRST_PTP_PPS : RO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_PTP_PPS    (BIT(0))
-#define SYS_CLKRST_PTP_PPS_M  (BIT(0))
-#define SYS_CLKRST_PTP_PPS_V  0x1
-#define SYS_CLKRST_PTP_PPS_S  0
-
-#define SYS_CLKRST_GMAC_CLK_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x60)
-/* SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON    (BIT(13))
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_M  (BIT(13))
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_V  0x1
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_S  13
-/* SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON    (BIT(12))
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_M  (BIT(12))
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_V  0x1
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_S  12
-/* SYS_CLKRST_GMAC_FUNC_RX_CLK_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN    (BIT(11))
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_M  (BIT(11))
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_V  0x1
-#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_S  11
-/* SYS_CLKRST_GMAC_FUNC_TX_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN    (BIT(10))
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_M  (BIT(10))
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_V  0x1
-#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_S  10
-/* SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON    (BIT(9))
-#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_M  (BIT(9))
-#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_V  0x1
-#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_S  9
-/* SYS_CLKRST_REVMII_PMA_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_REVMII_PMA_CLK_EN    (BIT(8))
-#define SYS_CLKRST_REVMII_PMA_CLK_EN_M  (BIT(8))
-#define SYS_CLKRST_REVMII_PMA_CLK_EN_V  0x1
-#define SYS_CLKRST_REVMII_PMA_CLK_EN_S  8
-/* SYS_CLKRST_RMII_CLK_PORT_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_RMII_CLK_PORT_SEL    (BIT(7))
-#define SYS_CLKRST_RMII_CLK_PORT_SEL_M  (BIT(7))
-#define SYS_CLKRST_RMII_CLK_PORT_SEL_V  0x1
-#define SYS_CLKRST_RMII_CLK_PORT_SEL_S  7
-/* SYS_CLKRST_SBD_FLOWCTRL : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_SBD_FLOWCTRL    (BIT(6))
-#define SYS_CLKRST_SBD_FLOWCTRL_M  (BIT(6))
-#define SYS_CLKRST_SBD_FLOWCTRL_V  0x1
-#define SYS_CLKRST_SBD_FLOWCTRL_S  6
-/* SYS_CLKRST_PHY_INTF_SEL : R/W ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_INTF_SEL    0x00000007
-#define SYS_CLKRST_PHY_INTF_SEL_M  ((SYS_CLKRST_PHY_INTF_SEL_V)<<(SYS_CLKRST_PHY_INTF_SEL_S))
-#define SYS_CLKRST_PHY_INTF_SEL_V  0x7
-#define SYS_CLKRST_PHY_INTF_SEL_S  3
-/* SYS_CLKRST_PTP_REF_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PTP_REF_CLK_SEL    (BIT(2))
-#define SYS_CLKRST_PTP_REF_CLK_SEL_M  (BIT(2))
-#define SYS_CLKRST_PTP_REF_CLK_SEL_V  0x1
-#define SYS_CLKRST_PTP_REF_CLK_SEL_S  2
-/* SYS_CLKRST_REVERSE_GMAC_TX : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_REVERSE_GMAC_TX    (BIT(1))
-#define SYS_CLKRST_REVERSE_GMAC_TX_M  (BIT(1))
-#define SYS_CLKRST_REVERSE_GMAC_TX_V  0x1
-#define SYS_CLKRST_REVERSE_GMAC_TX_S  1
-/* SYS_CLKRST_REVERSE_GMAC_RX : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_REVERSE_GMAC_RX    (BIT(0))
-#define SYS_CLKRST_REVERSE_GMAC_RX_M  (BIT(0))
-#define SYS_CLKRST_REVERSE_GMAC_RX_V  0x1
-#define SYS_CLKRST_REVERSE_GMAC_RX_S  0
-
-#define SYS_CLKRST_OTG_PHY_CLK_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x64)
-/* SYS_CLKRST_OTG_EXT_PHY_SEL : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_OTG_EXT_PHY_SEL    (BIT(10))
-#define SYS_CLKRST_OTG_EXT_PHY_SEL_M  (BIT(10))
-#define SYS_CLKRST_OTG_EXT_PHY_SEL_V  0x1
-#define SYS_CLKRST_OTG_EXT_PHY_SEL_S  10
-/* SYS_CLKRST_PHY_REF_CLK_SEL : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_REF_CLK_SEL    (BIT(9))
-#define SYS_CLKRST_PHY_REF_CLK_SEL_M  (BIT(9))
-#define SYS_CLKRST_PHY_REF_CLK_SEL_V  0x1
-#define SYS_CLKRST_PHY_REF_CLK_SEL_S  9
-/* SYS_CLKRST_PHY_RESET_FORCE_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_RESET_FORCE_EN    (BIT(8))
-#define SYS_CLKRST_PHY_RESET_FORCE_EN_M  (BIT(8))
-#define SYS_CLKRST_PHY_RESET_FORCE_EN_V  0x1
-#define SYS_CLKRST_PHY_RESET_FORCE_EN_S  8
-/* SYS_CLKRST_PHY_RSTN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_RSTN    (BIT(7))
-#define SYS_CLKRST_PHY_RSTN_M  (BIT(7))
-#define SYS_CLKRST_PHY_RSTN_V  0x1
-#define SYS_CLKRST_PHY_RSTN_S  7
-/* SYS_CLKRST_PHY_PLL_FORCE_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_PLL_FORCE_EN    (BIT(6))
-#define SYS_CLKRST_PHY_PLL_FORCE_EN_M  (BIT(6))
-#define SYS_CLKRST_PHY_PLL_FORCE_EN_V  0x1
-#define SYS_CLKRST_PHY_PLL_FORCE_EN_S  6
-/* SYS_CLKRST_PHY_PLL_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_PLL_EN    (BIT(5))
-#define SYS_CLKRST_PHY_PLL_EN_M  (BIT(5))
-#define SYS_CLKRST_PHY_PLL_EN_V  0x1
-#define SYS_CLKRST_PHY_PLL_EN_S  5
-/* SYS_CLKRST_PHY_SUSPEND_FORCE_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN    (BIT(4))
-#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_M  (BIT(4))
-#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_V  0x1
-#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_S  4
-/* SYS_CLKRST_PHY_SUSPENDM : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_PHY_SUSPENDM    (BIT(3))
-#define SYS_CLKRST_PHY_SUSPENDM_M  (BIT(3))
-#define SYS_CLKRST_PHY_SUSPENDM_V  0x1
-#define SYS_CLKRST_PHY_SUSPENDM_S  3
-/* SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN    (BIT(2))
-#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_M  (BIT(2))
-#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_V  0x1
-#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_S  2
-/* SYS_CLKRST_OTG_SUSPENDM : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_OTG_SUSPENDM    (BIT(1))
-#define SYS_CLKRST_OTG_SUSPENDM_M  (BIT(1))
-#define SYS_CLKRST_OTG_SUSPENDM_V  0x1
-#define SYS_CLKRST_OTG_SUSPENDM_S  1
-/* SYS_CLKRST_OTG_PHY_REFCLK_MODE : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_OTG_PHY_REFCLK_MODE    (BIT(0))
-#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_M  (BIT(0))
-#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_V  0x1
-#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_S  0
-
-#define SYS_CLKRST_SYS_PERI_APB_POSTW_CNTL_REG          (DR_REG_SYS_CLKRST_BASE + 0x68)
-/* SYS_CLKRST_DSI_HOST_APB_POSTW_EN : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN    (BIT(6))
-#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_M  (BIT(6))
-#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_V  0x1
-#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_S  6
-/* SYS_CLKRST_CSI_HOST_APB_POSTW_EN : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN    (BIT(5))
-#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_M  (BIT(5))
-#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_V  0x1
-#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_S  5
-/* SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN    (BIT(4))
-#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_M  (BIT(4))
-#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_V  0x1
-#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_S  4
-/* SYS_CLKRST_USB11_APB_POSTW_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_USB11_APB_POSTW_EN    (BIT(3))
-#define SYS_CLKRST_USB11_APB_POSTW_EN_M  (BIT(3))
-#define SYS_CLKRST_USB11_APB_POSTW_EN_V  0x1
-#define SYS_CLKRST_USB11_APB_POSTW_EN_S  3
-/* SYS_CLKRST_DMA2D_APB_POSTW_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_DMA2D_APB_POSTW_EN    (BIT(2))
-#define SYS_CLKRST_DMA2D_APB_POSTW_EN_M  (BIT(2))
-#define SYS_CLKRST_DMA2D_APB_POSTW_EN_V  0x1
-#define SYS_CLKRST_DMA2D_APB_POSTW_EN_S  2
-/* SYS_CLKRST_JPEG_APB_POSTW_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_JPEG_APB_POSTW_EN    (BIT(1))
-#define SYS_CLKRST_JPEG_APB_POSTW_EN_M  (BIT(1))
-#define SYS_CLKRST_JPEG_APB_POSTW_EN_V  0x1
-#define SYS_CLKRST_JPEG_APB_POSTW_EN_S  1
-/* SYS_CLKRST_GMAC_APB_POSTW_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_GMAC_APB_POSTW_EN    (BIT(0))
-#define SYS_CLKRST_GMAC_APB_POSTW_EN_M  (BIT(0))
-#define SYS_CLKRST_GMAC_APB_POSTW_EN_V  0x1
-#define SYS_CLKRST_GMAC_APB_POSTW_EN_S  0
-
-#define SYS_CLKRST_SYS_LSLP_MEM_PD_REG          (DR_REG_SYS_CLKRST_BASE + 0x6C)
-/* SYS_CLKRST_JPEG_SDSLP_MEM_PD : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_JPEG_SDSLP_MEM_PD    (BIT(4))
-#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_M  (BIT(4))
-#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_V  0x1
-#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_S  4
-/* SYS_CLKRST_JPEG_DSLP_MEM_PD : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_JPEG_DSLP_MEM_PD    (BIT(3))
-#define SYS_CLKRST_JPEG_DSLP_MEM_PD_M  (BIT(3))
-#define SYS_CLKRST_JPEG_DSLP_MEM_PD_V  0x1
-#define SYS_CLKRST_JPEG_DSLP_MEM_PD_S  3
-/* SYS_CLKRST_JPEG_LSLP_MEM_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_JPEG_LSLP_MEM_PD    (BIT(2))
-#define SYS_CLKRST_JPEG_LSLP_MEM_PD_M  (BIT(2))
-#define SYS_CLKRST_JPEG_LSLP_MEM_PD_V  0x1
-#define SYS_CLKRST_JPEG_LSLP_MEM_PD_S  2
-/* SYS_CLKRST_PPA_LSLP_MEM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_PPA_LSLP_MEM_PD    (BIT(1))
-#define SYS_CLKRST_PPA_LSLP_MEM_PD_M  (BIT(1))
-#define SYS_CLKRST_PPA_LSLP_MEM_PD_V  0x1
-#define SYS_CLKRST_PPA_LSLP_MEM_PD_S  1
-/* SYS_CLKRST_DMA2D_LSLP_MEM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_DMA2D_LSLP_MEM_PD    (BIT(0))
-#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_M  (BIT(0))
-#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_V  0x1
-#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_S  0
-
-#define SYS_CLKRST_ECO_CELL_EN_AND_DATA_REG          (DR_REG_SYS_CLKRST_BASE + 0x70)
-/* SYS_CLKRST_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_CLK_EN    (BIT(3))
-#define SYS_CLKRST_CLK_EN_M  (BIT(3))
-#define SYS_CLKRST_CLK_EN_V  0x1
-#define SYS_CLKRST_CLK_EN_S  3
-/* SYS_CLKRST_BIT_IN : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_BIT_IN    (BIT(2))
-#define SYS_CLKRST_BIT_IN_M  (BIT(2))
-#define SYS_CLKRST_BIT_IN_V  0x1
-#define SYS_CLKRST_BIT_IN_S  2
-/* SYS_CLKRST_BIT_OUT : RO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_BIT_OUT    (BIT(1))
-#define SYS_CLKRST_BIT_OUT_M  (BIT(1))
-#define SYS_CLKRST_BIT_OUT_V  0x1
-#define SYS_CLKRST_BIT_OUT_S  1
-/* SYS_CLKRST_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define SYS_CLKRST_EN    (BIT(0))
-#define SYS_CLKRST_EN_M  (BIT(0))
-#define SYS_CLKRST_EN_V  0x1
-#define SYS_CLKRST_EN_S  0
-
-#define SYS_CLKRST_USB_MEM_AUX_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x74)
-/* SYS_CLKRST_OTG_PHY_BISTEN : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_OTG_PHY_BISTEN    (BIT(15))
-#define SYS_CLKRST_OTG_PHY_BISTEN_M  (BIT(15))
-#define SYS_CLKRST_OTG_PHY_BISTEN_V  0x1
-#define SYS_CLKRST_OTG_PHY_BISTEN_S  15
-/* SYS_CLKRST_OTG_PHY_TEST_DONE : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_OTG_PHY_TEST_DONE    (BIT(14))
-#define SYS_CLKRST_OTG_PHY_TEST_DONE_M  (BIT(14))
-#define SYS_CLKRST_OTG_PHY_TEST_DONE_V  0x1
-#define SYS_CLKRST_OTG_PHY_TEST_DONE_S  14
-/* SYS_CLKRST_USB_MEM_AUX_CTRL : R/W ;bitpos:[13:0] ;default: 14'h1320 ; */
-/*description: .*/
-#define SYS_CLKRST_USB_MEM_AUX_CTRL    0x00003FFF
-#define SYS_CLKRST_USB_MEM_AUX_CTRL_M  ((SYS_CLKRST_USB_MEM_AUX_CTRL_V)<<(SYS_CLKRST_USB_MEM_AUX_CTRL_S))
-#define SYS_CLKRST_USB_MEM_AUX_CTRL_V  0x3FFF
-#define SYS_CLKRST_USB_MEM_AUX_CTRL_S  0
-
-#define SYS_CLKRST_DUAL_MSPI_CTRL_REG          (DR_REG_SYS_CLKRST_BASE + 0x78)
-/* SYS_CLKRST_DUAL_MSPI_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST    (BIT(2))
-#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_M  (BIT(2))
-#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_V  0x1
-#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_S  2
-/* SYS_CLKRST_DUAL_MSPI_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_DUAL_MSPI_RSTN    (BIT(1))
-#define SYS_CLKRST_DUAL_MSPI_RSTN_M  (BIT(1))
-#define SYS_CLKRST_DUAL_MSPI_RSTN_V  0x1
-#define SYS_CLKRST_DUAL_MSPI_RSTN_S  1
-/* SYS_CLKRST_DUAL_MSPI_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN    (BIT(0))
-#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_M  (BIT(0))
-#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_V  0x1
-#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_S  0
-
-#define SYS_CLKRST_HP_PERI_RDN_ECO_CS_REG          (DR_REG_SYS_CLKRST_BASE + 0x7C)
-/* SYS_CLKRST_HP_PERI_RDN_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT    (BIT(1))
-#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_M  (BIT(1))
-#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_V  0x1
-#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_S  1
-/* SYS_CLKRST_HP_PERI_RDN_ECO_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_HP_PERI_RDN_ECO_EN    (BIT(0))
-#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_M  (BIT(0))
-#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_V  0x1
-#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_S  0
-
-#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_REG          (DR_REG_SYS_CLKRST_BASE + 0x80)
-/* SYS_CLKRST_HP_PERI_RDN_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW    0xFFFFFFFF
-#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_M  ((SYS_CLKRST_HP_PERI_RDN_ECO_LOW_V)<<(SYS_CLKRST_HP_PERI_RDN_ECO_LOW_S))
-#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_V  0xFFFFFFFF
-#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_S  0
-
-#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_REG          (DR_REG_SYS_CLKRST_BASE + 0x84)
-/* SYS_CLKRST_HP_PERI_RDN_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: .*/
-#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH    0xFFFFFFFF
-#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_M  ((SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_V)<<(SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_S))
-#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_V  0xFFFFFFFF
-#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYS_CLKRST_REG_H_ */
diff --git a/components/soc/esp32p4/include/soc/tee_reg.h b/components/soc/esp32p4/include/soc/tee_reg.h
deleted file mode 100644
index 553ad23442..0000000000
--- a/components/soc/esp32p4/include/soc/tee_reg.h
+++ /dev/null
@@ -1,455 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TEE_M0_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
-/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M0_MODE    0x00000003U
-#define TEE_M0_MODE_M  (TEE_M0_MODE_V << TEE_M0_MODE_S)
-#define TEE_M0_MODE_V  0x00000003U
-#define TEE_M0_MODE_S  0
-
-/** TEE_M1_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
-/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M1_MODE    0x00000003U
-#define TEE_M1_MODE_M  (TEE_M1_MODE_V << TEE_M1_MODE_S)
-#define TEE_M1_MODE_V  0x00000003U
-#define TEE_M1_MODE_S  0
-
-/** TEE_M2_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
-/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0;
- *  M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M2_MODE    0x00000003U
-#define TEE_M2_MODE_M  (TEE_M2_MODE_V << TEE_M2_MODE_S)
-#define TEE_M2_MODE_V  0x00000003U
-#define TEE_M2_MODE_S  0
-
-/** TEE_M3_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
-/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M3_MODE    0x00000003U
-#define TEE_M3_MODE_M  (TEE_M3_MODE_V << TEE_M3_MODE_S)
-#define TEE_M3_MODE_V  0x00000003U
-#define TEE_M3_MODE_S  0
-
-/** TEE_M4_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
-/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M4_MODE    0x00000003U
-#define TEE_M4_MODE_M  (TEE_M4_MODE_V << TEE_M4_MODE_S)
-#define TEE_M4_MODE_V  0x00000003U
-#define TEE_M4_MODE_S  0
-
-/** TEE_M5_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
-/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M5_MODE    0x00000003U
-#define TEE_M5_MODE_M  (TEE_M5_MODE_V << TEE_M5_MODE_S)
-#define TEE_M5_MODE_V  0x00000003U
-#define TEE_M5_MODE_S  0
-
-/** TEE_M6_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
-/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M6_MODE    0x00000003U
-#define TEE_M6_MODE_M  (TEE_M6_MODE_V << TEE_M6_MODE_S)
-#define TEE_M6_MODE_V  0x00000003U
-#define TEE_M6_MODE_S  0
-
-/** TEE_M7_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
-/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M7_MODE    0x00000003U
-#define TEE_M7_MODE_M  (TEE_M7_MODE_V << TEE_M7_MODE_S)
-#define TEE_M7_MODE_V  0x00000003U
-#define TEE_M7_MODE_S  0
-
-/** TEE_M8_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
-/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M8_MODE    0x00000003U
-#define TEE_M8_MODE_M  (TEE_M8_MODE_V << TEE_M8_MODE_S)
-#define TEE_M8_MODE_V  0x00000003U
-#define TEE_M8_MODE_S  0
-
-/** TEE_M9_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
-/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M9_MODE    0x00000003U
-#define TEE_M9_MODE_M  (TEE_M9_MODE_V << TEE_M9_MODE_S)
-#define TEE_M9_MODE_V  0x00000003U
-#define TEE_M9_MODE_S  0
-
-/** TEE_M10_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28)
-/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M10_MODE    0x00000003U
-#define TEE_M10_MODE_M  (TEE_M10_MODE_V << TEE_M10_MODE_S)
-#define TEE_M10_MODE_V  0x00000003U
-#define TEE_M10_MODE_S  0
-
-/** TEE_M11_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c)
-/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M11_MODE    0x00000003U
-#define TEE_M11_MODE_M  (TEE_M11_MODE_V << TEE_M11_MODE_S)
-#define TEE_M11_MODE_V  0x00000003U
-#define TEE_M11_MODE_S  0
-
-/** TEE_M12_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30)
-/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M12_MODE    0x00000003U
-#define TEE_M12_MODE_M  (TEE_M12_MODE_V << TEE_M12_MODE_S)
-#define TEE_M12_MODE_V  0x00000003U
-#define TEE_M12_MODE_S  0
-
-/** TEE_M13_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34)
-/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M13_MODE    0x00000003U
-#define TEE_M13_MODE_M  (TEE_M13_MODE_V << TEE_M13_MODE_S)
-#define TEE_M13_MODE_V  0x00000003U
-#define TEE_M13_MODE_S  0
-
-/** TEE_M14_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38)
-/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M14_MODE    0x00000003U
-#define TEE_M14_MODE_M  (TEE_M14_MODE_V << TEE_M14_MODE_S)
-#define TEE_M14_MODE_V  0x00000003U
-#define TEE_M14_MODE_S  0
-
-/** TEE_M15_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c)
-/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M15_MODE    0x00000003U
-#define TEE_M15_MODE_M  (TEE_M15_MODE_V << TEE_M15_MODE_S)
-#define TEE_M15_MODE_V  0x00000003U
-#define TEE_M15_MODE_S  0
-
-/** TEE_M16_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40)
-/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M16_MODE    0x00000003U
-#define TEE_M16_MODE_M  (TEE_M16_MODE_V << TEE_M16_MODE_S)
-#define TEE_M16_MODE_V  0x00000003U
-#define TEE_M16_MODE_S  0
-
-/** TEE_M17_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44)
-/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M17_MODE    0x00000003U
-#define TEE_M17_MODE_M  (TEE_M17_MODE_V << TEE_M17_MODE_S)
-#define TEE_M17_MODE_V  0x00000003U
-#define TEE_M17_MODE_S  0
-
-/** TEE_M18_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48)
-/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M18_MODE    0x00000003U
-#define TEE_M18_MODE_M  (TEE_M18_MODE_V << TEE_M18_MODE_S)
-#define TEE_M18_MODE_V  0x00000003U
-#define TEE_M18_MODE_S  0
-
-/** TEE_M19_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c)
-/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M19_MODE    0x00000003U
-#define TEE_M19_MODE_M  (TEE_M19_MODE_V << TEE_M19_MODE_S)
-#define TEE_M19_MODE_V  0x00000003U
-#define TEE_M19_MODE_S  0
-
-/** TEE_M20_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50)
-/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M20_MODE    0x00000003U
-#define TEE_M20_MODE_M  (TEE_M20_MODE_V << TEE_M20_MODE_S)
-#define TEE_M20_MODE_V  0x00000003U
-#define TEE_M20_MODE_S  0
-
-/** TEE_M21_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54)
-/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M21_MODE    0x00000003U
-#define TEE_M21_MODE_M  (TEE_M21_MODE_V << TEE_M21_MODE_S)
-#define TEE_M21_MODE_V  0x00000003U
-#define TEE_M21_MODE_S  0
-
-/** TEE_M22_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58)
-/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M22_MODE    0x00000003U
-#define TEE_M22_MODE_M  (TEE_M22_MODE_V << TEE_M22_MODE_S)
-#define TEE_M22_MODE_V  0x00000003U
-#define TEE_M22_MODE_S  0
-
-/** TEE_M23_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c)
-/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M23_MODE    0x00000003U
-#define TEE_M23_MODE_M  (TEE_M23_MODE_V << TEE_M23_MODE_S)
-#define TEE_M23_MODE_V  0x00000003U
-#define TEE_M23_MODE_S  0
-
-/** TEE_M24_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60)
-/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M24_MODE    0x00000003U
-#define TEE_M24_MODE_M  (TEE_M24_MODE_V << TEE_M24_MODE_S)
-#define TEE_M24_MODE_V  0x00000003U
-#define TEE_M24_MODE_S  0
-
-/** TEE_M25_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64)
-/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M25_MODE    0x00000003U
-#define TEE_M25_MODE_M  (TEE_M25_MODE_V << TEE_M25_MODE_S)
-#define TEE_M25_MODE_V  0x00000003U
-#define TEE_M25_MODE_S  0
-
-/** TEE_M26_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68)
-/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M26_MODE    0x00000003U
-#define TEE_M26_MODE_M  (TEE_M26_MODE_V << TEE_M26_MODE_S)
-#define TEE_M26_MODE_V  0x00000003U
-#define TEE_M26_MODE_S  0
-
-/** TEE_M27_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c)
-/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M27_MODE    0x00000003U
-#define TEE_M27_MODE_M  (TEE_M27_MODE_V << TEE_M27_MODE_S)
-#define TEE_M27_MODE_V  0x00000003U
-#define TEE_M27_MODE_S  0
-
-/** TEE_M28_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70)
-/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M28_MODE    0x00000003U
-#define TEE_M28_MODE_M  (TEE_M28_MODE_V << TEE_M28_MODE_S)
-#define TEE_M28_MODE_V  0x00000003U
-#define TEE_M28_MODE_S  0
-
-/** TEE_M29_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74)
-/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M29_MODE    0x00000003U
-#define TEE_M29_MODE_M  (TEE_M29_MODE_V << TEE_M29_MODE_S)
-#define TEE_M29_MODE_V  0x00000003U
-#define TEE_M29_MODE_S  0
-
-/** TEE_M30_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78)
-/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M30_MODE    0x00000003U
-#define TEE_M30_MODE_M  (TEE_M30_MODE_V << TEE_M30_MODE_S)
-#define TEE_M30_MODE_V  0x00000003U
-#define TEE_M30_MODE_S  0
-
-/** TEE_M31_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c)
-/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M31_MODE    0x00000003U
-#define TEE_M31_MODE_M  (TEE_M31_MODE_V << TEE_M31_MODE_S)
-#define TEE_M31_MODE_V  0x00000003U
-#define TEE_M31_MODE_S  0
-
-/** TEE_CLOCK_GATE_REG register
- *  Clock gating register
- */
-#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80)
-/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define TEE_CLK_EN    (BIT(0))
-#define TEE_CLK_EN_M  (TEE_CLK_EN_V << TEE_CLK_EN_S)
-#define TEE_CLK_EN_V  0x00000001U
-#define TEE_CLK_EN_S  0
-
-/** TEE_DATE_REG register
- *  Version register
- */
-#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc)
-/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706;
- *  reg_tee_date
- */
-#define TEE_DATE_REG_M  (TEE_DATE_REG_V << TEE_DATE_REG_S)
-#define TEE_DATE_REG_V  0x0FFFFFFFU
-#define TEE_DATE_REG_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/tee_struct.h b/components/soc/esp32p4/include/soc/tee_struct.h
deleted file mode 100644
index 47f806da1a..0000000000
--- a/components/soc/esp32p4/include/soc/tee_struct.h
+++ /dev/null
@@ -1,573 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Tee mode control register */
-/** Type of m0_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m0_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m0_mode_ctrl_reg_t;
-
-/** Type of m1_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m1_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m1_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m1_mode_ctrl_reg_t;
-
-/** Type of m2_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m2_mode : R/W; bitpos: [1:0]; default: 0;
-         *  M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m2_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m2_mode_ctrl_reg_t;
-
-/** Type of m3_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m3_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m3_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m3_mode_ctrl_reg_t;
-
-/** Type of m4_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m4_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m4_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m4_mode_ctrl_reg_t;
-
-/** Type of m5_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m5_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m5_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m5_mode_ctrl_reg_t;
-
-/** Type of m6_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m6_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m6_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m6_mode_ctrl_reg_t;
-
-/** Type of m7_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m7_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m7_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m7_mode_ctrl_reg_t;
-
-/** Type of m8_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m8_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m8_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m8_mode_ctrl_reg_t;
-
-/** Type of m9_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m9_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m9_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m9_mode_ctrl_reg_t;
-
-/** Type of m10_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m10_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m10_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m10_mode_ctrl_reg_t;
-
-/** Type of m11_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m11_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m11_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m11_mode_ctrl_reg_t;
-
-/** Type of m12_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m12_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m12_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m12_mode_ctrl_reg_t;
-
-/** Type of m13_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m13_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m13_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m13_mode_ctrl_reg_t;
-
-/** Type of m14_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m14_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m14_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m14_mode_ctrl_reg_t;
-
-/** Type of m15_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m15_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m15_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m15_mode_ctrl_reg_t;
-
-/** Type of m16_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m16_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m16_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m16_mode_ctrl_reg_t;
-
-/** Type of m17_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m17_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m17_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m17_mode_ctrl_reg_t;
-
-/** Type of m18_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m18_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m18_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m18_mode_ctrl_reg_t;
-
-/** Type of m19_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m19_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m19_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m19_mode_ctrl_reg_t;
-
-/** Type of m20_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m20_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m20_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m20_mode_ctrl_reg_t;
-
-/** Type of m21_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m21_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m21_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m21_mode_ctrl_reg_t;
-
-/** Type of m22_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m22_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m22_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m22_mode_ctrl_reg_t;
-
-/** Type of m23_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m23_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m23_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m23_mode_ctrl_reg_t;
-
-/** Type of m24_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m24_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m24_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m24_mode_ctrl_reg_t;
-
-/** Type of m25_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m25_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m25_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m25_mode_ctrl_reg_t;
-
-/** Type of m26_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m26_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m26_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m26_mode_ctrl_reg_t;
-
-/** Type of m27_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m27_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m27_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m27_mode_ctrl_reg_t;
-
-/** Type of m28_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m28_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m28_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m28_mode_ctrl_reg_t;
-
-/** Type of m29_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m29_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m29_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m29_mode_ctrl_reg_t;
-
-/** Type of m30_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m30_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m30_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m30_mode_ctrl_reg_t;
-
-/** Type of m31_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m31_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m31_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} tee_m31_mode_ctrl_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  Clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} tee_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date_reg : R/W; bitpos: [27:0]; default: 35672706;
-         *  reg_tee_date
-         */
-        uint32_t date_reg:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} tee_date_reg_t;
-
-
-typedef struct tee_dev_t {
-    volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
-    volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
-    volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;
-    volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl;
-    volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl;
-    volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl;
-    volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl;
-    volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl;
-    volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl;
-    volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl;
-    volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl;
-    volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl;
-    volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl;
-    volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl;
-    volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl;
-    volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl;
-    volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl;
-    volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl;
-    volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl;
-    volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl;
-    volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl;
-    volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl;
-    volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl;
-    volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl;
-    volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl;
-    volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl;
-    volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl;
-    volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl;
-    volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl;
-    volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl;
-    volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl;
-    volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl;
-    volatile tee_clock_gate_reg_t clock_gate;
-    uint32_t reserved_084[990];
-    volatile tee_date_reg_t date;
-} tee_dev_t;
-
-extern tee_dev_t TEE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/twaifd_reg.h b/components/soc/esp32p4/include/soc/twaifd_reg.h
deleted file mode 100644
index 933e0dc154..0000000000
--- a/components/soc/esp32p4/include/soc/twaifd_reg.h
+++ /dev/null
@@ -1,1795 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TWAIFD_DEVICE_ID_REG register
- *  TWAI FD device id status register
- */
-#define TWAIFD_DEVICE_ID_REG (DR_REG_TWAIFD_BASE + 0x0)
-/** TWAIFD_DEVICE_ID : R/W; bitpos: [31:0]; default: 51965;
- *  Represents whether CAN IP function is mapped correctly on its base address.
- */
-#define TWAIFD_DEVICE_ID    0xFFFFFFFFU
-#define TWAIFD_DEVICE_ID_M  (TWAIFD_DEVICE_ID_V << TWAIFD_DEVICE_ID_S)
-#define TWAIFD_DEVICE_ID_V  0xFFFFFFFFU
-#define TWAIFD_DEVICE_ID_S  0
-
-/** TWAIFD_MODE_SETTING_REG register
- *  TWAI FD mode setting register
- */
-#define TWAIFD_MODE_SETTING_REG (DR_REG_TWAIFD_BASE + 0x4)
-/** TWAIFD_SW_RESET : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to reset the TWAI FD controller.\\
- *  0: invalid\\
- *  1: reset.\\
- */
-#define TWAIFD_SW_RESET    (BIT(0))
-#define TWAIFD_SW_RESET_M  (TWAIFD_SW_RESET_V << TWAIFD_SW_RESET_S)
-#define TWAIFD_SW_RESET_V  0x00000001U
-#define TWAIFD_SW_RESET_S  0
-/** TWAIFD_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
- *  bus monitor enable
- */
-#define TWAIFD_LISTEN_ONLY_MODE    (BIT(1))
-#define TWAIFD_LISTEN_ONLY_MODE_M  (TWAIFD_LISTEN_ONLY_MODE_V << TWAIFD_LISTEN_ONLY_MODE_S)
-#define TWAIFD_LISTEN_ONLY_MODE_V  0x00000001U
-#define TWAIFD_LISTEN_ONLY_MODE_S  1
-/** TWAIFD_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable the self test mode.\\
- *  0: disable\\
- *  1: enable\\
- */
-#define TWAIFD_SELF_TEST_MODE    (BIT(2))
-#define TWAIFD_SELF_TEST_MODE_M  (TWAIFD_SELF_TEST_MODE_V << TWAIFD_SELF_TEST_MODE_S)
-#define TWAIFD_SELF_TEST_MODE_V  0x00000001U
-#define TWAIFD_SELF_TEST_MODE_S  2
-/** TWAIFD_ACCEPT_FILTER_MODE : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable the usage of acceptance filters.\\
- *  0: disable\\
- *  1: enable\\
- */
-#define TWAIFD_ACCEPT_FILTER_MODE    (BIT(3))
-#define TWAIFD_ACCEPT_FILTER_MODE_M  (TWAIFD_ACCEPT_FILTER_MODE_V << TWAIFD_ACCEPT_FILTER_MODE_S)
-#define TWAIFD_ACCEPT_FILTER_MODE_V  0x00000001U
-#define TWAIFD_ACCEPT_FILTER_MODE_S  3
-/** TWAIFD_FLEXIBLE_DATA_RATE : R/W; bitpos: [4]; default: 1;
- *  Configures whether or not to support flexible data rate.\\
- *  0: not support\\
- *  1: support\\
- */
-#define TWAIFD_FLEXIBLE_DATA_RATE    (BIT(4))
-#define TWAIFD_FLEXIBLE_DATA_RATE_M  (TWAIFD_FLEXIBLE_DATA_RATE_V << TWAIFD_FLEXIBLE_DATA_RATE_S)
-#define TWAIFD_FLEXIBLE_DATA_RATE_V  0x00000001U
-#define TWAIFD_FLEXIBLE_DATA_RATE_S  4
-/** TWAIFD_RTR_FRM_BEHAVIOR : R/W; bitpos: [5]; default: 0;
- *  time_triggered transmission mode
- */
-#define TWAIFD_RTR_FRM_BEHAVIOR    (BIT(5))
-#define TWAIFD_RTR_FRM_BEHAVIOR_M  (TWAIFD_RTR_FRM_BEHAVIOR_V << TWAIFD_RTR_FRM_BEHAVIOR_S)
-#define TWAIFD_RTR_FRM_BEHAVIOR_V  0x00000001U
-#define TWAIFD_RTR_FRM_BEHAVIOR_S  5
-/** TWAIFD_ROM : R/W; bitpos: [6]; default: 0;
- *  a\\
- */
-#define TWAIFD_ROM    (BIT(6))
-#define TWAIFD_ROM_M  (TWAIFD_ROM_V << TWAIFD_ROM_S)
-#define TWAIFD_ROM_V  0x00000001U
-#define TWAIFD_ROM_S  6
-/** TWAIFD_ACK_BEHAVIOR : R/W; bitpos: [7]; default: 0;
- *  Configures the acknowledge behavior.\\
- *  0: normal behavior.\\
- *  1: acknowledge is not sent.\\
- */
-#define TWAIFD_ACK_BEHAVIOR    (BIT(7))
-#define TWAIFD_ACK_BEHAVIOR_M  (TWAIFD_ACK_BEHAVIOR_V << TWAIFD_ACK_BEHAVIOR_S)
-#define TWAIFD_ACK_BEHAVIOR_V  0x00000001U
-#define TWAIFD_ACK_BEHAVIOR_S  7
-/** TWAIFD_TEST_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable the triple sampling mode.\\
- *  0: disable\\
- *  1: enable\\
- */
-#define TWAIFD_TEST_MODE    (BIT(8))
-#define TWAIFD_TEST_MODE_M  (TWAIFD_TEST_MODE_V << TWAIFD_TEST_MODE_S)
-#define TWAIFD_TEST_MODE_V  0x00000001U
-#define TWAIFD_TEST_MODE_S  8
-/** TWAIFD_RXBAM : R/W; bitpos: [9]; default: 1;
- *  a\\
- */
-#define TWAIFD_RXBAM    (BIT(9))
-#define TWAIFD_RXBAM_M  (TWAIFD_RXBAM_V << TWAIFD_RXBAM_S)
-#define TWAIFD_RXBAM_V  0x00000001U
-#define TWAIFD_RXBAM_S  9
-/** TWAIFD_LIMIT_RETX_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the limit of retransmission.\\
- *  0: disable\\
- *  1: enable\\
- */
-#define TWAIFD_LIMIT_RETX_EN    (BIT(16))
-#define TWAIFD_LIMIT_RETX_EN_M  (TWAIFD_LIMIT_RETX_EN_V << TWAIFD_LIMIT_RETX_EN_S)
-#define TWAIFD_LIMIT_RETX_EN_V  0x00000001U
-#define TWAIFD_LIMIT_RETX_EN_S  16
-/** TWAIFD_RETX_THRES : R/W; bitpos: [20:17]; default: 0;
- *  Configures the threshold of retransmission attempts. \\
- */
-#define TWAIFD_RETX_THRES    0x0000000FU
-#define TWAIFD_RETX_THRES_M  (TWAIFD_RETX_THRES_V << TWAIFD_RETX_THRES_S)
-#define TWAIFD_RETX_THRES_V  0x0000000FU
-#define TWAIFD_RETX_THRES_S  17
-/** TWAIFD_ILBP : R/W; bitpos: [21]; default: 0;
- *  acknowledge forbidden mode
- */
-#define TWAIFD_ILBP    (BIT(21))
-#define TWAIFD_ILBP_M  (TWAIFD_ILBP_V << TWAIFD_ILBP_S)
-#define TWAIFD_ILBP_V  0x00000001U
-#define TWAIFD_ILBP_S  21
-/** TWAIFD_CTRL_EN : R/W; bitpos: [22]; default: 0;
- *  Configures whether or not to enable the twai FD controller.\\
- *  0: disable\\
- *  1: enable\\
- */
-#define TWAIFD_CTRL_EN    (BIT(22))
-#define TWAIFD_CTRL_EN_M  (TWAIFD_CTRL_EN_V << TWAIFD_CTRL_EN_S)
-#define TWAIFD_CTRL_EN_V  0x00000001U
-#define TWAIFD_CTRL_EN_S  22
-/** TWAIFD_FD_TYPE : R/W; bitpos: [23]; default: 0;
- *  Configure the twai fd frame type.\\
- *  0: ISO CAN FD\\
- *  1: CAN FD 1.0\\
- */
-#define TWAIFD_FD_TYPE    (BIT(23))
-#define TWAIFD_FD_TYPE_M  (TWAIFD_FD_TYPE_V << TWAIFD_FD_TYPE_S)
-#define TWAIFD_FD_TYPE_V  0x00000001U
-#define TWAIFD_FD_TYPE_S  23
-/** TWAIFD_PEX : R/W; bitpos: [24]; default: 0;
- *  protocol expection mode\\
- */
-#define TWAIFD_PEX    (BIT(24))
-#define TWAIFD_PEX_M  (TWAIFD_PEX_V << TWAIFD_PEX_S)
-#define TWAIFD_PEX_V  0x00000001U
-#define TWAIFD_PEX_S  24
-/** TWAIFD_TBFBO : R/W; bitpos: [25]; default: 1;
- *  a\\
- */
-#define TWAIFD_TBFBO    (BIT(25))
-#define TWAIFD_TBFBO_M  (TWAIFD_TBFBO_V << TWAIFD_TBFBO_S)
-#define TWAIFD_TBFBO_V  0x00000001U
-#define TWAIFD_TBFBO_S  25
-/** TWAIFD_FDRF : R/W; bitpos: [26]; default: 0;
- *  a\\
- */
-#define TWAIFD_FDRF    (BIT(26))
-#define TWAIFD_FDRF_M  (TWAIFD_FDRF_V << TWAIFD_FDRF_S)
-#define TWAIFD_FDRF_V  0x00000001U
-#define TWAIFD_FDRF_S  26
-
-/** TWAIFD_COMMAND_REG register
- *  TWAI FD command register
- */
-#define TWAIFD_COMMAND_REG (DR_REG_TWAIFD_BASE + 0x8)
-/** TWAIFD_RXRPMV : WO; bitpos: [1]; default: 0;
- *  a\\
- */
-#define TWAIFD_RXRPMV    (BIT(1))
-#define TWAIFD_RXRPMV_M  (TWAIFD_RXRPMV_V << TWAIFD_RXRPMV_S)
-#define TWAIFD_RXRPMV_V  0x00000001U
-#define TWAIFD_RXRPMV_S  1
-/** TWAIFD_RELEASE_RX_BUF : WO; bitpos: [2]; default: 0;
- *  Configures whether or not to delete all data from the receive buffer.\\
- *  0: invalid\\
- *  1: delete\\
- */
-#define TWAIFD_RELEASE_RX_BUF    (BIT(2))
-#define TWAIFD_RELEASE_RX_BUF_M  (TWAIFD_RELEASE_RX_BUF_V << TWAIFD_RELEASE_RX_BUF_S)
-#define TWAIFD_RELEASE_RX_BUF_V  0x00000001U
-#define TWAIFD_RELEASE_RX_BUF_S  2
-/** TWAIFD_CLR_OVERRUN_FLG : WO; bitpos: [3]; default: 0;
- *  Configures whether or not to clear the data overrun flag.\\
- *  0: invalid\\
- *  1: clear\\
- */
-#define TWAIFD_CLR_OVERRUN_FLG    (BIT(3))
-#define TWAIFD_CLR_OVERRUN_FLG_M  (TWAIFD_CLR_OVERRUN_FLG_V << TWAIFD_CLR_OVERRUN_FLG_S)
-#define TWAIFD_CLR_OVERRUN_FLG_V  0x00000001U
-#define TWAIFD_CLR_OVERRUN_FLG_S  3
-/** TWAIFD_ERCRST : WO; bitpos: [4]; default: 0;
- *  a\\
- */
-#define TWAIFD_ERCRST    (BIT(4))
-#define TWAIFD_ERCRST_M  (TWAIFD_ERCRST_V << TWAIFD_ERCRST_S)
-#define TWAIFD_ERCRST_V  0x00000001U
-#define TWAIFD_ERCRST_S  4
-/** TWAIFD_RXFCRST : WO; bitpos: [5]; default: 0;
- *  a\\
- */
-#define TWAIFD_RXFCRST    (BIT(5))
-#define TWAIFD_RXFCRST_M  (TWAIFD_RXFCRST_V << TWAIFD_RXFCRST_S)
-#define TWAIFD_RXFCRST_V  0x00000001U
-#define TWAIFD_RXFCRST_S  5
-/** TWAIFD_TXFCRST : WO; bitpos: [6]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXFCRST    (BIT(6))
-#define TWAIFD_TXFCRST_M  (TWAIFD_TXFCRST_V << TWAIFD_TXFCRST_S)
-#define TWAIFD_TXFCRST_V  0x00000001U
-#define TWAIFD_TXFCRST_S  6
-/** TWAIFD_CPEXS : WO; bitpos: [7]; default: 0;
- *  a\\
- */
-#define TWAIFD_CPEXS    (BIT(7))
-#define TWAIFD_CPEXS_M  (TWAIFD_CPEXS_V << TWAIFD_CPEXS_S)
-#define TWAIFD_CPEXS_V  0x00000001U
-#define TWAIFD_CPEXS_S  7
-
-/** TWAIFD_STATUS_REG register
- *  TWAI FD status register
- */
-#define TWAIFD_STATUS_REG (DR_REG_TWAIFD_BASE + 0xc)
-/** TWAIFD_RX_BUF_STAT : RO; bitpos: [0]; default: 0;
- *  Represents whether or not the receive buffer is empty.\\
- *  0: empty\\
- *  1: not empty\\
- */
-#define TWAIFD_RX_BUF_STAT    (BIT(0))
-#define TWAIFD_RX_BUF_STAT_M  (TWAIFD_RX_BUF_STAT_V << TWAIFD_RX_BUF_STAT_S)
-#define TWAIFD_RX_BUF_STAT_V  0x00000001U
-#define TWAIFD_RX_BUF_STAT_S  0
-/** TWAIFD_DATA_OVERRUN_FLG : RO; bitpos: [1]; default: 0;
- *  Represents whether or not the receive buffer is full and the frame is
- *  overrun(lost).\\
- *  0: not overrun\\
- *  1: overrun\\
- */
-#define TWAIFD_DATA_OVERRUN_FLG    (BIT(1))
-#define TWAIFD_DATA_OVERRUN_FLG_M  (TWAIFD_DATA_OVERRUN_FLG_V << TWAIFD_DATA_OVERRUN_FLG_S)
-#define TWAIFD_DATA_OVERRUN_FLG_V  0x00000001U
-#define TWAIFD_DATA_OVERRUN_FLG_S  1
-/** TWAIFD_TX_BUF_SAT : RO; bitpos: [2]; default: 0;
- *  Represents whether or not the transmit buffer is full.\\
- *  0: not full\\
- *  1: full\\
- */
-#define TWAIFD_TX_BUF_SAT    (BIT(2))
-#define TWAIFD_TX_BUF_SAT_M  (TWAIFD_TX_BUF_SAT_V << TWAIFD_TX_BUF_SAT_S)
-#define TWAIFD_TX_BUF_SAT_V  0x00000001U
-#define TWAIFD_TX_BUF_SAT_S  2
-/** TWAIFD_ERR_FRM_TX : RO; bitpos: [3]; default: 0;
- *  Represents whether or not the error frame is being transmitted.\\
- *  0: not being transmitted\\
- *  1: being transmitted\\
- */
-#define TWAIFD_ERR_FRM_TX    (BIT(3))
-#define TWAIFD_ERR_FRM_TX_M  (TWAIFD_ERR_FRM_TX_V << TWAIFD_ERR_FRM_TX_S)
-#define TWAIFD_ERR_FRM_TX_V  0x00000001U
-#define TWAIFD_ERR_FRM_TX_S  3
-/** TWAIFD_RX_FRM_STAT : RO; bitpos: [4]; default: 0;
- *  Represents whether or not the controller is receiving a frame.\\
- *  0: not receiving\\
- *  1: receiving\\
- */
-#define TWAIFD_RX_FRM_STAT    (BIT(4))
-#define TWAIFD_RX_FRM_STAT_M  (TWAIFD_RX_FRM_STAT_V << TWAIFD_RX_FRM_STAT_S)
-#define TWAIFD_RX_FRM_STAT_V  0x00000001U
-#define TWAIFD_RX_FRM_STAT_S  4
-/** TWAIFD_TX_FRM_STAT : RO; bitpos: [5]; default: 0;
- *  Represents whether or not the controller is transmitting a frame.\\
- *  0: not transmitting\\
- *  1: transmitting\\
- */
-#define TWAIFD_TX_FRM_STAT    (BIT(5))
-#define TWAIFD_TX_FRM_STAT_M  (TWAIFD_TX_FRM_STAT_V << TWAIFD_TX_FRM_STAT_S)
-#define TWAIFD_TX_FRM_STAT_V  0x00000001U
-#define TWAIFD_TX_FRM_STAT_S  5
-/** TWAIFD_ERR_STAT : RO; bitpos: [6]; default: 0;
- *  Represents whether or not the error warning limit is reached.\\
- *  0: not reached\\
- *  1: reached\\
- */
-#define TWAIFD_ERR_STAT    (BIT(6))
-#define TWAIFD_ERR_STAT_M  (TWAIFD_ERR_STAT_V << TWAIFD_ERR_STAT_S)
-#define TWAIFD_ERR_STAT_V  0x00000001U
-#define TWAIFD_ERR_STAT_S  6
-/** TWAIFD_BUS_STAT : RO; bitpos: [7]; default: 1;
- *  Represents whether or not bus is active.\\
- *  0: active\\
- *  1: not active\\
- */
-#define TWAIFD_BUS_STAT    (BIT(7))
-#define TWAIFD_BUS_STAT_M  (TWAIFD_BUS_STAT_V << TWAIFD_BUS_STAT_S)
-#define TWAIFD_BUS_STAT_V  0x00000001U
-#define TWAIFD_BUS_STAT_S  7
-/** TWAIFD_PEXS : RO; bitpos: [8]; default: 0;
- *  a\\
- */
-#define TWAIFD_PEXS    (BIT(8))
-#define TWAIFD_PEXS_M  (TWAIFD_PEXS_V << TWAIFD_PEXS_S)
-#define TWAIFD_PEXS_V  0x00000001U
-#define TWAIFD_PEXS_S  8
-/** TWAIFD_REINTEGRATING_WAIT : RO; bitpos: [9]; default: 0;
- *  fsm is in reintegrating wait status
- */
-#define TWAIFD_REINTEGRATING_WAIT    (BIT(9))
-#define TWAIFD_REINTEGRATING_WAIT_M  (TWAIFD_REINTEGRATING_WAIT_V << TWAIFD_REINTEGRATING_WAIT_S)
-#define TWAIFD_REINTEGRATING_WAIT_V  0x00000001U
-#define TWAIFD_REINTEGRATING_WAIT_S  9
-/** TWAIFD_STCNT : RO; bitpos: [16]; default: 0;
- *  a\\
- */
-#define TWAIFD_STCNT    (BIT(16))
-#define TWAIFD_STCNT_M  (TWAIFD_STCNT_V << TWAIFD_STCNT_S)
-#define TWAIFD_STCNT_V  0x00000001U
-#define TWAIFD_STCNT_S  16
-/** TWAIFD_STRGS : RO; bitpos: [17]; default: 0;
- *  a\\
- */
-#define TWAIFD_STRGS    (BIT(17))
-#define TWAIFD_STRGS_M  (TWAIFD_STRGS_V << TWAIFD_STRGS_S)
-#define TWAIFD_STRGS_V  0x00000001U
-#define TWAIFD_STRGS_S  17
-
-/** TWAIFD_INT_RAW_REG register
- *  TWAI FD interrupt raw register
- */
-#define TWAIFD_INT_RAW_REG (DR_REG_TWAIFD_BASE + 0x10)
-/** TWAIFD_RX_FRM_SUC_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status of TWAIFD_RX_FRM_SUC_INT.
- */
-#define TWAIFD_RX_FRM_SUC_INT_RAW    (BIT(0))
-#define TWAIFD_RX_FRM_SUC_INT_RAW_M  (TWAIFD_RX_FRM_SUC_INT_RAW_V << TWAIFD_RX_FRM_SUC_INT_RAW_S)
-#define TWAIFD_RX_FRM_SUC_INT_RAW_V  0x00000001U
-#define TWAIFD_RX_FRM_SUC_INT_RAW_S  0
-/** TWAIFD_TX_FRM_SUC_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status of TWAIFD_TX_FRM_SUC_INT.
- */
-#define TWAIFD_TX_FRM_SUC_INT_RAW    (BIT(1))
-#define TWAIFD_TX_FRM_SUC_INT_RAW_M  (TWAIFD_TX_FRM_SUC_INT_RAW_V << TWAIFD_TX_FRM_SUC_INT_RAW_S)
-#define TWAIFD_TX_FRM_SUC_INT_RAW_V  0x00000001U
-#define TWAIFD_TX_FRM_SUC_INT_RAW_S  1
-/** TWAIFD_ERR_WARNING_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status of TWAIFD_ERR_WARNING_INT.
- */
-#define TWAIFD_ERR_WARNING_INT_RAW    (BIT(2))
-#define TWAIFD_ERR_WARNING_INT_RAW_M  (TWAIFD_ERR_WARNING_INT_RAW_V << TWAIFD_ERR_WARNING_INT_RAW_S)
-#define TWAIFD_ERR_WARNING_INT_RAW_V  0x00000001U
-#define TWAIFD_ERR_WARNING_INT_RAW_S  2
-/** TWAIFD_RX_DATA_OVERRUN_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
- */
-#define TWAIFD_RX_DATA_OVERRUN_INT_RAW    (BIT(3))
-#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_M  (TWAIFD_RX_DATA_OVERRUN_INT_RAW_V << TWAIFD_RX_DATA_OVERRUN_INT_RAW_S)
-#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_V  0x00000001U
-#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_S  3
-/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
- */
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW    (BIT(5))
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_S)
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_V  0x00000001U
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_S  5
-/** TWAIFD_ARB_LOST_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt status of TWAIFD_ARB_LOST_INT.
- */
-#define TWAIFD_ARB_LOST_INT_RAW    (BIT(6))
-#define TWAIFD_ARB_LOST_INT_RAW_M  (TWAIFD_ARB_LOST_INT_RAW_V << TWAIFD_ARB_LOST_INT_RAW_S)
-#define TWAIFD_ARB_LOST_INT_RAW_V  0x00000001U
-#define TWAIFD_ARB_LOST_INT_RAW_S  6
-/** TWAIFD_ERR_DETECTED_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt status of TWAIFD_ERR_DETECTED_INT.
- */
-#define TWAIFD_ERR_DETECTED_INT_RAW    (BIT(7))
-#define TWAIFD_ERR_DETECTED_INT_RAW_M  (TWAIFD_ERR_DETECTED_INT_RAW_V << TWAIFD_ERR_DETECTED_INT_RAW_S)
-#define TWAIFD_ERR_DETECTED_INT_RAW_V  0x00000001U
-#define TWAIFD_ERR_DETECTED_INT_RAW_S  7
-/** TWAIFD_IS_OVERLOAD_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt status of TWAIFD_IS_OVERLOAD_INT.
- */
-#define TWAIFD_IS_OVERLOAD_INT_RAW    (BIT(8))
-#define TWAIFD_IS_OVERLOAD_INT_RAW_M  (TWAIFD_IS_OVERLOAD_INT_RAW_V << TWAIFD_IS_OVERLOAD_INT_RAW_S)
-#define TWAIFD_IS_OVERLOAD_INT_RAW_V  0x00000001U
-#define TWAIFD_IS_OVERLOAD_INT_RAW_S  8
-/** TWAIFD_RX_BUF_FULL_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt status of TWAIFD_RX_BUF_FULL_INT.
- */
-#define TWAIFD_RX_BUF_FULL_INT_RAW    (BIT(9))
-#define TWAIFD_RX_BUF_FULL_INT_RAW_M  (TWAIFD_RX_BUF_FULL_INT_RAW_V << TWAIFD_RX_BUF_FULL_INT_RAW_S)
-#define TWAIFD_RX_BUF_FULL_INT_RAW_V  0x00000001U
-#define TWAIFD_RX_BUF_FULL_INT_RAW_S  9
-/** TWAIFD_BIT_RATE_SHIFT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
- */
-#define TWAIFD_BIT_RATE_SHIFT_INT_RAW    (BIT(10))
-#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_M  (TWAIFD_BIT_RATE_SHIFT_INT_RAW_V << TWAIFD_BIT_RATE_SHIFT_INT_RAW_S)
-#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_V  0x00000001U
-#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_S  10
-/** TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
- */
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW    (BIT(11))
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_S)
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_V  0x00000001U
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_S  11
-/** TWAIFD_TX_BUF_STATUS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
- */
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW    (BIT(12))
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_V << TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_S)
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_V  0x00000001U
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_S  12
-
-/** TWAIFD_INT_ENA_REG register
- *  TWAI FD interrupt enable register
- */
-#define TWAIFD_INT_ENA_REG (DR_REG_TWAIFD_BASE + 0x14)
-/** TWAIFD_RX_FRM_SUC_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable TWAIFD_RX_FRM_SUC_INT.
- */
-#define TWAIFD_RX_FRM_SUC_INT_ENA    (BIT(0))
-#define TWAIFD_RX_FRM_SUC_INT_ENA_M  (TWAIFD_RX_FRM_SUC_INT_ENA_V << TWAIFD_RX_FRM_SUC_INT_ENA_S)
-#define TWAIFD_RX_FRM_SUC_INT_ENA_V  0x00000001U
-#define TWAIFD_RX_FRM_SUC_INT_ENA_S  0
-/** TWAIFD_TX_FRM_SUC_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable TWAIFD_TX_FRM_SUC_INT.
- */
-#define TWAIFD_TX_FRM_SUC_INT_ENA    (BIT(1))
-#define TWAIFD_TX_FRM_SUC_INT_ENA_M  (TWAIFD_TX_FRM_SUC_INT_ENA_V << TWAIFD_TX_FRM_SUC_INT_ENA_S)
-#define TWAIFD_TX_FRM_SUC_INT_ENA_V  0x00000001U
-#define TWAIFD_TX_FRM_SUC_INT_ENA_S  1
-/** TWAIFD_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable TWAIFD_ERR_WARNING_INT.
- */
-#define TWAIFD_ERR_WARNING_INT_ENA    (BIT(2))
-#define TWAIFD_ERR_WARNING_INT_ENA_M  (TWAIFD_ERR_WARNING_INT_ENA_V << TWAIFD_ERR_WARNING_INT_ENA_S)
-#define TWAIFD_ERR_WARNING_INT_ENA_V  0x00000001U
-#define TWAIFD_ERR_WARNING_INT_ENA_S  2
-/** TWAIFD_RX_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to enable TWAIFD_RX_DATA_OVERRUN_INT.
- */
-#define TWAIFD_RX_DATA_OVERRUN_INT_ENA    (BIT(3))
-#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_M  (TWAIFD_RX_DATA_OVERRUN_INT_ENA_V << TWAIFD_RX_DATA_OVERRUN_INT_ENA_S)
-#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_V  0x00000001U
-#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_S  3
-/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to enable TWAIFD_FAULT_CONFINEMENT_CHG_INT.
- */
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA    (BIT(5))
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_S)
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_V  0x00000001U
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_S  5
-/** TWAIFD_ARB_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Write 1 to enable TWAIFD_ARB_LOST_INT.
- */
-#define TWAIFD_ARB_LOST_INT_ENA    (BIT(6))
-#define TWAIFD_ARB_LOST_INT_ENA_M  (TWAIFD_ARB_LOST_INT_ENA_V << TWAIFD_ARB_LOST_INT_ENA_S)
-#define TWAIFD_ARB_LOST_INT_ENA_V  0x00000001U
-#define TWAIFD_ARB_LOST_INT_ENA_S  6
-/** TWAIFD_ERR_DETECTED_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Write 1 to enable TWAIFD_ERR_DETECTED_INT.
- */
-#define TWAIFD_ERR_DETECTED_INT_ENA    (BIT(7))
-#define TWAIFD_ERR_DETECTED_INT_ENA_M  (TWAIFD_ERR_DETECTED_INT_ENA_V << TWAIFD_ERR_DETECTED_INT_ENA_S)
-#define TWAIFD_ERR_DETECTED_INT_ENA_V  0x00000001U
-#define TWAIFD_ERR_DETECTED_INT_ENA_S  7
-/** TWAIFD_IS_OVERLOAD_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Write 1 to enable TWAIFD_IS_OVERLOAD_INT.
- */
-#define TWAIFD_IS_OVERLOAD_INT_ENA    (BIT(8))
-#define TWAIFD_IS_OVERLOAD_INT_ENA_M  (TWAIFD_IS_OVERLOAD_INT_ENA_V << TWAIFD_IS_OVERLOAD_INT_ENA_S)
-#define TWAIFD_IS_OVERLOAD_INT_ENA_V  0x00000001U
-#define TWAIFD_IS_OVERLOAD_INT_ENA_S  8
-/** TWAIFD_RX_BUF_FULL_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Write 1 to enable TWAIFD_RX_BUF_FULL_INT.
- */
-#define TWAIFD_RX_BUF_FULL_INT_ENA    (BIT(9))
-#define TWAIFD_RX_BUF_FULL_INT_ENA_M  (TWAIFD_RX_BUF_FULL_INT_ENA_V << TWAIFD_RX_BUF_FULL_INT_ENA_S)
-#define TWAIFD_RX_BUF_FULL_INT_ENA_V  0x00000001U
-#define TWAIFD_RX_BUF_FULL_INT_ENA_S  9
-/** TWAIFD_BIT_RATE_SHIFT_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Write 1 to enable TWAIFD_BIT_RATE_SHIFT_INT.
- */
-#define TWAIFD_BIT_RATE_SHIFT_INT_ENA    (BIT(10))
-#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_M  (TWAIFD_BIT_RATE_SHIFT_INT_ENA_V << TWAIFD_BIT_RATE_SHIFT_INT_ENA_S)
-#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_V  0x00000001U
-#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_S  10
-/** TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Write 1 to enable TWAIFD_RX_BUF_NOT_EMPTY_INT.
- */
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA    (BIT(11))
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_S)
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_V  0x00000001U
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_S  11
-/** TWAIFD_TX_BUF_STATUS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Write 1 to enable TWAIFD_TX_BUF_STATUS_CHG_INT.
- */
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA    (BIT(12))
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_V << TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_S)
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_V  0x00000001U
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_S  12
-
-/** TWAIFD_INT_ST_REG register
- *  TWAI FD interrupt status register
- */
-#define TWAIFD_INT_ST_REG (DR_REG_TWAIFD_BASE + 0x18)
-/** TWAIFD_RX_FRM_SUC_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status of TWAIFD_RX_FRM_SUC_INT.
- */
-#define TWAIFD_RX_FRM_SUC_INT_ST    (BIT(0))
-#define TWAIFD_RX_FRM_SUC_INT_ST_M  (TWAIFD_RX_FRM_SUC_INT_ST_V << TWAIFD_RX_FRM_SUC_INT_ST_S)
-#define TWAIFD_RX_FRM_SUC_INT_ST_V  0x00000001U
-#define TWAIFD_RX_FRM_SUC_INT_ST_S  0
-/** TWAIFD_TX_FRM_SUC_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status of TWAIFD_TX_FRM_SUC_INT.
- */
-#define TWAIFD_TX_FRM_SUC_INT_ST    (BIT(1))
-#define TWAIFD_TX_FRM_SUC_INT_ST_M  (TWAIFD_TX_FRM_SUC_INT_ST_V << TWAIFD_TX_FRM_SUC_INT_ST_S)
-#define TWAIFD_TX_FRM_SUC_INT_ST_V  0x00000001U
-#define TWAIFD_TX_FRM_SUC_INT_ST_S  1
-/** TWAIFD_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status of TWAIFD_ERR_WARNING_INT.
- */
-#define TWAIFD_ERR_WARNING_INT_ST    (BIT(2))
-#define TWAIFD_ERR_WARNING_INT_ST_M  (TWAIFD_ERR_WARNING_INT_ST_V << TWAIFD_ERR_WARNING_INT_ST_S)
-#define TWAIFD_ERR_WARNING_INT_ST_V  0x00000001U
-#define TWAIFD_ERR_WARNING_INT_ST_S  2
-/** TWAIFD_RX_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
- */
-#define TWAIFD_RX_DATA_OVERRUN_INT_ST    (BIT(3))
-#define TWAIFD_RX_DATA_OVERRUN_INT_ST_M  (TWAIFD_RX_DATA_OVERRUN_INT_ST_V << TWAIFD_RX_DATA_OVERRUN_INT_ST_S)
-#define TWAIFD_RX_DATA_OVERRUN_INT_ST_V  0x00000001U
-#define TWAIFD_RX_DATA_OVERRUN_INT_ST_S  3
-/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
- */
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST    (BIT(5))
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_S)
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_V  0x00000001U
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_S  5
-/** TWAIFD_ARB_LOST_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked interrupt status of TWAIFD_ARB_LOST_INT.
- */
-#define TWAIFD_ARB_LOST_INT_ST    (BIT(6))
-#define TWAIFD_ARB_LOST_INT_ST_M  (TWAIFD_ARB_LOST_INT_ST_V << TWAIFD_ARB_LOST_INT_ST_S)
-#define TWAIFD_ARB_LOST_INT_ST_V  0x00000001U
-#define TWAIFD_ARB_LOST_INT_ST_S  6
-/** TWAIFD_ERR_DETECTED_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked interrupt status of TWAIFD_ERR_DETECTED_INT.
- */
-#define TWAIFD_ERR_DETECTED_INT_ST    (BIT(7))
-#define TWAIFD_ERR_DETECTED_INT_ST_M  (TWAIFD_ERR_DETECTED_INT_ST_V << TWAIFD_ERR_DETECTED_INT_ST_S)
-#define TWAIFD_ERR_DETECTED_INT_ST_V  0x00000001U
-#define TWAIFD_ERR_DETECTED_INT_ST_S  7
-/** TWAIFD_IS_OVERLOAD_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked interrupt status of TWAIFD_IS_OVERLOAD_INT.
- */
-#define TWAIFD_IS_OVERLOAD_INT_ST    (BIT(8))
-#define TWAIFD_IS_OVERLOAD_INT_ST_M  (TWAIFD_IS_OVERLOAD_INT_ST_V << TWAIFD_IS_OVERLOAD_INT_ST_S)
-#define TWAIFD_IS_OVERLOAD_INT_ST_V  0x00000001U
-#define TWAIFD_IS_OVERLOAD_INT_ST_S  8
-/** TWAIFD_RX_BUF_FULL_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked interrupt status of TWAIFD_RX_BUF_FULL_INT.
- */
-#define TWAIFD_RX_BUF_FULL_INT_ST    (BIT(9))
-#define TWAIFD_RX_BUF_FULL_INT_ST_M  (TWAIFD_RX_BUF_FULL_INT_ST_V << TWAIFD_RX_BUF_FULL_INT_ST_S)
-#define TWAIFD_RX_BUF_FULL_INT_ST_V  0x00000001U
-#define TWAIFD_RX_BUF_FULL_INT_ST_S  9
-/** TWAIFD_BIT_RATE_SHIFT_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
- */
-#define TWAIFD_BIT_RATE_SHIFT_INT_ST    (BIT(10))
-#define TWAIFD_BIT_RATE_SHIFT_INT_ST_M  (TWAIFD_BIT_RATE_SHIFT_INT_ST_V << TWAIFD_BIT_RATE_SHIFT_INT_ST_S)
-#define TWAIFD_BIT_RATE_SHIFT_INT_ST_V  0x00000001U
-#define TWAIFD_BIT_RATE_SHIFT_INT_ST_S  10
-/** TWAIFD_RX_BUF_NOT_EMPTY_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
- */
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST    (BIT(11))
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_S)
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_V  0x00000001U
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_S  11
-/** TWAIFD_TX_BUF_STATUS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
- */
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST    (BIT(12))
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_ST_V << TWAIFD_TX_BUF_STATUS_CHG_INT_ST_S)
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_V  0x00000001U
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_S  12
-
-/** TWAIFD_INT_CLR_REG register
- *  TWAI FD interrupt clear register
- */
-#define TWAIFD_INT_CLR_REG (DR_REG_TWAIFD_BASE + 0x1c)
-/** TWAIFD_RX_FRM_SUC_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear TWAIFD_RX_FRM_SUC_INT.
- */
-#define TWAIFD_RX_FRM_SUC_INT_CLR    (BIT(0))
-#define TWAIFD_RX_FRM_SUC_INT_CLR_M  (TWAIFD_RX_FRM_SUC_INT_CLR_V << TWAIFD_RX_FRM_SUC_INT_CLR_S)
-#define TWAIFD_RX_FRM_SUC_INT_CLR_V  0x00000001U
-#define TWAIFD_RX_FRM_SUC_INT_CLR_S  0
-/** TWAIFD_TX_FRM_SUC_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear TWAIFD_TX_FRM_SUC_INT.
- */
-#define TWAIFD_TX_FRM_SUC_INT_CLR    (BIT(1))
-#define TWAIFD_TX_FRM_SUC_INT_CLR_M  (TWAIFD_TX_FRM_SUC_INT_CLR_V << TWAIFD_TX_FRM_SUC_INT_CLR_S)
-#define TWAIFD_TX_FRM_SUC_INT_CLR_V  0x00000001U
-#define TWAIFD_TX_FRM_SUC_INT_CLR_S  1
-/** TWAIFD_ERR_WARNING_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear TWAIFD_ERR_WARNING_INT.
- */
-#define TWAIFD_ERR_WARNING_INT_CLR    (BIT(2))
-#define TWAIFD_ERR_WARNING_INT_CLR_M  (TWAIFD_ERR_WARNING_INT_CLR_V << TWAIFD_ERR_WARNING_INT_CLR_S)
-#define TWAIFD_ERR_WARNING_INT_CLR_V  0x00000001U
-#define TWAIFD_ERR_WARNING_INT_CLR_S  2
-/** TWAIFD_RX_DATA_OVERRUN_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear TWAIFD_RX_DATA_OVERRUN_INT.
- */
-#define TWAIFD_RX_DATA_OVERRUN_INT_CLR    (BIT(3))
-#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_M  (TWAIFD_RX_DATA_OVERRUN_INT_CLR_V << TWAIFD_RX_DATA_OVERRUN_INT_CLR_S)
-#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_V  0x00000001U
-#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_S  3
-/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear TWAIFD_FAULT_CONFINEMENT_CHG_INT.
- */
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR    (BIT(5))
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_M  (TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_S)
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_V  0x00000001U
-#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_S  5
-/** TWAIFD_ARB_LOST_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear TWAIFD_ARB_LOST_INT.
- */
-#define TWAIFD_ARB_LOST_INT_CLR    (BIT(6))
-#define TWAIFD_ARB_LOST_INT_CLR_M  (TWAIFD_ARB_LOST_INT_CLR_V << TWAIFD_ARB_LOST_INT_CLR_S)
-#define TWAIFD_ARB_LOST_INT_CLR_V  0x00000001U
-#define TWAIFD_ARB_LOST_INT_CLR_S  6
-/** TWAIFD_ERR_DETECTED_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Write 1 to clear TWAIFD_ERR_DETECTED_INT.
- */
-#define TWAIFD_ERR_DETECTED_INT_CLR    (BIT(7))
-#define TWAIFD_ERR_DETECTED_INT_CLR_M  (TWAIFD_ERR_DETECTED_INT_CLR_V << TWAIFD_ERR_DETECTED_INT_CLR_S)
-#define TWAIFD_ERR_DETECTED_INT_CLR_V  0x00000001U
-#define TWAIFD_ERR_DETECTED_INT_CLR_S  7
-/** TWAIFD_IS_OVERLOAD_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Write 1 to clear TWAIFD_IS_OVERLOAD_INT.
- */
-#define TWAIFD_IS_OVERLOAD_INT_CLR    (BIT(8))
-#define TWAIFD_IS_OVERLOAD_INT_CLR_M  (TWAIFD_IS_OVERLOAD_INT_CLR_V << TWAIFD_IS_OVERLOAD_INT_CLR_S)
-#define TWAIFD_IS_OVERLOAD_INT_CLR_V  0x00000001U
-#define TWAIFD_IS_OVERLOAD_INT_CLR_S  8
-/** TWAIFD_RX_BUF_FULL_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Write 1 to clear TWAIFD_RX_BUF_FULL_INT.
- */
-#define TWAIFD_RX_BUF_FULL_INT_CLR    (BIT(9))
-#define TWAIFD_RX_BUF_FULL_INT_CLR_M  (TWAIFD_RX_BUF_FULL_INT_CLR_V << TWAIFD_RX_BUF_FULL_INT_CLR_S)
-#define TWAIFD_RX_BUF_FULL_INT_CLR_V  0x00000001U
-#define TWAIFD_RX_BUF_FULL_INT_CLR_S  9
-/** TWAIFD_BIT_RATE_SHIFT_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Write 1 to clear TWAIFD_BIT_RATE_SHIFT_INT.
- */
-#define TWAIFD_BIT_RATE_SHIFT_INT_CLR    (BIT(10))
-#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_M  (TWAIFD_BIT_RATE_SHIFT_INT_CLR_V << TWAIFD_BIT_RATE_SHIFT_INT_CLR_S)
-#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_V  0x00000001U
-#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_S  10
-/** TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Write 1 to clear TWAIFD_RX_BUF_NOT_EMPTY_INT.
- */
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR    (BIT(11))
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_M  (TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_S)
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_V  0x00000001U
-#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_S  11
-/** TWAIFD_TX_BUF_STATUS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Write 1 to clear TWAIFD_TX_BUF_STATUS_CHG_INT.
- */
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR    (BIT(12))
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_M  (TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_V << TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_S)
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_V  0x00000001U
-#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_S  12
-
-/** TWAIFD_BIT_TIMING_REG register
- *  TWAI FD bit-timing  register
- */
-#define TWAIFD_BIT_TIMING_REG (DR_REG_TWAIFD_BASE + 0x20)
-/** TWAIFD_PROP : R/W; bitpos: [6:0]; default: 5;
- *  Configures the propagation segment of nominal bit rate.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_PROP    0x0000007FU
-#define TWAIFD_PROP_M  (TWAIFD_PROP_V << TWAIFD_PROP_S)
-#define TWAIFD_PROP_V  0x0000007FU
-#define TWAIFD_PROP_S  0
-/** TWAIFD_PH1 : R/W; bitpos: [12:7]; default: 3;
- *  Configures the phase 1 segment of nominal bit rate.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_PH1    0x0000003FU
-#define TWAIFD_PH1_M  (TWAIFD_PH1_V << TWAIFD_PH1_S)
-#define TWAIFD_PH1_V  0x0000003FU
-#define TWAIFD_PH1_S  7
-/** TWAIFD_PH2 : R/W; bitpos: [18:13]; default: 5;
- *  Configures the phase 2 segment of nominal bit rate.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_PH2    0x0000003FU
-#define TWAIFD_PH2_M  (TWAIFD_PH2_V << TWAIFD_PH2_S)
-#define TWAIFD_PH2_V  0x0000003FU
-#define TWAIFD_PH2_S  13
-/** TWAIFD_BRP : R/W; bitpos: [26:19]; default: 16;
- *  Configures the baud-rate prescaler of nominal bit rate.\\
- *  Measurement unit: cycle of core clock.
- */
-#define TWAIFD_BRP    0x000000FFU
-#define TWAIFD_BRP_M  (TWAIFD_BRP_V << TWAIFD_BRP_S)
-#define TWAIFD_BRP_V  0x000000FFU
-#define TWAIFD_BRP_S  19
-/** TWAIFD_SJW : R/W; bitpos: [31:27]; default: 2;
- *  Represents the synchronization jump width in nominal bit time.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_SJW    0x0000001FU
-#define TWAIFD_SJW_M  (TWAIFD_SJW_V << TWAIFD_SJW_S)
-#define TWAIFD_SJW_V  0x0000001FU
-#define TWAIFD_SJW_S  27
-
-/** TWAIFD_BIT_TIMEING_FD_REG register
- *  TWAI FD bit-timing of FD register
- */
-#define TWAIFD_BIT_TIMEING_FD_REG (DR_REG_TWAIFD_BASE + 0x24)
-/** TWAIFD_PROP_FD : R/W; bitpos: [5:0]; default: 3;
- *  Configures the propagation segment of data bit rate.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_PROP_FD    0x0000003FU
-#define TWAIFD_PROP_FD_M  (TWAIFD_PROP_FD_V << TWAIFD_PROP_FD_S)
-#define TWAIFD_PROP_FD_V  0x0000003FU
-#define TWAIFD_PROP_FD_S  0
-/** TWAIFD_PH1_FD : R/W; bitpos: [11:7]; default: 3;
- *  Configures the phase 1 segment of data bit rate.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_PH1_FD    0x0000001FU
-#define TWAIFD_PH1_FD_M  (TWAIFD_PH1_FD_V << TWAIFD_PH1_FD_S)
-#define TWAIFD_PH1_FD_V  0x0000001FU
-#define TWAIFD_PH1_FD_S  7
-/** TWAIFD_PH2_FD : R/W; bitpos: [17:13]; default: 3;
- *  Configures the phase 2 segment of data bit rate.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_PH2_FD    0x0000001FU
-#define TWAIFD_PH2_FD_M  (TWAIFD_PH2_FD_V << TWAIFD_PH2_FD_S)
-#define TWAIFD_PH2_FD_V  0x0000001FU
-#define TWAIFD_PH2_FD_S  13
-/** TWAIFD_BRP_FD : R/W; bitpos: [26:19]; default: 4;
- *  Configures the baud-rate prescaler of data bit rate.\\
- *  Measurement unit: cycle of core clock.
- */
-#define TWAIFD_BRP_FD    0x000000FFU
-#define TWAIFD_BRP_FD_M  (TWAIFD_BRP_FD_V << TWAIFD_BRP_FD_S)
-#define TWAIFD_BRP_FD_V  0x000000FFU
-#define TWAIFD_BRP_FD_S  19
-/** TWAIFD_SJW_FD : R/W; bitpos: [31:27]; default: 2;
- *  Represents the synchronization jump width in data bit time.\\
- *  Measurement unit: time quanta\\
- */
-#define TWAIFD_SJW_FD    0x0000001FU
-#define TWAIFD_SJW_FD_M  (TWAIFD_SJW_FD_V << TWAIFD_SJW_FD_S)
-#define TWAIFD_SJW_FD_V  0x0000001FU
-#define TWAIFD_SJW_FD_S  27
-
-/** TWAIFD_ERR_TH_STAT_REG register
- *  TWAI FD error threshold and status register
- */
-#define TWAIFD_ERR_TH_STAT_REG (DR_REG_TWAIFD_BASE + 0x28)
-/** TWAIFD_ERR_WARNING_THRES : R/W; bitpos: [7:0]; default: 96;
- *  Configures the error warning threshold.\\
- */
-#define TWAIFD_ERR_WARNING_THRES    0x000000FFU
-#define TWAIFD_ERR_WARNING_THRES_M  (TWAIFD_ERR_WARNING_THRES_V << TWAIFD_ERR_WARNING_THRES_S)
-#define TWAIFD_ERR_WARNING_THRES_V  0x000000FFU
-#define TWAIFD_ERR_WARNING_THRES_S  0
-/** TWAIFD_ERR_PASSIVE_THRES : R/W; bitpos: [15:8]; default: 128;
- *  Configures the error passive threshold.\\
- */
-#define TWAIFD_ERR_PASSIVE_THRES    0x000000FFU
-#define TWAIFD_ERR_PASSIVE_THRES_M  (TWAIFD_ERR_PASSIVE_THRES_V << TWAIFD_ERR_PASSIVE_THRES_S)
-#define TWAIFD_ERR_PASSIVE_THRES_V  0x000000FFU
-#define TWAIFD_ERR_PASSIVE_THRES_S  8
-/** TWAIFD_ERR_ACTIVE : RO; bitpos: [16]; default: 1;
- *  Represents the fault state of error active.\\
- */
-#define TWAIFD_ERR_ACTIVE    (BIT(16))
-#define TWAIFD_ERR_ACTIVE_M  (TWAIFD_ERR_ACTIVE_V << TWAIFD_ERR_ACTIVE_S)
-#define TWAIFD_ERR_ACTIVE_V  0x00000001U
-#define TWAIFD_ERR_ACTIVE_S  16
-/** TWAIFD_ERR_PASSIVE : RO; bitpos: [17]; default: 0;
- *  Represents the fault state of error passive.\\
- */
-#define TWAIFD_ERR_PASSIVE    (BIT(17))
-#define TWAIFD_ERR_PASSIVE_M  (TWAIFD_ERR_PASSIVE_V << TWAIFD_ERR_PASSIVE_S)
-#define TWAIFD_ERR_PASSIVE_V  0x00000001U
-#define TWAIFD_ERR_PASSIVE_S  17
-/** TWAIFD_BUS_OFF : RO; bitpos: [18]; default: 0;
- *  Represents the fault state of bus off.\\
- */
-#define TWAIFD_BUS_OFF    (BIT(18))
-#define TWAIFD_BUS_OFF_M  (TWAIFD_BUS_OFF_V << TWAIFD_BUS_OFF_S)
-#define TWAIFD_BUS_OFF_V  0x00000001U
-#define TWAIFD_BUS_OFF_S  18
-
-/** TWAIFD_ERROR_COUNTERS_REG register
- *  TWAI FD error counters status register
- */
-#define TWAIFD_ERROR_COUNTERS_REG (DR_REG_TWAIFD_BASE + 0x2c)
-/** TWAIFD_RXC_VAL : RO; bitpos: [15:0]; default: 0;
- *  Represents the receiver error counter value.\\
- */
-#define TWAIFD_RXC_VAL    0x0000FFFFU
-#define TWAIFD_RXC_VAL_M  (TWAIFD_RXC_VAL_V << TWAIFD_RXC_VAL_S)
-#define TWAIFD_RXC_VAL_V  0x0000FFFFU
-#define TWAIFD_RXC_VAL_S  0
-/** TWAIFD_TXC_VAL : RO; bitpos: [31:16]; default: 0;
- *  Represents the transmitter error counter value.\\
- */
-#define TWAIFD_TXC_VAL    0x0000FFFFU
-#define TWAIFD_TXC_VAL_M  (TWAIFD_TXC_VAL_V << TWAIFD_TXC_VAL_S)
-#define TWAIFD_TXC_VAL_V  0x0000FFFFU
-#define TWAIFD_TXC_VAL_S  16
-
-/** TWAIFD_ERROR_COUNTERS_SP_REG register
- *  TWAI FD special error counters status register
- */
-#define TWAIFD_ERROR_COUNTERS_SP_REG (DR_REG_TWAIFD_BASE + 0x30)
-/** TWAIFD_ERR_FD_VAL : RO; bitpos: [15:0]; default: 0;
- *  Represents the number of error in the data bit time.\\
- */
-#define TWAIFD_ERR_FD_VAL    0x0000FFFFU
-#define TWAIFD_ERR_FD_VAL_M  (TWAIFD_ERR_FD_VAL_V << TWAIFD_ERR_FD_VAL_S)
-#define TWAIFD_ERR_FD_VAL_V  0x0000FFFFU
-#define TWAIFD_ERR_FD_VAL_S  0
-/** TWAIFD_ERR_NORM_VAL : RO; bitpos: [31:16]; default: 0;
- *  Represents the number of error in the nominal bit time.\\
- */
-#define TWAIFD_ERR_NORM_VAL    0x0000FFFFU
-#define TWAIFD_ERR_NORM_VAL_M  (TWAIFD_ERR_NORM_VAL_V << TWAIFD_ERR_NORM_VAL_S)
-#define TWAIFD_ERR_NORM_VAL_V  0x0000FFFFU
-#define TWAIFD_ERR_NORM_VAL_S  16
-
-/** TWAIFD_CTR_PRES_REG register
- *  TWAI FD error counters pre-define configuration register
- */
-#define TWAIFD_CTR_PRES_REG (DR_REG_TWAIFD_BASE + 0x34)
-/** TWAIFD_CTR_PRES_VAL : WO; bitpos: [8:0]; default: 0;
- *  Configures the pre-defined value to set the error counter.\\
- */
-#define TWAIFD_CTR_PRES_VAL    0x000001FFU
-#define TWAIFD_CTR_PRES_VAL_M  (TWAIFD_CTR_PRES_VAL_V << TWAIFD_CTR_PRES_VAL_S)
-#define TWAIFD_CTR_PRES_VAL_V  0x000001FFU
-#define TWAIFD_CTR_PRES_VAL_S  0
-/** TWAIFD_PTX : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to set the receiver error counter into the value of
- *  pre-defined value.\\
- *  0: invalid\\
- *  1: set\\
- */
-#define TWAIFD_PTX    (BIT(9))
-#define TWAIFD_PTX_M  (TWAIFD_PTX_V << TWAIFD_PTX_S)
-#define TWAIFD_PTX_V  0x00000001U
-#define TWAIFD_PTX_S  9
-/** TWAIFD_PRX : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to set the transmitter error counter into the value of
- *  pre-defined value.\\
- *  0: invalid\\
- *  1: set\\
- */
-#define TWAIFD_PRX    (BIT(10))
-#define TWAIFD_PRX_M  (TWAIFD_PRX_V << TWAIFD_PRX_S)
-#define TWAIFD_PRX_V  0x00000001U
-#define TWAIFD_PRX_S  10
-/** TWAIFD_ENORM : WO; bitpos: [11]; default: 0;
- *  Configures whether or not to erase the error counter of nominal bit time.\\
- *  0: invalid\\
- *  1: erase\\
- */
-#define TWAIFD_ENORM    (BIT(11))
-#define TWAIFD_ENORM_M  (TWAIFD_ENORM_V << TWAIFD_ENORM_S)
-#define TWAIFD_ENORM_V  0x00000001U
-#define TWAIFD_ENORM_S  11
-/** TWAIFD_EFD : WO; bitpos: [12]; default: 0;
- *  Configures whether or not to erase the error counter of data bit time.\\
- *  0: invalid\\
- *  1: erase\\
- */
-#define TWAIFD_EFD    (BIT(12))
-#define TWAIFD_EFD_M  (TWAIFD_EFD_V << TWAIFD_EFD_S)
-#define TWAIFD_EFD_V  0x00000001U
-#define TWAIFD_EFD_S  12
-
-/** TWAIFD_RX_MEM_INFO_REG register
- *  TWAI FD rx memory information register
- */
-#define TWAIFD_RX_MEM_INFO_REG (DR_REG_TWAIFD_BASE + 0x38)
-/** TWAIFD_RX_BUFF_SIZE_VAL : RO; bitpos: [12:0]; default: 0;
- *  Represents the size of RX buffer.\\
- */
-#define TWAIFD_RX_BUFF_SIZE_VAL    0x00001FFFU
-#define TWAIFD_RX_BUFF_SIZE_VAL_M  (TWAIFD_RX_BUFF_SIZE_VAL_V << TWAIFD_RX_BUFF_SIZE_VAL_S)
-#define TWAIFD_RX_BUFF_SIZE_VAL_V  0x00001FFFU
-#define TWAIFD_RX_BUFF_SIZE_VAL_S  0
-/** TWAIFD_RX_FREE_CTR : RO; bitpos: [28:16]; default: 0;
- *  Represents the number of free words in RX buffer.\\
- */
-#define TWAIFD_RX_FREE_CTR    0x00001FFFU
-#define TWAIFD_RX_FREE_CTR_M  (TWAIFD_RX_FREE_CTR_V << TWAIFD_RX_FREE_CTR_S)
-#define TWAIFD_RX_FREE_CTR_V  0x00001FFFU
-#define TWAIFD_RX_FREE_CTR_S  16
-
-/** TWAIFD_RX_POINTERS_REG register
- *  TWAI FD rx memory pointer information register
- */
-#define TWAIFD_RX_POINTERS_REG (DR_REG_TWAIFD_BASE + 0x3c)
-/** TWAIFD_RX_WPT_VAL : RO; bitpos: [11:0]; default: 0;
- *  Represents the write pointer position in RX buffer.\\
- */
-#define TWAIFD_RX_WPT_VAL    0x00000FFFU
-#define TWAIFD_RX_WPT_VAL_M  (TWAIFD_RX_WPT_VAL_V << TWAIFD_RX_WPT_VAL_S)
-#define TWAIFD_RX_WPT_VAL_V  0x00000FFFU
-#define TWAIFD_RX_WPT_VAL_S  0
-/** TWAIFD_RX_RPT_VAL : RO; bitpos: [27:16]; default: 0;
- *  Represents the read pointer position in RX buffer.\\
- */
-#define TWAIFD_RX_RPT_VAL    0x00000FFFU
-#define TWAIFD_RX_RPT_VAL_M  (TWAIFD_RX_RPT_VAL_V << TWAIFD_RX_RPT_VAL_S)
-#define TWAIFD_RX_RPT_VAL_V  0x00000FFFU
-#define TWAIFD_RX_RPT_VAL_S  16
-
-/** TWAIFD_RX_STATUS_SETTING_REG register
- *  TWAI FD tx status & setting register
- */
-#define TWAIFD_RX_STATUS_SETTING_REG (DR_REG_TWAIFD_BASE + 0x40)
-/** TWAIFD_RX_EMPTY : RO; bitpos: [0]; default: 0;
- *  Represents whether or not the RX buffer is empty.\\
- *  0: not empty\\
- *  1: empty\\
- */
-#define TWAIFD_RX_EMPTY    (BIT(0))
-#define TWAIFD_RX_EMPTY_M  (TWAIFD_RX_EMPTY_V << TWAIFD_RX_EMPTY_S)
-#define TWAIFD_RX_EMPTY_V  0x00000001U
-#define TWAIFD_RX_EMPTY_S  0
-/** TWAIFD_RX_FULL : RO; bitpos: [1]; default: 0;
- *  Represents whether or not the RX buffer is full.\\
- *  0: not full\\
- *  1: full\\
- */
-#define TWAIFD_RX_FULL    (BIT(1))
-#define TWAIFD_RX_FULL_M  (TWAIFD_RX_FULL_V << TWAIFD_RX_FULL_S)
-#define TWAIFD_RX_FULL_V  0x00000001U
-#define TWAIFD_RX_FULL_S  1
-/** TWAIFD_RX_FRM_CTR : RO; bitpos: [14:4]; default: 0;
- *  Represents the number of received frame in RX buffer.\\
- */
-#define TWAIFD_RX_FRM_CTR    0x000007FFU
-#define TWAIFD_RX_FRM_CTR_M  (TWAIFD_RX_FRM_CTR_V << TWAIFD_RX_FRM_CTR_S)
-#define TWAIFD_RX_FRM_CTR_V  0x000007FFU
-#define TWAIFD_RX_FRM_CTR_S  4
-/** TWAIFD_RTSOP : R/W; bitpos: [16]; default: 0;
- *  a\\
- */
-#define TWAIFD_RTSOP    (BIT(16))
-#define TWAIFD_RTSOP_M  (TWAIFD_RTSOP_V << TWAIFD_RTSOP_S)
-#define TWAIFD_RTSOP_V  0x00000001U
-#define TWAIFD_RTSOP_S  16
-
-/** TWAIFD_RX_DATA_REG register
- *  TWAI FD received data register
- */
-#define TWAIFD_RX_DATA_REG (DR_REG_TWAIFD_BASE + 0x44)
-/** TWAIFD_RX_DATA : RO; bitpos: [31:0]; default: 0;
- *  Data received.
- */
-#define TWAIFD_RX_DATA    0xFFFFFFFFU
-#define TWAIFD_RX_DATA_M  (TWAIFD_RX_DATA_V << TWAIFD_RX_DATA_S)
-#define TWAIFD_RX_DATA_V  0xFFFFFFFFU
-#define TWAIFD_RX_DATA_S  0
-
-/** TWAIFD_FILTER_A_MASK_REG register
- *  TWAI FD filter A mask value register
- */
-#define TWAIFD_FILTER_A_MASK_REG (DR_REG_TWAIFD_BASE + 0x60)
-/** TWAIFD_BIT_MASK_A : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit masked value.
- */
-#define TWAIFD_BIT_MASK_A    0x1FFFFFFFU
-#define TWAIFD_BIT_MASK_A_M  (TWAIFD_BIT_MASK_A_V << TWAIFD_BIT_MASK_A_S)
-#define TWAIFD_BIT_MASK_A_V  0x1FFFFFFFU
-#define TWAIFD_BIT_MASK_A_S  0
-
-/** TWAIFD_FILTER_A_VAL_REG register
- *  TWAI FD filter A bit value register
- */
-#define TWAIFD_FILTER_A_VAL_REG (DR_REG_TWAIFD_BASE + 0x64)
-/** TWAIFD_BIT_VAL_A : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit value.
- */
-#define TWAIFD_BIT_VAL_A    0x1FFFFFFFU
-#define TWAIFD_BIT_VAL_A_M  (TWAIFD_BIT_VAL_A_V << TWAIFD_BIT_VAL_A_S)
-#define TWAIFD_BIT_VAL_A_V  0x1FFFFFFFU
-#define TWAIFD_BIT_VAL_A_S  0
-
-/** TWAIFD_FILTER_B_MASK_REG register
- *  TWAI FD filter B mask value register
- */
-#define TWAIFD_FILTER_B_MASK_REG (DR_REG_TWAIFD_BASE + 0x68)
-/** TWAIFD_BIT_MASK_B : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit masked value.
- */
-#define TWAIFD_BIT_MASK_B    0x1FFFFFFFU
-#define TWAIFD_BIT_MASK_B_M  (TWAIFD_BIT_MASK_B_V << TWAIFD_BIT_MASK_B_S)
-#define TWAIFD_BIT_MASK_B_V  0x1FFFFFFFU
-#define TWAIFD_BIT_MASK_B_S  0
-
-/** TWAIFD_FILTER_B_VAL_REG register
- *  TWAI FD filter B bit value register
- */
-#define TWAIFD_FILTER_B_VAL_REG (DR_REG_TWAIFD_BASE + 0x6c)
-/** TWAIFD_BIT_VAL_B : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit value.
- */
-#define TWAIFD_BIT_VAL_B    0x1FFFFFFFU
-#define TWAIFD_BIT_VAL_B_M  (TWAIFD_BIT_VAL_B_V << TWAIFD_BIT_VAL_B_S)
-#define TWAIFD_BIT_VAL_B_V  0x1FFFFFFFU
-#define TWAIFD_BIT_VAL_B_S  0
-
-/** TWAIFD_FILTER_C_MASK_REG register
- *  TWAI FD filter C mask value register
- */
-#define TWAIFD_FILTER_C_MASK_REG (DR_REG_TWAIFD_BASE + 0x70)
-/** TWAIFD_BIT_MASK_C : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit masked value.
- */
-#define TWAIFD_BIT_MASK_C    0x1FFFFFFFU
-#define TWAIFD_BIT_MASK_C_M  (TWAIFD_BIT_MASK_C_V << TWAIFD_BIT_MASK_C_S)
-#define TWAIFD_BIT_MASK_C_V  0x1FFFFFFFU
-#define TWAIFD_BIT_MASK_C_S  0
-
-/** TWAIFD_FILTER_C_VAL_REG register
- *  TWAI FD filter C bit value register
- */
-#define TWAIFD_FILTER_C_VAL_REG (DR_REG_TWAIFD_BASE + 0x74)
-/** TWAIFD_BIT_VAL_C : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit value.
- */
-#define TWAIFD_BIT_VAL_C    0x1FFFFFFFU
-#define TWAIFD_BIT_VAL_C_M  (TWAIFD_BIT_VAL_C_V << TWAIFD_BIT_VAL_C_S)
-#define TWAIFD_BIT_VAL_C_V  0x1FFFFFFFU
-#define TWAIFD_BIT_VAL_C_S  0
-
-/** TWAIFD_FILTER_RAN_LOW_REG register
- *  TWAI FD filter range low value register
- */
-#define TWAIFD_FILTER_RAN_LOW_REG (DR_REG_TWAIFD_BASE + 0x78)
-/** TWAIFD_BIT_RAN_LOW : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit masked value.
- */
-#define TWAIFD_BIT_RAN_LOW    0x1FFFFFFFU
-#define TWAIFD_BIT_RAN_LOW_M  (TWAIFD_BIT_RAN_LOW_V << TWAIFD_BIT_RAN_LOW_S)
-#define TWAIFD_BIT_RAN_LOW_V  0x1FFFFFFFU
-#define TWAIFD_BIT_RAN_LOW_S  0
-
-/** TWAIFD_FILTER_RAN_HIGH_REG register
- *  TWAI FD filter range high value register
- */
-#define TWAIFD_FILTER_RAN_HIGH_REG (DR_REG_TWAIFD_BASE + 0x7c)
-/** TWAIFD_BIT_RAN_HIGH : R/W; bitpos: [28:0]; default: 0;
- *  filter A bit value.
- */
-#define TWAIFD_BIT_RAN_HIGH    0x1FFFFFFFU
-#define TWAIFD_BIT_RAN_HIGH_M  (TWAIFD_BIT_RAN_HIGH_V << TWAIFD_BIT_RAN_HIGH_S)
-#define TWAIFD_BIT_RAN_HIGH_V  0x1FFFFFFFU
-#define TWAIFD_BIT_RAN_HIGH_S  0
-
-/** TWAIFD_FILTER_CONTROL_REG register
- *  TWAI FD filter control register
- */
-#define TWAIFD_FILTER_CONTROL_REG (DR_REG_TWAIFD_BASE + 0x80)
-/** TWAIFD_FANB : R/W; bitpos: [0]; default: 1;
- *  filter A with nominal and base mode.
- */
-#define TWAIFD_FANB    (BIT(0))
-#define TWAIFD_FANB_M  (TWAIFD_FANB_V << TWAIFD_FANB_S)
-#define TWAIFD_FANB_V  0x00000001U
-#define TWAIFD_FANB_S  0
-/** TWAIFD_FANE : R/W; bitpos: [1]; default: 1;
- *  filter A with nominal and extended mode.
- */
-#define TWAIFD_FANE    (BIT(1))
-#define TWAIFD_FANE_M  (TWAIFD_FANE_V << TWAIFD_FANE_S)
-#define TWAIFD_FANE_V  0x00000001U
-#define TWAIFD_FANE_S  1
-/** TWAIFD_FAFB : R/W; bitpos: [2]; default: 1;
- *  filter A with FD and base mode.
- */
-#define TWAIFD_FAFB    (BIT(2))
-#define TWAIFD_FAFB_M  (TWAIFD_FAFB_V << TWAIFD_FAFB_S)
-#define TWAIFD_FAFB_V  0x00000001U
-#define TWAIFD_FAFB_S  2
-/** TWAIFD_FAFE : R/W; bitpos: [3]; default: 1;
- *  filter A with FD and extended mode.
- */
-#define TWAIFD_FAFE    (BIT(3))
-#define TWAIFD_FAFE_M  (TWAIFD_FAFE_V << TWAIFD_FAFE_S)
-#define TWAIFD_FAFE_V  0x00000001U
-#define TWAIFD_FAFE_S  3
-/** TWAIFD_FBNB : R/W; bitpos: [4]; default: 0;
- *  filter B with nominal and base mode.
- */
-#define TWAIFD_FBNB    (BIT(4))
-#define TWAIFD_FBNB_M  (TWAIFD_FBNB_V << TWAIFD_FBNB_S)
-#define TWAIFD_FBNB_V  0x00000001U
-#define TWAIFD_FBNB_S  4
-/** TWAIFD_FBNE : R/W; bitpos: [5]; default: 0;
- *  filter B with nominal and extended mode.
- */
-#define TWAIFD_FBNE    (BIT(5))
-#define TWAIFD_FBNE_M  (TWAIFD_FBNE_V << TWAIFD_FBNE_S)
-#define TWAIFD_FBNE_V  0x00000001U
-#define TWAIFD_FBNE_S  5
-/** TWAIFD_FBFB : R/W; bitpos: [6]; default: 0;
- *  filter B with FD and base mode.
- */
-#define TWAIFD_FBFB    (BIT(6))
-#define TWAIFD_FBFB_M  (TWAIFD_FBFB_V << TWAIFD_FBFB_S)
-#define TWAIFD_FBFB_V  0x00000001U
-#define TWAIFD_FBFB_S  6
-/** TWAIFD_FBFE : R/W; bitpos: [7]; default: 0;
- *  filter B with FD and extended mode.
- */
-#define TWAIFD_FBFE    (BIT(7))
-#define TWAIFD_FBFE_M  (TWAIFD_FBFE_V << TWAIFD_FBFE_S)
-#define TWAIFD_FBFE_V  0x00000001U
-#define TWAIFD_FBFE_S  7
-/** TWAIFD_FCNB : R/W; bitpos: [8]; default: 0;
- *  filter C with nominal and base mode.
- */
-#define TWAIFD_FCNB    (BIT(8))
-#define TWAIFD_FCNB_M  (TWAIFD_FCNB_V << TWAIFD_FCNB_S)
-#define TWAIFD_FCNB_V  0x00000001U
-#define TWAIFD_FCNB_S  8
-/** TWAIFD_FCNE : R/W; bitpos: [9]; default: 0;
- *  filter C with nominal and extended mode.
- */
-#define TWAIFD_FCNE    (BIT(9))
-#define TWAIFD_FCNE_M  (TWAIFD_FCNE_V << TWAIFD_FCNE_S)
-#define TWAIFD_FCNE_V  0x00000001U
-#define TWAIFD_FCNE_S  9
-/** TWAIFD_FCFB : R/W; bitpos: [10]; default: 0;
- *  filter C with FD and base mode.
- */
-#define TWAIFD_FCFB    (BIT(10))
-#define TWAIFD_FCFB_M  (TWAIFD_FCFB_V << TWAIFD_FCFB_S)
-#define TWAIFD_FCFB_V  0x00000001U
-#define TWAIFD_FCFB_S  10
-/** TWAIFD_FCFE : R/W; bitpos: [11]; default: 0;
- *  filter C with FD and extended mode.
- */
-#define TWAIFD_FCFE    (BIT(11))
-#define TWAIFD_FCFE_M  (TWAIFD_FCFE_V << TWAIFD_FCFE_S)
-#define TWAIFD_FCFE_V  0x00000001U
-#define TWAIFD_FCFE_S  11
-/** TWAIFD_FRNB : R/W; bitpos: [12]; default: 0;
- *  filter range with nominal and base mode.
- */
-#define TWAIFD_FRNB    (BIT(12))
-#define TWAIFD_FRNB_M  (TWAIFD_FRNB_V << TWAIFD_FRNB_S)
-#define TWAIFD_FRNB_V  0x00000001U
-#define TWAIFD_FRNB_S  12
-/** TWAIFD_FRNE : R/W; bitpos: [13]; default: 0;
- *  filter range with nominal and extended mode.
- */
-#define TWAIFD_FRNE    (BIT(13))
-#define TWAIFD_FRNE_M  (TWAIFD_FRNE_V << TWAIFD_FRNE_S)
-#define TWAIFD_FRNE_V  0x00000001U
-#define TWAIFD_FRNE_S  13
-/** TWAIFD_FRFB : R/W; bitpos: [14]; default: 0;
- *  filter range with FD and base mode.
- */
-#define TWAIFD_FRFB    (BIT(14))
-#define TWAIFD_FRFB_M  (TWAIFD_FRFB_V << TWAIFD_FRFB_S)
-#define TWAIFD_FRFB_V  0x00000001U
-#define TWAIFD_FRFB_S  14
-/** TWAIFD_FRFE : R/W; bitpos: [15]; default: 0;
- *  filter range with FD and extended mode.
- */
-#define TWAIFD_FRFE    (BIT(15))
-#define TWAIFD_FRFE_M  (TWAIFD_FRFE_V << TWAIFD_FRFE_S)
-#define TWAIFD_FRFE_V  0x00000001U
-#define TWAIFD_FRFE_S  15
-/** TWAIFD_SFA : RO; bitpos: [16]; default: 0;
- *  filter A status
- */
-#define TWAIFD_SFA    (BIT(16))
-#define TWAIFD_SFA_M  (TWAIFD_SFA_V << TWAIFD_SFA_S)
-#define TWAIFD_SFA_V  0x00000001U
-#define TWAIFD_SFA_S  16
-/** TWAIFD_SFB : RO; bitpos: [17]; default: 0;
- *  filter B status
- */
-#define TWAIFD_SFB    (BIT(17))
-#define TWAIFD_SFB_M  (TWAIFD_SFB_V << TWAIFD_SFB_S)
-#define TWAIFD_SFB_V  0x00000001U
-#define TWAIFD_SFB_S  17
-/** TWAIFD_SFC : RO; bitpos: [18]; default: 0;
- *  filter C status
- */
-#define TWAIFD_SFC    (BIT(18))
-#define TWAIFD_SFC_M  (TWAIFD_SFC_V << TWAIFD_SFC_S)
-#define TWAIFD_SFC_V  0x00000001U
-#define TWAIFD_SFC_S  18
-/** TWAIFD_SFR : RO; bitpos: [19]; default: 0;
- *  filter range status
- */
-#define TWAIFD_SFR    (BIT(19))
-#define TWAIFD_SFR_M  (TWAIFD_SFR_V << TWAIFD_SFR_S)
-#define TWAIFD_SFR_V  0x00000001U
-#define TWAIFD_SFR_S  19
-
-/** TWAIFD_TX_STAT_REG register
- *  TWAI FD TX buffer status register
- */
-#define TWAIFD_TX_STAT_REG (DR_REG_TWAIFD_BASE + 0x94)
-/** TWAIFD_TXT_1_EMPTY : RO; bitpos: [0]; default: 0;
- *  Represents whether or not the TX buffer1 is empty.\\
- *  0: not empty\\
- *  1: empty\\
- */
-#define TWAIFD_TXT_1_EMPTY    (BIT(0))
-#define TWAIFD_TXT_1_EMPTY_M  (TWAIFD_TXT_1_EMPTY_V << TWAIFD_TXT_1_EMPTY_S)
-#define TWAIFD_TXT_1_EMPTY_V  0x00000001U
-#define TWAIFD_TXT_1_EMPTY_S  0
-/** TWAIFD_TXT_2_EMPTY : RO; bitpos: [1]; default: 0;
- *  Represents whether or not the TX buffer2 is empty.\\
- *  0: not empty\\
- *  1: empty\\
- */
-#define TWAIFD_TXT_2_EMPTY    (BIT(1))
-#define TWAIFD_TXT_2_EMPTY_M  (TWAIFD_TXT_2_EMPTY_V << TWAIFD_TXT_2_EMPTY_S)
-#define TWAIFD_TXT_2_EMPTY_V  0x00000001U
-#define TWAIFD_TXT_2_EMPTY_S  1
-
-/** TWAIFD_TX_CFG_REG register
- *  TWAI FD TX buffer configuration register
- */
-#define TWAIFD_TX_CFG_REG (DR_REG_TWAIFD_BASE + 0x98)
-/** TWAIFD_TXT_1_ALLOW : R/W; bitpos: [0]; default: 1;
- *  Configures whether or not allow transmitting frames from TX buffer1.\\
- *  0: not allow\\
- *  1: allow\\
- */
-#define TWAIFD_TXT_1_ALLOW    (BIT(0))
-#define TWAIFD_TXT_1_ALLOW_M  (TWAIFD_TXT_1_ALLOW_V << TWAIFD_TXT_1_ALLOW_S)
-#define TWAIFD_TXT_1_ALLOW_V  0x00000001U
-#define TWAIFD_TXT_1_ALLOW_S  0
-/** TWAIFD_TXT_2_ALLOW : R/W; bitpos: [1]; default: 1;
- *  Configures whether or not allow transmitting frames from TX buffer2.\\
- *  0: not allow\\
- *  1: allow\\
- */
-#define TWAIFD_TXT_2_ALLOW    (BIT(1))
-#define TWAIFD_TXT_2_ALLOW_M  (TWAIFD_TXT_2_ALLOW_V << TWAIFD_TXT_2_ALLOW_S)
-#define TWAIFD_TXT_2_ALLOW_V  0x00000001U
-#define TWAIFD_TXT_2_ALLOW_S  1
-/** TWAIFD_TXT_1_COMMIT : WT; bitpos: [2]; default: 0;
- *  Configures whether or not the frames from TX register are inserted into TX
- *  buffer1.\\
- *  0: not inserted\\
- *  1: inserted\\
- */
-#define TWAIFD_TXT_1_COMMIT    (BIT(2))
-#define TWAIFD_TXT_1_COMMIT_M  (TWAIFD_TXT_1_COMMIT_V << TWAIFD_TXT_1_COMMIT_S)
-#define TWAIFD_TXT_1_COMMIT_V  0x00000001U
-#define TWAIFD_TXT_1_COMMIT_S  2
-/** TWAIFD_TXT_2_COMMIT : WT; bitpos: [3]; default: 0;
- *  Configures whether or not the frames from TX register are inserted into TX
- *  buffer2.\\
- *  0: not inserted\\
- *  1: inserted\\
- */
-#define TWAIFD_TXT_2_COMMIT    (BIT(3))
-#define TWAIFD_TXT_2_COMMIT_M  (TWAIFD_TXT_2_COMMIT_V << TWAIFD_TXT_2_COMMIT_S)
-#define TWAIFD_TXT_2_COMMIT_V  0x00000001U
-#define TWAIFD_TXT_2_COMMIT_S  3
-
-/** TWAIFD_TX_DATA_0_REG register
- *  TWAI FD transmit data register 0
- */
-#define TWAIFD_TX_DATA_0_REG (DR_REG_TWAIFD_BASE + 0x9c)
-/** TWAIFD_DLC_TX : R/W; bitpos: [3:0]; default: 0;
- *  Configures the brs to be transmitted.
- */
-#define TWAIFD_DLC_TX    0x0000000FU
-#define TWAIFD_DLC_TX_M  (TWAIFD_DLC_TX_V << TWAIFD_DLC_TX_S)
-#define TWAIFD_DLC_TX_V  0x0000000FU
-#define TWAIFD_DLC_TX_S  0
-/** TWAIFD_RTR_TX : R/W; bitpos: [5]; default: 0;
- *  Configures the rtr bit to be transmitted.
- */
-#define TWAIFD_RTR_TX    (BIT(5))
-#define TWAIFD_RTR_TX_M  (TWAIFD_RTR_TX_V << TWAIFD_RTR_TX_S)
-#define TWAIFD_RTR_TX_V  0x00000001U
-#define TWAIFD_RTR_TX_S  5
-/** TWAIFD_ID_TYPE_TX : R/W; bitpos: [6]; default: 0;
- *  Configures the frame type to be transmitted.
- */
-#define TWAIFD_ID_TYPE_TX    (BIT(6))
-#define TWAIFD_ID_TYPE_TX_M  (TWAIFD_ID_TYPE_TX_V << TWAIFD_ID_TYPE_TX_S)
-#define TWAIFD_ID_TYPE_TX_V  0x00000001U
-#define TWAIFD_ID_TYPE_TX_S  6
-/** TWAIFD_FR_TYPE_TX : R/W; bitpos: [7]; default: 0;
- *  Configures the fd type to be transmitted.
- */
-#define TWAIFD_FR_TYPE_TX    (BIT(7))
-#define TWAIFD_FR_TYPE_TX_M  (TWAIFD_FR_TYPE_TX_V << TWAIFD_FR_TYPE_TX_S)
-#define TWAIFD_FR_TYPE_TX_V  0x00000001U
-#define TWAIFD_FR_TYPE_TX_S  7
-/** TWAIFD_TBF_TX : R/W; bitpos: [8]; default: 0;
- *  Configures the tbf bit to be transmitted.
- */
-#define TWAIFD_TBF_TX    (BIT(8))
-#define TWAIFD_TBF_TX_M  (TWAIFD_TBF_TX_V << TWAIFD_TBF_TX_S)
-#define TWAIFD_TBF_TX_V  0x00000001U
-#define TWAIFD_TBF_TX_S  8
-/** TWAIFD_BRS_TX : R/W; bitpos: [9]; default: 0;
- *  Configures the brs bit to be transmitted.
- */
-#define TWAIFD_BRS_TX    (BIT(9))
-#define TWAIFD_BRS_TX_M  (TWAIFD_BRS_TX_V << TWAIFD_BRS_TX_S)
-#define TWAIFD_BRS_TX_V  0x00000001U
-#define TWAIFD_BRS_TX_S  9
-
-/** TWAIFD_TX_DATA_1_REG register
- *  TWAI FD transmit data register 1
- */
-#define TWAIFD_TX_DATA_1_REG (DR_REG_TWAIFD_BASE + 0xa0)
-/** TWAIFD_TS_VAL_U_TX : R/W; bitpos: [31:0]; default: 0;
- *  Configures the upper timestamp to be transmitted
- */
-#define TWAIFD_TS_VAL_U_TX    0xFFFFFFFFU
-#define TWAIFD_TS_VAL_U_TX_M  (TWAIFD_TS_VAL_U_TX_V << TWAIFD_TS_VAL_U_TX_S)
-#define TWAIFD_TS_VAL_U_TX_V  0xFFFFFFFFU
-#define TWAIFD_TS_VAL_U_TX_S  0
-
-/** TWAIFD_TX_DATA_2_REG register
- *  TWAI FD transmit data register 2
- */
-#define TWAIFD_TX_DATA_2_REG (DR_REG_TWAIFD_BASE + 0xa4)
-/** TWAIFD_TS_VAL_L_TX : R/W; bitpos: [31:0]; default: 0;
- *  Configures the lower timestamp to be transmitted
- */
-#define TWAIFD_TS_VAL_L_TX    0xFFFFFFFFU
-#define TWAIFD_TS_VAL_L_TX_M  (TWAIFD_TS_VAL_L_TX_V << TWAIFD_TS_VAL_L_TX_S)
-#define TWAIFD_TS_VAL_L_TX_V  0xFFFFFFFFU
-#define TWAIFD_TS_VAL_L_TX_S  0
-
-/** TWAIFD_TX_DATA_3_REG register
- *  TWAI FD transmit data register 3
- */
-#define TWAIFD_TX_DATA_3_REG (DR_REG_TWAIFD_BASE + 0xa8)
-/** TWAIFD_ID_EXT_TX : R/W; bitpos: [17:0]; default: 0;
- *  Configures the base ID to be transmitted
- */
-#define TWAIFD_ID_EXT_TX    0x0003FFFFU
-#define TWAIFD_ID_EXT_TX_M  (TWAIFD_ID_EXT_TX_V << TWAIFD_ID_EXT_TX_S)
-#define TWAIFD_ID_EXT_TX_V  0x0003FFFFU
-#define TWAIFD_ID_EXT_TX_S  0
-/** TWAIFD_ID_BASE_TX : R/W; bitpos: [28:18]; default: 0;
- *  Configures the extended ID to be transmitted
- */
-#define TWAIFD_ID_BASE_TX    0x000007FFU
-#define TWAIFD_ID_BASE_TX_M  (TWAIFD_ID_BASE_TX_V << TWAIFD_ID_BASE_TX_S)
-#define TWAIFD_ID_BASE_TX_V  0x000007FFU
-#define TWAIFD_ID_BASE_TX_S  18
-
-/** TWAIFD_TX_DATA_4_REG register
- *  TWAI FD transmit data register 4
- */
-#define TWAIFD_TX_DATA_4_REG (DR_REG_TWAIFD_BASE + 0xac)
-/** TWAIFD_TX_DATA0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th word to be transmitted
- */
-#define TWAIFD_TX_DATA0    0xFFFFFFFFU
-#define TWAIFD_TX_DATA0_M  (TWAIFD_TX_DATA0_V << TWAIFD_TX_DATA0_S)
-#define TWAIFD_TX_DATA0_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA0_S  0
-
-/** TWAIFD_TX_DATA_5_REG register
- *  TWAI FD transmit data register 5
- */
-#define TWAIFD_TX_DATA_5_REG (DR_REG_TWAIFD_BASE + 0xb0)
-/** TWAIFD_TX_DATA1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1th word to be transmitted
- */
-#define TWAIFD_TX_DATA1    0xFFFFFFFFU
-#define TWAIFD_TX_DATA1_M  (TWAIFD_TX_DATA1_V << TWAIFD_TX_DATA1_S)
-#define TWAIFD_TX_DATA1_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA1_S  0
-
-/** TWAIFD_TX_DATA_6_REG register
- *  TWAI FD transmit data register 6
- */
-#define TWAIFD_TX_DATA_6_REG (DR_REG_TWAIFD_BASE + 0xb4)
-/** TWAIFD_TX_DATA2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2th word to be transmitted
- */
-#define TWAIFD_TX_DATA2    0xFFFFFFFFU
-#define TWAIFD_TX_DATA2_M  (TWAIFD_TX_DATA2_V << TWAIFD_TX_DATA2_S)
-#define TWAIFD_TX_DATA2_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA2_S  0
-
-/** TWAIFD_TX_DATA_7_REG register
- *  TWAI FD transmit data register 7
- */
-#define TWAIFD_TX_DATA_7_REG (DR_REG_TWAIFD_BASE + 0xb8)
-/** TWAIFD_TX_DATA3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3th word to be transmitted
- */
-#define TWAIFD_TX_DATA3    0xFFFFFFFFU
-#define TWAIFD_TX_DATA3_M  (TWAIFD_TX_DATA3_V << TWAIFD_TX_DATA3_S)
-#define TWAIFD_TX_DATA3_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA3_S  0
-
-/** TWAIFD_TX_DATA_8_REG register
- *  TWAI FD transmit data register 8
- */
-#define TWAIFD_TX_DATA_8_REG (DR_REG_TWAIFD_BASE + 0xbc)
-/** TWAIFD_TX_DATA4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th word to be transmitted
- */
-#define TWAIFD_TX_DATA4    0xFFFFFFFFU
-#define TWAIFD_TX_DATA4_M  (TWAIFD_TX_DATA4_V << TWAIFD_TX_DATA4_S)
-#define TWAIFD_TX_DATA4_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA4_S  0
-
-/** TWAIFD_TX_DATA_9_REG register
- *  TWAI FD transmit data register 9
- */
-#define TWAIFD_TX_DATA_9_REG (DR_REG_TWAIFD_BASE + 0xc0)
-/** TWAIFD_TX_DATA5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th word to be transmitted
- */
-#define TWAIFD_TX_DATA5    0xFFFFFFFFU
-#define TWAIFD_TX_DATA5_M  (TWAIFD_TX_DATA5_V << TWAIFD_TX_DATA5_S)
-#define TWAIFD_TX_DATA5_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA5_S  0
-
-/** TWAIFD_TX_DATA_10_REG register
- *  TWAI FD transmit data register 10
- */
-#define TWAIFD_TX_DATA_10_REG (DR_REG_TWAIFD_BASE + 0xc4)
-/** TWAIFD_TX_DATA6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th word to be transmitted
- */
-#define TWAIFD_TX_DATA6    0xFFFFFFFFU
-#define TWAIFD_TX_DATA6_M  (TWAIFD_TX_DATA6_V << TWAIFD_TX_DATA6_S)
-#define TWAIFD_TX_DATA6_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA6_S  0
-
-/** TWAIFD_TX_DATA_11_REG register
- *  TWAI FD transmit data register 11
- */
-#define TWAIFD_TX_DATA_11_REG (DR_REG_TWAIFD_BASE + 0xc8)
-/** TWAIFD_TX_DATA7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th word to be transmitted
- */
-#define TWAIFD_TX_DATA7    0xFFFFFFFFU
-#define TWAIFD_TX_DATA7_M  (TWAIFD_TX_DATA7_V << TWAIFD_TX_DATA7_S)
-#define TWAIFD_TX_DATA7_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA7_S  0
-
-/** TWAIFD_TX_DATA_12_REG register
- *  TWAI FD transmit data register 12
- */
-#define TWAIFD_TX_DATA_12_REG (DR_REG_TWAIFD_BASE + 0xcc)
-/** TWAIFD_TX_DATA8 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 8th word to be transmitted
- */
-#define TWAIFD_TX_DATA8    0xFFFFFFFFU
-#define TWAIFD_TX_DATA8_M  (TWAIFD_TX_DATA8_V << TWAIFD_TX_DATA8_S)
-#define TWAIFD_TX_DATA8_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA8_S  0
-
-/** TWAIFD_TX_DATA_13_REG register
- *  TWAI FD transmit data register 13
- */
-#define TWAIFD_TX_DATA_13_REG (DR_REG_TWAIFD_BASE + 0xd0)
-/** TWAIFD_TX_DATA9 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 9th word to be transmitted
- */
-#define TWAIFD_TX_DATA9    0xFFFFFFFFU
-#define TWAIFD_TX_DATA9_M  (TWAIFD_TX_DATA9_V << TWAIFD_TX_DATA9_S)
-#define TWAIFD_TX_DATA9_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA9_S  0
-
-/** TWAIFD_TX_DATA_14_REG register
- *  TWAI FD transmit data register 14
- */
-#define TWAIFD_TX_DATA_14_REG (DR_REG_TWAIFD_BASE + 0xd4)
-/** TWAIFD_TX_DATA10 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 10th word to be transmitted
- */
-#define TWAIFD_TX_DATA10    0xFFFFFFFFU
-#define TWAIFD_TX_DATA10_M  (TWAIFD_TX_DATA10_V << TWAIFD_TX_DATA10_S)
-#define TWAIFD_TX_DATA10_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA10_S  0
-
-/** TWAIFD_TX_DATA_15_REG register
- *  TWAI FD transmit data register 15
- */
-#define TWAIFD_TX_DATA_15_REG (DR_REG_TWAIFD_BASE + 0xd8)
-/** TWAIFD_TX_DATA11 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 11th word to be transmitted
- */
-#define TWAIFD_TX_DATA11    0xFFFFFFFFU
-#define TWAIFD_TX_DATA11_M  (TWAIFD_TX_DATA11_V << TWAIFD_TX_DATA11_S)
-#define TWAIFD_TX_DATA11_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA11_S  0
-
-/** TWAIFD_TX_DATA_16_REG register
- *  TWAI FD transmit data register 16
- */
-#define TWAIFD_TX_DATA_16_REG (DR_REG_TWAIFD_BASE + 0xdc)
-/** TWAIFD_TX_DATA12 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 12th word to be transmitted
- */
-#define TWAIFD_TX_DATA12    0xFFFFFFFFU
-#define TWAIFD_TX_DATA12_M  (TWAIFD_TX_DATA12_V << TWAIFD_TX_DATA12_S)
-#define TWAIFD_TX_DATA12_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA12_S  0
-
-/** TWAIFD_TX_DATA_17_REG register
- *  TWAI FD transmit data register 17
- */
-#define TWAIFD_TX_DATA_17_REG (DR_REG_TWAIFD_BASE + 0xe0)
-/** TWAIFD_TX_DATA13 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 13th word to be transmitted
- */
-#define TWAIFD_TX_DATA13    0xFFFFFFFFU
-#define TWAIFD_TX_DATA13_M  (TWAIFD_TX_DATA13_V << TWAIFD_TX_DATA13_S)
-#define TWAIFD_TX_DATA13_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA13_S  0
-
-/** TWAIFD_TX_DATA_18_REG register
- *  TWAI FD transmit data register 18
- */
-#define TWAIFD_TX_DATA_18_REG (DR_REG_TWAIFD_BASE + 0xe4)
-/** TWAIFD_TX_DATA14 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 14th word to be transmitted
- */
-#define TWAIFD_TX_DATA14    0xFFFFFFFFU
-#define TWAIFD_TX_DATA14_M  (TWAIFD_TX_DATA14_V << TWAIFD_TX_DATA14_S)
-#define TWAIFD_TX_DATA14_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA14_S  0
-
-/** TWAIFD_TX_DATA_19_REG register
- *  TWAI FD transmit data register 19
- */
-#define TWAIFD_TX_DATA_19_REG (DR_REG_TWAIFD_BASE + 0xe8)
-/** TWAIFD_TX_DATA15 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 15th word to be transmitted
- */
-#define TWAIFD_TX_DATA15    0xFFFFFFFFU
-#define TWAIFD_TX_DATA15_M  (TWAIFD_TX_DATA15_V << TWAIFD_TX_DATA15_S)
-#define TWAIFD_TX_DATA15_V  0xFFFFFFFFU
-#define TWAIFD_TX_DATA15_S  0
-
-/** TWAIFD_TX_CAMMAND_INFO_REG register
- *  TWAI FD TXT buffer command & information register
- */
-#define TWAIFD_TX_CAMMAND_INFO_REG (DR_REG_TWAIFD_BASE + 0x14c)
-/** TWAIFD_TXTB_SW_SET_ETY : R/W; bitpos: [0]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXTB_SW_SET_ETY    (BIT(0))
-#define TWAIFD_TXTB_SW_SET_ETY_M  (TWAIFD_TXTB_SW_SET_ETY_V << TWAIFD_TXTB_SW_SET_ETY_S)
-#define TWAIFD_TXTB_SW_SET_ETY_V  0x00000001U
-#define TWAIFD_TXTB_SW_SET_ETY_S  0
-/** TWAIFD_TXTB_SW_SET_RDY : R/W; bitpos: [1]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXTB_SW_SET_RDY    (BIT(1))
-#define TWAIFD_TXTB_SW_SET_RDY_M  (TWAIFD_TXTB_SW_SET_RDY_V << TWAIFD_TXTB_SW_SET_RDY_S)
-#define TWAIFD_TXTB_SW_SET_RDY_V  0x00000001U
-#define TWAIFD_TXTB_SW_SET_RDY_S  1
-/** TWAIFD_TXTB_SW_SET_ABT : R/W; bitpos: [2]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXTB_SW_SET_ABT    (BIT(2))
-#define TWAIFD_TXTB_SW_SET_ABT_M  (TWAIFD_TXTB_SW_SET_ABT_V << TWAIFD_TXTB_SW_SET_ABT_S)
-#define TWAIFD_TXTB_SW_SET_ABT_V  0x00000001U
-#define TWAIFD_TXTB_SW_SET_ABT_S  2
-/** TWAIFD_TXB1 : R/W; bitpos: [8]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB1    (BIT(8))
-#define TWAIFD_TXB1_M  (TWAIFD_TXB1_V << TWAIFD_TXB1_S)
-#define TWAIFD_TXB1_V  0x00000001U
-#define TWAIFD_TXB1_S  8
-/** TWAIFD_TXB2 : R/W; bitpos: [9]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB2    (BIT(9))
-#define TWAIFD_TXB2_M  (TWAIFD_TXB2_V << TWAIFD_TXB2_S)
-#define TWAIFD_TXB2_V  0x00000001U
-#define TWAIFD_TXB2_S  9
-/** TWAIFD_TXB3 : R/W; bitpos: [10]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB3    (BIT(10))
-#define TWAIFD_TXB3_M  (TWAIFD_TXB3_V << TWAIFD_TXB3_S)
-#define TWAIFD_TXB3_V  0x00000001U
-#define TWAIFD_TXB3_S  10
-/** TWAIFD_TXB4 : R/W; bitpos: [11]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB4    (BIT(11))
-#define TWAIFD_TXB4_M  (TWAIFD_TXB4_V << TWAIFD_TXB4_S)
-#define TWAIFD_TXB4_V  0x00000001U
-#define TWAIFD_TXB4_S  11
-/** TWAIFD_TXB5 : R/W; bitpos: [12]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB5    (BIT(12))
-#define TWAIFD_TXB5_M  (TWAIFD_TXB5_V << TWAIFD_TXB5_S)
-#define TWAIFD_TXB5_V  0x00000001U
-#define TWAIFD_TXB5_S  12
-/** TWAIFD_TXB6 : R/W; bitpos: [13]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB6    (BIT(13))
-#define TWAIFD_TXB6_M  (TWAIFD_TXB6_V << TWAIFD_TXB6_S)
-#define TWAIFD_TXB6_V  0x00000001U
-#define TWAIFD_TXB6_S  13
-/** TWAIFD_TXB7 : R/W; bitpos: [14]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB7    (BIT(14))
-#define TWAIFD_TXB7_M  (TWAIFD_TXB7_V << TWAIFD_TXB7_S)
-#define TWAIFD_TXB7_V  0x00000001U
-#define TWAIFD_TXB7_S  14
-/** TWAIFD_TXB8 : R/W; bitpos: [15]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXB8    (BIT(15))
-#define TWAIFD_TXB8_M  (TWAIFD_TXB8_V << TWAIFD_TXB8_S)
-#define TWAIFD_TXB8_V  0x00000001U
-#define TWAIFD_TXB8_S  15
-/** TWAIFD_TXT_BUF_CTR : R/W; bitpos: [19:16]; default: 0;
- *  a\\
- */
-#define TWAIFD_TXT_BUF_CTR    0x0000000FU
-#define TWAIFD_TXT_BUF_CTR_M  (TWAIFD_TXT_BUF_CTR_V << TWAIFD_TXT_BUF_CTR_S)
-#define TWAIFD_TXT_BUF_CTR_V  0x0000000FU
-#define TWAIFD_TXT_BUF_CTR_S  16
-
-/** TWAIFD_ERR_CAP_RETR_CTR_ALC_REG register
- *  TWAI FD error capture & retransmit counter & arbitration lost register
- */
-#define TWAIFD_ERR_CAP_RETR_CTR_ALC_REG (DR_REG_TWAIFD_BASE + 0x160)
-/** TWAIFD_ERR_TYPE : RO; bitpos: [4:0]; default: 0;
- *  a\\
- */
-#define TWAIFD_ERR_TYPE    0x0000001FU
-#define TWAIFD_ERR_TYPE_M  (TWAIFD_ERR_TYPE_V << TWAIFD_ERR_TYPE_S)
-#define TWAIFD_ERR_TYPE_V  0x0000001FU
-#define TWAIFD_ERR_TYPE_S  0
-/** TWAIFD_ERR_POS : RO; bitpos: [7:5]; default: 0;
- *  a\\
- */
-#define TWAIFD_ERR_POS    0x00000007U
-#define TWAIFD_ERR_POS_M  (TWAIFD_ERR_POS_V << TWAIFD_ERR_POS_S)
-#define TWAIFD_ERR_POS_V  0x00000007U
-#define TWAIFD_ERR_POS_S  5
-/** TWAIFD_RETR_CTR : RO; bitpos: [11:8]; default: 0;
- *  a\\
- */
-#define TWAIFD_RETR_CTR    0x0000000FU
-#define TWAIFD_RETR_CTR_M  (TWAIFD_RETR_CTR_V << TWAIFD_RETR_CTR_S)
-#define TWAIFD_RETR_CTR_V  0x0000000FU
-#define TWAIFD_RETR_CTR_S  8
-/** TWAIFD_ALC_BIT : RO; bitpos: [20:16]; default: 0;
- *  a\\
- */
-#define TWAIFD_ALC_BIT    0x0000001FU
-#define TWAIFD_ALC_BIT_M  (TWAIFD_ALC_BIT_V << TWAIFD_ALC_BIT_S)
-#define TWAIFD_ALC_BIT_V  0x0000001FU
-#define TWAIFD_ALC_BIT_S  16
-/** TWAIFD_ALC_ID_FIELD : RO; bitpos: [23:21]; default: 0;
- *  a\\
- */
-#define TWAIFD_ALC_ID_FIELD    0x00000007U
-#define TWAIFD_ALC_ID_FIELD_M  (TWAIFD_ALC_ID_FIELD_V << TWAIFD_ALC_ID_FIELD_S)
-#define TWAIFD_ALC_ID_FIELD_V  0x00000007U
-#define TWAIFD_ALC_ID_FIELD_S  21
-
-/** TWAIFD_TRV_DELAY_SSP_CFG_REG register
- *  TWAI FD transmit delay & secondary sample point configuration register
- */
-#define TWAIFD_TRV_DELAY_SSP_CFG_REG (DR_REG_TWAIFD_BASE + 0x164)
-/** TWAIFD_TRV_DELAY_VALUE : RO; bitpos: [6:0]; default: 0;
- *  a\\
- */
-#define TWAIFD_TRV_DELAY_VALUE    0x0000007FU
-#define TWAIFD_TRV_DELAY_VALUE_M  (TWAIFD_TRV_DELAY_VALUE_V << TWAIFD_TRV_DELAY_VALUE_S)
-#define TWAIFD_TRV_DELAY_VALUE_V  0x0000007FU
-#define TWAIFD_TRV_DELAY_VALUE_S  0
-/** TWAIFD_SSP_OFFSET : R/W; bitpos: [23:16]; default: 10;
- *  a\\
- */
-#define TWAIFD_SSP_OFFSET    0x000000FFU
-#define TWAIFD_SSP_OFFSET_M  (TWAIFD_SSP_OFFSET_V << TWAIFD_SSP_OFFSET_S)
-#define TWAIFD_SSP_OFFSET_V  0x000000FFU
-#define TWAIFD_SSP_OFFSET_S  16
-/** TWAIFD_SSP_SRC : R/W; bitpos: [25:24]; default: 0;
- *  a\\
- */
-#define TWAIFD_SSP_SRC    0x00000003U
-#define TWAIFD_SSP_SRC_M  (TWAIFD_SSP_SRC_V << TWAIFD_SSP_SRC_S)
-#define TWAIFD_SSP_SRC_V  0x00000003U
-#define TWAIFD_SSP_SRC_S  24
-
-/** TWAIFD_RX_FRM_COUNTER_REG register
- *  TWAI FD received frame counter register
- */
-#define TWAIFD_RX_FRM_COUNTER_REG (DR_REG_TWAIFD_BASE + 0x180)
-/** TWAIFD_RX_COUNTER_VAL : RO; bitpos: [31:0]; default: 0;
- *  Configures the received frame counters to enable bus traffic measurement.
- */
-#define TWAIFD_RX_COUNTER_VAL    0xFFFFFFFFU
-#define TWAIFD_RX_COUNTER_VAL_M  (TWAIFD_RX_COUNTER_VAL_V << TWAIFD_RX_COUNTER_VAL_S)
-#define TWAIFD_RX_COUNTER_VAL_V  0xFFFFFFFFU
-#define TWAIFD_RX_COUNTER_VAL_S  0
-
-/** TWAIFD_TX_FRM_COUNTER_REG register
- *  TWAI FD transmitted frame counter register
- */
-#define TWAIFD_TX_FRM_COUNTER_REG (DR_REG_TWAIFD_BASE + 0x184)
-/** TWAIFD_TX_COUNTER_VAL : RO; bitpos: [31:0]; default: 0;
- *  Configures the transcieved frame counters to enable bus traffic measurement.
- */
-#define TWAIFD_TX_COUNTER_VAL    0xFFFFFFFFU
-#define TWAIFD_TX_COUNTER_VAL_M  (TWAIFD_TX_COUNTER_VAL_V << TWAIFD_TX_COUNTER_VAL_S)
-#define TWAIFD_TX_COUNTER_VAL_V  0xFFFFFFFFU
-#define TWAIFD_TX_COUNTER_VAL_S  0
-
-/** TWAIFD_CLK_REG register
- *  TWAI FD clock configuration register
- */
-#define TWAIFD_CLK_REG (DR_REG_TWAIFD_BASE + 0x18c)
-/** TWAIFD_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
- *  registers.
- */
-#define TWAIFD_CLK_EN    (BIT(31))
-#define TWAIFD_CLK_EN_M  (TWAIFD_CLK_EN_V << TWAIFD_CLK_EN_S)
-#define TWAIFD_CLK_EN_V  0x00000001U
-#define TWAIFD_CLK_EN_S  31
-
-/** TWAIFD_DATE_REG register
- *  TWAI FD version register
- */
-#define TWAIFD_DATE_REG (DR_REG_TWAIFD_BASE + 0x190)
-/** TWAIFD_TWAIFD_DATE : R/W; bitpos: [31:0]; default: 35717712;
- *  This is the version register.
- */
-#define TWAIFD_TWAIFD_DATE    0xFFFFFFFFU
-#define TWAIFD_TWAIFD_DATE_M  (TWAIFD_TWAIFD_DATE_V << TWAIFD_TWAIFD_DATE_S)
-#define TWAIFD_TWAIFD_DATE_V  0xFFFFFFFFU
-#define TWAIFD_TWAIFD_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/twaifd_struct.h b/components/soc/esp32p4/include/soc/twaifd_struct.h
deleted file mode 100644
index d0c0a3cd1e..0000000000
--- a/components/soc/esp32p4/include/soc/twaifd_struct.h
+++ /dev/null
@@ -1,1548 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: ID register */
-/** Type of device_id register
- *  TWAI FD device id status register
- */
-typedef union {
-    struct {
-        /** device_id : R/W; bitpos: [31:0]; default: 51965;
-         *  Represents whether CAN IP function is mapped correctly on its base address.
-         */
-        uint32_t device_id:32;
-    };
-    uint32_t val;
-} twaifd_device_id_reg_t;
-
-
-/** Group: Configuration register */
-/** Type of mode_setting register
- *  TWAI FD mode setting register
- */
-typedef union {
-    struct {
-        /** sw_reset : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to reset the TWAI FD controller.\\
-         *  0: invalid\\
-         *  1: reset.\\
-         */
-        uint32_t sw_reset:1;
-        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
-         *  bus monitor enable
-         */
-        uint32_t listen_only_mode:1;
-        /** self_test_mode : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable the self test mode.\\
-         *  0: disable\\
-         *  1: enable\\
-         */
-        uint32_t self_test_mode:1;
-        /** accept_filter_mode : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable the usage of acceptance filters.\\
-         *  0: disable\\
-         *  1: enable\\
-         */
-        uint32_t accept_filter_mode:1;
-        /** flexible_data_rate : R/W; bitpos: [4]; default: 1;
-         *  Configures whether or not to support flexible data rate.\\
-         *  0: not support\\
-         *  1: support\\
-         */
-        uint32_t flexible_data_rate:1;
-        /** rtr_frm_behavior : R/W; bitpos: [5]; default: 0;
-         *  time_triggered transmission mode
-         */
-        uint32_t rtr_frm_behavior:1;
-        /** rom : R/W; bitpos: [6]; default: 0;
-         *  a\\
-         */
-        uint32_t rom:1;
-        /** ack_behavior : R/W; bitpos: [7]; default: 0;
-         *  Configures the acknowledge behavior.\\
-         *  0: normal behavior.\\
-         *  1: acknowledge is not sent.\\
-         */
-        uint32_t ack_behavior:1;
-        /** test_mode : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable the triple sampling mode.\\
-         *  0: disable\\
-         *  1: enable\\
-         */
-        uint32_t test_mode:1;
-        /** rxbam : R/W; bitpos: [9]; default: 1;
-         *  a\\
-         */
-        uint32_t rxbam:1;
-        uint32_t reserved_10:6;
-        /** limit_retx_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable the limit of retransmission.\\
-         *  0: disable\\
-         *  1: enable\\
-         */
-        uint32_t limit_retx_en:1;
-        /** retx_thres : R/W; bitpos: [20:17]; default: 0;
-         *  Configures the threshold of retransmission attempts. \\
-         */
-        uint32_t retx_thres:4;
-        /** ilbp : R/W; bitpos: [21]; default: 0;
-         *  acknowledge forbidden mode
-         */
-        uint32_t ilbp:1;
-        /** ctrl_en : R/W; bitpos: [22]; default: 0;
-         *  Configures whether or not to enable the twai FD controller.\\
-         *  0: disable\\
-         *  1: enable\\
-         */
-        uint32_t ctrl_en:1;
-        /** fd_type : R/W; bitpos: [23]; default: 0;
-         *  Configure the twai fd frame type.\\
-         *  0: ISO CAN FD\\
-         *  1: CAN FD 1.0\\
-         */
-        uint32_t fd_type:1;
-        /** pex : R/W; bitpos: [24]; default: 0;
-         *  protocol expection mode\\
-         */
-        uint32_t pex:1;
-        /** tbfbo : R/W; bitpos: [25]; default: 1;
-         *  a\\
-         */
-        uint32_t tbfbo:1;
-        /** fdrf : R/W; bitpos: [26]; default: 0;
-         *  a\\
-         */
-        uint32_t fdrf:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} twaifd_mode_setting_reg_t;
-
-/** Type of command register
- *  TWAI FD command register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** rxrpmv : WO; bitpos: [1]; default: 0;
-         *  a\\
-         */
-        uint32_t rxrpmv:1;
-        /** release_rx_buf : WO; bitpos: [2]; default: 0;
-         *  Configures whether or not to delete all data from the receive buffer.\\
-         *  0: invalid\\
-         *  1: delete\\
-         */
-        uint32_t release_rx_buf:1;
-        /** clr_overrun_flg : WO; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear the data overrun flag.\\
-         *  0: invalid\\
-         *  1: clear\\
-         */
-        uint32_t clr_overrun_flg:1;
-        /** ercrst : WO; bitpos: [4]; default: 0;
-         *  a\\
-         */
-        uint32_t ercrst:1;
-        /** rxfcrst : WO; bitpos: [5]; default: 0;
-         *  a\\
-         */
-        uint32_t rxfcrst:1;
-        /** txfcrst : WO; bitpos: [6]; default: 0;
-         *  a\\
-         */
-        uint32_t txfcrst:1;
-        /** cpexs : WO; bitpos: [7]; default: 0;
-         *  a\\
-         */
-        uint32_t cpexs:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twaifd_command_reg_t;
-
-/** Type of bit_timing register
- *  TWAI FD bit-timing  register
- */
-typedef union {
-    struct {
-        /** prop : R/W; bitpos: [6:0]; default: 5;
-         *  Configures the propagation segment of nominal bit rate.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t prop:7;
-        /** ph1 : R/W; bitpos: [12:7]; default: 3;
-         *  Configures the phase 1 segment of nominal bit rate.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t ph1:6;
-        /** ph2 : R/W; bitpos: [18:13]; default: 5;
-         *  Configures the phase 2 segment of nominal bit rate.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t ph2:6;
-        /** brp : R/W; bitpos: [26:19]; default: 16;
-         *  Configures the baud-rate prescaler of nominal bit rate.\\
-         *  Measurement unit: cycle of core clock.
-         */
-        uint32_t brp:8;
-        /** sjw : R/W; bitpos: [31:27]; default: 2;
-         *  Represents the synchronization jump width in nominal bit time.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t sjw:5;
-    };
-    uint32_t val;
-} twaifd_bit_timing_reg_t;
-
-/** Type of bit_timeing_fd register
- *  TWAI FD bit-timing of FD register
- */
-typedef union {
-    struct {
-        /** prop_fd : R/W; bitpos: [5:0]; default: 3;
-         *  Configures the propagation segment of data bit rate.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t prop_fd:6;
-        uint32_t reserved_6:1;
-        /** ph1_fd : R/W; bitpos: [11:7]; default: 3;
-         *  Configures the phase 1 segment of data bit rate.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t ph1_fd:5;
-        uint32_t reserved_12:1;
-        /** ph2_fd : R/W; bitpos: [17:13]; default: 3;
-         *  Configures the phase 2 segment of data bit rate.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t ph2_fd:5;
-        uint32_t reserved_18:1;
-        /** brp_fd : R/W; bitpos: [26:19]; default: 4;
-         *  Configures the baud-rate prescaler of data bit rate.\\
-         *  Measurement unit: cycle of core clock.
-         */
-        uint32_t brp_fd:8;
-        /** sjw_fd : R/W; bitpos: [31:27]; default: 2;
-         *  Represents the synchronization jump width in data bit time.\\
-         *  Measurement unit: time quanta\\
-         */
-        uint32_t sjw_fd:5;
-    };
-    uint32_t val;
-} twaifd_bit_timeing_fd_reg_t;
-
-/** Type of tx_cfg register
- *  TWAI FD TX buffer configuration register
- */
-typedef union {
-    struct {
-        /** txt_1_allow : R/W; bitpos: [0]; default: 1;
-         *  Configures whether or not allow transmitting frames from TX buffer1.\\
-         *  0: not allow\\
-         *  1: allow\\
-         */
-        uint32_t txt_1_allow:1;
-        /** txt_2_allow : R/W; bitpos: [1]; default: 1;
-         *  Configures whether or not allow transmitting frames from TX buffer2.\\
-         *  0: not allow\\
-         *  1: allow\\
-         */
-        uint32_t txt_2_allow:1;
-        /** txt_1_commit : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not the frames from TX register are inserted into TX
-         *  buffer1.\\
-         *  0: not inserted\\
-         *  1: inserted\\
-         */
-        uint32_t txt_1_commit:1;
-        /** txt_2_commit : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not the frames from TX register are inserted into TX
-         *  buffer2.\\
-         *  0: not inserted\\
-         *  1: inserted\\
-         */
-        uint32_t txt_2_commit:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} twaifd_tx_cfg_reg_t;
-
-/** Type of trv_delay_ssp_cfg register
- *  TWAI FD transmit delay & secondary sample point configuration register
- */
-typedef union {
-    struct {
-        /** trv_delay_value : RO; bitpos: [6:0]; default: 0;
-         *  a\\
-         */
-        uint32_t trv_delay_value:7;
-        uint32_t reserved_7:9;
-        /** ssp_offset : R/W; bitpos: [23:16]; default: 10;
-         *  a\\
-         */
-        uint32_t ssp_offset:8;
-        /** ssp_src : R/W; bitpos: [25:24]; default: 0;
-         *  a\\
-         */
-        uint32_t ssp_src:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} twaifd_trv_delay_ssp_cfg_reg_t;
-
-
-/** Group: Status register */
-/** Type of status register
- *  TWAI FD status register
- */
-typedef union {
-    struct {
-        /** rx_buf_stat : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not the receive buffer is empty.\\
-         *  0: empty\\
-         *  1: not empty\\
-         */
-        uint32_t rx_buf_stat:1;
-        /** data_overrun_flg : RO; bitpos: [1]; default: 0;
-         *  Represents whether or not the receive buffer is full and the frame is
-         *  overrun(lost).\\
-         *  0: not overrun\\
-         *  1: overrun\\
-         */
-        uint32_t data_overrun_flg:1;
-        /** tx_buf_sat : RO; bitpos: [2]; default: 0;
-         *  Represents whether or not the transmit buffer is full.\\
-         *  0: not full\\
-         *  1: full\\
-         */
-        uint32_t tx_buf_sat:1;
-        /** err_frm_tx : RO; bitpos: [3]; default: 0;
-         *  Represents whether or not the error frame is being transmitted.\\
-         *  0: not being transmitted\\
-         *  1: being transmitted\\
-         */
-        uint32_t err_frm_tx:1;
-        /** rx_frm_stat : RO; bitpos: [4]; default: 0;
-         *  Represents whether or not the controller is receiving a frame.\\
-         *  0: not receiving\\
-         *  1: receiving\\
-         */
-        uint32_t rx_frm_stat:1;
-        /** tx_frm_stat : RO; bitpos: [5]; default: 0;
-         *  Represents whether or not the controller is transmitting a frame.\\
-         *  0: not transmitting\\
-         *  1: transmitting\\
-         */
-        uint32_t tx_frm_stat:1;
-        /** err_stat : RO; bitpos: [6]; default: 0;
-         *  Represents whether or not the error warning limit is reached.\\
-         *  0: not reached\\
-         *  1: reached\\
-         */
-        uint32_t err_stat:1;
-        /** bus_stat : RO; bitpos: [7]; default: 1;
-         *  Represents whether or not bus is active.\\
-         *  0: active\\
-         *  1: not active\\
-         */
-        uint32_t bus_stat:1;
-        /** pexs : RO; bitpos: [8]; default: 0;
-         *  a\\
-         */
-        uint32_t pexs:1;
-        /** reintegrating_wait : RO; bitpos: [9]; default: 0;
-         *  fsm is in reintegrating wait status
-         */
-        uint32_t reintegrating_wait:1;
-        uint32_t reserved_10:6;
-        /** stcnt : RO; bitpos: [16]; default: 0;
-         *  a\\
-         */
-        uint32_t stcnt:1;
-        /** strgs : RO; bitpos: [17]; default: 0;
-         *  a\\
-         */
-        uint32_t strgs:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} twaifd_status_reg_t;
-
-/** Type of rx_mem_info register
- *  TWAI FD rx memory information register
- */
-typedef union {
-    struct {
-        /** rx_buff_size_val : RO; bitpos: [12:0]; default: 0;
-         *  Represents the size of RX buffer.\\
-         */
-        uint32_t rx_buff_size_val:13;
-        uint32_t reserved_13:3;
-        /** rx_free_ctr : RO; bitpos: [28:16]; default: 0;
-         *  Represents the number of free words in RX buffer.\\
-         */
-        uint32_t rx_free_ctr:13;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_rx_mem_info_reg_t;
-
-/** Type of rx_pointers register
- *  TWAI FD rx memory pointer information register
- */
-typedef union {
-    struct {
-        /** rx_wpt_val : RO; bitpos: [11:0]; default: 0;
-         *  Represents the write pointer position in RX buffer.\\
-         */
-        uint32_t rx_wpt_val:12;
-        uint32_t reserved_12:4;
-        /** rx_rpt_val : RO; bitpos: [27:16]; default: 0;
-         *  Represents the read pointer position in RX buffer.\\
-         */
-        uint32_t rx_rpt_val:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} twaifd_rx_pointers_reg_t;
-
-/** Type of rx_status_setting register
- *  TWAI FD tx status & setting register
- */
-typedef union {
-    struct {
-        /** rx_empty : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not the RX buffer is empty.\\
-         *  0: not empty\\
-         *  1: empty\\
-         */
-        uint32_t rx_empty:1;
-        /** rx_full : RO; bitpos: [1]; default: 0;
-         *  Represents whether or not the RX buffer is full.\\
-         *  0: not full\\
-         *  1: full\\
-         */
-        uint32_t rx_full:1;
-        uint32_t reserved_2:2;
-        /** rx_frm_ctr : RO; bitpos: [14:4]; default: 0;
-         *  Represents the number of received frame in RX buffer.\\
-         */
-        uint32_t rx_frm_ctr:11;
-        uint32_t reserved_15:1;
-        /** rtsop : R/W; bitpos: [16]; default: 0;
-         *  a\\
-         */
-        uint32_t rtsop:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} twaifd_rx_status_setting_reg_t;
-
-/** Type of tx_stat register
- *  TWAI FD TX buffer status register
- */
-typedef union {
-    struct {
-        /** txt_1_empty : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not the TX buffer1 is empty.\\
-         *  0: not empty\\
-         *  1: empty\\
-         */
-        uint32_t txt_1_empty:1;
-        /** txt_2_empty : RO; bitpos: [1]; default: 0;
-         *  Represents whether or not the TX buffer2 is empty.\\
-         *  0: not empty\\
-         *  1: empty\\
-         */
-        uint32_t txt_2_empty:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} twaifd_tx_stat_reg_t;
-
-/** Type of err_cap_retr_ctr_alc register
- *  TWAI FD error capture & retransmit counter & arbitration lost register
- */
-typedef union {
-    struct {
-        /** err_type : RO; bitpos: [4:0]; default: 0;
-         *  a\\
-         */
-        uint32_t err_type:5;
-        /** err_pos : RO; bitpos: [7:5]; default: 0;
-         *  a\\
-         */
-        uint32_t err_pos:3;
-        /** retr_ctr : RO; bitpos: [11:8]; default: 0;
-         *  a\\
-         */
-        uint32_t retr_ctr:4;
-        uint32_t reserved_12:4;
-        /** alc_bit : RO; bitpos: [20:16]; default: 0;
-         *  a\\
-         */
-        uint32_t alc_bit:5;
-        /** alc_id_field : RO; bitpos: [23:21]; default: 0;
-         *  a\\
-         */
-        uint32_t alc_id_field:3;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} twaifd_err_cap_retr_ctr_alc_reg_t;
-
-
-/** Group: interrupt register */
-/** Type of int_raw register
- *  TWAI FD interrupt raw register
- */
-typedef union {
-    struct {
-        /** rx_frm_suc_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of TWAIFD_RX_FRM_SUC_INT.
-         */
-        uint32_t rx_frm_suc_int_raw:1;
-        /** tx_frm_suc_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status of TWAIFD_TX_FRM_SUC_INT.
-         */
-        uint32_t tx_frm_suc_int_raw:1;
-        /** err_warning_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of TWAIFD_ERR_WARNING_INT.
-         */
-        uint32_t err_warning_int_raw:1;
-        /** rx_data_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
-         */
-        uint32_t rx_data_overrun_int_raw:1;
-        uint32_t reserved_4:1;
-        /** fault_confinement_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
-         */
-        uint32_t fault_confinement_chg_int_raw:1;
-        /** arb_lost_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt status of TWAIFD_ARB_LOST_INT.
-         */
-        uint32_t arb_lost_int_raw:1;
-        /** err_detected_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt status of TWAIFD_ERR_DETECTED_INT.
-         */
-        uint32_t err_detected_int_raw:1;
-        /** is_overload_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt status of TWAIFD_IS_OVERLOAD_INT.
-         */
-        uint32_t is_overload_int_raw:1;
-        /** rx_buf_full_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt status of TWAIFD_RX_BUF_FULL_INT.
-         */
-        uint32_t rx_buf_full_int_raw:1;
-        /** bit_rate_shift_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
-         */
-        uint32_t bit_rate_shift_int_raw:1;
-        /** rx_buf_not_empty_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
-         */
-        uint32_t rx_buf_not_empty_int_raw:1;
-        /** tx_buf_status_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
-         */
-        uint32_t tx_buf_status_chg_int_raw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} twaifd_int_raw_reg_t;
-
-/** Type of int_ena register
- *  TWAI FD interrupt enable register
- */
-typedef union {
-    struct {
-        /** rx_frm_suc_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable TWAIFD_RX_FRM_SUC_INT.
-         */
-        uint32_t rx_frm_suc_int_ena:1;
-        /** tx_frm_suc_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable TWAIFD_TX_FRM_SUC_INT.
-         */
-        uint32_t tx_frm_suc_int_ena:1;
-        /** err_warning_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable TWAIFD_ERR_WARNING_INT.
-         */
-        uint32_t err_warning_int_ena:1;
-        /** rx_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable TWAIFD_RX_DATA_OVERRUN_INT.
-         */
-        uint32_t rx_data_overrun_int_ena:1;
-        uint32_t reserved_4:1;
-        /** fault_confinement_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable TWAIFD_FAULT_CONFINEMENT_CHG_INT.
-         */
-        uint32_t fault_confinement_chg_int_ena:1;
-        /** arb_lost_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to enable TWAIFD_ARB_LOST_INT.
-         */
-        uint32_t arb_lost_int_ena:1;
-        /** err_detected_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Write 1 to enable TWAIFD_ERR_DETECTED_INT.
-         */
-        uint32_t err_detected_int_ena:1;
-        /** is_overload_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to enable TWAIFD_IS_OVERLOAD_INT.
-         */
-        uint32_t is_overload_int_ena:1;
-        /** rx_buf_full_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to enable TWAIFD_RX_BUF_FULL_INT.
-         */
-        uint32_t rx_buf_full_int_ena:1;
-        /** bit_rate_shift_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Write 1 to enable TWAIFD_BIT_RATE_SHIFT_INT.
-         */
-        uint32_t bit_rate_shift_int_ena:1;
-        /** rx_buf_not_empty_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Write 1 to enable TWAIFD_RX_BUF_NOT_EMPTY_INT.
-         */
-        uint32_t rx_buf_not_empty_int_ena:1;
-        /** tx_buf_status_chg_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Write 1 to enable TWAIFD_TX_BUF_STATUS_CHG_INT.
-         */
-        uint32_t tx_buf_status_chg_int_ena:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} twaifd_int_ena_reg_t;
-
-/** Type of int_st register
- *  TWAI FD interrupt status register
- */
-typedef union {
-    struct {
-        /** rx_frm_suc_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status of TWAIFD_RX_FRM_SUC_INT.
-         */
-        uint32_t rx_frm_suc_int_st:1;
-        /** tx_frm_suc_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status of TWAIFD_TX_FRM_SUC_INT.
-         */
-        uint32_t tx_frm_suc_int_st:1;
-        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status of TWAIFD_ERR_WARNING_INT.
-         */
-        uint32_t err_warning_int_st:1;
-        /** rx_data_overrun_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status of TWAIFD_RX_DATA_OVERRUN_INT.
-         */
-        uint32_t rx_data_overrun_int_st:1;
-        uint32_t reserved_4:1;
-        /** fault_confinement_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT.
-         */
-        uint32_t fault_confinement_chg_int_st:1;
-        /** arb_lost_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status of TWAIFD_ARB_LOST_INT.
-         */
-        uint32_t arb_lost_int_st:1;
-        /** err_detected_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status of TWAIFD_ERR_DETECTED_INT.
-         */
-        uint32_t err_detected_int_st:1;
-        /** is_overload_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status of TWAIFD_IS_OVERLOAD_INT.
-         */
-        uint32_t is_overload_int_st:1;
-        /** rx_buf_full_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status of TWAIFD_RX_BUF_FULL_INT.
-         */
-        uint32_t rx_buf_full_int_st:1;
-        /** bit_rate_shift_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status of TWAIFD_BIT_RATE_SHIFT_INT.
-         */
-        uint32_t bit_rate_shift_int_st:1;
-        /** rx_buf_not_empty_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT.
-         */
-        uint32_t rx_buf_not_empty_int_st:1;
-        /** tx_buf_status_chg_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT.
-         */
-        uint32_t tx_buf_status_chg_int_st:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} twaifd_int_st_reg_t;
-
-/** Type of int_clr register
- *  TWAI FD interrupt clear register
- */
-typedef union {
-    struct {
-        /** rx_frm_suc_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear TWAIFD_RX_FRM_SUC_INT.
-         */
-        uint32_t rx_frm_suc_int_clr:1;
-        /** tx_frm_suc_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear TWAIFD_TX_FRM_SUC_INT.
-         */
-        uint32_t tx_frm_suc_int_clr:1;
-        /** err_warning_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear TWAIFD_ERR_WARNING_INT.
-         */
-        uint32_t err_warning_int_clr:1;
-        /** rx_data_overrun_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear TWAIFD_RX_DATA_OVERRUN_INT.
-         */
-        uint32_t rx_data_overrun_int_clr:1;
-        uint32_t reserved_4:1;
-        /** fault_confinement_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear TWAIFD_FAULT_CONFINEMENT_CHG_INT.
-         */
-        uint32_t fault_confinement_chg_int_clr:1;
-        /** arb_lost_int_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear TWAIFD_ARB_LOST_INT.
-         */
-        uint32_t arb_lost_int_clr:1;
-        /** err_detected_int_clr : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear TWAIFD_ERR_DETECTED_INT.
-         */
-        uint32_t err_detected_int_clr:1;
-        /** is_overload_int_clr : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear TWAIFD_IS_OVERLOAD_INT.
-         */
-        uint32_t is_overload_int_clr:1;
-        /** rx_buf_full_int_clr : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear TWAIFD_RX_BUF_FULL_INT.
-         */
-        uint32_t rx_buf_full_int_clr:1;
-        /** bit_rate_shift_int_clr : WT; bitpos: [10]; default: 0;
-         *  Write 1 to clear TWAIFD_BIT_RATE_SHIFT_INT.
-         */
-        uint32_t bit_rate_shift_int_clr:1;
-        /** rx_buf_not_empty_int_clr : WT; bitpos: [11]; default: 0;
-         *  Write 1 to clear TWAIFD_RX_BUF_NOT_EMPTY_INT.
-         */
-        uint32_t rx_buf_not_empty_int_clr:1;
-        /** tx_buf_status_chg_int_clr : WT; bitpos: [12]; default: 0;
-         *  Write 1 to clear TWAIFD_TX_BUF_STATUS_CHG_INT.
-         */
-        uint32_t tx_buf_status_chg_int_clr:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} twaifd_int_clr_reg_t;
-
-
-/** Group: error confinement register */
-/** Type of err_th_stat register
- *  TWAI FD error threshold and status register
- */
-typedef union {
-    struct {
-        /** err_warning_thres : R/W; bitpos: [7:0]; default: 96;
-         *  Configures the error warning threshold.\\
-         */
-        uint32_t err_warning_thres:8;
-        /** err_passive_thres : R/W; bitpos: [15:8]; default: 128;
-         *  Configures the error passive threshold.\\
-         */
-        uint32_t err_passive_thres:8;
-        /** err_active : RO; bitpos: [16]; default: 1;
-         *  Represents the fault state of error active.\\
-         */
-        uint32_t err_active:1;
-        /** err_passive : RO; bitpos: [17]; default: 0;
-         *  Represents the fault state of error passive.\\
-         */
-        uint32_t err_passive:1;
-        /** bus_off : RO; bitpos: [18]; default: 0;
-         *  Represents the fault state of bus off.\\
-         */
-        uint32_t bus_off:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} twaifd_err_th_stat_reg_t;
-
-/** Type of error_counters register
- *  TWAI FD error counters status register
- */
-typedef union {
-    struct {
-        /** rxc_val : RO; bitpos: [15:0]; default: 0;
-         *  Represents the receiver error counter value.\\
-         */
-        uint32_t rxc_val:16;
-        /** txc_val : RO; bitpos: [31:16]; default: 0;
-         *  Represents the transmitter error counter value.\\
-         */
-        uint32_t txc_val:16;
-    };
-    uint32_t val;
-} twaifd_error_counters_reg_t;
-
-/** Type of error_counters_sp register
- *  TWAI FD special error counters status register
- */
-typedef union {
-    struct {
-        /** err_fd_val : RO; bitpos: [15:0]; default: 0;
-         *  Represents the number of error in the data bit time.\\
-         */
-        uint32_t err_fd_val:16;
-        /** err_norm_val : RO; bitpos: [31:16]; default: 0;
-         *  Represents the number of error in the nominal bit time.\\
-         */
-        uint32_t err_norm_val:16;
-    };
-    uint32_t val;
-} twaifd_error_counters_sp_reg_t;
-
-/** Type of ctr_pres register
- *  TWAI FD error counters pre-define configuration register
- */
-typedef union {
-    struct {
-        /** ctr_pres_val : WO; bitpos: [8:0]; default: 0;
-         *  Configures the pre-defined value to set the error counter.\\
-         */
-        uint32_t ctr_pres_val:9;
-        /** ptx : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to set the receiver error counter into the value of
-         *  pre-defined value.\\
-         *  0: invalid\\
-         *  1: set\\
-         */
-        uint32_t ptx:1;
-        /** prx : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to set the transmitter error counter into the value of
-         *  pre-defined value.\\
-         *  0: invalid\\
-         *  1: set\\
-         */
-        uint32_t prx:1;
-        /** enorm : WO; bitpos: [11]; default: 0;
-         *  Configures whether or not to erase the error counter of nominal bit time.\\
-         *  0: invalid\\
-         *  1: erase\\
-         */
-        uint32_t enorm:1;
-        /** efd : WO; bitpos: [12]; default: 0;
-         *  Configures whether or not to erase the error counter of data bit time.\\
-         *  0: invalid\\
-         *  1: erase\\
-         */
-        uint32_t efd:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} twaifd_ctr_pres_reg_t;
-
-
-/** Group: receiver register */
-/** Type of rx_data register
- *  TWAI FD received data register
- */
-typedef union {
-    struct {
-        /** rx_data : RO; bitpos: [31:0]; default: 0;
-         *  Data received.
-         */
-        uint32_t rx_data:32;
-    };
-    uint32_t val;
-} twaifd_rx_data_reg_t;
-
-
-/** Group: filter register */
-/** Type of filter_a_mask register
- *  TWAI FD filter A mask value register
- */
-typedef union {
-    struct {
-        /** bit_mask_a : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit masked value.
-         */
-        uint32_t bit_mask_a:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_a_mask_reg_t;
-
-/** Type of filter_a_val register
- *  TWAI FD filter A bit value register
- */
-typedef union {
-    struct {
-        /** bit_val_a : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit value.
-         */
-        uint32_t bit_val_a:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_a_val_reg_t;
-
-/** Type of filter_b_mask register
- *  TWAI FD filter B mask value register
- */
-typedef union {
-    struct {
-        /** bit_mask_b : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit masked value.
-         */
-        uint32_t bit_mask_b:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_b_mask_reg_t;
-
-/** Type of filter_b_val register
- *  TWAI FD filter B bit value register
- */
-typedef union {
-    struct {
-        /** bit_val_b : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit value.
-         */
-        uint32_t bit_val_b:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_b_val_reg_t;
-
-/** Type of filter_c_mask register
- *  TWAI FD filter C mask value register
- */
-typedef union {
-    struct {
-        /** bit_mask_c : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit masked value.
-         */
-        uint32_t bit_mask_c:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_c_mask_reg_t;
-
-/** Type of filter_c_val register
- *  TWAI FD filter C bit value register
- */
-typedef union {
-    struct {
-        /** bit_val_c : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit value.
-         */
-        uint32_t bit_val_c:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_c_val_reg_t;
-
-/** Type of filter_ran_low register
- *  TWAI FD filter range low value register
- */
-typedef union {
-    struct {
-        /** bit_ran_low : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit masked value.
-         */
-        uint32_t bit_ran_low:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_ran_low_reg_t;
-
-/** Type of filter_ran_high register
- *  TWAI FD filter range high value register
- */
-typedef union {
-    struct {
-        /** bit_ran_high : R/W; bitpos: [28:0]; default: 0;
-         *  filter A bit value.
-         */
-        uint32_t bit_ran_high:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_filter_ran_high_reg_t;
-
-/** Type of filter_control register
- *  TWAI FD filter control register
- */
-typedef union {
-    struct {
-        /** fanb : R/W; bitpos: [0]; default: 1;
-         *  filter A with nominal and base mode.
-         */
-        uint32_t fanb:1;
-        /** fane : R/W; bitpos: [1]; default: 1;
-         *  filter A with nominal and extended mode.
-         */
-        uint32_t fane:1;
-        /** fafb : R/W; bitpos: [2]; default: 1;
-         *  filter A with FD and base mode.
-         */
-        uint32_t fafb:1;
-        /** fafe : R/W; bitpos: [3]; default: 1;
-         *  filter A with FD and extended mode.
-         */
-        uint32_t fafe:1;
-        /** fbnb : R/W; bitpos: [4]; default: 0;
-         *  filter B with nominal and base mode.
-         */
-        uint32_t fbnb:1;
-        /** fbne : R/W; bitpos: [5]; default: 0;
-         *  filter B with nominal and extended mode.
-         */
-        uint32_t fbne:1;
-        /** fbfb : R/W; bitpos: [6]; default: 0;
-         *  filter B with FD and base mode.
-         */
-        uint32_t fbfb:1;
-        /** fbfe : R/W; bitpos: [7]; default: 0;
-         *  filter B with FD and extended mode.
-         */
-        uint32_t fbfe:1;
-        /** fcnb : R/W; bitpos: [8]; default: 0;
-         *  filter C with nominal and base mode.
-         */
-        uint32_t fcnb:1;
-        /** fcne : R/W; bitpos: [9]; default: 0;
-         *  filter C with nominal and extended mode.
-         */
-        uint32_t fcne:1;
-        /** fcfb : R/W; bitpos: [10]; default: 0;
-         *  filter C with FD and base mode.
-         */
-        uint32_t fcfb:1;
-        /** fcfe : R/W; bitpos: [11]; default: 0;
-         *  filter C with FD and extended mode.
-         */
-        uint32_t fcfe:1;
-        /** frnb : R/W; bitpos: [12]; default: 0;
-         *  filter range with nominal and base mode.
-         */
-        uint32_t frnb:1;
-        /** frne : R/W; bitpos: [13]; default: 0;
-         *  filter range with nominal and extended mode.
-         */
-        uint32_t frne:1;
-        /** frfb : R/W; bitpos: [14]; default: 0;
-         *  filter range with FD and base mode.
-         */
-        uint32_t frfb:1;
-        /** frfe : R/W; bitpos: [15]; default: 0;
-         *  filter range with FD and extended mode.
-         */
-        uint32_t frfe:1;
-        /** sfa : RO; bitpos: [16]; default: 0;
-         *  filter A status
-         */
-        uint32_t sfa:1;
-        /** sfb : RO; bitpos: [17]; default: 0;
-         *  filter B status
-         */
-        uint32_t sfb:1;
-        /** sfc : RO; bitpos: [18]; default: 0;
-         *  filter C status
-         */
-        uint32_t sfc:1;
-        /** sfr : RO; bitpos: [19]; default: 0;
-         *  filter range status
-         */
-        uint32_t sfr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} twaifd_filter_control_reg_t;
-
-
-/** Group: transmitter register */
-/** Type of tx_data_0 register
- *  TWAI FD transmit data register 0
- */
-typedef union {
-    struct {
-        /** dlc_tx : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the brs to be transmitted.
-         */
-        uint32_t dlc_tx:4;
-        uint32_t reserved_4:1;
-        /** rtr_tx : R/W; bitpos: [5]; default: 0;
-         *  Configures the rtr bit to be transmitted.
-         */
-        uint32_t rtr_tx:1;
-        /** id_type_tx : R/W; bitpos: [6]; default: 0;
-         *  Configures the frame type to be transmitted.
-         */
-        uint32_t id_type_tx:1;
-        /** fr_type_tx : R/W; bitpos: [7]; default: 0;
-         *  Configures the fd type to be transmitted.
-         */
-        uint32_t fr_type_tx:1;
-        /** tbf_tx : R/W; bitpos: [8]; default: 0;
-         *  Configures the tbf bit to be transmitted.
-         */
-        uint32_t tbf_tx:1;
-        /** brs_tx : R/W; bitpos: [9]; default: 0;
-         *  Configures the brs bit to be transmitted.
-         */
-        uint32_t brs_tx:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} twaifd_tx_data_0_reg_t;
-
-/** Type of tx_data_1 register
- *  TWAI FD transmit data register 1
- */
-typedef union {
-    struct {
-        /** ts_val_u_tx : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the upper timestamp to be transmitted
-         */
-        uint32_t ts_val_u_tx:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_1_reg_t;
-
-/** Type of tx_data_2 register
- *  TWAI FD transmit data register 2
- */
-typedef union {
-    struct {
-        /** ts_val_l_tx : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the lower timestamp to be transmitted
-         */
-        uint32_t ts_val_l_tx:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_2_reg_t;
-
-/** Type of tx_data_3 register
- *  TWAI FD transmit data register 3
- */
-typedef union {
-    struct {
-        /** id_ext_tx : R/W; bitpos: [17:0]; default: 0;
-         *  Configures the base ID to be transmitted
-         */
-        uint32_t id_ext_tx:18;
-        /** id_base_tx : R/W; bitpos: [28:18]; default: 0;
-         *  Configures the extended ID to be transmitted
-         */
-        uint32_t id_base_tx:11;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} twaifd_tx_data_3_reg_t;
-
-/** Type of tx_data_4 register
- *  TWAI FD transmit data register 4
- */
-typedef union {
-    struct {
-        /** tx_data0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th word to be transmitted
-         */
-        uint32_t tx_data0:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_4_reg_t;
-
-/** Type of tx_data_5 register
- *  TWAI FD transmit data register 5
- */
-typedef union {
-    struct {
-        /** tx_data1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1th word to be transmitted
-         */
-        uint32_t tx_data1:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_5_reg_t;
-
-/** Type of tx_data_6 register
- *  TWAI FD transmit data register 6
- */
-typedef union {
-    struct {
-        /** tx_data2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2th word to be transmitted
-         */
-        uint32_t tx_data2:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_6_reg_t;
-
-/** Type of tx_data_7 register
- *  TWAI FD transmit data register 7
- */
-typedef union {
-    struct {
-        /** tx_data3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 3th word to be transmitted
-         */
-        uint32_t tx_data3:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_7_reg_t;
-
-/** Type of tx_data_8 register
- *  TWAI FD transmit data register 8
- */
-typedef union {
-    struct {
-        /** tx_data4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 4th word to be transmitted
-         */
-        uint32_t tx_data4:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_8_reg_t;
-
-/** Type of tx_data_9 register
- *  TWAI FD transmit data register 9
- */
-typedef union {
-    struct {
-        /** tx_data5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 5th word to be transmitted
-         */
-        uint32_t tx_data5:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_9_reg_t;
-
-/** Type of tx_data_10 register
- *  TWAI FD transmit data register 10
- */
-typedef union {
-    struct {
-        /** tx_data6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 6th word to be transmitted
-         */
-        uint32_t tx_data6:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_10_reg_t;
-
-/** Type of tx_data_11 register
- *  TWAI FD transmit data register 11
- */
-typedef union {
-    struct {
-        /** tx_data7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 7th word to be transmitted
-         */
-        uint32_t tx_data7:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_11_reg_t;
-
-/** Type of tx_data_12 register
- *  TWAI FD transmit data register 12
- */
-typedef union {
-    struct {
-        /** tx_data8 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 8th word to be transmitted
-         */
-        uint32_t tx_data8:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_12_reg_t;
-
-/** Type of tx_data_13 register
- *  TWAI FD transmit data register 13
- */
-typedef union {
-    struct {
-        /** tx_data9 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 9th word to be transmitted
-         */
-        uint32_t tx_data9:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_13_reg_t;
-
-/** Type of tx_data_14 register
- *  TWAI FD transmit data register 14
- */
-typedef union {
-    struct {
-        /** tx_data10 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 10th word to be transmitted
-         */
-        uint32_t tx_data10:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_14_reg_t;
-
-/** Type of tx_data_15 register
- *  TWAI FD transmit data register 15
- */
-typedef union {
-    struct {
-        /** tx_data11 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 11th word to be transmitted
-         */
-        uint32_t tx_data11:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_15_reg_t;
-
-/** Type of tx_data_16 register
- *  TWAI FD transmit data register 16
- */
-typedef union {
-    struct {
-        /** tx_data12 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 12th word to be transmitted
-         */
-        uint32_t tx_data12:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_16_reg_t;
-
-/** Type of tx_data_17 register
- *  TWAI FD transmit data register 17
- */
-typedef union {
-    struct {
-        /** tx_data13 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 13th word to be transmitted
-         */
-        uint32_t tx_data13:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_17_reg_t;
-
-/** Type of tx_data_18 register
- *  TWAI FD transmit data register 18
- */
-typedef union {
-    struct {
-        /** tx_data14 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 14th word to be transmitted
-         */
-        uint32_t tx_data14:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_18_reg_t;
-
-/** Type of tx_data_19 register
- *  TWAI FD transmit data register 19
- */
-typedef union {
-    struct {
-        /** tx_data15 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 15th word to be transmitted
-         */
-        uint32_t tx_data15:32;
-    };
-    uint32_t val;
-} twaifd_tx_data_19_reg_t;
-
-/** Type of tx_cammand_info register
- *  TWAI FD TXT buffer command & information register
- */
-typedef union {
-    struct {
-        /** txtb_sw_set_ety : R/W; bitpos: [0]; default: 0;
-         *  a\\
-         */
-        uint32_t txtb_sw_set_ety:1;
-        /** txtb_sw_set_rdy : R/W; bitpos: [1]; default: 0;
-         *  a\\
-         */
-        uint32_t txtb_sw_set_rdy:1;
-        /** txtb_sw_set_abt : R/W; bitpos: [2]; default: 0;
-         *  a\\
-         */
-        uint32_t txtb_sw_set_abt:1;
-        uint32_t reserved_3:5;
-        /** txb1 : R/W; bitpos: [8]; default: 0;
-         *  a\\
-         */
-        uint32_t txb1:1;
-        /** txb2 : R/W; bitpos: [9]; default: 0;
-         *  a\\
-         */
-        uint32_t txb2:1;
-        /** txb3 : R/W; bitpos: [10]; default: 0;
-         *  a\\
-         */
-        uint32_t txb3:1;
-        /** txb4 : R/W; bitpos: [11]; default: 0;
-         *  a\\
-         */
-        uint32_t txb4:1;
-        /** txb5 : R/W; bitpos: [12]; default: 0;
-         *  a\\
-         */
-        uint32_t txb5:1;
-        /** txb6 : R/W; bitpos: [13]; default: 0;
-         *  a\\
-         */
-        uint32_t txb6:1;
-        /** txb7 : R/W; bitpos: [14]; default: 0;
-         *  a\\
-         */
-        uint32_t txb7:1;
-        /** txb8 : R/W; bitpos: [15]; default: 0;
-         *  a\\
-         */
-        uint32_t txb8:1;
-        /** txt_buf_ctr : R/W; bitpos: [19:16]; default: 0;
-         *  a\\
-         */
-        uint32_t txt_buf_ctr:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} twaifd_tx_cammand_info_reg_t;
-
-
-/** Group: controller register */
-/** Type of rx_frm_counter register
- *  TWAI FD received frame counter register
- */
-typedef union {
-    struct {
-        /** rx_counter_val : RO; bitpos: [31:0]; default: 0;
-         *  Configures the received frame counters to enable bus traffic measurement.
-         */
-        uint32_t rx_counter_val:32;
-    };
-    uint32_t val;
-} twaifd_rx_frm_counter_reg_t;
-
-/** Type of tx_frm_counter register
- *  TWAI FD transmitted frame counter register
- */
-typedef union {
-    struct {
-        /** tx_counter_val : RO; bitpos: [31:0]; default: 0;
-         *  Configures the transcieved frame counters to enable bus traffic measurement.
-         */
-        uint32_t tx_counter_val:32;
-    };
-    uint32_t val;
-} twaifd_tx_frm_counter_reg_t;
-
-
-/** Group: clock register */
-/** Type of clk register
- *  TWAI FD clock configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} twaifd_clk_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  TWAI FD version register
- */
-typedef union {
-    struct {
-        /** twaifd_date : R/W; bitpos: [31:0]; default: 35717712;
-         *  This is the version register.
-         */
-        uint32_t twaifd_date:32;
-    };
-    uint32_t val;
-} twaifd_date_reg_t;
-
-
-typedef struct {
-    volatile twaifd_device_id_reg_t device_id;
-    volatile twaifd_mode_setting_reg_t mode_setting;
-    volatile twaifd_command_reg_t command;
-    volatile twaifd_status_reg_t status;
-    volatile twaifd_int_raw_reg_t int_raw;
-    volatile twaifd_int_ena_reg_t int_ena;
-    volatile twaifd_int_st_reg_t int_st;
-    volatile twaifd_int_clr_reg_t int_clr;
-    volatile twaifd_bit_timing_reg_t bit_timing;
-    volatile twaifd_bit_timeing_fd_reg_t bit_timeing_fd;
-    volatile twaifd_err_th_stat_reg_t err_th_stat;
-    volatile twaifd_error_counters_reg_t error_counters;
-    volatile twaifd_error_counters_sp_reg_t error_counters_sp;
-    volatile twaifd_ctr_pres_reg_t ctr_pres;
-    volatile twaifd_rx_mem_info_reg_t rx_mem_info;
-    volatile twaifd_rx_pointers_reg_t rx_pointers;
-    volatile twaifd_rx_status_setting_reg_t rx_status_setting;
-    volatile twaifd_rx_data_reg_t rx_data;
-    uint32_t reserved_048[6];
-    volatile twaifd_filter_a_mask_reg_t filter_a_mask;
-    volatile twaifd_filter_a_val_reg_t filter_a_val;
-    volatile twaifd_filter_b_mask_reg_t filter_b_mask;
-    volatile twaifd_filter_b_val_reg_t filter_b_val;
-    volatile twaifd_filter_c_mask_reg_t filter_c_mask;
-    volatile twaifd_filter_c_val_reg_t filter_c_val;
-    volatile twaifd_filter_ran_low_reg_t filter_ran_low;
-    volatile twaifd_filter_ran_high_reg_t filter_ran_high;
-    volatile twaifd_filter_control_reg_t filter_control;
-    uint32_t reserved_084[4];
-    volatile twaifd_tx_stat_reg_t tx_stat;
-    volatile twaifd_tx_cfg_reg_t tx_cfg;
-    volatile twaifd_tx_data_0_reg_t tx_data_0;
-    volatile twaifd_tx_data_1_reg_t tx_data_1;
-    volatile twaifd_tx_data_2_reg_t tx_data_2;
-    volatile twaifd_tx_data_3_reg_t tx_data_3;
-    volatile twaifd_tx_data_4_reg_t tx_data_4;
-    volatile twaifd_tx_data_5_reg_t tx_data_5;
-    volatile twaifd_tx_data_6_reg_t tx_data_6;
-    volatile twaifd_tx_data_7_reg_t tx_data_7;
-    volatile twaifd_tx_data_8_reg_t tx_data_8;
-    volatile twaifd_tx_data_9_reg_t tx_data_9;
-    volatile twaifd_tx_data_10_reg_t tx_data_10;
-    volatile twaifd_tx_data_11_reg_t tx_data_11;
-    volatile twaifd_tx_data_12_reg_t tx_data_12;
-    volatile twaifd_tx_data_13_reg_t tx_data_13;
-    volatile twaifd_tx_data_14_reg_t tx_data_14;
-    volatile twaifd_tx_data_15_reg_t tx_data_15;
-    volatile twaifd_tx_data_16_reg_t tx_data_16;
-    volatile twaifd_tx_data_17_reg_t tx_data_17;
-    volatile twaifd_tx_data_18_reg_t tx_data_18;
-    volatile twaifd_tx_data_19_reg_t tx_data_19;
-    uint32_t reserved_0ec[24];
-    volatile twaifd_tx_cammand_info_reg_t tx_cammand_info;
-    uint32_t reserved_150[4];
-    volatile twaifd_err_cap_retr_ctr_alc_reg_t err_cap_retr_ctr_alc;
-    volatile twaifd_trv_delay_ssp_cfg_reg_t trv_delay_ssp_cfg;
-    uint32_t reserved_168[6];
-    volatile twaifd_rx_frm_counter_reg_t rx_frm_counter;
-    volatile twaifd_tx_frm_counter_reg_t tx_frm_counter;
-    uint32_t reserved_188;
-    volatile twaifd_clk_reg_t clk;
-    volatile twaifd_date_reg_t date;
-} twaifd_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(twaifd_dev_t) == 0x194, "Invalid size of twaifd_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/uart_channel.h b/components/soc/esp32p4/include/soc/uart_channel.h
index 9d9fb454fd..c04136b38d 100644
--- a/components/soc/esp32p4/include/soc/uart_channel.h
+++ b/components/soc/esp32p4/include/soc/uart_channel.h
@@ -7,12 +7,3 @@
 // This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6.
 
 #pragma once
-
-//UART channels
-#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  16
-#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  17
-
-#define UART_TXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
-#define UART_RXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
diff --git a/components/soc/esp32p4/include/soc/uart_pins.h b/components/soc/esp32p4/include/soc/uart_pins.h
index 7164eeae56..a5d49ea6e7 100644
--- a/components/soc/esp32p4/include/soc/uart_pins.h
+++ b/components/soc/esp32p4/include/soc/uart_pins.h
@@ -10,27 +10,3 @@
 
 /* Specify the number of pins for UART */
 #define SOC_UART_PINS_COUNT  (4)
-
-/* Specify the GPIO pin number for each UART signal in the IOMUX */
-#define U0RXD_GPIO_NUM 17
-#define U0TXD_GPIO_NUM 16
-#define U0RTS_GPIO_NUM (-1)
-#define U0CTS_GPIO_NUM (-1)
-
-#define U1RXD_GPIO_NUM (-1)
-#define U1TXD_GPIO_NUM (-1)
-#define U1RTS_GPIO_NUM (-1)
-#define U1CTS_GPIO_NUM (-1)
-
-/* The following defines are necessary for reconfiguring the UART
- * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_GPIO37_UART0_TXD_PAD)
-#define U0RXD_MUX_FUNC  (FUNC_GPIO38_UART0_RXD_PAD)
-/* No func for the following pins, they shall not be used */
-#define U0RTS_MUX_FUNC  (-1)
-#define U0CTS_MUX_FUNC  (-1)
-/* Same goes for UART1 */
-#define U1TXD_MUX_FUNC  (-1)
-#define U1RXD_MUX_FUNC  (-1)
-#define U1RTS_MUX_FUNC  (-1)
-#define U1CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32p4/include/soc/usb_device_reg.h b/components/soc/esp32p4/include/soc/usb_device_reg.h
deleted file mode 100644
index 478c734ea8..0000000000
--- a/components/soc/esp32p4/include/soc/usb_device_reg.h
+++ /dev/null
@@ -1,1282 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0;
- *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
- *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
- *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
- *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
- *  received, then read data from UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
- *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
- *  Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- *  1'b1: Indicate there is data in UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  Interrupt raw status register.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when flush cmd is received for IN
- *  endpoint 2 of JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when SOF frame is received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- *  one packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when pid error is detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt bit turns to high level when CRC5 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt bit turns to high level when CRC16 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt bit turns to high level when stuff error is detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
- *  received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt bit turns to high level when usb bus reset is detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  Interrupt status register.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  Interrupt enable status register.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  Interrupt clear status register.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  PHY hardware configuration.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  Select internal/external PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- *  Enable software control USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- *  USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
- *  Control single-end input high threshold,1.76V to 2V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003U
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFH_S  3
-/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
- *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003U
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFL_S  5
-/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- *  Enable software control input  threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- *  Enable software control USB D+ D- pullup pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- *  Control USB D+ pull up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- *  Control USB D+ pull down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- *  Control USB D- pull up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- *  Control USB D- pull down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- *  Control pull up value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- *  Enable USB pad function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
- *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
- *  through GPIO Matrix.
- */
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  Registers used for debugging the PHY.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable test of the USB pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
- *  USB RCV value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
- *  USB D+ rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  JTAG FIFO status and control registers.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
- *  JTAT in fifo counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  1: JTAG in fifo is empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  1: JTAG in fifo is full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
- *  JTAT out fifo counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- *  1: JTAG out fifo is empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- *  1: JTAG out fifo is full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- *  Write 1 to reset JTAG in fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- *  Write 1 to reset JTAG out fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  Last received SOF frame index register.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
- *  Frame index of received SOF frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  Control IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  CDC-ACM IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  JTAG IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  Control OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  CDC-ACM OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
- *  Data count in OUT endpoint 1 when one packet is received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  JTAG OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  Clock enable control
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  Memory power control
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  1: power down usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  1: Force clock on for usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-/** USB_SERIAL_JTAG_CHIP_RST_REG register
- *  CDC-ACM chip reset control.
- */
-#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
-/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
- *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_RTS    (BIT(0))
-#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
-#define USB_SERIAL_JTAG_RTS_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_S  0
-/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
- *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_DTR    (BIT(1))
-#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
-#define USB_SERIAL_JTAG_DTR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_S  1
-/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable chip reset from usb serial channel to reset chip.
- */
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
- *  W0 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
-/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
- *  W1 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
-/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
-/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_S  16
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
- *  W0 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
-/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
- *  W1 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
-/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
-/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
-
-/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
- *  Configuration registers' value update
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
-/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
- *  Write 1 to this register would update the value of configure registers from APB
- *  clock domain to 48MHz clock domain.
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
-
-/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
- *  Serial AFIFO configure register
- */
-#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
- *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
-
-/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
- *  USB Bus reset status register
- */
-#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
-/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
- *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
- *  reset is released.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
-
-/** USB_SERIAL_JTAG_ECO_LOW_48_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
-/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M  (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S)
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S  0
-
-/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
-/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S)
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S  0
-
-/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74)
-/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_RESULT_48    (BIT(0))
-#define USB_SERIAL_JTAG_RDN_RESULT_48_M  (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S)
-#define USB_SERIAL_JTAG_RDN_RESULT_48_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_RESULT_48_S  0
-/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_ENA_48    (BIT(1))
-#define USB_SERIAL_JTAG_RDN_ENA_48_M  (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S)
-#define USB_SERIAL_JTAG_RDN_ENA_48_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_ENA_48_S  1
-
-/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78)
-/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M  (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S)
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S  0
-
-/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c)
-/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S)
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S  0
-
-/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_RESULT_APB    (BIT(0))
-#define USB_SERIAL_JTAG_RDN_RESULT_APB_M  (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S)
-#define USB_SERIAL_JTAG_RDN_RESULT_APB_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_RESULT_APB_S  0
-/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_ENA_APB    (BIT(1))
-#define USB_SERIAL_JTAG_RDN_ENA_APB_M  (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S)
-#define USB_SERIAL_JTAG_RDN_ENA_APB_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_ENA_APB_S  1
-
-/** USB_SERIAL_JTAG_SRAM_CTRL_REG register
- *  PPA SRAM Control Register
- */
-#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84)
-/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
- *  Control signals
- */
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL    0x00003FFFU
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M  (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S)
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V  0x00003FFFU
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S  0
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  Date register
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88)
-/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752;
- *  register version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/usb_device_struct.h b/components/soc/esp32p4/include/soc/usb_device_struct.h
deleted file mode 100644
index ed400ae548..0000000000
--- a/components/soc/esp32p4/include/soc/usb_device_struct.h
+++ /dev/null
@@ -1,1044 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of ep1 register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-typedef union {
-    struct {
-        /** rdwr_byte : RO; bitpos: [7:0]; default: 0;
-         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
-         *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
-         *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
-         *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
-         *  received, then read data from UART Rx FIFO.
-         */
-        uint32_t rdwr_byte:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} usb_serial_jtag_ep1_reg_t;
-
-/** Type of ep1_conf register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-typedef union {
-    struct {
-        /** wr_done : WT; bitpos: [0]; default: 0;
-         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
-         */
-        uint32_t wr_done:1;
-        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
-         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
-         *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
-         *  Host.
-         */
-        uint32_t serial_in_ep_data_free:1;
-        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
-         *  1'b1: Indicate there is data in UART Rx FIFO.
-         */
-        uint32_t serial_out_ep_data_avail:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} usb_serial_jtag_ep1_conf_reg_t;
-
-/** Type of conf0 register
- *  PHY hardware configuration.
- */
-typedef union {
-    struct {
-        /** phy_sel : R/W; bitpos: [0]; default: 0;
-         *  Select internal/external PHY
-         */
-        uint32_t phy_sel:1;
-        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
-         *  Enable software control USB D+ D- exchange
-         */
-        uint32_t exchg_pins_override:1;
-        /** exchg_pins : R/W; bitpos: [2]; default: 0;
-         *  USB D+ D- exchange
-         */
-        uint32_t exchg_pins:1;
-        /** vrefh : R/W; bitpos: [4:3]; default: 0;
-         *  Control single-end input high threshold,1.76V to 2V, step 80mV
-         */
-        uint32_t vrefh:2;
-        /** vrefl : R/W; bitpos: [6:5]; default: 0;
-         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
-         */
-        uint32_t vrefl:2;
-        /** vref_override : R/W; bitpos: [7]; default: 0;
-         *  Enable software control input  threshold
-         */
-        uint32_t vref_override:1;
-        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
-         *  Enable software control USB D+ D- pullup pulldown
-         */
-        uint32_t pad_pull_override:1;
-        /** dp_pullup : R/W; bitpos: [9]; default: 1;
-         *  Control USB D+ pull up.
-         */
-        uint32_t dp_pullup:1;
-        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
-         *  Control USB D+ pull down.
-         */
-        uint32_t dp_pulldown:1;
-        /** dm_pullup : R/W; bitpos: [11]; default: 0;
-         *  Control USB D- pull up.
-         */
-        uint32_t dm_pullup:1;
-        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
-         *  Control USB D- pull down.
-         */
-        uint32_t dm_pulldown:1;
-        /** pullup_value : R/W; bitpos: [13]; default: 0;
-         *  Control pull up value.
-         */
-        uint32_t pullup_value:1;
-        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
-         *  Enable USB pad function.
-         */
-        uint32_t usb_pad_enable:1;
-        /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
-         *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
-         *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
-         *  through GPIO Matrix.
-         */
-        uint32_t usb_jtag_bridge_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_conf0_reg_t;
-
-/** Type of test register
- *  Registers used for debugging the PHY.
- */
-typedef union {
-    struct {
-        /** test_enable : R/W; bitpos: [0]; default: 0;
-         *  Enable test of the USB pad
-         */
-        uint32_t test_enable:1;
-        /** test_usb_oe : R/W; bitpos: [1]; default: 0;
-         *  USB pad oen in test
-         */
-        uint32_t test_usb_oe:1;
-        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
-         *  USB D+ tx value in test
-         */
-        uint32_t test_tx_dp:1;
-        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
-         *  USB D- tx value in test
-         */
-        uint32_t test_tx_dm:1;
-        /** test_rx_rcv : RO; bitpos: [4]; default: 1;
-         *  USB RCV value in test
-         */
-        uint32_t test_rx_rcv:1;
-        /** test_rx_dp : RO; bitpos: [5]; default: 1;
-         *  USB D+ rx value in test
-         */
-        uint32_t test_rx_dp:1;
-        /** test_rx_dm : RO; bitpos: [6]; default: 0;
-         *  USB D- rx value in test
-         */
-        uint32_t test_rx_dm:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} usb_serial_jtag_test_reg_t;
-
-/** Type of misc_conf register
- *  Clock enable control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_misc_conf_reg_t;
-
-/** Type of mem_conf register
- *  Memory power control
- */
-typedef union {
-    struct {
-        /** usb_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  1: power down usb memory.
-         */
-        uint32_t usb_mem_pd:1;
-        /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
-         *  1: Force clock on for usb memory.
-         */
-        uint32_t usb_mem_clk_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_serial_jtag_mem_conf_reg_t;
-
-/** Type of chip_rst register
- *  CDC-ACM chip reset control.
- */
-typedef union {
-    struct {
-        /** rts : RO; bitpos: [0]; default: 0;
-         *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
-         */
-        uint32_t rts:1;
-        /** dtr : RO; bitpos: [1]; default: 0;
-         *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
-         */
-        uint32_t dtr:1;
-        /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to disable chip reset from usb serial channel to reset chip.
-         */
-        uint32_t usb_uart_chip_rst_dis:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} usb_serial_jtag_chip_rst_reg_t;
-
-/** Type of get_line_code_w0 register
- *  W0 of GET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
-         *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_dw_dte_rate:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_get_line_code_w0_reg_t;
-
-/** Type of get_line_code_w1 register
- *  W1 of GET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
-         *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bdata_bits:8;
-        /** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
-         *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bparity_type:8;
-        /** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
-         *  The value of bDataBits set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bchar_format:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} usb_serial_jtag_get_line_code_w1_reg_t;
-
-/** Type of config_update register
- *  Configuration registers' value update
- */
-typedef union {
-    struct {
-        /** config_update : WT; bitpos: [0]; default: 0;
-         *  Write 1 to this register would update the value of configure registers from APB
-         *  clock domain to 48MHz clock domain.
-         */
-        uint32_t config_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_config_update_reg_t;
-
-/** Type of ser_afifo_config register
- *  Serial AFIFO configure register
- */
-typedef union {
-    struct {
-        /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
-         */
-        uint32_t serial_in_afifo_reset_wr:1;
-        /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
-         */
-        uint32_t serial_in_afifo_reset_rd:1;
-        /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
-         */
-        uint32_t serial_out_afifo_reset_wr:1;
-        /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
-         */
-        uint32_t serial_out_afifo_reset_rd:1;
-        /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
-         *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
-         */
-        uint32_t serial_out_afifo_rempty:1;
-        /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
-         *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
-         */
-        uint32_t serial_in_afifo_wfull:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} usb_serial_jtag_ser_afifo_config_reg_t;
-
-/** Type of eco_low_48 register
- *  Reserved.
- */
-typedef union {
-    struct {
-        /** rnd_eco_low_48 : R/W; bitpos: [31:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rnd_eco_low_48:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_eco_low_48_reg_t;
-
-/** Type of eco_high_48 register
- *  Reserved.
- */
-typedef union {
-    struct {
-        /** rnd_eco_high_48 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Reserved.
-         */
-        uint32_t rnd_eco_high_48:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_eco_high_48_reg_t;
-
-/** Type of eco_low_apb register
- *  Reserved.
- */
-typedef union {
-    struct {
-        /** rnd_eco_low_apb : R/W; bitpos: [31:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rnd_eco_low_apb:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_eco_low_apb_reg_t;
-
-/** Type of eco_high_apb register
- *  Reserved.
- */
-typedef union {
-    struct {
-        /** rnd_eco_high_apb : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Reserved.
-         */
-        uint32_t rnd_eco_high_apb:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_eco_high_apb_reg_t;
-
-/** Type of sram_ctrl register
- *  PPA SRAM Control Register
- */
-typedef union {
-    struct {
-        /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
-         *  Control signals
-         */
-        uint32_t mem_aux_ctrl:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} usb_serial_jtag_sram_ctrl_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_raw register
- *  Interrupt raw status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when flush cmd is received for IN
-         *  endpoint 2 of JTAG.
-         */
-        uint32_t jtag_in_flush_int_raw:1;
-        /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when SOF frame is received.
-         */
-        uint32_t sof_int_raw:1;
-        /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
-         *  one packet.
-         */
-        uint32_t serial_out_recv_pkt_int_raw:1;
-        /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
-         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
-         */
-        uint32_t serial_in_empty_int_raw:1;
-        /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when pid error is detected.
-         */
-        uint32_t pid_err_int_raw:1;
-        /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when CRC5 error is detected.
-         */
-        uint32_t crc5_err_int_raw:1;
-        /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when CRC16 error is detected.
-         */
-        uint32_t crc16_err_int_raw:1;
-        /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when stuff error is detected.
-         */
-        uint32_t stuff_err_int_raw:1;
-        /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
-         *  received.
-         */
-        uint32_t in_token_rec_in_ep1_int_raw:1;
-        /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when usb bus reset is detected.
-         */
-        uint32_t usb_bus_reset_int_raw:1;
-        /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
-         *  zero palyload.
-         */
-        uint32_t out_ep1_zero_payload_int_raw:1;
-        /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
-         *  zero palyload.
-         */
-        uint32_t out_ep2_zero_payload_int_raw:1;
-        /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
-         *  is changed.
-         */
-        uint32_t rts_chg_int_raw:1;
-        /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
-         *  is changed.
-         */
-        uint32_t dtr_chg_int_raw:1;
-        /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
-         *  received.
-         */
-        uint32_t get_line_code_int_raw:1;
-        /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
-         *  received.
-         */
-        uint32_t set_line_code_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_raw_reg_t;
-
-/** Type of int_st register
- *  Interrupt status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_st:1;
-        /** sof_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
-         */
-        uint32_t sof_int_st:1;
-        /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_st:1;
-        /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_st:1;
-        /** pid_err_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_st:1;
-        /** crc5_err_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_st:1;
-        /** crc16_err_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_st:1;
-        /** stuff_err_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_st:1;
-        /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_st:1;
-        /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_st:1;
-        /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_st:1;
-        /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_st:1;
-        /** rts_chg_int_st : RO; bitpos: [12]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_st:1;
-        /** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_st:1;
-        /** get_line_code_int_st : RO; bitpos: [14]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_st:1;
-        /** set_line_code_int_st : RO; bitpos: [15]; default: 0;
-         *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_ena:1;
-        /** sof_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
-         */
-        uint32_t sof_int_ena:1;
-        /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_ena:1;
-        /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_ena:1;
-        /** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_ena:1;
-        /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_ena:1;
-        /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_ena:1;
-        /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_ena:1;
-        /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_ena:1;
-        /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_ena:1;
-        /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_ena:1;
-        /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_ena:1;
-        /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_ena:1;
-        /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_ena:1;
-        /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_ena:1;
-        /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_clr:1;
-        /** sof_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
-         */
-        uint32_t sof_int_clr:1;
-        /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_clr:1;
-        /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_clr:1;
-        /** pid_err_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_clr:1;
-        /** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_clr:1;
-        /** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_clr:1;
-        /** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_clr:1;
-        /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_clr:1;
-        /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_clr:1;
-        /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_clr:1;
-        /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_clr:1;
-        /** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_clr:1;
-        /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_clr:1;
-        /** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_clr:1;
-        /** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_clr_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of jfifo_st register
- *  JTAG FIFO status and control registers.
- */
-typedef union {
-    struct {
-        /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
-         *  JTAT in fifo counter.
-         */
-        uint32_t in_fifo_cnt:2;
-        /** in_fifo_empty : RO; bitpos: [2]; default: 1;
-         *  1: JTAG in fifo is empty.
-         */
-        uint32_t in_fifo_empty:1;
-        /** in_fifo_full : RO; bitpos: [3]; default: 0;
-         *  1: JTAG in fifo is full.
-         */
-        uint32_t in_fifo_full:1;
-        /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
-         *  JTAT out fifo counter.
-         */
-        uint32_t out_fifo_cnt:2;
-        /** out_fifo_empty : RO; bitpos: [6]; default: 1;
-         *  1: JTAG out fifo is empty.
-         */
-        uint32_t out_fifo_empty:1;
-        /** out_fifo_full : RO; bitpos: [7]; default: 0;
-         *  1: JTAG out fifo is full.
-         */
-        uint32_t out_fifo_full:1;
-        /** in_fifo_reset : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to reset JTAG in fifo.
-         */
-        uint32_t in_fifo_reset:1;
-        /** out_fifo_reset : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to reset JTAG out fifo.
-         */
-        uint32_t out_fifo_reset:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} usb_serial_jtag_jfifo_st_reg_t;
-
-/** Type of fram_num register
- *  Last received SOF frame index register.
- */
-typedef union {
-    struct {
-        /** sof_frame_index : RO; bitpos: [10:0]; default: 0;
-         *  Frame index of received SOF frame.
-         */
-        uint32_t sof_frame_index:11;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} usb_serial_jtag_fram_num_reg_t;
-
-/** Type of in_ep0_st register
- *  Control IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep0_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 0.
-         */
-        uint32_t in_ep0_state:2;
-        /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 0.
-         */
-        uint32_t in_ep0_wr_addr:7;
-        /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 0.
-         */
-        uint32_t in_ep0_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep0_st_reg_t;
-
-/** Type of in_ep1_st register
- *  CDC-ACM IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep1_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 1.
-         */
-        uint32_t in_ep1_state:2;
-        /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 1.
-         */
-        uint32_t in_ep1_wr_addr:7;
-        /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 1.
-         */
-        uint32_t in_ep1_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep1_st_reg_t;
-
-/** Type of in_ep2_st register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep2_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 2.
-         */
-        uint32_t in_ep2_state:2;
-        /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 2.
-         */
-        uint32_t in_ep2_wr_addr:7;
-        /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 2.
-         */
-        uint32_t in_ep2_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep2_st_reg_t;
-
-/** Type of in_ep3_st register
- *  JTAG IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep3_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 3.
-         */
-        uint32_t in_ep3_state:2;
-        /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 3.
-         */
-        uint32_t in_ep3_wr_addr:7;
-        /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 3.
-         */
-        uint32_t in_ep3_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep3_st_reg_t;
-
-/** Type of out_ep0_st register
- *  Control OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep0_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 0.
-         */
-        uint32_t out_ep0_state:2;
-        /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-         *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
-         */
-        uint32_t out_ep0_wr_addr:7;
-        /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 0.
-         */
-        uint32_t out_ep0_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep0_st_reg_t;
-
-/** Type of out_ep1_st register
- *  CDC-ACM OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep1_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 1.
-         */
-        uint32_t out_ep1_state:2;
-        /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-         *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
-         */
-        uint32_t out_ep1_wr_addr:7;
-        /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 1.
-         */
-        uint32_t out_ep1_rd_addr:7;
-        /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
-         *  Data count in OUT endpoint 1 when one packet is received.
-         */
-        uint32_t out_ep1_rec_data_cnt:7;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep1_st_reg_t;
-
-/** Type of out_ep2_st register
- *  JTAG OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep2_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 2.
-         */
-        uint32_t out_ep2_state:2;
-        /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-         *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
-         */
-        uint32_t out_ep2_wr_addr:7;
-        /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 2.
-         */
-        uint32_t out_ep2_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep2_st_reg_t;
-
-/** Type of set_line_code_w0 register
- *  W0 of SET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
-         *  The value of dwDTERate set by host through SET_LINE_CODING command.
-         */
-        uint32_t dw_dte_rate:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_set_line_code_w0_reg_t;
-
-/** Type of set_line_code_w1 register
- *  W1 of SET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** bchar_format : RO; bitpos: [7:0]; default: 0;
-         *  The value of bCharFormat set by host through SET_LINE_CODING command.
-         */
-        uint32_t bchar_format:8;
-        /** bparity_type : RO; bitpos: [15:8]; default: 0;
-         *  The value of bParityTpye set by host through SET_LINE_CODING command.
-         */
-        uint32_t bparity_type:8;
-        /** bdata_bits : RO; bitpos: [23:16]; default: 0;
-         *  The value of bDataBits set by host through SET_LINE_CODING command.
-         */
-        uint32_t bdata_bits:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} usb_serial_jtag_set_line_code_w1_reg_t;
-
-/** Type of bus_reset_st register
- *  USB Bus reset status register
- */
-typedef union {
-    struct {
-        /** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
-         *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
-         *  reset is released.
-         */
-        uint32_t usb_bus_reset_st:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_bus_reset_st_reg_t;
-
-/** Type of eco_cell_ctrl_48 register
- *  Reserved.
- */
-typedef union {
-    struct {
-        /** rdn_result_48 : RO; bitpos: [0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rdn_result_48:1;
-        /** rdn_ena_48 : R/W; bitpos: [1]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rdn_ena_48:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_serial_jtag_eco_cell_ctrl_48_reg_t;
-
-/** Type of eco_cell_ctrl_apb register
- *  Reserved.
- */
-typedef union {
-    struct {
-        /** rdn_result_apb : RO; bitpos: [0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rdn_result_apb:1;
-        /** rdn_ena_apb : R/W; bitpos: [1]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rdn_ena_apb:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_serial_jtag_eco_cell_ctrl_apb_reg_t;
-
-
-/** Group: Version Registers */
-/** Type of date register
- *  Date register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 34676752;
-         *  register version.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_date_reg_t;
-
-
-typedef struct {
-    volatile usb_serial_jtag_ep1_reg_t ep1;
-    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
-    volatile usb_serial_jtag_int_raw_reg_t int_raw;
-    volatile usb_serial_jtag_int_st_reg_t int_st;
-    volatile usb_serial_jtag_int_ena_reg_t int_ena;
-    volatile usb_serial_jtag_int_clr_reg_t int_clr;
-    volatile usb_serial_jtag_conf0_reg_t conf0;
-    volatile usb_serial_jtag_test_reg_t test;
-    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
-    volatile usb_serial_jtag_fram_num_reg_t fram_num;
-    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
-    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
-    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
-    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
-    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
-    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
-    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
-    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
-    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
-    volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
-    volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
-    volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
-    volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
-    volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
-    volatile usb_serial_jtag_config_update_reg_t config_update;
-    volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
-    volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
-    volatile usb_serial_jtag_eco_low_48_reg_t eco_low_48;
-    volatile usb_serial_jtag_eco_high_48_reg_t eco_high_48;
-    volatile usb_serial_jtag_eco_cell_ctrl_48_reg_t eco_cell_ctrl_48;
-    volatile usb_serial_jtag_eco_low_apb_reg_t eco_low_apb;
-    volatile usb_serial_jtag_eco_high_apb_reg_t eco_high_apb;
-    volatile usb_serial_jtag_eco_cell_ctrl_apb_reg_t eco_cell_ctrl_apb;
-    volatile usb_serial_jtag_sram_ctrl_reg_t sram_ctrl;
-    volatile usb_serial_jtag_date_reg_t date;
-} usb_serial_jtag_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
index 64aaa0c3e6..0f3e87e1e5 100644
--- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld
+++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
@@ -27,12 +27,11 @@ PROVIDE ( I2S1              = 0x500C7000 );
 PROVIDE ( I2S2              = 0x500C8000 );
 PROVIDE ( TWAI1             = 0x500D8000 );
 PROVIDE ( TWAI2             = 0x500D9000 );
-PROVIDE ( APB_SARADC        = 0x6000E000 ); /* need remove */
+PROVIDE ( ADC               = 0x500DE000 );
 PROVIDE ( USB_SERIAL_JTAG   = 0x500D2000 );
 PROVIDE ( SDMMC             = 0x50083000 );
 
 PROVIDE ( INTMTX        = 0x500D6000 );
-PROVIDE ( ATOMIC_LOCKER = 0x60011000 ); /* need remove */
 PROVIDE ( PCNT          = 0x500C9000 );
 PROVIDE ( SOC_ETM       = 0x500D5000 );
 PROVIDE ( MCPWM0        = 0x500C0000 );
@@ -42,6 +41,7 @@ PROVIDE ( PVT_MONITOR   = 0x5009E000 );
 
 PROVIDE ( GDMA      = 0x50081000 );
 PROVIDE ( GPSPI2    = 0x500D0000 );
+PROVIDE ( GPSPI3    = 0x500D1000 );
 
 PROVIDE ( AES       = 0x50090000 );
 PROVIDE ( SHA       = 0x50091000 );
@@ -51,14 +51,13 @@ PROVIDE ( DS        = 0x50094000 );
 PROVIDE ( HMAC      = 0x50095000 );
 PROVIDE ( ECDSA     = 0x50096000 );
 
-PROVIDE ( IO_MUX         = 0x500e1000 );
 PROVIDE ( IOMUX          = 0x500e1000 );
 PROVIDE ( GPIO           = 0x500E0000 );
 PROVIDE ( SIGMADELTA     = 0x500E0F00 );
 
 PROVIDE ( HP_SYSTEM         = 0x500E5000 );
-PROVIDE ( TEE               = 0x60098000 ); /* need update */
-PROVIDE ( HP_APM            = 0x60099000 ); /* need update */
+PROVIDE ( TEE               = 0x60098000 ); /* TODO: IDF-7542 */
+PROVIDE ( HP_APM            = 0x60099000 ); /* TODO: IDF-7542 */
 
 PROVIDE ( PMU           = 0x50115000 );
 PROVIDE ( LP_AON_CLKRST = 0x50111000 );
@@ -66,12 +65,13 @@ PROVIDE ( EFUSE         = 0x5012D000 );
 PROVIDE ( LP_TIMER      = 0x50112000 );
 PROVIDE ( LP_UART       = 0x50121000 );
 PROVIDE ( LP_I2C        = 0x50122000 );
+PROVIDE ( LP_SPI        = 0x50123000 );
 PROVIDE ( LP_WDT        = 0x50116000 );
 PROVIDE ( LP_I2S        = 0x50125000 );
 PROVIDE ( LP_GPIO         = 0x5012A000 );
 PROVIDE ( LP_I2C_ANA_MST = 0x50124000 );
 PROVIDE ( LP_ANA_PERI   = 0x50113000 );
-PROVIDE ( LP_APM        = 0x600B3800 ); /* need update */
+PROVIDE ( LP_APM        = 0x600B3800 ); /* TODO: IDF-7542 */
 PROVIDE ( AHB_DMA      =  0x50085000 );
 PROVIDE ( AXI_DMA      =  0x5008a000 );
 PROVIDE ( LCD_CAM      = 0x500dc000 );
diff --git a/components/soc/esp32p4/ledc_periph.c b/components/soc/esp32p4/ledc_periph.c
index 18e9d9a68d..867ad4bfd6 100644
--- a/components/soc/esp32p4/ledc_periph.c
+++ b/components/soc/esp32p4/ledc_periph.c
@@ -11,7 +11,5 @@
  Bunch of constants for every LEDC peripheral: GPIO signals
 */
 const ledc_signal_conn_t ledc_periph_signal[1] = {
-	{
-        .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
-	}
+
 };
diff --git a/components/soc/esp32p4/mcpwm_periph.c b/components/soc/esp32p4/mcpwm_periph.c
index 6de1cfa631..fea03e5a8d 100644
--- a/components/soc/esp32p4/mcpwm_periph.c
+++ b/components/soc/esp32p4/mcpwm_periph.c
@@ -9,75 +9,5 @@
 #include "soc/gpio_sig_map.h"
 
 const mcpwm_signal_conn_t mcpwm_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_MCPWM0_MODULE,
-            .irq_id = ETS_PWM0_INTR_SOURCE,
-            .operators = {
-                [0] = {
-                    .generators = {
-                        [0] = {
-                            .pwm_sig = 0
-                        },
-                        [1] = {
-                            .pwm_sig = 0
-                        }
-                    }
-                },
-                [1] = {
-                    .generators = {
-                        [0] = {
-                            .pwm_sig = 0
-                        },
-                        [1] = {
-                            .pwm_sig = 0
-                        }
-                    }
-                },
-                [2] = {
-                    .generators = {
-                        [0] = {
-                            .pwm_sig = 0
-                        },
-                        [1] = {
-                            .pwm_sig = 0
-                        }
-                    }
-                }
-            },
-            .gpio_faults = {
-                [0] = {
-                    .fault_sig = 0
-                },
-                [1] = {
-                    .fault_sig = 0
-                },
-                [2] = {
-                    .fault_sig = 0
-                }
-            },
-            .captures = {
-                [0] = {
-                    .cap_sig = 0
-                },
-                [1] = {
-                    .cap_sig = 0
-                },
-                [2] = {
-                    .cap_sig = 0
-                }
-            },
-            .gpio_synchros = {
-                [0] = {
-                    .sync_sig = 0
-                },
-                [1] = {
-                    .sync_sig = 0
-                },
-                [2] = {
-                    .sync_sig = 0
-                }
-            }
-        },
-    }
+
 };
diff --git a/components/soc/esp32p4/parlio_periph.c b/components/soc/esp32p4/parlio_periph.c
index 40ac06320c..827c614415 100644
--- a/components/soc/esp32p4/parlio_periph.c
+++ b/components/soc/esp32p4/parlio_periph.c
@@ -8,59 +8,5 @@
 #include "soc/gpio_sig_map.h"
 
 const parlio_signal_conn_t parlio_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_PARLIO_MODULE,
-            .tx_irq_id = ETS_PARL_IO_INTR_SOURCE,
-            .rx_irq_id = ETS_PARL_IO_INTR_SOURCE,
-            .tx_units = {
-                [0] = {
-                    .data_sigs = {
-                        PARL_TX_DATA0_IDX,
-                        PARL_TX_DATA1_IDX,
-                        PARL_TX_DATA2_IDX,
-                        PARL_TX_DATA3_IDX,
-                        PARL_TX_DATA4_IDX,
-                        PARL_TX_DATA5_IDX,
-                        PARL_TX_DATA6_IDX,
-                        PARL_TX_DATA7_IDX,
-                        PARL_TX_DATA8_IDX,
-                        PARL_TX_DATA9_IDX,
-                        PARL_TX_DATA10_IDX,
-                        PARL_TX_DATA11_IDX,
-                        PARL_TX_DATA12_IDX,
-                        PARL_TX_DATA13_IDX,
-                        PARL_TX_DATA14_IDX,
-                        PARL_TX_DATA15_IDX,
-                    },
-                    .clk_out_sig = PARL_TX_CLK_OUT_IDX,
-                    .clk_in_sig = PARL_TX_CLK_IN_IDX,
-                }
-            },
-            .rx_units = {
-                [0] = {
-                    .data_sigs = {
-                        PARL_RX_DATA0_IDX,
-                        PARL_RX_DATA1_IDX,
-                        PARL_RX_DATA2_IDX,
-                        PARL_RX_DATA3_IDX,
-                        PARL_RX_DATA4_IDX,
-                        PARL_RX_DATA5_IDX,
-                        PARL_RX_DATA6_IDX,
-                        PARL_RX_DATA7_IDX,
-                        PARL_RX_DATA8_IDX,
-                        PARL_RX_DATA9_IDX,
-                        PARL_RX_DATA10_IDX,
-                        PARL_RX_DATA11_IDX,
-                        PARL_RX_DATA12_IDX,
-                        PARL_RX_DATA13_IDX,
-                        PARL_RX_DATA14_IDX,
-                        PARL_RX_DATA15_IDX,
-                    },
-                    .clk_out_sig = -1,
-                    .clk_in_sig = PARL_RX_CLK_IN_IDX,
-                }
-            }
-        },
-    },
+
 };
diff --git a/components/soc/esp32p4/pcnt_periph.c b/components/soc/esp32p4/pcnt_periph.c
index a3b2adaee2..ca289c2e28 100644
--- a/components/soc/esp32p4/pcnt_periph.c
+++ b/components/soc/esp32p4/pcnt_periph.c
@@ -8,60 +8,5 @@
 #include "soc/gpio_sig_map.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_PCNT_MODULE,
-            .irq = ETS_PCNT_INTR_SOURCE,
-            .units = {
-                [0] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        },
-                        [1] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        }
-                    }
-                },
-                [1] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        },
-                        [1] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        }
-                    }
-                },
-                [2] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        },
-                        [1] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        }
-                    }
-                },
-                [3] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        },
-                        [1] = {
-                            .control_sig = 0,
-                            .pulse_sig = 0
-                        }
-                    }
-                }
-            }
-        }
-    }
+
 };
diff --git a/components/soc/esp32p4/rmt_periph.c b/components/soc/esp32p4/rmt_periph.c
index 06ed9e3b74..650b4ddcf1 100644
--- a/components/soc/esp32p4/rmt_periph.c
+++ b/components/soc/esp32p4/rmt_periph.c
@@ -8,28 +8,5 @@
 #include "soc/gpio_sig_map.h"
 
 const rmt_signal_conn_t rmt_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_RMT_MODULE,
-            .irq = ETS_RMT_INTR_SOURCE,
-            .channels = {
-                [0] = {
-                    .tx_sig = RMT_SIG_PAD_OUT0_IDX,
-                    .rx_sig = -1
-                },
-                [1] = {
-                    .tx_sig = RMT_SIG_PAD_OUT1_IDX,
-                    .rx_sig = -1
-                },
-                [2] = {
-                    .tx_sig = -1,
-                    .rx_sig = RMT_SIG_PAD_IN0_IDX
-                },
-                [3] = {
-                    .tx_sig = -1,
-                    .rx_sig = RMT_SIG_PAD_IN1_IDX
-                },
-            }
-        }
-    }
+
 };
diff --git a/components/soc/esp32p4/rtc_io_periph.c b/components/soc/esp32p4/rtc_io_periph.c
index 51befd2bae..c8273e3f5b 100644
--- a/components/soc/esp32p4/rtc_io_periph.c
+++ b/components/soc/esp32p4/rtc_io_periph.c
@@ -7,35 +7,5 @@
 #include "soc/rtc_periph.h"
 
 const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-    RTCIO_GPIO0_CHANNEL,    //GPIO0
-    RTCIO_GPIO1_CHANNEL,    //GPIO1
-    RTCIO_GPIO2_CHANNEL,    //GPIO2
-    RTCIO_GPIO3_CHANNEL,    //GPIO3
-    RTCIO_GPIO4_CHANNEL,    //GPIO4
-    RTCIO_GPIO5_CHANNEL,    //GPIO5
-    RTCIO_GPIO6_CHANNEL,    //GPIO6
-    RTCIO_GPIO7_CHANNEL,    //GPIO7
-    -1,//GPIO8
-    -1,//GPIO9
-    -1,//GPIO10
-    -1,//GPIO11
-    -1,//GPIO12
-    -1,//GPIO13
-    -1,//GPIO14
-    -1,//GPIO15
-    -1,//GPIO16
-    -1,//GPIO17
-    -1,//GPIO18
-    -1,//GPIO19
-    -1,//GPIO20
-    -1,//GPIO21
-    -1,//GPIO22
-    -1,//GPIO23
-    -1,//GPIO24
-    -1,//GPIO25
-    -1,//GPIO26
-    -1,//GPIO27
-    -1,//GPIO28
-    -1,//GPIO29
-    -1,//GPIO30
+
 };
diff --git a/components/soc/esp32p4/sdio_slave_periph.c b/components/soc/esp32p4/sdio_slave_periph.c
index 21d9501108..e5f5a19fc5 100644
--- a/components/soc/esp32p4/sdio_slave_periph.c
+++ b/components/soc/esp32p4/sdio_slave_periph.c
@@ -8,13 +8,5 @@
 #include "soc/sdio_slave_pins.h"
 
 const sdio_slave_slot_info_t sdio_slave_slot_info[1]  = {
-    {
-        .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK,
-        .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD,
-        .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0,
-        .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1,
-        .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2,
-        .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3,
-        .func = SDIO_SLAVE_SLOT0_FUNC,
-    },
+
 };
diff --git a/components/soc/esp32p4/sdm_periph.c b/components/soc/esp32p4/sdm_periph.c
index 2c47c3bee1..da3f711ad8 100644
--- a/components/soc/esp32p4/sdm_periph.c
+++ b/components/soc/esp32p4/sdm_periph.c
@@ -8,18 +8,5 @@
 #include "soc/gpio_sig_map.h"
 
 const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
-    .channels = {
-        [0] = {
-            GPIO_SD0_OUT_IDX
-        },
-        [1] = {
-            GPIO_SD1_OUT_IDX
-        },
-        [2] = {
-            GPIO_SD2_OUT_IDX
-        },
-        [3] = {
-            GPIO_SD3_OUT_IDX
-        }
-    }
+
 };
diff --git a/components/soc/esp32p4/sdmmc_periph.c b/components/soc/esp32p4/sdmmc_periph.c
index 8b12f54d34..1fb72fb2c3 100644
--- a/components/soc/esp32p4/sdmmc_periph.c
+++ b/components/soc/esp32p4/sdmmc_periph.c
@@ -7,57 +7,13 @@
 #include "soc/sdmmc_periph.h"
 // ESP32P4-TODO: need new iomux and sig map
 const sdmmc_slot_info_t sdmmc_slot_info[SOC_SDMMC_NUM_SLOTS] = {
-    {
-        .width = 8,
-        .card_detect = 0,
-        .write_protect = 0,
-        .card_int = 0,
-    },
-    {
-        .width = 4,
-        .card_detect = 0,
-        .write_protect = 0,
-        .card_int = 0,
-    }
+
 };
 
 const sdmmc_slot_io_info_t sdmmc_slot_gpio_num[SOC_SDMMC_NUM_SLOTS] = {
-    {
-        .clk = SDMMC_SLOT0_IOMUX_PIN_NUM_CLK,
-        .cmd = SDMMC_SLOT0_IOMUX_PIN_NUM_CMD,
-        .d0 = SDMMC_SLOT0_IOMUX_PIN_NUM_D0,
-        .d1 = SDMMC_SLOT0_IOMUX_PIN_NUM_D1,
-        .d2 = SDMMC_SLOT0_IOMUX_PIN_NUM_D2,
-        .d3 = SDMMC_SLOT0_IOMUX_PIN_NUM_D3,
-        .d4 = SDMMC_SLOT0_IOMUX_PIN_NUM_D4,
-        .d5 = SDMMC_SLOT0_IOMUX_PIN_NUM_D5,
-        .d6 = SDMMC_SLOT0_IOMUX_PIN_NUM_D6,
-        .d7 = SDMMC_SLOT0_IOMUX_PIN_NUM_D7,
-    },
-    {
-        .clk = SDMMC_SLOT1_IOMUX_PIN_NUM_CLK,
-        .cmd = SDMMC_SLOT1_IOMUX_PIN_NUM_CMD,
-        .d0 = SDMMC_SLOT1_IOMUX_PIN_NUM_D0,
-        .d1 = SDMMC_SLOT1_IOMUX_PIN_NUM_D1,
-        .d2 = SDMMC_SLOT1_IOMUX_PIN_NUM_D2,
-        .d3 = SDMMC_SLOT1_IOMUX_PIN_NUM_D3,
-    }
+
 };
 
 const sdmmc_slot_io_info_t sdmmc_slot_gpio_sig[SOC_SDMMC_NUM_SLOTS] = {
-    {
 
-    },
-    {
-        .clk = SD_CARD_CCLK_2_PAD_OUT_IDX,
-        .cmd = SD_CARD_CCMD_2_PAD_OUT_IDX,
-        .d0 = SD_CARD_CDATA0_2_PAD_OUT_IDX,
-        .d1 = SD_CARD_CDATA1_2_PAD_OUT_IDX,
-        .d2 = SD_CARD_CDATA2_2_PAD_OUT_IDX,
-        .d3 = SD_CARD_CDATA3_2_PAD_OUT_IDX,
-        .d4 = SD_CARD_CDATA4_2_PAD_OUT_IDX,
-        .d5 = SD_CARD_CDATA5_2_PAD_OUT_IDX,
-        .d6 = SD_CARD_CDATA6_2_PAD_OUT_IDX,
-        .d7 = SD_CARD_CDATA7_2_PAD_OUT_IDX,
-    },
 };
diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c
index 86c2e7bbfe..3534bb9428 100644
--- a/components/soc/esp32p4/spi_periph.c
+++ b/components/soc/esp32p4/spi_periph.c
@@ -11,43 +11,5 @@
  Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
-    {
-        .spiclk_in = 0,/* SPI clock is not an input signal*/
-        .spics_in = 0,/* SPI cs is not an input signal*/
-        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
-        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
-        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
-        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
-        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
-        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
-        .irq = ETS_MSPI_INTR_SOURCE,
-        .irq_dma = -1,
-        .module = PERIPH_SPI_MODULE,
-        .hw = (spi_dev_t *) &SPIMEM1,
-        .func = SPI_FUNC_NUM,
-    }, { // TODO: IDF-5334 Need check
-        .spiclk_out = FSPICLK_OUT_IDX,
-        .spiclk_in = FSPICLK_IN_IDX,
-        .spid_out = FSPID_OUT_IDX,
-        .spiq_out = FSPIQ_OUT_IDX,
-        .spiwp_out = FSPIWP_OUT_IDX,
-        .spihd_out = FSPIHD_OUT_IDX,
-        .spid_in = FSPID_IN_IDX,
-        .spiq_in = FSPIQ_IN_IDX,
-        .spiwp_in = FSPIWP_IN_IDX,
-        .spihd_in = FSPIHD_IN_IDX,
-        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
-        .spics_in = FSPICS0_IN_IDX,
-        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
-        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
-        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
-        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
-        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
-        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
-        .irq = ETS_GSPI2_INTR_SOURCE,
-        .irq_dma = -1,
-        .module = PERIPH_SPI2_MODULE,
-        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
-    }
+
 };
diff --git a/components/soc/esp32p4/temperature_sensor_periph.c b/components/soc/esp32p4/temperature_sensor_periph.c
index a681a41e3b..a9812ecc72 100644
--- a/components/soc/esp32p4/temperature_sensor_periph.c
+++ b/components/soc/esp32p4/temperature_sensor_periph.c
@@ -7,10 +7,5 @@
 #include "soc/temperature_sensor_periph.h"
 
 const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
-    /*Offset   reg_val  min  max  error */
-    {-2,     5,    50,  125,   3},
-    {-1,     7,    20,  100,   2},
-    { 0,    15,   -10,   80,   1},
-    { 1,    11,   -30,   50,   2},
-    { 2,    10,   -40,   20,   3},
+
 };
diff --git a/components/soc/esp32p4/timer_periph.c b/components/soc/esp32p4/timer_periph.c
index d0d4ca2e81..96eb286c20 100644
--- a/components/soc/esp32p4/timer_periph.c
+++ b/components/soc/esp32p4/timer_periph.c
@@ -7,18 +7,5 @@
 #include "soc/timer_periph.h"
 
 const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-            }
-        },
-        [1] = {
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
-            }
-        }
-    }
+
 };
diff --git a/components/soc/esp32p4/twai_periph.c b/components/soc/esp32p4/twai_periph.c
index 3f7d17c41d..061cd4a4d7 100644
--- a/components/soc/esp32p4/twai_periph.c
+++ b/components/soc/esp32p4/twai_periph.c
@@ -8,24 +8,5 @@
 #include "soc/gpio_sig_map.h"
 
 const twai_controller_signal_conn_t twai_controller_periph_signals = {
-    .controllers = {
-        [0] = {
-            .module = PERIPH_TWAI0_MODULE,
-            .irq_id = ETS_TWAI0_INTR_SOURCE,
-            .tx_sig = TWAI0_TX_IDX,
-            .rx_sig = TWAI0_RX_IDX,
-            .bus_off_sig = TWAI0_BUS_OFF_ON_IDX,
-            .clk_out_sig = TWAI0_CLKOUT_IDX,
-            .stand_by_sig = TWAI0_STANDBY_IDX,
-        },
-        [1] = {
-            .module = PERIPH_TWAI1_MODULE,
-            .irq_id = ETS_TWAI1_INTR_SOURCE,
-            .tx_sig = TWAI1_TX_IDX,
-            .rx_sig = TWAI1_RX_IDX,
-            .bus_off_sig = TWAI1_BUS_OFF_ON_IDX,
-            .clk_out_sig = TWAI1_CLKOUT_IDX,
-            .stand_by_sig = TWAI1_STANDBY_IDX,
-        }
-    }
+
 };
diff --git a/components/soc/esp32p4/uart_periph.c b/components/soc/esp32p4/uart_periph.c
index 506d808273..2b0c63eb1b 100644
--- a/components/soc/esp32p4/uart_periph.c
+++ b/components/soc/esp32p4/uart_periph.c
@@ -10,71 +10,5 @@
  Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
-   {
-        .pins = {
-            [SOC_UART_TX_PIN_IDX] = {
-                .default_gpio = U0TXD_GPIO_NUM,
-                .iomux_func = U0TXD_MUX_FUNC,
-                .input = 0,
-                .signal = 0,
-            },
 
-            [SOC_UART_RX_PIN_IDX] = {
-                .default_gpio = U0RXD_GPIO_NUM,
-                .iomux_func = U0RXD_MUX_FUNC,
-                .input = 1,
-                .signal = 0,
-            },
-
-            [SOC_UART_RTS_PIN_IDX] = {
-                .default_gpio = U0RTS_GPIO_NUM,
-                .iomux_func = U0RTS_MUX_FUNC,
-                .input = 0,
-                .signal = 0,
-            },
-
-            [SOC_UART_CTS_PIN_IDX] = {
-                .default_gpio = U0CTS_GPIO_NUM,
-                .iomux_func = U0CTS_MUX_FUNC,
-                .input = 1,
-                .signal = 0,
-            }
-        },
-        .irq = ETS_UART0_INTR_SOURCE,
-        .module = PERIPH_UART0_MODULE,
-    },
-
-    {
-        .pins = {
-            [SOC_UART_TX_PIN_IDX] = {
-                .default_gpio = U1TXD_GPIO_NUM,
-                .iomux_func = U1TXD_MUX_FUNC,
-                .input = 0,
-                .signal = 0,
-            },
-
-            [SOC_UART_RX_PIN_IDX] = {
-                .default_gpio = U1RXD_GPIO_NUM,
-                .iomux_func = U1RXD_MUX_FUNC,
-                .input = 1,
-                .signal = 0,
-            },
-
-            [SOC_UART_RTS_PIN_IDX] = {
-                .default_gpio = U1RTS_GPIO_NUM,
-                .iomux_func = U1RTS_MUX_FUNC,
-                .input = 0,
-                .signal = 0,
-            },
-
-            [SOC_UART_CTS_PIN_IDX] = {
-                .default_gpio = U1CTS_GPIO_NUM,
-                .iomux_func = U1CTS_MUX_FUNC,
-                .input = 1,
-                .signal = 0,
-            },
-        },
-        .irq = ETS_UART1_INTR_SOURCE,
-        .module = PERIPH_UART1_MODULE,
-    },
 };
diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h
index 725486d50f..80fd7187e1 100644
--- a/components/soc/include/soc/rtc_cntl_periph.h
+++ b/components/soc/include/soc/rtc_cntl_periph.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,15 +9,28 @@
 #include "sdkconfig.h"
 
 // TODO: IDF-5645
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4
+#if CONFIG_IDF_TARGET_ESP32C6
+#include "soc/lp_io_reg.h"
+#include "soc/lp_io_struct.h"
 #include "soc/lp_aon_reg.h"
+
+// ESP32H2-TODO: IDF-6327
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "soc/lp_aon_reg.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "soc/lp_gpio_reg.h"
+#include "soc/lp_gpio_struct.h"
+#include "soc/lp_iomux_reg.h"
+#include "soc/lp_iomux_struct.h"
+#endif
+
+// TODO: IDF-5645
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4
 #include "soc/lp_analog_peri_reg.h"
 #include "soc/lp_clkrst_reg.h"
 #include "soc/lp_clkrst_struct.h"
 #include "soc/lp_i2c_reg.h"
 #include "soc/lp_i2c_struct.h"
-#include "soc/lp_io_reg.h"
-#include "soc/lp_io_struct.h"
 #include "soc/lp_timer_reg.h"
 #include "soc/lp_timer_struct.h"
 #include "soc/lp_uart_reg.h"
@@ -26,7 +39,6 @@
 #include "soc/lp_wdt_struct.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 // ESP32H2-TODO: IDF-6327
-#include "soc/lp_aon_reg.h"
 #include "soc/lp_analog_peri_reg.h"
 #include "soc/lp_clkrst_reg.h"
 #include "soc/lp_clkrst_struct.h"

From e921d03a0d4b5ce47d7d23432aa3d928f92e67e2 Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Fri, 30 Jun 2023 10:49:44 +0800
Subject: [PATCH 08/13] feat(soc): update gpio_ext_reg.h and its base addr

---
 .../soc/esp32p4/include/soc/gpio_ext_reg.h    | 80 +++++++++----------
 components/soc/esp32p4/include/soc/reg_base.h |  6 +-
 2 files changed, 41 insertions(+), 45 deletions(-)

diff --git a/components/soc/esp32p4/include/soc/gpio_ext_reg.h b/components/soc/esp32p4/include/soc/gpio_ext_reg.h
index f994cd233e..157a4c9e0a 100644
--- a/components/soc/esp32p4/include/soc/gpio_ext_reg.h
+++ b/components/soc/esp32p4/include/soc/gpio_ext_reg.h
@@ -23,7 +23,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA0_REG register
  *  Duty Cycle Configure Register of SDM0
  */
-#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0)
+#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -42,7 +42,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA1_REG register
  *  Duty Cycle Configure Register of SDM1
  */
-#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4)
+#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -61,7 +61,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA2_REG register
  *  Duty Cycle Configure Register of SDM2
  */
-#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8)
+#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -80,7 +80,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA3_REG register
  *  Duty Cycle Configure Register of SDM3
  */
-#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc)
+#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -99,7 +99,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA4_REG register
  *  Duty Cycle Configure Register of SDM4
  */
-#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10)
+#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIO_EXT_BASE + 0x10)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -118,7 +118,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA5_REG register
  *  Duty Cycle Configure Register of SDM5
  */
-#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14)
+#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIO_EXT_BASE + 0x14)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -137,7 +137,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA6_REG register
  *  Duty Cycle Configure Register of SDM6
  */
-#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18)
+#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIO_EXT_BASE + 0x18)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -156,7 +156,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA7_REG register
  *  Duty Cycle Configure Register of SDM7
  */
-#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c)
+#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIO_EXT_BASE + 0x1c)
 /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -175,7 +175,7 @@ extern "C" {
 /** GPIOSD_SIGMADELTA_MISC_REG register
  *  MISC Register
  */
-#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24)
+#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24)
 /** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
  *  Clock enable bit of sigma delta modulation.
  */
@@ -194,7 +194,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH0_REG register
  *  Glitch Filter Configure Register of Channel0
  */
-#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30)
+#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -227,7 +227,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH1_REG register
  *  Glitch Filter Configure Register of Channel1
  */
-#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34)
+#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -260,7 +260,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH2_REG register
  *  Glitch Filter Configure Register of Channel2
  */
-#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38)
+#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -293,7 +293,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH3_REG register
  *  Glitch Filter Configure Register of Channel3
  */
-#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c)
+#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -326,7 +326,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH4_REG register
  *  Glitch Filter Configure Register of Channel4
  */
-#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40)
+#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -359,7 +359,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH5_REG register
  *  Glitch Filter Configure Register of Channel5
  */
-#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44)
+#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -392,7 +392,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH6_REG register
  *  Glitch Filter Configure Register of Channel6
  */
-#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48)
+#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -425,7 +425,7 @@ extern "C" {
 /** GPIOSD_GLITCH_FILTER_CH7_REG register
  *  Glitch Filter Configure Register of Channel7
  */
-#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c)
+#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c)
 /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -458,7 +458,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH0_CFG_REG register
  *  Etm Config register of Channel0
  */
-#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60)
+#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -477,7 +477,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH1_CFG_REG register
  *  Etm Config register of Channel1
  */
-#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64)
+#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -496,7 +496,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH2_CFG_REG register
  *  Etm Config register of Channel2
  */
-#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68)
+#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -515,7 +515,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH3_CFG_REG register
  *  Etm Config register of Channel3
  */
-#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c)
+#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -534,7 +534,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH4_CFG_REG register
  *  Etm Config register of Channel4
  */
-#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70)
+#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -553,7 +553,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH5_CFG_REG register
  *  Etm Config register of Channel5
  */
-#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74)
+#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -572,7 +572,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH6_CFG_REG register
  *  Etm Config register of Channel6
  */
-#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78)
+#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -591,7 +591,7 @@ extern "C" {
 /** GPIOSD_ETM_EVENT_CH7_CFG_REG register
  *  Etm Config register of Channel7
  */
-#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c)
+#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c)
 /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -610,7 +610,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P0_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0)
+#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0)
 /** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -671,7 +671,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P1_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4)
+#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4)
 /** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -732,7 +732,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P2_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8)
+#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8)
 /** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -793,7 +793,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P3_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac)
+#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac)
 /** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -854,7 +854,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P4_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0)
+#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0)
 /** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -915,7 +915,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P5_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4)
+#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4)
 /** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -976,7 +976,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P6_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8)
+#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8)
 /** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1037,7 +1037,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P7_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc)
+#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xbc)
 /** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1098,7 +1098,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P8_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0)
+#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc0)
 /** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1159,7 +1159,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P9_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4)
+#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc4)
 /** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1220,7 +1220,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P10_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8)
+#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc8)
 /** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1281,7 +1281,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P11_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc)
+#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xcc)
 /** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1342,7 +1342,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P12_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0)
+#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd0)
 /** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1403,7 +1403,7 @@ extern "C" {
 /** GPIOSD_ETM_TASK_P13_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4)
+#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd4)
 /** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0;
  *  Enable bit of GPIO response etm task.
  */
@@ -1450,7 +1450,7 @@ extern "C" {
 /** GPIOSD_VERSION_REG register
  *  Version Control Register
  */
-#define GPIOSD_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc)
+#define GPIOSD_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc)
 /** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952;
  *  Version control register.
  */
diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h
index c6397f4729..5fb009f8cb 100644
--- a/components/soc/esp32p4/include/soc/reg_base.h
+++ b/components/soc/esp32p4/include/soc/reg_base.h
@@ -106,7 +106,7 @@
 #define DR_REG_ADC_BASE               (DR_REG_HPPERIPH1_BASE + 0x1E000)
 #define DR_REG_UHCI_BASE              (DR_REG_HPPERIPH1_BASE + 0x1F000)
 #define DR_REG_GPIO_BASE              (DR_REG_HPPERIPH1_BASE + 0x20000)
-#define DR_REG_GPIO_SD_BASE           (DR_REG_HPPERIPH1_BASE + 0x20F00)
+#define DR_REG_GPIO_EXT_BASE          (DR_REG_HPPERIPH1_BASE + 0x20F00)
 #define DR_REG_IO_MUX_BASE            (DR_REG_HPPERIPH1_BASE + 0x21000)
 #define DR_REG_SYSTIMER_BASE          (DR_REG_HPPERIPH1_BASE + 0x22000)
 #define DR_REG_MEM_MON_BASE           (DR_REG_HPPERIPH1_BASE + 0x23000)
@@ -186,10 +186,6 @@
 #define DR_REG_LPPERI_BASE                      DR_REG_LP_PERI_CLKRST_BASE
 #define DR_REG_CPU_BUS_MONITOR_BASE             DR_REG_CPU_BUS_MON_BASE
 
-
-//TODO: IDF-7481, TODO: IDF-7479, TODO: IDF-7551
-// #define DR_REG_GPIO_EXT_BASE                    0x60091f00
-
 //TODO: IDF-7542
 // #define DR_REG_TEE_BASE                         0x60098000
 // #define DR_REG_HP_APM_BASE                      0x60099000

From 9d755f855ecb44ebf0825f0ce1d0c0317f06335d Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Fri, 30 Jun 2023 11:18:53 +0800
Subject: [PATCH 09/13] feat(soc): update efuse registers

---
 .../soc/esp32p4/include/soc/efuse_mem_reg.h   | 4139 -----------
 .../esp32p4/include/soc/efuse_mem_struct.h    | 4449 ------------
 .../soc/esp32p4/include/soc/efuse_reg.h       | 6194 ++++++++++-------
 .../soc/esp32p4/include/soc/efuse_struct.h    | 5425 ++++++++++++---
 4 files changed, 8056 insertions(+), 12151 deletions(-)
 delete mode 100644 components/soc/esp32p4/include/soc/efuse_mem_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/efuse_mem_struct.h

diff --git a/components/soc/esp32p4/include/soc/efuse_mem_reg.h b/components/soc/esp32p4/include/soc/efuse_mem_reg.h
deleted file mode 100644
index e982d77684..0000000000
--- a/components/soc/esp32p4/include/soc/efuse_mem_reg.h
+++ /dev/null
@@ -1,4139 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled. 1: Disabled. 0 Enabled.
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0;
- *  Enable usb device exchange pins of D+ and D-.
- */
-#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
-#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
-#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
-/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0;
- *  Enable usb otg11 exchange pins of D+ and D-.
- */
-#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
-#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
-#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
- *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_POWERGLITCH_EN    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
-#define EFUSE_POWERGLITCH_EN_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_S  10
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
- *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
- *  boot_mode_download.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
- *  enabled.
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode). 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
- *  TBD
- */
-#define EFUSE_USB_PHY_SEL    (BIT(25))
-#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
-#define EFUSE_USB_PHY_SEL_V  0x00000001U
-#define EFUSE_USB_PHY_SEL_S  25
-/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0;
- *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
- *  of 1 is valid.
- */
-#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003FU
-#define EFUSE_KM_HUK_GEN_STATE_LOW_M  (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S)
-#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x0000003FU
-#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  BLOCK0 data register 2.
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0;
- *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
- *  of 1 is valid.
- */
-#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S)
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0;
- *  Set bits to control key manager random number switch cycle. 0: control by register.
- *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
-/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0;
- *  Set each bit to control whether corresponding key can only be deployed once. 1 is
- *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0;
- *  Set each bit to control whether corresponding key must come from key manager.. 1 is
- *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0;
- *  Set this bit to disable software written init key, and force use efuse_init_key.
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
-/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
- *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
- */
-#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
-#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_S  14
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
- *  selected. 0: not selected.
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
- *  1: enabled. Even number of 1: disabled.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Represents the purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Represents the purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  BLOCK0 data register 3.
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
- */
-#define EFUSE_SEC_DPA_LEVEL    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
-#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_S  16
-/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0;
- *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
- *  0: not force used.
- */
-#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S)
-#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x00000001U
-#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
-/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
- *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
- */
-#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
-#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_S  19
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
- *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
- */
-#define EFUSE_FLASH_TYPE    (BIT(23))
-#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
-#define EFUSE_FLASH_TYPE_V  0x00000001U
-#define EFUSE_FLASH_TYPE_S  23
-/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0;
- *  Set flash page size.
- */
-#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
-#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_S  24
-/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0;
- *  Set this bit to enable ecc for flash boot.
- */
-#define EFUSE_FLASH_ECC_EN    (BIT(26))
-#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
-#define EFUSE_FLASH_ECC_EN_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_S  26
-/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0;
- *  Set this bit to disable download via USB-OTG.
- */
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
- *  is 2 times the programmed value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  BLOCK0 data register 4.
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
- *  0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
- *  TBD
- */
-#define EFUSE_LOCK_KM_KEY    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
-#define EFUSE_LOCK_KM_KEY_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Represents whether security download is enabled or disabled. 1: enabled. 0:
- *  disabled.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Represents the type of UART printing. 00: force enable printing. 01: enable
- *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
- *  at high level. 11: force disable printing.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
- *  forced. 0:not forced.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  8
-/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
- *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
-/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
- *  enabled. 0:disabled.
- */
-#define EFUSE_HYS_EN_PAD    (BIT(26))
-#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
-#define EFUSE_HYS_EN_PAD_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_S  26
-/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0;
- *  Set the dcdc voltage default.
- */
-#define EFUSE_DCDC_VSET    0x0000001FU
-#define EFUSE_DCDC_VSET_M  (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S)
-#define EFUSE_DCDC_VSET_V  0x0000001FU
-#define EFUSE_DCDC_VSET_S  27
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  BLOCK0 data register 5.
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_0PXA_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
- *  TBD
- */
-#define EFUSE_0PXA_TIEH_SEL_0    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_M  (EFUSE_0PXA_TIEH_SEL_0_V << EFUSE_0PXA_TIEH_SEL_0_S)
-#define EFUSE_0PXA_TIEH_SEL_0_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_S  0
-/** EFUSE_0PXA_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
- *  TBD.
- */
-#define EFUSE_0PXA_TIEH_SEL_1    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_M  (EFUSE_0PXA_TIEH_SEL_1_V << EFUSE_0PXA_TIEH_SEL_1_S)
-#define EFUSE_0PXA_TIEH_SEL_1_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_S  2
-/** EFUSE_0PXA_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
- *  TBD.
- */
-#define EFUSE_0PXA_TIEH_SEL_2    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_M  (EFUSE_0PXA_TIEH_SEL_2_V << EFUSE_0PXA_TIEH_SEL_2_S)
-#define EFUSE_0PXA_TIEH_SEL_2_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_S  4
-/** EFUSE_0PXA_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
- *  TBD.
- */
-#define EFUSE_0PXA_TIEH_SEL_3    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_M  (EFUSE_0PXA_TIEH_SEL_3_V << EFUSE_0PXA_TIEH_SEL_3_S)
-#define EFUSE_0PXA_TIEH_SEL_3_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_S  6
-/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
- *  TBD.
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
-/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
- *  HP system power source select. 0:LDO. 1: DCDC.
- */
-#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_M  (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S)
-#define EFUSE_HP_PWR_SRC_SEL_V  0x00000001U
-#define EFUSE_HP_PWR_SRC_SEL_S  18
-/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0;
- *  Select dcdc vset use efuse_dcdc_vset.
- */
-#define EFUSE_DCDC_VSET_EN    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
-#define EFUSE_DCDC_VSET_EN_V  0x00000001U
-#define EFUSE_DCDC_VSET_EN_S  19
-/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0;
- *  Set this bit to disable watch dog.
- */
-#define EFUSE_DIS_WDT    (BIT(20))
-#define EFUSE_DIS_WDT_M  (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S)
-#define EFUSE_DIS_WDT_V  0x00000001U
-#define EFUSE_DIS_WDT_S  20
-/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0;
- *  Set this bit to disable super-watchdog.
- */
-#define EFUSE_DIS_SWD    (BIT(21))
-#define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
-#define EFUSE_DIS_SWD_V  0x00000001U
-#define EFUSE_DIS_SWD_S  21
-
-/** EFUSE_RD_MAC_SYS_0_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the low 32 bits of MAC address.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SYS_1_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Stores the high 16 bits of MAC address.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
- *  Stores the extended bits of MAC address.
- */
-#define EFUSE_MAC_EXT    0x0000FFFFU
-#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
-#define EFUSE_MAC_EXT_V  0x0000FFFFU
-#define EFUSE_MAC_EXT_S  16
-
-/** EFUSE_RD_MAC_SYS_2_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_1    0x00003FFFU
-#define EFUSE_MAC_RESERVED_1_M  (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
-#define EFUSE_MAC_RESERVED_1_V  0x00003FFFU
-#define EFUSE_MAC_RESERVED_1_S  0
-/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_0    0x0003FFFFU
-#define EFUSE_MAC_RESERVED_0_M  (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
-#define EFUSE_MAC_RESERVED_0_V  0x0003FFFFU
-#define EFUSE_MAC_RESERVED_0_S  14
-
-/** EFUSE_RD_MAC_SYS_3_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_2    0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
-#define EFUSE_MAC_RESERVED_2_V  0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_S  0
-/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
- *  Stores the first 14 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
-#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_S  18
-
-/** EFUSE_RD_MAC_SYS_4_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
-#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_S  0
-
-/** EFUSE_RD_MAC_SYS_5_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_0_M  (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
-#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_0_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_1_M  (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
-#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_2_M  (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
-#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_3_M  (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
-#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
-#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
-#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
-#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
-#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_S  0
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA6    0xFFFFFFFFU
-#define EFUSE_USR_DATA6_M  (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
-#define EFUSE_USR_DATA6_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA6_S  0
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA7    0xFFFFFFFFU
-#define EFUSE_USR_DATA7_M  (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
-#define EFUSE_USR_DATA7_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA7_S  0
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_ERR0_REG register
- *  Programming error record register 0 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Indicates a programming error of RD_DIS.
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0;
- *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
- */
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S)
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
-/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
- */
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S)
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Indicates a programming error of DIS_USB_JTAG.
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
- *  Indicates a programming error of POWERGLITCH_EN.
- */
-#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
-#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_ERR_S  10
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
-/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of DIS_TWAI.
- */
-#define EFUSE_DIS_TWAI_ERR    (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
-#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
-#define EFUSE_DIS_TWAI_ERR_S  14
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  Indicates a programming error of JTAG_SEL_ENABLE.
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  Indicates a programming error of SOFT_DIS_JTAG.
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DIS_PAD_JTAG.
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of USB_PHY_SEL.
- */
-#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
-#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
-#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
-#define EFUSE_USB_PHY_SEL_ERR_S  25
-/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0;
- *  Indicates a programming error of HUK_GEN_STATE_LOW.
- */
-#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003FU
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S)
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x0000003FU
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
-
-/** EFUSE_RD_REPEAT_ERR1_REG register
- *  Programming error record register 1 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0;
- *  Indicates a programming error of HUK_GEN_STATE_HIGH.
- */
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0;
- *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
-/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0;
- *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0;
- *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
-/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of XTS_KEY_LENGTH_256.
- */
-#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of WDT_DELAY_SEL.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_0.
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_1.
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR2_REG register
- *  Programming error record register 2 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_2.
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_3.
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_4.
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_5.
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of SEC_DPA_LEVEL.
- */
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0;
- *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
- */
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S)
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x00000001U
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
-/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of CRYPT_DPA_ENABLE.
- */
-#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_EN.
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of FLASH_TYPE.
- */
-#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
-#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
-#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
-#define EFUSE_FLASH_TYPE_ERR_S  23
-/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0;
- *  Indicates a programming error of FLASH_PAGE_SIZE.
- */
-#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
-#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
-/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of FLASH_ECC_EN.
- */
-#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
-#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
-#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_ERR_S  26
-/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0;
- *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of FLASH_TPUW.
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR3_REG register
- *  Programming error record register 3 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Indicates a programming error of DIS_DIRECT_BOOT.
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
-/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
- *  TBD
- */
-#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
-#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_ERR_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of UART_PRINT_CONTROL.
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of FORCE_SEND_RESUME.
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
- *  Indicates a programming error of SECURE VERSION.
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
-/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of HYS_EN_PAD.
- */
-#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
-#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
-#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_ERR_S  26
-/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0;
- *  Indicates a programming error of DCDC_VSET.
- */
-#define EFUSE_DCDC_VSET_ERR    0x0000001FU
-#define EFUSE_DCDC_VSET_ERR_M  (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S)
-#define EFUSE_DCDC_VSET_ERR_V  0x0000001FU
-#define EFUSE_DCDC_VSET_ERR_S  27
-
-/** EFUSE_RD_REPEAT_ERR4_REG register
- *  Programming error record register 4 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
-/** EFUSE_0PXA_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_0.
- */
-#define EFUSE_0PXA_TIEH_SEL_0_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_M  (EFUSE_0PXA_TIEH_SEL_0_ERR_V << EFUSE_0PXA_TIEH_SEL_0_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_S  0
-/** EFUSE_0PXA_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_1.
- */
-#define EFUSE_0PXA_TIEH_SEL_1_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_M  (EFUSE_0PXA_TIEH_SEL_1_ERR_V << EFUSE_0PXA_TIEH_SEL_1_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_S  2
-/** EFUSE_0PXA_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_2.
- */
-#define EFUSE_0PXA_TIEH_SEL_2_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_M  (EFUSE_0PXA_TIEH_SEL_2_ERR_V << EFUSE_0PXA_TIEH_SEL_2_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_S  4
-/** EFUSE_0PXA_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_3.
- */
-#define EFUSE_0PXA_TIEH_SEL_3_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_M  (EFUSE_0PXA_TIEH_SEL_3_ERR_V << EFUSE_0PXA_TIEH_SEL_3_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_S  6
-/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
- *  TBD.
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
-/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0;
- *  Indicates a programming error of USB_DEVICE_DREFL.
- */
-#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_ERR_M  (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S)
-#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
-/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0;
- *  Indicates a programming error of USB_OTG11_DREFL.
- */
-#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003U
-#define EFUSE_USB_OTG11_DREFL_ERR_M  (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S)
-#define EFUSE_USB_OTG11_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFL_ERR_S  14
-/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0;
- *  Indicates a programming error of HP_PWR_SRC_SEL.
- */
-#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S)
-#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x00000001U
-#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
-/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DCDC_VSET_EN.
- */
-#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
-#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
-#define EFUSE_DCDC_VSET_EN_ERR_S  19
-/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_WDT.
- */
-#define EFUSE_DIS_WDT_ERR    (BIT(20))
-#define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
-#define EFUSE_DIS_WDT_ERR_V  0x00000001U
-#define EFUSE_DIS_WDT_ERR_S  20
-/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of DIS_SWD.
- */
-#define EFUSE_DIS_SWD_ERR    (BIT(21))
-#define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
-#define EFUSE_DIS_SWD_ERR_V  0x00000001U
-#define EFUSE_DIS_SWD_ERR_S  21
-
-/** EFUSE_RD_RS_ERR0_REG register
- *  Programming error record register 0 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_MAC_SYS_ERR_NUM    0x00000007U
-#define EFUSE_MAC_SYS_ERR_NUM_M  (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S)
-#define EFUSE_MAC_SYS_ERR_NUM_V  0x00000007U
-#define EFUSE_MAC_SYS_ERR_NUM_S  0
-/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_MAC_SYS_FAIL    (BIT(3))
-#define EFUSE_MAC_SYS_FAIL_M  (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S)
-#define EFUSE_MAC_SYS_FAIL_V  0x00000001U
-#define EFUSE_MAC_SYS_FAIL_S  3
-/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART1_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART1_ERR_NUM_M  (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S)
-#define EFUSE_SYS_PART1_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART1_ERR_NUM_S  4
-/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART1_FAIL    (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
-#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART1_FAIL_S  7
-/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
-#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the user data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
-#define EFUSE_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_USR_DATA_FAIL_S  11
-/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY0_ERR_NUM    0x00000007U
-#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
-#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY0_ERR_NUM_S  12
-/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
- *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
- *  key0 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY0_FAIL    (BIT(15))
-#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
-#define EFUSE_KEY0_FAIL_V  0x00000001U
-#define EFUSE_KEY0_FAIL_S  15
-/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY1_ERR_NUM    0x00000007U
-#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
-#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY1_ERR_NUM_S  16
-/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
- *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
- *  key1 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY1_FAIL    (BIT(19))
-#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
-#define EFUSE_KEY1_FAIL_V  0x00000001U
-#define EFUSE_KEY1_FAIL_S  19
-/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY2_ERR_NUM    0x00000007U
-#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
-#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY2_ERR_NUM_S  20
-/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
- *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
- *  key2 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY2_FAIL    (BIT(23))
-#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
-#define EFUSE_KEY2_FAIL_V  0x00000001U
-#define EFUSE_KEY2_FAIL_S  23
-/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY3_ERR_NUM    0x00000007U
-#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
-#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY3_ERR_NUM_S  24
-/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
- *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
- *  key3 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY3_FAIL    (BIT(27))
-#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
-#define EFUSE_KEY3_FAIL_V  0x00000001U
-#define EFUSE_KEY3_FAIL_S  27
-/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY4_ERR_NUM    0x00000007U
-#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
-#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY4_ERR_NUM_S  28
-/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
- *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
- *  key4 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY4_FAIL    (BIT(31))
-#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
-#define EFUSE_KEY4_FAIL_V  0x00000001U
-#define EFUSE_KEY4_FAIL_S  31
-
-/** EFUSE_RD_RS_ERR1_REG register
- *  Programming error record register 1 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY5_ERR_NUM    0x00000007U
-#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
-#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY5_ERR_NUM_S  0
-/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
- *  key5 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY5_FAIL    (BIT(3))
-#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
-#define EFUSE_KEY5_FAIL_V  0x00000001U
-#define EFUSE_KEY5_FAIL_S  3
-/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART2_FAIL    (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
-#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART2_FAIL_S  7
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to force enable eFuse register configuration clock signal.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A:  programming operation command 0x5AA5: read operation command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
- *  Configures which block to use for ECDSA key output.
- */
-#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
-#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_S  16
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
- *  Indicates the number of block valid bit.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
- *  Indicates which block is used for ECDSA key output.
- */
-#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
-#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_S  20
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the read hold time.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures the read time.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures the read setup time.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
- *  Configures the waiting time of reading eFuse memory.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the programming setup time.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
- *  Configures the programming hold time.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  24
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
- *  Configures the active programming time.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
-/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
- *  Set this bit to bypass reed solomon correction step.
- */
-#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
-#define EFUSE_BYPASS_RS_CORRECTION_S  0
-/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
- *  Configures block number of programming twice operation.
- */
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
- *  Set this bit to update multi-bit register signals.
- */
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
-#define EFUSE_UPDATE_V  0x00000001U
-#define EFUSE_UPDATE_S  12
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
- *  Configures the inactive programming time.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  13
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-/** EFUSE_APB2OTP_WR_DIS_REG register
- *  eFuse apb2otp block0 data register1.
- */
-#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800)
-/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 write disable data.
- */
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
- *  eFuse apb2otp block0 data register2.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
- *  eFuse apb2otp block0 data register3.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
- *  eFuse apb2otp block0 data register4.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
- *  eFuse apb2otp block0 data register5.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
- *  eFuse apb2otp block0 data register6.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
- *  eFuse apb2otp block0 data register7.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
- *  eFuse apb2otp block0 data register8.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
- *  eFuse apb2otp block0 data register9.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
- *  eFuse apb2otp block0 data register10.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
- *  eFuse apb2otp block0 data register11.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
- *  eFuse apb2otp block0 data register12.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
- *  eFuse apb2otp block0 data register13.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
- *  eFuse apb2otp block0 data register14.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
- *  eFuse apb2otp block0 data register15.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
- *  eFuse apb2otp block0 data register16.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
- *  eFuse apb2otp block0 data register17.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
- *  eFuse apb2otp block0 data register18.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
- *  eFuse apb2otp block0 data register19.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
- *  eFuse apb2otp block0 data register20.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
- *  eFuse apb2otp block0 data register21.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W1_REG register
- *  eFuse apb2otp block1 data register1.
- */
-#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854)
-/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
-#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK1_W2_REG register
- *  eFuse apb2otp block1 data register2.
- */
-#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858)
-/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
-#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK1_W3_REG register
- *  eFuse apb2otp block1 data register3.
- */
-#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c)
-/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
-#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK1_W4_REG register
- *  eFuse apb2otp block1 data register4.
- */
-#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860)
-/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
-#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK1_W5_REG register
- *  eFuse apb2otp block1 data register5.
- */
-#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864)
-/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
-#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W6_REG register
- *  eFuse apb2otp block1 data register6.
- */
-#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868)
-/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
-#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_S  0
-
-/** EFUSE_APB2OTP_BLK1_W7_REG register
- *  eFuse apb2otp block1 data register7.
- */
-#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c)
-/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
-#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_S  0
-
-/** EFUSE_APB2OTP_BLK1_W8_REG register
- *  eFuse apb2otp block1 data register8.
- */
-#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870)
-/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
-#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_S  0
-
-/** EFUSE_APB2OTP_BLK1_W9_REG register
- *  eFuse apb2otp block1 data register9.
- */
-#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874)
-/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
-#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W1_REG register
- *  eFuse apb2otp block2 data register1.
- */
-#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878)
-/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
-#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK2_W2_REG register
- *  eFuse apb2otp block2 data register2.
- */
-#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c)
-/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
-#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK2_W3_REG register
- *  eFuse apb2otp block2 data register3.
- */
-#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880)
-/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
-#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK2_W4_REG register
- *  eFuse apb2otp block2 data register4.
- */
-#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884)
-/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
-#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK2_W5_REG register
- *  eFuse apb2otp block2 data register5.
- */
-#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888)
-/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
-#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK2_W6_REG register
- *  eFuse apb2otp block2 data register6.
- */
-#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c)
-/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
-#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_S  0
-
-/** EFUSE_APB2OTP_BLK2_W7_REG register
- *  eFuse apb2otp block2 data register7.
- */
-#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890)
-/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
-#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_S  0
-
-/** EFUSE_APB2OTP_BLK2_W8_REG register
- *  eFuse apb2otp block2 data register8.
- */
-#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894)
-/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
-#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_S  0
-
-/** EFUSE_APB2OTP_BLK2_W9_REG register
- *  eFuse apb2otp block2 data register9.
- */
-#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898)
-/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
-#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W10_REG register
- *  eFuse apb2otp block2 data register10.
- */
-#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c)
-/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
-#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_S  0
-
-/** EFUSE_APB2OTP_BLK2_W11_REG register
- *  eFuse apb2otp block2 data register11.
- */
-#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0)
-/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
-#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_S  0
-
-/** EFUSE_APB2OTP_BLK3_W1_REG register
- *  eFuse apb2otp block3 data register1.
- */
-#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4)
-/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
-#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK3_W2_REG register
- *  eFuse apb2otp block3 data register2.
- */
-#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8)
-/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
-#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK3_W3_REG register
- *  eFuse apb2otp block3 data register3.
- */
-#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac)
-/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
-#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK3_W4_REG register
- *  eFuse apb2otp block3 data register4.
- */
-#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0)
-/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
-#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK3_W5_REG register
- *  eFuse apb2otp block3 data register5.
- */
-#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4)
-/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
-#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK3_W6_REG register
- *  eFuse apb2otp block3 data register6.
- */
-#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8)
-/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
-#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_S  0
-
-/** EFUSE_APB2OTP_BLK3_W7_REG register
- *  eFuse apb2otp block3 data register7.
- */
-#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc)
-/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
-#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_S  0
-
-/** EFUSE_APB2OTP_BLK3_W8_REG register
- *  eFuse apb2otp block3 data register8.
- */
-#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0)
-/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
-#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_S  0
-
-/** EFUSE_APB2OTP_BLK3_W9_REG register
- *  eFuse apb2otp block3 data register9.
- */
-#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4)
-/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
-#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_S  0
-
-/** EFUSE_APB2OTP_BLK3_W10_REG register
- *  eFuse apb2otp block3 data register10.
- */
-#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8)
-/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
-#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_S  0
-
-/** EFUSE_APB2OTP_BLK3_W11_REG register
- *  eFuse apb2otp block3 data register11.
- */
-#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc)
-/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
-#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_S  0
-
-/** EFUSE_APB2OTP_BLK4_W1_REG register
- *  eFuse apb2otp block4 data register1.
- */
-#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0)
-/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
-#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK4_W2_REG register
- *  eFuse apb2otp block4 data register2.
- */
-#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4)
-/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
-#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK4_W3_REG register
- *  eFuse apb2otp block4 data register3.
- */
-#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8)
-/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
-#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK4_W4_REG register
- *  eFuse apb2otp block4 data register4.
- */
-#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc)
-/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
-#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK4_W5_REG register
- *  eFuse apb2otp block4 data register5.
- */
-#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0)
-/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
-#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK4_W6_REG register
- *  eFuse apb2otp block4 data register6.
- */
-#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4)
-/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
-#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_S  0
-
-/** EFUSE_APB2OTP_BLK4_W7_REG register
- *  eFuse apb2otp block4 data register7.
- */
-#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8)
-/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
-#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_S  0
-
-/** EFUSE_APB2OTP_BLK4_W8_REG register
- *  eFuse apb2otp block4 data register8.
- */
-#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec)
-/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
-#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_S  0
-
-/** EFUSE_APB2OTP_BLK4_W9_REG register
- *  eFuse apb2otp block4 data register9.
- */
-#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0)
-/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
-#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_S  0
-
-/** EFUSE_APB2OTP_BLK4_W10_REG register
- *  eFuse apb2otp block4 data registe10.
- */
-#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4)
-/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
-#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_S  0
-
-/** EFUSE_APB2OTP_BLK4_W11_REG register
- *  eFuse apb2otp block4 data register11.
- */
-#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8)
-/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
-#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_S  0
-
-/** EFUSE_APB2OTP_BLK5_W1_REG register
- *  eFuse apb2otp block5 data register1.
- */
-#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc)
-/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
-#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_S  0
-
-/** EFUSE_APB2OTP_BLK5_W2_REG register
- *  eFuse apb2otp block5 data register2.
- */
-#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900)
-/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
-#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_S  0
-
-/** EFUSE_APB2OTP_BLK5_W3_REG register
- *  eFuse apb2otp block5 data register3.
- */
-#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904)
-/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
-#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_S  0
-
-/** EFUSE_APB2OTP_BLK5_W4_REG register
- *  eFuse apb2otp block5 data register4.
- */
-#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908)
-/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
-#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_S  0
-
-/** EFUSE_APB2OTP_BLK5_W5_REG register
- *  eFuse apb2otp block5 data register5.
- */
-#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c)
-/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
-#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_S  0
-
-/** EFUSE_APB2OTP_BLK5_W6_REG register
- *  eFuse apb2otp block5 data register6.
- */
-#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910)
-/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
-#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_S  0
-
-/** EFUSE_APB2OTP_BLK5_W7_REG register
- *  eFuse apb2otp block5 data register7.
- */
-#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914)
-/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
-#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_S  0
-
-/** EFUSE_APB2OTP_BLK5_W8_REG register
- *  eFuse apb2otp block5 data register8.
- */
-#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918)
-/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
-#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_S  0
-
-/** EFUSE_APB2OTP_BLK5_W9_REG register
- *  eFuse apb2otp block5 data register9.
- */
-#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c)
-/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
-#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_S  0
-
-/** EFUSE_APB2OTP_BLK5_W10_REG register
- *  eFuse apb2otp block5 data register10.
- */
-#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920)
-/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
-#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_S  0
-
-/** EFUSE_APB2OTP_BLK5_W11_REG register
- *  eFuse apb2otp block5 data register11.
- */
-#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924)
-/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
-#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_S  0
-
-/** EFUSE_APB2OTP_BLK6_W1_REG register
- *  eFuse apb2otp block6 data register1.
- */
-#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928)
-/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
-#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_S  0
-
-/** EFUSE_APB2OTP_BLK6_W2_REG register
- *  eFuse apb2otp block6 data register2.
- */
-#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c)
-/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
-#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_S  0
-
-/** EFUSE_APB2OTP_BLK6_W3_REG register
- *  eFuse apb2otp block6 data register3.
- */
-#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930)
-/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
-#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_S  0
-
-/** EFUSE_APB2OTP_BLK6_W4_REG register
- *  eFuse apb2otp block6 data register4.
- */
-#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934)
-/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
-#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_S  0
-
-/** EFUSE_APB2OTP_BLK6_W5_REG register
- *  eFuse apb2otp block6 data register5.
- */
-#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938)
-/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
-#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_S  0
-
-/** EFUSE_APB2OTP_BLK6_W6_REG register
- *  eFuse apb2otp block6 data register6.
- */
-#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c)
-/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
-#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_S  0
-
-/** EFUSE_APB2OTP_BLK6_W7_REG register
- *  eFuse apb2otp block6 data register7.
- */
-#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940)
-/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
-#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_S  0
-
-/** EFUSE_APB2OTP_BLK6_W8_REG register
- *  eFuse apb2otp block6 data register8.
- */
-#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944)
-/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
-#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_S  0
-
-/** EFUSE_APB2OTP_BLK6_W9_REG register
- *  eFuse apb2otp block6 data register9.
- */
-#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948)
-/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
-#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_S  0
-
-/** EFUSE_APB2OTP_BLK6_W10_REG register
- *  eFuse apb2otp block6 data register10.
- */
-#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c)
-/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
-#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_S  0
-
-/** EFUSE_APB2OTP_BLK6_W11_REG register
- *  eFuse apb2otp block6 data register11.
- */
-#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950)
-/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
-#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_S  0
-
-/** EFUSE_APB2OTP_BLK7_W1_REG register
- *  eFuse apb2otp block7 data register1.
- */
-#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954)
-/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
-#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_S  0
-
-/** EFUSE_APB2OTP_BLK7_W2_REG register
- *  eFuse apb2otp block7 data register2.
- */
-#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958)
-/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
-#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_S  0
-
-/** EFUSE_APB2OTP_BLK7_W3_REG register
- *  eFuse apb2otp block7 data register3.
- */
-#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c)
-/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
-#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_S  0
-
-/** EFUSE_APB2OTP_BLK7_W4_REG register
- *  eFuse apb2otp block7 data register4.
- */
-#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960)
-/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
-#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_S  0
-
-/** EFUSE_APB2OTP_BLK7_W5_REG register
- *  eFuse apb2otp block7 data register5.
- */
-#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964)
-/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
-#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_S  0
-
-/** EFUSE_APB2OTP_BLK7_W6_REG register
- *  eFuse apb2otp block7 data register6.
- */
-#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968)
-/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
-#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_S  0
-
-/** EFUSE_APB2OTP_BLK7_W7_REG register
- *  eFuse apb2otp block7 data register7.
- */
-#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c)
-/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
-#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_S  0
-
-/** EFUSE_APB2OTP_BLK7_W8_REG register
- *  eFuse apb2otp block7 data register8.
- */
-#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970)
-/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
-#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_S  0
-
-/** EFUSE_APB2OTP_BLK7_W9_REG register
- *  eFuse apb2otp block7 data register9.
- */
-#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974)
-/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
-#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_S  0
-
-/** EFUSE_APB2OTP_BLK7_W10_REG register
- *  eFuse apb2otp block7 data register10.
- */
-#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978)
-/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
-#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_S  0
-
-/** EFUSE_APB2OTP_BLK7_W11_REG register
- *  eFuse apb2otp block7 data register11.
- */
-#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c)
-/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
-#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_S  0
-
-/** EFUSE_APB2OTP_BLK8_W1_REG register
- *  eFuse apb2otp block8 data register1.
- */
-#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980)
-/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
-#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_S  0
-
-/** EFUSE_APB2OTP_BLK8_W2_REG register
- *  eFuse apb2otp block8 data register2.
- */
-#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984)
-/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
-#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_S  0
-
-/** EFUSE_APB2OTP_BLK8_W3_REG register
- *  eFuse apb2otp block8 data register3.
- */
-#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988)
-/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
-#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_S  0
-
-/** EFUSE_APB2OTP_BLK8_W4_REG register
- *  eFuse apb2otp block8 data register4.
- */
-#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c)
-/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
-#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_S  0
-
-/** EFUSE_APB2OTP_BLK8_W5_REG register
- *  eFuse apb2otp block8 data register5.
- */
-#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990)
-/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
-#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_S  0
-
-/** EFUSE_APB2OTP_BLK8_W6_REG register
- *  eFuse apb2otp block8 data register6.
- */
-#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994)
-/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
-#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_S  0
-
-/** EFUSE_APB2OTP_BLK8_W7_REG register
- *  eFuse apb2otp block8 data register7.
- */
-#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998)
-/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
-#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_S  0
-
-/** EFUSE_APB2OTP_BLK8_W8_REG register
- *  eFuse apb2otp block8 data register8.
- */
-#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c)
-/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
-#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_S  0
-
-/** EFUSE_APB2OTP_BLK8_W9_REG register
- *  eFuse apb2otp block8 data register9.
- */
-#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0)
-/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
-#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_S  0
-
-/** EFUSE_APB2OTP_BLK8_W10_REG register
- *  eFuse apb2otp block8 data register10.
- */
-#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4)
-/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
-#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_S  0
-
-/** EFUSE_APB2OTP_BLK8_W11_REG register
- *  eFuse apb2otp block8 data register11.
- */
-#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8)
-/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
-#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_S  0
-
-/** EFUSE_APB2OTP_BLK9_W1_REG register
- *  eFuse apb2otp block9 data register1.
- */
-#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac)
-/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
-#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_S  0
-
-/** EFUSE_APB2OTP_BLK9_W2_REG register
- *  eFuse apb2otp block9 data register2.
- */
-#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0)
-/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
-#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_S  0
-
-/** EFUSE_APB2OTP_BLK9_W3_REG register
- *  eFuse apb2otp block9 data register3.
- */
-#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4)
-/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
-#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_S  0
-
-/** EFUSE_APB2OTP_BLK9_W4_REG register
- *  eFuse apb2otp block9 data register4.
- */
-#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8)
-/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
-#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_S  0
-
-/** EFUSE_APB2OTP_BLK9_W5_REG register
- *  eFuse apb2otp block9 data register5.
- */
-#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc)
-/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
-#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_S  0
-
-/** EFUSE_APB2OTP_BLK9_W6_REG register
- *  eFuse apb2otp block9 data register6.
- */
-#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0)
-/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
-#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_S  0
-
-/** EFUSE_APB2OTP_BLK9_W7_REG register
- *  eFuse apb2otp block9 data register7.
- */
-#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4)
-/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
-#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_S  0
-
-/** EFUSE_APB2OTP_BLK9_W8_REG register
- *  eFuse apb2otp block9 data register8.
- */
-#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8)
-/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
-#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_S  0
-
-/** EFUSE_APB2OTP_BLK9_W9_REG register
- *  eFuse apb2otp block9 data register9.
- */
-#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc)
-/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
-#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_S  0
-
-/** EFUSE_APB2OTP_BLK9_W10_REG register
- *  eFuse apb2otp block9 data register10.
- */
-#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0)
-/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
-#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_S  0
-
-/** EFUSE_APB2OTP_BLK9_W11_REG register
- *  eFuse apb2otp block9 data register11.
- */
-#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4)
-/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
-#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_S  0
-
-/** EFUSE_APB2OTP_BLK10_W1_REG register
- *  eFuse apb2otp block10 data register1.
- */
-#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8)
-/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
-#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_S  0
-
-/** EFUSE_APB2OTP_BLK10_W2_REG register
- *  eFuse apb2otp block10 data register2.
- */
-#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc)
-/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
-#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_S  0
-
-/** EFUSE_APB2OTP_BLK10_W3_REG register
- *  eFuse apb2otp block10 data register3.
- */
-#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0)
-/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
-#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_S  0
-
-/** EFUSE_APB2OTP_BLK10_W4_REG register
- *  eFuse apb2otp block10 data register4.
- */
-#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4)
-/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
-#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_S  0
-
-/** EFUSE_APB2OTP_BLK10_W5_REG register
- *  eFuse apb2otp block10 data register5.
- */
-#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8)
-/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
-#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_S  0
-
-/** EFUSE_APB2OTP_BLK10_W6_REG register
- *  eFuse apb2otp block10 data register6.
- */
-#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec)
-/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
-#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_S  0
-
-/** EFUSE_APB2OTP_BLK10_W7_REG register
- *  eFuse apb2otp block10 data register7.
- */
-#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0)
-/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
-#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_S  0
-
-/** EFUSE_APB2OTP_BLK10_W8_REG register
- *  eFuse apb2otp block10 data register8.
- */
-#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4)
-/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
-#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_S  0
-
-/** EFUSE_APB2OTP_BLK10_W9_REG register
- *  eFuse apb2otp block10 data register9.
- */
-#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8)
-/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
-#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_S  0
-
-/** EFUSE_APB2OTP_BLK10_W10_REG register
- *  eFuse apb2otp block10 data register10.
- */
-#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc)
-/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK19_W10_M  (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S)
-#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK19_W10_S  0
-
-/** EFUSE_APB2OTP_BLK10_W11_REG register
- *  eFuse apb2otp block10 data register11.
- */
-#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00)
-/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
-#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_S  0
-
-/** EFUSE_APB2OTP_EN_REG register
- *  eFuse apb2otp enable configuration register.
- */
-#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08)
-/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
- *  Apb2otp mode enable signal.
- */
-#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
-#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
-#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
-#define EFUSE_APB2OTP_APB2OTP_EN_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/efuse_mem_struct.h b/components/soc/esp32p4/include/soc/efuse_mem_struct.h
deleted file mode 100644
index 5db3b2ace5..0000000000
--- a/components/soc/esp32p4/include/soc/efuse_mem_struct.h
+++ /dev/null
@@ -1,4449 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: ******** Registers */
-/** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled. 1: Disabled. 0 Enabled.
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t rd_dis:7;
-        /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0;
-         *  Enable usb device exchange pins of D+ and D-.
-         */
-        uint32_t usb_device_exchg_pins:1;
-        /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0;
-         *  Enable usb otg11 exchange pins of D+ and D-.
-         */
-        uint32_t usb_otg11_exchg_pins:1;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** powerglitch_en : RO; bitpos: [10]; default: 0;
-         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
-         */
-        uint32_t powerglitch_en:1;
-        uint32_t reserved_11:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
-         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
-         *  boot_mode_download.
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
-         *  enabled.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode). 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        uint32_t reserved_21:4;
-        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
-         *  TBD
-         */
-        uint32_t usb_phy_sel:1;
-        /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0;
-         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
-         *  of 1 is valid.
-         */
-        uint32_t km_huk_gen_state_low:6;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  BLOCK0 data register 2.
- */
-typedef union {
-    struct {
-        /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0;
-         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
-         *  of 1 is valid.
-         */
-        uint32_t km_huk_gen_state_high:3;
-        /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0;
-         *  Set bits to control key manager random number switch cycle. 0: control by register.
-         *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
-         */
-        uint32_t km_rnd_switch_cycle:2;
-        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
-         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
-         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
-         */
-        uint32_t km_deploy_only_once:4;
-        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
-         *  Set each bit to control whether corresponding key must come from key manager.. 1 is
-         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
-         */
-        uint32_t force_use_key_manager_key:4;
-        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
-         *  Set this bit to disable software written init key, and force use efuse_init_key.
-         */
-        uint32_t force_disable_sw_init_key:1;
-        /** xts_key_length_256 : RO; bitpos: [14]; default: 0;
-         *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
-         */
-        uint32_t xts_key_length_256:1;
-        uint32_t reserved_15:1;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
-         *  selected. 0: not selected.
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
-         *  1: enabled. Even number of 1: disabled.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Represents the purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Represents the purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  BLOCK0 data register 3.
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
-         */
-        uint32_t sec_dpa_level:2;
-        /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0;
-         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
-         *  0: not force used.
-         */
-        uint32_t ecdsa_enable_soft_k:1;
-        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
-         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
-         */
-        uint32_t crypt_dpa_enable:1;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        uint32_t reserved_22:1;
-        /** flash_type : RO; bitpos: [23]; default: 0;
-         *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
-         */
-        uint32_t flash_type:1;
-        /** flash_page_size : RO; bitpos: [25:24]; default: 0;
-         *  Set flash page size.
-         */
-        uint32_t flash_page_size:2;
-        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
-         *  Set this bit to enable ecc for flash boot.
-         */
-        uint32_t flash_ecc_en:1;
-        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
-         *  Set this bit to disable download via USB-OTG.
-         */
-        uint32_t dis_usb_otg_download_mode:1;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
-         *  is 2 times the programmed value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  BLOCK0 data register 4.
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
-         *  0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** lock_km_key : RO; bitpos: [3]; default: 0;
-         *  TBD
-         */
-        uint32_t lock_km_key:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
-         *  disabled.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Represents the type of UART printing. 00: force enable printing. 01: enable
-         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
-         *  at high level. 11: force disable printing.
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [8]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
-         *  forced. 0:not forced.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [24:9]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
-         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** hys_en_pad : RO; bitpos: [26]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
-         *  enabled. 0:disabled.
-         */
-        uint32_t hys_en_pad:1;
-        /** dcdc_vset : RO; bitpos: [31:27]; default: 0;
-         *  Set the dcdc voltage default.
-         */
-        uint32_t dcdc_vset:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  BLOCK0 data register 5.
- */
-typedef union {
-    struct {
-        /** 0pxa_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
-         *  TBD
-         */
-        uint32_t rd_0pxa_tieh_sel_0:2;
-        /** 0pxa_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
-         *  TBD.
-         */
-        uint32_t rd_0pxa_tieh_sel_1:2;
-        /** 0pxa_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
-         *  TBD.
-         */
-        uint32_t rd_0pxa_tieh_sel_2:2;
-        /** 0pxa_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
-         *  TBD.
-         */
-        uint32_t rd_0pxa_tieh_sel_3:2;
-        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
-         *  TBD.
-         */
-        uint32_t km_disable_deploy_mode:4;
-        uint32_t reserved_12:6;
-        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
-         *  HP system power source select. 0:LDO. 1: DCDC.
-         */
-        uint32_t hp_pwr_src_sel:1;
-        /** dcdc_vset_en : RO; bitpos: [19]; default: 0;
-         *  Select dcdc vset use efuse_dcdc_vset.
-         */
-        uint32_t dcdc_vset_en:1;
-        /** dis_wdt : RO; bitpos: [20]; default: 0;
-         *  Set this bit to disable watch dog.
-         */
-        uint32_t dis_wdt:1;
-        /** dis_swd : RO; bitpos: [21]; default: 0;
-         *  Set this bit to disable super-watchdog.
-         */
-        uint32_t dis_swd:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-/** Type of rd_mac_sys_0 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the low 32 bits of MAC address.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_0_reg_t;
-
-/** Type of rd_mac_sys_1 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Stores the high 16 bits of MAC address.
-         */
-        uint32_t mac_1:16;
-        /** mac_ext : RO; bitpos: [31:16]; default: 0;
-         *  Stores the extended bits of MAC address.
-         */
-        uint32_t mac_ext:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_1_reg_t;
-
-/** Type of rd_mac_sys_2 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_1:14;
-        /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_0:18;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_2_reg_t;
-
-/** Type of rd_mac_sys_3 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_2:18;
-        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
-         *  Stores the first 14 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_0:14;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_3_reg_t;
-
-/** Type of rd_mac_sys_4 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_1:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_4_reg_t;
-
-/** Type of rd_mac_sys_5 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_5_reg_t;
-
-/** Type of rd_sys_part1_data0 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-/** Type of rd_usr_data0 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-/** Type of rd_key0_data0 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-/** Type of rd_key1_data0 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-/** Type of rd_key2_data0 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-/** Type of rd_key3_data0 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-/** Type of rd_key4_data0 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-/** Type of rd_key5_data0 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-/** Type of rd_sys_part2_data0 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-/** Type of rd_repeat_err0 register
- *  Programming error record register 0 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Indicates a programming error of RD_DIS.
-         */
-        uint32_t rd_dis_err:7;
-        /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0;
-         *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
-         */
-        uint32_t dis_usb_device_exchg_pins_err:1;
-        /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
-         */
-        uint32_t dis_usb_otg11_exchg_pins_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Indicates a programming error of DIS_USB_JTAG.
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
-         *  Indicates a programming error of POWERGLITCH_EN.
-         */
-        uint32_t powerglitch_en_err:1;
-        uint32_t reserved_11:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of DIS_TWAI.
-         */
-        uint32_t dis_twai_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Indicates a programming error of JTAG_SEL_ENABLE.
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Indicates a programming error of SOFT_DIS_JTAG.
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DIS_PAD_JTAG.
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        uint32_t reserved_21:4;
-        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of USB_PHY_SEL.
-         */
-        uint32_t usb_phy_sel_err:1;
-        /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0;
-         *  Indicates a programming error of HUK_GEN_STATE_LOW.
-         */
-        uint32_t huk_gen_state_low_err:6;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err0_reg_t;
-
-/** Type of rd_repeat_err1 register
- *  Programming error record register 1 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0;
-         *  Indicates a programming error of HUK_GEN_STATE_HIGH.
-         */
-        uint32_t km_huk_gen_state_high_err:3;
-        /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0;
-         *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
-         */
-        uint32_t km_rnd_switch_cycle_err:2;
-        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
-         *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
-         */
-        uint32_t km_deploy_only_once_err:4;
-        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
-         *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
-         */
-        uint32_t force_use_key_manager_key_err:4;
-        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
-         */
-        uint32_t force_disable_sw_init_key_err:1;
-        /** xts_key_length_256_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of XTS_KEY_LENGTH_256.
-         */
-        uint32_t xts_key_length_256_err:1;
-        uint32_t reserved_15:1;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of WDT_DELAY_SEL.
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_0.
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_1.
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err1_reg_t;
-
-/** Type of rd_repeat_err2 register
- *  Programming error record register 2 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_2.
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_3.
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_4.
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_5.
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of SEC_DPA_LEVEL.
-         */
-        uint32_t sec_dpa_level_err:2;
-        /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0;
-         *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
-         */
-        uint32_t ecdsa_enable_soft_k_err:1;
-        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of CRYPT_DPA_ENABLE.
-         */
-        uint32_t crypt_dpa_enable_err:1;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_EN.
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        uint32_t reserved_22:1;
-        /** flash_type_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of FLASH_TYPE.
-         */
-        uint32_t flash_type_err:1;
-        /** flash_page_size_err : RO; bitpos: [25:24]; default: 0;
-         *  Indicates a programming error of FLASH_PAGE_SIZE.
-         */
-        uint32_t flash_page_size_err:2;
-        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of FLASH_ECC_EN.
-         */
-        uint32_t flash_ecc_en_err:1;
-        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
-         *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
-         */
-        uint32_t dis_usb_otg_download_mode_err:1;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of FLASH_TPUW.
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err2_reg_t;
-
-/** Type of rd_repeat_err3 register
- *  Programming error record register 3 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Indicates a programming error of DIS_DIRECT_BOOT.
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print_err:1;
-        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
-         *  TBD
-         */
-        uint32_t lock_km_key_err:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of UART_PRINT_CONTROL.
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of FORCE_SEND_RESUME.
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
-         *  Indicates a programming error of SECURE VERSION.
-         */
-        uint32_t secure_version_err:16;
-        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
-         */
-        uint32_t secure_boot_disable_fast_wake_err:1;
-        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of HYS_EN_PAD.
-         */
-        uint32_t hys_en_pad_err:1;
-        /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0;
-         *  Indicates a programming error of DCDC_VSET.
-         */
-        uint32_t dcdc_vset_err:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err3_reg_t;
-
-/** Type of rd_repeat_err4 register
- *  Programming error record register 4 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** 0pxa_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_0.
-         */
-        uint32_t rd_0pxa_tieh_sel_0_err:2;
-        /** 0pxa_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_1.
-         */
-        uint32_t rd_0pxa_tieh_sel_1_err:2;
-        /** 0pxa_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_2.
-         */
-        uint32_t rd_0pxa_tieh_sel_2_err:2;
-        /** 0pxa_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_3.
-         */
-        uint32_t rd_0pxa_tieh_sel_3_err:2;
-        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
-         *  TBD.
-         */
-        uint32_t km_disable_deploy_mode_err:4;
-        /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0;
-         *  Indicates a programming error of USB_DEVICE_DREFL.
-         */
-        uint32_t usb_device_drefl_err:2;
-        /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0;
-         *  Indicates a programming error of USB_OTG11_DREFL.
-         */
-        uint32_t usb_otg11_drefl_err:2;
-        uint32_t reserved_16:2;
-        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
-         *  Indicates a programming error of HP_PWR_SRC_SEL.
-         */
-        uint32_t hp_pwr_src_sel_err:1;
-        /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DCDC_VSET_EN.
-         */
-        uint32_t dcdc_vset_en_err:1;
-        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_WDT.
-         */
-        uint32_t dis_wdt_err:1;
-        /** dis_swd_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of DIS_SWD.
-         */
-        uint32_t dis_swd_err:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err4_reg_t;
-
-/** Type of rd_rs_err0 register
- *  Programming error record register 0 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t mac_sys_err_num:3;
-        /** mac_sys_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t mac_sys_fail:1;
-        /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part1_err_num:3;
-        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part1_fail:1;
-        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t usr_data_err_num:3;
-        /** usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the user data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t usr_data_fail:1;
-        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key0_err_num:3;
-        /** key0_fail : RO; bitpos: [15]; default: 0;
-         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
-         *  key0 failed and the number of error bytes is over 6.
-         */
-        uint32_t key0_fail:1;
-        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key1_err_num:3;
-        /** key1_fail : RO; bitpos: [19]; default: 0;
-         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
-         *  key1 failed and the number of error bytes is over 6.
-         */
-        uint32_t key1_fail:1;
-        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key2_err_num:3;
-        /** key2_fail : RO; bitpos: [23]; default: 0;
-         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
-         *  key2 failed and the number of error bytes is over 6.
-         */
-        uint32_t key2_fail:1;
-        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key3_err_num:3;
-        /** key3_fail : RO; bitpos: [27]; default: 0;
-         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
-         *  key3 failed and the number of error bytes is over 6.
-         */
-        uint32_t key3_fail:1;
-        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key4_err_num:3;
-        /** key4_fail : RO; bitpos: [31]; default: 0;
-         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
-         *  key4 failed and the number of error bytes is over 6.
-         */
-        uint32_t key4_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_err0_reg_t;
-
-/** Type of rd_rs_err1 register
- *  Programming error record register 1 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key5_err_num:3;
-        /** key5_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
-         *  key5 failed and the number of error bytes is over 6.
-         */
-        uint32_t key5_fail:1;
-        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part2_err_num:3;
-        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part2_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_err1_reg_t;
-
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuraiton register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
-         *  Configures which block to use for ECDSA key output.
-         */
-        uint32_t cfg_ecdsa_blk:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        uint32_t reserved_4:6;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 160;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-
-/** Group: EFUSE Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720720;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
-/** Type of apb2otp_wr_dis register
- *  eFuse apb2otp block0 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 write disable data.
-         */
-        uint32_t apb2otp_block0_wr_dis:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_wr_dis_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
-/** Type of apb2otp_blk0_backup1_w1 register
- *  eFuse apb2otp block0 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word1 data.
-         */
-        uint32_t apb2otp_block0_backup1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
-/** Type of apb2otp_blk0_backup1_w2 register
- *  eFuse apb2otp block0 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word2 data.
-         */
-        uint32_t apb2otp_block0_backup1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
-/** Type of apb2otp_blk0_backup1_w3 register
- *  eFuse apb2otp block0 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word3 data.
-         */
-        uint32_t apb2otp_block0_backup1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
-/** Type of apb2otp_blk0_backup1_w4 register
- *  eFuse apb2otp block0 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word4 data.
-         */
-        uint32_t apb2otp_block0_backup1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
-/** Type of apb2otp_blk0_backup1_w5 register
- *  eFuse apb2otp block0 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word5 data.
-         */
-        uint32_t apb2otp_block0_backup1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
-/** Type of apb2otp_blk0_backup2_w1 register
- *  eFuse apb2otp block0 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word1 data.
-         */
-        uint32_t apb2otp_block0_backup2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
-/** Type of apb2otp_blk0_backup2_w2 register
- *  eFuse apb2otp block0 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word2 data.
-         */
-        uint32_t apb2otp_block0_backup2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
-/** Type of apb2otp_blk0_backup2_w3 register
- *  eFuse apb2otp block0 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word3 data.
-         */
-        uint32_t apb2otp_block0_backup2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
-/** Type of apb2otp_blk0_backup2_w4 register
- *  eFuse apb2otp block0 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word4 data.
-         */
-        uint32_t apb2otp_block0_backup2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
-/** Type of apb2otp_blk0_backup2_w5 register
- *  eFuse apb2otp block0 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word5 data.
-         */
-        uint32_t apb2otp_block0_backup2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
-/** Type of apb2otp_blk0_backup3_w1 register
- *  eFuse apb2otp block0 data register12.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word1 data.
-         */
-        uint32_t apb2otp_block0_backup3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
-/** Type of apb2otp_blk0_backup3_w2 register
- *  eFuse apb2otp block0 data register13.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word2 data.
-         */
-        uint32_t apb2otp_block0_backup3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
-/** Type of apb2otp_blk0_backup3_w3 register
- *  eFuse apb2otp block0 data register14.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word3 data.
-         */
-        uint32_t apb2otp_block0_backup3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
-/** Type of apb2otp_blk0_backup3_w4 register
- *  eFuse apb2otp block0 data register15.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word4 data.
-         */
-        uint32_t apb2otp_block0_backup3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
-/** Type of apb2otp_blk0_backup3_w5 register
- *  eFuse apb2otp block0 data register16.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word5 data.
-         */
-        uint32_t apb2otp_block0_backup3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
-/** Type of apb2otp_blk0_backup4_w1 register
- *  eFuse apb2otp block0 data register17.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word1 data.
-         */
-        uint32_t apb2otp_block0_backup4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
-/** Type of apb2otp_blk0_backup4_w2 register
- *  eFuse apb2otp block0 data register18.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word2 data.
-         */
-        uint32_t apb2otp_block0_backup4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
-/** Type of apb2otp_blk0_backup4_w3 register
- *  eFuse apb2otp block0 data register19.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word3 data.
-         */
-        uint32_t apb2otp_block0_backup4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
-/** Type of apb2otp_blk0_backup4_w4 register
- *  eFuse apb2otp block0 data register20.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word4 data.
-         */
-        uint32_t apb2otp_block0_backup4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
-/** Type of apb2otp_blk0_backup4_w5 register
- *  eFuse apb2otp block0 data register21.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word5 data.
-         */
-        uint32_t apb2otp_block0_backup4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word1 Data */
-/** Type of apb2otp_blk1_w1 register
- *  eFuse apb2otp block1 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word1 data.
-         */
-        uint32_t apb2otp_block1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word2 Data */
-/** Type of apb2otp_blk1_w2 register
- *  eFuse apb2otp block1 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word2 data.
-         */
-        uint32_t apb2otp_block1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word3 Data */
-/** Type of apb2otp_blk1_w3 register
- *  eFuse apb2otp block1 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word3 data.
-         */
-        uint32_t apb2otp_block1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word4 Data */
-/** Type of apb2otp_blk1_w4 register
- *  eFuse apb2otp block1 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word4 data.
-         */
-        uint32_t apb2otp_block1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word5 Data */
-/** Type of apb2otp_blk1_w5 register
- *  eFuse apb2otp block1 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word5 data.
-         */
-        uint32_t apb2otp_block1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word6 Data */
-/** Type of apb2otp_blk1_w6 register
- *  eFuse apb2otp block1 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word6 data.
-         */
-        uint32_t apb2otp_block1_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word7 Data */
-/** Type of apb2otp_blk1_w7 register
- *  eFuse apb2otp block1 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word7 data.
-         */
-        uint32_t apb2otp_block1_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word8 Data */
-/** Type of apb2otp_blk1_w8 register
- *  eFuse apb2otp block1 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word8 data.
-         */
-        uint32_t apb2otp_block1_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word9 Data */
-/** Type of apb2otp_blk1_w9 register
- *  eFuse apb2otp block1 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word9 data.
-         */
-        uint32_t apb2otp_block1_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word1 Data */
-/** Type of apb2otp_blk2_w1 register
- *  eFuse apb2otp block2 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word1 data.
-         */
-        uint32_t apb2otp_block2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word2 Data */
-/** Type of apb2otp_blk2_w2 register
- *  eFuse apb2otp block2 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word2 data.
-         */
-        uint32_t apb2otp_block2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word3 Data */
-/** Type of apb2otp_blk2_w3 register
- *  eFuse apb2otp block2 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word3 data.
-         */
-        uint32_t apb2otp_block2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word4 Data */
-/** Type of apb2otp_blk2_w4 register
- *  eFuse apb2otp block2 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word4 data.
-         */
-        uint32_t apb2otp_block2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word5 Data */
-/** Type of apb2otp_blk2_w5 register
- *  eFuse apb2otp block2 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word5 data.
-         */
-        uint32_t apb2otp_block2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word6 Data */
-/** Type of apb2otp_blk2_w6 register
- *  eFuse apb2otp block2 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word6 data.
-         */
-        uint32_t apb2otp_block2_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word7 Data */
-/** Type of apb2otp_blk2_w7 register
- *  eFuse apb2otp block2 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word7 data.
-         */
-        uint32_t apb2otp_block2_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word8 Data */
-/** Type of apb2otp_blk2_w8 register
- *  eFuse apb2otp block2 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word8 data.
-         */
-        uint32_t apb2otp_block2_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word9 Data */
-/** Type of apb2otp_blk2_w9 register
- *  eFuse apb2otp block2 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word9 data.
-         */
-        uint32_t apb2otp_block2_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word10 Data */
-/** Type of apb2otp_blk2_w10 register
- *  eFuse apb2otp block2 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word10 data.
-         */
-        uint32_t apb2otp_block2_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word11 Data */
-/** Type of apb2otp_blk2_w11 register
- *  eFuse apb2otp block2 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word11 data.
-         */
-        uint32_t apb2otp_block2_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w11_reg_t;
-
-/** Type of apb2otp_blk10_w11 register
- *  eFuse apb2otp block10 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word11 data.
-         */
-        uint32_t apb2otp_block10_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word1 Data */
-/** Type of apb2otp_blk3_w1 register
- *  eFuse apb2otp block3 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word1 data.
-         */
-        uint32_t apb2otp_block3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word2 Data */
-/** Type of apb2otp_blk3_w2 register
- *  eFuse apb2otp block3 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word2 data.
-         */
-        uint32_t apb2otp_block3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word3 Data */
-/** Type of apb2otp_blk3_w3 register
- *  eFuse apb2otp block3 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word3 data.
-         */
-        uint32_t apb2otp_block3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word4 Data */
-/** Type of apb2otp_blk3_w4 register
- *  eFuse apb2otp block3 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word4 data.
-         */
-        uint32_t apb2otp_block3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word5 Data */
-/** Type of apb2otp_blk3_w5 register
- *  eFuse apb2otp block3 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word5 data.
-         */
-        uint32_t apb2otp_block3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word6 Data */
-/** Type of apb2otp_blk3_w6 register
- *  eFuse apb2otp block3 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word6 data.
-         */
-        uint32_t apb2otp_block3_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word7 Data */
-/** Type of apb2otp_blk3_w7 register
- *  eFuse apb2otp block3 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word7 data.
-         */
-        uint32_t apb2otp_block3_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word8 Data */
-/** Type of apb2otp_blk3_w8 register
- *  eFuse apb2otp block3 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word8 data.
-         */
-        uint32_t apb2otp_block3_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word9 Data */
-/** Type of apb2otp_blk3_w9 register
- *  eFuse apb2otp block3 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word9 data.
-         */
-        uint32_t apb2otp_block3_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word10 Data */
-/** Type of apb2otp_blk3_w10 register
- *  eFuse apb2otp block3 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word10 data.
-         */
-        uint32_t apb2otp_block3_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word11 Data */
-/** Type of apb2otp_blk3_w11 register
- *  eFuse apb2otp block3 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word11 data.
-         */
-        uint32_t apb2otp_block3_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word1 Data */
-/** Type of apb2otp_blk4_w1 register
- *  eFuse apb2otp block4 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word1 data.
-         */
-        uint32_t apb2otp_block4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word2 Data */
-/** Type of apb2otp_blk4_w2 register
- *  eFuse apb2otp block4 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word2 data.
-         */
-        uint32_t apb2otp_block4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word3 Data */
-/** Type of apb2otp_blk4_w3 register
- *  eFuse apb2otp block4 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word3 data.
-         */
-        uint32_t apb2otp_block4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word4 Data */
-/** Type of apb2otp_blk4_w4 register
- *  eFuse apb2otp block4 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word4 data.
-         */
-        uint32_t apb2otp_block4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word5 Data */
-/** Type of apb2otp_blk4_w5 register
- *  eFuse apb2otp block4 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word5 data.
-         */
-        uint32_t apb2otp_block4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word6 Data */
-/** Type of apb2otp_blk4_w6 register
- *  eFuse apb2otp block4 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word6 data.
-         */
-        uint32_t apb2otp_block4_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word7 Data */
-/** Type of apb2otp_blk4_w7 register
- *  eFuse apb2otp block4 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word7 data.
-         */
-        uint32_t apb2otp_block4_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word8 Data */
-/** Type of apb2otp_blk4_w8 register
- *  eFuse apb2otp block4 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word8 data.
-         */
-        uint32_t apb2otp_block4_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word9 Data */
-/** Type of apb2otp_blk4_w9 register
- *  eFuse apb2otp block4 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word9 data.
-         */
-        uint32_t apb2otp_block4_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word10 Data */
-/** Type of apb2otp_blk4_w10 register
- *  eFuse apb2otp block4 data registe10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word10 data.
-         */
-        uint32_t apb2otp_block4_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word11 Data */
-/** Type of apb2otp_blk4_w11 register
- *  eFuse apb2otp block4 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word11 data.
-         */
-        uint32_t apb2otp_block4_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word1 Data */
-/** Type of apb2otp_blk5_w1 register
- *  eFuse apb2otp block5 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word1 data.
-         */
-        uint32_t apb2otp_block5_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word2 Data */
-/** Type of apb2otp_blk5_w2 register
- *  eFuse apb2otp block5 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word2 data.
-         */
-        uint32_t apb2otp_block5_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word3 Data */
-/** Type of apb2otp_blk5_w3 register
- *  eFuse apb2otp block5 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word3 data.
-         */
-        uint32_t apb2otp_block5_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word4 Data */
-/** Type of apb2otp_blk5_w4 register
- *  eFuse apb2otp block5 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word4 data.
-         */
-        uint32_t apb2otp_block5_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word5 Data */
-/** Type of apb2otp_blk5_w5 register
- *  eFuse apb2otp block5 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word5 data.
-         */
-        uint32_t apb2otp_block5_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word6 Data */
-/** Type of apb2otp_blk5_w6 register
- *  eFuse apb2otp block5 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word6 data.
-         */
-        uint32_t apb2otp_block5_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word7 Data */
-/** Type of apb2otp_blk5_w7 register
- *  eFuse apb2otp block5 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word7 data.
-         */
-        uint32_t apb2otp_block5_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word8 Data */
-/** Type of apb2otp_blk5_w8 register
- *  eFuse apb2otp block5 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word8 data.
-         */
-        uint32_t apb2otp_block5_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word9 Data */
-/** Type of apb2otp_blk5_w9 register
- *  eFuse apb2otp block5 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word9 data.
-         */
-        uint32_t apb2otp_block5_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word10 Data */
-/** Type of apb2otp_blk5_w10 register
- *  eFuse apb2otp block5 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word10 data.
-         */
-        uint32_t apb2otp_block5_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word11 Data */
-/** Type of apb2otp_blk5_w11 register
- *  eFuse apb2otp block5 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word11 data.
-         */
-        uint32_t apb2otp_block5_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word1 Data */
-/** Type of apb2otp_blk6_w1 register
- *  eFuse apb2otp block6 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word1 data.
-         */
-        uint32_t apb2otp_block6_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word2 Data */
-/** Type of apb2otp_blk6_w2 register
- *  eFuse apb2otp block6 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word2 data.
-         */
-        uint32_t apb2otp_block6_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word3 Data */
-/** Type of apb2otp_blk6_w3 register
- *  eFuse apb2otp block6 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word3 data.
-         */
-        uint32_t apb2otp_block6_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word4 Data */
-/** Type of apb2otp_blk6_w4 register
- *  eFuse apb2otp block6 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word4 data.
-         */
-        uint32_t apb2otp_block6_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word5 Data */
-/** Type of apb2otp_blk6_w5 register
- *  eFuse apb2otp block6 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word5 data.
-         */
-        uint32_t apb2otp_block6_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word6 Data */
-/** Type of apb2otp_blk6_w6 register
- *  eFuse apb2otp block6 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word6 data.
-         */
-        uint32_t apb2otp_block6_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word7 Data */
-/** Type of apb2otp_blk6_w7 register
- *  eFuse apb2otp block6 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word7 data.
-         */
-        uint32_t apb2otp_block6_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word8 Data */
-/** Type of apb2otp_blk6_w8 register
- *  eFuse apb2otp block6 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word8 data.
-         */
-        uint32_t apb2otp_block6_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word9 Data */
-/** Type of apb2otp_blk6_w9 register
- *  eFuse apb2otp block6 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word9 data.
-         */
-        uint32_t apb2otp_block6_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word10 Data */
-/** Type of apb2otp_blk6_w10 register
- *  eFuse apb2otp block6 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word10 data.
-         */
-        uint32_t apb2otp_block6_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word11 Data */
-/** Type of apb2otp_blk6_w11 register
- *  eFuse apb2otp block6 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word11 data.
-         */
-        uint32_t apb2otp_block6_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word1 Data */
-/** Type of apb2otp_blk7_w1 register
- *  eFuse apb2otp block7 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word1 data.
-         */
-        uint32_t apb2otp_block7_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word2 Data */
-/** Type of apb2otp_blk7_w2 register
- *  eFuse apb2otp block7 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word2 data.
-         */
-        uint32_t apb2otp_block7_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word3 Data */
-/** Type of apb2otp_blk7_w3 register
- *  eFuse apb2otp block7 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word3 data.
-         */
-        uint32_t apb2otp_block7_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word4 Data */
-/** Type of apb2otp_blk7_w4 register
- *  eFuse apb2otp block7 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word4 data.
-         */
-        uint32_t apb2otp_block7_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word5 Data */
-/** Type of apb2otp_blk7_w5 register
- *  eFuse apb2otp block7 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word5 data.
-         */
-        uint32_t apb2otp_block7_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word6 Data */
-/** Type of apb2otp_blk7_w6 register
- *  eFuse apb2otp block7 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word6 data.
-         */
-        uint32_t apb2otp_block7_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word7 Data */
-/** Type of apb2otp_blk7_w7 register
- *  eFuse apb2otp block7 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word7 data.
-         */
-        uint32_t apb2otp_block7_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word8 Data */
-/** Type of apb2otp_blk7_w8 register
- *  eFuse apb2otp block7 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word8 data.
-         */
-        uint32_t apb2otp_block7_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word9 Data */
-/** Type of apb2otp_blk7_w9 register
- *  eFuse apb2otp block7 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word9 data.
-         */
-        uint32_t apb2otp_block7_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word10 Data */
-/** Type of apb2otp_blk7_w10 register
- *  eFuse apb2otp block7 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word10 data.
-         */
-        uint32_t apb2otp_block7_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word11 Data */
-/** Type of apb2otp_blk7_w11 register
- *  eFuse apb2otp block7 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word11 data.
-         */
-        uint32_t apb2otp_block7_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word1 Data */
-/** Type of apb2otp_blk8_w1 register
- *  eFuse apb2otp block8 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word1 data.
-         */
-        uint32_t apb2otp_block8_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word2 Data */
-/** Type of apb2otp_blk8_w2 register
- *  eFuse apb2otp block8 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word2 data.
-         */
-        uint32_t apb2otp_block8_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word3 Data */
-/** Type of apb2otp_blk8_w3 register
- *  eFuse apb2otp block8 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word3 data.
-         */
-        uint32_t apb2otp_block8_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word4 Data */
-/** Type of apb2otp_blk8_w4 register
- *  eFuse apb2otp block8 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word4 data.
-         */
-        uint32_t apb2otp_block8_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word5 Data */
-/** Type of apb2otp_blk8_w5 register
- *  eFuse apb2otp block8 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word5 data.
-         */
-        uint32_t apb2otp_block8_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word6 Data */
-/** Type of apb2otp_blk8_w6 register
- *  eFuse apb2otp block8 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word6 data.
-         */
-        uint32_t apb2otp_block8_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word7 Data */
-/** Type of apb2otp_blk8_w7 register
- *  eFuse apb2otp block8 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word7 data.
-         */
-        uint32_t apb2otp_block8_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word8 Data */
-/** Type of apb2otp_blk8_w8 register
- *  eFuse apb2otp block8 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word8 data.
-         */
-        uint32_t apb2otp_block8_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word9 Data */
-/** Type of apb2otp_blk8_w9 register
- *  eFuse apb2otp block8 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word9 data.
-         */
-        uint32_t apb2otp_block8_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word10 Data */
-/** Type of apb2otp_blk8_w10 register
- *  eFuse apb2otp block8 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word10 data.
-         */
-        uint32_t apb2otp_block8_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word11 Data */
-/** Type of apb2otp_blk8_w11 register
- *  eFuse apb2otp block8 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word11 data.
-         */
-        uint32_t apb2otp_block8_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word1 Data */
-/** Type of apb2otp_blk9_w1 register
- *  eFuse apb2otp block9 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word1 data.
-         */
-        uint32_t apb2otp_block9_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word2 Data */
-/** Type of apb2otp_blk9_w2 register
- *  eFuse apb2otp block9 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word2 data.
-         */
-        uint32_t apb2otp_block9_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word3 Data */
-/** Type of apb2otp_blk9_w3 register
- *  eFuse apb2otp block9 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word3 data.
-         */
-        uint32_t apb2otp_block9_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word4 Data */
-/** Type of apb2otp_blk9_w4 register
- *  eFuse apb2otp block9 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word4 data.
-         */
-        uint32_t apb2otp_block9_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word5 Data */
-/** Type of apb2otp_blk9_w5 register
- *  eFuse apb2otp block9 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word5 data.
-         */
-        uint32_t apb2otp_block9_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word6 Data */
-/** Type of apb2otp_blk9_w6 register
- *  eFuse apb2otp block9 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word6 data.
-         */
-        uint32_t apb2otp_block9_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word7 Data */
-/** Type of apb2otp_blk9_w7 register
- *  eFuse apb2otp block9 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word7 data.
-         */
-        uint32_t apb2otp_block9_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word8 Data */
-/** Type of apb2otp_blk9_w8 register
- *  eFuse apb2otp block9 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word8 data.
-         */
-        uint32_t apb2otp_block9_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word9 Data */
-/** Type of apb2otp_blk9_w9 register
- *  eFuse apb2otp block9 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word9 data.
-         */
-        uint32_t apb2otp_block9_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word10 Data */
-/** Type of apb2otp_blk9_w10 register
- *  eFuse apb2otp block9 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word10 data.
-         */
-        uint32_t apb2otp_block9_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word11 Data */
-/** Type of apb2otp_blk9_w11 register
- *  eFuse apb2otp block9 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word11 data.
-         */
-        uint32_t apb2otp_block9_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word1 Data */
-/** Type of apb2otp_blk10_w1 register
- *  eFuse apb2otp block10 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word1 data.
-         */
-        uint32_t apb2otp_block10_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word2 Data */
-/** Type of apb2otp_blk10_w2 register
- *  eFuse apb2otp block10 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word2 data.
-         */
-        uint32_t apb2otp_block10_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word3 Data */
-/** Type of apb2otp_blk10_w3 register
- *  eFuse apb2otp block10 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word3 data.
-         */
-        uint32_t apb2otp_block10_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word4 Data */
-/** Type of apb2otp_blk10_w4 register
- *  eFuse apb2otp block10 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word4 data.
-         */
-        uint32_t apb2otp_block10_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word5 Data */
-/** Type of apb2otp_blk10_w5 register
- *  eFuse apb2otp block10 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word5 data.
-         */
-        uint32_t apb2otp_block10_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word6 Data */
-/** Type of apb2otp_blk10_w6 register
- *  eFuse apb2otp block10 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word6 data.
-         */
-        uint32_t apb2otp_block10_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word7 Data */
-/** Type of apb2otp_blk10_w7 register
- *  eFuse apb2otp block10 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word7 data.
-         */
-        uint32_t apb2otp_block10_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word8 Data */
-/** Type of apb2otp_blk10_w8 register
- *  eFuse apb2otp block10 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word8 data.
-         */
-        uint32_t apb2otp_block10_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word9 Data */
-/** Type of apb2otp_blk10_w9 register
- *  eFuse apb2otp block10 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word9 data.
-         */
-        uint32_t apb2otp_block10_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word10 Data */
-/** Type of apb2otp_blk10_w10 register
- *  eFuse apb2otp block10 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word10 data.
-         */
-        uint32_t apb2otp_block19_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Function Enable Singal */
-/** Type of apb2otp_en register
- *  eFuse apb2otp enable configuration register.
- */
-typedef union {
-    struct {
-        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
-         *  Apb2otp mode enable signal.
-         */
-        uint32_t apb2otp_apb2otp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} efuse_apb2otp_en_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
-    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
-    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
-    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
-    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
-    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
-    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
-    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
-    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
-    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
-    uint32_t reserved_190[12];
-    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
-    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    volatile efuse_date_reg_t date;
-    uint32_t reserved_200[384];
-    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
-    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
-    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
-    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
-    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
-    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
-    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
-    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
-    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
-    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
-    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
-    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
-    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
-    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
-    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
-    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
-    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
-    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
-    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
-    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
-    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
-    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
-    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
-    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
-    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
-    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
-    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
-    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
-    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
-    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
-    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
-    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
-    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
-    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
-    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
-    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
-    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
-    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
-    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
-    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
-    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
-    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
-    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
-    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
-    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
-    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
-    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
-    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
-    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
-    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
-    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
-    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
-    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
-    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
-    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
-    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
-    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
-    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
-    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
-    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
-    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
-    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
-    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
-    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
-    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
-    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
-    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
-    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
-    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
-    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
-    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
-    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
-    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
-    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
-    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
-    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
-    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
-    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
-    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
-    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
-    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
-    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
-    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
-    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
-    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
-    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
-    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
-    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
-    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
-    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
-    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
-    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
-    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
-    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
-    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
-    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
-    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
-    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
-    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
-    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
-    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
-    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
-    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
-    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
-    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
-    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
-    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
-    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
-    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
-    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
-    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
-    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
-    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
-    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
-    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
-    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
-    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
-    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
-    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
-    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
-    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
-    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
-    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
-    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
-    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
-    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
-    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
-    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
-    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
-    uint32_t reserved_a04;
-    volatile efuse_apb2otp_en_reg_t apb2otp_en;
-} efuse_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/efuse_reg.h b/components/soc/esp32p4/include/soc/efuse_reg.h
index faed73b495..f095267388 100644
--- a/components/soc/esp32p4/include/soc/efuse_reg.h
+++ b/components/soc/esp32p4/include/soc/efuse_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,3079 +10,4133 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
+
 #define EFUSE_READ_OP_CODE 0x5aa5
 #define EFUSE_WRITE_OP_CODE 0x5a5a
-#define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0)
-/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 0th 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_0    0xFFFFFFFF
-#define EFUSE_PGM_DATA_0_M  ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S))
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFF
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_0_S  0
 
-#define EFUSE_PGM_DATA1_REG          (DR_REG_EFUSE_BASE + 0x4)
-/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 1st 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_1    0xFFFFFFFF
-#define EFUSE_PGM_DATA_1_M  ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S))
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFF
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_1_S  0
 
-#define EFUSE_PGM_DATA2_REG          (DR_REG_EFUSE_BASE + 0x8)
-/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 2nd 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_2    0xFFFFFFFF
-#define EFUSE_PGM_DATA_2_M  ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S))
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFF
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_2_S  0
 
-#define EFUSE_PGM_DATA3_REG          (DR_REG_EFUSE_BASE + 0xC)
-/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 3rd 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_3    0xFFFFFFFF
-#define EFUSE_PGM_DATA_3_M  ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S))
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFF
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_3_S  0
 
-#define EFUSE_PGM_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10)
-/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 4th 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_4    0xFFFFFFFF
-#define EFUSE_PGM_DATA_4_M  ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S))
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFF
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_4_S  0
 
-#define EFUSE_PGM_DATA5_REG          (DR_REG_EFUSE_BASE + 0x14)
-/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 5th 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_5    0xFFFFFFFF
-#define EFUSE_PGM_DATA_5_M  ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S))
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFF
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_5_S  0
 
-#define EFUSE_PGM_DATA6_REG          (DR_REG_EFUSE_BASE + 0x18)
-/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 6th 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_6    0xFFFFFFFF
-#define EFUSE_PGM_DATA_6_M  ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S))
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFF
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_6_S  0
 
-#define EFUSE_PGM_DATA7_REG          (DR_REG_EFUSE_BASE + 0x1C)
-/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 7th 32-bit data to be programmed..*/
-#define EFUSE_PGM_DATA_7    0xFFFFFFFF
-#define EFUSE_PGM_DATA_7_M  ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S))
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFF
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
 #define EFUSE_PGM_DATA_7_S  0
 
-#define EFUSE_PGM_CHECK_VALUE0_REG          (DR_REG_EFUSE_BASE + 0x20)
-/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 0th 32-bit RS code to be programmed..*/
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFF
-#define EFUSE_PGM_RS_DATA_0_M  ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S))
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFF
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
 #define EFUSE_PGM_RS_DATA_0_S  0
 
-#define EFUSE_PGM_CHECK_VALUE1_REG          (DR_REG_EFUSE_BASE + 0x24)
-/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 1st 32-bit RS code to be programmed..*/
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFF
-#define EFUSE_PGM_RS_DATA_1_M  ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S))
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFF
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
 #define EFUSE_PGM_RS_DATA_1_S  0
 
-#define EFUSE_PGM_CHECK_VALUE2_REG          (DR_REG_EFUSE_BASE + 0x28)
-/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Configures the 2nd 32-bit RS code to be programmed..*/
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFF
-#define EFUSE_PGM_RS_DATA_2_M  ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S))
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFF
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
 #define EFUSE_PGM_RS_DATA_2_S  0
 
-#define EFUSE_RD_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x2C)
-/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Represents whether programming of individual eFuse memory bit is disabled or ena
-bled. 1: Disabled. 0 Enabled..*/
-#define EFUSE_WR_DIS    0xFFFFFFFF
-#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
-#define EFUSE_WR_DIS_V  0xFFFFFFFF
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled. 1: Disabled. 0 Enabled.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
 #define EFUSE_WR_DIS_S  0
 
-#define EFUSE_RD_REPEAT_DATA0_REG          (DR_REG_EFUSE_BASE + 0x30)
-/* EFUSE_KM_HUK_GEN_STATE_LOW : RO ;bitpos:[31:26] ;default: 6'h0 ; */
-/*description: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, ev
-en of 1 is valid..*/
-#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003F
-#define EFUSE_KM_HUK_GEN_STATE_LOW_M  ((EFUSE_KM_HUK_GEN_STATE_LOW_V)<<(EFUSE_KM_HUK_GEN_STATE_LOW_S))
-#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x3F
-#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
-/* EFUSE_USB_PHY_SEL : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: TBD.*/
-#define EFUSE_USB_PHY_SEL    (BIT(25))
-#define EFUSE_USB_PHY_SEL_M  (BIT(25))
-#define EFUSE_USB_PHY_SEL_V  0x1
-#define EFUSE_USB_PHY_SEL_S  25
-/* EFUSE_USB_OTG11_DREFH : RO ;bitpos:[24:23] ;default: 2'h0 ; */
-/*description: USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80
-mV.*/
-#define EFUSE_USB_OTG11_DREFH    0x00000003
-#define EFUSE_USB_OTG11_DREFH_M  ((EFUSE_USB_OTG11_DREFH_V)<<(EFUSE_USB_OTG11_DREFH_S))
-#define EFUSE_USB_OTG11_DREFH_V  0x3
-#define EFUSE_USB_OTG11_DREFH_S  23
-/* EFUSE_USB_DEVICE_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */
-/*description: USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 8
-0mV.*/
-#define EFUSE_USB_DEVICE_DREFH    0x00000003
-#define EFUSE_USB_DEVICE_DREFH_M  ((EFUSE_USB_DEVICE_DREFH_V)<<(EFUSE_USB_DEVICE_DREFH_S))
-#define EFUSE_USB_DEVICE_DREFH_V  0x3
-#define EFUSE_USB_DEVICE_DREFH_S  21
-/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Represents whether flash encrypt function is disabled or enabled(except in SPI b
-oot mode). 1: disabled. 0: enabled..*/
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0
-: enabled..*/
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_V  0x1
-#define EFUSE_DIS_PAD_JTAG_S  19
-/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */
-/*description: Represents whether JTAG is disabled in soft way. Odd number: disabled. Even numb
-er: enabled..*/
-#define EFUSE_SOFT_DIS_JTAG    0x00000007
-#define EFUSE_SOFT_DIS_JTAG_M  ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S))
-#define EFUSE_SOFT_DIS_JTAG_V  0x7
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Represents whether the selection between usb_to_jtag and pad_to_jtag through str
-apping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- is enabled or disabled. 1: enabled. 0: disabled..*/
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_V  0x1
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
-..*/
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (BIT(14))
-#define EFUSE_DIS_TWAI_V  0x1
-#define EFUSE_DIS_TWAI_S  14
-/* EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during b
-oot_mode_download..*/
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x1
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Represents whether the function that forces chip into download mode is disabled
-or enabled. 1: disabled. 0: enabled..*/
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x1
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/* EFUSE_DIS_USB_SERIAL_JTAG : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabl
-ed..*/
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x1
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
-/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Represents whether power glitch function is enabled. 1: enabled. 0: disabled..*/
-#define EFUSE_POWERGLITCH_EN    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_M  (BIT(10))
-#define EFUSE_POWERGLITCH_EN_V  0x1
-#define EFUSE_POWERGLITCH_EN_S  10
-/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Represents whether the function of usb switch to jtag is disabled or enabled. 1:
- disabled. 0: enabled..*/
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (BIT(9))
-#define EFUSE_DIS_USB_JTAG_V  0x1
-#define EFUSE_DIS_USB_JTAG_S  9
-/* EFUSE_USB_OTG11_EXCHG_PINS : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Enable usb otg11 exchange pins of D+ and D-..*/
-#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
-#define EFUSE_USB_OTG11_EXCHG_PINS_M  (BIT(8))
-#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x1
-#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
-/* EFUSE_USB_DEVICE_EXCHG_PINS : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Enable usb device exchange pins of D+ and D-..*/
-#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
-#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (BIT(7))
-#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x1
-#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
-/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
-/*description: Represents whether reading of individual eFuse block(block4~block10) is disabled
- or enabled. 1: disabled. 0: enabled..*/
-#define EFUSE_RD_DIS    0x0000007F
-#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
-#define EFUSE_RD_DIS_V  0x7F
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
 #define EFUSE_RD_DIS_S  0
+/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0;
+ *  Enable usb device exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
+#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
+/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0;
+ *  Enable usb otg11 exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
+#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
+#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
+ *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+ *  boot_mode_download.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+ *  enabled.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+ *  enabled.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode). 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
+ *  TBD
+ */
+#define EFUSE_USB_PHY_SEL    (BIT(25))
+#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
+#define EFUSE_USB_PHY_SEL_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_S  25
+/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_M  (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S)
+#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
 
-#define EFUSE_RD_REPEAT_DATA1_REG          (DR_REG_EFUSE_BASE + 0x34)
-/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: Represents the purpose of Key1..*/
-#define EFUSE_KEY_PURPOSE_1    0x0000000F
-#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
-#define EFUSE_KEY_PURPOSE_1_V  0xF
-#define EFUSE_KEY_PURPOSE_1_S  28
-/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */
-/*description: Represents the purpose of Key0..*/
-#define EFUSE_KEY_PURPOSE_0    0x0000000F
-#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
-#define EFUSE_KEY_PURPOSE_0_V  0xF
-#define EFUSE_KEY_PURPOSE_0_S  24
-/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Represents whether revoking third secure boot key is enabled or disabled. 1: ena
-bled. 0: disabled..*/
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Represents whether revoking second secure boot key is enabled or disabled. 1: en
-abled. 0: disabled..*/
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Represents whether revoking first secure boot key is enabled or disabled. 1: ena
-bled. 0: disabled..*/
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number o
-f 1: enabled. Even number of 1: disabled..*/
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: Represents whether RTC watchdog timeout threshold is selected at startup. 1: sel
-ected. 0: not selected..*/
-#define EFUSE_WDT_DELAY_SEL    0x00000003
-#define EFUSE_WDT_DELAY_SEL_M  ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
-#define EFUSE_WDT_DELAY_SEL_V  0x3
-#define EFUSE_WDT_DELAY_SEL_S  16
-/* EFUSE_XTS_KEY_LENGTH_256 : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to configure flash encryption use xts-128 key, else use xts-256 key
-..*/
-#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_M  (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_V  0x1
-#define EFUSE_XTS_KEY_LENGTH_256_S  14
-/* EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO ;bitpos:[13] ;default: 3'h0 ; */
-/*description: Set this bit to disable software written init key, and force use efuse_init_key..*/
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x1
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
-/* EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO ;bitpos:[12:9] ;default: 4'h0 ; */
-/*description: Set each bit to control whether corresponding key must come from key manager.. 1
- is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds..*/
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000F
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  ((EFUSE_FORCE_USE_KEY_MANAGER_KEY_V)<<(EFUSE_FORCE_USE_KEY_MANAGER_KEY_S))
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0xF
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
-/* EFUSE_KM_DEPLOY_ONLY_ONCE : RO ;bitpos:[8:5] ;default: 4'h0 ; */
-/*description: Set each bit to control whether corresponding key can only be deployed once. 1 i
-s true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds..*/
-#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000F
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  ((EFUSE_KM_DEPLOY_ONLY_ONCE_V)<<(EFUSE_KM_DEPLOY_ONLY_ONCE_S))
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0xF
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
-/* EFUSE_KM_RND_SWITCH_CYCLE : RO ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: Set bits to control key manager random number switch cycle. 0: control by regist
-er. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles..*/
-#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003
-#define EFUSE_KM_RND_SWITCH_CYCLE_M  ((EFUSE_KM_RND_SWITCH_CYCLE_V)<<(EFUSE_KM_RND_SWITCH_CYCLE_S))
-#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x3
-#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
-/* EFUSE_KM_HUK_GEN_STATE_HIGH : RO ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, ev
-en of 1 is valid..*/
-#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  ((EFUSE_KM_HUK_GEN_STATE_HIGH_V)<<(EFUSE_KM_HUK_GEN_STATE_HIGH_S))
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x7
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x00000007U
 #define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0;
+ *  Set bits to control key manager random number switch cycle. 0: control by register.
+ *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0;
+ *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0;
+ *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable software written init key, and force use efuse_init_key.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
+/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
+ *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
+#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_S  14
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+ *  selected. 0: not selected.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+ *  1: enabled. Even number of 1: disabled.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
 
-#define EFUSE_RD_REPEAT_DATA2_REG          (DR_REG_EFUSE_BASE + 0x38)
-/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: Represents the flash waiting time after power-up, in unit of ms. When the value
-less than 15, the waiting time is the programmed value. Otherwise, the waiting t
-ime is 2 times the programmed value..*/
-#define EFUSE_FLASH_TPUW    0x0000000F
-#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
-#define EFUSE_FLASH_TPUW_V  0xF
-#define EFUSE_FLASH_TPUW_S  28
-/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to disable download via USB-OTG..*/
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x1
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
-/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable ecc for flash boot..*/
-#define EFUSE_FLASH_ECC_EN    (BIT(26))
-#define EFUSE_FLASH_ECC_EN_M  (BIT(26))
-#define EFUSE_FLASH_ECC_EN_V  0x1
-#define EFUSE_FLASH_ECC_EN_S  26
-/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[25:24] ;default: 2'b0 ; */
-/*description: Set flash page size..*/
-#define EFUSE_FLASH_PAGE_SIZE    0x00000003
-#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
-#define EFUSE_FLASH_PAGE_SIZE_V  0x3
-#define EFUSE_FLASH_PAGE_SIZE_S  24
-/* EFUSE_FLASH_TYPE : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: The type of interfaced flash. 0: four data lines, 1: eight data lines..*/
-#define EFUSE_FLASH_TYPE    (BIT(23))
-#define EFUSE_FLASH_TYPE_M  (BIT(23))
-#define EFUSE_FLASH_TYPE_V  0x1
-#define EFUSE_FLASH_TYPE_S  23
-/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Represents whether revoking aggressive secure boot is enabled or disabled. 1: en
-abled. 0: disabled..*/
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled..*/
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_V  0x1
-#define EFUSE_SECURE_BOOT_EN_S  20
-/* EFUSE_CRYPT_DPA_ENABLE : RO ;bitpos:[19] ;default: 1'b1 ; */
-/*description: Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled..*/
-#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_M  (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_V  0x1
-#define EFUSE_CRYPT_DPA_ENABLE_S  19
-/* EFUSE_ECDSA_ENABLE_SOFT_K : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Represents whether hardware random number k is forced used in ESDCA. 1: force us
-ed. 0: not force used..*/
-#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x1
-#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
-/* EFUSE_SEC_DPA_LEVEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: Represents the spa secure level by configuring the clock random divide mode..*/
-#define EFUSE_SEC_DPA_LEVEL    0x00000003
-#define EFUSE_SEC_DPA_LEVEL_M  ((EFUSE_SEC_DPA_LEVEL_V)<<(EFUSE_SEC_DPA_LEVEL_S))
-#define EFUSE_SEC_DPA_LEVEL_V  0x3
-#define EFUSE_SEC_DPA_LEVEL_S  16
-/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */
-/*description: Represents the purpose of Key5..*/
-#define EFUSE_KEY_PURPOSE_5    0x0000000F
-#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
-#define EFUSE_KEY_PURPOSE_5_V  0xF
-#define EFUSE_KEY_PURPOSE_5_S  12
-/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */
-/*description: Represents the purpose of Key4..*/
-#define EFUSE_KEY_PURPOSE_4    0x0000000F
-#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
-#define EFUSE_KEY_PURPOSE_4_V  0xF
-#define EFUSE_KEY_PURPOSE_4_S  8
-/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */
-/*description: Represents the purpose of Key3..*/
-#define EFUSE_KEY_PURPOSE_3    0x0000000F
-#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
-#define EFUSE_KEY_PURPOSE_3_V  0xF
-#define EFUSE_KEY_PURPOSE_3_S  4
-/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: Represents the purpose of Key2..*/
-#define EFUSE_KEY_PURPOSE_2    0x0000000F
-#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
-#define EFUSE_KEY_PURPOSE_2_V  0xF
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0;
+ *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+ *  0: not force used.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
+/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
+ *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
+#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_S  19
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
+ *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+ */
+#define EFUSE_FLASH_TYPE    (BIT(23))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  23
+/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0;
+ *  Set flash page size.
+ */
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_S  24
+/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0;
+ *  Set this bit to enable ecc for flash boot.
+ */
+#define EFUSE_FLASH_ECC_EN    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0;
+ *  Set this bit to disable download via USB-OTG.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
 
-#define EFUSE_RD_REPEAT_DATA3_REG          (DR_REG_EFUSE_BASE + 0x3C)
-/* EFUSE_DCDC_VSET : RO ;bitpos:[31:27] ;default: 5'h0 ; */
-/*description: Set the dcdc voltage default..*/
-#define EFUSE_DCDC_VSET    0x0000001F
-#define EFUSE_DCDC_VSET_M  ((EFUSE_DCDC_VSET_V)<<(EFUSE_DCDC_VSET_S))
-#define EFUSE_DCDC_VSET_V  0x1F
-#define EFUSE_DCDC_VSET_S  27
-/* EFUSE_HYS_EN_PAD : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Represents whether the hysteresis function of corresponding PAD is enabled. 1: e
-nabled. 0:disabled..*/
-#define EFUSE_HYS_EN_PAD    (BIT(26))
-#define EFUSE_HYS_EN_PAD_M  (BIT(26))
-#define EFUSE_HYS_EN_PAD_V  0x1
-#define EFUSE_HYS_EN_PAD_S  26
-/* EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot i
-s enabled. 1: disabled. 0: enabled..*/
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x1
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
-/* EFUSE_SECURE_VERSION : RO ;bitpos:[24:9] ;default: 16'h0 ; */
-/*description: Represents the version used by ESP-IDF anti-rollback feature..*/
-#define EFUSE_SECURE_VERSION    0x0000FFFF
-#define EFUSE_SECURE_VERSION_M  ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S))
-#define EFUSE_SECURE_VERSION_V  0xFFFF
-#define EFUSE_SECURE_VERSION_S  9
-/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Represents whether ROM code is forced to send a resume command during SPI boot.
-1: forced. 0:not forced..*/
-#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_M  (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_V  0x1
-#define EFUSE_FORCE_SEND_RESUME_S  8
-/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: Represents the type of UART printing. 00: force enable printing. 01: enable prin
-ting when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset a
-t high level. 11: force disable printing..*/
-#define EFUSE_UART_PRINT_CONTROL    0x00000003
-#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
-#define EFUSE_UART_PRINT_CONTROL_V  0x3
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Represents whether security download is enabled or disabled. 1: enabled. 0: disa
-bled..*/
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Represents whether the USB-Serial-JTAG download function is disabled or enabled.
- 1: disabled. 0: enabled..*/
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x1
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/* EFUSE_LOCK_KM_KEY : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: TBD.*/
-#define EFUSE_LOCK_KM_KEY    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_M  (BIT(3))
-#define EFUSE_LOCK_KM_KEY_V  0x1
-#define EFUSE_LOCK_KM_KEY_S  3
-/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disable
-d. 0: enabled..*/
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x1
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enab
-led..*/
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_V  0x1
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
-..*/
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
 #define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+ *  0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
+#define EFUSE_LOCK_KM_KEY_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+ *  disabled.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Represents the type of UART printing. 00: force enable printing. 01: enable
+ *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+ *  at high level. 11: force disable printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+ *  forced. 0:not forced.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  8
+/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
+/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
+ *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+ *  enabled. 0:disabled.
+ */
+#define EFUSE_HYS_EN_PAD    (BIT(26))
+#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
+#define EFUSE_HYS_EN_PAD_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_S  26
+/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0;
+ *  Set the dcdc voltage default.
+ */
+#define EFUSE_DCDC_VSET    0x0000001FU
+#define EFUSE_DCDC_VSET_M  (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S)
+#define EFUSE_DCDC_VSET_V  0x0000001FU
+#define EFUSE_DCDC_VSET_S  27
 
-#define EFUSE_RD_REPEAT_DATA4_REG          (DR_REG_EFUSE_BASE + 0x40)
-/* EFUSE_DIS_SWD : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Set this bit to disable super-watchdog..*/
-#define EFUSE_DIS_SWD    (BIT(21))
-#define EFUSE_DIS_SWD_M  (BIT(21))
-#define EFUSE_DIS_SWD_V  0x1
-#define EFUSE_DIS_SWD_S  21
-/* EFUSE_DIS_WDT : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Set this bit to disable watch dog..*/
-#define EFUSE_DIS_WDT    (BIT(20))
-#define EFUSE_DIS_WDT_M  (BIT(20))
-#define EFUSE_DIS_WDT_V  0x1
-#define EFUSE_DIS_WDT_S  20
-/* EFUSE_DCDC_VSET_EN : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Select dcdc vset use efuse_dcdc_vset..*/
-#define EFUSE_DCDC_VSET_EN    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_M  (BIT(19))
-#define EFUSE_DCDC_VSET_EN_V  0x1
-#define EFUSE_DCDC_VSET_EN_S  19
-/* EFUSE_HP_PWR_SRC_SEL : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: HP system power source select. 0:LDO. 1: DCDC..*/
-#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_M  (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_V  0x1
-#define EFUSE_HP_PWR_SRC_SEL_S  18
-/* EFUSE_USB_OTG11_DREFL : RO ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with ste
-p of 80 mV..*/
-#define EFUSE_USB_OTG11_DREFL    0x00000003
-#define EFUSE_USB_OTG11_DREFL_M  ((EFUSE_USB_OTG11_DREFL_V)<<(EFUSE_USB_OTG11_DREFL_S))
-#define EFUSE_USB_OTG11_DREFL_V  0x3
-#define EFUSE_USB_OTG11_DREFL_S  14
-/* EFUSE_USB_DEVICE_DREFL : RO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with st
-ep of 80 mV..*/
-#define EFUSE_USB_DEVICE_DREFL    0x00000003
-#define EFUSE_USB_DEVICE_DREFL_M  ((EFUSE_USB_DEVICE_DREFL_V)<<(EFUSE_USB_DEVICE_DREFL_S))
-#define EFUSE_USB_DEVICE_DREFL_V  0x3
-#define EFUSE_USB_DEVICE_DREFL_S  12
-/* EFUSE_KM_DISABLE_DEPLOY_MODE : RO ;bitpos:[11:8] ;default: 4'h0 ; */
-/*description: TBD..*/
-#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000F
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  ((EFUSE_KM_DISABLE_DEPLOY_MODE_V)<<(EFUSE_KM_DISABLE_DEPLOY_MODE_S))
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0xF
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
-/* EFUSE_0PXA_TIEH_SEL_3 : RO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: TBD..*/
-#define EFUSE_0PXA_TIEH_SEL_3    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_3_M  ((EFUSE_0PXA_TIEH_SEL_3_V)<<(EFUSE_0PXA_TIEH_SEL_3_S))
-#define EFUSE_0PXA_TIEH_SEL_3_V  0x3
-#define EFUSE_0PXA_TIEH_SEL_3_S  6
-/* EFUSE_0PXA_TIEH_SEL_2 : RO ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: TBD..*/
-#define EFUSE_0PXA_TIEH_SEL_2    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_2_M  ((EFUSE_0PXA_TIEH_SEL_2_V)<<(EFUSE_0PXA_TIEH_SEL_2_S))
-#define EFUSE_0PXA_TIEH_SEL_2_V  0x3
-#define EFUSE_0PXA_TIEH_SEL_2_S  4
-/* EFUSE_0PXA_TIEH_SEL_1 : RO ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: TBD..*/
-#define EFUSE_0PXA_TIEH_SEL_1    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_1_M  ((EFUSE_0PXA_TIEH_SEL_1_V)<<(EFUSE_0PXA_TIEH_SEL_1_S))
-#define EFUSE_0PXA_TIEH_SEL_1_V  0x3
-#define EFUSE_0PXA_TIEH_SEL_1_S  2
-/* EFUSE_0PXA_TIEH_SEL_0 : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: TBD.*/
-#define EFUSE_0PXA_TIEH_SEL_0    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_0_M  ((EFUSE_0PXA_TIEH_SEL_0_V)<<(EFUSE_0PXA_TIEH_SEL_0_S))
-#define EFUSE_0PXA_TIEH_SEL_0_V  0x3
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_0PXA_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
+ *  TBD
+ */
+#define EFUSE_0PXA_TIEH_SEL_0    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_0_M  (EFUSE_0PXA_TIEH_SEL_0_V << EFUSE_0PXA_TIEH_SEL_0_S)
+#define EFUSE_0PXA_TIEH_SEL_0_V  0x00000003U
 #define EFUSE_0PXA_TIEH_SEL_0_S  0
+/** EFUSE_0PXA_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_0PXA_TIEH_SEL_1    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_1_M  (EFUSE_0PXA_TIEH_SEL_1_V << EFUSE_0PXA_TIEH_SEL_1_S)
+#define EFUSE_0PXA_TIEH_SEL_1_V  0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_1_S  2
+/** EFUSE_0PXA_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_0PXA_TIEH_SEL_2    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_2_M  (EFUSE_0PXA_TIEH_SEL_2_V << EFUSE_0PXA_TIEH_SEL_2_S)
+#define EFUSE_0PXA_TIEH_SEL_2_V  0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_2_S  4
+/** EFUSE_0PXA_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_0PXA_TIEH_SEL_3    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_3_M  (EFUSE_0PXA_TIEH_SEL_3_V << EFUSE_0PXA_TIEH_SEL_3_S)
+#define EFUSE_0PXA_TIEH_SEL_3_V  0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_3_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
+/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
+ *  HP system power source select. 0:LDO. 1: DCDC.
+ */
+#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_M  (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S)
+#define EFUSE_HP_PWR_SRC_SEL_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_S  18
+/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0;
+ *  Select dcdc vset use efuse_dcdc_vset.
+ */
+#define EFUSE_DCDC_VSET_EN    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
+#define EFUSE_DCDC_VSET_EN_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_S  19
+/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0;
+ *  Set this bit to disable watch dog.
+ */
+#define EFUSE_DIS_WDT    (BIT(20))
+#define EFUSE_DIS_WDT_M  (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S)
+#define EFUSE_DIS_WDT_V  0x00000001U
+#define EFUSE_DIS_WDT_S  20
+/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0;
+ *  Set this bit to disable super-watchdog.
+ */
+#define EFUSE_DIS_SWD    (BIT(21))
+#define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
+#define EFUSE_DIS_SWD_V  0x00000001U
+#define EFUSE_DIS_SWD_S  21
 
-#define EFUSE_RD_MAC_SYS_0_REG          (DR_REG_EFUSE_BASE + 0x44)
-/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the low 32 bits of MAC address..*/
-#define EFUSE_MAC_0    0xFFFFFFFF
-#define EFUSE_MAC_0_M  ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S))
-#define EFUSE_MAC_0_V  0xFFFFFFFF
+/** EFUSE_RD_MAC_SYS_0_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
 #define EFUSE_MAC_0_S  0
 
-#define EFUSE_RD_MAC_SYS_1_REG          (DR_REG_EFUSE_BASE + 0x48)
-/* EFUSE_MAC_EXT : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: Stores the extended bits of MAC address..*/
-#define EFUSE_MAC_EXT    0x0000FFFF
-#define EFUSE_MAC_EXT_M  ((EFUSE_MAC_EXT_V)<<(EFUSE_MAC_EXT_S))
-#define EFUSE_MAC_EXT_V  0xFFFF
-#define EFUSE_MAC_EXT_S  16
-/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: Stores the high 16 bits of MAC address..*/
-#define EFUSE_MAC_1    0x0000FFFF
-#define EFUSE_MAC_1_M  ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S))
-#define EFUSE_MAC_1_V  0xFFFF
+/** EFUSE_RD_MAC_SYS_1_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
 #define EFUSE_MAC_1_S  0
+/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
+ *  Stores the extended bits of MAC address.
+ */
+#define EFUSE_MAC_EXT    0x0000FFFFU
+#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
+#define EFUSE_MAC_EXT_V  0x0000FFFFU
+#define EFUSE_MAC_EXT_S  16
 
-#define EFUSE_RD_MAC_SYS_2_REG          (DR_REG_EFUSE_BASE + 0x4C)
-/* EFUSE_MAC_RESERVED_0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */
-/*description: Reserved..*/
-#define EFUSE_MAC_RESERVED_0    0x0003FFFF
-#define EFUSE_MAC_RESERVED_0_M  ((EFUSE_MAC_RESERVED_0_V)<<(EFUSE_MAC_RESERVED_0_S))
-#define EFUSE_MAC_RESERVED_0_V  0x3FFFF
-#define EFUSE_MAC_RESERVED_0_S  14
-/* EFUSE_MAC_RESERVED_1 : RO ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: Reserved..*/
-#define EFUSE_MAC_RESERVED_1    0x00003FFF
-#define EFUSE_MAC_RESERVED_1_M  ((EFUSE_MAC_RESERVED_1_V)<<(EFUSE_MAC_RESERVED_1_S))
-#define EFUSE_MAC_RESERVED_1_V  0x3FFF
+/** EFUSE_RD_MAC_SYS_2_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_MAC_RESERVED_1    0x00003FFFU
+#define EFUSE_MAC_RESERVED_1_M  (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
+#define EFUSE_MAC_RESERVED_1_V  0x00003FFFU
 #define EFUSE_MAC_RESERVED_1_S  0
+/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_MAC_RESERVED_0    0x0003FFFFU
+#define EFUSE_MAC_RESERVED_0_M  (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
+#define EFUSE_MAC_RESERVED_0_V  0x0003FFFFU
+#define EFUSE_MAC_RESERVED_0_S  14
 
-#define EFUSE_RD_MAC_SYS_3_REG          (DR_REG_EFUSE_BASE + 0x50)
-/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
-/*description: Stores the first 14 bits of the zeroth part of system data..*/
-#define EFUSE_SYS_DATA_PART0_0    0x00003FFF
-#define EFUSE_SYS_DATA_PART0_0_M  ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
-#define EFUSE_SYS_DATA_PART0_0_V  0x3FFF
-#define EFUSE_SYS_DATA_PART0_0_S  18
-/* EFUSE_MAC_RESERVED_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
-/*description: Reserved..*/
-#define EFUSE_MAC_RESERVED_2    0x0003FFFF
-#define EFUSE_MAC_RESERVED_2_M  ((EFUSE_MAC_RESERVED_2_V)<<(EFUSE_MAC_RESERVED_2_S))
-#define EFUSE_MAC_RESERVED_2_V  0x3FFFF
+/** EFUSE_RD_MAC_SYS_3_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_MAC_RESERVED_2    0x0003FFFFU
+#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
+#define EFUSE_MAC_RESERVED_2_V  0x0003FFFFU
 #define EFUSE_MAC_RESERVED_2_S  0
+/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
+ *  Stores the first 14 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
+#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_S  18
 
-#define EFUSE_RD_MAC_SYS_4_REG          (DR_REG_EFUSE_BASE + 0x54)
-/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of the zeroth part of system data..*/
-#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART0_1_M  ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
-#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFF
+/** EFUSE_RD_MAC_SYS_4_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART0_1_S  0
 
-#define EFUSE_RD_MAC_SYS_5_REG          (DR_REG_EFUSE_BASE + 0x58)
-/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of the zeroth part of system data..*/
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART0_2_M  ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S))
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFF
+/** EFUSE_RD_MAC_SYS_5_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART0_2_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x5C)
-/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_0_M  ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S))
-#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_0_M  (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
+#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_0_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x60)
-/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_1_M  ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S))
-#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_1_M  (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
+#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_1_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x64)
-/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_2_M  ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S))
-#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_2_M  (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
+#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_2_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA3_REG          (DR_REG_EFUSE_BASE + 0x68)
-/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_3_M  ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S))
-#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_3_M  (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
+#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_3_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA4_REG          (DR_REG_EFUSE_BASE + 0x6C)
-/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_4_M  ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S))
-#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
+#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_4_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA5_REG          (DR_REG_EFUSE_BASE + 0x70)
-/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_5_M  ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S))
-#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
+#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_5_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA6_REG          (DR_REG_EFUSE_BASE + 0x74)
-/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_6_M  ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S))
-#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
+#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_6_S  0
 
-#define EFUSE_RD_SYS_PART1_DATA7_REG          (DR_REG_EFUSE_BASE + 0x78)
-/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of the first part of system data..*/
-#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART1_7_M  ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S))
-#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
+#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART1_7_S  0
 
-#define EFUSE_RD_USR_DATA0_REG          (DR_REG_EFUSE_BASE + 0x7C)
-/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA0    0xFFFFFFFF
-#define EFUSE_USR_DATA0_M  ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S))
-#define EFUSE_USR_DATA0_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA0_S  0
 
-#define EFUSE_RD_USR_DATA1_REG          (DR_REG_EFUSE_BASE + 0x80)
-/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA1    0xFFFFFFFF
-#define EFUSE_USR_DATA1_M  ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S))
-#define EFUSE_USR_DATA1_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA1_S  0
 
-#define EFUSE_RD_USR_DATA2_REG          (DR_REG_EFUSE_BASE + 0x84)
-/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA2    0xFFFFFFFF
-#define EFUSE_USR_DATA2_M  ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S))
-#define EFUSE_USR_DATA2_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA2_S  0
 
-#define EFUSE_RD_USR_DATA3_REG          (DR_REG_EFUSE_BASE + 0x88)
-/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA3    0xFFFFFFFF
-#define EFUSE_USR_DATA3_M  ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S))
-#define EFUSE_USR_DATA3_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA3_S  0
 
-#define EFUSE_RD_USR_DATA4_REG          (DR_REG_EFUSE_BASE + 0x8C)
-/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA4    0xFFFFFFFF
-#define EFUSE_USR_DATA4_M  ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S))
-#define EFUSE_USR_DATA4_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA4_S  0
 
-#define EFUSE_RD_USR_DATA5_REG          (DR_REG_EFUSE_BASE + 0x90)
-/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA5    0xFFFFFFFF
-#define EFUSE_USR_DATA5_M  ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S))
-#define EFUSE_USR_DATA5_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA5_S  0
 
-#define EFUSE_RD_USR_DATA6_REG          (DR_REG_EFUSE_BASE + 0x94)
-/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA6    0xFFFFFFFF
-#define EFUSE_USR_DATA6_M  ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S))
-#define EFUSE_USR_DATA6_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA6    0xFFFFFFFFU
+#define EFUSE_USR_DATA6_M  (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
+#define EFUSE_USR_DATA6_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA6_S  0
 
-#define EFUSE_RD_USR_DATA7_REG          (DR_REG_EFUSE_BASE + 0x98)
-/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of BLOCK3 (user)..*/
-#define EFUSE_USR_DATA7    0xFFFFFFFF
-#define EFUSE_USR_DATA7_M  ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S))
-#define EFUSE_USR_DATA7_V  0xFFFFFFFF
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA7    0xFFFFFFFFU
+#define EFUSE_USR_DATA7_M  (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
+#define EFUSE_USR_DATA7_V  0xFFFFFFFFU
 #define EFUSE_USR_DATA7_S  0
 
-#define EFUSE_RD_KEY0_DATA0_REG          (DR_REG_EFUSE_BASE + 0x9C)
-/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA0    0xFFFFFFFF
-#define EFUSE_KEY0_DATA0_M  ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S))
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA0_S  0
 
-#define EFUSE_RD_KEY0_DATA1_REG          (DR_REG_EFUSE_BASE + 0xA0)
-/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA1    0xFFFFFFFF
-#define EFUSE_KEY0_DATA1_M  ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S))
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA1_S  0
 
-#define EFUSE_RD_KEY0_DATA2_REG          (DR_REG_EFUSE_BASE + 0xA4)
-/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA2    0xFFFFFFFF
-#define EFUSE_KEY0_DATA2_M  ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S))
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA2_S  0
 
-#define EFUSE_RD_KEY0_DATA3_REG          (DR_REG_EFUSE_BASE + 0xA8)
-/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA3    0xFFFFFFFF
-#define EFUSE_KEY0_DATA3_M  ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S))
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA3_S  0
 
-#define EFUSE_RD_KEY0_DATA4_REG          (DR_REG_EFUSE_BASE + 0xAC)
-/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA4    0xFFFFFFFF
-#define EFUSE_KEY0_DATA4_M  ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S))
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA4_S  0
 
-#define EFUSE_RD_KEY0_DATA5_REG          (DR_REG_EFUSE_BASE + 0xB0)
-/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA5    0xFFFFFFFF
-#define EFUSE_KEY0_DATA5_M  ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S))
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA5_S  0
 
-#define EFUSE_RD_KEY0_DATA6_REG          (DR_REG_EFUSE_BASE + 0xB4)
-/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA6    0xFFFFFFFF
-#define EFUSE_KEY0_DATA6_M  ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S))
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA6_S  0
 
-#define EFUSE_RD_KEY0_DATA7_REG          (DR_REG_EFUSE_BASE + 0xB8)
-/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of KEY0..*/
-#define EFUSE_KEY0_DATA7    0xFFFFFFFF
-#define EFUSE_KEY0_DATA7_M  ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S))
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFF
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
 #define EFUSE_KEY0_DATA7_S  0
 
-#define EFUSE_RD_KEY1_DATA0_REG          (DR_REG_EFUSE_BASE + 0xBC)
-/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA0    0xFFFFFFFF
-#define EFUSE_KEY1_DATA0_M  ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S))
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA0_S  0
 
-#define EFUSE_RD_KEY1_DATA1_REG          (DR_REG_EFUSE_BASE + 0xC0)
-/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA1    0xFFFFFFFF
-#define EFUSE_KEY1_DATA1_M  ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S))
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA1_S  0
 
-#define EFUSE_RD_KEY1_DATA2_REG          (DR_REG_EFUSE_BASE + 0xC4)
-/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA2    0xFFFFFFFF
-#define EFUSE_KEY1_DATA2_M  ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S))
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA2_S  0
 
-#define EFUSE_RD_KEY1_DATA3_REG          (DR_REG_EFUSE_BASE + 0xC8)
-/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA3    0xFFFFFFFF
-#define EFUSE_KEY1_DATA3_M  ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S))
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA3_S  0
 
-#define EFUSE_RD_KEY1_DATA4_REG          (DR_REG_EFUSE_BASE + 0xCC)
-/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA4    0xFFFFFFFF
-#define EFUSE_KEY1_DATA4_M  ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S))
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA4_S  0
 
-#define EFUSE_RD_KEY1_DATA5_REG          (DR_REG_EFUSE_BASE + 0xD0)
-/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA5    0xFFFFFFFF
-#define EFUSE_KEY1_DATA5_M  ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S))
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA5_S  0
 
-#define EFUSE_RD_KEY1_DATA6_REG          (DR_REG_EFUSE_BASE + 0xD4)
-/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA6    0xFFFFFFFF
-#define EFUSE_KEY1_DATA6_M  ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S))
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA6_S  0
 
-#define EFUSE_RD_KEY1_DATA7_REG          (DR_REG_EFUSE_BASE + 0xD8)
-/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of KEY1..*/
-#define EFUSE_KEY1_DATA7    0xFFFFFFFF
-#define EFUSE_KEY1_DATA7_M  ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S))
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFF
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
 #define EFUSE_KEY1_DATA7_S  0
 
-#define EFUSE_RD_KEY2_DATA0_REG          (DR_REG_EFUSE_BASE + 0xDC)
-/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA0    0xFFFFFFFF
-#define EFUSE_KEY2_DATA0_M  ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S))
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA0_S  0
 
-#define EFUSE_RD_KEY2_DATA1_REG          (DR_REG_EFUSE_BASE + 0xE0)
-/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA1    0xFFFFFFFF
-#define EFUSE_KEY2_DATA1_M  ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S))
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA1_S  0
 
-#define EFUSE_RD_KEY2_DATA2_REG          (DR_REG_EFUSE_BASE + 0xE4)
-/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA2    0xFFFFFFFF
-#define EFUSE_KEY2_DATA2_M  ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S))
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA2_S  0
 
-#define EFUSE_RD_KEY2_DATA3_REG          (DR_REG_EFUSE_BASE + 0xE8)
-/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA3    0xFFFFFFFF
-#define EFUSE_KEY2_DATA3_M  ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S))
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA3_S  0
 
-#define EFUSE_RD_KEY2_DATA4_REG          (DR_REG_EFUSE_BASE + 0xEC)
-/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA4    0xFFFFFFFF
-#define EFUSE_KEY2_DATA4_M  ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S))
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA4_S  0
 
-#define EFUSE_RD_KEY2_DATA5_REG          (DR_REG_EFUSE_BASE + 0xF0)
-/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA5    0xFFFFFFFF
-#define EFUSE_KEY2_DATA5_M  ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S))
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA5_S  0
 
-#define EFUSE_RD_KEY2_DATA6_REG          (DR_REG_EFUSE_BASE + 0xF4)
-/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA6    0xFFFFFFFF
-#define EFUSE_KEY2_DATA6_M  ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S))
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA6_S  0
 
-#define EFUSE_RD_KEY2_DATA7_REG          (DR_REG_EFUSE_BASE + 0xF8)
-/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of KEY2..*/
-#define EFUSE_KEY2_DATA7    0xFFFFFFFF
-#define EFUSE_KEY2_DATA7_M  ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S))
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFF
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
 #define EFUSE_KEY2_DATA7_S  0
 
-#define EFUSE_RD_KEY3_DATA0_REG          (DR_REG_EFUSE_BASE + 0xFC)
-/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA0    0xFFFFFFFF
-#define EFUSE_KEY3_DATA0_M  ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S))
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA0_S  0
 
-#define EFUSE_RD_KEY3_DATA1_REG          (DR_REG_EFUSE_BASE + 0x100)
-/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA1    0xFFFFFFFF
-#define EFUSE_KEY3_DATA1_M  ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S))
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA1_S  0
 
-#define EFUSE_RD_KEY3_DATA2_REG          (DR_REG_EFUSE_BASE + 0x104)
-/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA2    0xFFFFFFFF
-#define EFUSE_KEY3_DATA2_M  ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S))
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA2_S  0
 
-#define EFUSE_RD_KEY3_DATA3_REG          (DR_REG_EFUSE_BASE + 0x108)
-/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA3    0xFFFFFFFF
-#define EFUSE_KEY3_DATA3_M  ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S))
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA3_S  0
 
-#define EFUSE_RD_KEY3_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10C)
-/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA4    0xFFFFFFFF
-#define EFUSE_KEY3_DATA4_M  ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S))
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA4_S  0
 
-#define EFUSE_RD_KEY3_DATA5_REG          (DR_REG_EFUSE_BASE + 0x110)
-/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA5    0xFFFFFFFF
-#define EFUSE_KEY3_DATA5_M  ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S))
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA5_S  0
 
-#define EFUSE_RD_KEY3_DATA6_REG          (DR_REG_EFUSE_BASE + 0x114)
-/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA6    0xFFFFFFFF
-#define EFUSE_KEY3_DATA6_M  ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S))
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA6_S  0
 
-#define EFUSE_RD_KEY3_DATA7_REG          (DR_REG_EFUSE_BASE + 0x118)
-/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of KEY3..*/
-#define EFUSE_KEY3_DATA7    0xFFFFFFFF
-#define EFUSE_KEY3_DATA7_M  ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S))
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFF
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
 #define EFUSE_KEY3_DATA7_S  0
 
-#define EFUSE_RD_KEY4_DATA0_REG          (DR_REG_EFUSE_BASE + 0x11C)
-/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA0    0xFFFFFFFF
-#define EFUSE_KEY4_DATA0_M  ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S))
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA0_S  0
 
-#define EFUSE_RD_KEY4_DATA1_REG          (DR_REG_EFUSE_BASE + 0x120)
-/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA1    0xFFFFFFFF
-#define EFUSE_KEY4_DATA1_M  ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S))
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA1_S  0
 
-#define EFUSE_RD_KEY4_DATA2_REG          (DR_REG_EFUSE_BASE + 0x124)
-/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA2    0xFFFFFFFF
-#define EFUSE_KEY4_DATA2_M  ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S))
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA2_S  0
 
-#define EFUSE_RD_KEY4_DATA3_REG          (DR_REG_EFUSE_BASE + 0x128)
-/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA3    0xFFFFFFFF
-#define EFUSE_KEY4_DATA3_M  ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S))
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA3_S  0
 
-#define EFUSE_RD_KEY4_DATA4_REG          (DR_REG_EFUSE_BASE + 0x12C)
-/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA4    0xFFFFFFFF
-#define EFUSE_KEY4_DATA4_M  ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S))
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA4_S  0
 
-#define EFUSE_RD_KEY4_DATA5_REG          (DR_REG_EFUSE_BASE + 0x130)
-/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA5    0xFFFFFFFF
-#define EFUSE_KEY4_DATA5_M  ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S))
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA5_S  0
 
-#define EFUSE_RD_KEY4_DATA6_REG          (DR_REG_EFUSE_BASE + 0x134)
-/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA6    0xFFFFFFFF
-#define EFUSE_KEY4_DATA6_M  ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S))
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA6_S  0
 
-#define EFUSE_RD_KEY4_DATA7_REG          (DR_REG_EFUSE_BASE + 0x138)
-/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of KEY4..*/
-#define EFUSE_KEY4_DATA7    0xFFFFFFFF
-#define EFUSE_KEY4_DATA7_M  ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S))
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFF
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
 #define EFUSE_KEY4_DATA7_S  0
 
-#define EFUSE_RD_KEY5_DATA0_REG          (DR_REG_EFUSE_BASE + 0x13C)
-/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the zeroth 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA0    0xFFFFFFFF
-#define EFUSE_KEY5_DATA0_M  ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S))
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA0_S  0
 
-#define EFUSE_RD_KEY5_DATA1_REG          (DR_REG_EFUSE_BASE + 0x140)
-/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA1    0xFFFFFFFF
-#define EFUSE_KEY5_DATA1_M  ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S))
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA1_S  0
 
-#define EFUSE_RD_KEY5_DATA2_REG          (DR_REG_EFUSE_BASE + 0x144)
-/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the second 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA2    0xFFFFFFFF
-#define EFUSE_KEY5_DATA2_M  ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S))
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA2_S  0
 
-#define EFUSE_RD_KEY5_DATA3_REG          (DR_REG_EFUSE_BASE + 0x148)
-/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the third 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA3    0xFFFFFFFF
-#define EFUSE_KEY5_DATA3_M  ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S))
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA3_S  0
 
-#define EFUSE_RD_KEY5_DATA4_REG          (DR_REG_EFUSE_BASE + 0x14C)
-/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fourth 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA4    0xFFFFFFFF
-#define EFUSE_KEY5_DATA4_M  ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S))
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA4_S  0
 
-#define EFUSE_RD_KEY5_DATA5_REG          (DR_REG_EFUSE_BASE + 0x150)
-/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the fifth 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA5    0xFFFFFFFF
-#define EFUSE_KEY5_DATA5_M  ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S))
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA5_S  0
 
-#define EFUSE_RD_KEY5_DATA6_REG          (DR_REG_EFUSE_BASE + 0x154)
-/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the sixth 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA6    0xFFFFFFFF
-#define EFUSE_KEY5_DATA6_M  ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S))
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA6_S  0
 
-#define EFUSE_RD_KEY5_DATA7_REG          (DR_REG_EFUSE_BASE + 0x158)
-/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the seventh 32 bits of KEY5..*/
-#define EFUSE_KEY5_DATA7    0xFFFFFFFF
-#define EFUSE_KEY5_DATA7_M  ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S))
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFF
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
 #define EFUSE_KEY5_DATA7_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x15C)
-/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_0_M  ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S))
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_0_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x160)
-/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_1_M  ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S))
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_1_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x164)
-/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_2_M  ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S))
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_2_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x168)
-/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_3_M  ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S))
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_3_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x16C)
-/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_4_M  ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S))
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_4_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x170)
-/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_5_M  ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S))
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_5_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x174)
-/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_6_M  ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S))
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_6_S  0
 
-#define EFUSE_RD_SYS_PART2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x178)
-/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the $nth 32 bits of the 2nd part of system data..*/
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFF
-#define EFUSE_SYS_DATA_PART2_7_M  ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S))
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFF
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_7_S  0
 
-#define EFUSE_RD_REPEAT_ERR0_REG          (DR_REG_EFUSE_BASE + 0x17C)
-/* EFUSE_HUK_GEN_STATE_LOW_ERR : RO ;bitpos:[31:26] ;default: 6'h0 ; */
-/*description: Indicates a programming error of HUK_GEN_STATE_LOW..*/
-#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003F
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  ((EFUSE_HUK_GEN_STATE_LOW_ERR_V)<<(EFUSE_HUK_GEN_STATE_LOW_ERR_S))
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x3F
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
-/* EFUSE_USB_PHY_SEL_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Indicates a programming error of USB_PHY_SEL..*/
-#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
-#define EFUSE_USB_PHY_SEL_ERR_M  (BIT(25))
-#define EFUSE_USB_PHY_SEL_ERR_V  0x1
-#define EFUSE_USB_PHY_SEL_ERR_S  25
-/* EFUSE_USB_OTG11_DREFH_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */
-/*description: Indicates a programming error of USB_OTG11_DREFH..*/
-#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003
-#define EFUSE_USB_OTG11_DREFH_ERR_M  ((EFUSE_USB_OTG11_DREFH_ERR_V)<<(EFUSE_USB_OTG11_DREFH_ERR_S))
-#define EFUSE_USB_OTG11_DREFH_ERR_V  0x3
-#define EFUSE_USB_OTG11_DREFH_ERR_S  23
-/* EFUSE_USB_DEVICE_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */
-/*description: Indicates a programming error of USB_DEVICE_DREFH..*/
-#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003
-#define EFUSE_USB_DEVICE_DREFH_ERR_M  ((EFUSE_USB_DEVICE_DREFH_ERR_V)<<(EFUSE_USB_DEVICE_DREFH_ERR_S))
-#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x3
-#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
-/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT..*/
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x1
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_PAD_JTAG..*/
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x1
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */
-/*description: Indicates a programming error of SOFT_DIS_JTAG..*/
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S))
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x7
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Indicates a programming error of JTAG_SEL_ENABLE..*/
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x1
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_TWAI..*/
-#define EFUSE_DIS_TWAI_ERR    (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_M  (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_V  0x1
-#define EFUSE_DIS_TWAI_ERR_S  14
-/* EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS..*/
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x1
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
-/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_FORCE_DOWNLOAD..*/
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x1
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/* EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG..*/
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x1
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
-/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Indicates a programming error of POWERGLITCH_EN..*/
-#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_ERR_M  (BIT(10))
-#define EFUSE_POWERGLITCH_EN_ERR_V  0x1
-#define EFUSE_POWERGLITCH_EN_ERR_S  10
-/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_USB_JTAG..*/
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x1
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/* EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS..*/
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (BIT(8))
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x1
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
-/* EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS..*/
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (BIT(7))
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x1
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
-/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
-/*description: Indicates a programming error of RD_DIS..*/
-#define EFUSE_RD_DIS_ERR    0x0000007F
-#define EFUSE_RD_DIS_ERR_M  ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S))
-#define EFUSE_RD_DIS_ERR_V  0x7F
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Indicates a programming error of RD_DIS.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
 #define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0;
+ *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
+/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Indicates a programming error of DIS_USB_JTAG.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
+ *  Indicates a programming error of POWERGLITCH_EN.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  10
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of DIS_TWAI.
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Indicates a programming error of JTAG_SEL_ENABLE.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Indicates a programming error of SOFT_DIS_JTAG.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DIS_PAD_JTAG.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of USB_PHY_SEL.
+ */
+#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
+#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_ERR_S  25
+/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_LOW.
+ */
+#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S)
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
 
-#define EFUSE_RD_REPEAT_ERR1_REG          (DR_REG_EFUSE_BASE + 0x180)
-/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: Indicates a programming error of KEY_PURPOSE_1..*/
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000F
-#define EFUSE_KEY_PURPOSE_1_ERR_M  ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S))
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0xF
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */
-/*description: Indicates a programming error of KEY_PURPOSE_0..*/
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000F
-#define EFUSE_KEY_PURPOSE_0_ERR_M  ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S))
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0xF
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE2..*/
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x1
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE1..*/
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x1
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE0..*/
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x1
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: Indicates a programming error of SPI_BOOT_CRYPT_CNT..*/
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S))
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x7
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: Indicates a programming error of WDT_DELAY_SEL..*/
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003
-#define EFUSE_WDT_DELAY_SEL_ERR_M  ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S))
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x3
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/* EFUSE_XTS_KEY_LENGTH_256_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Indicates a programming error of XTS_KEY_LENGTH_256..*/
-#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x1
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
-/* EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO ;bitpos:[13] ;default: 3'h0 ; */
-/*description: Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY..*/
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x1
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
-/* EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO ;bitpos:[12:9] ;default: 4'h0 ; */
-/*description: Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY..*/
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000F
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  ((EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V)<<(EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S))
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0xF
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
-/* EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO ;bitpos:[8:5] ;default: 4'h0 ; */
-/*description: Indicates a programming error of KM_DEPLOY_ONLY_ONCE..*/
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000F
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  ((EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V)<<(EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S))
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0xF
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
-/* EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: Indicates a programming error of KM_RND_SWITCH_CYCLE..*/
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  ((EFUSE_KM_RND_SWITCH_CYCLE_ERR_V)<<(EFUSE_KM_RND_SWITCH_CYCLE_ERR_S))
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x3
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
-/* EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: Indicates a programming error of HUK_GEN_STATE_HIGH..*/
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  ((EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V)<<(EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S))
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x7
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x00000007U
 #define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0;
+ *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0;
+ *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0;
+ *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
+/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of XTS_KEY_LENGTH_256.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of WDT_DELAY_SEL.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_0.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_1.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
 
-#define EFUSE_RD_REPEAT_ERR2_REG          (DR_REG_EFUSE_BASE + 0x184)
-/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: Indicates a programming error of FLASH_TPUW..*/
-#define EFUSE_FLASH_TPUW_ERR    0x0000000F
-#define EFUSE_FLASH_TPUW_ERR_M  ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S))
-#define EFUSE_FLASH_TPUW_ERR_V  0xF
-#define EFUSE_FLASH_TPUW_ERR_S  28
-/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE..*/
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x1
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
-/* EFUSE_FLASH_ECC_EN_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Indicates a programming error of FLASH_ECC_EN..*/
-#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
-#define EFUSE_FLASH_ECC_EN_ERR_M  (BIT(26))
-#define EFUSE_FLASH_ECC_EN_ERR_V  0x1
-#define EFUSE_FLASH_ECC_EN_ERR_S  26
-/* EFUSE_FLASH_PAGE_SIZE_ERR : RO ;bitpos:[25:24] ;default: 2'b0 ; */
-/*description: Indicates a programming error of FLASH_PAGE_SIZE..*/
-#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003
-#define EFUSE_FLASH_PAGE_SIZE_ERR_M  ((EFUSE_FLASH_PAGE_SIZE_ERR_V)<<(EFUSE_FLASH_PAGE_SIZE_ERR_S))
-#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x3
-#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
-/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Indicates a programming error of FLASH_TYPE..*/
-#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
-#define EFUSE_FLASH_TYPE_ERR_M  (BIT(23))
-#define EFUSE_FLASH_TYPE_ERR_V  0x1
-#define EFUSE_FLASH_TYPE_ERR_S  23
-/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE..*/
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x1
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Indicates a programming error of SECURE_BOOT_EN..*/
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x1
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/* EFUSE_CRYPT_DPA_ENABLE_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Indicates a programming error of CRYPT_DPA_ENABLE..*/
-#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x1
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
-/* EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K..*/
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x1
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
-/* EFUSE_SEC_DPA_LEVEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: Indicates a programming error of SEC_DPA_LEVEL..*/
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  ((EFUSE_SEC_DPA_LEVEL_ERR_V)<<(EFUSE_SEC_DPA_LEVEL_ERR_S))
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x3
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */
-/*description: Indicates a programming error of KEY_PURPOSE_5..*/
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000F
-#define EFUSE_KEY_PURPOSE_5_ERR_M  ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S))
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0xF
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */
-/*description: Indicates a programming error of KEY_PURPOSE_4..*/
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000F
-#define EFUSE_KEY_PURPOSE_4_ERR_M  ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S))
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0xF
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */
-/*description: Indicates a programming error of KEY_PURPOSE_3..*/
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000F
-#define EFUSE_KEY_PURPOSE_3_ERR_M  ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S))
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0xF
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: Indicates a programming error of KEY_PURPOSE_2..*/
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000F
-#define EFUSE_KEY_PURPOSE_2_ERR_M  ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S))
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0xF
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_2.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_3.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_4.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_5.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of SEC_DPA_LEVEL.
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
+/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of CRYPT_DPA_ENABLE.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_EN.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of FLASH_TYPE.
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  23
+/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0;
+ *  Indicates a programming error of FLASH_PAGE_SIZE.
+ */
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
+/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of FLASH_ECC_EN.
+ */
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_ERR_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of FLASH_TPUW.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
 
-#define EFUSE_RD_REPEAT_ERR3_REG          (DR_REG_EFUSE_BASE + 0x188)
-/* EFUSE_DCDC_VSET_ERR : RO ;bitpos:[31:27] ;default: 5'h0 ; */
-/*description: Indicates a programming error of DCDC_VSET..*/
-#define EFUSE_DCDC_VSET_ERR    0x0000001F
-#define EFUSE_DCDC_VSET_ERR_M  ((EFUSE_DCDC_VSET_ERR_V)<<(EFUSE_DCDC_VSET_ERR_S))
-#define EFUSE_DCDC_VSET_ERR_V  0x1F
-#define EFUSE_DCDC_VSET_ERR_S  27
-/* EFUSE_HYS_EN_PAD_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Indicates a programming error of HYS_EN_PAD..*/
-#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
-#define EFUSE_HYS_EN_PAD_ERR_M  (BIT(26))
-#define EFUSE_HYS_EN_PAD_ERR_V  0x1
-#define EFUSE_HYS_EN_PAD_ERR_S  26
-/* EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE..*/
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x1
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
-/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[24:9] ;default: 16'h0 ; */
-/*description: Indicates a programming error of SECURE VERSION..*/
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFF
-#define EFUSE_SECURE_VERSION_ERR_M  ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S))
-#define EFUSE_SECURE_VERSION_ERR_V  0xFFFF
-#define EFUSE_SECURE_VERSION_ERR_S  9
-/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Indicates a programming error of FORCE_SEND_RESUME..*/
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x1
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
-/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: Indicates a programming error of UART_PRINT_CONTROL..*/
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S))
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x3
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Indicates a programming error of ENABLE_SECURITY_DOWNLOAD..*/
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x1
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE..*/
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x1
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
-/* EFUSE_LOCK_KM_KEY_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: TBD.*/
-#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_ERR_M  (BIT(3))
-#define EFUSE_LOCK_KM_KEY_ERR_V  0x1
-#define EFUSE_LOCK_KM_KEY_ERR_S  3
-/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR..*/
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x1
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
-/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_DIRECT_BOOT..*/
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x1
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_DOWNLOAD_MODE..*/
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+ */
 #define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Indicates a programming error of DIS_DIRECT_BOOT.
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
+/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
+#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_ERR_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CONTROL.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of FORCE_SEND_RESUME.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
+ *  Indicates a programming error of SECURE VERSION.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
+/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of HYS_EN_PAD.
+ */
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
+#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
+#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_ERR_S  26
+/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0;
+ *  Indicates a programming error of DCDC_VSET.
+ */
+#define EFUSE_DCDC_VSET_ERR    0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_M  (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S)
+#define EFUSE_DCDC_VSET_ERR_V  0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_S  27
 
-#define EFUSE_RD_REPEAT_ERR4_REG          (DR_REG_EFUSE_BASE + 0x18C)
-/* EFUSE_DIS_SWD_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_SWD..*/
-#define EFUSE_DIS_SWD_ERR    (BIT(21))
-#define EFUSE_DIS_SWD_ERR_M  (BIT(21))
-#define EFUSE_DIS_SWD_ERR_V  0x1
-#define EFUSE_DIS_SWD_ERR_S  21
-/* EFUSE_DIS_WDT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DIS_WDT..*/
-#define EFUSE_DIS_WDT_ERR    (BIT(20))
-#define EFUSE_DIS_WDT_ERR_M  (BIT(20))
-#define EFUSE_DIS_WDT_ERR_V  0x1
-#define EFUSE_DIS_WDT_ERR_S  20
-/* EFUSE_DCDC_VSET_EN_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Indicates a programming error of DCDC_VSET_EN..*/
-#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_ERR_M  (BIT(19))
-#define EFUSE_DCDC_VSET_EN_ERR_V  0x1
-#define EFUSE_DCDC_VSET_EN_ERR_S  19
-/* EFUSE_HP_PWR_SRC_SEL_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Indicates a programming error of HP_PWR_SRC_SEL..*/
-#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x1
-#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
-/* EFUSE_USB_OTG11_DREFL_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: Indicates a programming error of USB_OTG11_DREFL..*/
-#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003
-#define EFUSE_USB_OTG11_DREFL_ERR_M  ((EFUSE_USB_OTG11_DREFL_ERR_V)<<(EFUSE_USB_OTG11_DREFL_ERR_S))
-#define EFUSE_USB_OTG11_DREFL_ERR_V  0x3
-#define EFUSE_USB_OTG11_DREFL_ERR_S  14
-/* EFUSE_USB_DEVICE_DREFL_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: Indicates a programming error of USB_DEVICE_DREFL..*/
-#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003
-#define EFUSE_USB_DEVICE_DREFL_ERR_M  ((EFUSE_USB_DEVICE_DREFL_ERR_V)<<(EFUSE_USB_DEVICE_DREFL_ERR_S))
-#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x3
-#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
-/* EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */
-/*description: TBD..*/
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000F
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  ((EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V)<<(EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S))
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0xF
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
-/* EFUSE_0PXA_TIEH_SEL_3_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: Indicates a programming error of 0PXA_TIEH_SEL_3..*/
-#define EFUSE_0PXA_TIEH_SEL_3_ERR    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_M  ((EFUSE_0PXA_TIEH_SEL_3_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_3_ERR_S))
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_V  0x3
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_S  6
-/* EFUSE_0PXA_TIEH_SEL_2_ERR : RO ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: Indicates a programming error of 0PXA_TIEH_SEL_2..*/
-#define EFUSE_0PXA_TIEH_SEL_2_ERR    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_M  ((EFUSE_0PXA_TIEH_SEL_2_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_2_ERR_S))
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_V  0x3
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_S  4
-/* EFUSE_0PXA_TIEH_SEL_1_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: Indicates a programming error of 0PXA_TIEH_SEL_1..*/
-#define EFUSE_0PXA_TIEH_SEL_1_ERR    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_M  ((EFUSE_0PXA_TIEH_SEL_1_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_1_ERR_S))
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_V  0x3
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_S  2
-/* EFUSE_0PXA_TIEH_SEL_0_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: Indicates a programming error of 0PXA_TIEH_SEL_0..*/
-#define EFUSE_0PXA_TIEH_SEL_0_ERR    0x00000003
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_M  ((EFUSE_0PXA_TIEH_SEL_0_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_0_ERR_S))
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_V  0x3
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
+/** EFUSE_0PXA_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+ */
+#define EFUSE_0PXA_TIEH_SEL_0_ERR    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_0_ERR_M  (EFUSE_0PXA_TIEH_SEL_0_ERR_V << EFUSE_0PXA_TIEH_SEL_0_ERR_S)
+#define EFUSE_0PXA_TIEH_SEL_0_ERR_V  0x00000003U
 #define EFUSE_0PXA_TIEH_SEL_0_ERR_S  0
+/** EFUSE_0PXA_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+ */
+#define EFUSE_0PXA_TIEH_SEL_1_ERR    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_1_ERR_M  (EFUSE_0PXA_TIEH_SEL_1_ERR_V << EFUSE_0PXA_TIEH_SEL_1_ERR_S)
+#define EFUSE_0PXA_TIEH_SEL_1_ERR_V  0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_1_ERR_S  2
+/** EFUSE_0PXA_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+ */
+#define EFUSE_0PXA_TIEH_SEL_2_ERR    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_2_ERR_M  (EFUSE_0PXA_TIEH_SEL_2_ERR_V << EFUSE_0PXA_TIEH_SEL_2_ERR_S)
+#define EFUSE_0PXA_TIEH_SEL_2_ERR_V  0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_2_ERR_S  4
+/** EFUSE_0PXA_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+ */
+#define EFUSE_0PXA_TIEH_SEL_3_ERR    0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_3_ERR_M  (EFUSE_0PXA_TIEH_SEL_3_ERR_V << EFUSE_0PXA_TIEH_SEL_3_ERR_S)
+#define EFUSE_0PXA_TIEH_SEL_3_ERR_V  0x00000003U
+#define EFUSE_0PXA_TIEH_SEL_3_ERR_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
+/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFL.
+ */
+#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_M  (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S)
+#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
+/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFL.
+ */
+#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_M  (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S)
+#define EFUSE_USB_OTG11_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_S  14
+/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of HP_PWR_SRC_SEL.
+ */
+#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S)
+#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
+/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DCDC_VSET_EN.
+ */
+#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
+#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_ERR_S  19
+/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_WDT.
+ */
+#define EFUSE_DIS_WDT_ERR    (BIT(20))
+#define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
+#define EFUSE_DIS_WDT_ERR_V  0x00000001U
+#define EFUSE_DIS_WDT_ERR_S  20
+/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of DIS_SWD.
+ */
+#define EFUSE_DIS_SWD_ERR    (BIT(21))
+#define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
+#define EFUSE_DIS_SWD_ERR_V  0x00000001U
+#define EFUSE_DIS_SWD_ERR_S  21
 
-#define EFUSE_RD_RS_ERR0_REG          (DR_REG_EFUSE_BASE + 0x1C0)
-/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of key4 is reliable 1: Means that programm
-ing key4 failed and the number of error bytes is over 6..*/
-#define EFUSE_KEY4_FAIL    (BIT(31))
-#define EFUSE_KEY4_FAIL_M  (BIT(31))
-#define EFUSE_KEY4_FAIL_V  0x1
-#define EFUSE_KEY4_FAIL_S  31
-/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_KEY4_ERR_NUM    0x00000007
-#define EFUSE_KEY4_ERR_NUM_M  ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S))
-#define EFUSE_KEY4_ERR_NUM_V  0x7
-#define EFUSE_KEY4_ERR_NUM_S  28
-/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of key3 is reliable 1: Means that programm
-ing key3 failed and the number of error bytes is over 6..*/
-#define EFUSE_KEY3_FAIL    (BIT(27))
-#define EFUSE_KEY3_FAIL_M  (BIT(27))
-#define EFUSE_KEY3_FAIL_V  0x1
-#define EFUSE_KEY3_FAIL_S  27
-/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_KEY3_ERR_NUM    0x00000007
-#define EFUSE_KEY3_ERR_NUM_M  ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S))
-#define EFUSE_KEY3_ERR_NUM_V  0x7
-#define EFUSE_KEY3_ERR_NUM_S  24
-/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of key2 is reliable 1: Means that programm
-ing key2 failed and the number of error bytes is over 6..*/
-#define EFUSE_KEY2_FAIL    (BIT(23))
-#define EFUSE_KEY2_FAIL_M  (BIT(23))
-#define EFUSE_KEY2_FAIL_V  0x1
-#define EFUSE_KEY2_FAIL_S  23
-/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_KEY2_ERR_NUM    0x00000007
-#define EFUSE_KEY2_ERR_NUM_M  ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S))
-#define EFUSE_KEY2_ERR_NUM_V  0x7
-#define EFUSE_KEY2_ERR_NUM_S  20
-/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of key1 is reliable 1: Means that programm
-ing key1 failed and the number of error bytes is over 6..*/
-#define EFUSE_KEY1_FAIL    (BIT(19))
-#define EFUSE_KEY1_FAIL_M  (BIT(19))
-#define EFUSE_KEY1_FAIL_V  0x1
-#define EFUSE_KEY1_FAIL_S  19
-/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_KEY1_ERR_NUM    0x00000007
-#define EFUSE_KEY1_ERR_NUM_M  ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S))
-#define EFUSE_KEY1_ERR_NUM_V  0x7
-#define EFUSE_KEY1_ERR_NUM_S  16
-/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of key0 is reliable 1: Means that programm
-ing key0 failed and the number of error bytes is over 6..*/
-#define EFUSE_KEY0_FAIL    (BIT(15))
-#define EFUSE_KEY0_FAIL_M  (BIT(15))
-#define EFUSE_KEY0_FAIL_V  0x1
-#define EFUSE_KEY0_FAIL_S  15
-/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_KEY0_ERR_NUM    0x00000007
-#define EFUSE_KEY0_ERR_NUM_M  ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S))
-#define EFUSE_KEY0_ERR_NUM_V  0x7
-#define EFUSE_KEY0_ERR_NUM_S  12
-/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the user data is reliable 1: Means that programming
- user data failed and the number of error bytes is over 6..*/
-#define EFUSE_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_USR_DATA_FAIL_M  (BIT(11))
-#define EFUSE_USR_DATA_FAIL_V  0x1
-#define EFUSE_USR_DATA_FAIL_S  11
-/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007
-#define EFUSE_USR_DATA_ERR_NUM_M  ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S))
-#define EFUSE_USR_DATA_ERR_NUM_V  0x7
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of system part1 is reliable 1: Means that
-programming user data failed and the number of error bytes is over 6..*/
-#define EFUSE_SYS_PART1_FAIL    (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_M  (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_V  0x1
-#define EFUSE_SYS_PART1_FAIL_S  7
-/* EFUSE_SYS_PART1_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_SYS_PART1_ERR_NUM    0x00000007
-#define EFUSE_SYS_PART1_ERR_NUM_M  ((EFUSE_SYS_PART1_ERR_NUM_V)<<(EFUSE_SYS_PART1_ERR_NUM_S))
-#define EFUSE_SYS_PART1_ERR_NUM_V  0x7
-#define EFUSE_SYS_PART1_ERR_NUM_S  4
-/* EFUSE_MAC_SYS_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that pr
-ogramming user data failed and the number of error bytes is over 6..*/
-#define EFUSE_MAC_SYS_FAIL    (BIT(3))
-#define EFUSE_MAC_SYS_FAIL_M  (BIT(3))
-#define EFUSE_MAC_SYS_FAIL_V  0x1
-#define EFUSE_MAC_SYS_FAIL_S  3
-/* EFUSE_MAC_SYS_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_MAC_SYS_ERR_NUM    0x00000007
-#define EFUSE_MAC_SYS_ERR_NUM_M  ((EFUSE_MAC_SYS_ERR_NUM_V)<<(EFUSE_MAC_SYS_ERR_NUM_S))
-#define EFUSE_MAC_SYS_ERR_NUM_V  0x7
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SYS_ERR_NUM_M  (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S)
+#define EFUSE_MAC_SYS_ERR_NUM_V  0x00000007U
 #define EFUSE_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_MAC_SYS_FAIL_M  (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S)
+#define EFUSE_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_MAC_SYS_FAIL_S  3
+/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_M  (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S)
+#define EFUSE_SYS_PART1_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
 
-#define EFUSE_RD_RS_ERR1_REG          (DR_REG_EFUSE_BASE + 0x1C4)
-/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of system part2 is reliable 1: Means that
-programming user data failed and the number of error bytes is over 6..*/
-#define EFUSE_SYS_PART2_FAIL    (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_M  (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_V  0x1
-#define EFUSE_SYS_PART2_FAIL_S  7
-/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007
-#define EFUSE_SYS_PART2_ERR_NUM_M  ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S))
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x7
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 0: Means no failure and that the data of key5 is reliable 1: Means that programm
-ing key5 failed and the number of error bytes is over 6..*/
-#define EFUSE_KEY5_FAIL    (BIT(3))
-#define EFUSE_KEY5_FAIL_M  (BIT(3))
-#define EFUSE_KEY5_FAIL_V  0x1
-#define EFUSE_KEY5_FAIL_S  3
-/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: The value of this signal means the number of error bytes..*/
-#define EFUSE_KEY5_ERR_NUM    0x00000007
-#define EFUSE_KEY5_ERR_NUM_M  ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S))
-#define EFUSE_KEY5_ERR_NUM_V  0x7
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
 #define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+ *  key5 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
 
-#define EFUSE_CLK_REG          (DR_REG_EFUSE_BASE + 0x1C8)
-/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to force enable eFuse register configuration clock signal..*/
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (BIT(16))
-#define EFUSE_CLK_EN_V  0x1
-#define EFUSE_CLK_EN_S  16
-/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to force eFuse SRAM into working mode..*/
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (BIT(2))
-#define EFUSE_MEM_FORCE_PU_V  0x1
-#define EFUSE_MEM_FORCE_PU_S  2
-/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x1
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to force eFuse SRAM into power-saving mode..*/
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
 #define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (BIT(0))
-#define EFUSE_MEM_FORCE_PD_V  0x1
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
 #define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
 
-#define EFUSE_CONF_REG          (DR_REG_EFUSE_BASE + 0x1CC)
-/* EFUSE_CFG_ECDSA_BLK : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
-/*description: Configures which block to use for ECDSA key output..*/
-#define EFUSE_CFG_ECDSA_BLK    0x0000000F
-#define EFUSE_CFG_ECDSA_BLK_M  ((EFUSE_CFG_ECDSA_BLK_V)<<(EFUSE_CFG_ECDSA_BLK_S))
-#define EFUSE_CFG_ECDSA_BLK_V  0xF
-#define EFUSE_CFG_ECDSA_BLK_S  16
-/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: 0x5A5A:  programming operation command 0x5AA5: read operation command..*/
-#define EFUSE_OP_CODE    0x0000FFFF
-#define EFUSE_OP_CODE_M  ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
-#define EFUSE_OP_CODE_V  0xFFFF
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuraiton register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
 #define EFUSE_OP_CODE_S  0
+/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
+ *  Configures which block to use for ECDSA key output.
+ */
+#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
+#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_S  16
 
-#define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x1D0)
-/* EFUSE_CUR_ECDSA_BLK : RO ;bitpos:[23:20] ;default: 4'h0 ; */
-/*description: Indicates which block is used for ECDSA key output..*/
-#define EFUSE_CUR_ECDSA_BLK    0x0000000F
-#define EFUSE_CUR_ECDSA_BLK_M  ((EFUSE_CUR_ECDSA_BLK_V)<<(EFUSE_CUR_ECDSA_BLK_S))
-#define EFUSE_CUR_ECDSA_BLK_V  0xF
-#define EFUSE_CUR_ECDSA_BLK_S  20
-/* EFUSE_BLK0_VALID_BIT_CNT : RO ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: Indicates the number of block valid bit..*/
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FF
-#define EFUSE_BLK0_VALID_BIT_CNT_M  ((EFUSE_BLK0_VALID_BIT_CNT_V)<<(EFUSE_BLK0_VALID_BIT_CNT_S))
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x3FF
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The value of OTP_VDDQ_IS_SW..*/
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x1
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The value of OTP_PGENB_SW..*/
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (BIT(8))
-#define EFUSE_OTP_PGENB_SW_V  0x1
-#define EFUSE_OTP_PGENB_SW_S  8
-/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The value of OTP_CSB_SW..*/
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (BIT(7))
-#define EFUSE_OTP_CSB_SW_V  0x1
-#define EFUSE_OTP_CSB_SW_S  7
-/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The value of OTP_STROBE_SW..*/
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (BIT(6))
-#define EFUSE_OTP_STROBE_SW_V  0x1
-#define EFUSE_OTP_STROBE_SW_S  6
-/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The value of OTP_VDDQ_C_SYNC2..*/
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x1
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The value of OTP_LOAD_SW..*/
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (BIT(4))
-#define EFUSE_OTP_LOAD_SW_V  0x1
-#define EFUSE_OTP_LOAD_SW_S  4
-/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: Indicates the state of the eFuse state machine..*/
-#define EFUSE_STATE    0x0000000F
-#define EFUSE_STATE_M  ((EFUSE_STATE_V)<<(EFUSE_STATE_S))
-#define EFUSE_STATE_V  0xF
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
 #define EFUSE_STATE_S  0
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Indicates which block is used for ECDSA key output.
+ */
+#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
+#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_S  20
 
-#define EFUSE_CMD_REG          (DR_REG_EFUSE_BASE + 0x1D4)
-/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */
-/*description: The serial number of the block to be programmed. Value 0-10 corresponds to block
- number 0-10, respectively..*/
-#define EFUSE_BLK_NUM    0x0000000F
-#define EFUSE_BLK_NUM_M  ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S))
-#define EFUSE_BLK_NUM_V  0xF
-#define EFUSE_BLK_NUM_S  2
-/* EFUSE_PGM_CMD : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to send programming command..*/
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (BIT(1))
-#define EFUSE_PGM_CMD_V  0x1
-#define EFUSE_PGM_CMD_S  1
-/* EFUSE_READ_CMD : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to send read command..*/
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
 #define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (BIT(0))
-#define EFUSE_READ_CMD_V  0x1
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
 #define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
 
-#define EFUSE_INT_RAW_REG          (DR_REG_EFUSE_BASE + 0x1D8)
-/* EFUSE_PGM_DONE_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit signal for pgm_done interrupt..*/
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_V  0x1
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-/* EFUSE_READ_DONE_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit signal for read_done interrupt..*/
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
 #define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_V  0x1
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
 #define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
 
-#define EFUSE_INT_ST_REG          (DR_REG_EFUSE_BASE + 0x1DC)
-/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status signal for pgm_done interrupt..*/
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_V  0x1
-#define EFUSE_PGM_DONE_INT_ST_S  1
-/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status signal for read_done interrupt..*/
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
 #define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_V  0x1
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
 #define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
 
-#define EFUSE_INT_ENA_REG          (DR_REG_EFUSE_BASE + 0x1E0)
-/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable signal for pgm_done interrupt..*/
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_V  0x1
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable signal for read_done interrupt..*/
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
 #define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_V  0x1
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
 #define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
 
-#define EFUSE_INT_CLR_REG          (DR_REG_EFUSE_BASE + 0x1E4)
-/* EFUSE_PGM_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear signal for pgm_done interrupt..*/
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_V  0x1
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-/* EFUSE_READ_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear signal for read_done interrupt..*/
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
 #define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_V  0x1
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
 #define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
 
-#define EFUSE_DAC_CONF_REG          (DR_REG_EFUSE_BASE + 0x1E8)
-/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Reduces the power supply of the programming voltage..*/
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (BIT(17))
-#define EFUSE_OE_CLR_V  0x1
-#define EFUSE_OE_CLR_S  17
-/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */
-/*description: Controls the rising period of the programming voltage..*/
-#define EFUSE_DAC_NUM    0x000000FF
-#define EFUSE_DAC_NUM_M  ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S))
-#define EFUSE_DAC_NUM_V  0xFF
-#define EFUSE_DAC_NUM_S  9
-/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Don't care..*/
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x1
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd23 ; */
-/*description: Controls the division factor of the rising clock of the programming voltage..*/
-#define EFUSE_DAC_CLK_DIV    0x000000FF
-#define EFUSE_DAC_CLK_DIV_M  ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
-#define EFUSE_DAC_CLK_DIV_V  0xFF
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
 #define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
 
-#define EFUSE_RD_TIM_CONF_REG          (DR_REG_EFUSE_BASE + 0x1EC)
-/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'hf ; */
-/*description: Configures the waiting time of reading eFuse memory..*/
-#define EFUSE_READ_INIT_NUM    0x000000FF
-#define EFUSE_READ_INIT_NUM_M  ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S))
-#define EFUSE_READ_INIT_NUM_V  0xFF
-#define EFUSE_READ_INIT_NUM_S  24
-/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
-/*description: Configures the read setup time..*/
-#define EFUSE_TSUR_A    0x000000FF
-#define EFUSE_TSUR_A_M  ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S))
-#define EFUSE_TSUR_A_V  0xFF
-#define EFUSE_TSUR_A_S  16
-/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
-/*description: Configures the read time..*/
-#define EFUSE_TRD    0x000000FF
-#define EFUSE_TRD_M  ((EFUSE_TRD_V)<<(EFUSE_TRD_S))
-#define EFUSE_TRD_V  0xFF
-#define EFUSE_TRD_S  8
-/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
-/*description: Configures the read hold time..*/
-#define EFUSE_THR_A    0x000000FF
-#define EFUSE_THR_A_M  ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S))
-#define EFUSE_THR_A_V  0xFF
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
 #define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
 
-#define EFUSE_WR_TIM_CONF1_REG          (DR_REG_EFUSE_BASE + 0x1F0)
-/* EFUSE_THP_A : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
-/*description: Configures the programming hold time..*/
-#define EFUSE_THP_A    0x000000FF
-#define EFUSE_THP_A_M  ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S))
-#define EFUSE_THP_A_V  0xFF
-#define EFUSE_THP_A_S  24
-/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2667 ; */
-/*description: Configures the power up time for VDDQ..*/
-#define EFUSE_PWR_ON_NUM    0x0000FFFF
-#define EFUSE_PWR_ON_NUM_M  ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S))
-#define EFUSE_PWR_ON_NUM_V  0xFFFF
-#define EFUSE_PWR_ON_NUM_S  8
-/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
-/*description: Configures the programming setup time..*/
-#define EFUSE_TSUP_A    0x000000FF
-#define EFUSE_TSUP_A_M  ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S))
-#define EFUSE_TSUP_A_V  0xFF
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
 #define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
 
-#define EFUSE_WR_TIM_CONF2_REG          (DR_REG_EFUSE_BASE + 0x1F4)
-/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'ha0 ; */
-/*description: Configures the active programming time..*/
-#define EFUSE_TPGM    0x0000FFFF
-#define EFUSE_TPGM_M  ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S))
-#define EFUSE_TPGM_V  0xFFFF
-#define EFUSE_TPGM_S  16
-/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h140 ; */
-/*description: Configures the power outage time for VDDQ..*/
-#define EFUSE_PWR_OFF_NUM    0x0000FFFF
-#define EFUSE_PWR_OFF_NUM_M  ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S))
-#define EFUSE_PWR_OFF_NUM_V  0xFFFF
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
 #define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
 
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG          (DR_REG_EFUSE_BASE + 0x1F8)
-/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[20:13] ;default: 8'h1 ; */
-/*description: Configures the inactive programming time..*/
-#define EFUSE_TPGM_INACTIVE    0x000000FF
-#define EFUSE_TPGM_INACTIVE_M  ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S))
-#define EFUSE_TPGM_INACTIVE_V  0xFF
-#define EFUSE_TPGM_INACTIVE_S  13
-/* EFUSE_UPDATE : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to update multi-bit register signals..*/
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (BIT(12))
-#define EFUSE_UPDATE_V  0x1
-#define EFUSE_UPDATE_S  12
-/* EFUSE_BYPASS_RS_BLK_NUM : R/W ;bitpos:[11:1] ;default: 11'h0 ; */
-/*description: Configures block number of programming twice operation..*/
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FF
-#define EFUSE_BYPASS_RS_BLK_NUM_M  ((EFUSE_BYPASS_RS_BLK_NUM_V)<<(EFUSE_BYPASS_RS_BLK_NUM_S))
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x7FF
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/* EFUSE_BYPASS_RS_CORRECTION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to bypass reed solomon correction step..*/
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
 #define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x1
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
 #define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
 
-#define EFUSE_DATE_REG          (DR_REG_EFUSE_BASE + 0x1FC)
-/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2305050 ; */
-/*description: Stores eFuse version..*/
-#define EFUSE_DATE    0x0FFFFFFF
-#define EFUSE_DATE_M  ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
-#define EFUSE_DATE_V  0xFFFFFFF
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
 #define EFUSE_DATE_S  0
 
-#define EFUSE_APB2OTP_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x800)
-/* EFUSE_APB2OTP_BLOCK0_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 write disable data..*/
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  ((EFUSE_APB2OTP_BLOCK0_WR_DIS_V)<<(EFUSE_APB2OTP_BLOCK0_WR_DIS_S))
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_WR_DIS_REG register
+ *  eFuse apb2otp block0 data register1.
+ */
+#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800)
+/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 write disable data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG          (DR_REG_EFUSE_BASE + 0x804)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup1 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
+ *  eFuse apb2otp block0 data register2.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG          (DR_REG_EFUSE_BASE + 0x808)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup1 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
+ *  eFuse apb2otp block0 data register3.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG          (DR_REG_EFUSE_BASE + 0x80C)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup1 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
+ *  eFuse apb2otp block0 data register4.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG          (DR_REG_EFUSE_BASE + 0x810)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup1 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
+ *  eFuse apb2otp block0 data register5.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG          (DR_REG_EFUSE_BASE + 0x814)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup1 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
+ *  eFuse apb2otp block0 data register6.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG          (DR_REG_EFUSE_BASE + 0x818)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup2 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
+ *  eFuse apb2otp block0 data register7.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG          (DR_REG_EFUSE_BASE + 0x81C)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup2 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
+ *  eFuse apb2otp block0 data register8.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG          (DR_REG_EFUSE_BASE + 0x820)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup2 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
+ *  eFuse apb2otp block0 data register9.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG          (DR_REG_EFUSE_BASE + 0x824)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup2 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
+ *  eFuse apb2otp block0 data register10.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG          (DR_REG_EFUSE_BASE + 0x828)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup2 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
+ *  eFuse apb2otp block0 data register11.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG          (DR_REG_EFUSE_BASE + 0x82C)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup3 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
+ *  eFuse apb2otp block0 data register12.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG          (DR_REG_EFUSE_BASE + 0x830)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup3 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
+ *  eFuse apb2otp block0 data register13.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG          (DR_REG_EFUSE_BASE + 0x834)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup3 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
+ *  eFuse apb2otp block0 data register14.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG          (DR_REG_EFUSE_BASE + 0x838)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup3 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
+ *  eFuse apb2otp block0 data register15.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG          (DR_REG_EFUSE_BASE + 0x83C)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup3 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
+ *  eFuse apb2otp block0 data register16.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG          (DR_REG_EFUSE_BASE + 0x840)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup4 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
+ *  eFuse apb2otp block0 data register17.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG          (DR_REG_EFUSE_BASE + 0x844)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup4 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
+ *  eFuse apb2otp block0 data register18.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG          (DR_REG_EFUSE_BASE + 0x848)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup4 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
+ *  eFuse apb2otp block0 data register19.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG          (DR_REG_EFUSE_BASE + 0x84C)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup4 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
+ *  eFuse apb2otp block0 data register20.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
 
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG          (DR_REG_EFUSE_BASE + 0x850)
-/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block0 backup4 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S))
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
+ *  eFuse apb2otp block0 data register21.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
 
-#define EFUSE_APB2OTP_BLK1_W1_REG          (DR_REG_EFUSE_BASE + 0x854)
-/* EFUSE_APB2OTP_BLOCK1_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word1 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W1_M  ((EFUSE_APB2OTP_BLOCK1_W1_V)<<(EFUSE_APB2OTP_BLOCK1_W1_S))
-#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W1_REG register
+ *  eFuse apb2otp block1 data register1.
+ */
+#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854)
+/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
+#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W1_S  0
 
-#define EFUSE_APB2OTP_BLK1_W2_REG          (DR_REG_EFUSE_BASE + 0x858)
-/* EFUSE_APB2OTP_BLOCK1_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word2 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W2_M  ((EFUSE_APB2OTP_BLOCK1_W2_V)<<(EFUSE_APB2OTP_BLOCK1_W2_S))
-#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W2_REG register
+ *  eFuse apb2otp block1 data register2.
+ */
+#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858)
+/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
+#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W2_S  0
 
-#define EFUSE_APB2OTP_BLK1_W3_REG          (DR_REG_EFUSE_BASE + 0x85C)
-/* EFUSE_APB2OTP_BLOCK1_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word3 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W3_M  ((EFUSE_APB2OTP_BLOCK1_W3_V)<<(EFUSE_APB2OTP_BLOCK1_W3_S))
-#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W3_REG register
+ *  eFuse apb2otp block1 data register3.
+ */
+#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c)
+/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
+#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W3_S  0
 
-#define EFUSE_APB2OTP_BLK1_W4_REG          (DR_REG_EFUSE_BASE + 0x860)
-/* EFUSE_APB2OTP_BLOCK1_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word4 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W4_M  ((EFUSE_APB2OTP_BLOCK1_W4_V)<<(EFUSE_APB2OTP_BLOCK1_W4_S))
-#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W4_REG register
+ *  eFuse apb2otp block1 data register4.
+ */
+#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860)
+/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
+#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W4_S  0
 
-#define EFUSE_APB2OTP_BLK1_W5_REG          (DR_REG_EFUSE_BASE + 0x864)
-/* EFUSE_APB2OTP_BLOCK1_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word5 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W5_M  ((EFUSE_APB2OTP_BLOCK1_W5_V)<<(EFUSE_APB2OTP_BLOCK1_W5_S))
-#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W5_REG register
+ *  eFuse apb2otp block1 data register5.
+ */
+#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864)
+/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
+#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W5_S  0
 
-#define EFUSE_APB2OTP_BLK1_W6_REG          (DR_REG_EFUSE_BASE + 0x868)
-/* EFUSE_APB2OTP_BLOCK1_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word6 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W6_M  ((EFUSE_APB2OTP_BLOCK1_W6_V)<<(EFUSE_APB2OTP_BLOCK1_W6_S))
-#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W6_REG register
+ *  eFuse apb2otp block1 data register6.
+ */
+#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868)
+/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
+#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W6_S  0
 
-#define EFUSE_APB2OTP_BLK1_W7_REG          (DR_REG_EFUSE_BASE + 0x86C)
-/* EFUSE_APB2OTP_BLOCK1_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word7 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W7_M  ((EFUSE_APB2OTP_BLOCK1_W7_V)<<(EFUSE_APB2OTP_BLOCK1_W7_S))
-#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W7_REG register
+ *  eFuse apb2otp block1 data register7.
+ */
+#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c)
+/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
+#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W7_S  0
 
-#define EFUSE_APB2OTP_BLK1_W8_REG          (DR_REG_EFUSE_BASE + 0x870)
-/* EFUSE_APB2OTP_BLOCK1_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word8 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W8_M  ((EFUSE_APB2OTP_BLOCK1_W8_V)<<(EFUSE_APB2OTP_BLOCK1_W8_S))
-#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W8_REG register
+ *  eFuse apb2otp block1 data register8.
+ */
+#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870)
+/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
+#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W8_S  0
 
-#define EFUSE_APB2OTP_BLK1_W9_REG          (DR_REG_EFUSE_BASE + 0x874)
-/* EFUSE_APB2OTP_BLOCK1_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block1  word9 data..*/
-#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK1_W9_M  ((EFUSE_APB2OTP_BLOCK1_W9_V)<<(EFUSE_APB2OTP_BLOCK1_W9_S))
-#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK1_W9_REG register
+ *  eFuse apb2otp block1 data register9.
+ */
+#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874)
+/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
+#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK1_W9_S  0
 
-#define EFUSE_APB2OTP_BLK2_W1_REG          (DR_REG_EFUSE_BASE + 0x878)
-/* EFUSE_APB2OTP_BLOCK2_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W1_M  ((EFUSE_APB2OTP_BLOCK2_W1_V)<<(EFUSE_APB2OTP_BLOCK2_W1_S))
-#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W1_REG register
+ *  eFuse apb2otp block2 data register1.
+ */
+#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878)
+/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
+#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W1_S  0
 
-#define EFUSE_APB2OTP_BLK2_W2_REG          (DR_REG_EFUSE_BASE + 0x87C)
-/* EFUSE_APB2OTP_BLOCK2_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W2_M  ((EFUSE_APB2OTP_BLOCK2_W2_V)<<(EFUSE_APB2OTP_BLOCK2_W2_S))
-#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W2_REG register
+ *  eFuse apb2otp block2 data register2.
+ */
+#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c)
+/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
+#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W2_S  0
 
-#define EFUSE_APB2OTP_BLK2_W3_REG          (DR_REG_EFUSE_BASE + 0x880)
-/* EFUSE_APB2OTP_BLOCK2_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W3_M  ((EFUSE_APB2OTP_BLOCK2_W3_V)<<(EFUSE_APB2OTP_BLOCK2_W3_S))
-#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W3_REG register
+ *  eFuse apb2otp block2 data register3.
+ */
+#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880)
+/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
+#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W3_S  0
 
-#define EFUSE_APB2OTP_BLK2_W4_REG          (DR_REG_EFUSE_BASE + 0x884)
-/* EFUSE_APB2OTP_BLOCK2_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W4_M  ((EFUSE_APB2OTP_BLOCK2_W4_V)<<(EFUSE_APB2OTP_BLOCK2_W4_S))
-#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W4_REG register
+ *  eFuse apb2otp block2 data register4.
+ */
+#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884)
+/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
+#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W4_S  0
 
-#define EFUSE_APB2OTP_BLK2_W5_REG          (DR_REG_EFUSE_BASE + 0x888)
-/* EFUSE_APB2OTP_BLOCK2_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W5_M  ((EFUSE_APB2OTP_BLOCK2_W5_V)<<(EFUSE_APB2OTP_BLOCK2_W5_S))
-#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W5_REG register
+ *  eFuse apb2otp block2 data register5.
+ */
+#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888)
+/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
+#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W5_S  0
 
-#define EFUSE_APB2OTP_BLK2_W6_REG          (DR_REG_EFUSE_BASE + 0x88C)
-/* EFUSE_APB2OTP_BLOCK2_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W6_M  ((EFUSE_APB2OTP_BLOCK2_W6_V)<<(EFUSE_APB2OTP_BLOCK2_W6_S))
-#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W6_REG register
+ *  eFuse apb2otp block2 data register6.
+ */
+#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c)
+/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
+#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W6_S  0
 
-#define EFUSE_APB2OTP_BLK2_W7_REG          (DR_REG_EFUSE_BASE + 0x890)
-/* EFUSE_APB2OTP_BLOCK2_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W7_M  ((EFUSE_APB2OTP_BLOCK2_W7_V)<<(EFUSE_APB2OTP_BLOCK2_W7_S))
-#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W7_REG register
+ *  eFuse apb2otp block2 data register7.
+ */
+#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890)
+/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
+#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W7_S  0
 
-#define EFUSE_APB2OTP_BLK2_W8_REG          (DR_REG_EFUSE_BASE + 0x894)
-/* EFUSE_APB2OTP_BLOCK2_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W8_M  ((EFUSE_APB2OTP_BLOCK2_W8_V)<<(EFUSE_APB2OTP_BLOCK2_W8_S))
-#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W8_REG register
+ *  eFuse apb2otp block2 data register8.
+ */
+#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894)
+/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
+#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W8_S  0
 
-#define EFUSE_APB2OTP_BLK2_W9_REG          (DR_REG_EFUSE_BASE + 0x898)
-/* EFUSE_APB2OTP_BLOCK2_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W9_M  ((EFUSE_APB2OTP_BLOCK2_W9_V)<<(EFUSE_APB2OTP_BLOCK2_W9_S))
-#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W9_REG register
+ *  eFuse apb2otp block2 data register9.
+ */
+#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898)
+/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
+#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W9_S  0
 
-#define EFUSE_APB2OTP_BLK2_W10_REG          (DR_REG_EFUSE_BASE + 0x89C)
-/* EFUSE_APB2OTP_BLOCK2_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W10_M  ((EFUSE_APB2OTP_BLOCK2_W10_V)<<(EFUSE_APB2OTP_BLOCK2_W10_S))
-#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W10_REG register
+ *  eFuse apb2otp block2 data register10.
+ */
+#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c)
+/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
+#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W10_S  0
 
-#define EFUSE_APB2OTP_BLK2_W11_REG          (DR_REG_EFUSE_BASE + 0x8A0)
-/* EFUSE_APB2OTP_BLOCK2_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block2 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK2_W11_M  ((EFUSE_APB2OTP_BLOCK2_W11_V)<<(EFUSE_APB2OTP_BLOCK2_W11_S))
-#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK2_W11_REG register
+ *  eFuse apb2otp block2 data register11.
+ */
+#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0)
+/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
+#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK2_W11_S  0
 
-#define EFUSE_APB2OTP_BLK3_W1_REG          (DR_REG_EFUSE_BASE + 0x8A4)
-/* EFUSE_APB2OTP_BLOCK3_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W1_M  ((EFUSE_APB2OTP_BLOCK3_W1_V)<<(EFUSE_APB2OTP_BLOCK3_W1_S))
-#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W1_REG register
+ *  eFuse apb2otp block3 data register1.
+ */
+#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4)
+/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
+#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W1_S  0
 
-#define EFUSE_APB2OTP_BLK3_W2_REG          (DR_REG_EFUSE_BASE + 0x8A8)
-/* EFUSE_APB2OTP_BLOCK3_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W2_M  ((EFUSE_APB2OTP_BLOCK3_W2_V)<<(EFUSE_APB2OTP_BLOCK3_W2_S))
-#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W2_REG register
+ *  eFuse apb2otp block3 data register2.
+ */
+#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8)
+/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
+#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W2_S  0
 
-#define EFUSE_APB2OTP_BLK3_W3_REG          (DR_REG_EFUSE_BASE + 0x8AC)
-/* EFUSE_APB2OTP_BLOCK3_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W3_M  ((EFUSE_APB2OTP_BLOCK3_W3_V)<<(EFUSE_APB2OTP_BLOCK3_W3_S))
-#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W3_REG register
+ *  eFuse apb2otp block3 data register3.
+ */
+#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac)
+/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
+#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W3_S  0
 
-#define EFUSE_APB2OTP_BLK3_W4_REG          (DR_REG_EFUSE_BASE + 0x8B0)
-/* EFUSE_APB2OTP_BLOCK3_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W4_M  ((EFUSE_APB2OTP_BLOCK3_W4_V)<<(EFUSE_APB2OTP_BLOCK3_W4_S))
-#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W4_REG register
+ *  eFuse apb2otp block3 data register4.
+ */
+#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0)
+/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
+#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W4_S  0
 
-#define EFUSE_APB2OTP_BLK3_W5_REG          (DR_REG_EFUSE_BASE + 0x8B4)
-/* EFUSE_APB2OTP_BLOCK3_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W5_M  ((EFUSE_APB2OTP_BLOCK3_W5_V)<<(EFUSE_APB2OTP_BLOCK3_W5_S))
-#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W5_REG register
+ *  eFuse apb2otp block3 data register5.
+ */
+#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4)
+/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
+#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W5_S  0
 
-#define EFUSE_APB2OTP_BLK3_W6_REG          (DR_REG_EFUSE_BASE + 0x8B8)
-/* EFUSE_APB2OTP_BLOCK3_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W6_M  ((EFUSE_APB2OTP_BLOCK3_W6_V)<<(EFUSE_APB2OTP_BLOCK3_W6_S))
-#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W6_REG register
+ *  eFuse apb2otp block3 data register6.
+ */
+#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8)
+/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
+#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W6_S  0
 
-#define EFUSE_APB2OTP_BLK3_W7_REG          (DR_REG_EFUSE_BASE + 0x8BC)
-/* EFUSE_APB2OTP_BLOCK3_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W7_M  ((EFUSE_APB2OTP_BLOCK3_W7_V)<<(EFUSE_APB2OTP_BLOCK3_W7_S))
-#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W7_REG register
+ *  eFuse apb2otp block3 data register7.
+ */
+#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc)
+/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
+#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W7_S  0
 
-#define EFUSE_APB2OTP_BLK3_W8_REG          (DR_REG_EFUSE_BASE + 0x8C0)
-/* EFUSE_APB2OTP_BLOCK3_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W8_M  ((EFUSE_APB2OTP_BLOCK3_W8_V)<<(EFUSE_APB2OTP_BLOCK3_W8_S))
-#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W8_REG register
+ *  eFuse apb2otp block3 data register8.
+ */
+#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0)
+/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
+#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W8_S  0
 
-#define EFUSE_APB2OTP_BLK3_W9_REG          (DR_REG_EFUSE_BASE + 0x8C4)
-/* EFUSE_APB2OTP_BLOCK3_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W9_M  ((EFUSE_APB2OTP_BLOCK3_W9_V)<<(EFUSE_APB2OTP_BLOCK3_W9_S))
-#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W9_REG register
+ *  eFuse apb2otp block3 data register9.
+ */
+#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4)
+/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
+#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W9_S  0
 
-#define EFUSE_APB2OTP_BLK3_W10_REG          (DR_REG_EFUSE_BASE + 0x8C8)
-/* EFUSE_APB2OTP_BLOCK3_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W10_M  ((EFUSE_APB2OTP_BLOCK3_W10_V)<<(EFUSE_APB2OTP_BLOCK3_W10_S))
-#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W10_REG register
+ *  eFuse apb2otp block3 data register10.
+ */
+#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8)
+/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
+#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W10_S  0
 
-#define EFUSE_APB2OTP_BLK3_W11_REG          (DR_REG_EFUSE_BASE + 0x8CC)
-/* EFUSE_APB2OTP_BLOCK3_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block3 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK3_W11_M  ((EFUSE_APB2OTP_BLOCK3_W11_V)<<(EFUSE_APB2OTP_BLOCK3_W11_S))
-#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK3_W11_REG register
+ *  eFuse apb2otp block3 data register11.
+ */
+#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc)
+/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
+#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK3_W11_S  0
 
-#define EFUSE_APB2OTP_BLK4_W1_REG          (DR_REG_EFUSE_BASE + 0x8D0)
-/* EFUSE_APB2OTP_BLOCK4_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W1_M  ((EFUSE_APB2OTP_BLOCK4_W1_V)<<(EFUSE_APB2OTP_BLOCK4_W1_S))
-#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W1_REG register
+ *  eFuse apb2otp block4 data register1.
+ */
+#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0)
+/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
+#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W1_S  0
 
-#define EFUSE_APB2OTP_BLK4_W2_REG          (DR_REG_EFUSE_BASE + 0x8D4)
-/* EFUSE_APB2OTP_BLOCK4_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W2_M  ((EFUSE_APB2OTP_BLOCK4_W2_V)<<(EFUSE_APB2OTP_BLOCK4_W2_S))
-#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W2_REG register
+ *  eFuse apb2otp block4 data register2.
+ */
+#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4)
+/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
+#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W2_S  0
 
-#define EFUSE_APB2OTP_BLK4_W3_REG          (DR_REG_EFUSE_BASE + 0x8D8)
-/* EFUSE_APB2OTP_BLOCK4_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W3_M  ((EFUSE_APB2OTP_BLOCK4_W3_V)<<(EFUSE_APB2OTP_BLOCK4_W3_S))
-#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W3_REG register
+ *  eFuse apb2otp block4 data register3.
+ */
+#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8)
+/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
+#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W3_S  0
 
-#define EFUSE_APB2OTP_BLK4_W4_REG          (DR_REG_EFUSE_BASE + 0x8DC)
-/* EFUSE_APB2OTP_BLOCK4_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W4_M  ((EFUSE_APB2OTP_BLOCK4_W4_V)<<(EFUSE_APB2OTP_BLOCK4_W4_S))
-#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W4_REG register
+ *  eFuse apb2otp block4 data register4.
+ */
+#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc)
+/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
+#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W4_S  0
 
-#define EFUSE_APB2OTP_BLK4_W5_REG          (DR_REG_EFUSE_BASE + 0x8E0)
-/* EFUSE_APB2OTP_BLOCK4_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W5_M  ((EFUSE_APB2OTP_BLOCK4_W5_V)<<(EFUSE_APB2OTP_BLOCK4_W5_S))
-#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W5_REG register
+ *  eFuse apb2otp block4 data register5.
+ */
+#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0)
+/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
+#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W5_S  0
 
-#define EFUSE_APB2OTP_BLK4_W6_REG          (DR_REG_EFUSE_BASE + 0x8E4)
-/* EFUSE_APB2OTP_BLOCK4_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W6_M  ((EFUSE_APB2OTP_BLOCK4_W6_V)<<(EFUSE_APB2OTP_BLOCK4_W6_S))
-#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W6_REG register
+ *  eFuse apb2otp block4 data register6.
+ */
+#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4)
+/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
+#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W6_S  0
 
-#define EFUSE_APB2OTP_BLK4_W7_REG          (DR_REG_EFUSE_BASE + 0x8E8)
-/* EFUSE_APB2OTP_BLOCK4_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W7_M  ((EFUSE_APB2OTP_BLOCK4_W7_V)<<(EFUSE_APB2OTP_BLOCK4_W7_S))
-#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W7_REG register
+ *  eFuse apb2otp block4 data register7.
+ */
+#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8)
+/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
+#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W7_S  0
 
-#define EFUSE_APB2OTP_BLK4_W8_REG          (DR_REG_EFUSE_BASE + 0x8EC)
-/* EFUSE_APB2OTP_BLOCK4_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W8_M  ((EFUSE_APB2OTP_BLOCK4_W8_V)<<(EFUSE_APB2OTP_BLOCK4_W8_S))
-#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W8_REG register
+ *  eFuse apb2otp block4 data register8.
+ */
+#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec)
+/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
+#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W8_S  0
 
-#define EFUSE_APB2OTP_BLK4_W9_REG          (DR_REG_EFUSE_BASE + 0x8F0)
-/* EFUSE_APB2OTP_BLOCK4_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W9_M  ((EFUSE_APB2OTP_BLOCK4_W9_V)<<(EFUSE_APB2OTP_BLOCK4_W9_S))
-#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W9_REG register
+ *  eFuse apb2otp block4 data register9.
+ */
+#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0)
+/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
+#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W9_S  0
 
-#define EFUSE_APB2OTP_BLK4_W10_REG          (DR_REG_EFUSE_BASE + 0x8F4)
-/* EFUSE_APB2OTP_BLOCK4_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W10_M  ((EFUSE_APB2OTP_BLOCK4_W10_V)<<(EFUSE_APB2OTP_BLOCK4_W10_S))
-#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W10_REG register
+ *  eFuse apb2otp block4 data registe10.
+ */
+#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4)
+/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
+#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W10_S  0
 
-#define EFUSE_APB2OTP_BLK4_W11_REG          (DR_REG_EFUSE_BASE + 0x8F8)
-/* EFUSE_APB2OTP_BLOCK4_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block4 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK4_W11_M  ((EFUSE_APB2OTP_BLOCK4_W11_V)<<(EFUSE_APB2OTP_BLOCK4_W11_S))
-#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK4_W11_REG register
+ *  eFuse apb2otp block4 data register11.
+ */
+#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8)
+/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
+#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK4_W11_S  0
 
-#define EFUSE_APB2OTP_BLK5_W1_REG          (DR_REG_EFUSE_BASE + 0x8FC)
-/* EFUSE_APB2OTP_BLOCK5_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W1_M  ((EFUSE_APB2OTP_BLOCK5_W1_V)<<(EFUSE_APB2OTP_BLOCK5_W1_S))
-#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W1_REG register
+ *  eFuse apb2otp block5 data register1.
+ */
+#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc)
+/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
+#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W1_S  0
 
-#define EFUSE_APB2OTP_BLK5_W2_REG          (DR_REG_EFUSE_BASE + 0x900)
-/* EFUSE_APB2OTP_BLOCK5_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W2_M  ((EFUSE_APB2OTP_BLOCK5_W2_V)<<(EFUSE_APB2OTP_BLOCK5_W2_S))
-#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W2_REG register
+ *  eFuse apb2otp block5 data register2.
+ */
+#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900)
+/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
+#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W2_S  0
 
-#define EFUSE_APB2OTP_BLK5_W3_REG          (DR_REG_EFUSE_BASE + 0x904)
-/* EFUSE_APB2OTP_BLOCK5_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W3_M  ((EFUSE_APB2OTP_BLOCK5_W3_V)<<(EFUSE_APB2OTP_BLOCK5_W3_S))
-#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W3_REG register
+ *  eFuse apb2otp block5 data register3.
+ */
+#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904)
+/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
+#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W3_S  0
 
-#define EFUSE_APB2OTP_BLK5_W4_REG          (DR_REG_EFUSE_BASE + 0x908)
-/* EFUSE_APB2OTP_BLOCK5_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W4_M  ((EFUSE_APB2OTP_BLOCK5_W4_V)<<(EFUSE_APB2OTP_BLOCK5_W4_S))
-#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W4_REG register
+ *  eFuse apb2otp block5 data register4.
+ */
+#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908)
+/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
+#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W4_S  0
 
-#define EFUSE_APB2OTP_BLK5_W5_REG          (DR_REG_EFUSE_BASE + 0x90C)
-/* EFUSE_APB2OTP_BLOCK5_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W5_M  ((EFUSE_APB2OTP_BLOCK5_W5_V)<<(EFUSE_APB2OTP_BLOCK5_W5_S))
-#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W5_REG register
+ *  eFuse apb2otp block5 data register5.
+ */
+#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c)
+/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
+#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W5_S  0
 
-#define EFUSE_APB2OTP_BLK5_W6_REG          (DR_REG_EFUSE_BASE + 0x910)
-/* EFUSE_APB2OTP_BLOCK5_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W6_M  ((EFUSE_APB2OTP_BLOCK5_W6_V)<<(EFUSE_APB2OTP_BLOCK5_W6_S))
-#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W6_REG register
+ *  eFuse apb2otp block5 data register6.
+ */
+#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910)
+/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
+#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W6_S  0
 
-#define EFUSE_APB2OTP_BLK5_W7_REG          (DR_REG_EFUSE_BASE + 0x914)
-/* EFUSE_APB2OTP_BLOCK5_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W7_M  ((EFUSE_APB2OTP_BLOCK5_W7_V)<<(EFUSE_APB2OTP_BLOCK5_W7_S))
-#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W7_REG register
+ *  eFuse apb2otp block5 data register7.
+ */
+#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914)
+/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
+#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W7_S  0
 
-#define EFUSE_APB2OTP_BLK5_W8_REG          (DR_REG_EFUSE_BASE + 0x918)
-/* EFUSE_APB2OTP_BLOCK5_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W8_M  ((EFUSE_APB2OTP_BLOCK5_W8_V)<<(EFUSE_APB2OTP_BLOCK5_W8_S))
-#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W8_REG register
+ *  eFuse apb2otp block5 data register8.
+ */
+#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918)
+/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
+#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W8_S  0
 
-#define EFUSE_APB2OTP_BLK5_W9_REG          (DR_REG_EFUSE_BASE + 0x91C)
-/* EFUSE_APB2OTP_BLOCK5_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W9_M  ((EFUSE_APB2OTP_BLOCK5_W9_V)<<(EFUSE_APB2OTP_BLOCK5_W9_S))
-#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W9_REG register
+ *  eFuse apb2otp block5 data register9.
+ */
+#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c)
+/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
+#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W9_S  0
 
-#define EFUSE_APB2OTP_BLK5_W10_REG          (DR_REG_EFUSE_BASE + 0x920)
-/* EFUSE_APB2OTP_BLOCK5_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W10_M  ((EFUSE_APB2OTP_BLOCK5_W10_V)<<(EFUSE_APB2OTP_BLOCK5_W10_S))
-#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W10_REG register
+ *  eFuse apb2otp block5 data register10.
+ */
+#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920)
+/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
+#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W10_S  0
 
-#define EFUSE_APB2OTP_BLK5_W11_REG          (DR_REG_EFUSE_BASE + 0x924)
-/* EFUSE_APB2OTP_BLOCK5_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block5 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK5_W11_M  ((EFUSE_APB2OTP_BLOCK5_W11_V)<<(EFUSE_APB2OTP_BLOCK5_W11_S))
-#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK5_W11_REG register
+ *  eFuse apb2otp block5 data register11.
+ */
+#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924)
+/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
+#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK5_W11_S  0
 
-#define EFUSE_APB2OTP_BLK6_W1_REG          (DR_REG_EFUSE_BASE + 0x928)
-/* EFUSE_APB2OTP_BLOCK6_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W1_M  ((EFUSE_APB2OTP_BLOCK6_W1_V)<<(EFUSE_APB2OTP_BLOCK6_W1_S))
-#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W1_REG register
+ *  eFuse apb2otp block6 data register1.
+ */
+#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928)
+/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
+#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W1_S  0
 
-#define EFUSE_APB2OTP_BLK6_W2_REG          (DR_REG_EFUSE_BASE + 0x92C)
-/* EFUSE_APB2OTP_BLOCK6_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W2_M  ((EFUSE_APB2OTP_BLOCK6_W2_V)<<(EFUSE_APB2OTP_BLOCK6_W2_S))
-#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W2_REG register
+ *  eFuse apb2otp block6 data register2.
+ */
+#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c)
+/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
+#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W2_S  0
 
-#define EFUSE_APB2OTP_BLK6_W3_REG          (DR_REG_EFUSE_BASE + 0x930)
-/* EFUSE_APB2OTP_BLOCK6_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W3_M  ((EFUSE_APB2OTP_BLOCK6_W3_V)<<(EFUSE_APB2OTP_BLOCK6_W3_S))
-#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W3_REG register
+ *  eFuse apb2otp block6 data register3.
+ */
+#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930)
+/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
+#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W3_S  0
 
-#define EFUSE_APB2OTP_BLK6_W4_REG          (DR_REG_EFUSE_BASE + 0x934)
-/* EFUSE_APB2OTP_BLOCK6_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W4_M  ((EFUSE_APB2OTP_BLOCK6_W4_V)<<(EFUSE_APB2OTP_BLOCK6_W4_S))
-#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W4_REG register
+ *  eFuse apb2otp block6 data register4.
+ */
+#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934)
+/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
+#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W4_S  0
 
-#define EFUSE_APB2OTP_BLK6_W5_REG          (DR_REG_EFUSE_BASE + 0x938)
-/* EFUSE_APB2OTP_BLOCK6_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W5_M  ((EFUSE_APB2OTP_BLOCK6_W5_V)<<(EFUSE_APB2OTP_BLOCK6_W5_S))
-#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W5_REG register
+ *  eFuse apb2otp block6 data register5.
+ */
+#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938)
+/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
+#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W5_S  0
 
-#define EFUSE_APB2OTP_BLK6_W6_REG          (DR_REG_EFUSE_BASE + 0x93C)
-/* EFUSE_APB2OTP_BLOCK6_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W6_M  ((EFUSE_APB2OTP_BLOCK6_W6_V)<<(EFUSE_APB2OTP_BLOCK6_W6_S))
-#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W6_REG register
+ *  eFuse apb2otp block6 data register6.
+ */
+#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c)
+/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
+#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W6_S  0
 
-#define EFUSE_APB2OTP_BLK6_W7_REG          (DR_REG_EFUSE_BASE + 0x940)
-/* EFUSE_APB2OTP_BLOCK6_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W7_M  ((EFUSE_APB2OTP_BLOCK6_W7_V)<<(EFUSE_APB2OTP_BLOCK6_W7_S))
-#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W7_REG register
+ *  eFuse apb2otp block6 data register7.
+ */
+#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940)
+/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
+#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W7_S  0
 
-#define EFUSE_APB2OTP_BLK6_W8_REG          (DR_REG_EFUSE_BASE + 0x944)
-/* EFUSE_APB2OTP_BLOCK6_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W8_M  ((EFUSE_APB2OTP_BLOCK6_W8_V)<<(EFUSE_APB2OTP_BLOCK6_W8_S))
-#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W8_REG register
+ *  eFuse apb2otp block6 data register8.
+ */
+#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944)
+/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
+#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W8_S  0
 
-#define EFUSE_APB2OTP_BLK6_W9_REG          (DR_REG_EFUSE_BASE + 0x948)
-/* EFUSE_APB2OTP_BLOCK6_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W9_M  ((EFUSE_APB2OTP_BLOCK6_W9_V)<<(EFUSE_APB2OTP_BLOCK6_W9_S))
-#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W9_REG register
+ *  eFuse apb2otp block6 data register9.
+ */
+#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948)
+/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
+#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W9_S  0
 
-#define EFUSE_APB2OTP_BLK6_W10_REG          (DR_REG_EFUSE_BASE + 0x94C)
-/* EFUSE_APB2OTP_BLOCK6_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W10_M  ((EFUSE_APB2OTP_BLOCK6_W10_V)<<(EFUSE_APB2OTP_BLOCK6_W10_S))
-#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W10_REG register
+ *  eFuse apb2otp block6 data register10.
+ */
+#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c)
+/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
+#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W10_S  0
 
-#define EFUSE_APB2OTP_BLK6_W11_REG          (DR_REG_EFUSE_BASE + 0x950)
-/* EFUSE_APB2OTP_BLOCK6_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block6 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK6_W11_M  ((EFUSE_APB2OTP_BLOCK6_W11_V)<<(EFUSE_APB2OTP_BLOCK6_W11_S))
-#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK6_W11_REG register
+ *  eFuse apb2otp block6 data register11.
+ */
+#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950)
+/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
+#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK6_W11_S  0
 
-#define EFUSE_APB2OTP_BLK7_W1_REG          (DR_REG_EFUSE_BASE + 0x954)
-/* EFUSE_APB2OTP_BLOCK7_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W1_M  ((EFUSE_APB2OTP_BLOCK7_W1_V)<<(EFUSE_APB2OTP_BLOCK7_W1_S))
-#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W1_REG register
+ *  eFuse apb2otp block7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954)
+/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
+#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W1_S  0
 
-#define EFUSE_APB2OTP_BLK7_W2_REG          (DR_REG_EFUSE_BASE + 0x958)
-/* EFUSE_APB2OTP_BLOCK7_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W2_M  ((EFUSE_APB2OTP_BLOCK7_W2_V)<<(EFUSE_APB2OTP_BLOCK7_W2_S))
-#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W2_REG register
+ *  eFuse apb2otp block7 data register2.
+ */
+#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958)
+/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
+#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W2_S  0
 
-#define EFUSE_APB2OTP_BLK7_W3_REG          (DR_REG_EFUSE_BASE + 0x95C)
-/* EFUSE_APB2OTP_BLOCK7_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W3_M  ((EFUSE_APB2OTP_BLOCK7_W3_V)<<(EFUSE_APB2OTP_BLOCK7_W3_S))
-#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W3_REG register
+ *  eFuse apb2otp block7 data register3.
+ */
+#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c)
+/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
+#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W3_S  0
 
-#define EFUSE_APB2OTP_BLK7_W4_REG          (DR_REG_EFUSE_BASE + 0x960)
-/* EFUSE_APB2OTP_BLOCK7_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W4_M  ((EFUSE_APB2OTP_BLOCK7_W4_V)<<(EFUSE_APB2OTP_BLOCK7_W4_S))
-#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W4_REG register
+ *  eFuse apb2otp block7 data register4.
+ */
+#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960)
+/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
+#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W4_S  0
 
-#define EFUSE_APB2OTP_BLK7_W5_REG          (DR_REG_EFUSE_BASE + 0x964)
-/* EFUSE_APB2OTP_BLOCK7_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W5_M  ((EFUSE_APB2OTP_BLOCK7_W5_V)<<(EFUSE_APB2OTP_BLOCK7_W5_S))
-#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W5_REG register
+ *  eFuse apb2otp block7 data register5.
+ */
+#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964)
+/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
+#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W5_S  0
 
-#define EFUSE_APB2OTP_BLK7_W6_REG          (DR_REG_EFUSE_BASE + 0x968)
-/* EFUSE_APB2OTP_BLOCK7_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W6_M  ((EFUSE_APB2OTP_BLOCK7_W6_V)<<(EFUSE_APB2OTP_BLOCK7_W6_S))
-#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W6_REG register
+ *  eFuse apb2otp block7 data register6.
+ */
+#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968)
+/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
+#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W6_S  0
 
-#define EFUSE_APB2OTP_BLK7_W7_REG          (DR_REG_EFUSE_BASE + 0x96C)
-/* EFUSE_APB2OTP_BLOCK7_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W7_M  ((EFUSE_APB2OTP_BLOCK7_W7_V)<<(EFUSE_APB2OTP_BLOCK7_W7_S))
-#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W7_REG register
+ *  eFuse apb2otp block7 data register7.
+ */
+#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c)
+/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
+#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W7_S  0
 
-#define EFUSE_APB2OTP_BLK7_W8_REG          (DR_REG_EFUSE_BASE + 0x970)
-/* EFUSE_APB2OTP_BLOCK7_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W8_M  ((EFUSE_APB2OTP_BLOCK7_W8_V)<<(EFUSE_APB2OTP_BLOCK7_W8_S))
-#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W8_REG register
+ *  eFuse apb2otp block7 data register8.
+ */
+#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970)
+/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
+#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W8_S  0
 
-#define EFUSE_APB2OTP_BLK7_W9_REG          (DR_REG_EFUSE_BASE + 0x974)
-/* EFUSE_APB2OTP_BLOCK7_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W9_M  ((EFUSE_APB2OTP_BLOCK7_W9_V)<<(EFUSE_APB2OTP_BLOCK7_W9_S))
-#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W9_REG register
+ *  eFuse apb2otp block7 data register9.
+ */
+#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974)
+/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
+#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W9_S  0
 
-#define EFUSE_APB2OTP_BLK7_W10_REG          (DR_REG_EFUSE_BASE + 0x978)
-/* EFUSE_APB2OTP_BLOCK7_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W10_M  ((EFUSE_APB2OTP_BLOCK7_W10_V)<<(EFUSE_APB2OTP_BLOCK7_W10_S))
-#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W10_REG register
+ *  eFuse apb2otp block7 data register10.
+ */
+#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978)
+/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
+#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W10_S  0
 
-#define EFUSE_APB2OTP_BLK7_W11_REG          (DR_REG_EFUSE_BASE + 0x97C)
-/* EFUSE_APB2OTP_BLOCK7_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block7 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK7_W11_M  ((EFUSE_APB2OTP_BLOCK7_W11_V)<<(EFUSE_APB2OTP_BLOCK7_W11_S))
-#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK7_W11_REG register
+ *  eFuse apb2otp block7 data register11.
+ */
+#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c)
+/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
+#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK7_W11_S  0
 
-#define EFUSE_APB2OTP_BLK8_W1_REG          (DR_REG_EFUSE_BASE + 0x980)
-/* EFUSE_APB2OTP_BLOCK8_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W1_M  ((EFUSE_APB2OTP_BLOCK8_W1_V)<<(EFUSE_APB2OTP_BLOCK8_W1_S))
-#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W1_REG register
+ *  eFuse apb2otp block8 data register1.
+ */
+#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980)
+/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
+#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W1_S  0
 
-#define EFUSE_APB2OTP_BLK8_W2_REG          (DR_REG_EFUSE_BASE + 0x984)
-/* EFUSE_APB2OTP_BLOCK8_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W2_M  ((EFUSE_APB2OTP_BLOCK8_W2_V)<<(EFUSE_APB2OTP_BLOCK8_W2_S))
-#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W2_REG register
+ *  eFuse apb2otp block8 data register2.
+ */
+#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984)
+/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
+#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W2_S  0
 
-#define EFUSE_APB2OTP_BLK8_W3_REG          (DR_REG_EFUSE_BASE + 0x988)
-/* EFUSE_APB2OTP_BLOCK8_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W3_M  ((EFUSE_APB2OTP_BLOCK8_W3_V)<<(EFUSE_APB2OTP_BLOCK8_W3_S))
-#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W3_REG register
+ *  eFuse apb2otp block8 data register3.
+ */
+#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988)
+/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
+#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W3_S  0
 
-#define EFUSE_APB2OTP_BLK8_W4_REG          (DR_REG_EFUSE_BASE + 0x98C)
-/* EFUSE_APB2OTP_BLOCK8_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W4_M  ((EFUSE_APB2OTP_BLOCK8_W4_V)<<(EFUSE_APB2OTP_BLOCK8_W4_S))
-#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W4_REG register
+ *  eFuse apb2otp block8 data register4.
+ */
+#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c)
+/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
+#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W4_S  0
 
-#define EFUSE_APB2OTP_BLK8_W5_REG          (DR_REG_EFUSE_BASE + 0x990)
-/* EFUSE_APB2OTP_BLOCK8_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W5_M  ((EFUSE_APB2OTP_BLOCK8_W5_V)<<(EFUSE_APB2OTP_BLOCK8_W5_S))
-#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W5_REG register
+ *  eFuse apb2otp block8 data register5.
+ */
+#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990)
+/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
+#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W5_S  0
 
-#define EFUSE_APB2OTP_BLK8_W6_REG          (DR_REG_EFUSE_BASE + 0x994)
-/* EFUSE_APB2OTP_BLOCK8_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W6_M  ((EFUSE_APB2OTP_BLOCK8_W6_V)<<(EFUSE_APB2OTP_BLOCK8_W6_S))
-#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W6_REG register
+ *  eFuse apb2otp block8 data register6.
+ */
+#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994)
+/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
+#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W6_S  0
 
-#define EFUSE_APB2OTP_BLK8_W7_REG          (DR_REG_EFUSE_BASE + 0x998)
-/* EFUSE_APB2OTP_BLOCK8_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W7_M  ((EFUSE_APB2OTP_BLOCK8_W7_V)<<(EFUSE_APB2OTP_BLOCK8_W7_S))
-#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W7_REG register
+ *  eFuse apb2otp block8 data register7.
+ */
+#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998)
+/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
+#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W7_S  0
 
-#define EFUSE_APB2OTP_BLK8_W8_REG          (DR_REG_EFUSE_BASE + 0x99C)
-/* EFUSE_APB2OTP_BLOCK8_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W8_M  ((EFUSE_APB2OTP_BLOCK8_W8_V)<<(EFUSE_APB2OTP_BLOCK8_W8_S))
-#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W8_REG register
+ *  eFuse apb2otp block8 data register8.
+ */
+#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c)
+/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
+#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W8_S  0
 
-#define EFUSE_APB2OTP_BLK8_W9_REG          (DR_REG_EFUSE_BASE + 0x9A0)
-/* EFUSE_APB2OTP_BLOCK8_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W9_M  ((EFUSE_APB2OTP_BLOCK8_W9_V)<<(EFUSE_APB2OTP_BLOCK8_W9_S))
-#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W9_REG register
+ *  eFuse apb2otp block8 data register9.
+ */
+#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0)
+/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
+#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W9_S  0
 
-#define EFUSE_APB2OTP_BLK8_W10_REG          (DR_REG_EFUSE_BASE + 0x9A4)
-/* EFUSE_APB2OTP_BLOCK8_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W10_M  ((EFUSE_APB2OTP_BLOCK8_W10_V)<<(EFUSE_APB2OTP_BLOCK8_W10_S))
-#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W10_REG register
+ *  eFuse apb2otp block8 data register10.
+ */
+#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4)
+/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
+#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W10_S  0
 
-#define EFUSE_APB2OTP_BLK8_W11_REG          (DR_REG_EFUSE_BASE + 0x9A8)
-/* EFUSE_APB2OTP_BLOCK8_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block8 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK8_W11_M  ((EFUSE_APB2OTP_BLOCK8_W11_V)<<(EFUSE_APB2OTP_BLOCK8_W11_S))
-#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK8_W11_REG register
+ *  eFuse apb2otp block8 data register11.
+ */
+#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8)
+/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
+#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK8_W11_S  0
 
-#define EFUSE_APB2OTP_BLK9_W1_REG          (DR_REG_EFUSE_BASE + 0x9AC)
-/* EFUSE_APB2OTP_BLOCK9_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W1_M  ((EFUSE_APB2OTP_BLOCK9_W1_V)<<(EFUSE_APB2OTP_BLOCK9_W1_S))
-#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W1_REG register
+ *  eFuse apb2otp block9 data register1.
+ */
+#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac)
+/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
+#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W1_S  0
 
-#define EFUSE_APB2OTP_BLK9_W2_REG          (DR_REG_EFUSE_BASE + 0x9B0)
-/* EFUSE_APB2OTP_BLOCK9_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W2_M  ((EFUSE_APB2OTP_BLOCK9_W2_V)<<(EFUSE_APB2OTP_BLOCK9_W2_S))
-#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W2_REG register
+ *  eFuse apb2otp block9 data register2.
+ */
+#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0)
+/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
+#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W2_S  0
 
-#define EFUSE_APB2OTP_BLK9_W3_REG          (DR_REG_EFUSE_BASE + 0x9B4)
-/* EFUSE_APB2OTP_BLOCK9_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W3_M  ((EFUSE_APB2OTP_BLOCK9_W3_V)<<(EFUSE_APB2OTP_BLOCK9_W3_S))
-#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W3_REG register
+ *  eFuse apb2otp block9 data register3.
+ */
+#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4)
+/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
+#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W3_S  0
 
-#define EFUSE_APB2OTP_BLK9_W4_REG          (DR_REG_EFUSE_BASE + 0x9B8)
-/* EFUSE_APB2OTP_BLOCK9_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W4_M  ((EFUSE_APB2OTP_BLOCK9_W4_V)<<(EFUSE_APB2OTP_BLOCK9_W4_S))
-#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W4_REG register
+ *  eFuse apb2otp block9 data register4.
+ */
+#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8)
+/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
+#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W4_S  0
 
-#define EFUSE_APB2OTP_BLK9_W5_REG          (DR_REG_EFUSE_BASE + 0x9BC)
-/* EFUSE_APB2OTP_BLOCK9_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W5_M  ((EFUSE_APB2OTP_BLOCK9_W5_V)<<(EFUSE_APB2OTP_BLOCK9_W5_S))
-#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W5_REG register
+ *  eFuse apb2otp block9 data register5.
+ */
+#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc)
+/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
+#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W5_S  0
 
-#define EFUSE_APB2OTP_BLK9_W6_REG          (DR_REG_EFUSE_BASE + 0x9C0)
-/* EFUSE_APB2OTP_BLOCK9_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W6_M  ((EFUSE_APB2OTP_BLOCK9_W6_V)<<(EFUSE_APB2OTP_BLOCK9_W6_S))
-#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W6_REG register
+ *  eFuse apb2otp block9 data register6.
+ */
+#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0)
+/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
+#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W6_S  0
 
-#define EFUSE_APB2OTP_BLK9_W7_REG          (DR_REG_EFUSE_BASE + 0x9C4)
-/* EFUSE_APB2OTP_BLOCK9_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W7_M  ((EFUSE_APB2OTP_BLOCK9_W7_V)<<(EFUSE_APB2OTP_BLOCK9_W7_S))
-#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W7_REG register
+ *  eFuse apb2otp block9 data register7.
+ */
+#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4)
+/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
+#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W7_S  0
 
-#define EFUSE_APB2OTP_BLK9_W8_REG          (DR_REG_EFUSE_BASE + 0x9C8)
-/* EFUSE_APB2OTP_BLOCK9_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W8_M  ((EFUSE_APB2OTP_BLOCK9_W8_V)<<(EFUSE_APB2OTP_BLOCK9_W8_S))
-#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W8_REG register
+ *  eFuse apb2otp block9 data register8.
+ */
+#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8)
+/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
+#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W8_S  0
 
-#define EFUSE_APB2OTP_BLK9_W9_REG          (DR_REG_EFUSE_BASE + 0x9CC)
-/* EFUSE_APB2OTP_BLOCK9_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W9_M  ((EFUSE_APB2OTP_BLOCK9_W9_V)<<(EFUSE_APB2OTP_BLOCK9_W9_S))
-#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W9_REG register
+ *  eFuse apb2otp block9 data register9.
+ */
+#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc)
+/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
+#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W9_S  0
 
-#define EFUSE_APB2OTP_BLK9_W10_REG          (DR_REG_EFUSE_BASE + 0x9D0)
-/* EFUSE_APB2OTP_BLOCK9_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W10_M  ((EFUSE_APB2OTP_BLOCK9_W10_V)<<(EFUSE_APB2OTP_BLOCK9_W10_S))
-#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W10_REG register
+ *  eFuse apb2otp block9 data register10.
+ */
+#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0)
+/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
+#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W10_S  0
 
-#define EFUSE_APB2OTP_BLK9_W11_REG          (DR_REG_EFUSE_BASE + 0x9D4)
-/* EFUSE_APB2OTP_BLOCK9_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block9 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK9_W11_M  ((EFUSE_APB2OTP_BLOCK9_W11_V)<<(EFUSE_APB2OTP_BLOCK9_W11_S))
-#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK9_W11_REG register
+ *  eFuse apb2otp block9 data register11.
+ */
+#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4)
+/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
+#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK9_W11_S  0
 
-#define EFUSE_APB2OTP_BLK10_W1_REG          (DR_REG_EFUSE_BASE + 0x9D8)
-/* EFUSE_APB2OTP_BLOCK10_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word1 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W1_M  ((EFUSE_APB2OTP_BLOCK10_W1_V)<<(EFUSE_APB2OTP_BLOCK10_W1_S))
-#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W1_REG register
+ *  eFuse apb2otp block10 data register1.
+ */
+#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8)
+/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
+#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W1_S  0
 
-#define EFUSE_APB2OTP_BLK10_W2_REG          (DR_REG_EFUSE_BASE + 0x9DC)
-/* EFUSE_APB2OTP_BLOCK10_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word2 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W2_M  ((EFUSE_APB2OTP_BLOCK10_W2_V)<<(EFUSE_APB2OTP_BLOCK10_W2_S))
-#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W2_REG register
+ *  eFuse apb2otp block10 data register2.
+ */
+#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc)
+/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
+#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W2_S  0
 
-#define EFUSE_APB2OTP_BLK10_W3_REG          (DR_REG_EFUSE_BASE + 0x9E0)
-/* EFUSE_APB2OTP_BLOCK10_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word3 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W3_M  ((EFUSE_APB2OTP_BLOCK10_W3_V)<<(EFUSE_APB2OTP_BLOCK10_W3_S))
-#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W3_REG register
+ *  eFuse apb2otp block10 data register3.
+ */
+#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0)
+/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
+#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W3_S  0
 
-#define EFUSE_APB2OTP_BLK10_W4_REG          (DR_REG_EFUSE_BASE + 0x9E4)
-/* EFUSE_APB2OTP_BLOCK10_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word4 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W4_M  ((EFUSE_APB2OTP_BLOCK10_W4_V)<<(EFUSE_APB2OTP_BLOCK10_W4_S))
-#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W4_REG register
+ *  eFuse apb2otp block10 data register4.
+ */
+#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4)
+/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
+#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W4_S  0
 
-#define EFUSE_APB2OTP_BLK10_W5_REG          (DR_REG_EFUSE_BASE + 0x9E8)
-/* EFUSE_APB2OTP_BLOCK10_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word5 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W5_M  ((EFUSE_APB2OTP_BLOCK10_W5_V)<<(EFUSE_APB2OTP_BLOCK10_W5_S))
-#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W5_REG register
+ *  eFuse apb2otp block10 data register5.
+ */
+#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8)
+/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
+#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W5_S  0
 
-#define EFUSE_APB2OTP_BLK10_W6_REG          (DR_REG_EFUSE_BASE + 0x9EC)
-/* EFUSE_APB2OTP_BLOCK10_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word6 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W6_M  ((EFUSE_APB2OTP_BLOCK10_W6_V)<<(EFUSE_APB2OTP_BLOCK10_W6_S))
-#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W6_REG register
+ *  eFuse apb2otp block10 data register6.
+ */
+#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec)
+/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
+#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W6_S  0
 
-#define EFUSE_APB2OTP_BLK10_W7_REG          (DR_REG_EFUSE_BASE + 0x9F0)
-/* EFUSE_APB2OTP_BLOCK10_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word7 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W7_M  ((EFUSE_APB2OTP_BLOCK10_W7_V)<<(EFUSE_APB2OTP_BLOCK10_W7_S))
-#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W7_REG register
+ *  eFuse apb2otp block10 data register7.
+ */
+#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0)
+/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
+#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W7_S  0
 
-#define EFUSE_APB2OTP_BLK10_W8_REG          (DR_REG_EFUSE_BASE + 0x9F4)
-/* EFUSE_APB2OTP_BLOCK10_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word8 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W8_M  ((EFUSE_APB2OTP_BLOCK10_W8_V)<<(EFUSE_APB2OTP_BLOCK10_W8_S))
-#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W8_REG register
+ *  eFuse apb2otp block10 data register8.
+ */
+#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4)
+/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
+#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W8_S  0
 
-#define EFUSE_APB2OTP_BLK10_W9_REG          (DR_REG_EFUSE_BASE + 0x9F8)
-/* EFUSE_APB2OTP_BLOCK10_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word9 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W9_M  ((EFUSE_APB2OTP_BLOCK10_W9_V)<<(EFUSE_APB2OTP_BLOCK10_W9_S))
-#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W9_REG register
+ *  eFuse apb2otp block10 data register9.
+ */
+#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8)
+/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
+#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W9_S  0
 
-#define EFUSE_APB2OTP_BLK10_W10_REG          (DR_REG_EFUSE_BASE + 0x9FC)
-/* EFUSE_APB2OTP_BLOCK19_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word10 data..*/
-#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK19_W10_M  ((EFUSE_APB2OTP_BLOCK19_W10_V)<<(EFUSE_APB2OTP_BLOCK19_W10_S))
-#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W10_REG register
+ *  eFuse apb2otp block10 data register10.
+ */
+#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc)
+/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK19_W10_M  (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S)
+#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK19_W10_S  0
 
-#define EFUSE_APB2OTP_BLK10_W11_REG          (DR_REG_EFUSE_BASE + 0xA00)
-/* EFUSE_APB2OTP_BLOCK10_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Otp block10 word11 data..*/
-#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFF
-#define EFUSE_APB2OTP_BLOCK10_W11_M  ((EFUSE_APB2OTP_BLOCK10_W11_V)<<(EFUSE_APB2OTP_BLOCK10_W11_S))
-#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFF
+/** EFUSE_APB2OTP_BLK10_W11_REG register
+ *  eFuse apb2otp block10 data register11.
+ */
+#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00)
+/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
+#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
 #define EFUSE_APB2OTP_BLOCK10_W11_S  0
 
-#define EFUSE_APB2OTP_EN_REG          (DR_REG_EFUSE_BASE + 0xA08)
-/* EFUSE_APB2OTP_APB2OTP_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Apb2otp mode enable signal..*/
+/** EFUSE_APB2OTP_EN_REG register
+ *  eFuse apb2otp enable configuration register.
+ */
+#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08)
+/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
+ *  Apb2otp mode enable signal.
+ */
 #define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
-#define EFUSE_APB2OTP_APB2OTP_EN_M  (BIT(0))
-#define EFUSE_APB2OTP_APB2OTP_EN_V  0x1
+#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
+#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
 #define EFUSE_APB2OTP_APB2OTP_EN_S  0
 
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32p4/include/soc/efuse_struct.h b/components/soc/esp32p4/include/soc/efuse_struct.h
index ffa54c2a0e..1ed1b20ab8 100644
--- a/components/soc/esp32p4/include/soc/efuse_struct.h
+++ b/components/soc/esp32p4/include/soc/efuse_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,1002 +10,4441 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
-    uint32_t pgm_data0;
-    uint32_t pgm_data1;
-    uint32_t pgm_data2;
-    uint32_t pgm_data3;
-    uint32_t pgm_data4;
-    uint32_t pgm_data5;
-    uint32_t pgm_data6;
-    uint32_t pgm_data7;
-    uint32_t pgm_check_value0;
-    uint32_t pgm_check_value1;
-    uint32_t pgm_check_value2;
-    uint32_t rd_wr_dis;
-    union {
-        struct {
-            uint32_t rd_dis                    :    7;  /*Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t usb_device_exchg_pins     :    1;  /*Enable usb device exchange pins of D+ and D-.*/
-            uint32_t usb_otg11_exchg_pins      :    1;  /*Enable usb otg11 exchange pins of D+ and D-.*/
-            uint32_t dis_usb_jtag              :    1;  /*Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t powerglitch_en            :    1;  /*Represents whether power glitch function is enabled. 1: enabled. 0: disabled.*/
-            uint32_t dis_usb_serial_jtag       :    1;  /*Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t dis_force_download        :    1;  /*Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t spi_download_mspi_dis     :    1;  /*Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download.*/
-            uint32_t dis_twai                  :    1;  /*Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t jtag_sel_enable           :    1;  /*Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled.*/
-            uint32_t soft_dis_jtag             :    3;  /*Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled.*/
-            uint32_t dis_pad_jtag              :    1;  /*Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled.*/
-            uint32_t dis_download_manual_encrypt:    1;  /*Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled.*/
-            uint32_t usb_device_drefh          :    2;  /*USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV*/
-            uint32_t usb_otg11_drefh           :    2;  /*USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV*/
-            uint32_t usb_phy_sel               :    1;  /*TBD*/
-            uint32_t huk_gen_state_low         :    6;  /*Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid.*/
-        };
-        uint32_t val;
-    } rd_repeat_data0;
-    union {
-        struct {
-            uint32_t huk_gen_state_high        :    3;  /*Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid.*/
-            uint32_t km_rnd_switch_cycle       :    2;  /*Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.*/
-            uint32_t km_deploy_only_once       :    4;  /*Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.*/
-            uint32_t force_use_key_manager_key :    4;  /*Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.*/
-            uint32_t force_disable_sw_init_key :    1;  /*Set this bit to disable software written init key, and force use efuse_init_key.*/
-            uint32_t xts_key_length_256        :    1;  /*Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.*/
-            uint32_t reserved15                    :    1;  /*Reserved.*/
-            uint32_t wdt_delay_sel             :    2;  /*Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected.*/
-            uint32_t spi_boot_crypt_cnt        :    3;  /*Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled.*/
-            uint32_t secure_boot_key_revoke0   :    1;  /*Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/
-            uint32_t secure_boot_key_revoke1   :    1;  /*Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/
-            uint32_t secure_boot_key_revoke2   :    1;  /*Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/
-            uint32_t key_purpose_0             :    4;  /*Represents the purpose of Key0.*/
-            uint32_t key_purpose_1             :    4;  /*Represents the purpose of Key1.*/
-        };
-        uint32_t val;
-    } rd_repeat_data1;
-    union {
-        struct {
-            uint32_t key_purpose_2             :    4;  /*Represents the purpose of Key2.*/
-            uint32_t key_purpose_3             :    4;  /*Represents the purpose of Key3.*/
-            uint32_t key_purpose_4             :    4;  /*Represents the purpose of Key4.*/
-            uint32_t key_purpose_5             :    4;  /*Represents the purpose of Key5.*/
-            uint32_t sec_dpa_level             :    2;  /*Represents the spa secure level by configuring the clock random divide mode.*/
-            uint32_t ecdsa_enable_soft_k       :    1;  /*Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used.*/
-            uint32_t crypt_dpa_enable          :    1;  /*Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.*/
-            uint32_t secure_boot_en            :    1;  /*Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.*/
-            uint32_t secure_boot_aggressive_revoke:    1;  /*Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled.*/
-            uint32_t reserved22                    :    1;  /*Reserved.*/
-            uint32_t flash_type                :    1;  /*The type of interfaced flash. 0: four data lines, 1: eight data lines.*/
-            uint32_t flash_page_size           :    2;  /*Set flash page size.*/
-            uint32_t flash_ecc_en              :    1;  /*Set this bit to enable ecc for flash boot.*/
-            uint32_t dis_usb_otg_download_mode :    1;  /*Set this bit to disable download via USB-OTG.*/
-            uint32_t flash_tpuw                :    4;  /*Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value.*/
-        };
-        uint32_t val;
-    } rd_repeat_data2;
-    union {
-        struct {
-            uint32_t dis_download_mode         :    1;  /*Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t dis_direct_boot           :    1;  /*Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t dis_usb_serial_jtag_rom_print:    1;  /*Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t lock_km_key               :    1;  /*TBD*/
-            uint32_t dis_usb_serial_jtag_download_mode:    1;  /*Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled.*/
-            uint32_t enable_security_download  :    1;  /*Represents whether security download is enabled or disabled. 1: enabled. 0: disabled.*/
-            uint32_t uart_print_control        :    2;  /*Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. */
-            uint32_t force_send_resume         :    1;  /*Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced.*/
-            uint32_t secure_version            :    16;  /*Represents the version used by ESP-IDF anti-rollback feature.*/
-            uint32_t secure_boot_disable_fast_wake:    1;  /*Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled.*/
-            uint32_t hys_en_pad                :    1;  /*Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled.*/
-            uint32_t dcdc_vset                 :    5;  /*Set the dcdc voltage default.*/
-        };
-        uint32_t val;
-    } rd_repeat_data3;
-    union {
-        struct {
-            uint32_t _0pxa_tieh_sel_0           :    2;  /*TBD*/
-            uint32_t _0pxa_tieh_sel_1           :    2;  /*TBD.*/
-            uint32_t _0pxa_tieh_sel_2           :    2;  /*TBD.*/
-            uint32_t _0pxa_tieh_sel_3           :    2;  /*TBD.*/
-            uint32_t km_disable_deploy_mode    :    4;  /*TBD*/
-            uint32_t usb_device_drefl          :    2;  /*Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV.*/
-            uint32_t usb_otg11_drefl           :    2;  /*Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV.*/
-            uint32_t reserved16                    :    2;  /*Reserved.*/
-            uint32_t hp_pwr_src_sel            :    1;  /*HP system power source select. 0:LDO. 1: DCDC.*/
-            uint32_t dcdc_vset_en              :    1;  /*Select dcdc vset use efuse_dcdc_vset.*/
-            uint32_t dis_wdt                   :    1;  /*Set this bit to disable watch dog.*/
-            uint32_t dis_swd                   :    1;  /*Set this bit to disable super-watchdog.*/
-            uint32_t reserved22                    :    2;  /*Reserved.*/
-            uint32_t reserved24                    :    8;  /*Reserved.*/
-        };
-        uint32_t val;
-    } rd_repeat_data4;
-    uint32_t rd_mac_sys_0;
-    union {
-        struct {
-            uint32_t mac_1                     :    16;  /*Stores the high 16 bits of MAC address.*/
-            uint32_t mac_ext                   :    16;  /*Stores the extended bits of MAC address.*/
-        };
-        uint32_t val;
-    } rd_mac_sys_1;
-    union {
-        struct {
-            uint32_t mac_reserved_1            :    14;  /*Reserved.*/
-            uint32_t mac_reserved_0            :    18;  /*Reserved.*/
-        };
-        uint32_t val;
-    } rd_mac_sys_2;
-    union {
-        struct {
-            uint32_t mac_reserved_2            :    18;  /*Reserved.*/
-            uint32_t sys_data_part0_0          :    14;  /*Stores the first 14 bits of the zeroth part of system data.*/
-        };
-        uint32_t val;
-    } rd_mac_sys_3;
-    uint32_t rd_mac_sys_4;
-    uint32_t rd_mac_sys_5;
-    uint32_t rd_sys_part1_data0;
-    uint32_t rd_sys_part1_data1;
-    uint32_t rd_sys_part1_data2;
-    uint32_t rd_sys_part1_data3;
-    uint32_t rd_sys_part1_data4;
-    uint32_t rd_sys_part1_data5;
-    uint32_t rd_sys_part1_data6;
-    uint32_t rd_sys_part1_data7;
-    uint32_t rd_usr_data0;
-    uint32_t rd_usr_data1;
-    uint32_t rd_usr_data2;
-    uint32_t rd_usr_data3;
-    uint32_t rd_usr_data4;
-    uint32_t rd_usr_data5;
-    uint32_t rd_usr_data6;
-    uint32_t rd_usr_data7;
-    uint32_t rd_key0_data0;
-    uint32_t rd_key0_data1;
-    uint32_t rd_key0_data2;
-    uint32_t rd_key0_data3;
-    uint32_t rd_key0_data4;
-    uint32_t rd_key0_data5;
-    uint32_t rd_key0_data6;
-    uint32_t rd_key0_data7;
-    uint32_t rd_key1_data0;
-    uint32_t rd_key1_data1;
-    uint32_t rd_key1_data2;
-    uint32_t rd_key1_data3;
-    uint32_t rd_key1_data4;
-    uint32_t rd_key1_data5;
-    uint32_t rd_key1_data6;
-    uint32_t rd_key1_data7;
-    uint32_t rd_key2_data0;
-    uint32_t rd_key2_data1;
-    uint32_t rd_key2_data2;
-    uint32_t rd_key2_data3;
-    uint32_t rd_key2_data4;
-    uint32_t rd_key2_data5;
-    uint32_t rd_key2_data6;
-    uint32_t rd_key2_data7;
-    uint32_t rd_key3_data0;
-    uint32_t rd_key3_data1;
-    uint32_t rd_key3_data2;
-    uint32_t rd_key3_data3;
-    uint32_t rd_key3_data4;
-    uint32_t rd_key3_data5;
-    uint32_t rd_key3_data6;
-    uint32_t rd_key3_data7;
-    uint32_t rd_key4_data0;
-    uint32_t rd_key4_data1;
-    uint32_t rd_key4_data2;
-    uint32_t rd_key4_data3;
-    uint32_t rd_key4_data4;
-    uint32_t rd_key4_data5;
-    uint32_t rd_key4_data6;
-    uint32_t rd_key4_data7;
-    uint32_t rd_key5_data0;
-    uint32_t rd_key5_data1;
-    uint32_t rd_key5_data2;
-    uint32_t rd_key5_data3;
-    uint32_t rd_key5_data4;
-    uint32_t rd_key5_data5;
-    uint32_t rd_key5_data6;
-    uint32_t rd_key5_data7;
-    uint32_t rd_sys_part2_data0;
-    uint32_t rd_sys_part2_data1;
-    uint32_t rd_sys_part2_data2;
-    uint32_t rd_sys_part2_data3;
-    uint32_t rd_sys_part2_data4;
-    uint32_t rd_sys_part2_data5;
-    uint32_t rd_sys_part2_data6;
-    uint32_t rd_sys_part2_data7;
-    union {
-        struct {
-            uint32_t rd_dis_err                :    7;  /*Indicates a programming error of RD_DIS.*/
-            uint32_t usb_device_exchg_pins_err :    1;  /*Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.*/
-            uint32_t usb_otg11_exchg_pins_err  :    1;  /*Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.*/
-            uint32_t dis_usb_jtag_err          :    1;  /*Indicates a programming error of DIS_USB_JTAG.*/
-            uint32_t powerglitch_en_err        :    1;  /*Indicates a programming error of POWERGLITCH_EN.*/
-            uint32_t dis_usb_serial_jtag_err   :    1;  /*Indicates a programming error of DIS_USB_SERIAL_JTAG.*/
-            uint32_t dis_force_download_err    :    1;  /*Indicates a programming error of DIS_FORCE_DOWNLOAD.*/
-            uint32_t spi_download_mspi_dis_err :    1;  /*Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.*/
-            uint32_t dis_twai_err              :    1;  /*Indicates a programming error of DIS_TWAI.*/
-            uint32_t jtag_sel_enable_err       :    1;  /*Indicates a programming error of JTAG_SEL_ENABLE.*/
-            uint32_t soft_dis_jtag_err         :    3;  /*Indicates a programming error of SOFT_DIS_JTAG.*/
-            uint32_t dis_pad_jtag_err          :    1;  /*Indicates a programming error of DIS_PAD_JTAG.*/
-            uint32_t dis_download_manual_encrypt_err:    1;  /*Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/
-            uint32_t usb_device_drefh_err      :    2;  /*Indicates a programming error of USB_DEVICE_DREFH.*/
-            uint32_t usb_otg11_drefh_err       :    2;  /*Indicates a programming error of USB_OTG11_DREFH.*/
-            uint32_t usb_phy_sel_err           :    1;  /*Indicates a programming error of USB_PHY_SEL.*/
-            uint32_t huk_gen_state_low_err     :    6;  /*Indicates a programming error of HUK_GEN_STATE_LOW.*/
-        };
-        uint32_t val;
-    } rd_repeat_err0;
-    union {
-        struct {
-            uint32_t huk_gen_state_high_err    :    3;  /*Indicates a programming error of HUK_GEN_STATE_HIGH.*/
-            uint32_t km_rnd_switch_cycle_err   :    2;  /*Indicates a programming error of KM_RND_SWITCH_CYCLE.*/
-            uint32_t km_deploy_only_once_err   :    4;  /*Indicates a programming error of KM_DEPLOY_ONLY_ONCE.*/
-            uint32_t force_use_key_manager_key_err:    4;  /*Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.*/
-            uint32_t force_disable_sw_init_key_err:    1;  /*Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.*/
-            uint32_t xts_key_length_256_err    :    1;  /*Indicates a programming error of XTS_KEY_LENGTH_256.*/
-            uint32_t reserved15                    :    1;  /*Reserved.*/
-            uint32_t wdt_delay_sel_err         :    2;  /*Indicates a programming error of WDT_DELAY_SEL.*/
-            uint32_t spi_boot_crypt_cnt_err    :    3;  /*Indicates a programming error of SPI_BOOT_CRYPT_CNT.*/
-            uint32_t secure_boot_key_revoke0_err:    1;  /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.*/
-            uint32_t secure_boot_key_revoke1_err:    1;  /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.*/
-            uint32_t secure_boot_key_revoke2_err:    1;  /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.*/
-            uint32_t key_purpose_0_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_0.*/
-            uint32_t key_purpose_1_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_1.*/
-        };
-        uint32_t val;
-    } rd_repeat_err1;
-    union {
-        struct {
-            uint32_t key_purpose_2_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_2.*/
-            uint32_t key_purpose_3_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_3.*/
-            uint32_t key_purpose_4_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_4.*/
-            uint32_t key_purpose_5_err         :    4;  /*Indicates a programming error of KEY_PURPOSE_5.*/
-            uint32_t sec_dpa_level_err         :    2;  /*Indicates a programming error of SEC_DPA_LEVEL.*/
-            uint32_t ecdsa_enable_soft_k_err   :    1;  /*Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.*/
-            uint32_t crypt_dpa_enable_err      :    1;  /*Indicates a programming error of CRYPT_DPA_ENABLE.*/
-            uint32_t secure_boot_en_err        :    1;  /*Indicates a programming error of SECURE_BOOT_EN.*/
-            uint32_t secure_boot_aggressive_revoke_err:    1;  /*Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.*/
-            uint32_t reserved22                    :    1;  /*Reserved.*/
-            uint32_t flash_type_err            :    1;  /*Indicates a programming error of FLASH_TYPE.*/
-            uint32_t flash_page_size_err       :    2;  /*Indicates a programming error of FLASH_PAGE_SIZE.*/
-            uint32_t flash_ecc_en_err          :    1;  /*Indicates a programming error of FLASH_ECC_EN.*/
-            uint32_t dis_usb_otg_download_mode_err:    1;  /*Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.*/
-            uint32_t flash_tpuw_err            :    4;  /*Indicates a programming error of FLASH_TPUW.*/
-        };
-        uint32_t val;
-    } rd_repeat_err2;
-    union {
-        struct {
-            uint32_t dis_download_mode_err     :    1;  /*Indicates a programming error of DIS_DOWNLOAD_MODE.*/
-            uint32_t dis_direct_boot_err       :    1;  /*Indicates a programming error of DIS_DIRECT_BOOT.*/
-            uint32_t dis_usb_serial_jtag_rom_print_err:    1;  /*Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.*/
-            uint32_t lock_km_key_err           :    1;  /*TBD*/
-            uint32_t dis_usb_serial_jtag_download_mode_err:    1;  /*Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/
-            uint32_t enable_security_download_err:    1;  /*Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.*/
-            uint32_t uart_print_control_err    :    2;  /*Indicates a programming error of UART_PRINT_CONTROL.*/
-            uint32_t force_send_resume_err     :    1;  /*Indicates a programming error of FORCE_SEND_RESUME.*/
-            uint32_t secure_version_err        :    16;  /*Indicates a programming error of SECURE VERSION.*/
-            uint32_t secure_boot_disable_fast_wake_err:    1;  /*Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.*/
-            uint32_t hys_en_pad_err            :    1;  /*Indicates a programming error of HYS_EN_PAD.*/
-            uint32_t dcdc_vset_err             :    5;  /*Indicates a programming error of DCDC_VSET.*/
-        };
-        uint32_t val;
-    } rd_repeat_err3;
-    union {
-        struct {
-            uint32_t _0pxa_tieh_sel_0_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_0.*/
-            uint32_t _0pxa_tieh_sel_1_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_1.*/
-            uint32_t _0pxa_tieh_sel_2_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_2.*/
-            uint32_t _0pxa_tieh_sel_3_err       :    2;  /*Indicates a programming error of 0PXA_TIEH_SEL_3.*/
-            uint32_t km_disable_deploy_mode_err:    4;  /*TBD.*/
-            uint32_t usb_device_drefl_err      :    2;  /*Indicates a programming error of USB_DEVICE_DREFL.*/
-            uint32_t usb_otg11_drefl_err       :    2;  /*Indicates a programming error of USB_OTG11_DREFL.*/
-            uint32_t reserved16                    :    2;  /*Reserved.*/
-            uint32_t hp_pwr_src_sel_err        :    1;  /*Indicates a programming error of HP_PWR_SRC_SEL.*/
-            uint32_t dcdc_vset_en_err          :    1;  /*Indicates a programming error of DCDC_VSET_EN.*/
-            uint32_t dis_wdt_err               :    1;  /*Indicates a programming error of DIS_WDT.*/
-            uint32_t dis_swd_err               :    1;  /*Indicates a programming error of DIS_SWD.*/
-            uint32_t reserved22                    :    2;  /*Reserved.*/
-            uint32_t reserved24                    :    8;  /*Reserved.*/
-        };
-        uint32_t val;
-    } rd_repeat_err4;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    union {
-        struct {
-            uint32_t mac_sys_err_num           :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t mac_sys_fail              :    1;  /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
-            uint32_t sys_part1_err_num         :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t sys_part1_fail            :    1;  /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
-            uint32_t usr_data_err_num          :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t usr_data_fail             :    1;  /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
-            uint32_t key0_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t key0_fail                 :    1;  /*0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.*/
-            uint32_t key1_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t key1_fail                 :    1;  /*0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.*/
-            uint32_t key2_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t key2_fail                 :    1;  /*0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.*/
-            uint32_t key3_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t key3_fail                 :    1;  /*0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.*/
-            uint32_t key4_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t key4_fail                 :    1;  /*0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.*/
-        };
-        uint32_t val;
-    } rd_rs_err0;
-    union {
-        struct {
-            uint32_t key5_err_num              :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t key5_fail                 :    1;  /*0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6.*/
-            uint32_t sys_part2_err_num         :    3;  /*The value of this signal means the number of error bytes.*/
-            uint32_t sys_part2_fail            :    1;  /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
-            uint32_t reserved8                     :    24;  /*Reserved.*/
-        };
-        uint32_t val;
-    } rd_rs_err1;
-    union {
-        struct {
-            uint32_t efuse_mem_force_pd        :    1;  /*Set this bit to force eFuse SRAM into power-saving mode.*/
-            uint32_t efuse_mem_clk_force_on    :    1;  /*Set this bit and force to activate clock signal of eFuse SRAM.*/
-            uint32_t efuse_mem_force_pu        :    1;  /*Set this bit to force eFuse SRAM into working mode.*/
-            uint32_t reserved3                     :    13;  /*Reserved.*/
-            uint32_t clk_en                    :    1;  /*Set this bit to force enable eFuse register configuration clock signal.*/
-            uint32_t reserved17                    :    15;  /*Reserved.*/
-        };
-        uint32_t val;
-    } clk;
-    union {
-        struct {
-            uint32_t op_code                   :    16;  /*0x5A5A:  programming operation command 0x5AA5: read operation command.*/
-            uint32_t cfg_ecdsa_blk             :    4;  /*Configures which block to use for ECDSA key output.*/
-            uint32_t reserved20                    :    12;  /*Reserved.*/
-        };
-        uint32_t val;
-    } conf;
-    union {
-        struct {
-            uint32_t state                     :    4;  /*Indicates the state of the eFuse state machine.*/
-            uint32_t otp_load_sw               :    1;  /*The value of OTP_LOAD_SW.*/
-            uint32_t otp_vddq_c_sync2          :    1;  /*The value of OTP_VDDQ_C_SYNC2.*/
-            uint32_t otp_strobe_sw             :    1;  /*The value of OTP_STROBE_SW.*/
-            uint32_t otp_csb_sw                :    1;  /*The value of OTP_CSB_SW.*/
-            uint32_t otp_pgenb_sw              :    1;  /*The value of OTP_PGENB_SW.*/
-            uint32_t otp_vddq_is_sw            :    1;  /*The value of OTP_VDDQ_IS_SW.*/
-            uint32_t blk0_valid_bit_cnt        :    10;  /*Indicates the number of block valid bit.*/
-            uint32_t cur_ecdsa_blk             :    4;  /*Indicates which block is used for ECDSA key output.*/
-            uint32_t reserved24                    :    8;  /*Reserved.*/
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t read_cmd                  :    1;  /*Set this bit to send read command.*/
-            uint32_t pgm_cmd                   :    1;  /*Set this bit to send programming command.*/
-            uint32_t blk_num                   :    4;  /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.*/
-            uint32_t reserved6                     :    26;  /*Reserved.*/
-        };
-        uint32_t val;
-    } cmd;
-    union {
-        struct {
-            uint32_t read_done_int_raw         :    1;  /*The raw bit signal for read_done interrupt.*/
-            uint32_t pgm_done_int_raw          :    1;  /*The raw bit signal for pgm_done interrupt.*/
-            uint32_t reserved2                     :    30;  /*Reserved.*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t read_done_int_st          :    1;  /*The status signal for read_done interrupt.*/
-            uint32_t pgm_done_int_st           :    1;  /*The status signal for pgm_done interrupt.*/
-            uint32_t reserved2                     :    30;  /*Reserved.*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t read_done_int_ena         :    1;  /*The enable signal for read_done interrupt.*/
-            uint32_t pgm_done_int_ena          :    1;  /*The enable signal for pgm_done interrupt.*/
-            uint32_t reserved2                     :    30;  /*Reserved.*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t read_done_int_clr         :    1;  /*The clear signal for read_done interrupt.*/
-            uint32_t pgm_done_int_clr          :    1;  /*The clear signal for pgm_done interrupt.*/
-            uint32_t reserved2                     :    30;  /*Reserved.*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t dac_clk_div               :    8;  /*Controls the division factor of the rising clock of the programming voltage.*/
-            uint32_t dac_clk_pad_sel           :    1;  /*Don't care.*/
-            uint32_t dac_num                   :    8;  /*Controls the rising period of the programming voltage.*/
-            uint32_t oe_clr                    :    1;  /*Reduces the power supply of the programming voltage.*/
-            uint32_t reserved18                    :    14;  /*Reserved.*/
-        };
-        uint32_t val;
-    } dac_conf;
-    union {
-        struct {
-            uint32_t thr_a                     :    8;  /*Configures the read hold time.*/
-            uint32_t trd                       :    8;  /*Configures the read time.*/
-            uint32_t tsur_a                    :    8;  /*Configures the read setup time.*/
-            uint32_t read_init_num             :    8;  /*Configures the waiting time of reading eFuse memory.*/
-        };
-        uint32_t val;
-    } rd_tim_conf;
-    union {
-        struct {
-            uint32_t tsup_a                    :    8;  /*Configures the programming setup time.*/
-            uint32_t pwr_on_num                :    16;  /*Configures the power up time for VDDQ.*/
-            uint32_t thp_a                     :    8;  /*Configures the programming hold time.*/
-        };
-        uint32_t val;
-    } wr_tim_conf1;
-    union {
-        struct {
-            uint32_t pwr_off_num               :    16;  /*Configures the power outage time for VDDQ.*/
-            uint32_t tpgm                      :    16;  /*Configures the active programming time.*/
-        };
-        uint32_t val;
-    } wr_tim_conf2;
-    union {
-        struct {
-            uint32_t bypass_rs_correction      :    1;  /*Set this bit to bypass reed solomon correction step.*/
-            uint32_t bypass_rs_blk_num         :    11;  /*Configures block number of programming twice operation.*/
-            uint32_t update                    :    1;  /*Set this bit to update multi-bit register signals.*/
-            uint32_t tpgm_inactive             :    8;  /*Configures the inactive programming time.*/
-            uint32_t reserved21                    :    11;  /*Reserved.*/
-        };
-        uint32_t val;
-    } wr_tim_conf0_rs_bypass;
-    union {
-        struct {
-            uint32_t date                      :    28;  /*Stores eFuse version.*/
-            uint32_t reserved28                    :    4;  /*Reserved.*/
-        };
-        uint32_t val;
-    } date;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    uint32_t reserved_3fc;
-    uint32_t reserved_400;
-    uint32_t reserved_404;
-    uint32_t reserved_408;
-    uint32_t reserved_40c;
-    uint32_t reserved_410;
-    uint32_t reserved_414;
-    uint32_t reserved_418;
-    uint32_t reserved_41c;
-    uint32_t reserved_420;
-    uint32_t reserved_424;
-    uint32_t reserved_428;
-    uint32_t reserved_42c;
-    uint32_t reserved_430;
-    uint32_t reserved_434;
-    uint32_t reserved_438;
-    uint32_t reserved_43c;
-    uint32_t reserved_440;
-    uint32_t reserved_444;
-    uint32_t reserved_448;
-    uint32_t reserved_44c;
-    uint32_t reserved_450;
-    uint32_t reserved_454;
-    uint32_t reserved_458;
-    uint32_t reserved_45c;
-    uint32_t reserved_460;
-    uint32_t reserved_464;
-    uint32_t reserved_468;
-    uint32_t reserved_46c;
-    uint32_t reserved_470;
-    uint32_t reserved_474;
-    uint32_t reserved_478;
-    uint32_t reserved_47c;
-    uint32_t reserved_480;
-    uint32_t reserved_484;
-    uint32_t reserved_488;
-    uint32_t reserved_48c;
-    uint32_t reserved_490;
-    uint32_t reserved_494;
-    uint32_t reserved_498;
-    uint32_t reserved_49c;
-    uint32_t reserved_4a0;
-    uint32_t reserved_4a4;
-    uint32_t reserved_4a8;
-    uint32_t reserved_4ac;
-    uint32_t reserved_4b0;
-    uint32_t reserved_4b4;
-    uint32_t reserved_4b8;
-    uint32_t reserved_4bc;
-    uint32_t reserved_4c0;
-    uint32_t reserved_4c4;
-    uint32_t reserved_4c8;
-    uint32_t reserved_4cc;
-    uint32_t reserved_4d0;
-    uint32_t reserved_4d4;
-    uint32_t reserved_4d8;
-    uint32_t reserved_4dc;
-    uint32_t reserved_4e0;
-    uint32_t reserved_4e4;
-    uint32_t reserved_4e8;
-    uint32_t reserved_4ec;
-    uint32_t reserved_4f0;
-    uint32_t reserved_4f4;
-    uint32_t reserved_4f8;
-    uint32_t reserved_4fc;
-    uint32_t reserved_500;
-    uint32_t reserved_504;
-    uint32_t reserved_508;
-    uint32_t reserved_50c;
-    uint32_t reserved_510;
-    uint32_t reserved_514;
-    uint32_t reserved_518;
-    uint32_t reserved_51c;
-    uint32_t reserved_520;
-    uint32_t reserved_524;
-    uint32_t reserved_528;
-    uint32_t reserved_52c;
-    uint32_t reserved_530;
-    uint32_t reserved_534;
-    uint32_t reserved_538;
-    uint32_t reserved_53c;
-    uint32_t reserved_540;
-    uint32_t reserved_544;
-    uint32_t reserved_548;
-    uint32_t reserved_54c;
-    uint32_t reserved_550;
-    uint32_t reserved_554;
-    uint32_t reserved_558;
-    uint32_t reserved_55c;
-    uint32_t reserved_560;
-    uint32_t reserved_564;
-    uint32_t reserved_568;
-    uint32_t reserved_56c;
-    uint32_t reserved_570;
-    uint32_t reserved_574;
-    uint32_t reserved_578;
-    uint32_t reserved_57c;
-    uint32_t reserved_580;
-    uint32_t reserved_584;
-    uint32_t reserved_588;
-    uint32_t reserved_58c;
-    uint32_t reserved_590;
-    uint32_t reserved_594;
-    uint32_t reserved_598;
-    uint32_t reserved_59c;
-    uint32_t reserved_5a0;
-    uint32_t reserved_5a4;
-    uint32_t reserved_5a8;
-    uint32_t reserved_5ac;
-    uint32_t reserved_5b0;
-    uint32_t reserved_5b4;
-    uint32_t reserved_5b8;
-    uint32_t reserved_5bc;
-    uint32_t reserved_5c0;
-    uint32_t reserved_5c4;
-    uint32_t reserved_5c8;
-    uint32_t reserved_5cc;
-    uint32_t reserved_5d0;
-    uint32_t reserved_5d4;
-    uint32_t reserved_5d8;
-    uint32_t reserved_5dc;
-    uint32_t reserved_5e0;
-    uint32_t reserved_5e4;
-    uint32_t reserved_5e8;
-    uint32_t reserved_5ec;
-    uint32_t reserved_5f0;
-    uint32_t reserved_5f4;
-    uint32_t reserved_5f8;
-    uint32_t reserved_5fc;
-    uint32_t reserved_600;
-    uint32_t reserved_604;
-    uint32_t reserved_608;
-    uint32_t reserved_60c;
-    uint32_t reserved_610;
-    uint32_t reserved_614;
-    uint32_t reserved_618;
-    uint32_t reserved_61c;
-    uint32_t reserved_620;
-    uint32_t reserved_624;
-    uint32_t reserved_628;
-    uint32_t reserved_62c;
-    uint32_t reserved_630;
-    uint32_t reserved_634;
-    uint32_t reserved_638;
-    uint32_t reserved_63c;
-    uint32_t reserved_640;
-    uint32_t reserved_644;
-    uint32_t reserved_648;
-    uint32_t reserved_64c;
-    uint32_t reserved_650;
-    uint32_t reserved_654;
-    uint32_t reserved_658;
-    uint32_t reserved_65c;
-    uint32_t reserved_660;
-    uint32_t reserved_664;
-    uint32_t reserved_668;
-    uint32_t reserved_66c;
-    uint32_t reserved_670;
-    uint32_t reserved_674;
-    uint32_t reserved_678;
-    uint32_t reserved_67c;
-    uint32_t reserved_680;
-    uint32_t reserved_684;
-    uint32_t reserved_688;
-    uint32_t reserved_68c;
-    uint32_t reserved_690;
-    uint32_t reserved_694;
-    uint32_t reserved_698;
-    uint32_t reserved_69c;
-    uint32_t reserved_6a0;
-    uint32_t reserved_6a4;
-    uint32_t reserved_6a8;
-    uint32_t reserved_6ac;
-    uint32_t reserved_6b0;
-    uint32_t reserved_6b4;
-    uint32_t reserved_6b8;
-    uint32_t reserved_6bc;
-    uint32_t reserved_6c0;
-    uint32_t reserved_6c4;
-    uint32_t reserved_6c8;
-    uint32_t reserved_6cc;
-    uint32_t reserved_6d0;
-    uint32_t reserved_6d4;
-    uint32_t reserved_6d8;
-    uint32_t reserved_6dc;
-    uint32_t reserved_6e0;
-    uint32_t reserved_6e4;
-    uint32_t reserved_6e8;
-    uint32_t reserved_6ec;
-    uint32_t reserved_6f0;
-    uint32_t reserved_6f4;
-    uint32_t reserved_6f8;
-    uint32_t reserved_6fc;
-    uint32_t reserved_700;
-    uint32_t reserved_704;
-    uint32_t reserved_708;
-    uint32_t reserved_70c;
-    uint32_t reserved_710;
-    uint32_t reserved_714;
-    uint32_t reserved_718;
-    uint32_t reserved_71c;
-    uint32_t reserved_720;
-    uint32_t reserved_724;
-    uint32_t reserved_728;
-    uint32_t reserved_72c;
-    uint32_t reserved_730;
-    uint32_t reserved_734;
-    uint32_t reserved_738;
-    uint32_t reserved_73c;
-    uint32_t reserved_740;
-    uint32_t reserved_744;
-    uint32_t reserved_748;
-    uint32_t reserved_74c;
-    uint32_t reserved_750;
-    uint32_t reserved_754;
-    uint32_t reserved_758;
-    uint32_t reserved_75c;
-    uint32_t reserved_760;
-    uint32_t reserved_764;
-    uint32_t reserved_768;
-    uint32_t reserved_76c;
-    uint32_t reserved_770;
-    uint32_t reserved_774;
-    uint32_t reserved_778;
-    uint32_t reserved_77c;
-    uint32_t reserved_780;
-    uint32_t reserved_784;
-    uint32_t reserved_788;
-    uint32_t reserved_78c;
-    uint32_t reserved_790;
-    uint32_t reserved_794;
-    uint32_t reserved_798;
-    uint32_t reserved_79c;
-    uint32_t reserved_7a0;
-    uint32_t reserved_7a4;
-    uint32_t reserved_7a8;
-    uint32_t reserved_7ac;
-    uint32_t reserved_7b0;
-    uint32_t reserved_7b4;
-    uint32_t reserved_7b8;
-    uint32_t reserved_7bc;
-    uint32_t reserved_7c0;
-    uint32_t reserved_7c4;
-    uint32_t reserved_7c8;
-    uint32_t reserved_7cc;
-    uint32_t reserved_7d0;
-    uint32_t reserved_7d4;
-    uint32_t reserved_7d8;
-    uint32_t reserved_7dc;
-    uint32_t reserved_7e0;
-    uint32_t reserved_7e4;
-    uint32_t reserved_7e8;
-    uint32_t reserved_7ec;
-    uint32_t reserved_7f0;
-    uint32_t reserved_7f4;
-    uint32_t reserved_7f8;
-    uint32_t reserved_7fc;
-    uint32_t apb2otp_wr_dis;
-    uint32_t apb2otp_blk0_backup1_w1;
-    uint32_t apb2otp_blk0_backup1_w2;
-    uint32_t apb2otp_blk0_backup1_w3;
-    uint32_t apb2otp_blk0_backup1_w4;
-    uint32_t apb2otp_blk0_backup1_w5;
-    uint32_t apb2otp_blk0_backup2_w1;
-    uint32_t apb2otp_blk0_backup2_w2;
-    uint32_t apb2otp_blk0_backup2_w3;
-    uint32_t apb2otp_blk0_backup2_w4;
-    uint32_t apb2otp_blk0_backup2_w5;
-    uint32_t apb2otp_blk0_backup3_w1;
-    uint32_t apb2otp_blk0_backup3_w2;
-    uint32_t apb2otp_blk0_backup3_w3;
-    uint32_t apb2otp_blk0_backup3_w4;
-    uint32_t apb2otp_blk0_backup3_w5;
-    uint32_t apb2otp_blk0_backup4_w1;
-    uint32_t apb2otp_blk0_backup4_w2;
-    uint32_t apb2otp_blk0_backup4_w3;
-    uint32_t apb2otp_blk0_backup4_w4;
-    uint32_t apb2otp_blk0_backup4_w5;
-    uint32_t apb2otp_blk1_w1;
-    uint32_t apb2otp_blk1_w2;
-    uint32_t apb2otp_blk1_w3;
-    uint32_t apb2otp_blk1_w4;
-    uint32_t apb2otp_blk1_w5;
-    uint32_t apb2otp_blk1_w6;
-    uint32_t apb2otp_blk1_w7;
-    uint32_t apb2otp_blk1_w8;
-    uint32_t apb2otp_blk1_w9;
-    uint32_t apb2otp_blk2_w1;
-    uint32_t apb2otp_blk2_w2;
-    uint32_t apb2otp_blk2_w3;
-    uint32_t apb2otp_blk2_w4;
-    uint32_t apb2otp_blk2_w5;
-    uint32_t apb2otp_blk2_w6;
-    uint32_t apb2otp_blk2_w7;
-    uint32_t apb2otp_blk2_w8;
-    uint32_t apb2otp_blk2_w9;
-    uint32_t apb2otp_blk2_w10;
-    uint32_t apb2otp_blk2_w11;
-    uint32_t apb2otp_blk3_w1;
-    uint32_t apb2otp_blk3_w2;
-    uint32_t apb2otp_blk3_w3;
-    uint32_t apb2otp_blk3_w4;
-    uint32_t apb2otp_blk3_w5;
-    uint32_t apb2otp_blk3_w6;
-    uint32_t apb2otp_blk3_w7;
-    uint32_t apb2otp_blk3_w8;
-    uint32_t apb2otp_blk3_w9;
-    uint32_t apb2otp_blk3_w10;
-    uint32_t apb2otp_blk3_w11;
-    uint32_t apb2otp_blk4_w1;
-    uint32_t apb2otp_blk4_w2;
-    uint32_t apb2otp_blk4_w3;
-    uint32_t apb2otp_blk4_w4;
-    uint32_t apb2otp_blk4_w5;
-    uint32_t apb2otp_blk4_w6;
-    uint32_t apb2otp_blk4_w7;
-    uint32_t apb2otp_blk4_w8;
-    uint32_t apb2otp_blk4_w9;
-    uint32_t apb2otp_blk4_w10;
-    uint32_t apb2otp_blk4_w11;
-    uint32_t apb2otp_blk5_w1;
-    uint32_t apb2otp_blk5_w2;
-    uint32_t apb2otp_blk5_w3;
-    uint32_t apb2otp_blk5_w4;
-    uint32_t apb2otp_blk5_w5;
-    uint32_t apb2otp_blk5_w6;
-    uint32_t apb2otp_blk5_w7;
-    uint32_t apb2otp_blk5_w8;
-    uint32_t apb2otp_blk5_w9;
-    uint32_t apb2otp_blk5_w10;
-    uint32_t apb2otp_blk5_w11;
-    uint32_t apb2otp_blk6_w1;
-    uint32_t apb2otp_blk6_w2;
-    uint32_t apb2otp_blk6_w3;
-    uint32_t apb2otp_blk6_w4;
-    uint32_t apb2otp_blk6_w5;
-    uint32_t apb2otp_blk6_w6;
-    uint32_t apb2otp_blk6_w7;
-    uint32_t apb2otp_blk6_w8;
-    uint32_t apb2otp_blk6_w9;
-    uint32_t apb2otp_blk6_w10;
-    uint32_t apb2otp_blk6_w11;
-    uint32_t apb2otp_blk7_w1;
-    uint32_t apb2otp_blk7_w2;
-    uint32_t apb2otp_blk7_w3;
-    uint32_t apb2otp_blk7_w4;
-    uint32_t apb2otp_blk7_w5;
-    uint32_t apb2otp_blk7_w6;
-    uint32_t apb2otp_blk7_w7;
-    uint32_t apb2otp_blk7_w8;
-    uint32_t apb2otp_blk7_w9;
-    uint32_t apb2otp_blk7_w10;
-    uint32_t apb2otp_blk7_w11;
-    uint32_t apb2otp_blk8_w1;
-    uint32_t apb2otp_blk8_w2;
-    uint32_t apb2otp_blk8_w3;
-    uint32_t apb2otp_blk8_w4;
-    uint32_t apb2otp_blk8_w5;
-    uint32_t apb2otp_blk8_w6;
-    uint32_t apb2otp_blk8_w7;
-    uint32_t apb2otp_blk8_w8;
-    uint32_t apb2otp_blk8_w9;
-    uint32_t apb2otp_blk8_w10;
-    uint32_t apb2otp_blk8_w11;
-    uint32_t apb2otp_blk9_w1;
-    uint32_t apb2otp_blk9_w2;
-    uint32_t apb2otp_blk9_w3;
-    uint32_t apb2otp_blk9_w4;
-    uint32_t apb2otp_blk9_w5;
-    uint32_t apb2otp_blk9_w6;
-    uint32_t apb2otp_blk9_w7;
-    uint32_t apb2otp_blk9_w8;
-    uint32_t apb2otp_blk9_w9;
-    uint32_t apb2otp_blk9_w10;
-    uint32_t apb2otp_blk9_w11;
-    uint32_t apb2otp_blk10_w1;
-    uint32_t apb2otp_blk10_w2;
-    uint32_t apb2otp_blk10_w3;
-    uint32_t apb2otp_blk10_w4;
-    uint32_t apb2otp_blk10_w5;
-    uint32_t apb2otp_blk10_w6;
-    uint32_t apb2otp_blk10_w7;
-    uint32_t apb2otp_blk10_w8;
-    uint32_t apb2otp_blk10_w9;
-    uint32_t apb2otp_blk10_w10;
-    uint32_t apb2otp_blk10_w11;
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: ******** Registers */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled. 1: Disabled. 0 Enabled.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t rd_dis:7;
+        /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0;
+         *  Enable usb device exchange pins of D+ and D-.
+         */
+        uint32_t usb_device_exchg_pins:1;
+        /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0;
+         *  Enable usb otg11 exchange pins of D+ and D-.
+         */
+        uint32_t usb_otg11_exchg_pins:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** powerglitch_en : RO; bitpos: [10]; default: 0;
+         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+         */
+        uint32_t powerglitch_en:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+         *  boot_mode_download.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+         *  enabled.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+         *  enabled.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode). 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        uint32_t reserved_21:4;
+        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
+         *  TBD
+         */
+        uint32_t usb_phy_sel:1;
+        /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_low:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_high:3;
+        /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0;
+         *  Set bits to control key manager random number switch cycle. 0: control by register.
+         *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+         */
+        uint32_t km_rnd_switch_cycle:2;
+        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
+         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t km_deploy_only_once:4;
+        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
+         *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t force_use_key_manager_key:4;
+        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable software written init key, and force use efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** xts_key_length_256 : RO; bitpos: [14]; default: 0;
+         *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+         */
+        uint32_t xts_key_length_256:1;
+        uint32_t reserved_15:1;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+         *  selected. 0: not selected.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+         *  1: enabled. Even number of 1: disabled.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0;
+         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+         *  0: not force used.
+         */
+        uint32_t ecdsa_enable_soft_k:1;
+        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
+         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+         */
+        uint32_t crypt_dpa_enable:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        uint32_t reserved_22:1;
+        /** flash_type : RO; bitpos: [23]; default: 0;
+         *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+         */
+        uint32_t flash_type:1;
+        /** flash_page_size : RO; bitpos: [25:24]; default: 0;
+         *  Set flash page size.
+         */
+        uint32_t flash_page_size:2;
+        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
+         *  Set this bit to enable ecc for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
+         *  Set this bit to disable download via USB-OTG.
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+         *  0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+         *  disabled.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Represents the type of UART printing. 00: force enable printing. 01: enable
+         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+         *  at high level. 11: force disable printing.
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+         *  forced. 0:not forced.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [26]; default: 0;
+         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+         *  enabled. 0:disabled.
+         */
+        uint32_t hys_en_pad:1;
+        /** dcdc_vset : RO; bitpos: [31:27]; default: 0;
+         *  Set the dcdc voltage default.
+         */
+        uint32_t dcdc_vset:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** 0pxa_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+         *  TBD
+         */
+        uint32_t rd_0pxa_tieh_sel_0:2;
+        /** 0pxa_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
+         *  TBD.
+         */
+        uint32_t rd_0pxa_tieh_sel_1:2;
+        /** 0pxa_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
+         *  TBD.
+         */
+        uint32_t rd_0pxa_tieh_sel_2:2;
+        /** 0pxa_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
+         *  TBD.
+         */
+        uint32_t rd_0pxa_tieh_sel_3:2;
+        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode:4;
+        uint32_t reserved_12:6;
+        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
+         *  HP system power source select. 0:LDO. 1: DCDC.
+         */
+        uint32_t hp_pwr_src_sel:1;
+        /** dcdc_vset_en : RO; bitpos: [19]; default: 0;
+         *  Select dcdc vset use efuse_dcdc_vset.
+         */
+        uint32_t dcdc_vset_en:1;
+        /** dis_wdt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable watch dog.
+         */
+        uint32_t dis_wdt:1;
+        /** dis_swd : RO; bitpos: [21]; default: 0;
+         *  Set this bit to disable super-watchdog.
+         */
+        uint32_t dis_swd:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_sys_0 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_0_reg_t;
+
+/** Type of rd_mac_sys_1 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** mac_ext : RO; bitpos: [31:16]; default: 0;
+         *  Stores the extended bits of MAC address.
+         */
+        uint32_t mac_ext:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_1_reg_t;
+
+/** Type of rd_mac_sys_2 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t mac_reserved_1:14;
+        /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0;
+         *  Reserved.
+         */
+        uint32_t mac_reserved_0:18;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_2_reg_t;
+
+/** Type of rd_mac_sys_3 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t mac_reserved_2:18;
+        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
+         *  Stores the first 14 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_0:14;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_3_reg_t;
+
+/** Type of rd_mac_sys_4 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_1:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_4_reg_t;
+
+/** Type of rd_mac_sys_5 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Indicates a programming error of RD_DIS.
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0;
+         *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+         */
+        uint32_t dis_usb_device_exchg_pins_err:1;
+        /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+         */
+        uint32_t dis_usb_otg11_exchg_pins_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Indicates a programming error of DIS_USB_JTAG.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
+         *  Indicates a programming error of POWERGLITCH_EN.
+         */
+        uint32_t powerglitch_en_err:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of DIS_TWAI.
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Indicates a programming error of JTAG_SEL_ENABLE.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Indicates a programming error of SOFT_DIS_JTAG.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DIS_PAD_JTAG.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        uint32_t reserved_21:4;
+        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of USB_PHY_SEL.
+         */
+        uint32_t usb_phy_sel_err:1;
+        /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_LOW.
+         */
+        uint32_t huk_gen_state_low_err:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+         */
+        uint32_t km_huk_gen_state_high_err:3;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0;
+         *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+         */
+        uint32_t km_rnd_switch_cycle_err:2;
+        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
+         *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+         */
+        uint32_t km_deploy_only_once_err:4;
+        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
+         *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+         */
+        uint32_t force_use_key_manager_key_err:4;
+        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        /** xts_key_length_256_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of XTS_KEY_LENGTH_256.
+         */
+        uint32_t xts_key_length_256_err:1;
+        uint32_t reserved_15:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of WDT_DELAY_SEL.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_0.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_1.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_2.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_3.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_4.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_5.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+         */
+        uint32_t ecdsa_enable_soft_k_err:1;
+        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of CRYPT_DPA_ENABLE.
+         */
+        uint32_t crypt_dpa_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_EN.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        uint32_t reserved_22:1;
+        /** flash_type_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of FLASH_TYPE.
+         */
+        uint32_t flash_type_err:1;
+        /** flash_page_size_err : RO; bitpos: [25:24]; default: 0;
+         *  Indicates a programming error of FLASH_PAGE_SIZE.
+         */
+        uint32_t flash_page_size_err:2;
+        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of FLASH_ECC_EN.
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_otg_download_mode_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of FLASH_TPUW.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Indicates a programming error of DIS_DIRECT_BOOT.
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CONTROL.
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of FORCE_SEND_RESUME.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Indicates a programming error of SECURE VERSION.
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of HYS_EN_PAD.
+         */
+        uint32_t hys_en_pad_err:1;
+        /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0;
+         *  Indicates a programming error of DCDC_VSET.
+         */
+        uint32_t dcdc_vset_err:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** 0pxa_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+         */
+        uint32_t rd_0pxa_tieh_sel_0_err:2;
+        /** 0pxa_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+         */
+        uint32_t rd_0pxa_tieh_sel_1_err:2;
+        /** 0pxa_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+         */
+        uint32_t rd_0pxa_tieh_sel_2_err:2;
+        /** 0pxa_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+         */
+        uint32_t rd_0pxa_tieh_sel_3_err:2;
+        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode_err:4;
+        /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFL.
+         */
+        uint32_t usb_device_drefl_err:2;
+        /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFL.
+         */
+        uint32_t usb_otg11_drefl_err:2;
+        uint32_t reserved_16:2;
+        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of HP_PWR_SRC_SEL.
+         */
+        uint32_t hp_pwr_src_sel_err:1;
+        /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DCDC_VSET_EN.
+         */
+        uint32_t dcdc_vset_en_err:1;
+        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_WDT.
+         */
+        uint32_t dis_wdt_err:1;
+        /** dis_swd_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of DIS_SWD.
+         */
+        uint32_t dis_swd_err:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_sys_err_num:3;
+        /** mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_sys_fail:1;
+        /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_err_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+         *  key5 failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuraiton register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
+         *  Configures which block to use for ECDSA key output.
+         */
+        uint32_t cfg_ecdsa_blk:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        uint32_t reserved_4:6;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 160;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36720720;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp block4 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block19_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Singal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
+    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
+    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
+    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
+    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
+    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_190[12];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_200[384];
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
     uint32_t reserved_a04;
-    union {
-        struct {
-            uint32_t apb2otp_enable            :    1;  /*Apb2otp mode enable signal.*/
-            uint32_t reserved1                     :    31;  /*Reserved.*/
-        };
-        uint32_t val;
-    } apb2otp_en;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
 } efuse_dev_t;
 
 extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
+#endif
+
 #ifdef __cplusplus
 }
 #endif

From 369f8ba459d85cc75718e3ef67e16e8a59cd83d1 Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Tue, 4 Jul 2023 12:07:22 +0800
Subject: [PATCH 10/13] feat(soc): update interrupts.c

---
 components/soc/esp32p4/interrupts.c | 203 +++++++++++++++++-----------
 1 file changed, 127 insertions(+), 76 deletions(-)

diff --git a/components/soc/esp32p4/interrupts.c b/components/soc/esp32p4/interrupts.c
index 48f79a467c..30ae62bf57 100644
--- a/components/soc/esp32p4/interrupts.c
+++ b/components/soc/esp32p4/interrupts.c
@@ -7,81 +7,132 @@
 #include "soc/interrupts.h"
 
 const char *const esp_isr_names[] = {
-    [0] = "WIFI_MAC",
-    [1] = "WIFI_MAC_NMI",
-    [2] = "WIFI_PWR",
-    [3] = "WIFI_BB",
-    [4] = "BT_MAC",
-    [5] = "BT_BB",
-    [6] = "BT_BB_NMI",
-    [7] = "LP_TIMER",
-    [8] = "COEX",
-    [9] = "BLE_TIMER",
-    [10] = "BLE_SEC",
-    [11] = "I2C_MASTER",
-    [12] = "ZB_MAC",
-    [13] = "PMU",
-    [14] = "EFUSE",
-    [15] = "LP_RTC_TIMER",
+    [0] = "LP_RTC",
+    [1] = "LP_WDT",
+    [2] = "LP_TIMER0",
+    [3] = "LP_TIMER1",
+    [4] = "MB_HP",
+    [5] = "MB_LP",
+    [6] = "PMU0",
+    [7] = "PMU1",
+    [8] = "LP_ANA",
+    [9] = "LP_ADC",
+    [10] = "LP_GPIO",
+    [11] = "LP_I2C",
+    [12] = "LP_I2S",
+    [13] = "LP_SPI",
+    [14] = "LP_TOUCH",
+    [15] = "LP_TSENS",
     [16] = "LP_UART",
-    [17] = "LP_I2C",
-    [18] = "LP_WDT",
-    [19] = "LP_PERI_TIMEOUT",
-    [20] = "LP_APM_M0",
-    [21] = "LP_APM_M1",
-    [22] = "CPU_FROM_CPU_0",
-    [23] = "CPU_FROM_CPU_1",
-    [24] = "CPU_FROM_CPU_2",
-    [25] = "CPU_FROM_CPU_3",
-    [26] = "ASSIST_DEBUG",
-    [27] = "TRACE",
-    [28] = "CACHE",
-    [29] = "CPU_PERI_TIMEOUT",
-    [30] = "GPIO_INTERRUPT_PRO",
-    [31] = "GPIO_INTERRUPT_PRO_NMI",
-    [32] = "PAU",
-    [33] = "HP_PERI_TIMEOUT",
-    [34] = "MODEM_PERI_TIMEOUT",
-    [35] = "HP_APM_M0",
-    [36] = "HP_APM_M1",
-    [37] = "HP_APM_M2",
-    [38] = "HP_APM_M3",
-    [39] = "LP_APM0",
-    [40] = "MSPI",
-    [41] = "I2S1",
-    [42] = "UHCI0",
-    [43] = "UART0",
-    [44] = "UART1",
-    [45] = "LEDC",
-    [46] = "CAN0",
-    [47] = "CAN1",
-    [48] = "USB",
-    [49] = "RMT",
-    [50] = "I2C_EXT0",
-    [51] = "TG0_T0",
-    [52] = "TG0_T1",
-    [53] = "TG0_WDT",
-    [54] = "TG1_T0",
-    [55] = "TG1_T1",
-    [56] = "TG1_WDT",
-    [57] = "SYSTIMER_TARGET0",
-    [58] = "SYSTIMER_TARGET1",
-    [59] = "SYSTIMER_TARGET2",
-    [60] = "APB_ADC",
-    [61] = "PWM",
-    [62] = "PCNT",
-    [63] = "PARL_IO",
-    [64] = "SLC0",
-    [65] = "SLC1",
-    [66] = "DMA_IN_CH0",
-    [67] = "DMA_IN_CH1",
-    [68] = "DMA_IN_CH2",
-    [69] = "DMA_OUT_CH0",
-    [70] = "DMA_OUT_CH1",
-    [71] = "DMA_OUT_CH2",
-    [72] = "GPSPI2",
-    [73] = "AES",
-    [74] = "SHA",
-    [75] = "RSA",
-    [76] = "ECC",
+    [17] = "LP_EFUSE",
+    [18] = "LP_SW",
+    [19] = "LP_SYSREG",
+    [20] = "LP_HUK",
+    [21] = "SYS_ICM",
+    [22] = "USB_DEVICE",
+    [23] = "SDIO_HOST",
+    [24] = "GDMA",
+    [25] = "GPSPI2",
+    [26] = "GPSPI3",
+    [27] = "I2S0",
+    [28] = "I2S1",
+    [29] = "I2S2",
+    [30] = "UHCI0",
+    [31] = "UART0",
+    [32] = "UART1",
+    [33] = "UART2",
+    [34] = "UART3",
+    [35] = "UART4",
+    [36] = "LCD_CAM",
+    [37] = "ADC",
+    [38] = "PWM0",
+    [39] = "PWM1",
+    [40] = "CAN0",
+    [41] = "CAN1",
+    [42] = "CAN2",
+    [43] = "RMT",
+    [44] = "I2C0",
+    [45] = "I2C1",
+    [46] = "TG0_T0",
+    [47] = "TG0_T1",
+    [48] = "TG0_WDT",
+    [49] = "TG1_T0",
+    [50] = "TG1_T1",
+    [51] = "TG1_WDT",
+    [52] = "LEDC",
+    [53] = "SYSTIMER_TARGET0",
+    [54] = "SYSTIMER_TARGET1",
+    [55] = "SYSTIMER_TARGET2",
+    [56] = "AHB_PDMA_IN_CH0",
+    [57] = "AHB_PDMA_IN_CH1",
+    [58] = "AHB_PDMA_IN_CH2",
+    [59] = "AHB_PDMA_OUT_CH0",
+    [60] = "AHB_PDMA_OUT_CH1",
+    [61] = "AHB_PDMA_OUT_CH2",
+    [62] = "AXI_PDMA_IN_CH0",
+    [63] = "AXI_PDMA_IN_CH1",
+    [64] = "AXI_PDMA_IN_CH2",
+    [65] = "AXI_PDMA_OUT_CH0",
+    [66] = "AXI_PDMA_OUT_CH1",
+    [67] = "AXI_PDMA_OUT_CH2",
+    [68] = "RSA",
+    [69] = "AES",
+    [70] = "SHA",
+    [71] = "ECC",
+    [72] = "ECDSA",
+    [73] = "KM",
+    [74] = "GPIO_INT0",
+    [75] = "GPIO_INT1",
+    [76] = "GPIO_INT2",
+    [77] = "GPIO_INT3",
+    [78] = "GPIO_PAD_COMP",
+    [79] = "CPU_INT_FROM_CPU_0",
+    [80] = "CPU_INT_FROM_CPU_1",
+    [81] = "CPU_INT_FROM_CPU_2",
+    [82] = "CPU_INT_FROM_CPU_3",
+    [83] = "CACHE",
+    [84] = "FLASH_MSPI",
+    [85] = "CSI_BRIDGE",
+    [86] = "DSI_BRIDGE",
+    [87] = "CSI",
+    [88] = "DSI",
+    [89] = "GMII_PHY",
+    [90] = "LPI",
+    [91] = "PMT",
+    [92] = "SBD",
+    [93] = "USB_OTG",
+    [94] = "USB_OTG_ENDP_MULTI_PROC",
+    [95] = "JPEG",
+    [96] = "PPA",
+    [97] = "CORE0_TRACE",
+    [98] = "CORE1_TRACE",
+    [99] = "HP_CORE",
+    [100] = "ISP",
+    [101] = "I3C",
+    [102] = "I3C_SLV",
+    [103] = "USB_OTG11",
+    [104] = "DMA2D_IN_CH0",
+    [105] = "DMA2D_IN_CH1",
+    [106] = "DMA2D_OUT_CH0",
+    [107] = "DMA2D_OUT_CH1",
+    [108] = "DMA2D_OUT_CH2",
+    [109] = "PSRAM_MSPI",
+    [110] = "HP_SYSREG",
+    [111] = "PCNT",
+    [112] = "HP_PAU",
+    [113] = "HP_PARLIO_RX",
+    [114] = "HP_PARLIO_TX",
+    [115] = "H264_DMA2D_OUT_CH0",
+    [116] = "H264_DMA2D_OUT_CH1",
+    [117] = "H264_DMA2D_OUT_CH2",
+    [118] = "H264_DMA2D_OUT_CH3",
+    [119] = "H264_DMA2D_OUT_CH4",
+    [120] = "H264_DMA2D_IN_CH0",
+    [121] = "H264_DMA2D_IN_CH1",
+    [122] = "H264_DMA2D_IN_CH2",
+    [123] = "H264_DMA2D_IN_CH3",
+    [124] = "H264_DMA2D_IN_CH4",
+    [125] = "H264_DMA2D_IN_CH5",
+    [126] = "H264_REG",
+    [127] = "ASSIST_DEBUG",
 };

From a9365b80492c471d34bc115525052098b36dd5bd Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Tue, 4 Jul 2023 14:31:09 +0800
Subject: [PATCH 11/13] feat(soc): rename rtc_timer_reg to lp_timer_reg

---
 .../soc/esp32p4/include/soc/lp_timer_reg.h    |   2 +-
 .../soc/esp32p4/include/soc/lp_timer_struct.h |   5 +-
 .../soc/esp32p4/include/soc/rtc_timer_reg.h   | 342 -----------------
 .../esp32p4/include/soc/rtc_timer_struct.h    | 362 ------------------
 4 files changed, 3 insertions(+), 708 deletions(-)
 delete mode 100644 components/soc/esp32p4/include/soc/rtc_timer_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/rtc_timer_struct.h

diff --git a/components/soc/esp32p4/include/soc/lp_timer_reg.h b/components/soc/esp32p4/include/soc/lp_timer_reg.h
index 46d19733a7..7628cbf7e0 100644
--- a/components/soc/esp32p4/include/soc/lp_timer_reg.h
+++ b/components/soc/esp32p4/include/soc/lp_timer_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/soc/esp32p4/include/soc/lp_timer_struct.h b/components/soc/esp32p4/include/soc/lp_timer_struct.h
index 4809c3d3b9..11c0aad66e 100644
--- a/components/soc/esp32p4/include/soc/lp_timer_struct.h
+++ b/components/soc/esp32p4/include/soc/lp_timer_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -329,7 +329,7 @@ typedef union {
 } lp_timer_date_reg_t;
 
 
-typedef struct lp_timer_dev_t {
+typedef struct {
     volatile lp_timer_tar0_low_reg_t tar0_low;
     volatile lp_timer_tar0_high_reg_t tar0_high;
     volatile lp_timer_tar1_low_reg_t tar1_low;
@@ -352,7 +352,6 @@ typedef struct lp_timer_dev_t {
     volatile lp_timer_date_reg_t date;
 } lp_timer_dev_t;
 
-extern lp_timer_dev_t LP_TIMER;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
diff --git a/components/soc/esp32p4/include/soc/rtc_timer_reg.h b/components/soc/esp32p4/include/soc/rtc_timer_reg.h
deleted file mode 100644
index 16fe3acfba..0000000000
--- a/components/soc/esp32p4/include/soc/rtc_timer_reg.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** RTC_TIMER_TAR0_LOW_REG register
- *  need_des
- */
-#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0)
-/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW0    0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M  (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S)
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V  0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S  0
-
-/** RTC_TIMER_TAR0_HIGH_REG register
- *  need_des
- */
-#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4)
-/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0    0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M  (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S)
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V  0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S  0
-/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_TAR_EN0    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M  (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S)
-#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S  31
-
-/** RTC_TIMER_TAR1_LOW_REG register
- *  need_des
- */
-#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8)
-/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW1    0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M  (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S)
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V  0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S  0
-
-/** RTC_TIMER_TAR1_HIGH_REG register
- *  need_des
- */
-#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc)
-/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1    0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M  (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S)
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V  0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S  0
-/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_TAR_EN1    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M  (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S)
-#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S  31
-
-/** RTC_TIMER_UPDATE_REG register
- *  need_des
- */
-#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10)
-/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_UPDATE    (BIT(28))
-#define RTC_TIMER_MAIN_TIMER_UPDATE_M  (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S)
-#define RTC_TIMER_MAIN_TIMER_UPDATE_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_UPDATE_S  28
-/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_XTAL_OFF    (BIT(29))
-#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M  (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S)
-#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S  29
-/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_SYS_STALL    (BIT(30))
-#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M  (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S)
-#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S  30
-/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_SYS_RST    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_SYS_RST_M  (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S)
-#define RTC_TIMER_MAIN_TIMER_SYS_RST_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_SYS_RST_S  31
-
-/** RTC_TIMER_MAIN_BUF0_LOW_REG register
- *  need_des
- */
-#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14)
-/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_BUF0_LOW    0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M  (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S)
-#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V  0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S  0
-
-/** RTC_TIMER_MAIN_BUF0_HIGH_REG register
- *  need_des
- */
-#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18)
-/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH    0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M  (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S)
-#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V  0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S  0
-
-/** RTC_TIMER_MAIN_BUF1_LOW_REG register
- *  need_des
- */
-#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c)
-/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_BUF1_LOW    0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M  (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S)
-#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V  0xFFFFFFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S  0
-
-/** RTC_TIMER_MAIN_BUF1_HIGH_REG register
- *  need_des
- */
-#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20)
-/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH    0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M  (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S)
-#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V  0x0000FFFFU
-#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S  0
-
-/** RTC_TIMER_MAIN_OVERFLOW_REG register
- *  need_des
- */
-#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24)
-/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M  (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S)
-#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S  31
-
-/** RTC_TIMER_INT_RAW_REG register
- *  need_des
- */
-#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28)
-/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_OVERFLOW_RAW    (BIT(30))
-#define RTC_TIMER_OVERFLOW_RAW_M  (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S)
-#define RTC_TIMER_OVERFLOW_RAW_V  0x00000001U
-#define RTC_TIMER_OVERFLOW_RAW_S  30
-/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_SOC_WAKEUP_INT_RAW    (BIT(31))
-#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M  (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S)
-#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V  0x00000001U
-#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S  31
-
-/** RTC_TIMER_INT_ST_REG register
- *  need_des
- */
-#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c)
-/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_OVERFLOW_ST    (BIT(30))
-#define RTC_TIMER_OVERFLOW_ST_M  (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S)
-#define RTC_TIMER_OVERFLOW_ST_V  0x00000001U
-#define RTC_TIMER_OVERFLOW_ST_S  30
-/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_SOC_WAKEUP_INT_ST    (BIT(31))
-#define RTC_TIMER_SOC_WAKEUP_INT_ST_M  (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S)
-#define RTC_TIMER_SOC_WAKEUP_INT_ST_V  0x00000001U
-#define RTC_TIMER_SOC_WAKEUP_INT_ST_S  31
-
-/** RTC_TIMER_INT_ENA_REG register
- *  need_des
- */
-#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30)
-/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_OVERFLOW_ENA    (BIT(30))
-#define RTC_TIMER_OVERFLOW_ENA_M  (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S)
-#define RTC_TIMER_OVERFLOW_ENA_V  0x00000001U
-#define RTC_TIMER_OVERFLOW_ENA_S  30
-/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_SOC_WAKEUP_INT_ENA    (BIT(31))
-#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M  (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S)
-#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V  0x00000001U
-#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S  31
-
-/** RTC_TIMER_INT_CLR_REG register
- *  need_des
- */
-#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34)
-/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_OVERFLOW_CLR    (BIT(30))
-#define RTC_TIMER_OVERFLOW_CLR_M  (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S)
-#define RTC_TIMER_OVERFLOW_CLR_V  0x00000001U
-#define RTC_TIMER_OVERFLOW_CLR_S  30
-/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_SOC_WAKEUP_INT_CLR    (BIT(31))
-#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M  (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S)
-#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V  0x00000001U
-#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S  31
-
-/** RTC_TIMER_LP_INT_RAW_REG register
- *  need_des
- */
-#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38)
-/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW    (BIT(30))
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S  30
-/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M  (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S)
-#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S  31
-
-/** RTC_TIMER_LP_INT_ST_REG register
- *  need_des
- */
-#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c)
-/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST    (BIT(30))
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S  30
-/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ST    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M  (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S)
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S  31
-
-/** RTC_TIMER_LP_INT_ENA_REG register
- *  need_des
- */
-#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40)
-/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA    (BIT(30))
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S  30
-/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M  (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S)
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S  31
-
-/** RTC_TIMER_LP_INT_CLR_REG register
- *  need_des
- */
-#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44)
-/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR    (BIT(30))
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S  30
-/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR    (BIT(31))
-#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M  (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S)
-#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V  0x00000001U
-#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S  31
-
-/** RTC_TIMER_DATE_REG register
- *  need_des
- */
-#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc)
-/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
- *  need_des
- */
-#define RTC_TIMER_DATE    0x7FFFFFFFU
-#define RTC_TIMER_DATE_M  (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S)
-#define RTC_TIMER_DATE_V  0x7FFFFFFFU
-#define RTC_TIMER_DATE_S  0
-/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define RTC_TIMER_CLK_EN    (BIT(31))
-#define RTC_TIMER_CLK_EN_M  (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S)
-#define RTC_TIMER_CLK_EN_V  0x00000001U
-#define RTC_TIMER_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/rtc_timer_struct.h b/components/soc/esp32p4/include/soc/rtc_timer_struct.h
deleted file mode 100644
index b20d4e0eb6..0000000000
--- a/components/soc/esp32p4/include/soc/rtc_timer_struct.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of tar0_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_low0:32;
-    };
-    uint32_t val;
-} rtc_timer_tar0_low_reg_t;
-
-/** Type of tar0_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_high0:16;
-        uint32_t reserved_16:15;
-        /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_en0:1;
-    };
-    uint32_t val;
-} rtc_timer_tar0_high_reg_t;
-
-/** Type of tar1_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_low1:32;
-    };
-    uint32_t val;
-} rtc_timer_tar1_low_reg_t;
-
-/** Type of tar1_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_high1:16;
-        uint32_t reserved_16:15;
-        /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_en1:1;
-    };
-    uint32_t val;
-} rtc_timer_tar1_high_reg_t;
-
-/** Type of update register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** main_timer_update : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_update:1;
-        /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_xtal_off:1;
-        /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_sys_stall:1;
-        /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_sys_rst:1;
-    };
-    uint32_t val;
-} rtc_timer_update_reg_t;
-
-/** Type of main_buf0_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf0_low:32;
-    };
-    uint32_t val;
-} rtc_timer_main_buf0_low_reg_t;
-
-/** Type of main_buf0_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf0_high:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} rtc_timer_main_buf0_high_reg_t;
-
-/** Type of main_buf1_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf1_low:32;
-    };
-    uint32_t val;
-} rtc_timer_main_buf1_low_reg_t;
-
-/** Type of main_buf1_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf1_high:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} rtc_timer_main_buf1_high_reg_t;
-
-/** Type of main_overflow register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_alarm_load:1;
-    };
-    uint32_t val;
-} rtc_timer_main_overflow_reg_t;
-
-/** Type of int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_raw:1;
-        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_raw:1;
-    };
-    uint32_t val;
-} rtc_timer_int_raw_reg_t;
-
-/** Type of int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_st:1;
-        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_st:1;
-    };
-    uint32_t val;
-} rtc_timer_int_st_reg_t;
-
-/** Type of int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_ena:1;
-        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_ena:1;
-    };
-    uint32_t val;
-} rtc_timer_int_ena_reg_t;
-
-/** Type of int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_clr:1;
-        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_clr:1;
-    };
-    uint32_t val;
-} rtc_timer_int_clr_reg_t;
-
-/** Type of lp_int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_raw:1;
-        /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_raw:1;
-    };
-    uint32_t val;
-} rtc_timer_lp_int_raw_reg_t;
-
-/** Type of lp_int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_st:1;
-        /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_st:1;
-    };
-    uint32_t val;
-} rtc_timer_lp_int_st_reg_t;
-
-/** Type of lp_int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_ena:1;
-        /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_ena:1;
-    };
-    uint32_t val;
-} rtc_timer_lp_int_ena_reg_t;
-
-/** Type of lp_int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_clr:1;
-        /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_clr:1;
-    };
-    uint32_t val;
-} rtc_timer_lp_int_clr_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [30:0]; default: 34672976;
-         *  need_des
-         */
-        uint32_t date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} rtc_timer_date_reg_t;
-
-
-typedef struct {
-    volatile rtc_timer_tar0_low_reg_t tar0_low;
-    volatile rtc_timer_tar0_high_reg_t tar0_high;
-    volatile rtc_timer_tar1_low_reg_t tar1_low;
-    volatile rtc_timer_tar1_high_reg_t tar1_high;
-    volatile rtc_timer_update_reg_t update;
-    volatile rtc_timer_main_buf0_low_reg_t main_buf0_low;
-    volatile rtc_timer_main_buf0_high_reg_t main_buf0_high;
-    volatile rtc_timer_main_buf1_low_reg_t main_buf1_low;
-    volatile rtc_timer_main_buf1_high_reg_t main_buf1_high;
-    volatile rtc_timer_main_overflow_reg_t main_overflow;
-    volatile rtc_timer_int_raw_reg_t int_raw;
-    volatile rtc_timer_int_st_reg_t int_st;
-    volatile rtc_timer_int_ena_reg_t int_ena;
-    volatile rtc_timer_int_clr_reg_t int_clr;
-    volatile rtc_timer_lp_int_raw_reg_t lp_int_raw;
-    volatile rtc_timer_lp_int_st_reg_t lp_int_st;
-    volatile rtc_timer_lp_int_ena_reg_t lp_int_ena;
-    volatile rtc_timer_lp_int_clr_reg_t lp_int_clr;
-    uint32_t reserved_048[237];
-    volatile rtc_timer_date_reg_t date;
-} rtc_timer_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(rtc_timer_dev_t) == 0x400, "Invalid size of rtc_timer_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif

From 1c3aedf45e95a2e308b2ea0ee882ddca9182e6db Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Thu, 6 Jul 2023 17:51:54 +0800
Subject: [PATCH 12/13] remove p4 rtc_io related files as requested

---
 .../soc/esp32p4/include/soc/rtc_io_channel.h  |  7 -------
 .../soc/esp32p4/include/soc/rtc_io_reg.h      |  9 ---------
 .../soc/esp32p4/include/soc/rtc_io_struct.h   | 19 -------------------
 components/soc/esp32p4/rtc_io_periph.c        | 11 -----------
 4 files changed, 46 deletions(-)
 delete mode 100644 components/soc/esp32p4/include/soc/rtc_io_channel.h
 delete mode 100644 components/soc/esp32p4/include/soc/rtc_io_reg.h
 delete mode 100644 components/soc/esp32p4/include/soc/rtc_io_struct.h
 delete mode 100644 components/soc/esp32p4/rtc_io_periph.c

diff --git a/components/soc/esp32p4/include/soc/rtc_io_channel.h b/components/soc/esp32p4/include/soc/rtc_io_channel.h
deleted file mode 100644
index d2aa55b41e..0000000000
--- a/components/soc/esp32p4/include/soc/rtc_io_channel.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
diff --git a/components/soc/esp32p4/include/soc/rtc_io_reg.h b/components/soc/esp32p4/include/soc/rtc_io_reg.h
deleted file mode 100644
index c053494821..0000000000
--- a/components/soc/esp32p4/include/soc/rtc_io_reg.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/lp_gpio_reg.h"
-#include "soc/lp_iomux_reg.h"
diff --git a/components/soc/esp32p4/include/soc/rtc_io_struct.h b/components/soc/esp32p4/include/soc/rtc_io_struct.h
deleted file mode 100644
index 5e314ff7d8..0000000000
--- a/components/soc/esp32p4/include/soc/rtc_io_struct.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/lp_gpio_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef lp_gpio_dev_t   rtc_io_dev_t;
-#define RTCIO           LP_GPIO
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/rtc_io_periph.c b/components/soc/esp32p4/rtc_io_periph.c
deleted file mode 100644
index c8273e3f5b..0000000000
--- a/components/soc/esp32p4/rtc_io_periph.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/rtc_periph.h"
-
-const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-
-};

From 93d4095fb0af80293d0210f91459f264bdeb3d8e Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Thu, 6 Jul 2023 18:57:41 +0800
Subject: [PATCH 13/13] feat(soc): added pmu_icg_mapping.h on p4

---
 .../soc/esp32p4/include/soc/pmu_icg_mapping.h | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
index f2c4877096..a4fa889f1f 100644
--- a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
+++ b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
@@ -3,3 +3,33 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
+#pragma once
+
+#define PMU_ICG_FUNC_CORE0_CPU_CLK_EN            0
+#define PMU_ICG_FUNC_CORE1_CPU_CLK_EN            1
+#define PMU_ICG_FUNC_CORE0_CLIC_CLK_EN           2
+#define PMU_ICG_FUNC_CORE1_CLIC_CLK_EN           3
+#define PMU_ICG_FUNC_MISC_CPU_CLK_EN             4
+#define PMU_ICG_FUNC_MISC_SYS_CLK_EN             5
+#define PMU_ICG_FUNC_ICM_SYS_CLK_EN              6
+#define PMU_ICG_FUNC_ICM_CPU_CLK_EN              7
+#define PMU_ICG_FUNC_ICM_MEM_CLK_EN              8
+#define PMU_ICG_FUNC_ICM_APB_CLK_EN              9
+#define PMU_ICG_FUNC_TCM_CPU_CLK_EN              10
+#define PMU_ICG_FUNC_L2MEM_MEM_CLK_EN            11
+#define PMU_ICG_FUNC_L2MEM_SYS_CLK_EN            12
+#define PMU_ICG_FUNC_L1CACHE_CPU_CLK_EN          13
+#define PMU_ICG_FUNC_LICACHE_D_CPU_CLK_EN        14
+#define PMU_ICG_FUNC_L1CACHE_I0_CPU_CLK_EN       15
+#define PMU_ICG_FUNC_L1CACHE_I1_CPU_CLK_EN       16
+#define PMU_ICG_FUNC_L1CACHE_MEM_CLK_EN          17
+#define PMU_ICG_FUNC_L1CACHE_D_MEM_CLK_EN        18
+#define PMU_ICG_FUNC_L1CACHE_I0_MEM_CLK_EN       19
+#define PMU_ICG_FUNC_L1CACHE_I1_MEM_CLK_EN       20
+#define PMU_ICG_FUNC_L2CACHE_MEM_CLK_EN          21
+#define PMU_ICG_FUNC_L2CACHE_SYS_CLK_EN          22
+#define PMU_ICG_FUNC_REGDMA_SYS_CLK_EN           23
+#define PMU_ICG_FUNC_HP_CLKRST_APB_CLK_EN        24
+#define PMU_ICG_FUNC_SYSREG_APB_CLK_EN           25
+#define PMU_ICG_FUNC_INTRMTX_APB_CLK_EN          26